projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: start splitting out common code from eg/r600.
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_double_list.h>
36 #include <util/u_pack_color.h>
37 #include <util/u_memory.h>
38 #include <util/u_inlines.h>
39 #include <util/u_upload_mgr.h>
40 #include <util/u_framebuffer.h>
41 #include <pipebuffer/pb_buffer.h>
42 #include "r600.h"
43 #include "r600d.h"
44 #include "r600_resource.h"
45 #include "r600_shader.h"
46 #include "r600_pipe.h"
47 #include "r600_state_inlines.h"
48
49 static void r600_draw_common(struct r600_drawl *draw)
50 {
51 struct r600_pipe_context *rctx = (struct r600_pipe_context *)draw->ctx;
52 struct r600_pipe_state *rstate;
53 struct r600_resource *rbuffer;
54 unsigned i, j, offset, prim;
55 u32 vgt_dma_index_type, vgt_draw_initiator, mask;
56 struct pipe_vertex_buffer *vertex_buffer;
57 struct r600_draw rdraw;
58 struct r600_pipe_state vgt;
59
60 switch (draw->index_size) {
61 case 2:
62 vgt_draw_initiator = 0;
63 vgt_dma_index_type = 0;
64 break;
65 case 4:
66 vgt_draw_initiator = 0;
67 vgt_dma_index_type = 1;
68 break;
69 case 0:
70 vgt_draw_initiator = 2;
71 vgt_dma_index_type = 0;
72 break;
73 default:
74 R600_ERR("unsupported index size %d\n", draw->index_size);
75 return;
76 }
77 if (r600_conv_pipe_prim(draw->mode, &prim))
78 return;
79
80
81 /* rebuild vertex shader if input format changed */
82 if (r600_pipe_shader_update(&rctx->context, rctx->vs_shader))
83 return;
84 if (r600_pipe_shader_update(&rctx->context, rctx->ps_shader))
85 return;
86
87 for (i = 0 ; i < rctx->vertex_elements->count; i++) {
88 uint32_t word2, format;
89
90 rstate = &rctx->vs_resource[i];
91 rstate->id = R600_PIPE_STATE_RESOURCE;
92 rstate->nregs = 0;
93
94 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
95 vertex_buffer = &rctx->vertex_buffer[j];
96 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
97 offset = rctx->vertex_elements->elements[i].src_offset +
98 vertex_buffer->buffer_offset +
99 r600_bo_offset(rbuffer->bo);
100
101 format = r600_translate_vertex_data_type(rctx->vertex_elements->hw_format[i]);
102
103 word2 = format | S_038008_STRIDE(vertex_buffer->stride);
104
105 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
106 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
107 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2, word2, 0xFFFFFFFF, NULL);
108 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3, 0x00000000, 0xFFFFFFFF, NULL);
109 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
110 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
111 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6, 0xC0000000, 0xFFFFFFFF, NULL);
112 r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, i);
113 }
114
115 mask = 0;
116 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
117 mask |= (0xF << (i * 4));
118 }
119
120 vgt.id = R600_PIPE_STATE_VGT;
121 vgt.nregs = 0;
122 r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
123 r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw->index_bias, 0xFFFFFFFF, NULL);
124 r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw->max_index, 0xFFFFFFFF, NULL);
125 r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw->min_index, 0xFFFFFFFF, NULL);
126 r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
127 r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
128 r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
129 /* build late state */
130 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
131 float offset_units = rctx->rasterizer->offset_units;
132 unsigned offset_db_fmt_cntl = 0, depth;
133
134 switch (rctx->framebuffer.zsbuf->texture->format) {
135 case PIPE_FORMAT_Z24X8_UNORM:
136 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
137 depth = -24;
138 offset_units *= 2.0f;
139 break;
140 case PIPE_FORMAT_Z32_FLOAT:
141 depth = -23;
142 offset_units *= 1.0f;
143 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
144 break;
145 case PIPE_FORMAT_Z16_UNORM:
146 depth = -16;
147 offset_units *= 4.0f;
148 break;
149 default:
150 return;
151 }
152 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
153 r600_pipe_state_add_reg(&vgt,
154 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
155 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
156 r600_pipe_state_add_reg(&vgt,
157 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
158 fui(offset_units), 0xFFFFFFFF, NULL);
159 r600_pipe_state_add_reg(&vgt,
160 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
161 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
162 r600_pipe_state_add_reg(&vgt,
163 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
164 fui(offset_units), 0xFFFFFFFF, NULL);
165 r600_pipe_state_add_reg(&vgt,
166 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
167 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
168 }
169 r600_context_pipe_state_set(&rctx->ctx, &vgt);
170
171 rdraw.vgt_num_indices = draw->count;
172 rdraw.vgt_num_instances = 1;
173 rdraw.vgt_index_type = vgt_dma_index_type;
174 rdraw.vgt_draw_initiator = vgt_draw_initiator;
175 rdraw.indices = NULL;
176 if (draw->index_buffer) {
177 rbuffer = (struct r600_resource*)draw->index_buffer;
178 rdraw.indices = rbuffer->bo;
179 rdraw.indices_bo_offset = draw->index_buffer_offset;
180 }
181 r600_context_draw(&rctx->ctx, &rdraw);
182 }
183
184 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
185 {
186 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
187 struct r600_drawl draw;
188 boolean translate = FALSE;
189
190 if (rctx->vertex_elements->incompatible_layout) {
191 r600_begin_vertex_translate(rctx);
192 translate = TRUE;
193 }
194
195 if (rctx->any_user_vbs) {
196 r600_upload_user_buffers(rctx);
197 rctx->any_user_vbs = FALSE;
198 }
199 memset(&draw, 0, sizeof(struct r600_drawl));
200 draw.ctx = ctx;
201 draw.mode = info->mode;
202 draw.start = info->start;
203 draw.count = info->count;
204 if (info->indexed && rctx->index_buffer.buffer) {
205 draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
206 draw.min_index = info->min_index;
207 draw.max_index = info->max_index;
208 draw.index_bias = info->index_bias;
209
210 r600_translate_index_buffer(rctx, &rctx->index_buffer.buffer,
211 &rctx->index_buffer.index_size,
212 &draw.start,
213 info->count);
214
215 draw.index_size = rctx->index_buffer.index_size;
216 pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
217 draw.index_buffer_offset = draw.start * draw.index_size;
218 draw.start = 0;
219 r600_upload_index_buffer(rctx, &draw);
220 } else {
221 draw.index_size = 0;
222 draw.index_buffer = NULL;
223 draw.min_index = info->min_index;
224 draw.max_index = info->max_index;
225 draw.index_bias = info->start;
226 }
227 r600_draw_common(&draw);
228
229 if (translate)
230 r600_end_vertex_translate(rctx);
231
232 pipe_resource_reference(&draw.index_buffer, NULL);
233 }
234
235 static void r600_set_blend_color(struct pipe_context *ctx,
236 const struct pipe_blend_color *state)
237 {
238 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
239 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
240
241 if (rstate == NULL)
242 return;
243
244 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
245 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
246 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
247 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
248 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
249 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
250 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
251 r600_context_pipe_state_set(&rctx->ctx, rstate);
252 }
253
254 static void *r600_create_blend_state(struct pipe_context *ctx,
255 const struct pipe_blend_state *state)
256 {
257 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
258 struct r600_pipe_state *rstate;
259 u32 color_control, target_mask;
260
261 if (blend == NULL) {
262 return NULL;
263 }
264 rstate = &blend->rstate;
265
266 rstate->id = R600_PIPE_STATE_BLEND;
267
268 target_mask = 0;
269 color_control = S_028808_PER_MRT_BLEND(1);
270 if (state->logicop_enable) {
271 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
272 } else {
273 color_control |= (0xcc << 16);
274 }
275 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
276 if (state->independent_blend_enable) {
277 for (int i = 0; i < 8; i++) {
278 if (state->rt[i].blend_enable) {
279 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
280 }
281 target_mask |= (state->rt[i].colormask << (4 * i));
282 }
283 } else {
284 for (int i = 0; i < 8; i++) {
285 if (state->rt[0].blend_enable) {
286 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
287 }
288 target_mask |= (state->rt[0].colormask << (4 * i));
289 }
290 }
291 blend->cb_target_mask = target_mask;
292 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
293 color_control, 0xFFFFFFFF, NULL);
294
295 for (int i = 0; i < 8; i++) {
296 unsigned eqRGB = state->rt[i].rgb_func;
297 unsigned srcRGB = state->rt[i].rgb_src_factor;
298 unsigned dstRGB = state->rt[i].rgb_dst_factor;
299
300 unsigned eqA = state->rt[i].alpha_func;
301 unsigned srcA = state->rt[i].alpha_src_factor;
302 unsigned dstA = state->rt[i].alpha_dst_factor;
303 uint32_t bc = 0;
304
305 if (!state->rt[i].blend_enable)
306 continue;
307
308 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
309 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
310 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
311
312 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
313 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
314 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
315 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
316 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
317 }
318
319 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
320 if (i == 0) {
321 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
322 }
323 }
324 return rstate;
325 }
326
327 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
328 {
329 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
330 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
331 struct r600_pipe_state *rstate;
332
333 if (state == NULL)
334 return;
335 rstate = &blend->rstate;
336 rctx->states[rstate->id] = rstate;
337 rctx->cb_target_mask = blend->cb_target_mask;
338 r600_context_pipe_state_set(&rctx->ctx, rstate);
339 }
340
341 static void *r600_create_dsa_state(struct pipe_context *ctx,
342 const struct pipe_depth_stencil_alpha_state *state)
343 {
344 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
345 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
346 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
347
348 if (rstate == NULL) {
349 return NULL;
350 }
351
352 rstate->id = R600_PIPE_STATE_DSA;
353 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
354 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
355 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
356 * be set if shader use texkill instruction
357 */
358 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
359 stencil_ref_mask = 0;
360 stencil_ref_mask_bf = 0;
361 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
362 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
363 S_028800_ZFUNC(state->depth.func);
364
365 /* stencil */
366 if (state->stencil[0].enabled) {
367 db_depth_control |= S_028800_STENCIL_ENABLE(1);
368 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
369 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
370 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
371 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
372
373
374 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
375 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
376 if (state->stencil[1].enabled) {
377 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
378 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
379 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
380 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
381 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
382 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
383 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
384 }
385 }
386
387 /* alpha */
388 alpha_test_control = 0;
389 alpha_ref = 0;
390 if (state->alpha.enabled) {
391 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
392 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
393 alpha_ref = fui(state->alpha.ref_value);
394 }
395
396 /* misc */
397 db_render_control = 0;
398 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
399 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
400 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
401 /* TODO db_render_override depends on query */
402 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
403 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
404 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
405 r600_pipe_state_add_reg(rstate,
406 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
407 0xFFFFFFFF & C_028430_STENCILREF, NULL);
408 r600_pipe_state_add_reg(rstate,
409 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
410 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
411 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
412 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
413 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
414 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
415 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
416 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
417 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
418 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
419 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
420 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
421 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
422
423 return rstate;
424 }
425
426 static void *r600_create_rs_state(struct pipe_context *ctx,
427 const struct pipe_rasterizer_state *state)
428 {
429 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
430 struct r600_pipe_state *rstate;
431 unsigned tmp;
432 unsigned prov_vtx = 1, polygon_dual_mode;
433 unsigned clip_rule;
434
435 if (rs == NULL) {
436 return NULL;
437 }
438
439 rstate = &rs->rstate;
440 rs->flatshade = state->flatshade;
441 rs->sprite_coord_enable = state->sprite_coord_enable;
442
443 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
444 /* offset */
445 rs->offset_units = state->offset_units;
446 rs->offset_scale = state->offset_scale * 12.0f;
447
448 rstate->id = R600_PIPE_STATE_RASTERIZER;
449 if (state->flatshade_first)
450 prov_vtx = 0;
451 tmp = 0x00000001;
452 if (state->sprite_coord_enable) {
453 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
454 S_0286D4_PNT_SPRITE_OVRD_X(2) |
455 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
456 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
457 S_0286D4_PNT_SPRITE_OVRD_W(1);
458 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
459 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
460 }
461 }
462 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
463
464 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
465 state->fill_back != PIPE_POLYGON_MODE_FILL);
466 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
467 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
468 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
469 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
470 S_028814_FACE(!state->front_ccw) |
471 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
472 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
473 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
474 S_028814_POLY_MODE(polygon_dual_mode) |
475 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
476 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
477 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
478 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
479 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
480 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
481 /* point size 12.4 fixed point */
482 tmp = (unsigned)(state->point_size * 8.0);
483 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
484 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
485
486 tmp = (unsigned)(state->line_width * 8.0);
487 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
488
489 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
490 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
491 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
492 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
493 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
494 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
495 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
496 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
497 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
498
499 return rstate;
500 }
501
502 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
503 {
504 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
505 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
506
507 if (state == NULL)
508 return;
509
510 rctx->flatshade = rs->flatshade;
511 rctx->sprite_coord_enable = rs->sprite_coord_enable;
512 rctx->rasterizer = rs;
513
514 rctx->states[rs->rstate.id] = &rs->rstate;
515 r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
516 }
517
518 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
519 {
520 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
521 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
522
523 if (rctx->rasterizer == rs) {
524 rctx->rasterizer = NULL;
525 }
526 if (rctx->states[rs->rstate.id] == &rs->rstate) {
527 rctx->states[rs->rstate.id] = NULL;
528 }
529 free(rs);
530 }
531
532 static void *r600_create_sampler_state(struct pipe_context *ctx,
533 const struct pipe_sampler_state *state)
534 {
535 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
536 union util_color uc;
537
538 if (rstate == NULL) {
539 return NULL;
540 }
541
542 rstate->id = R600_PIPE_STATE_SAMPLER;
543 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
544 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
545 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
546 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
547 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
548 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
549 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
550 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
551 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
552 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
553 /* FIXME LOD it depends on texture base level ... */
554 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
555 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
556 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
557 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
558 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
559 if (uc.ui) {
560 r600_pipe_state_add_reg(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
561 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
562 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
563 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
564 }
565 return rstate;
566 }
567
568
569 static void r600_sampler_view_destroy(struct pipe_context *ctx,
570 struct pipe_sampler_view *state)
571 {
572 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
573
574 pipe_resource_reference(&state->texture, NULL);
575 FREE(resource);
576 }
577
578 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
579 struct pipe_resource *texture,
580 const struct pipe_sampler_view *state)
581 {
582 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
583 struct r600_pipe_state *rstate;
584 const struct util_format_description *desc;
585 struct r600_resource_texture *tmp;
586 struct r600_resource *rbuffer;
587 unsigned format;
588 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
589 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
590 struct r600_bo *bo[2];
591
592 if (resource == NULL)
593 return NULL;
594 rstate = &resource->state;
595
596 /* initialize base object */
597 resource->base = *state;
598 resource->base.texture = NULL;
599 pipe_reference(NULL, &texture->reference);
600 resource->base.texture = texture;
601 resource->base.reference.count = 1;
602 resource->base.context = ctx;
603
604 swizzle[0] = state->swizzle_r;
605 swizzle[1] = state->swizzle_g;
606 swizzle[2] = state->swizzle_b;
607 swizzle[3] = state->swizzle_a;
608 format = r600_translate_texformat(state->format,
609 swizzle,
610 &word4, &yuv_format);
611 if (format == ~0) {
612 format = 0;
613 }
614 desc = util_format_description(state->format);
615 if (desc == NULL) {
616 R600_ERR("unknow format %d\n", state->format);
617 }
618 tmp = (struct r600_resource_texture*)texture;
619 rbuffer = &tmp->resource;
620 bo[0] = rbuffer->bo;
621 bo[1] = rbuffer->bo;
622 /* FIXME depth texture decompression */
623 if (tmp->depth) {
624 r600_texture_depth_flush(ctx, texture);
625 tmp = (struct r600_resource_texture*)texture;
626 rbuffer = &tmp->flushed_depth_texture->resource;
627 bo[0] = rbuffer->bo;
628 bo[1] = rbuffer->bo;
629 }
630 pitch = align(tmp->pitch_in_pixels[0], 8);
631 if (tmp->tiled) {
632 array_mode = tmp->array_mode[0];
633 tile_type = tmp->tile_type;
634 }
635
636 /* FIXME properly handle first level != 0 */
637 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
638 S_038000_DIM(r600_tex_dim(texture->target)) |
639 S_038000_TILE_MODE(array_mode) |
640 S_038000_TILE_TYPE(tile_type) |
641 S_038000_PITCH((pitch / 8) - 1) |
642 S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
643 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
644 S_038004_TEX_HEIGHT(texture->height0 - 1) |
645 S_038004_TEX_DEPTH(texture->depth0 - 1) |
646 S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
647 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
648 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
649 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
650 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
651 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
652 word4 | S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
653 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
654 S_038010_REQUEST_SIZE(1) |
655 S_038010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
656 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
657 S_038014_LAST_LEVEL(state->last_level) |
658 S_038014_BASE_ARRAY(0) |
659 S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL);
660 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
661 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
662
663 return &resource->base;
664 }
665
666 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
667 struct pipe_sampler_view **views)
668 {
669 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
670 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
671
672 for (int i = 0; i < count; i++) {
673 if (resource[i]) {
674 r600_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, i + PIPE_MAX_ATTRIBS);
675 }
676 }
677 }
678
679 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
680 struct pipe_sampler_view **views)
681 {
682 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
683 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
684 int i;
685
686 for (i = 0; i < count; i++) {
687 if (&rctx->ps_samplers.views[i]->base != views[i]) {
688 if (resource[i])
689 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
690 else
691 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
692
693 pipe_sampler_view_reference(
694 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
695 views[i]);
696
697 }
698 }
699 for (i = count; i < NUM_TEX_UNITS; i++) {
700 if (rctx->ps_samplers.views[i]) {
701 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
702 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
703 }
704 }
705 rctx->ps_samplers.n_views = count;
706 }
707
708 static void r600_bind_state(struct pipe_context *ctx, void *state)
709 {
710 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
711 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
712
713 if (state == NULL)
714 return;
715 rctx->states[rstate->id] = rstate;
716 r600_context_pipe_state_set(&rctx->ctx, rstate);
717 }
718
719 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
720 {
721 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
722 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
723
724 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
725 rctx->ps_samplers.n_samplers = count;
726
727 for (int i = 0; i < count; i++) {
728 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
729 }
730 }
731
732 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
733 {
734 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
735 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
736
737 for (int i = 0; i < count; i++) {
738 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
739 }
740 }
741
742 static void r600_delete_state(struct pipe_context *ctx, void *state)
743 {
744 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
745 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
746
747 if (rctx->states[rstate->id] == rstate) {
748 rctx->states[rstate->id] = NULL;
749 }
750 for (int i = 0; i < rstate->nregs; i++) {
751 r600_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
752 }
753 free(rstate);
754 }
755
756 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
757 {
758 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
759
760 if (v == NULL)
761 return;
762 if (--v->refcount)
763 return;
764 free(v);
765 }
766
767 static void r600_set_clip_state(struct pipe_context *ctx,
768 const struct pipe_clip_state *state)
769 {
770 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
771 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
772
773 if (rstate == NULL)
774 return;
775
776 rctx->clip = *state;
777 rstate->id = R600_PIPE_STATE_CLIP;
778 for (int i = 0; i < state->nr; i++) {
779 r600_pipe_state_add_reg(rstate,
780 R_028E20_PA_CL_UCP0_X + i * 4,
781 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
782 r600_pipe_state_add_reg(rstate,
783 R_028E24_PA_CL_UCP0_Y + i * 4,
784 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
785 r600_pipe_state_add_reg(rstate,
786 R_028E28_PA_CL_UCP0_Z + i * 4,
787 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
788 r600_pipe_state_add_reg(rstate,
789 R_028E2C_PA_CL_UCP0_W + i * 4,
790 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
791 }
792 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
793 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
794 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
795 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
796
797 free(rctx->states[R600_PIPE_STATE_CLIP]);
798 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
799 r600_context_pipe_state_set(&rctx->ctx, rstate);
800 }
801
802 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
803 {
804 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
805 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
806
807 r600_delete_vertex_element(ctx, rctx->vertex_elements);
808 rctx->vertex_elements = v;
809 if (v) {
810 v->refcount++;
811 // rctx->vs_rebuild = TRUE;
812 }
813 }
814
815 static void r600_set_polygon_stipple(struct pipe_context *ctx,
816 const struct pipe_poly_stipple *state)
817 {
818 }
819
820 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
821 {
822 }
823
824 static void r600_set_scissor_state(struct pipe_context *ctx,
825 const struct pipe_scissor_state *state)
826 {
827 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
828 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
829 u32 tl, br;
830
831 if (rstate == NULL)
832 return;
833
834 rstate->id = R600_PIPE_STATE_SCISSOR;
835 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
836 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
837 r600_pipe_state_add_reg(rstate,
838 R_028210_PA_SC_CLIPRECT_0_TL, tl,
839 0xFFFFFFFF, NULL);
840 r600_pipe_state_add_reg(rstate,
841 R_028214_PA_SC_CLIPRECT_0_BR, br,
842 0xFFFFFFFF, NULL);
843 r600_pipe_state_add_reg(rstate,
844 R_028218_PA_SC_CLIPRECT_1_TL, tl,
845 0xFFFFFFFF, NULL);
846 r600_pipe_state_add_reg(rstate,
847 R_02821C_PA_SC_CLIPRECT_1_BR, br,
848 0xFFFFFFFF, NULL);
849 r600_pipe_state_add_reg(rstate,
850 R_028220_PA_SC_CLIPRECT_2_TL, tl,
851 0xFFFFFFFF, NULL);
852 r600_pipe_state_add_reg(rstate,
853 R_028224_PA_SC_CLIPRECT_2_BR, br,
854 0xFFFFFFFF, NULL);
855 r600_pipe_state_add_reg(rstate,
856 R_028228_PA_SC_CLIPRECT_3_TL, tl,
857 0xFFFFFFFF, NULL);
858 r600_pipe_state_add_reg(rstate,
859 R_02822C_PA_SC_CLIPRECT_3_BR, br,
860 0xFFFFFFFF, NULL);
861
862 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
863 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
864 r600_context_pipe_state_set(&rctx->ctx, rstate);
865 }
866
867 static void r600_set_stencil_ref(struct pipe_context *ctx,
868 const struct pipe_stencil_ref *state)
869 {
870 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
871 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
872 u32 tmp;
873
874 if (rstate == NULL)
875 return;
876
877 rctx->stencil_ref = *state;
878 rstate->id = R600_PIPE_STATE_STENCIL_REF;
879 tmp = S_028430_STENCILREF(state->ref_value[0]);
880 r600_pipe_state_add_reg(rstate,
881 R_028430_DB_STENCILREFMASK, tmp,
882 ~C_028430_STENCILREF, NULL);
883 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
884 r600_pipe_state_add_reg(rstate,
885 R_028434_DB_STENCILREFMASK_BF, tmp,
886 ~C_028434_STENCILREF_BF, NULL);
887
888 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
889 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
890 r600_context_pipe_state_set(&rctx->ctx, rstate);
891 }
892
893 static void r600_set_viewport_state(struct pipe_context *ctx,
894 const struct pipe_viewport_state *state)
895 {
896 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
897 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
898
899 if (rstate == NULL)
900 return;
901
902 rctx->viewport = *state;
903 rstate->id = R600_PIPE_STATE_VIEWPORT;
904 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
905 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
906 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
907 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
908 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
909 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
910 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
911 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
912 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
913
914 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
915 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
916 r600_context_pipe_state_set(&rctx->ctx, rstate);
917 }
918
919 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
920 const struct pipe_framebuffer_state *state, int cb)
921 {
922 struct r600_resource_texture *rtex;
923 struct r600_resource *rbuffer;
924 struct r600_surface *surf;
925 unsigned level = state->cbufs[cb]->level;
926 unsigned pitch, slice;
927 unsigned color_info;
928 unsigned format, swap, ntype;
929 const struct util_format_description *desc;
930 struct r600_bo *bo[3];
931
932 surf = (struct r600_surface *)state->cbufs[cb];
933 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
934 rbuffer = &rtex->resource;
935 bo[0] = rbuffer->bo;
936 bo[1] = rbuffer->bo;
937 bo[2] = rbuffer->bo;
938
939 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
940 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
941 ntype = 0;
942 desc = util_format_description(rtex->resource.base.b.format);
943 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
944 ntype = V_0280A0_NUMBER_SRGB;
945
946 format = r600_translate_colorformat(rtex->resource.base.b.format);
947 swap = r600_translate_colorswap(rtex->resource.base.b.format);
948 color_info = S_0280A0_FORMAT(format) |
949 S_0280A0_COMP_SWAP(swap) |
950 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
951 S_0280A0_BLEND_CLAMP(1) |
952 S_0280A0_NUMBER_TYPE(ntype);
953 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
954 color_info |= S_0280A0_SOURCE_FORMAT(1);
955
956 r600_pipe_state_add_reg(rstate,
957 R_028040_CB_COLOR0_BASE + cb * 4,
958 (state->cbufs[cb]->offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
959 r600_pipe_state_add_reg(rstate,
960 R_0280A0_CB_COLOR0_INFO + cb * 4,
961 color_info, 0xFFFFFFFF, bo[0]);
962 r600_pipe_state_add_reg(rstate,
963 R_028060_CB_COLOR0_SIZE + cb * 4,
964 S_028060_PITCH_TILE_MAX(pitch) |
965 S_028060_SLICE_TILE_MAX(slice),
966 0xFFFFFFFF, NULL);
967 r600_pipe_state_add_reg(rstate,
968 R_028080_CB_COLOR0_VIEW + cb * 4,
969 0x00000000, 0xFFFFFFFF, NULL);
970 r600_pipe_state_add_reg(rstate,
971 R_0280E0_CB_COLOR0_FRAG + cb * 4,
972 r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]);
973 r600_pipe_state_add_reg(rstate,
974 R_0280C0_CB_COLOR0_TILE + cb * 4,
975 r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]);
976 r600_pipe_state_add_reg(rstate,
977 R_028100_CB_COLOR0_MASK + cb * 4,
978 0x00000000, 0xFFFFFFFF, NULL);
979 }
980
981 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
982 const struct pipe_framebuffer_state *state)
983 {
984 struct r600_resource_texture *rtex;
985 struct r600_resource *rbuffer;
986 struct r600_surface *surf;
987 unsigned level;
988 unsigned pitch, slice, format;
989
990 if (state->zsbuf == NULL)
991 return;
992
993 level = state->zsbuf->level;
994
995 surf = (struct r600_surface *)state->zsbuf;
996 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
997 rtex->tiled = 1;
998 rtex->array_mode[level] = 2;
999 rtex->tile_type = 1;
1000 rtex->depth = 1;
1001 rbuffer = &rtex->resource;
1002
1003 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
1004 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
1005 format = r600_translate_dbformat(state->zsbuf->texture->format);
1006
1007 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
1008 (state->zsbuf->offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
1009 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1010 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1011 0xFFFFFFFF, NULL);
1012 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
1013 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
1014 S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format),
1015 0xFFFFFFFF, rbuffer->bo);
1016 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1017 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL);
1018 }
1019
1020 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1021 const struct pipe_framebuffer_state *state)
1022 {
1023 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1024 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1025 u32 shader_mask, tl, br, shader_control, target_mask;
1026
1027 if (rstate == NULL)
1028 return;
1029
1030 /* unreference old buffer and reference new one */
1031 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1032
1033 util_copy_framebuffer_state(&rctx->framebuffer, state);
1034
1035 rctx->pframebuffer = &rctx->framebuffer;
1036
1037 /* build states */
1038 for (int i = 0; i < state->nr_cbufs; i++) {
1039 r600_cb(rctx, rstate, state, i);
1040 }
1041 if (state->zsbuf) {
1042 r600_db(rctx, rstate, state);
1043 }
1044
1045 target_mask = 0x00000000;
1046 target_mask = 0xFFFFFFFF;
1047 shader_mask = 0;
1048 shader_control = 0;
1049 for (int i = 0; i < state->nr_cbufs; i++) {
1050 target_mask ^= 0xf << (i * 4);
1051 shader_mask |= 0xf << (i * 4);
1052 shader_control |= 1 << i;
1053 }
1054 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1055 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1056
1057 r600_pipe_state_add_reg(rstate,
1058 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1059 0xFFFFFFFF, NULL);
1060 r600_pipe_state_add_reg(rstate,
1061 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1062 0xFFFFFFFF, NULL);
1063 r600_pipe_state_add_reg(rstate,
1064 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1065 0xFFFFFFFF, NULL);
1066 r600_pipe_state_add_reg(rstate,
1067 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1068 0xFFFFFFFF, NULL);
1069 r600_pipe_state_add_reg(rstate,
1070 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1071 0xFFFFFFFF, NULL);
1072 r600_pipe_state_add_reg(rstate,
1073 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1074 0xFFFFFFFF, NULL);
1075 r600_pipe_state_add_reg(rstate,
1076 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1077 0xFFFFFFFF, NULL);
1078 r600_pipe_state_add_reg(rstate,
1079 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1080 0xFFFFFFFF, NULL);
1081 r600_pipe_state_add_reg(rstate,
1082 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1083 0xFFFFFFFF, NULL);
1084 if (rctx->family >= CHIP_RV770) {
1085 r600_pipe_state_add_reg(rstate,
1086 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1087 0xFFFFFFFF, NULL);
1088 }
1089
1090 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1091 shader_control, 0xFFFFFFFF, NULL);
1092 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1093 0x00000000, target_mask, NULL);
1094 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1095 shader_mask, 0xFFFFFFFF, NULL);
1096 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1097 0x00000000, 0xFFFFFFFF, NULL);
1098 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1099 0x00000000, 0xFFFFFFFF, NULL);
1100 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1101 0x00000000, 0xFFFFFFFF, NULL);
1102 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1103 0x01000000, 0xFFFFFFFF, NULL);
1104 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1105 0x00000000, 0xFFFFFFFF, NULL);
1106 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1107 0x000000FF, 0xFFFFFFFF, NULL);
1108 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1109 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1110 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1111 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1112
1113 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1114 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1115 r600_context_pipe_state_set(&rctx->ctx, rstate);
1116 }
1117
1118 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
1119 struct pipe_resource *buffer)
1120 {
1121 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1122 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
1123
1124 switch (shader) {
1125 case PIPE_SHADER_VERTEX:
1126 rctx->vs_const_buffer.nregs = 0;
1127 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1128 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1129 ALIGN_DIVUP(buffer->width0 >> 4, 16),
1130 0xFFFFFFFF, NULL);
1131 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1132 R_028980_ALU_CONST_CACHE_VS_0,
1133 r600_bo_offset(rbuffer->bo) >> 8, 0xFFFFFFFF, rbuffer->bo);
1134 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
1135 break;
1136 case PIPE_SHADER_FRAGMENT:
1137 rctx->ps_const_buffer.nregs = 0;
1138 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1139 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1140 ALIGN_DIVUP(buffer->width0 >> 4, 16),
1141 0xFFFFFFFF, NULL);
1142 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1143 R_028940_ALU_CONST_CACHE_PS_0,
1144 r600_bo_offset(rbuffer->bo) >> 8, 0xFFFFFFFF, rbuffer->bo);
1145 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
1146 break;
1147 default:
1148 R600_ERR("unsupported %d\n", shader);
1149 return;
1150 }
1151 }
1152
1153 static void *r600_create_shader_state(struct pipe_context *ctx,
1154 const struct pipe_shader_state *state)
1155 {
1156 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
1157 int r;
1158
1159 r = r600_pipe_shader_create(ctx, shader, state->tokens);
1160 if (r) {
1161 return NULL;
1162 }
1163 return shader;
1164 }
1165
1166 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
1167 {
1168 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1169
1170 /* TODO delete old shader */
1171 rctx->ps_shader = (struct r600_pipe_shader *)state;
1172 }
1173
1174 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
1175 {
1176 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1177
1178 /* TODO delete old shader */
1179 rctx->vs_shader = (struct r600_pipe_shader *)state;
1180 }
1181
1182 static void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
1183 {
1184 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1185 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1186
1187 if (rctx->ps_shader == shader) {
1188 rctx->ps_shader = NULL;
1189 }
1190 /* TODO proper delete */
1191 free(shader);
1192 }
1193
1194 static void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
1195 {
1196 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1197 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1198
1199 if (rctx->vs_shader == shader) {
1200 rctx->vs_shader = NULL;
1201 }
1202 /* TODO proper delete */
1203 free(shader);
1204 }
1205
1206 void r600_init_state_functions(struct r600_pipe_context *rctx)
1207 {
1208 rctx->context.create_blend_state = r600_create_blend_state;
1209 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1210 rctx->context.create_fs_state = r600_create_shader_state;
1211 rctx->context.create_rasterizer_state = r600_create_rs_state;
1212 rctx->context.create_sampler_state = r600_create_sampler_state;
1213 rctx->context.create_sampler_view = r600_create_sampler_view;
1214 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1215 rctx->context.create_vs_state = r600_create_shader_state;
1216 rctx->context.bind_blend_state = r600_bind_blend_state;
1217 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
1218 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
1219 rctx->context.bind_fs_state = r600_bind_ps_shader;
1220 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1221 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1222 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
1223 rctx->context.bind_vs_state = r600_bind_vs_shader;
1224 rctx->context.delete_blend_state = r600_delete_state;
1225 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1226 rctx->context.delete_fs_state = r600_delete_ps_shader;
1227 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1228 rctx->context.delete_sampler_state = r600_delete_state;
1229 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1230 rctx->context.delete_vs_state = r600_delete_vs_shader;
1231 rctx->context.set_blend_color = r600_set_blend_color;
1232 rctx->context.set_clip_state = r600_set_clip_state;
1233 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1234 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
1235 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1236 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1237 rctx->context.set_sample_mask = r600_set_sample_mask;
1238 rctx->context.set_scissor_state = r600_set_scissor_state;
1239 rctx->context.set_stencil_ref = r600_set_stencil_ref;
1240 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1241 rctx->context.set_index_buffer = r600_set_index_buffer;
1242 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
1243 rctx->context.set_viewport_state = r600_set_viewport_state;
1244 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1245 }
1246
1247 void r600_init_config(struct r600_pipe_context *rctx)
1248 {
1249 int ps_prio;
1250 int vs_prio;
1251 int gs_prio;
1252 int es_prio;
1253 int num_ps_gprs;
1254 int num_vs_gprs;
1255 int num_gs_gprs;
1256 int num_es_gprs;
1257 int num_temp_gprs;
1258 int num_ps_threads;
1259 int num_vs_threads;
1260 int num_gs_threads;
1261 int num_es_threads;
1262 int num_ps_stack_entries;
1263 int num_vs_stack_entries;
1264 int num_gs_stack_entries;
1265 int num_es_stack_entries;
1266 enum radeon_family family;
1267 struct r600_pipe_state *rstate = &rctx->config;
1268 u32 tmp;
1269
1270 family = r600_get_family(rctx->radeon);
1271 ps_prio = 0;
1272 vs_prio = 1;
1273 gs_prio = 2;
1274 es_prio = 3;
1275 switch (family) {
1276 case CHIP_R600:
1277 num_ps_gprs = 192;
1278 num_vs_gprs = 56;
1279 num_temp_gprs = 4;
1280 num_gs_gprs = 0;
1281 num_es_gprs = 0;
1282 num_ps_threads = 136;
1283 num_vs_threads = 48;
1284 num_gs_threads = 4;
1285 num_es_threads = 4;
1286 num_ps_stack_entries = 128;
1287 num_vs_stack_entries = 128;
1288 num_gs_stack_entries = 0;
1289 num_es_stack_entries = 0;
1290 break;
1291 case CHIP_RV630:
1292 case CHIP_RV635:
1293 num_ps_gprs = 84;
1294 num_vs_gprs = 36;
1295 num_temp_gprs = 4;
1296 num_gs_gprs = 0;
1297 num_es_gprs = 0;
1298 num_ps_threads = 144;
1299 num_vs_threads = 40;
1300 num_gs_threads = 4;
1301 num_es_threads = 4;
1302 num_ps_stack_entries = 40;
1303 num_vs_stack_entries = 40;
1304 num_gs_stack_entries = 32;
1305 num_es_stack_entries = 16;
1306 break;
1307 case CHIP_RV610:
1308 case CHIP_RV620:
1309 case CHIP_RS780:
1310 case CHIP_RS880:
1311 default:
1312 num_ps_gprs = 84;
1313 num_vs_gprs = 36;
1314 num_temp_gprs = 4;
1315 num_gs_gprs = 0;
1316 num_es_gprs = 0;
1317 num_ps_threads = 136;
1318 num_vs_threads = 48;
1319 num_gs_threads = 4;
1320 num_es_threads = 4;
1321 num_ps_stack_entries = 40;
1322 num_vs_stack_entries = 40;
1323 num_gs_stack_entries = 32;
1324 num_es_stack_entries = 16;
1325 break;
1326 case CHIP_RV670:
1327 num_ps_gprs = 144;
1328 num_vs_gprs = 40;
1329 num_temp_gprs = 4;
1330 num_gs_gprs = 0;
1331 num_es_gprs = 0;
1332 num_ps_threads = 136;
1333 num_vs_threads = 48;
1334 num_gs_threads = 4;
1335 num_es_threads = 4;
1336 num_ps_stack_entries = 40;
1337 num_vs_stack_entries = 40;
1338 num_gs_stack_entries = 32;
1339 num_es_stack_entries = 16;
1340 break;
1341 case CHIP_RV770:
1342 num_ps_gprs = 192;
1343 num_vs_gprs = 56;
1344 num_temp_gprs = 4;
1345 num_gs_gprs = 0;
1346 num_es_gprs = 0;
1347 num_ps_threads = 188;
1348 num_vs_threads = 60;
1349 num_gs_threads = 0;
1350 num_es_threads = 0;
1351 num_ps_stack_entries = 256;
1352 num_vs_stack_entries = 256;
1353 num_gs_stack_entries = 0;
1354 num_es_stack_entries = 0;
1355 break;
1356 case CHIP_RV730:
1357 case CHIP_RV740:
1358 num_ps_gprs = 84;
1359 num_vs_gprs = 36;
1360 num_temp_gprs = 4;
1361 num_gs_gprs = 0;
1362 num_es_gprs = 0;
1363 num_ps_threads = 188;
1364 num_vs_threads = 60;
1365 num_gs_threads = 0;
1366 num_es_threads = 0;
1367 num_ps_stack_entries = 128;
1368 num_vs_stack_entries = 128;
1369 num_gs_stack_entries = 0;
1370 num_es_stack_entries = 0;
1371 break;
1372 case CHIP_RV710:
1373 num_ps_gprs = 192;
1374 num_vs_gprs = 56;
1375 num_temp_gprs = 4;
1376 num_gs_gprs = 0;
1377 num_es_gprs = 0;
1378 num_ps_threads = 144;
1379 num_vs_threads = 48;
1380 num_gs_threads = 0;
1381 num_es_threads = 0;
1382 num_ps_stack_entries = 128;
1383 num_vs_stack_entries = 128;
1384 num_gs_stack_entries = 0;
1385 num_es_stack_entries = 0;
1386 break;
1387 }
1388
1389 rstate->id = R600_PIPE_STATE_CONFIG;
1390
1391 /* SQ_CONFIG */
1392 tmp = 0;
1393 switch (family) {
1394 case CHIP_RV610:
1395 case CHIP_RV620:
1396 case CHIP_RS780:
1397 case CHIP_RS880:
1398 case CHIP_RV710:
1399 break;
1400 default:
1401 tmp |= S_008C00_VC_ENABLE(1);
1402 break;
1403 }
1404 tmp |= S_008C00_DX9_CONSTS(0);
1405 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1406 tmp |= S_008C00_PS_PRIO(ps_prio);
1407 tmp |= S_008C00_VS_PRIO(vs_prio);
1408 tmp |= S_008C00_GS_PRIO(gs_prio);
1409 tmp |= S_008C00_ES_PRIO(es_prio);
1410 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1411
1412 /* SQ_GPR_RESOURCE_MGMT_1 */
1413 tmp = 0;
1414 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1415 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1416 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1417 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1418
1419 /* SQ_GPR_RESOURCE_MGMT_2 */
1420 tmp = 0;
1421 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1422 tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
1423 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1424
1425 /* SQ_THREAD_RESOURCE_MGMT */
1426 tmp = 0;
1427 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1428 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1429 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1430 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1431 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1432
1433 /* SQ_STACK_RESOURCE_MGMT_1 */
1434 tmp = 0;
1435 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1436 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1437 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1438
1439 /* SQ_STACK_RESOURCE_MGMT_2 */
1440 tmp = 0;
1441 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1442 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1443 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1444
1445 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1446 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1447
1448 if (family >= CHIP_RV770) {
1449 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1450 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
1451 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1452 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1453 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1454 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL);
1455 } else {
1456 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1457 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
1458 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1459 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1460 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1461 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL);
1462 }
1463 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1464 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1465 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1466 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1467 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1468 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1469 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1470 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1471 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1472 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1473 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1474 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1475 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1476 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
1477 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
1478 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1479 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1480 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1481 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1482 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1483 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1484 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
1485 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1486 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1487 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1488 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
1489
1490 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1491 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
1492 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
1493 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
1494 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
1495 r600_context_pipe_state_set(&rctx->ctx, rstate);
1496 }
1497
1498 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
1499 {
1500 struct pipe_depth_stencil_alpha_state dsa;
1501 struct r600_pipe_state *rstate;
1502 boolean quirk = false;
1503
1504 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
1505 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
1506 quirk = true;
1507
1508 memset(&dsa, 0, sizeof(dsa));
1509
1510 if (quirk) {
1511 dsa.depth.enabled = 1;
1512 dsa.depth.func = PIPE_FUNC_LEQUAL;
1513 dsa.stencil[0].enabled = 1;
1514 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
1515 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
1516 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
1517 dsa.stencil[0].writemask = 0xff;
1518 }
1519
1520 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1521 r600_pipe_state_add_reg(rstate,
1522 R_02880C_DB_SHADER_CONTROL,
1523 0x0,
1524 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1525 r600_pipe_state_add_reg(rstate,
1526 R_028D0C_DB_RENDER_CONTROL,
1527 S_028D0C_DEPTH_COPY_ENABLE(1) |
1528 S_028D0C_STENCIL_COPY_ENABLE(1) |
1529 S_028D0C_COPY_CENTROID(1),
1530 S_028D0C_DEPTH_COPY_ENABLE(1) |
1531 S_028D0C_STENCIL_COPY_ENABLE(1) |
1532 S_028D0C_COPY_CENTROID(1), NULL);
1533 return rstate;
1534 }