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r600g: partialy fix texturing from depth buffer + initial support for untiling
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include <stdio.h>
27 #include <errno.h>
28 #include "util/u_inlines.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "r600_screen.h"
32 #include "r600_context.h"
33 #include "r600_resource.h"
34 #include "r600d.h"
35 #include "r600_state_inlines.h"
36
37 static void *r600_create_blend_state(struct pipe_context *ctx,
38 const struct pipe_blend_state *state)
39 {
40 struct r600_context *rctx = r600_context(ctx);
41
42 return r600_context_state(rctx, pipe_blend_type, state);
43 }
44
45 static void *r600_create_dsa_state(struct pipe_context *ctx,
46 const struct pipe_depth_stencil_alpha_state *state)
47 {
48 struct r600_context *rctx = r600_context(ctx);
49
50 return r600_context_state(rctx, pipe_dsa_type, state);
51 }
52
53 static void *r600_create_rs_state(struct pipe_context *ctx,
54 const struct pipe_rasterizer_state *state)
55 {
56 struct r600_context *rctx = r600_context(ctx);
57
58 return r600_context_state(rctx, pipe_rasterizer_type, state);
59 }
60
61 static void *r600_create_sampler_state(struct pipe_context *ctx,
62 const struct pipe_sampler_state *state)
63 {
64 struct r600_context *rctx = r600_context(ctx);
65
66 return r600_context_state(rctx, pipe_sampler_type, state);
67 }
68
69 static void r600_sampler_view_destroy(struct pipe_context *ctx,
70 struct pipe_sampler_view *state)
71 {
72 struct r600_context_state *rstate = (struct r600_context_state *)state;
73
74 r600_context_state_decref(rstate);
75 }
76
77 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
78 struct pipe_resource *texture,
79 const struct pipe_sampler_view *state)
80 {
81 struct r600_context *rctx = r600_context(ctx);
82 struct r600_context_state *rstate;
83
84 rstate = r600_context_state(rctx, pipe_sampler_type, state);
85 pipe_reference(NULL, &texture->reference);
86 rstate->state.sampler_view.texture = texture;
87 rstate->state.sampler_view.reference.count = 1;
88 rstate->state.sampler_view.context = ctx;
89 return &rstate->state.sampler_view;
90 }
91
92 static void *r600_create_shader_state(struct pipe_context *ctx,
93 const struct pipe_shader_state *state)
94 {
95 struct r600_context *rctx = r600_context(ctx);
96
97 return r600_context_state(rctx, pipe_shader_type, state);
98 }
99
100 static void *r600_create_vertex_elements(struct pipe_context *ctx,
101 unsigned count,
102 const struct pipe_vertex_element *elements)
103 {
104 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
105
106 assert(count < 32);
107 v->count = count;
108 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
109 v->refcount = 1;
110 return v;
111 }
112
113 static void r600_bind_state(struct pipe_context *ctx, void *state)
114 {
115 struct r600_context *rctx = r600_context(ctx);
116 struct r600_context_state *rstate = (struct r600_context_state *)state;
117
118 if (state == NULL)
119 return;
120 switch (rstate->type) {
121 case pipe_rasterizer_type:
122 rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
123 rctx->rasterizer = r600_context_state_incref(rstate);
124 break;
125 case pipe_poly_stipple_type:
126 rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple);
127 rctx->poly_stipple = r600_context_state_incref(rstate);
128 break;
129 case pipe_scissor_type:
130 rctx->scissor = r600_context_state_decref(rctx->scissor);
131 rctx->scissor = r600_context_state_incref(rstate);
132 break;
133 case pipe_clip_type:
134 rctx->clip = r600_context_state_decref(rctx->clip);
135 rctx->clip = r600_context_state_incref(rstate);
136 break;
137 case pipe_depth_type:
138 rctx->depth = r600_context_state_decref(rctx->depth);
139 rctx->depth = r600_context_state_incref(rstate);
140 break;
141 case pipe_stencil_type:
142 rctx->stencil = r600_context_state_decref(rctx->stencil);
143 rctx->stencil = r600_context_state_incref(rstate);
144 break;
145 case pipe_alpha_type:
146 rctx->alpha = r600_context_state_decref(rctx->alpha);
147 rctx->alpha = r600_context_state_incref(rstate);
148 break;
149 case pipe_dsa_type:
150 rctx->dsa = r600_context_state_decref(rctx->dsa);
151 rctx->dsa = r600_context_state_incref(rstate);
152 break;
153 case pipe_blend_type:
154 rctx->blend = r600_context_state_decref(rctx->blend);
155 rctx->blend = r600_context_state_incref(rstate);
156 break;
157 case pipe_framebuffer_type:
158 rctx->framebuffer = r600_context_state_decref(rctx->framebuffer);
159 rctx->framebuffer = r600_context_state_incref(rstate);
160 break;
161 case pipe_stencil_ref_type:
162 rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref);
163 rctx->stencil_ref = r600_context_state_incref(rstate);
164 break;
165 case pipe_viewport_type:
166 rctx->viewport = r600_context_state_decref(rctx->viewport);
167 rctx->viewport = r600_context_state_incref(rstate);
168 break;
169 case pipe_shader_type:
170 case pipe_sampler_type:
171 case pipe_sampler_view_type:
172 default:
173 R600_ERR("invalid type %d\n", rstate->type);
174 return;
175 }
176 }
177
178 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
179 {
180 struct r600_context *rctx = r600_context(ctx);
181 struct r600_context_state *rstate = (struct r600_context_state *)state;
182
183 rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
184 rctx->ps_shader = r600_context_state_incref(rstate);
185 }
186
187 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
188 {
189 struct r600_context *rctx = r600_context(ctx);
190 struct r600_context_state *rstate = (struct r600_context_state *)state;
191
192 rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
193 rctx->vs_shader = r600_context_state_incref(rstate);
194 }
195
196 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
197 {
198 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
199
200 if (v == NULL)
201 return;
202 if (--v->refcount)
203 return;
204 free(v);
205 }
206
207 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
208 {
209 struct r600_context *rctx = r600_context(ctx);
210 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
211
212 r600_delete_vertex_element(ctx, rctx->vertex_elements);
213 rctx->vertex_elements = v;
214 if (v) {
215 v->refcount++;
216 }
217 }
218
219 static void r600_bind_ps_sampler(struct pipe_context *ctx,
220 unsigned count, void **states)
221 {
222 struct r600_context *rctx = r600_context(ctx);
223 struct r600_context_state *rstate;
224 unsigned i;
225
226 for (i = 0; i < rctx->ps_nsampler; i++) {
227 rctx->ps_sampler[i] = r600_context_state_decref(rctx->ps_sampler[i]);
228 }
229 for (i = 0; i < count; i++) {
230 rstate = (struct r600_context_state *)states[i];
231 rctx->ps_sampler[i] = r600_context_state_incref(rstate);
232 }
233 rctx->ps_nsampler = count;
234 }
235
236 static void r600_bind_vs_sampler(struct pipe_context *ctx,
237 unsigned count, void **states)
238 {
239 struct r600_context *rctx = r600_context(ctx);
240 struct r600_context_state *rstate;
241 unsigned i;
242
243 for (i = 0; i < rctx->vs_nsampler; i++) {
244 rctx->vs_sampler[i] = r600_context_state_decref(rctx->vs_sampler[i]);
245 }
246 for (i = 0; i < count; i++) {
247 rstate = (struct r600_context_state *)states[i];
248 rctx->vs_sampler[i] = r600_context_state_incref(rstate);
249 }
250 rctx->vs_nsampler = count;
251 }
252
253 static void r600_delete_state(struct pipe_context *ctx, void *state)
254 {
255 struct r600_context_state *rstate = (struct r600_context_state *)state;
256
257 r600_context_state_decref(rstate);
258 }
259
260 static void r600_set_blend_color(struct pipe_context *ctx,
261 const struct pipe_blend_color *color)
262 {
263 struct r600_context *rctx = r600_context(ctx);
264
265 rctx->blend_color = *color;
266 }
267
268 static void r600_set_clip_state(struct pipe_context *ctx,
269 const struct pipe_clip_state *state)
270 {
271 struct r600_context *rctx = r600_context(ctx);
272 struct r600_context_state *rstate;
273
274 rstate = r600_context_state(rctx, pipe_clip_type, state);
275 r600_bind_state(ctx, rstate);
276 /* refcount is taken care of this */
277 r600_delete_state(ctx, rstate);
278 }
279
280 static void r600_set_constant_buffer(struct pipe_context *ctx,
281 uint shader, uint index,
282 struct pipe_resource *buffer)
283 {
284 struct r600_screen *rscreen = r600_screen(ctx->screen);
285 struct r600_context *rctx = r600_context(ctx);
286 unsigned nconstant = 0, i, type, id;
287 struct radeon_state *rstate;
288 struct pipe_transfer *transfer;
289 u32 *ptr;
290
291 switch (shader) {
292 case PIPE_SHADER_VERTEX:
293 id = R600_VS_CONSTANT;
294 type = R600_VS_CONSTANT_TYPE;
295 break;
296 case PIPE_SHADER_FRAGMENT:
297 id = R600_PS_CONSTANT;
298 type = R600_PS_CONSTANT_TYPE;
299 break;
300 default:
301 R600_ERR("unsupported %d\n", shader);
302 return;
303 }
304 if (buffer && buffer->width0 > 0) {
305 nconstant = buffer->width0 / 16;
306 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
307 if (ptr == NULL)
308 return;
309 for (i = 0; i < nconstant; i++) {
310 rstate = radeon_state(rscreen->rw, type, id + i);
311 if (rstate == NULL)
312 return;
313 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
314 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
315 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
316 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
317 if (radeon_state_pm4(rstate))
318 return;
319 if (radeon_draw_set_new(rctx->draw, rstate))
320 return;
321 }
322 pipe_buffer_unmap(ctx, buffer, transfer);
323 }
324 }
325
326 static void r600_set_ps_sampler_view(struct pipe_context *ctx,
327 unsigned count,
328 struct pipe_sampler_view **views)
329 {
330 struct r600_context *rctx = r600_context(ctx);
331 struct r600_context_state *rstate;
332 unsigned i;
333
334 for (i = 0; i < rctx->ps_nsampler_view; i++) {
335 rctx->ps_sampler_view[i] = r600_context_state_decref(rctx->ps_sampler_view[i]);
336 }
337 for (i = 0; i < count; i++) {
338 rstate = (struct r600_context_state *)views[i];
339 rctx->ps_sampler_view[i] = r600_context_state_incref(rstate);
340 }
341 rctx->ps_nsampler_view = count;
342 }
343
344 static void r600_set_vs_sampler_view(struct pipe_context *ctx,
345 unsigned count,
346 struct pipe_sampler_view **views)
347 {
348 struct r600_context *rctx = r600_context(ctx);
349 struct r600_context_state *rstate;
350 unsigned i;
351
352 for (i = 0; i < rctx->vs_nsampler_view; i++) {
353 rctx->vs_sampler_view[i] = r600_context_state_decref(rctx->vs_sampler_view[i]);
354 }
355 for (i = 0; i < count; i++) {
356 rstate = (struct r600_context_state *)views[i];
357 rctx->vs_sampler_view[i] = r600_context_state_incref(rstate);
358 }
359 rctx->vs_nsampler_view = count;
360 }
361
362 static void r600_set_framebuffer_state(struct pipe_context *ctx,
363 const struct pipe_framebuffer_state *state)
364 {
365 struct r600_context *rctx = r600_context(ctx);
366 struct r600_context_state *rstate;
367
368 rstate = r600_context_state(rctx, pipe_framebuffer_type, state);
369 r600_bind_state(ctx, rstate);
370 }
371
372 static void r600_set_polygon_stipple(struct pipe_context *ctx,
373 const struct pipe_poly_stipple *state)
374 {
375 }
376
377 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
378 {
379 }
380
381 static void r600_set_scissor_state(struct pipe_context *ctx,
382 const struct pipe_scissor_state *state)
383 {
384 struct r600_context *rctx = r600_context(ctx);
385 struct r600_context_state *rstate;
386
387 rstate = r600_context_state(rctx, pipe_scissor_type, state);
388 r600_bind_state(ctx, rstate);
389 /* refcount is taken care of this */
390 r600_delete_state(ctx, rstate);
391 }
392
393 static void r600_set_stencil_ref(struct pipe_context *ctx,
394 const struct pipe_stencil_ref *state)
395 {
396 struct r600_context *rctx = r600_context(ctx);
397 struct r600_context_state *rstate;
398
399 rstate = r600_context_state(rctx, pipe_stencil_ref_type, state);
400 r600_bind_state(ctx, rstate);
401 /* refcount is taken care of this */
402 r600_delete_state(ctx, rstate);
403 }
404
405 static void r600_set_vertex_buffers(struct pipe_context *ctx,
406 unsigned count,
407 const struct pipe_vertex_buffer *buffers)
408 {
409 struct r600_context *rctx = r600_context(ctx);
410 unsigned i;
411
412 for (i = 0; i < rctx->nvertex_buffer; i++) {
413 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
414 }
415 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
416 for (i = 0; i < count; i++) {
417 rctx->vertex_buffer[i].buffer = NULL;
418 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
419 }
420 rctx->nvertex_buffer = count;
421 }
422
423 static void r600_set_index_buffer(struct pipe_context *ctx,
424 const struct pipe_index_buffer *ib)
425 {
426 struct r600_context *rctx = r600_context(ctx);
427
428 if (ib) {
429 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
430 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
431 } else {
432 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
433 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
434 }
435
436 /* TODO make this more like a state */
437 }
438
439 static void r600_set_viewport_state(struct pipe_context *ctx,
440 const struct pipe_viewport_state *state)
441 {
442 struct r600_context *rctx = r600_context(ctx);
443 struct r600_context_state *rstate;
444
445 rstate = r600_context_state(rctx, pipe_viewport_type, state);
446 r600_bind_state(ctx, rstate);
447 r600_delete_state(ctx, rstate);
448 }
449
450 void r600_init_state_functions(struct r600_context *rctx)
451 {
452 rctx->context.create_blend_state = r600_create_blend_state;
453 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
454 rctx->context.create_fs_state = r600_create_shader_state;
455 rctx->context.create_rasterizer_state = r600_create_rs_state;
456 rctx->context.create_sampler_state = r600_create_sampler_state;
457 rctx->context.create_sampler_view = r600_create_sampler_view;
458 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
459 rctx->context.create_vs_state = r600_create_shader_state;
460 rctx->context.bind_blend_state = r600_bind_state;
461 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
462 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
463 rctx->context.bind_fs_state = r600_bind_ps_shader;
464 rctx->context.bind_rasterizer_state = r600_bind_state;
465 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
466 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
467 rctx->context.bind_vs_state = r600_bind_vs_shader;
468 rctx->context.delete_blend_state = r600_delete_state;
469 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
470 rctx->context.delete_fs_state = r600_delete_state;
471 rctx->context.delete_rasterizer_state = r600_delete_state;
472 rctx->context.delete_sampler_state = r600_delete_state;
473 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
474 rctx->context.delete_vs_state = r600_delete_state;
475 rctx->context.set_blend_color = r600_set_blend_color;
476 rctx->context.set_clip_state = r600_set_clip_state;
477 rctx->context.set_constant_buffer = r600_set_constant_buffer;
478 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
479 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
480 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
481 rctx->context.set_sample_mask = r600_set_sample_mask;
482 rctx->context.set_scissor_state = r600_set_scissor_state;
483 rctx->context.set_stencil_ref = r600_set_stencil_ref;
484 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
485 rctx->context.set_index_buffer = r600_set_index_buffer;
486 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
487 rctx->context.set_viewport_state = r600_set_viewport_state;
488 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
489 }
490
491 struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate)
492 {
493 if (rstate == NULL)
494 return NULL;
495 rstate->refcount++;
496 return rstate;
497 }
498
499 struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate)
500 {
501 unsigned i;
502
503 if (rstate == NULL)
504 return NULL;
505 if (--rstate->refcount)
506 return NULL;
507 switch (rstate->type) {
508 case pipe_sampler_view_type:
509 pipe_resource_reference(&rstate->state.sampler_view.texture, NULL);
510 break;
511 case pipe_framebuffer_type:
512 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
513 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], NULL);
514 }
515 pipe_surface_reference(&rstate->state.framebuffer.zsbuf, NULL);
516 break;
517 case pipe_viewport_type:
518 case pipe_depth_type:
519 case pipe_rasterizer_type:
520 case pipe_poly_stipple_type:
521 case pipe_scissor_type:
522 case pipe_clip_type:
523 case pipe_stencil_type:
524 case pipe_alpha_type:
525 case pipe_dsa_type:
526 case pipe_blend_type:
527 case pipe_stencil_ref_type:
528 case pipe_shader_type:
529 case pipe_sampler_type:
530 break;
531 default:
532 R600_ERR("invalid type %d\n", rstate->type);
533 return NULL;
534 }
535 radeon_state_decref(rstate->rstate);
536 FREE(rstate);
537 return NULL;
538 }
539
540 struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state)
541 {
542 struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state);
543 const union pipe_states *states = state;
544 unsigned i;
545 int r;
546
547 if (rstate == NULL)
548 return NULL;
549 rstate->type = type;
550 rstate->refcount = 1;
551
552 switch (rstate->type) {
553 case pipe_sampler_view_type:
554 rstate->state.sampler_view = (*states).sampler_view;
555 rstate->state.sampler_view.texture = NULL;
556 break;
557 case pipe_framebuffer_type:
558 rstate->state.framebuffer = (*states).framebuffer;
559 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
560 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i],
561 (*states).framebuffer.cbufs[i]);
562 }
563 pipe_surface_reference(&rstate->state.framebuffer.zsbuf,
564 (*states).framebuffer.zsbuf);
565 break;
566 case pipe_viewport_type:
567 rstate->state.viewport = (*states).viewport;
568 break;
569 case pipe_depth_type:
570 rstate->state.depth = (*states).depth;
571 break;
572 case pipe_rasterizer_type:
573 rstate->state.rasterizer = (*states).rasterizer;
574 break;
575 case pipe_poly_stipple_type:
576 rstate->state.poly_stipple = (*states).poly_stipple;
577 break;
578 case pipe_scissor_type:
579 rstate->state.scissor = (*states).scissor;
580 break;
581 case pipe_clip_type:
582 rstate->state.clip = (*states).clip;
583 break;
584 case pipe_stencil_type:
585 rstate->state.stencil = (*states).stencil;
586 break;
587 case pipe_alpha_type:
588 rstate->state.alpha = (*states).alpha;
589 break;
590 case pipe_dsa_type:
591 rstate->state.dsa = (*states).dsa;
592 break;
593 case pipe_blend_type:
594 rstate->state.blend = (*states).blend;
595 break;
596 case pipe_stencil_ref_type:
597 rstate->state.stencil_ref = (*states).stencil_ref;
598 break;
599 case pipe_shader_type:
600 rstate->state.shader = (*states).shader;
601 r = r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens);
602 if (r) {
603 r600_context_state_decref(rstate);
604 return NULL;
605 }
606 break;
607 case pipe_sampler_type:
608 rstate->state.sampler = (*states).sampler;
609 break;
610 default:
611 R600_ERR("invalid type %d\n", rstate->type);
612 FREE(rstate);
613 return NULL;
614 }
615 return rstate;
616 }
617
618 static struct radeon_state *r600_blend(struct r600_context *rctx)
619 {
620 struct r600_screen *rscreen = rctx->screen;
621 struct radeon_state *rstate;
622 const struct pipe_blend_state *state = &rctx->blend->state.blend;
623 int i;
624
625 rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
626 if (rstate == NULL)
627 return NULL;
628 rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
629 rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
630 rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
631 rstate->states[R600_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
632 rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
633 rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
634 rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
635 rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
636 rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
637 rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
638 rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
639 rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
640 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
641
642 for (i = 0; i < 8; i++) {
643 unsigned eqRGB = state->rt[i].rgb_func;
644 unsigned srcRGB = state->rt[i].rgb_src_factor;
645 unsigned dstRGB = state->rt[i].rgb_dst_factor;
646
647 unsigned eqA = state->rt[i].alpha_func;
648 unsigned srcA = state->rt[i].alpha_src_factor;
649 unsigned dstA = state->rt[i].alpha_dst_factor;
650 uint32_t bc = 0;
651
652 if (!state->rt[i].blend_enable)
653 continue;
654
655 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
656 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
657 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
658
659 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
660 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
661 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
662 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
663 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
664 }
665
666 rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc;
667 if (i == 0)
668 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
669 }
670
671 if (radeon_state_pm4(rstate)) {
672 radeon_state_decref(rstate);
673 return NULL;
674 }
675 return rstate;
676 }
677
678 static struct radeon_state *r600_ucp(struct r600_context *rctx, int clip)
679 {
680 struct r600_screen *rscreen = rctx->screen;
681 struct radeon_state *rstate;
682 const struct pipe_clip_state *state = &rctx->clip->state.clip;
683
684 rstate = radeon_state(rscreen->rw, R600_CLIP_TYPE, R600_CLIP + clip);
685 if (rstate == NULL)
686 return NULL;
687
688 rstate->states[R600_CLIP__PA_CL_UCP_X_0] = fui(state->ucp[clip][0]);
689 rstate->states[R600_CLIP__PA_CL_UCP_Y_0] = fui(state->ucp[clip][1]);
690 rstate->states[R600_CLIP__PA_CL_UCP_Z_0] = fui(state->ucp[clip][2]);
691 rstate->states[R600_CLIP__PA_CL_UCP_W_0] = fui(state->ucp[clip][3]);
692
693 if (radeon_state_pm4(rstate)) {
694 radeon_state_decref(rstate);
695 return NULL;
696 }
697 return rstate;
698
699 }
700
701 static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
702 {
703 struct r600_screen *rscreen = rctx->screen;
704 struct r600_resource_texture *rtex;
705 struct r600_resource *rbuffer;
706 struct radeon_state *rstate;
707 const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
708 unsigned level = state->cbufs[cb]->level;
709 unsigned pitch, slice;
710 unsigned color_info;
711 unsigned format, swap, ntype;
712 const struct util_format_description *desc;
713
714 rstate = radeon_state(rscreen->rw, R600_CB0_TYPE + cb, R600_CB0 + cb);
715 if (rstate == NULL)
716 return NULL;
717 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
718 rbuffer = &rtex->resource;
719 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
720 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
721 rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
722 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
723 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
724 rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
725 rstate->nbo = 3;
726 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
727 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
728
729 ntype = 0;
730 desc = util_format_description(rtex->resource.base.b.format);
731 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
732 ntype = V_0280A0_NUMBER_SRGB;
733
734 format = r600_translate_colorformat(rtex->resource.base.b.format);
735 swap = r600_translate_colorswap(rtex->resource.base.b.format);
736
737 color_info = S_0280A0_FORMAT(format) |
738 S_0280A0_COMP_SWAP(swap) |
739 S_0280A0_BLEND_CLAMP(1) |
740 S_0280A0_SOURCE_FORMAT(1) |
741 S_0280A0_NUMBER_TYPE(ntype);
742
743 rstate->states[R600_CB0__CB_COLOR0_BASE] = rtex->offset[level] >> 8;
744 rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
745 rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
746 S_028060_SLICE_TILE_MAX(slice);
747 rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
748 rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
749 rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
750 rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
751 if (radeon_state_pm4(rstate)) {
752 radeon_state_decref(rstate);
753 return NULL;
754 }
755 return rstate;
756 }
757
758 static struct radeon_state *r600_db(struct r600_context *rctx)
759 {
760 struct r600_screen *rscreen = rctx->screen;
761 struct r600_resource_texture *rtex;
762 struct r600_resource *rbuffer;
763 struct radeon_state *rstate;
764 const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
765 unsigned level;
766 unsigned pitch, slice, format;
767
768 if (state->zsbuf == NULL)
769 return NULL;
770
771 rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
772 if (rstate == NULL)
773 return NULL;
774
775 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
776 rtex->tilled = 1;
777 rtex->array_mode = 2;
778 rtex->tile_type = 1;
779 rbuffer = &rtex->resource;
780 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
781 rstate->nbo = 1;
782 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
783 level = state->zsbuf->level;
784 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
785 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
786 format = r600_translate_dbformat(state->zsbuf->texture->format);
787 rstate->states[R600_DB__DB_DEPTH_BASE] = rtex->offset[level] >> 8;
788 rstate->states[R600_DB__DB_DEPTH_INFO] = 0x00010000 |
789 S_028010_FORMAT(format);
790 rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
791 rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
792 rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
793 S_028000_SLICE_TILE_MAX(slice);
794 if (radeon_state_pm4(rstate)) {
795 radeon_state_decref(rstate);
796 return NULL;
797 }
798 return rstate;
799 }
800
801 static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
802 {
803 const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
804 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
805 const struct pipe_clip_state *clip = NULL;
806 struct r600_screen *rscreen = rctx->screen;
807 struct radeon_state *rstate;
808 float offset_units = 0, offset_scale = 0;
809 char depth = 0;
810 unsigned offset_db_fmt_cntl = 0;
811 unsigned tmp;
812 unsigned prov_vtx = 1;
813
814 if (rctx->clip)
815 clip = &rctx->clip->state.clip;
816 if (fb->zsbuf) {
817 offset_units = state->offset_units;
818 offset_scale = state->offset_scale * 12.0f;
819 switch (fb->zsbuf->texture->format) {
820 case PIPE_FORMAT_Z24X8_UNORM:
821 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
822 depth = -24;
823 offset_units *= 2.0f;
824 break;
825 case PIPE_FORMAT_Z32_FLOAT:
826 depth = -23;
827 offset_units *= 1.0f;
828 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
829 break;
830 case PIPE_FORMAT_Z16_UNORM:
831 depth = -16;
832 offset_units *= 4.0f;
833 break;
834 default:
835 R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
836 return NULL;
837 }
838 }
839 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
840
841 if (state->flatshade_first)
842 prov_vtx = 0;
843
844 rctx->flat_shade = state->flatshade;
845 rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
846 if (rstate == NULL)
847 return NULL;
848 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
849 if (state->sprite_coord_enable) {
850 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
851 S_0286D4_PNT_SPRITE_ENA(1) |
852 S_0286D4_PNT_SPRITE_OVRD_X(2) |
853 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
854 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
855 S_0286D4_PNT_SPRITE_OVRD_W(1);
856 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
857 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
858 S_0286D4_PNT_SPRITE_TOP_1(1);
859 }
860 }
861 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
862 if (clip && clip->nr) {
863 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1);
864 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_CLIP_DISABLE(clip->depth_clamp);
865 }
866 rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] =
867 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
868 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
869 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
870 S_028814_FACE(!state->front_ccw) |
871 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
872 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
873 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
874 rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] =
875 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
876 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
877 rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
878 /* point size 12.4 fixed point */
879 tmp = (unsigned)(state->point_size * 8.0);
880 rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
881 rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
882 rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
883 rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
884 rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
885 rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
886 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
887 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
888 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
889 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
890 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
891 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
892 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
893 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
894 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
895 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
896 if (radeon_state_pm4(rstate)) {
897 radeon_state_decref(rstate);
898 return NULL;
899 }
900 return rstate;
901 }
902
903 static struct radeon_state *r600_scissor(struct r600_context *rctx)
904 {
905 const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
906 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
907 struct r600_screen *rscreen = rctx->screen;
908 struct radeon_state *rstate;
909 unsigned minx, maxx, miny, maxy;
910 u32 tl, br;
911
912 if (state == NULL) {
913 minx = 0;
914 miny = 0;
915 maxx = fb->cbufs[0]->width;
916 maxy = fb->cbufs[0]->height;
917 } else {
918 minx = state->minx;
919 miny = state->miny;
920 maxx = state->maxx;
921 maxy = state->maxy;
922 }
923 tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
924 br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
925 rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
926 if (rstate == NULL)
927 return NULL;
928 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
929 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
930 rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
931 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
932 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
933 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
934 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
935 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
936 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
937 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
938 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
939 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
940 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
941 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
942 rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
943 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
944 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
945 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
946 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
947 if (radeon_state_pm4(rstate)) {
948 radeon_state_decref(rstate);
949 return NULL;
950 }
951 return rstate;
952 }
953
954 static struct radeon_state *r600_viewport(struct r600_context *rctx)
955 {
956 const struct pipe_viewport_state *state = &rctx->viewport->state.viewport;
957 struct r600_screen *rscreen = rctx->screen;
958 struct radeon_state *rstate;
959
960 rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
961 if (rstate == NULL)
962 return NULL;
963 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
964 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
965 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
966 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
967 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
968 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
969 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
970 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
971 rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
972 if (radeon_state_pm4(rstate)) {
973 radeon_state_decref(rstate);
974 return NULL;
975 }
976 return rstate;
977 }
978
979 static struct radeon_state *r600_dsa(struct r600_context *rctx)
980 {
981 const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
982 const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
983 struct r600_screen *rscreen = rctx->screen;
984 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
985 unsigned stencil_ref_mask, stencil_ref_mask_bf;
986 struct r600_shader *rshader;
987 struct radeon_state *rstate;
988 int i;
989
990 if (rctx->ps_shader == NULL) {
991 return NULL;
992 }
993 rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
994 if (rstate == NULL)
995 return NULL;
996
997 db_shader_control = 0x210;
998 rshader = &rctx->ps_shader->shader;
999 for (i = 0; i < rshader->noutput; i++) {
1000 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1001 db_shader_control |= 1;
1002 }
1003 stencil_ref_mask = 0;
1004 stencil_ref_mask_bf = 0;
1005 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1006 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1007 S_028800_ZFUNC(state->depth.func);
1008 /* set stencil enable */
1009
1010 if (state->stencil[0].enabled) {
1011 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1012 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
1013 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
1014 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
1015 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
1016
1017 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
1018 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
1019 stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]);
1020 if (state->stencil[1].enabled) {
1021 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1022 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
1023 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
1024 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
1025 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
1026 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
1027 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
1028 stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]);
1029 }
1030 }
1031
1032 alpha_test_control = 0;
1033 alpha_ref = 0;
1034 if (state->alpha.enabled) {
1035 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
1036 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
1037 alpha_ref = fui(state->alpha.ref_value);
1038 }
1039
1040 rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
1041 rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
1042 rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
1043 rstate->states[R600_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
1044 rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
1045 rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref;
1046 rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
1047 rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
1048 rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
1049 rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
1050 rstate->states[R600_DSA__DB_SHADER_CONTROL] = db_shader_control;
1051 rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060;
1052 rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
1053 rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
1054 rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
1055 rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
1056 if (radeon_state_pm4(rstate)) {
1057 radeon_state_decref(rstate);
1058 return NULL;
1059 }
1060 return rstate;
1061 }
1062
1063 static inline unsigned r600_tex_wrap(unsigned wrap)
1064 {
1065 switch (wrap) {
1066 default:
1067 case PIPE_TEX_WRAP_REPEAT:
1068 return V_03C000_SQ_TEX_WRAP;
1069 case PIPE_TEX_WRAP_CLAMP:
1070 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1071 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1072 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1073 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1074 return V_03C000_SQ_TEX_CLAMP_BORDER;
1075 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1076 return V_03C000_SQ_TEX_MIRROR;
1077 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1078 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1079 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1080 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1081 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1082 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1083 }
1084 }
1085
1086 static inline unsigned r600_tex_filter(unsigned filter)
1087 {
1088 switch (filter) {
1089 default:
1090 case PIPE_TEX_FILTER_NEAREST:
1091 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1092 case PIPE_TEX_FILTER_LINEAR:
1093 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1094 }
1095 }
1096
1097 static inline unsigned r600_tex_mipfilter(unsigned filter)
1098 {
1099 switch (filter) {
1100 case PIPE_TEX_MIPFILTER_NEAREST:
1101 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1102 case PIPE_TEX_MIPFILTER_LINEAR:
1103 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1104 default:
1105 case PIPE_TEX_MIPFILTER_NONE:
1106 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1107 }
1108 }
1109
1110 static inline unsigned r600_tex_compare(unsigned compare)
1111 {
1112 switch (compare) {
1113 default:
1114 case PIPE_FUNC_NEVER:
1115 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1116 case PIPE_FUNC_LESS:
1117 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1118 case PIPE_FUNC_EQUAL:
1119 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1120 case PIPE_FUNC_LEQUAL:
1121 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1122 case PIPE_FUNC_GREATER:
1123 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1124 case PIPE_FUNC_NOTEQUAL:
1125 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1126 case PIPE_FUNC_GEQUAL:
1127 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1128 case PIPE_FUNC_ALWAYS:
1129 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1130 }
1131 }
1132
1133 static INLINE u32 S_FIXED(float value, u32 frac_bits)
1134 {
1135 return value * (1 << frac_bits);
1136 }
1137
1138 static struct radeon_state *r600_sampler(struct r600_context *rctx,
1139 const struct pipe_sampler_state *state,
1140 unsigned id)
1141 {
1142 struct r600_screen *rscreen = rctx->screen;
1143 struct radeon_state *rstate;
1144
1145 rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, id);
1146 if (rstate == NULL)
1147 return NULL;
1148 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
1149 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1150 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1151 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1152 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
1153 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
1154 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1155 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func));
1156 /* FIXME LOD it depends on texture base level ... */
1157 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
1158 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1159 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1160 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
1161 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
1162 if (radeon_state_pm4(rstate)) {
1163 radeon_state_decref(rstate);
1164 return NULL;
1165 }
1166 return rstate;
1167 }
1168
1169 static inline unsigned r600_tex_swizzle(unsigned swizzle)
1170 {
1171 switch (swizzle) {
1172 case PIPE_SWIZZLE_RED:
1173 return V_038010_SQ_SEL_X;
1174 case PIPE_SWIZZLE_GREEN:
1175 return V_038010_SQ_SEL_Y;
1176 case PIPE_SWIZZLE_BLUE:
1177 return V_038010_SQ_SEL_Z;
1178 case PIPE_SWIZZLE_ALPHA:
1179 return V_038010_SQ_SEL_W;
1180 case PIPE_SWIZZLE_ZERO:
1181 return V_038010_SQ_SEL_0;
1182 default:
1183 case PIPE_SWIZZLE_ONE:
1184 return V_038010_SQ_SEL_1;
1185 }
1186 }
1187
1188 static inline unsigned r600_format_type(unsigned format_type)
1189 {
1190 switch (format_type) {
1191 default:
1192 case UTIL_FORMAT_TYPE_UNSIGNED:
1193 return V_038010_SQ_FORMAT_COMP_UNSIGNED;
1194 case UTIL_FORMAT_TYPE_SIGNED:
1195 return V_038010_SQ_FORMAT_COMP_SIGNED;
1196 case UTIL_FORMAT_TYPE_FIXED:
1197 return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED;
1198 }
1199 }
1200
1201 static inline unsigned r600_tex_dim(unsigned dim)
1202 {
1203 switch (dim) {
1204 default:
1205 case PIPE_TEXTURE_1D:
1206 return V_038000_SQ_TEX_DIM_1D;
1207 case PIPE_TEXTURE_2D:
1208 case PIPE_TEXTURE_RECT:
1209 return V_038000_SQ_TEX_DIM_2D;
1210 case PIPE_TEXTURE_3D:
1211 return V_038000_SQ_TEX_DIM_3D;
1212 case PIPE_TEXTURE_CUBE:
1213 return V_038000_SQ_TEX_DIM_CUBEMAP;
1214 }
1215 }
1216
1217 static struct radeon_state *r600_resource(struct r600_context *rctx,
1218 const struct pipe_sampler_view *view,
1219 unsigned id)
1220 {
1221 struct r600_screen *rscreen = rctx->screen;
1222 const struct util_format_description *desc;
1223 struct r600_resource_texture *tmp;
1224 struct r600_resource *rbuffer;
1225 struct radeon_state *rstate;
1226 unsigned format;
1227 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1228 unsigned char swizzle[4];
1229
1230 swizzle[0] = view->swizzle_r;
1231 swizzle[1] = view->swizzle_g;
1232 swizzle[2] = view->swizzle_b;
1233 swizzle[3] = view->swizzle_a;
1234 format = r600_translate_texformat(view->texture->format,
1235 swizzle,
1236 &word4, &yuv_format);
1237 if (format == ~0)
1238 return NULL;
1239 desc = util_format_description(view->texture->format);
1240 if (desc == NULL) {
1241 R600_ERR("unknow format %d\n", view->texture->format);
1242 return NULL;
1243 }
1244 rstate = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, id);
1245 if (rstate == NULL) {
1246 return NULL;
1247 }
1248 tmp = (struct r600_resource_texture*)view->texture;
1249 rbuffer = &tmp->resource;
1250 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1251 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1252 rstate->nbo = 2;
1253 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
1254 rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
1255 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
1256 rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
1257
1258 pitch = (tmp->pitch[0] / tmp->bpt);
1259 pitch = (pitch + 0x7) & ~0x7;
1260
1261 /* FIXME properly handle first level != 0 */
1262 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
1263 S_038000_DIM(r600_tex_dim(view->texture->target)) |
1264 S_038000_TILE_MODE(tmp->array_mode) |
1265 S_038000_TILE_TYPE(tmp->tile_type) |
1266 S_038000_PITCH((pitch / 8) - 1) |
1267 S_038000_TEX_WIDTH(view->texture->width0 - 1);
1268 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
1269 S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
1270 S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
1271 S_038004_DATA_FORMAT(format);
1272 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
1273 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
1274 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
1275 word4 |
1276 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
1277 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
1278 S_038010_REQUEST_SIZE(1) |
1279 S_038010_BASE_LEVEL(view->first_level);
1280 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
1281 S_038014_LAST_LEVEL(view->last_level) |
1282 S_038014_BASE_ARRAY(0) |
1283 S_038014_LAST_ARRAY(0);
1284 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
1285 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
1286 if (radeon_state_pm4(rstate)) {
1287 radeon_state_decref(rstate);
1288 return NULL;
1289 }
1290 return rstate;
1291 }
1292
1293 static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
1294 {
1295 struct r600_screen *rscreen = rctx->screen;
1296 struct radeon_state *rstate;
1297 const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
1298 int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
1299 uint32_t color_control, target_mask, shader_mask;
1300 int i;
1301
1302 target_mask = 0;
1303 shader_mask = 0;
1304 color_control = S_028808_PER_MRT_BLEND(1);
1305
1306 for (i = 0; i < nr_cbufs; i++) {
1307 shader_mask |= 0xf << (i * 4);
1308 }
1309
1310 if (pbs->logicop_enable) {
1311 color_control |= (pbs->logicop_func) << 16;
1312 } else {
1313 color_control |= (0xcc << 16);
1314 }
1315
1316 if (pbs->independent_blend_enable) {
1317 for (i = 0; i < nr_cbufs; i++) {
1318 if (pbs->rt[i].blend_enable) {
1319 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
1320 }
1321 target_mask |= (pbs->rt[i].colormask << (4 * i));
1322 }
1323 } else {
1324 for (i = 0; i < nr_cbufs; i++) {
1325 if (pbs->rt[0].blend_enable) {
1326 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
1327 }
1328 target_mask |= (pbs->rt[0].colormask << (4 * i));
1329 }
1330 }
1331 rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
1332 rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
1333 rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
1334 rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
1335 rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
1336 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
1337 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
1338 rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
1339 rstate->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
1340 rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
1341 rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
1342 rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
1343 if (radeon_state_pm4(rstate)) {
1344 radeon_state_decref(rstate);
1345 return NULL;
1346 }
1347 return rstate;
1348 }
1349
1350 int r600_context_hw_states(struct r600_context *rctx)
1351 {
1352 unsigned i;
1353 int r;
1354 int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
1355 int ucp_nclip = 0;
1356
1357 if (rctx->clip)
1358 ucp_nclip = rctx->clip->state.clip.nr;
1359
1360 /* free previous TODO determine what need to be updated, what
1361 * doesn't
1362 */
1363 //radeon_state_decref(rctx->hw_states.config);
1364 rctx->hw_states.cb_cntl = radeon_state_decref(rctx->hw_states.cb_cntl);
1365 rctx->hw_states.db = radeon_state_decref(rctx->hw_states.db);
1366 rctx->hw_states.rasterizer = radeon_state_decref(rctx->hw_states.rasterizer);
1367 rctx->hw_states.scissor = radeon_state_decref(rctx->hw_states.scissor);
1368 rctx->hw_states.dsa = radeon_state_decref(rctx->hw_states.dsa);
1369 rctx->hw_states.blend = radeon_state_decref(rctx->hw_states.blend);
1370 rctx->hw_states.viewport = radeon_state_decref(rctx->hw_states.viewport);
1371 for (i = 0; i < 8; i++) {
1372 rctx->hw_states.cb[i] = radeon_state_decref(rctx->hw_states.cb[i]);
1373 }
1374 for (i = 0; i < 6; i++) {
1375 rctx->hw_states.ucp[i] = radeon_state_decref(rctx->hw_states.ucp[i]);
1376 }
1377 for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
1378 radeon_state_decref(rctx->hw_states.ps_resource[i]);
1379 rctx->hw_states.ps_resource[i] = NULL;
1380 }
1381 rctx->hw_states.ps_nresource = 0;
1382 for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
1383 radeon_state_decref(rctx->hw_states.ps_sampler[i]);
1384 rctx->hw_states.ps_sampler[i] = NULL;
1385 }
1386 rctx->hw_states.ps_nsampler = 0;
1387
1388 /* build new states */
1389 rctx->hw_states.rasterizer = r600_rasterizer(rctx);
1390 rctx->hw_states.scissor = r600_scissor(rctx);
1391 rctx->hw_states.dsa = r600_dsa(rctx);
1392 rctx->hw_states.blend = r600_blend(rctx);
1393 rctx->hw_states.viewport = r600_viewport(rctx);
1394 for (i = 0; i < nr_cbufs; i++) {
1395 rctx->hw_states.cb[i] = r600_cb(rctx, i);
1396 }
1397 for (i = 0; i < ucp_nclip; i++) {
1398 rctx->hw_states.ucp[i] = r600_ucp(rctx, i);
1399 }
1400 rctx->hw_states.db = r600_db(rctx);
1401 rctx->hw_states.cb_cntl = r600_cb_cntl(rctx);
1402
1403 for (i = 0; i < rctx->ps_nsampler; i++) {
1404 if (rctx->ps_sampler[i]) {
1405 rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
1406 &rctx->ps_sampler[i]->state.sampler,
1407 R600_PS_SAMPLER + i);
1408 }
1409 }
1410 rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
1411 for (i = 0; i < rctx->ps_nsampler_view; i++) {
1412 if (rctx->ps_sampler_view[i]) {
1413 rctx->hw_states.ps_resource[i] = r600_resource(rctx,
1414 &rctx->ps_sampler_view[i]->state.sampler_view,
1415 R600_PS_RESOURCE + i);
1416 }
1417 }
1418 rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
1419
1420 /* bind states */
1421 for (i = 0; i < ucp_nclip; i++) {
1422 r = radeon_draw_set(rctx->draw, rctx->hw_states.ucp[i]);
1423 if (r)
1424 return r;
1425 }
1426 r = radeon_draw_set(rctx->draw, rctx->hw_states.db);
1427 if (r)
1428 return r;
1429 r = radeon_draw_set(rctx->draw, rctx->hw_states.rasterizer);
1430 if (r)
1431 return r;
1432 r = radeon_draw_set(rctx->draw, rctx->hw_states.scissor);
1433 if (r)
1434 return r;
1435 r = radeon_draw_set(rctx->draw, rctx->hw_states.dsa);
1436 if (r)
1437 return r;
1438 r = radeon_draw_set(rctx->draw, rctx->hw_states.blend);
1439 if (r)
1440 return r;
1441 r = radeon_draw_set(rctx->draw, rctx->hw_states.viewport);
1442 if (r)
1443 return r;
1444 for (i = 0; i < nr_cbufs; i++) {
1445 r = radeon_draw_set(rctx->draw, rctx->hw_states.cb[i]);
1446 if (r)
1447 return r;
1448 }
1449 r = radeon_draw_set(rctx->draw, rctx->hw_states.config);
1450 if (r)
1451 return r;
1452 r = radeon_draw_set(rctx->draw, rctx->hw_states.cb_cntl);
1453 if (r)
1454 return r;
1455 for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
1456 if (rctx->hw_states.ps_resource[i]) {
1457 r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_resource[i]);
1458 if (r)
1459 return r;
1460 }
1461 }
1462 for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
1463 if (rctx->hw_states.ps_sampler[i]) {
1464 r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_sampler[i]);
1465 if (r)
1466 return r;
1467 }
1468 }
1469 return 0;
1470 }