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f6a840a9cde9192118e828a46984011e9adaee07
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include "pipe/p_defines.h"
30 #include "pipe/p_state.h"
31 #include "pipe/p_context.h"
32 #include "tgsi/tgsi_scan.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_util.h"
35 #include "util/u_double_list.h"
36 #include "util/u_pack_color.h"
37 #include "util/u_memory.h"
38 #include "util/u_inlines.h"
39 #include "util/u_framebuffer.h"
40 #include "util/u_transfer.h"
41 #include "pipebuffer/pb_buffer.h"
42 #include "r600.h"
43 #include "r600d.h"
44 #include "r600_resource.h"
45 #include "r600_shader.h"
46 #include "r600_pipe.h"
47 #include "r600_formats.h"
48
49 static uint32_t r600_translate_blend_function(int blend_func)
50 {
51 switch (blend_func) {
52 case PIPE_BLEND_ADD:
53 return V_028804_COMB_DST_PLUS_SRC;
54 case PIPE_BLEND_SUBTRACT:
55 return V_028804_COMB_SRC_MINUS_DST;
56 case PIPE_BLEND_REVERSE_SUBTRACT:
57 return V_028804_COMB_DST_MINUS_SRC;
58 case PIPE_BLEND_MIN:
59 return V_028804_COMB_MIN_DST_SRC;
60 case PIPE_BLEND_MAX:
61 return V_028804_COMB_MAX_DST_SRC;
62 default:
63 R600_ERR("Unknown blend function %d\n", blend_func);
64 assert(0);
65 break;
66 }
67 return 0;
68 }
69
70 static uint32_t r600_translate_blend_factor(int blend_fact)
71 {
72 switch (blend_fact) {
73 case PIPE_BLENDFACTOR_ONE:
74 return V_028804_BLEND_ONE;
75 case PIPE_BLENDFACTOR_SRC_COLOR:
76 return V_028804_BLEND_SRC_COLOR;
77 case PIPE_BLENDFACTOR_SRC_ALPHA:
78 return V_028804_BLEND_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_DST_ALPHA:
80 return V_028804_BLEND_DST_ALPHA;
81 case PIPE_BLENDFACTOR_DST_COLOR:
82 return V_028804_BLEND_DST_COLOR;
83 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
84 return V_028804_BLEND_SRC_ALPHA_SATURATE;
85 case PIPE_BLENDFACTOR_CONST_COLOR:
86 return V_028804_BLEND_CONST_COLOR;
87 case PIPE_BLENDFACTOR_CONST_ALPHA:
88 return V_028804_BLEND_CONST_ALPHA;
89 case PIPE_BLENDFACTOR_ZERO:
90 return V_028804_BLEND_ZERO;
91 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
92 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
94 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
95 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
96 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
97 case PIPE_BLENDFACTOR_INV_DST_COLOR:
98 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
99 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
100 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
101 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
102 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
103 case PIPE_BLENDFACTOR_SRC1_COLOR:
104 return V_028804_BLEND_SRC1_COLOR;
105 case PIPE_BLENDFACTOR_SRC1_ALPHA:
106 return V_028804_BLEND_SRC1_ALPHA;
107 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
108 return V_028804_BLEND_INV_SRC1_COLOR;
109 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
110 return V_028804_BLEND_INV_SRC1_ALPHA;
111 default:
112 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
113 assert(0);
114 break;
115 }
116 return 0;
117 }
118
119 static uint32_t r600_translate_stencil_op(int s_op)
120 {
121 switch (s_op) {
122 case PIPE_STENCIL_OP_KEEP:
123 return V_028800_STENCIL_KEEP;
124 case PIPE_STENCIL_OP_ZERO:
125 return V_028800_STENCIL_ZERO;
126 case PIPE_STENCIL_OP_REPLACE:
127 return V_028800_STENCIL_REPLACE;
128 case PIPE_STENCIL_OP_INCR:
129 return V_028800_STENCIL_INCR;
130 case PIPE_STENCIL_OP_DECR:
131 return V_028800_STENCIL_DECR;
132 case PIPE_STENCIL_OP_INCR_WRAP:
133 return V_028800_STENCIL_INCR_WRAP;
134 case PIPE_STENCIL_OP_DECR_WRAP:
135 return V_028800_STENCIL_DECR_WRAP;
136 case PIPE_STENCIL_OP_INVERT:
137 return V_028800_STENCIL_INVERT;
138 default:
139 R600_ERR("Unknown stencil op %d", s_op);
140 assert(0);
141 break;
142 }
143 return 0;
144 }
145
146 static uint32_t r600_translate_fill(uint32_t func)
147 {
148 switch(func) {
149 case PIPE_POLYGON_MODE_FILL:
150 return 2;
151 case PIPE_POLYGON_MODE_LINE:
152 return 1;
153 case PIPE_POLYGON_MODE_POINT:
154 return 0;
155 default:
156 assert(0);
157 return 0;
158 }
159 }
160
161 /* translates straight */
162 static uint32_t r600_translate_ds_func(int func)
163 {
164 return func;
165 }
166
167 static unsigned r600_tex_wrap(unsigned wrap)
168 {
169 switch (wrap) {
170 default:
171 case PIPE_TEX_WRAP_REPEAT:
172 return V_03C000_SQ_TEX_WRAP;
173 case PIPE_TEX_WRAP_CLAMP:
174 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
175 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
176 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
177 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
178 return V_03C000_SQ_TEX_CLAMP_BORDER;
179 case PIPE_TEX_WRAP_MIRROR_REPEAT:
180 return V_03C000_SQ_TEX_MIRROR;
181 case PIPE_TEX_WRAP_MIRROR_CLAMP:
182 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
183 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
184 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
185 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
186 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
187 }
188 }
189
190 static unsigned r600_tex_filter(unsigned filter)
191 {
192 switch (filter) {
193 default:
194 case PIPE_TEX_FILTER_NEAREST:
195 return V_03C000_SQ_TEX_XY_FILTER_POINT;
196 case PIPE_TEX_FILTER_LINEAR:
197 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
198 }
199 }
200
201 static unsigned r600_tex_mipfilter(unsigned filter)
202 {
203 switch (filter) {
204 case PIPE_TEX_MIPFILTER_NEAREST:
205 return V_03C000_SQ_TEX_Z_FILTER_POINT;
206 case PIPE_TEX_MIPFILTER_LINEAR:
207 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
208 default:
209 case PIPE_TEX_MIPFILTER_NONE:
210 return V_03C000_SQ_TEX_Z_FILTER_NONE;
211 }
212 }
213
214 static unsigned r600_tex_compare(unsigned compare)
215 {
216 switch (compare) {
217 default:
218 case PIPE_FUNC_NEVER:
219 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
220 case PIPE_FUNC_LESS:
221 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
222 case PIPE_FUNC_EQUAL:
223 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
224 case PIPE_FUNC_LEQUAL:
225 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
226 case PIPE_FUNC_GREATER:
227 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
228 case PIPE_FUNC_NOTEQUAL:
229 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
230 case PIPE_FUNC_GEQUAL:
231 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
232 case PIPE_FUNC_ALWAYS:
233 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
234 }
235 }
236
237 static unsigned r600_tex_dim(unsigned dim)
238 {
239 switch (dim) {
240 default:
241 case PIPE_TEXTURE_1D:
242 return V_038000_SQ_TEX_DIM_1D;
243 case PIPE_TEXTURE_1D_ARRAY:
244 return V_038000_SQ_TEX_DIM_1D_ARRAY;
245 case PIPE_TEXTURE_2D:
246 case PIPE_TEXTURE_RECT:
247 return V_038000_SQ_TEX_DIM_2D;
248 case PIPE_TEXTURE_2D_ARRAY:
249 return V_038000_SQ_TEX_DIM_2D_ARRAY;
250 case PIPE_TEXTURE_3D:
251 return V_038000_SQ_TEX_DIM_3D;
252 case PIPE_TEXTURE_CUBE:
253 return V_038000_SQ_TEX_DIM_CUBEMAP;
254 }
255 }
256
257 static uint32_t r600_translate_dbformat(enum pipe_format format)
258 {
259 switch (format) {
260 case PIPE_FORMAT_Z16_UNORM:
261 return V_028010_DEPTH_16;
262 case PIPE_FORMAT_Z24X8_UNORM:
263 return V_028010_DEPTH_X8_24;
264 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
265 return V_028010_DEPTH_8_24;
266 case PIPE_FORMAT_Z32_FLOAT:
267 return V_028010_DEPTH_32_FLOAT;
268 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
269 return V_028010_DEPTH_X24_8_32_FLOAT;
270 default:
271 return ~0U;
272 }
273 }
274
275 static uint32_t r600_translate_colorswap(enum pipe_format format)
276 {
277 switch (format) {
278 /* 8-bit buffers. */
279 case PIPE_FORMAT_A8_UNORM:
280 case PIPE_FORMAT_R4A4_UNORM:
281 return V_0280A0_SWAP_ALT_REV;
282 case PIPE_FORMAT_I8_UNORM:
283 case PIPE_FORMAT_L8_UNORM:
284 case PIPE_FORMAT_L8_SRGB:
285 case PIPE_FORMAT_R8_UNORM:
286 case PIPE_FORMAT_R8_SNORM:
287 return V_0280A0_SWAP_STD;
288
289 case PIPE_FORMAT_L4A4_UNORM:
290 case PIPE_FORMAT_A4R4_UNORM:
291 return V_0280A0_SWAP_ALT;
292
293 /* 16-bit buffers. */
294 case PIPE_FORMAT_B5G6R5_UNORM:
295 return V_0280A0_SWAP_STD_REV;
296
297 case PIPE_FORMAT_B5G5R5A1_UNORM:
298 case PIPE_FORMAT_B5G5R5X1_UNORM:
299 return V_0280A0_SWAP_ALT;
300
301 case PIPE_FORMAT_B4G4R4A4_UNORM:
302 case PIPE_FORMAT_B4G4R4X4_UNORM:
303 return V_0280A0_SWAP_ALT;
304
305 case PIPE_FORMAT_Z16_UNORM:
306 return V_0280A0_SWAP_STD;
307
308 case PIPE_FORMAT_L8A8_UNORM:
309 case PIPE_FORMAT_L8A8_SRGB:
310 return V_0280A0_SWAP_ALT;
311 case PIPE_FORMAT_R8G8_UNORM:
312 return V_0280A0_SWAP_STD;
313
314 case PIPE_FORMAT_R16_UNORM:
315 case PIPE_FORMAT_R16_FLOAT:
316 return V_0280A0_SWAP_STD;
317
318 /* 32-bit buffers. */
319
320 case PIPE_FORMAT_A8B8G8R8_SRGB:
321 return V_0280A0_SWAP_STD_REV;
322 case PIPE_FORMAT_B8G8R8A8_SRGB:
323 return V_0280A0_SWAP_ALT;
324
325 case PIPE_FORMAT_B8G8R8A8_UNORM:
326 case PIPE_FORMAT_B8G8R8X8_UNORM:
327 return V_0280A0_SWAP_ALT;
328
329 case PIPE_FORMAT_A8R8G8B8_UNORM:
330 case PIPE_FORMAT_X8R8G8B8_UNORM:
331 return V_0280A0_SWAP_ALT_REV;
332 case PIPE_FORMAT_R8G8B8A8_SNORM:
333 case PIPE_FORMAT_R8G8B8A8_UNORM:
334 case PIPE_FORMAT_R8G8B8X8_UNORM:
335 case PIPE_FORMAT_R8G8B8A8_SSCALED:
336 case PIPE_FORMAT_R8G8B8A8_USCALED:
337 return V_0280A0_SWAP_STD;
338
339 case PIPE_FORMAT_A8B8G8R8_UNORM:
340 case PIPE_FORMAT_X8B8G8R8_UNORM:
341 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
342 return V_0280A0_SWAP_STD_REV;
343
344 case PIPE_FORMAT_Z24X8_UNORM:
345 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
346 return V_0280A0_SWAP_STD;
347
348 case PIPE_FORMAT_X8Z24_UNORM:
349 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
350 return V_0280A0_SWAP_STD;
351
352 case PIPE_FORMAT_R10G10B10A2_UNORM:
353 case PIPE_FORMAT_R10G10B10X2_SNORM:
354 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
355 return V_0280A0_SWAP_STD;
356
357 case PIPE_FORMAT_B10G10R10A2_UNORM:
358 return V_0280A0_SWAP_ALT;
359
360 case PIPE_FORMAT_R11G11B10_FLOAT:
361 case PIPE_FORMAT_R16G16_UNORM:
362 case PIPE_FORMAT_R16G16_FLOAT:
363 case PIPE_FORMAT_R32_FLOAT:
364 case PIPE_FORMAT_Z32_FLOAT:
365 return V_0280A0_SWAP_STD;
366
367 /* 64-bit buffers. */
368 case PIPE_FORMAT_R32G32_FLOAT:
369 case PIPE_FORMAT_R16G16B16A16_UNORM:
370 case PIPE_FORMAT_R16G16B16A16_SNORM:
371 case PIPE_FORMAT_R16G16B16A16_USCALED:
372 case PIPE_FORMAT_R16G16B16A16_SSCALED:
373 case PIPE_FORMAT_R16G16B16A16_FLOAT:
374 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
375
376 /* 128-bit buffers. */
377 case PIPE_FORMAT_R32G32B32A32_FLOAT:
378 case PIPE_FORMAT_R32G32B32A32_SNORM:
379 case PIPE_FORMAT_R32G32B32A32_UNORM:
380 return V_0280A0_SWAP_STD;
381 default:
382 R600_ERR("unsupported colorswap format %d\n", format);
383 return ~0U;
384 }
385 return ~0U;
386 }
387
388 static uint32_t r600_translate_colorformat(enum pipe_format format)
389 {
390 switch (format) {
391 case PIPE_FORMAT_L4A4_UNORM:
392 case PIPE_FORMAT_R4A4_UNORM:
393 case PIPE_FORMAT_A4R4_UNORM:
394 return V_0280A0_COLOR_4_4;
395
396 /* 8-bit buffers. */
397 case PIPE_FORMAT_A8_UNORM:
398 case PIPE_FORMAT_I8_UNORM:
399 case PIPE_FORMAT_L8_UNORM:
400 case PIPE_FORMAT_L8_SRGB:
401 case PIPE_FORMAT_R8_UNORM:
402 case PIPE_FORMAT_R8_SNORM:
403 return V_0280A0_COLOR_8;
404
405 /* 16-bit buffers. */
406 case PIPE_FORMAT_B5G6R5_UNORM:
407 return V_0280A0_COLOR_5_6_5;
408
409 case PIPE_FORMAT_B5G5R5A1_UNORM:
410 case PIPE_FORMAT_B5G5R5X1_UNORM:
411 return V_0280A0_COLOR_1_5_5_5;
412
413 case PIPE_FORMAT_B4G4R4A4_UNORM:
414 case PIPE_FORMAT_B4G4R4X4_UNORM:
415 return V_0280A0_COLOR_4_4_4_4;
416
417 case PIPE_FORMAT_Z16_UNORM:
418 return V_0280A0_COLOR_16;
419
420 case PIPE_FORMAT_L8A8_UNORM:
421 case PIPE_FORMAT_L8A8_SRGB:
422 case PIPE_FORMAT_R8G8_UNORM:
423 return V_0280A0_COLOR_8_8;
424
425 case PIPE_FORMAT_R16_UNORM:
426 return V_0280A0_COLOR_16;
427
428 case PIPE_FORMAT_R16_FLOAT:
429 return V_0280A0_COLOR_16_FLOAT;
430
431 /* 32-bit buffers. */
432 case PIPE_FORMAT_A8B8G8R8_SRGB:
433 case PIPE_FORMAT_A8B8G8R8_UNORM:
434 case PIPE_FORMAT_A8R8G8B8_UNORM:
435 case PIPE_FORMAT_B8G8R8A8_SRGB:
436 case PIPE_FORMAT_B8G8R8A8_UNORM:
437 case PIPE_FORMAT_B8G8R8X8_UNORM:
438 case PIPE_FORMAT_R8G8B8A8_SNORM:
439 case PIPE_FORMAT_R8G8B8A8_UNORM:
440 case PIPE_FORMAT_R8G8B8A8_SSCALED:
441 case PIPE_FORMAT_R8G8B8A8_USCALED:
442 case PIPE_FORMAT_R8G8B8X8_UNORM:
443 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
444 case PIPE_FORMAT_X8B8G8R8_UNORM:
445 case PIPE_FORMAT_X8R8G8B8_UNORM:
446 case PIPE_FORMAT_R8G8B8_UNORM:
447 return V_0280A0_COLOR_8_8_8_8;
448
449 case PIPE_FORMAT_R10G10B10A2_UNORM:
450 case PIPE_FORMAT_R10G10B10X2_SNORM:
451 case PIPE_FORMAT_B10G10R10A2_UNORM:
452 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
453 return V_0280A0_COLOR_2_10_10_10;
454
455 case PIPE_FORMAT_Z24X8_UNORM:
456 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
457 return V_0280A0_COLOR_8_24;
458
459 case PIPE_FORMAT_X8Z24_UNORM:
460 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
461 return V_0280A0_COLOR_24_8;
462
463 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
464 return V_0280A0_COLOR_X24_8_32_FLOAT;
465
466 case PIPE_FORMAT_R32_FLOAT:
467 case PIPE_FORMAT_Z32_FLOAT:
468 return V_0280A0_COLOR_32_FLOAT;
469
470 case PIPE_FORMAT_R16G16_FLOAT:
471 return V_0280A0_COLOR_16_16_FLOAT;
472
473 case PIPE_FORMAT_R16G16_SSCALED:
474 case PIPE_FORMAT_R16G16_UNORM:
475 return V_0280A0_COLOR_16_16;
476
477 case PIPE_FORMAT_R11G11B10_FLOAT:
478 return V_0280A0_COLOR_10_11_11_FLOAT;
479
480 /* 64-bit buffers. */
481 case PIPE_FORMAT_R16G16B16_USCALED:
482 case PIPE_FORMAT_R16G16B16A16_USCALED:
483 case PIPE_FORMAT_R16G16B16_SSCALED:
484 case PIPE_FORMAT_R16G16B16A16_SSCALED:
485 case PIPE_FORMAT_R16G16B16A16_UNORM:
486 case PIPE_FORMAT_R16G16B16A16_SNORM:
487 return V_0280A0_COLOR_16_16_16_16;
488
489 case PIPE_FORMAT_R16G16B16_FLOAT:
490 case PIPE_FORMAT_R16G16B16A16_FLOAT:
491 return V_0280A0_COLOR_16_16_16_16_FLOAT;
492
493 case PIPE_FORMAT_R32G32_FLOAT:
494 return V_0280A0_COLOR_32_32_FLOAT;
495
496 case PIPE_FORMAT_R32G32_USCALED:
497 case PIPE_FORMAT_R32G32_SSCALED:
498 return V_0280A0_COLOR_32_32;
499
500 /* 96-bit buffers. */
501 case PIPE_FORMAT_R32G32B32_FLOAT:
502 return V_0280A0_COLOR_32_32_32_FLOAT;
503
504 /* 128-bit buffers. */
505 case PIPE_FORMAT_R32G32B32A32_FLOAT:
506 return V_0280A0_COLOR_32_32_32_32_FLOAT;
507 case PIPE_FORMAT_R32G32B32A32_SNORM:
508 case PIPE_FORMAT_R32G32B32A32_UNORM:
509 return V_0280A0_COLOR_32_32_32_32;
510
511 /* YUV buffers. */
512 case PIPE_FORMAT_UYVY:
513 case PIPE_FORMAT_YUYV:
514 default:
515 return ~0U; /* Unsupported. */
516 }
517 }
518
519 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
520 {
521 if (R600_BIG_ENDIAN) {
522 switch(colorformat) {
523 case V_0280A0_COLOR_4_4:
524 return ENDIAN_NONE;
525
526 /* 8-bit buffers. */
527 case V_0280A0_COLOR_8:
528 return ENDIAN_NONE;
529
530 /* 16-bit buffers. */
531 case V_0280A0_COLOR_5_6_5:
532 case V_0280A0_COLOR_1_5_5_5:
533 case V_0280A0_COLOR_4_4_4_4:
534 case V_0280A0_COLOR_16:
535 case V_0280A0_COLOR_8_8:
536 return ENDIAN_8IN16;
537
538 /* 32-bit buffers. */
539 case V_0280A0_COLOR_8_8_8_8:
540 case V_0280A0_COLOR_2_10_10_10:
541 case V_0280A0_COLOR_8_24:
542 case V_0280A0_COLOR_24_8:
543 case V_0280A0_COLOR_32_FLOAT:
544 case V_0280A0_COLOR_16_16_FLOAT:
545 case V_0280A0_COLOR_16_16:
546 return ENDIAN_8IN32;
547
548 /* 64-bit buffers. */
549 case V_0280A0_COLOR_16_16_16_16:
550 case V_0280A0_COLOR_16_16_16_16_FLOAT:
551 return ENDIAN_8IN16;
552
553 case V_0280A0_COLOR_32_32_FLOAT:
554 case V_0280A0_COLOR_32_32:
555 case V_0280A0_COLOR_X24_8_32_FLOAT:
556 return ENDIAN_8IN32;
557
558 /* 128-bit buffers. */
559 case V_0280A0_COLOR_32_32_32_FLOAT:
560 case V_0280A0_COLOR_32_32_32_32_FLOAT:
561 case V_0280A0_COLOR_32_32_32_32:
562 return ENDIAN_8IN32;
563 default:
564 return ENDIAN_NONE; /* Unsupported. */
565 }
566 } else {
567 return ENDIAN_NONE;
568 }
569 }
570
571 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
572 {
573 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
574 }
575
576 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
577 {
578 return r600_translate_colorformat(format) != ~0U &&
579 r600_translate_colorswap(format) != ~0U;
580 }
581
582 static bool r600_is_zs_format_supported(enum pipe_format format)
583 {
584 return r600_translate_dbformat(format) != ~0U;
585 }
586
587 boolean r600_is_format_supported(struct pipe_screen *screen,
588 enum pipe_format format,
589 enum pipe_texture_target target,
590 unsigned sample_count,
591 unsigned usage)
592 {
593 unsigned retval = 0;
594
595 if (target >= PIPE_MAX_TEXTURE_TYPES) {
596 R600_ERR("r600: unsupported texture type %d\n", target);
597 return FALSE;
598 }
599
600 if (!util_format_is_supported(format, usage))
601 return FALSE;
602
603 /* Multisample */
604 if (sample_count > 1)
605 return FALSE;
606
607 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
608 r600_is_sampler_format_supported(screen, format)) {
609 retval |= PIPE_BIND_SAMPLER_VIEW;
610 }
611
612 if ((usage & (PIPE_BIND_RENDER_TARGET |
613 PIPE_BIND_DISPLAY_TARGET |
614 PIPE_BIND_SCANOUT |
615 PIPE_BIND_SHARED)) &&
616 r600_is_colorbuffer_format_supported(format)) {
617 retval |= usage &
618 (PIPE_BIND_RENDER_TARGET |
619 PIPE_BIND_DISPLAY_TARGET |
620 PIPE_BIND_SCANOUT |
621 PIPE_BIND_SHARED);
622 }
623
624 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
625 r600_is_zs_format_supported(format)) {
626 retval |= PIPE_BIND_DEPTH_STENCIL;
627 }
628
629 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
630 r600_is_vertex_format_supported(format)) {
631 retval |= PIPE_BIND_VERTEX_BUFFER;
632 }
633
634 if (usage & PIPE_BIND_TRANSFER_READ)
635 retval |= PIPE_BIND_TRANSFER_READ;
636 if (usage & PIPE_BIND_TRANSFER_WRITE)
637 retval |= PIPE_BIND_TRANSFER_WRITE;
638
639 return retval == usage;
640 }
641
642 void r600_polygon_offset_update(struct r600_pipe_context *rctx)
643 {
644 struct r600_pipe_state state;
645
646 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
647 state.nregs = 0;
648 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
649 float offset_units = rctx->rasterizer->offset_units;
650 unsigned offset_db_fmt_cntl = 0, depth;
651
652 switch (rctx->framebuffer.zsbuf->texture->format) {
653 case PIPE_FORMAT_Z24X8_UNORM:
654 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
655 depth = -24;
656 offset_units *= 2.0f;
657 break;
658 case PIPE_FORMAT_Z32_FLOAT:
659 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
660 depth = -23;
661 offset_units *= 1.0f;
662 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
663 break;
664 case PIPE_FORMAT_Z16_UNORM:
665 depth = -16;
666 offset_units *= 4.0f;
667 break;
668 default:
669 return;
670 }
671 /* FIXME some of those reg can be computed with cso */
672 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
673 r600_pipe_state_add_reg(&state,
674 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
675 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
676 r600_pipe_state_add_reg(&state,
677 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
678 fui(offset_units), 0xFFFFFFFF, NULL, 0);
679 r600_pipe_state_add_reg(&state,
680 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
681 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
682 r600_pipe_state_add_reg(&state,
683 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
684 fui(offset_units), 0xFFFFFFFF, NULL, 0);
685 r600_pipe_state_add_reg(&state,
686 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
687 offset_db_fmt_cntl, 0xFFFFFFFF, NULL, 0);
688 r600_context_pipe_state_set(&rctx->ctx, &state);
689 }
690 }
691
692 static void r600_set_blend_color(struct pipe_context *ctx,
693 const struct pipe_blend_color *state)
694 {
695 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
696 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
697
698 if (rstate == NULL)
699 return;
700
701 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
702 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL, 0);
703 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL, 0);
704 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL, 0);
705 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL, 0);
706 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
707 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
708 r600_context_pipe_state_set(&rctx->ctx, rstate);
709 }
710
711 static void *r600_create_blend_state(struct pipe_context *ctx,
712 const struct pipe_blend_state *state)
713 {
714 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
715 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
716 struct r600_pipe_state *rstate;
717 u32 color_control = 0, target_mask;
718
719 if (blend == NULL) {
720 return NULL;
721 }
722 rstate = &blend->rstate;
723
724 rstate->id = R600_PIPE_STATE_BLEND;
725
726 target_mask = 0;
727
728 /* R600 does not support per-MRT blends */
729 if (rctx->family > CHIP_R600)
730 color_control |= S_028808_PER_MRT_BLEND(1);
731 if (state->logicop_enable) {
732 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
733 } else {
734 color_control |= (0xcc << 16);
735 }
736 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
737 if (state->independent_blend_enable) {
738 for (int i = 0; i < 8; i++) {
739 if (state->rt[i].blend_enable) {
740 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
741 }
742 target_mask |= (state->rt[i].colormask << (4 * i));
743 }
744 } else {
745 for (int i = 0; i < 8; i++) {
746 if (state->rt[0].blend_enable) {
747 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
748 }
749 target_mask |= (state->rt[0].colormask << (4 * i));
750 }
751 }
752 blend->cb_target_mask = target_mask;
753 /* MULTIWRITE_ENABLE is controlled by r600_pipe_shader_ps(). */
754 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
755 color_control, 0xFFFFFFFD, NULL, 0);
756
757 for (int i = 0; i < 8; i++) {
758 /* state->rt entries > 0 only written if independent blending */
759 const int j = state->independent_blend_enable ? i : 0;
760
761 unsigned eqRGB = state->rt[j].rgb_func;
762 unsigned srcRGB = state->rt[j].rgb_src_factor;
763 unsigned dstRGB = state->rt[j].rgb_dst_factor;
764
765 unsigned eqA = state->rt[j].alpha_func;
766 unsigned srcA = state->rt[j].alpha_src_factor;
767 unsigned dstA = state->rt[j].alpha_dst_factor;
768 uint32_t bc = 0;
769
770 if (!state->rt[j].blend_enable)
771 continue;
772
773 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
774 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
775 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
776
777 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
778 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
779 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
780 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
781 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
782 }
783
784 /* R600 does not support per-MRT blends */
785 if (rctx->family > CHIP_R600)
786 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL, 0);
787 if (i == 0)
788 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL, 0);
789 }
790 return rstate;
791 }
792
793 static void *r600_create_dsa_state(struct pipe_context *ctx,
794 const struct pipe_depth_stencil_alpha_state *state)
795 {
796 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
797 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
798 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
799 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
800 struct r600_pipe_state *rstate;
801
802 if (dsa == NULL) {
803 return NULL;
804 }
805
806 rstate = &dsa->rstate;
807
808 rstate->id = R600_PIPE_STATE_DSA;
809 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
810 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
811 stencil_ref_mask = 0;
812 stencil_ref_mask_bf = 0;
813 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
814 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
815 S_028800_ZFUNC(state->depth.func);
816
817 /* stencil */
818 if (state->stencil[0].enabled) {
819 db_depth_control |= S_028800_STENCIL_ENABLE(1);
820 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
821 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
822 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
823 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
824
825
826 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
827 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
828 if (state->stencil[1].enabled) {
829 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
830 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
831 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
832 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
833 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
834 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
835 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
836 }
837 }
838
839 /* alpha */
840 alpha_test_control = 0;
841 alpha_ref = 0;
842 if (state->alpha.enabled) {
843 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
844 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
845 alpha_ref = fui(state->alpha.ref_value);
846 }
847 dsa->alpha_ref = alpha_ref;
848
849 /* misc */
850 db_render_control = 0;
851 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
852 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
853 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
854 /* TODO db_render_override depends on query */
855 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL, 0);
856 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL, 0);
857 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL, 0);
858 r600_pipe_state_add_reg(rstate,
859 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
860 0xFFFFFFFF & C_028430_STENCILREF, NULL, 0);
861 r600_pipe_state_add_reg(rstate,
862 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
863 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL, 0);
864 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL, 0);
865 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL, 0);
866 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
867 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL, 0);
868 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
869 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
870 * r600_pipe_shader_ps().*/
871 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL, 0);
872 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL, 0);
873 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL, 0);
874 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL, 0);
875 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL, 0);
876 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL, 0);
877
878 return rstate;
879 }
880
881 static void *r600_create_rs_state(struct pipe_context *ctx,
882 const struct pipe_rasterizer_state *state)
883 {
884 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
885 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
886 struct r600_pipe_state *rstate;
887 unsigned tmp;
888 unsigned prov_vtx = 1, polygon_dual_mode;
889 unsigned clip_rule;
890
891 if (rs == NULL) {
892 return NULL;
893 }
894
895 rstate = &rs->rstate;
896 rs->clamp_vertex_color = state->clamp_vertex_color;
897 rs->clamp_fragment_color = state->clamp_fragment_color;
898 rs->flatshade = state->flatshade;
899 rs->sprite_coord_enable = state->sprite_coord_enable;
900
901 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
902 /* offset */
903 rs->offset_units = state->offset_units;
904 rs->offset_scale = state->offset_scale * 12.0f;
905
906 rstate->id = R600_PIPE_STATE_RASTERIZER;
907 if (state->flatshade_first)
908 prov_vtx = 0;
909 tmp = S_0286D4_FLAT_SHADE_ENA(1);
910 if (state->sprite_coord_enable) {
911 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
912 S_0286D4_PNT_SPRITE_OVRD_X(2) |
913 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
914 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
915 S_0286D4_PNT_SPRITE_OVRD_W(1);
916 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
917 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
918 }
919 }
920 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL, 0);
921
922 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
923 state->fill_back != PIPE_POLYGON_MODE_FILL);
924 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
925 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
926 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
927 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
928 S_028814_FACE(!state->front_ccw) |
929 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
930 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
931 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
932 S_028814_POLY_MODE(polygon_dual_mode) |
933 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
934 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL, 0);
935 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
936 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
937 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL, 0);
938 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
939 /* point size 12.4 fixed point */
940 tmp = (unsigned)(state->point_size * 8.0);
941 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
942 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL, 0);
943
944 tmp = (unsigned)state->line_width * 8;
945 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
946
947 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL, 0);
948 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
949 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL, 0);
950
951 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
952 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
953 0xFFFFFFFF, NULL, 0);
954
955 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
956 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
957 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
958 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
959 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL, 0);
960 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL, 0);
961
962 return rstate;
963 }
964
965 static void *r600_create_sampler_state(struct pipe_context *ctx,
966 const struct pipe_sampler_state *state)
967 {
968 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
969 struct r600_pipe_state *rstate;
970 union util_color uc;
971 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
972
973 if (ss == NULL) {
974 return NULL;
975 }
976
977 ss->seamless_cube_map = state->seamless_cube_map;
978 rstate = &ss->rstate;
979 rstate->id = R600_PIPE_STATE_SAMPLER;
980 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
981 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
982 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
983 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
984 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
985 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
986 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
987 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
988 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
989 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
990 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL, 0);
991 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
992 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
993 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
994 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL, 0);
995 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL, 0);
996 if (uc.ui) {
997 r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL, 0);
998 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL, 0);
999 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL, 0);
1000 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL, 0);
1001 }
1002 return rstate;
1003 }
1004
1005 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
1006 struct pipe_resource *texture,
1007 const struct pipe_sampler_view *state)
1008 {
1009 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1010 struct r600_pipe_resource_state *rstate;
1011 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1012 struct r600_resource *rbuffer;
1013 unsigned format, endian;
1014 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1015 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1016 struct r600_bo *bo[2];
1017 unsigned width, height, depth, offset_level, last_level;
1018
1019 if (view == NULL)
1020 return NULL;
1021 rstate = &view->state;
1022
1023 /* initialize base object */
1024 view->base = *state;
1025 view->base.texture = NULL;
1026 pipe_reference(NULL, &texture->reference);
1027 view->base.texture = texture;
1028 view->base.reference.count = 1;
1029 view->base.context = ctx;
1030
1031 swizzle[0] = state->swizzle_r;
1032 swizzle[1] = state->swizzle_g;
1033 swizzle[2] = state->swizzle_b;
1034 swizzle[3] = state->swizzle_a;
1035
1036 format = r600_translate_texformat(ctx->screen, state->format,
1037 swizzle,
1038 &word4, &yuv_format);
1039 if (format == ~0) {
1040 format = 0;
1041 }
1042
1043 if (tmp->depth && !tmp->is_flushing_texture) {
1044 r600_texture_depth_flush(ctx, texture, TRUE);
1045 tmp = tmp->flushed_depth_texture;
1046 }
1047
1048 endian = r600_colorformat_endian_swap(format);
1049
1050 if (tmp->force_int_type) {
1051 word4 &= C_038010_NUM_FORMAT_ALL;
1052 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1053 }
1054
1055 rbuffer = &tmp->resource;
1056 bo[0] = rbuffer->bo;
1057 bo[1] = rbuffer->bo;
1058
1059 offset_level = state->u.tex.first_level;
1060 last_level = state->u.tex.last_level - offset_level;
1061 width = u_minify(texture->width0, offset_level);
1062 height = u_minify(texture->height0, offset_level);
1063 depth = u_minify(texture->depth0, offset_level);
1064
1065 pitch = align(tmp->pitch_in_blocks[offset_level] *
1066 util_format_get_blockwidth(state->format), 8);
1067 array_mode = tmp->array_mode[offset_level];
1068 tile_type = tmp->tile_type;
1069
1070 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1071 height = 1;
1072 depth = texture->array_size;
1073 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1074 depth = texture->array_size;
1075 }
1076
1077 rstate->bo[0] = bo[0];
1078 rstate->bo[1] = bo[1];
1079 rstate->bo_usage[0] = RADEON_USAGE_READ;
1080 rstate->bo_usage[1] = RADEON_USAGE_READ;
1081
1082 rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1083 S_038000_TILE_MODE(array_mode) |
1084 S_038000_TILE_TYPE(tile_type) |
1085 S_038000_PITCH((pitch / 8) - 1) |
1086 S_038000_TEX_WIDTH(width - 1));
1087 rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
1088 S_038004_TEX_DEPTH(depth - 1) |
1089 S_038004_DATA_FORMAT(format));
1090 rstate->val[2] = tmp->offset[offset_level] >> 8;
1091 rstate->val[3] = tmp->offset[offset_level+1] >> 8;
1092 rstate->val[4] = (word4 |
1093 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1094 S_038010_REQUEST_SIZE(1) |
1095 S_038010_ENDIAN_SWAP(endian) |
1096 S_038010_BASE_LEVEL(0));
1097 rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
1098 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1099 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1100 rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1101 S_038018_MAX_ANISO(4 /* max 16 samples */));
1102
1103 return &view->base;
1104 }
1105
1106 static void r600_set_sampler_views(struct r600_pipe_context *rctx,
1107 struct r600_textures_info *dst,
1108 unsigned count,
1109 struct pipe_sampler_view **views,
1110 void (*set_resource)(struct r600_context*, struct r600_pipe_resource_state*, unsigned))
1111 {
1112 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
1113 unsigned i;
1114
1115 for (i = 0; i < count; i++) {
1116 if (rviews[i]) {
1117 if (((struct r600_resource_texture *)rviews[i]->base.texture)->depth)
1118 rctx->have_depth_texture = true;
1119
1120 /* Changing from array to non-arrays textures and vice versa requires updating TEX_ARRAY_OVERRIDE. */
1121 if ((rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1122 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i])
1123 dst->samplers_dirty = true;
1124
1125 set_resource(&rctx->ctx, &rviews[i]->state, i + R600_MAX_CONST_BUFFERS);
1126 } else {
1127 set_resource(&rctx->ctx, NULL, i + R600_MAX_CONST_BUFFERS);
1128 }
1129
1130 pipe_sampler_view_reference(
1131 (struct pipe_sampler_view **)&dst->views[i],
1132 views[i]);
1133 }
1134
1135 for (i = count; i < dst->n_views; i++) {
1136 if (dst->views[i]) {
1137 set_resource(&rctx->ctx, NULL, i + R600_MAX_CONST_BUFFERS);
1138 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], NULL);
1139 }
1140 }
1141
1142 dst->n_views = count;
1143 }
1144
1145 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1146 struct pipe_sampler_view **views)
1147 {
1148 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1149 r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views,
1150 r600_context_pipe_state_set_vs_resource);
1151 }
1152
1153 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1154 struct pipe_sampler_view **views)
1155 {
1156 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1157 r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views,
1158 r600_context_pipe_state_set_ps_resource);
1159 }
1160
1161 static void r600_set_seamless_cubemap(struct r600_pipe_context *rctx, boolean enable)
1162 {
1163 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1164 if (rstate == NULL)
1165 return;
1166
1167 rstate->id = R600_PIPE_STATE_SEAMLESS_CUBEMAP;
1168 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1169 (enable ? 0 : S_009508_DISABLE_CUBE_WRAP(1)),
1170 1, NULL, 0);
1171
1172 free(rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP]);
1173 rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP] = rstate;
1174 r600_context_pipe_state_set(&rctx->ctx, rstate);
1175 }
1176
1177 static void r600_bind_samplers(struct r600_pipe_context *rctx,
1178 struct r600_textures_info *dst,
1179 unsigned count, void **states)
1180 {
1181 memcpy(dst->samplers, states, sizeof(void*) * count);
1182 dst->n_samplers = count;
1183 dst->samplers_dirty = true;
1184 }
1185
1186 static void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states)
1187 {
1188 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1189 r600_bind_samplers(rctx, &rctx->vs_samplers, count, states);
1190 }
1191
1192 static void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states)
1193 {
1194 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1195 r600_bind_samplers(rctx, &rctx->ps_samplers, count, states);
1196 }
1197
1198 static void r600_update_samplers(struct r600_pipe_context *rctx,
1199 struct r600_textures_info *tex,
1200 void (*set_sampler)(struct r600_context*, struct r600_pipe_state*, unsigned))
1201 {
1202 unsigned i;
1203
1204 if (tex->samplers_dirty) {
1205 int seamless = -1;
1206 for (i = 0; i < tex->n_samplers; i++) {
1207 if (!tex->samplers[i])
1208 continue;
1209
1210 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1211 * filtering between layers.
1212 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. */
1213 if (tex->views[i]) {
1214 if (tex->views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1215 tex->views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
1216 tex->samplers[i]->rstate.regs[0].value |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1217 tex->is_array_sampler[i] = true;
1218 } else {
1219 tex->samplers[i]->rstate.regs[0].value &= C_03C000_TEX_ARRAY_OVERRIDE;
1220 tex->is_array_sampler[i] = false;
1221 }
1222 }
1223
1224 set_sampler(&rctx->ctx, &tex->samplers[i]->rstate, i);
1225
1226 if (tex->samplers[i])
1227 seamless = tex->samplers[i]->seamless_cube_map;
1228 }
1229
1230 if (seamless != -1)
1231 r600_set_seamless_cubemap(rctx, seamless);
1232
1233 tex->samplers_dirty = false;
1234 }
1235 }
1236
1237 void r600_update_sampler_states(struct r600_pipe_context *rctx)
1238 {
1239 r600_update_samplers(rctx, &rctx->vs_samplers,
1240 r600_context_pipe_state_set_vs_sampler);
1241 r600_update_samplers(rctx, &rctx->ps_samplers,
1242 r600_context_pipe_state_set_ps_sampler);
1243 }
1244
1245 static void r600_set_clip_state(struct pipe_context *ctx,
1246 const struct pipe_clip_state *state)
1247 {
1248 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1249 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1250
1251 if (rstate == NULL)
1252 return;
1253
1254 rctx->clip = *state;
1255 rstate->id = R600_PIPE_STATE_CLIP;
1256 for (int i = 0; i < state->nr; i++) {
1257 r600_pipe_state_add_reg(rstate,
1258 R_028E20_PA_CL_UCP0_X + i * 16,
1259 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL, 0);
1260 r600_pipe_state_add_reg(rstate,
1261 R_028E24_PA_CL_UCP0_Y + i * 16,
1262 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL, 0);
1263 r600_pipe_state_add_reg(rstate,
1264 R_028E28_PA_CL_UCP0_Z + i * 16,
1265 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL, 0);
1266 r600_pipe_state_add_reg(rstate,
1267 R_028E2C_PA_CL_UCP0_W + i * 16,
1268 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL, 0);
1269 }
1270 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
1271 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
1272 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
1273 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL, 0);
1274
1275 free(rctx->states[R600_PIPE_STATE_CLIP]);
1276 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1277 r600_context_pipe_state_set(&rctx->ctx, rstate);
1278 }
1279
1280 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1281 const struct pipe_poly_stipple *state)
1282 {
1283 }
1284
1285 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1286 {
1287 }
1288
1289 static void r600_set_scissor_state(struct pipe_context *ctx,
1290 const struct pipe_scissor_state *state)
1291 {
1292 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1293 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1294 u32 tl, br;
1295
1296 if (rstate == NULL)
1297 return;
1298
1299 rstate->id = R600_PIPE_STATE_SCISSOR;
1300 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1301 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1302 r600_pipe_state_add_reg(rstate,
1303 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1304 0xFFFFFFFF, NULL, 0);
1305 r600_pipe_state_add_reg(rstate,
1306 R_028214_PA_SC_CLIPRECT_0_BR, br,
1307 0xFFFFFFFF, NULL, 0);
1308 r600_pipe_state_add_reg(rstate,
1309 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1310 0xFFFFFFFF, NULL, 0);
1311 r600_pipe_state_add_reg(rstate,
1312 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1313 0xFFFFFFFF, NULL, 0);
1314 r600_pipe_state_add_reg(rstate,
1315 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1316 0xFFFFFFFF, NULL, 0);
1317 r600_pipe_state_add_reg(rstate,
1318 R_028224_PA_SC_CLIPRECT_2_BR, br,
1319 0xFFFFFFFF, NULL, 0);
1320 r600_pipe_state_add_reg(rstate,
1321 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1322 0xFFFFFFFF, NULL, 0);
1323 r600_pipe_state_add_reg(rstate,
1324 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1325 0xFFFFFFFF, NULL, 0);
1326
1327 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1328 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1329 r600_context_pipe_state_set(&rctx->ctx, rstate);
1330 }
1331
1332 static void r600_set_stencil_ref(struct pipe_context *ctx,
1333 const struct pipe_stencil_ref *state)
1334 {
1335 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1336 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1337 u32 tmp;
1338
1339 if (rstate == NULL)
1340 return;
1341
1342 rctx->stencil_ref = *state;
1343 rstate->id = R600_PIPE_STATE_STENCIL_REF;
1344 tmp = S_028430_STENCILREF(state->ref_value[0]);
1345 r600_pipe_state_add_reg(rstate,
1346 R_028430_DB_STENCILREFMASK, tmp,
1347 ~C_028430_STENCILREF, NULL, 0);
1348 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
1349 r600_pipe_state_add_reg(rstate,
1350 R_028434_DB_STENCILREFMASK_BF, tmp,
1351 ~C_028434_STENCILREF_BF, NULL, 0);
1352
1353 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
1354 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
1355 r600_context_pipe_state_set(&rctx->ctx, rstate);
1356 }
1357
1358 static void r600_set_viewport_state(struct pipe_context *ctx,
1359 const struct pipe_viewport_state *state)
1360 {
1361 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1362 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1363
1364 if (rstate == NULL)
1365 return;
1366
1367 rctx->viewport = *state;
1368 rstate->id = R600_PIPE_STATE_VIEWPORT;
1369 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL, 0);
1370 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1371 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL, 0);
1372 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL, 0);
1373 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL, 0);
1374 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL, 0);
1375 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL, 0);
1376 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL, 0);
1377 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL, 0);
1378
1379 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1380 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1381 r600_context_pipe_state_set(&rctx->ctx, rstate);
1382 }
1383
1384 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1385 const struct pipe_framebuffer_state *state, int cb)
1386 {
1387 struct r600_resource_texture *rtex;
1388 struct r600_resource *rbuffer;
1389 struct r600_surface *surf;
1390 unsigned level = state->cbufs[cb]->u.tex.level;
1391 unsigned pitch, slice;
1392 unsigned color_info;
1393 unsigned format, swap, ntype, endian;
1394 unsigned offset;
1395 const struct util_format_description *desc;
1396 struct r600_bo *bo[3];
1397 int i;
1398
1399 surf = (struct r600_surface *)state->cbufs[cb];
1400 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1401
1402 if (rtex->depth)
1403 rctx->have_depth_fb = TRUE;
1404
1405 if (rtex->depth && !rtex->is_flushing_texture) {
1406 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1407 rtex = rtex->flushed_depth_texture;
1408 }
1409
1410 rbuffer = &rtex->resource;
1411 bo[0] = rbuffer->bo;
1412 bo[1] = rbuffer->bo;
1413 bo[2] = rbuffer->bo;
1414
1415 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1416 offset = r600_texture_get_offset(rtex,
1417 level, state->cbufs[cb]->u.tex.first_layer);
1418 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1419 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1420 desc = util_format_description(surf->base.format);
1421
1422 for (i = 0; i < 4; i++) {
1423 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1424 break;
1425 }
1426 }
1427 ntype = V_0280A0_NUMBER_UNORM;
1428 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1429 ntype = V_0280A0_NUMBER_SRGB;
1430 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED)
1431 ntype = V_0280A0_NUMBER_SNORM;
1432
1433 format = r600_translate_colorformat(surf->base.format);
1434 swap = r600_translate_colorswap(surf->base.format);
1435 if(rbuffer->b.b.b.usage == PIPE_USAGE_STAGING) {
1436 endian = ENDIAN_NONE;
1437 } else {
1438 endian = r600_colorformat_endian_swap(format);
1439 }
1440
1441 /* disable when gallium grows int textures */
1442 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
1443 ntype = V_0280A0_NUMBER_UINT;
1444
1445 color_info = S_0280A0_FORMAT(format) |
1446 S_0280A0_COMP_SWAP(swap) |
1447 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
1448 S_0280A0_BLEND_CLAMP(1) |
1449 S_0280A0_NUMBER_TYPE(ntype) |
1450 S_0280A0_ENDIAN(endian);
1451
1452 /* EXPORT_NORM is an optimzation that can be enabled for better
1453 * performance in certain cases
1454 */
1455 if (rctx->chip_class == R600) {
1456 /* EXPORT_NORM can be enabled if:
1457 * - 11-bit or smaller UNORM/SNORM/SRGB
1458 * - BLEND_CLAMP is enabled
1459 * - BLEND_FLOAT32 is disabled
1460 */
1461 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1462 (desc->channel[i].size < 12 &&
1463 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1464 ntype != V_0280A0_NUMBER_UINT &&
1465 ntype != V_0280A0_NUMBER_SINT) &&
1466 G_0280A0_BLEND_CLAMP(color_info) &&
1467 !G_0280A0_BLEND_FLOAT32(color_info))
1468 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1469 } else {
1470 /* EXPORT_NORM can be enabled if:
1471 * - 11-bit or smaller UNORM/SNORM/SRGB
1472 * - 16-bit or smaller FLOAT
1473 */
1474 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1475 ((desc->channel[i].size < 12 &&
1476 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1477 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1478 (desc->channel[i].size < 17 &&
1479 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT)))
1480 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1481 }
1482
1483 r600_pipe_state_add_reg(rstate,
1484 R_028040_CB_COLOR0_BASE + cb * 4,
1485 offset >> 8, 0xFFFFFFFF, bo[0], RADEON_USAGE_READWRITE);
1486 r600_pipe_state_add_reg(rstate,
1487 R_0280A0_CB_COLOR0_INFO + cb * 4,
1488 color_info, 0xFFFFFFFF, bo[0], RADEON_USAGE_READWRITE);
1489 r600_pipe_state_add_reg(rstate,
1490 R_028060_CB_COLOR0_SIZE + cb * 4,
1491 S_028060_PITCH_TILE_MAX(pitch) |
1492 S_028060_SLICE_TILE_MAX(slice),
1493 0xFFFFFFFF, NULL, 0);
1494 r600_pipe_state_add_reg(rstate,
1495 R_028080_CB_COLOR0_VIEW + cb * 4,
1496 0x00000000, 0xFFFFFFFF, NULL, 0);
1497 r600_pipe_state_add_reg(rstate,
1498 R_0280E0_CB_COLOR0_FRAG + cb * 4,
1499 0, 0xFFFFFFFF, bo[1], RADEON_USAGE_READWRITE);
1500 r600_pipe_state_add_reg(rstate,
1501 R_0280C0_CB_COLOR0_TILE + cb * 4,
1502 0, 0xFFFFFFFF, bo[2], RADEON_USAGE_READWRITE);
1503 r600_pipe_state_add_reg(rstate,
1504 R_028100_CB_COLOR0_MASK + cb * 4,
1505 0x00000000, 0xFFFFFFFF, NULL, 0);
1506 }
1507
1508 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1509 const struct pipe_framebuffer_state *state)
1510 {
1511 struct r600_resource_texture *rtex;
1512 struct r600_resource *rbuffer;
1513 struct r600_surface *surf;
1514 unsigned level;
1515 unsigned pitch, slice, format;
1516 unsigned offset;
1517
1518 if (state->zsbuf == NULL)
1519 return;
1520
1521 level = state->zsbuf->u.tex.level;
1522
1523 surf = (struct r600_surface *)state->zsbuf;
1524 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1525
1526 rbuffer = &rtex->resource;
1527
1528 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1529 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
1530 level, state->zsbuf->u.tex.first_layer);
1531 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1532 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1533 format = r600_translate_dbformat(state->zsbuf->texture->format);
1534
1535 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
1536 offset >> 8, 0xFFFFFFFF, rbuffer->bo, RADEON_USAGE_READWRITE);
1537 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1538 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1539 0xFFFFFFFF, NULL, 0);
1540 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL, 0);
1541 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
1542 S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format),
1543 0xFFFFFFFF, rbuffer->bo, RADEON_USAGE_READWRITE);
1544 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1545 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL, 0);
1546 }
1547
1548 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1549 const struct pipe_framebuffer_state *state)
1550 {
1551 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1552 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1553 u32 shader_mask, tl, br, shader_control, target_mask;
1554
1555 if (rstate == NULL)
1556 return;
1557
1558 r600_context_flush_dest_caches(&rctx->ctx);
1559 rctx->ctx.num_dest_buffers = state->nr_cbufs;
1560
1561 /* unreference old buffer and reference new one */
1562 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1563
1564 util_copy_framebuffer_state(&rctx->framebuffer, state);
1565
1566 /* build states */
1567 rctx->have_depth_fb = 0;
1568 for (int i = 0; i < state->nr_cbufs; i++) {
1569 r600_cb(rctx, rstate, state, i);
1570 }
1571 if (state->zsbuf) {
1572 r600_db(rctx, rstate, state);
1573 rctx->ctx.num_dest_buffers++;
1574 }
1575
1576 target_mask = 0x00000000;
1577 target_mask = 0xFFFFFFFF;
1578 shader_mask = 0;
1579 shader_control = 0;
1580 for (int i = 0; i < state->nr_cbufs; i++) {
1581 target_mask ^= 0xf << (i * 4);
1582 shader_mask |= 0xf << (i * 4);
1583 shader_control |= 1 << i;
1584 }
1585 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1586 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1587
1588 r600_pipe_state_add_reg(rstate,
1589 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1590 0xFFFFFFFF, NULL, 0);
1591 r600_pipe_state_add_reg(rstate,
1592 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1593 0xFFFFFFFF, NULL, 0);
1594 r600_pipe_state_add_reg(rstate,
1595 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1596 0xFFFFFFFF, NULL, 0);
1597 r600_pipe_state_add_reg(rstate,
1598 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1599 0xFFFFFFFF, NULL, 0);
1600 r600_pipe_state_add_reg(rstate,
1601 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1602 0xFFFFFFFF, NULL, 0);
1603 r600_pipe_state_add_reg(rstate,
1604 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1605 0xFFFFFFFF, NULL, 0);
1606 r600_pipe_state_add_reg(rstate,
1607 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1608 0xFFFFFFFF, NULL, 0);
1609 r600_pipe_state_add_reg(rstate,
1610 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1611 0xFFFFFFFF, NULL, 0);
1612 r600_pipe_state_add_reg(rstate,
1613 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1614 0xFFFFFFFF, NULL, 0);
1615 if (rctx->chip_class >= R700) {
1616 r600_pipe_state_add_reg(rstate,
1617 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1618 0xFFFFFFFF, NULL, 0);
1619 }
1620
1621 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1622 shader_control, 0xFFFFFFFF, NULL, 0);
1623 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1624 0x00000000, target_mask, NULL, 0);
1625 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1626 shader_mask, 0xFFFFFFFF, NULL, 0);
1627 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1628 0x00000000, 0xFFFFFFFF, NULL, 0);
1629 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1630 0x00000000, 0xFFFFFFFF, NULL, 0);
1631 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1632 0x00000000, 0xFFFFFFFF, NULL, 0);
1633 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1634 0x01000000, 0xFFFFFFFF, NULL, 0);
1635 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1636 0x00000000, 0xFFFFFFFF, NULL, 0);
1637 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1638 0x000000FF, 0xFFFFFFFF, NULL, 0);
1639 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1640 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
1641 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1642 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
1643
1644 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1645 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1646 r600_context_pipe_state_set(&rctx->ctx, rstate);
1647
1648 if (state->zsbuf) {
1649 r600_polygon_offset_update(rctx);
1650 }
1651 }
1652
1653 static void r600_texture_barrier(struct pipe_context *ctx)
1654 {
1655 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1656
1657 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
1658 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
1659 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
1660 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
1661 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1));
1662 }
1663
1664 void r600_init_state_functions(struct r600_pipe_context *rctx)
1665 {
1666 rctx->context.create_blend_state = r600_create_blend_state;
1667 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1668 rctx->context.create_fs_state = r600_create_shader_state;
1669 rctx->context.create_rasterizer_state = r600_create_rs_state;
1670 rctx->context.create_sampler_state = r600_create_sampler_state;
1671 rctx->context.create_sampler_view = r600_create_sampler_view;
1672 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1673 rctx->context.create_vs_state = r600_create_shader_state;
1674 rctx->context.bind_blend_state = r600_bind_blend_state;
1675 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1676 rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
1677 rctx->context.bind_fs_state = r600_bind_ps_shader;
1678 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1679 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1680 rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
1681 rctx->context.bind_vs_state = r600_bind_vs_shader;
1682 rctx->context.delete_blend_state = r600_delete_state;
1683 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1684 rctx->context.delete_fs_state = r600_delete_ps_shader;
1685 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1686 rctx->context.delete_sampler_state = r600_delete_state;
1687 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1688 rctx->context.delete_vs_state = r600_delete_vs_shader;
1689 rctx->context.set_blend_color = r600_set_blend_color;
1690 rctx->context.set_clip_state = r600_set_clip_state;
1691 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1692 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1693 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1694 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1695 rctx->context.set_sample_mask = r600_set_sample_mask;
1696 rctx->context.set_scissor_state = r600_set_scissor_state;
1697 rctx->context.set_stencil_ref = r600_set_stencil_ref;
1698 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1699 rctx->context.set_index_buffer = r600_set_index_buffer;
1700 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1701 rctx->context.set_viewport_state = r600_set_viewport_state;
1702 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1703 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1704 rctx->context.texture_barrier = r600_texture_barrier;
1705 }
1706
1707 void r600_adjust_gprs(struct r600_pipe_context *rctx)
1708 {
1709 struct r600_pipe_state rstate;
1710 unsigned num_ps_gprs = rctx->default_ps_gprs;
1711 unsigned num_vs_gprs = rctx->default_vs_gprs;
1712 unsigned tmp;
1713 int diff;
1714
1715 if (rctx->chip_class >= EVERGREEN)
1716 return;
1717
1718 if (!rctx->ps_shader || !rctx->vs_shader)
1719 return;
1720
1721 if (rctx->ps_shader->shader.bc.ngpr > rctx->default_ps_gprs)
1722 {
1723 diff = rctx->ps_shader->shader.bc.ngpr - rctx->default_ps_gprs;
1724 num_vs_gprs -= diff;
1725 num_ps_gprs += diff;
1726 }
1727
1728 if (rctx->vs_shader->shader.bc.ngpr > rctx->default_vs_gprs)
1729 {
1730 diff = rctx->vs_shader->shader.bc.ngpr - rctx->default_vs_gprs;
1731 num_ps_gprs -= diff;
1732 num_vs_gprs += diff;
1733 }
1734
1735 tmp = 0;
1736 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1737 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1738 rstate.nregs = 0;
1739 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0x0FFFFFFF, NULL, 0);
1740
1741 r600_context_pipe_state_set(&rctx->ctx, &rstate);
1742 }
1743
1744 void r600_init_config(struct r600_pipe_context *rctx)
1745 {
1746 int ps_prio;
1747 int vs_prio;
1748 int gs_prio;
1749 int es_prio;
1750 int num_ps_gprs;
1751 int num_vs_gprs;
1752 int num_gs_gprs;
1753 int num_es_gprs;
1754 int num_temp_gprs;
1755 int num_ps_threads;
1756 int num_vs_threads;
1757 int num_gs_threads;
1758 int num_es_threads;
1759 int num_ps_stack_entries;
1760 int num_vs_stack_entries;
1761 int num_gs_stack_entries;
1762 int num_es_stack_entries;
1763 enum radeon_family family;
1764 struct r600_pipe_state *rstate = &rctx->config;
1765 u32 tmp;
1766
1767 family = rctx->family;
1768 ps_prio = 0;
1769 vs_prio = 1;
1770 gs_prio = 2;
1771 es_prio = 3;
1772 switch (family) {
1773 case CHIP_R600:
1774 num_ps_gprs = 192;
1775 num_vs_gprs = 56;
1776 num_temp_gprs = 4;
1777 num_gs_gprs = 0;
1778 num_es_gprs = 0;
1779 num_ps_threads = 136;
1780 num_vs_threads = 48;
1781 num_gs_threads = 4;
1782 num_es_threads = 4;
1783 num_ps_stack_entries = 128;
1784 num_vs_stack_entries = 128;
1785 num_gs_stack_entries = 0;
1786 num_es_stack_entries = 0;
1787 break;
1788 case CHIP_RV630:
1789 case CHIP_RV635:
1790 num_ps_gprs = 84;
1791 num_vs_gprs = 36;
1792 num_temp_gprs = 4;
1793 num_gs_gprs = 0;
1794 num_es_gprs = 0;
1795 num_ps_threads = 144;
1796 num_vs_threads = 40;
1797 num_gs_threads = 4;
1798 num_es_threads = 4;
1799 num_ps_stack_entries = 40;
1800 num_vs_stack_entries = 40;
1801 num_gs_stack_entries = 32;
1802 num_es_stack_entries = 16;
1803 break;
1804 case CHIP_RV610:
1805 case CHIP_RV620:
1806 case CHIP_RS780:
1807 case CHIP_RS880:
1808 default:
1809 num_ps_gprs = 84;
1810 num_vs_gprs = 36;
1811 num_temp_gprs = 4;
1812 num_gs_gprs = 0;
1813 num_es_gprs = 0;
1814 num_ps_threads = 136;
1815 num_vs_threads = 48;
1816 num_gs_threads = 4;
1817 num_es_threads = 4;
1818 num_ps_stack_entries = 40;
1819 num_vs_stack_entries = 40;
1820 num_gs_stack_entries = 32;
1821 num_es_stack_entries = 16;
1822 break;
1823 case CHIP_RV670:
1824 num_ps_gprs = 144;
1825 num_vs_gprs = 40;
1826 num_temp_gprs = 4;
1827 num_gs_gprs = 0;
1828 num_es_gprs = 0;
1829 num_ps_threads = 136;
1830 num_vs_threads = 48;
1831 num_gs_threads = 4;
1832 num_es_threads = 4;
1833 num_ps_stack_entries = 40;
1834 num_vs_stack_entries = 40;
1835 num_gs_stack_entries = 32;
1836 num_es_stack_entries = 16;
1837 break;
1838 case CHIP_RV770:
1839 num_ps_gprs = 192;
1840 num_vs_gprs = 56;
1841 num_temp_gprs = 4;
1842 num_gs_gprs = 0;
1843 num_es_gprs = 0;
1844 num_ps_threads = 188;
1845 num_vs_threads = 60;
1846 num_gs_threads = 0;
1847 num_es_threads = 0;
1848 num_ps_stack_entries = 256;
1849 num_vs_stack_entries = 256;
1850 num_gs_stack_entries = 0;
1851 num_es_stack_entries = 0;
1852 break;
1853 case CHIP_RV730:
1854 case CHIP_RV740:
1855 num_ps_gprs = 84;
1856 num_vs_gprs = 36;
1857 num_temp_gprs = 4;
1858 num_gs_gprs = 0;
1859 num_es_gprs = 0;
1860 num_ps_threads = 188;
1861 num_vs_threads = 60;
1862 num_gs_threads = 0;
1863 num_es_threads = 0;
1864 num_ps_stack_entries = 128;
1865 num_vs_stack_entries = 128;
1866 num_gs_stack_entries = 0;
1867 num_es_stack_entries = 0;
1868 break;
1869 case CHIP_RV710:
1870 num_ps_gprs = 192;
1871 num_vs_gprs = 56;
1872 num_temp_gprs = 4;
1873 num_gs_gprs = 0;
1874 num_es_gprs = 0;
1875 num_ps_threads = 144;
1876 num_vs_threads = 48;
1877 num_gs_threads = 0;
1878 num_es_threads = 0;
1879 num_ps_stack_entries = 128;
1880 num_vs_stack_entries = 128;
1881 num_gs_stack_entries = 0;
1882 num_es_stack_entries = 0;
1883 break;
1884 }
1885
1886 rctx->default_ps_gprs = num_ps_gprs;
1887 rctx->default_vs_gprs = num_vs_gprs;
1888
1889 rstate->id = R600_PIPE_STATE_CONFIG;
1890
1891 /* SQ_CONFIG */
1892 tmp = 0;
1893 switch (family) {
1894 case CHIP_RV610:
1895 case CHIP_RV620:
1896 case CHIP_RS780:
1897 case CHIP_RS880:
1898 case CHIP_RV710:
1899 break;
1900 default:
1901 tmp |= S_008C00_VC_ENABLE(1);
1902 break;
1903 }
1904 tmp |= S_008C00_DX9_CONSTS(0);
1905 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1906 tmp |= S_008C00_PS_PRIO(ps_prio);
1907 tmp |= S_008C00_VS_PRIO(vs_prio);
1908 tmp |= S_008C00_GS_PRIO(gs_prio);
1909 tmp |= S_008C00_ES_PRIO(es_prio);
1910 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL, 0);
1911
1912 /* SQ_GPR_RESOURCE_MGMT_1 */
1913 tmp = 0;
1914 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1915 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1916 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1917 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
1918
1919 /* SQ_GPR_RESOURCE_MGMT_2 */
1920 tmp = 0;
1921 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1922 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1923 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
1924
1925 /* SQ_THREAD_RESOURCE_MGMT */
1926 tmp = 0;
1927 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1928 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1929 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1930 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1931 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL, 0);
1932
1933 /* SQ_STACK_RESOURCE_MGMT_1 */
1934 tmp = 0;
1935 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1936 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1937 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
1938
1939 /* SQ_STACK_RESOURCE_MGMT_2 */
1940 tmp = 0;
1941 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1942 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1943 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
1944
1945 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1946 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL, 0);
1947
1948 if (rctx->chip_class >= R700) {
1949 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL, 0);
1950 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1951 S_009508_DISABLE_CUBE_ANISO(1) |
1952 S_009508_SYNC_GRADIENT(1) |
1953 S_009508_SYNC_WALKER(1) |
1954 S_009508_SYNC_ALIGNER(1), 0xFFFFFFFF, NULL, 0);
1955 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL, 0);
1956 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL, 0);
1957 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL, 0);
1958 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL, 0);
1959 } else {
1960 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL, 0);
1961 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1962 S_009508_DISABLE_CUBE_ANISO(1) |
1963 S_009508_SYNC_GRADIENT(1) |
1964 S_009508_SYNC_WALKER(1) |
1965 S_009508_SYNC_ALIGNER(1), 0xFFFFFFFF, NULL, 0);
1966 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL, 0);
1967 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL, 0);
1968 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL, 0);
1969 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL, 0);
1970 }
1971 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1972 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1973 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1974 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1975 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1976 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1977 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1978 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1979 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1980 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
1981 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
1982 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL, 0);
1983 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL, 0);
1984 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL, 0);
1985 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1986 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL, 0);
1987 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL, 0);
1988 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
1989 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
1990 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
1991 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
1992 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1993 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
1994 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL, 0);
1995 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
1996 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
1997
1998 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL, 0);
1999 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
2000 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
2001 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL, 0);
2002 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL, 0);
2003 r600_context_pipe_state_set(&rctx->ctx, rstate);
2004 }
2005
2006 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2007 {
2008 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2009 struct r600_pipe_state *rstate = &shader->rstate;
2010 struct r600_shader *rshader = &shader->shader;
2011 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2012 int pos_index = -1, face_index = -1;
2013
2014 rstate->nregs = 0;
2015
2016 for (i = 0; i < rshader->ninput; i++) {
2017 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2018 pos_index = i;
2019 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2020 face_index = i;
2021 }
2022
2023 db_shader_control = 0;
2024 for (i = 0; i < rshader->noutput; i++) {
2025 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2026 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2027 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2028 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1);
2029 }
2030 if (rshader->uses_kill)
2031 db_shader_control |= S_02880C_KILL_ENABLE(1);
2032
2033 exports_ps = 0;
2034 num_cout = 0;
2035 for (i = 0; i < rshader->noutput; i++) {
2036 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2037 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2038 exports_ps |= 1;
2039 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2040 num_cout++;
2041 }
2042 }
2043 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2044 if (!exports_ps) {
2045 /* always at least export 1 component per pixel */
2046 exports_ps = 2;
2047 }
2048
2049 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2050 S_0286CC_PERSP_GRADIENT_ENA(1);
2051 spi_input_z = 0;
2052 if (pos_index != -1) {
2053 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2054 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2055 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2056 S_0286CC_BARYC_SAMPLE_CNTL(1));
2057 spi_input_z |= 1;
2058 }
2059
2060 spi_ps_in_control_1 = 0;
2061 if (face_index != -1) {
2062 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2063 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2064 }
2065
2066 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL, 0);
2067 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL, 0);
2068 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL, 0);
2069 r600_pipe_state_add_reg(rstate,
2070 R_028840_SQ_PGM_START_PS,
2071 0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2072 r600_pipe_state_add_reg(rstate,
2073 R_028850_SQ_PGM_RESOURCES_PS,
2074 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2075 S_028868_STACK_SIZE(rshader->bc.nstack),
2076 0xFFFFFFFF, NULL, 0);
2077 r600_pipe_state_add_reg(rstate,
2078 R_028854_SQ_PGM_EXPORTS_PS,
2079 exports_ps, 0xFFFFFFFF, NULL, 0);
2080 r600_pipe_state_add_reg(rstate,
2081 R_0288CC_SQ_PGM_CF_OFFSET_PS,
2082 0x00000000, 0xFFFFFFFF, NULL, 0);
2083 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
2084 S_028808_MULTIWRITE_ENABLE(!!rshader->fs_write_all),
2085 S_028808_MULTIWRITE_ENABLE(1),
2086 NULL, 0);
2087 /* only set some bits here, the other bits are set in the dsa state */
2088 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2089 db_shader_control,
2090 S_02880C_Z_EXPORT_ENABLE(1) |
2091 S_02880C_STENCIL_REF_EXPORT_ENABLE(1) |
2092 S_02880C_KILL_ENABLE(1),
2093 NULL, 0);
2094
2095 r600_pipe_state_add_reg(rstate,
2096 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
2097 0xFFFFFFFF, NULL, 0);
2098 }
2099
2100 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2101 {
2102 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2103 struct r600_pipe_state *rstate = &shader->rstate;
2104 struct r600_shader *rshader = &shader->shader;
2105 unsigned spi_vs_out_id[10];
2106 unsigned i, tmp, nparams;
2107
2108 /* clear previous register */
2109 rstate->nregs = 0;
2110
2111 /* so far never got proper semantic id from tgsi */
2112 /* FIXME better to move this in config things so they get emited
2113 * only one time per cs
2114 */
2115 for (i = 0; i < 10; i++) {
2116 spi_vs_out_id[i] = 0;
2117 }
2118 for (i = 0; i < 32; i++) {
2119 tmp = i << ((i & 3) * 8);
2120 spi_vs_out_id[i / 4] |= tmp;
2121 }
2122 for (i = 0; i < 10; i++) {
2123 r600_pipe_state_add_reg(rstate,
2124 R_028614_SPI_VS_OUT_ID_0 + i * 4,
2125 spi_vs_out_id[i], 0xFFFFFFFF, NULL, 0);
2126 }
2127
2128 /* Certain attributes (position, psize, etc.) don't count as params.
2129 * VS is required to export at least one param and r600_shader_from_tgsi()
2130 * takes care of adding a dummy export.
2131 */
2132 nparams = rshader->noutput - rshader->npos;
2133 if (nparams < 1)
2134 nparams = 1;
2135
2136 r600_pipe_state_add_reg(rstate,
2137 R_0286C4_SPI_VS_OUT_CONFIG,
2138 S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2139 0xFFFFFFFF, NULL, 0);
2140 r600_pipe_state_add_reg(rstate,
2141 R_028868_SQ_PGM_RESOURCES_VS,
2142 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2143 S_028868_STACK_SIZE(rshader->bc.nstack),
2144 0xFFFFFFFF, NULL, 0);
2145 r600_pipe_state_add_reg(rstate,
2146 R_0288D0_SQ_PGM_CF_OFFSET_VS,
2147 0x00000000, 0xFFFFFFFF, NULL, 0);
2148 r600_pipe_state_add_reg(rstate,
2149 R_028858_SQ_PGM_START_VS,
2150 0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2151
2152 r600_pipe_state_add_reg(rstate,
2153 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2154 0xFFFFFFFF, NULL, 0);
2155 }
2156
2157 void r600_fetch_shader(struct pipe_context *ctx,
2158 struct r600_vertex_element *ve)
2159 {
2160 struct r600_pipe_state *rstate;
2161 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2162
2163 rstate = &ve->rstate;
2164 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2165 rstate->nregs = 0;
2166 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
2167 0x00000000, 0xFFFFFFFF, NULL, 0);
2168 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
2169 0x00000000, 0xFFFFFFFF, NULL, 0);
2170 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
2171 0,
2172 0xFFFFFFFF, ve->fetch_shader, RADEON_USAGE_READ);
2173 }
2174
2175 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
2176 {
2177 struct pipe_depth_stencil_alpha_state dsa;
2178 struct r600_pipe_state *rstate;
2179 boolean quirk = false;
2180
2181 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2182 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2183 quirk = true;
2184
2185 memset(&dsa, 0, sizeof(dsa));
2186
2187 if (quirk) {
2188 dsa.depth.enabled = 1;
2189 dsa.depth.func = PIPE_FUNC_LEQUAL;
2190 dsa.stencil[0].enabled = 1;
2191 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2192 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2193 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2194 dsa.stencil[0].writemask = 0xff;
2195 }
2196
2197 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2198 r600_pipe_state_add_reg(rstate,
2199 R_02880C_DB_SHADER_CONTROL,
2200 0x0,
2201 S_02880C_DUAL_EXPORT_ENABLE(1), NULL, 0);
2202 r600_pipe_state_add_reg(rstate,
2203 R_028D0C_DB_RENDER_CONTROL,
2204 S_028D0C_DEPTH_COPY_ENABLE(1) |
2205 S_028D0C_STENCIL_COPY_ENABLE(1) |
2206 S_028D0C_COPY_CENTROID(1),
2207 S_028D0C_DEPTH_COPY_ENABLE(1) |
2208 S_028D0C_STENCIL_COPY_ENABLE(1) |
2209 S_028D0C_COPY_CENTROID(1), NULL, 0);
2210 return rstate;
2211 }
2212
2213 void r600_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
2214 struct r600_pipe_resource_state *rstate)
2215 {
2216 rstate->id = R600_PIPE_STATE_RESOURCE;
2217
2218 rstate->bo[0] = NULL;
2219 rstate->val[0] = 0;
2220 rstate->val[1] = 0;
2221 rstate->val[2] = 0;
2222 rstate->val[3] = 0;
2223 rstate->val[4] = 0;
2224 rstate->val[5] = 0;
2225 rstate->val[6] = 0xc0000000;
2226 }
2227
2228 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
2229 struct r600_resource *rbuffer,
2230 unsigned offset, unsigned stride,
2231 enum radeon_bo_usage usage)
2232 {
2233 rstate->val[0] = offset;
2234 rstate->bo[0] = rbuffer->bo;
2235 rstate->bo_usage[0] = usage;
2236 rstate->val[1] = rbuffer->bo_size - offset - 1;
2237 rstate->val[2] = S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
2238 S_038008_STRIDE(stride);
2239 }