src/gallium/drivers/r600/r600_state.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #include <stdio.h>
  27 #include "util/u_inlines.h"
  28 #include "util/u_format.h"
  29 #include "util/u_memory.h"
  30 #include "r600_screen.h"
  31 #include "r600_context.h"
  32 #include "r600_resource.h"
  33 #include "r600d.h"
  34
  35 static void *r600_create_blend_state(struct pipe_context *ctx,
  36                                         const struct pipe_blend_state *state)
  37 {
  38         struct r600_context *rctx = r600_context(ctx);
  39
  40         return r600_context_state(rctx, pipe_blend_type, state);
  41 }
  42
  43 static void *r600_create_dsa_state(struct pipe_context *ctx,
  44                                         const struct pipe_depth_stencil_alpha_state *state)
  45 {
  46         struct r600_context *rctx = r600_context(ctx);
  47
  48         return r600_context_state(rctx, pipe_dsa_type, state);
  49 }
  50
  51 static void *r600_create_rs_state(struct pipe_context *ctx,
  52                                         const struct pipe_rasterizer_state *state)
  53 {
  54         struct r600_context *rctx = r600_context(ctx);
  55
  56         return r600_context_state(rctx, pipe_rasterizer_type, state);
  57 }
  58
  59 static void *r600_create_sampler_state(struct pipe_context *ctx,
  60                                         const struct pipe_sampler_state *state)
  61 {
  62         struct r600_context *rctx = r600_context(ctx);
  63
  64         return r600_context_state(rctx, pipe_sampler_type, state);
  65 }
  66
  67 static void r600_sampler_view_destroy(struct pipe_context *ctx,
  68                                       struct pipe_sampler_view *state)
  69 {
  70         struct r600_context_state *rstate = (struct r600_context_state *)state;
  71
  72         r600_context_state_decref(rstate);
  73 }
  74
  75 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
  76                                                         struct pipe_resource *texture,
  77                                                         const struct pipe_sampler_view *state)
  78 {
  79         struct r600_context *rctx = r600_context(ctx);
  80         struct r600_context_state *rstate;
  81
  82         rstate = r600_context_state(rctx, pipe_sampler_type, state);
  83         pipe_reference(NULL, &texture->reference);
  84         rstate->state.sampler_view.texture = texture;
  85         rstate->state.sampler_view.reference.count = 1;
  86         rstate->state.sampler_view.context = ctx;
  87         return &rstate->state.sampler_view;
  88 }
  89
  90 static void *r600_create_shader_state(struct pipe_context *ctx,
  91                                         const struct pipe_shader_state *state)
  92 {
  93         struct r600_context *rctx = r600_context(ctx);
  94
  95         return r600_context_state(rctx, pipe_shader_type, state);
  96 }
  97
  98 static void *r600_create_vertex_elements(struct pipe_context *ctx,
  99                                 unsigned count,
 100                                 const struct pipe_vertex_element *elements)
 101 {
 102         struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
 103
 104         assert(count < 32);
 105         v->count = count;
 106         memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
 107         v->refcount = 1;
 108         return v;
 109 }
 110
 111 static void r600_bind_state(struct pipe_context *ctx, void *state)
 112 {
 113         struct r600_context *rctx = r600_context(ctx);
 114         struct r600_context_state *rstate = (struct r600_context_state *)state;
 115
 116         if (state == NULL)
 117                 return;
 118         switch (rstate->type) {
 119         case pipe_rasterizer_type:
 120                 rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
 121                 rctx->rasterizer = r600_context_state_incref(rstate);
 122                 break;
 123         case pipe_poly_stipple_type:
 124                 rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple);
 125                 rctx->poly_stipple = r600_context_state_incref(rstate);
 126                 break;
 127         case pipe_scissor_type:
 128                 rctx->scissor = r600_context_state_decref(rctx->scissor);
 129                 rctx->scissor = r600_context_state_incref(rstate);
 130                 break;
 131         case pipe_clip_type:
 132                 rctx->clip = r600_context_state_decref(rctx->clip);
 133                 rctx->clip = r600_context_state_incref(rstate);
 134                 break;
 135         case pipe_depth_type:
 136                 rctx->depth = r600_context_state_decref(rctx->depth);
 137                 rctx->depth = r600_context_state_incref(rstate);
 138                 break;
 139         case pipe_stencil_type:
 140                 rctx->stencil = r600_context_state_decref(rctx->stencil);
 141                 rctx->stencil = r600_context_state_incref(rstate);
 142                 break;
 143         case pipe_alpha_type:
 144                 rctx->alpha = r600_context_state_decref(rctx->alpha);
 145                 rctx->alpha = r600_context_state_incref(rstate);
 146                 break;
 147         case pipe_dsa_type:
 148                 rctx->dsa = r600_context_state_decref(rctx->dsa);
 149                 rctx->dsa = r600_context_state_incref(rstate);
 150                 break;
 151         case pipe_blend_type:
 152                 rctx->blend = r600_context_state_decref(rctx->blend);
 153                 rctx->blend = r600_context_state_incref(rstate);
 154                 break;
 155         case pipe_framebuffer_type:
 156                 rctx->framebuffer = r600_context_state_decref(rctx->framebuffer);
 157                 rctx->framebuffer = r600_context_state_incref(rstate);
 158                 break;
 159         case pipe_stencil_ref_type:
 160                 rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref);
 161                 rctx->stencil_ref = r600_context_state_incref(rstate);
 162                 break;
 163         case pipe_viewport_type:
 164                 rctx->viewport = r600_context_state_decref(rctx->viewport);
 165                 rctx->viewport = r600_context_state_incref(rstate);
 166                 break;
 167         case pipe_shader_type:
 168         case pipe_sampler_type:
 169         case pipe_sampler_view_type:
 170         default:
 171                 R600_ERR("invalid type %d\n", rstate->type);
 172                 return;
 173         }
 174 }
 175
 176 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
 177 {
 178         struct r600_context *rctx = r600_context(ctx);
 179         struct r600_context_state *rstate = (struct r600_context_state *)state;
 180
 181         rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
 182         rctx->ps_shader = r600_context_state_incref(rstate);
 183 }
 184
 185 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
 186 {
 187         struct r600_context *rctx = r600_context(ctx);
 188         struct r600_context_state *rstate = (struct r600_context_state *)state;
 189
 190         rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
 191         rctx->vs_shader = r600_context_state_incref(rstate);
 192 }
 193
 194 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
 195 {
 196         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 197
 198         if (v == NULL)
 199                 return;
 200         if (--v->refcount)
 201                 return;
 202         free(v);
 203 }
 204
 205 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 206 {
 207         struct r600_context *rctx = r600_context(ctx);
 208         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 209
 210         r600_delete_vertex_element(ctx, rctx->vertex_elements);
 211         rctx->vertex_elements = v;
 212         if (v) {
 213                 v->refcount++;
 214         }
 215 }
 216
 217 static void r600_bind_ps_sampler(struct pipe_context *ctx,
 218                                         unsigned count, void **states)
 219 {
 220         struct r600_context *rctx = r600_context(ctx);
 221         struct r600_context_state *rstate;
 222         unsigned i;
 223
 224         for (i = 0; i < rctx->ps_nsampler; i++) {
 225                 rctx->ps_sampler[i] = r600_context_state_decref(rctx->ps_sampler[i]);
 226         }
 227         for (i = 0; i < count; i++) {
 228                 rstate = (struct r600_context_state *)states[i];
 229                 rctx->ps_sampler[i] = r600_context_state_incref(rstate);
 230         }
 231         rctx->ps_nsampler = count;
 232 }
 233
 234 static void r600_bind_vs_sampler(struct pipe_context *ctx,
 235                                         unsigned count, void **states)
 236 {
 237         struct r600_context *rctx = r600_context(ctx);
 238         struct r600_context_state *rstate;
 239         unsigned i;
 240
 241         for (i = 0; i < rctx->vs_nsampler; i++) {
 242                 rctx->vs_sampler[i] = r600_context_state_decref(rctx->vs_sampler[i]);
 243         }
 244         for (i = 0; i < count; i++) {
 245                 rstate = (struct r600_context_state *)states[i];
 246                 rctx->vs_sampler[i] = r600_context_state_incref(rstate);
 247         }
 248         rctx->vs_nsampler = count;
 249 }
 250
 251 static void r600_delete_state(struct pipe_context *ctx, void *state)
 252 {
 253         struct r600_context_state *rstate = (struct r600_context_state *)state;
 254
 255         r600_context_state_decref(rstate);
 256 }
 257
 258 static void r600_set_blend_color(struct pipe_context *ctx,
 259                                         const struct pipe_blend_color *color)
 260 {
 261 }
 262
 263 static void r600_set_clip_state(struct pipe_context *ctx,
 264                                 const struct pipe_clip_state *state)
 265 {
 266 }
 267
 268 static void r600_set_constant_buffer(struct pipe_context *ctx,
 269                                         uint shader, uint index,
 270                                         struct pipe_resource *buffer)
 271 {
 272         struct r600_screen *rscreen = r600_screen(ctx->screen);
 273         struct r600_context *rctx = r600_context(ctx);
 274         unsigned nconstant = 0, i, type, id;
 275         struct radeon_state *rstate;
 276         struct pipe_transfer *transfer;
 277         u32 *ptr;
 278
 279         switch (shader) {
 280         case PIPE_SHADER_VERTEX:
 281                 id = R600_VS_CONSTANT;
 282                 type = R600_VS_CONSTANT_TYPE;
 283                 break;
 284         case PIPE_SHADER_FRAGMENT:
 285                 id = R600_PS_CONSTANT;
 286                 type = R600_PS_CONSTANT_TYPE;
 287                 break;
 288         default:
 289                 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, shader);
 290                 return;
 291         }
 292         if (buffer && buffer->width0 > 0) {
 293                 nconstant = buffer->width0 / 16;
 294                 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
 295                 if (ptr == NULL)
 296                         return;
 297                 for (i = 0; i < nconstant; i++) {
 298                         rstate = radeon_state(rscreen->rw, type, id + i);
 299                         if (rstate == NULL)
 300                                 return;
 301                         rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
 302                         rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
 303                         rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
 304                         rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
 305                         if (radeon_state_pm4(rstate))
 306                                 return;
 307                         if (radeon_draw_set_new(rctx->draw, rstate))
 308                                 return;
 309                 }
 310                 pipe_buffer_unmap(ctx, buffer, transfer);
 311         }
 312 }
 313
 314 static void r600_set_ps_sampler_view(struct pipe_context *ctx,
 315                                         unsigned count,
 316                                         struct pipe_sampler_view **views)
 317 {
 318         struct r600_context *rctx = r600_context(ctx);
 319         struct r600_context_state *rstate;
 320         unsigned i;
 321
 322         for (i = 0; i < rctx->ps_nsampler_view; i++) {
 323                 rctx->ps_sampler_view[i] = r600_context_state_decref(rctx->ps_sampler_view[i]);
 324         }
 325         for (i = 0; i < count; i++) {
 326                 rstate = (struct r600_context_state *)views[i];
 327                 rctx->ps_sampler_view[i] = r600_context_state_incref(rstate);
 328         }
 329         rctx->ps_nsampler_view = count;
 330 }
 331
 332 static void r600_set_vs_sampler_view(struct pipe_context *ctx,
 333                                         unsigned count,
 334                                         struct pipe_sampler_view **views)
 335 {
 336         struct r600_context *rctx = r600_context(ctx);
 337         struct r600_context_state *rstate;
 338         unsigned i;
 339
 340         for (i = 0; i < rctx->vs_nsampler_view; i++) {
 341                 rctx->vs_sampler_view[i] = r600_context_state_decref(rctx->vs_sampler_view[i]);
 342         }
 343         for (i = 0; i < count; i++) {
 344                 rstate = (struct r600_context_state *)views[i];
 345                 rctx->vs_sampler_view[i] = r600_context_state_incref(rstate);
 346         }
 347         rctx->vs_nsampler_view = count;
 348 }
 349
 350 static void r600_set_framebuffer_state(struct pipe_context *ctx,
 351                                         const struct pipe_framebuffer_state *state)
 352 {
 353         struct r600_context *rctx = r600_context(ctx);
 354         struct r600_context_state *rstate;
 355
 356         rstate = r600_context_state(rctx, pipe_framebuffer_type, state);
 357         r600_bind_state(ctx, rstate);
 358 }
 359
 360 static void r600_set_polygon_stipple(struct pipe_context *ctx,
 361                                          const struct pipe_poly_stipple *state)
 362 {
 363 }
 364
 365 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
 366 {
 367 }
 368
 369 static void r600_set_scissor_state(struct pipe_context *ctx,
 370                                         const struct pipe_scissor_state *state)
 371 {
 372         struct r600_context *rctx = r600_context(ctx);
 373         struct r600_context_state *rstate;
 374
 375         rstate = r600_context_state(rctx, pipe_scissor_type, state);
 376         r600_bind_state(ctx, rstate);
 377 }
 378
 379 static void r600_set_stencil_ref(struct pipe_context *ctx,
 380                                 const struct pipe_stencil_ref *state)
 381 {
 382         struct r600_context *rctx = r600_context(ctx);
 383         struct r600_context_state *rstate;
 384
 385         rstate = r600_context_state(rctx, pipe_stencil_ref_type, state);
 386         r600_bind_state(ctx, rstate);
 387 }
 388
 389 static void r600_set_vertex_buffers(struct pipe_context *ctx,
 390                                         unsigned count,
 391                                         const struct pipe_vertex_buffer *buffers)
 392 {
 393         struct r600_context *rctx = r600_context(ctx);
 394         unsigned i;
 395
 396         for (i = 0; i < rctx->nvertex_buffer; i++) {
 397                 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
 398         }
 399         memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
 400         for (i = 0; i < count; i++) {
 401                 rctx->vertex_buffer[i].buffer = NULL;
 402                 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
 403         }
 404         rctx->nvertex_buffer = count;
 405 }
 406
 407 static void r600_set_viewport_state(struct pipe_context *ctx,
 408                                         const struct pipe_viewport_state *state)
 409 {
 410         struct r600_context *rctx = r600_context(ctx);
 411         struct r600_context_state *rstate;
 412
 413         rstate = r600_context_state(rctx, pipe_viewport_type, state);
 414         r600_bind_state(ctx, rstate);
 415 }
 416
 417 void r600_init_state_functions(struct r600_context *rctx)
 418 {
 419         rctx->context.create_blend_state = r600_create_blend_state;
 420         rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
 421         rctx->context.create_fs_state = r600_create_shader_state;
 422         rctx->context.create_rasterizer_state = r600_create_rs_state;
 423         rctx->context.create_sampler_state = r600_create_sampler_state;
 424         rctx->context.create_sampler_view = r600_create_sampler_view;
 425         rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
 426         rctx->context.create_vs_state = r600_create_shader_state;
 427         rctx->context.bind_blend_state = r600_bind_state;
 428         rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
 429         rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
 430         rctx->context.bind_fs_state = r600_bind_ps_shader;
 431         rctx->context.bind_rasterizer_state = r600_bind_state;
 432         rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
 433         rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
 434         rctx->context.bind_vs_state = r600_bind_vs_shader;
 435         rctx->context.delete_blend_state = r600_delete_state;
 436         rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
 437         rctx->context.delete_fs_state = r600_delete_state;
 438         rctx->context.delete_rasterizer_state = r600_delete_state;
 439         rctx->context.delete_sampler_state = r600_delete_state;
 440         rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
 441         rctx->context.delete_vs_state = r600_delete_state;
 442         rctx->context.set_blend_color = r600_set_blend_color;
 443         rctx->context.set_clip_state = r600_set_clip_state;
 444         rctx->context.set_constant_buffer = r600_set_constant_buffer;
 445         rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
 446         rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
 447         rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
 448         rctx->context.set_sample_mask = r600_set_sample_mask;
 449         rctx->context.set_scissor_state = r600_set_scissor_state;
 450         rctx->context.set_stencil_ref = r600_set_stencil_ref;
 451         rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
 452         rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
 453         rctx->context.set_viewport_state = r600_set_viewport_state;
 454         rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
 455 }
 456
 457 struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate)
 458 {
 459         if (rstate == NULL)
 460                 return NULL;
 461         rstate->refcount++;
 462         return rstate;
 463 }
 464
 465 struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate)
 466 {
 467         unsigned i;
 468
 469         if (rstate == NULL)
 470                 return NULL;
 471         if (--rstate->refcount)
 472                 return NULL;
 473         switch (rstate->type) {
 474         case pipe_sampler_view_type:
 475                 pipe_resource_reference(&rstate->state.sampler_view.texture, NULL);
 476                 break;
 477         case pipe_framebuffer_type:
 478                 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
 479                         pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], NULL);
 480                 }
 481                 pipe_surface_reference(&rstate->state.framebuffer.zsbuf, NULL);
 482                 break;
 483         case pipe_viewport_type:
 484         case pipe_depth_type:
 485         case pipe_rasterizer_type:
 486         case pipe_poly_stipple_type:
 487         case pipe_scissor_type:
 488         case pipe_clip_type:
 489         case pipe_stencil_type:
 490         case pipe_alpha_type:
 491         case pipe_dsa_type:
 492         case pipe_blend_type:
 493         case pipe_stencil_ref_type:
 494         case pipe_shader_type:
 495         case pipe_sampler_type:
 496                 break;
 497         default:
 498                 R600_ERR("invalid type %d\n", rstate->type);
 499                 return NULL;
 500         }
 501         radeon_state_decref(rstate->rstate);
 502         FREE(rstate);
 503         return NULL;
 504 }
 505
 506 struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state)
 507 {
 508         struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state);
 509         const union pipe_states *states = state;
 510         unsigned i;
 511         int r;
 512
 513         if (rstate == NULL)
 514                 return NULL;
 515         rstate->type = type;
 516         rstate->refcount = 1;
 517
 518         switch (rstate->type) {
 519         case pipe_sampler_view_type:
 520                 rstate->state.sampler_view = (*states).sampler_view;
 521                 rstate->state.sampler_view.texture = NULL;
 522                 break;
 523         case pipe_framebuffer_type:
 524                 rstate->state.framebuffer = (*states).framebuffer;
 525                 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
 526                         pipe_surface_reference(&rstate->state.framebuffer.cbufs[i],
 527                                                 (*states).framebuffer.cbufs[i]);
 528                 }
 529                 pipe_surface_reference(&rstate->state.framebuffer.zsbuf,
 530                                         (*states).framebuffer.zsbuf);
 531                 break;
 532         case pipe_viewport_type:
 533                 rstate->state.viewport = (*states).viewport;
 534                 break;
 535         case pipe_depth_type:
 536                 rstate->state.depth = (*states).depth;
 537                 break;
 538         case pipe_rasterizer_type:
 539                 rstate->state.rasterizer = (*states).rasterizer;
 540                 break;
 541         case pipe_poly_stipple_type:
 542                 rstate->state.poly_stipple = (*states).poly_stipple;
 543                 break;
 544         case pipe_scissor_type:
 545                 rstate->state.scissor = (*states).scissor;
 546                 break;
 547         case pipe_clip_type:
 548                 rstate->state.clip = (*states).clip;
 549                 break;
 550         case pipe_stencil_type:
 551                 rstate->state.stencil = (*states).stencil;
 552                 break;
 553         case pipe_alpha_type:
 554                 rstate->state.alpha = (*states).alpha;
 555                 break;
 556         case pipe_dsa_type:
 557                 rstate->state.dsa = (*states).dsa;
 558                 break;
 559         case pipe_blend_type:
 560                 rstate->state.blend = (*states).blend;
 561                 break;
 562         case pipe_stencil_ref_type:
 563                 rstate->state.stencil_ref = (*states).stencil_ref;
 564                 break;
 565         case pipe_shader_type:
 566                 rstate->state.shader = (*states).shader;
 567                 r =  r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens);
 568                 if (r) {
 569                         r600_context_state_decref(rstate);
 570                         return NULL;
 571                 }
 572                 break;
 573         case pipe_sampler_type:
 574                 rstate->state.sampler = (*states).sampler;
 575                 break;
 576         default:
 577                 R600_ERR("invalid type %d\n", rstate->type);
 578                 FREE(rstate);
 579                 return NULL;
 580         }
 581         return rstate;
 582 }
 583
 584 static struct radeon_state *r600_blend(struct r600_context *rctx)
 585 {
 586         struct r600_screen *rscreen = rctx->screen;
 587         struct radeon_state *rstate;
 588
 589         rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
 590         if (rstate == NULL)
 591                 return NULL;
 592         rstate->states[R600_BLEND__CB_BLEND_RED] = 0x00000000;
 593         rstate->states[R600_BLEND__CB_BLEND_GREEN] = 0x00000000;
 594         rstate->states[R600_BLEND__CB_BLEND_BLUE] = 0x00000000;
 595         rstate->states[R600_BLEND__CB_BLEND_ALPHA] = 0x00000000;
 596         rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00010001;
 597         rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
 598         rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
 599         rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
 600         rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
 601         rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
 602         rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
 603         rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
 604         rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
 605         if (radeon_state_pm4(rstate)) {
 606                 radeon_state_decref(rstate);
 607                 return NULL;
 608         }
 609         return rstate;
 610 }
 611
 612 static struct radeon_state *r600_cb0(struct r600_context *rctx)
 613 {
 614         struct r600_screen *rscreen = rctx->screen;
 615         struct r600_resource_texture *rtex;
 616         struct r600_resource *rbuffer;
 617         struct radeon_state *rstate;
 618         const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
 619         unsigned level = state->cbufs[0]->level;
 620         unsigned pitch, slice;
 621
 622         rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, R600_CB0);
 623         if (rstate == NULL)
 624                 return NULL;
 625         rtex = (struct r600_resource_texture*)state->cbufs[0]->texture;
 626         rbuffer = &rtex->resource;
 627         rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 628         rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 629         rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 630         rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 631         rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
 632         rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
 633         rstate->nbo = 3;
 634         pitch = rtex->pitch[level] / 8 - 1;
 635         slice = rtex->pitch[level] * state->cbufs[0]->height / 64 - 1;
 636         rstate->states[R600_CB0__CB_COLOR0_BASE] = 0x00000000;
 637         rstate->states[R600_CB0__CB_COLOR0_INFO] = 0x08110068;
 638         rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
 639                                                 S_028060_SLICE_TILE_MAX(slice);
 640         rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
 641         rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
 642         rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
 643         rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
 644         if (radeon_state_pm4(rstate)) {
 645                 radeon_state_decref(rstate);
 646                 return NULL;
 647         }
 648         return rstate;
 649 }
 650
 651 static struct radeon_state *r600_db(struct r600_context *rctx)
 652 {
 653         struct r600_screen *rscreen = rctx->screen;
 654         struct r600_resource_texture *rtex;
 655         struct r600_resource *rbuffer;
 656         struct radeon_state *rstate;
 657         const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
 658         unsigned level = state->cbufs[0]->level;
 659         unsigned pitch, slice;
 660
 661         if (state->zsbuf == NULL)
 662                 return NULL;
 663
 664         rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
 665         if (rstate == NULL)
 666                 return NULL;
 667
 668         rtex = (struct r600_resource_texture*)state->zsbuf->texture;
 669         rbuffer = &rtex->resource;
 670         rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 671         rstate->nbo = 1;
 672         rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
 673         level = state->zsbuf->level;
 674         pitch = rtex->pitch[level] / 8 - 1;
 675         slice = rtex->pitch[level] * state->zsbuf->height / 64 - 1;
 676         rstate->states[R600_DB__DB_DEPTH_BASE] = 0x00000000;
 677         rstate->states[R600_DB__DB_DEPTH_INFO] = 0x00010006;
 678         rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
 679         rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
 680         rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
 681                                                 S_028000_SLICE_TILE_MAX(slice);
 682         if (radeon_state_pm4(rstate)) {
 683                 radeon_state_decref(rstate);
 684                 return NULL;
 685         }
 686         return rstate;
 687 }
 688
 689 static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 690 {
 691         const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
 692         struct r600_screen *rscreen = rctx->screen;
 693         struct radeon_state *rstate;
 694
 695         rctx->flat_shade = state->flatshade;
 696         rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
 697         if (rstate == NULL)
 698                 return NULL;
 699         rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
 700         rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0x00000000;
 701         rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080000;
 702         rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] = 0x00000000;
 703         rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
 704         rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = 0x00080008;
 705         rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x00000000;
 706         rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
 707         rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
 708         rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
 709         rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
 710         rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
 711         rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
 712         rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
 713         rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
 714         rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = 0x00000000;
 715         rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
 716         rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = 0x00000000;
 717         rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = 0x00000000;
 718         rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = 0x00000000;
 719         rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = 0x00000000;
 720         if (radeon_state_pm4(rstate)) {
 721                 radeon_state_decref(rstate);
 722                 return NULL;
 723         }
 724         return rstate;
 725 }
 726
 727 static struct radeon_state *r600_scissor(struct r600_context *rctx)
 728 {
 729         const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
 730         struct r600_screen *rscreen = rctx->screen;
 731         struct radeon_state *rstate;
 732         u32 tl, br;
 733
 734         tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
 735         br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
 736         rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
 737         if (rstate == NULL)
 738                 return NULL;
 739         rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
 740         rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
 741         rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
 742         rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
 743         rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
 744         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
 745         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
 746         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
 747         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
 748         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
 749         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
 750         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
 751         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
 752         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
 753         rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
 754         rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
 755         rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
 756         rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
 757         rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
 758         if (radeon_state_pm4(rstate)) {
 759                 radeon_state_decref(rstate);
 760                 return NULL;
 761         }
 762         return rstate;
 763 }
 764
 765 static struct radeon_state *r600_viewport(struct r600_context *rctx)
 766 {
 767         const struct pipe_viewport_state *state = &rctx->viewport->state.viewport;
 768         struct r600_screen *rscreen = rctx->screen;
 769         struct radeon_state *rstate;
 770
 771         rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
 772         if (rstate == NULL)
 773                 return NULL;
 774         rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
 775         rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
 776         rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
 777         rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
 778         rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
 779         rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
 780         rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
 781         rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
 782         rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
 783         if (radeon_state_pm4(rstate)) {
 784                 radeon_state_decref(rstate);
 785                 return NULL;
 786         }
 787         return rstate;
 788 }
 789
 790 static struct radeon_state *r600_dsa(struct r600_context *rctx)
 791 {
 792         const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
 793         struct r600_screen *rscreen = rctx->screen;
 794         struct radeon_state *rstate;
 795         unsigned db_depth_control;
 796
 797         rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
 798         if (rstate == NULL)
 799                 return NULL;
 800         db_depth_control = 0x00700700 | S_028800_Z_ENABLE(state->depth.enabled) | S_028800_Z_WRITE_ENABLE(state->depth.writemask) | S_028800_ZFUNC(state->depth.func);
 801
 802         rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
 803         rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
 804         rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = 0x00000000;
 805         rstate->states[R600_DSA__DB_STENCILREFMASK] = 0xFFFFFF00;
 806         rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = 0xFFFFFF00;
 807         rstate->states[R600_DSA__SX_ALPHA_REF] = 0x00000000;
 808         rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
 809         rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
 810         rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
 811         rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
 812         rstate->states[R600_DSA__DB_SHADER_CONTROL] = 0x00000210;
 813         rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060;
 814         rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
 815         rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
 816         rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
 817         rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
 818         if (radeon_state_pm4(rstate)) {
 819                 radeon_state_decref(rstate);
 820                 return NULL;
 821         }
 822         return rstate;
 823 }
 824
 825 static inline unsigned r600_tex_wrap(unsigned wrap)
 826 {
 827         switch (wrap) {
 828         default:
 829         case PIPE_TEX_WRAP_REPEAT:
 830                 return V_03C000_SQ_TEX_WRAP;
 831         case PIPE_TEX_WRAP_CLAMP:
 832                 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
 833         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
 834                 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
 835         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
 836                 return V_03C000_SQ_TEX_CLAMP_BORDER;
 837         case PIPE_TEX_WRAP_MIRROR_REPEAT:
 838                 return V_03C000_SQ_TEX_MIRROR;
 839         case PIPE_TEX_WRAP_MIRROR_CLAMP:
 840                 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
 841         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
 842                 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
 843         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
 844                 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
 845         }
 846 }
 847
 848 static inline unsigned r600_tex_filter(unsigned filter)
 849 {
 850         switch (filter) {
 851         default:
 852         case PIPE_TEX_FILTER_NEAREST:
 853                 return V_03C000_SQ_TEX_XY_FILTER_POINT;
 854         case PIPE_TEX_FILTER_LINEAR:
 855                 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
 856         }
 857 }
 858
 859 static inline unsigned r600_tex_mipfilter(unsigned filter)
 860 {
 861         switch (filter) {
 862         case PIPE_TEX_MIPFILTER_NEAREST:
 863                 return V_03C000_SQ_TEX_Z_FILTER_POINT;
 864         case PIPE_TEX_MIPFILTER_LINEAR:
 865                 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
 866         default:
 867         case PIPE_TEX_MIPFILTER_NONE:
 868                 return V_03C000_SQ_TEX_Z_FILTER_NONE;
 869         }
 870 }
 871
 872 static inline unsigned r600_tex_compare(unsigned compare)
 873 {
 874         switch (compare) {
 875         default:
 876         case PIPE_FUNC_NEVER:
 877                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
 878         case PIPE_FUNC_LESS:
 879                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
 880         case PIPE_FUNC_EQUAL:
 881                 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
 882         case PIPE_FUNC_LEQUAL:
 883                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
 884         case PIPE_FUNC_GREATER:
 885                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
 886         case PIPE_FUNC_NOTEQUAL:
 887                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
 888         case PIPE_FUNC_GEQUAL:
 889                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
 890         case PIPE_FUNC_ALWAYS:
 891                 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
 892         }
 893 }
 894
 895 static struct radeon_state *r600_sampler(struct r600_context *rctx,
 896                                 const struct pipe_sampler_state *state,
 897                                 unsigned id)
 898 {
 899         struct r600_screen *rscreen = rctx->screen;
 900         struct radeon_state *rstate;
 901
 902         rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, id);
 903         if (rstate == NULL)
 904                 return NULL;
 905         rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
 906                         S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
 907                         S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
 908                         S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
 909                         S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
 910                         S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
 911                         S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
 912                         S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func));
 913         /* FIXME LOD it depends on texture base level ... */
 914         rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
 915                         S_03C004_MIN_LOD(0) |
 916                         S_03C004_MAX_LOD(0) |
 917                         S_03C004_LOD_BIAS(0);
 918         rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
 919         if (radeon_state_pm4(rstate)) {
 920                 radeon_state_decref(rstate);
 921                 return NULL;
 922         }
 923         return rstate;
 924 }
 925
 926 static inline unsigned r600_tex_swizzle(unsigned swizzle)
 927 {
 928         switch (swizzle) {
 929         case PIPE_SWIZZLE_RED:
 930                 return V_038010_SQ_SEL_X;
 931         case PIPE_SWIZZLE_GREEN:
 932                 return V_038010_SQ_SEL_Y;
 933         case PIPE_SWIZZLE_BLUE:
 934                 return V_038010_SQ_SEL_Z;
 935         case PIPE_SWIZZLE_ALPHA:
 936                 return V_038010_SQ_SEL_W;
 937         case PIPE_SWIZZLE_ZERO:
 938                 return V_038010_SQ_SEL_0;
 939         default:
 940         case PIPE_SWIZZLE_ONE:
 941                 return V_038010_SQ_SEL_1;
 942         }
 943 }
 944
 945 static inline unsigned r600_format_type(unsigned format_type)
 946 {
 947         switch (format_type) {
 948         default:
 949         case UTIL_FORMAT_TYPE_UNSIGNED:
 950                 return V_038010_SQ_FORMAT_COMP_UNSIGNED;
 951         case UTIL_FORMAT_TYPE_SIGNED:
 952                 return V_038010_SQ_FORMAT_COMP_SIGNED;
 953         case UTIL_FORMAT_TYPE_FIXED:
 954                 return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED;
 955         }
 956 }
 957
 958 static inline unsigned r600_tex_dim(unsigned dim)
 959 {
 960         switch (dim) {
 961         default:
 962         case PIPE_TEXTURE_1D:
 963                 return V_038000_SQ_TEX_DIM_1D;
 964         case PIPE_TEXTURE_2D:
 965                 return V_038000_SQ_TEX_DIM_2D;
 966         case PIPE_TEXTURE_3D:
 967                 return V_038000_SQ_TEX_DIM_3D;
 968         case PIPE_TEXTURE_CUBE:
 969                 return V_038000_SQ_TEX_DIM_CUBEMAP;
 970         }
 971 }
 972
 973 static struct radeon_state *r600_resource(struct r600_context *rctx,
 974                                         const struct pipe_sampler_view *view,
 975                                         unsigned id)
 976 {
 977         struct r600_screen *rscreen = rctx->screen;
 978         const struct util_format_description *desc;
 979         struct r600_resource_texture *tmp;
 980         struct r600_resource *rbuffer;
 981         struct radeon_state *rstate;
 982         unsigned format;
 983
 984         if (r600_conv_pipe_format(view->texture->format, &format))
 985                 return NULL;
 986         desc = util_format_description(view->texture->format);
 987         assert(desc == NULL);
 988         rstate = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, id);
 989         if (rstate == NULL) {
 990                 return NULL;
 991         }
 992         tmp = (struct r600_resource_texture*)view->texture;
 993         rbuffer = &tmp->resource;
 994         rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 995         rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 996         rstate->nbo = 2;
 997         rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 998         rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
 999         rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
1000         rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
1001
1002         /* FIXME properly handle first level != 0 */
1003         rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
1004                         S_038000_DIM(r600_tex_dim(view->texture->target)) |
1005                         S_038000_PITCH((tmp->pitch[0] / 8) - 1) |
1006                         S_038000_TEX_WIDTH(view->texture->width0 - 1);
1007         rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
1008                         S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
1009                         S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
1010                         S_038004_DATA_FORMAT(format);
1011         rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = 0;
1012         rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
1013         rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
1014                         S_038010_FORMAT_COMP_X(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
1015                         S_038010_FORMAT_COMP_Y(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
1016                         S_038010_FORMAT_COMP_Z(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
1017                         S_038010_FORMAT_COMP_W(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
1018                         S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
1019                         S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
1020                         S_038010_REQUEST_SIZE(1) |
1021                         S_038010_DST_SEL_X(r600_tex_swizzle(view->swizzle_r)) |
1022                         S_038010_DST_SEL_Y(r600_tex_swizzle(view->swizzle_g)) |
1023                         S_038010_DST_SEL_Z(r600_tex_swizzle(view->swizzle_b)) |
1024                         S_038010_DST_SEL_W(r600_tex_swizzle(view->swizzle_a)) |
1025                         S_038010_BASE_LEVEL(view->first_level);
1026         rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
1027                         S_038014_LAST_LEVEL(view->last_level) |
1028                         S_038014_BASE_ARRAY(0) |
1029                         S_038014_LAST_ARRAY(0);
1030         rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
1031                         S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
1032         if (radeon_state_pm4(rstate)) {
1033                 radeon_state_decref(rstate);
1034                 return NULL;
1035         }
1036         return rstate;
1037 }
1038
1039 int r600_context_hw_states(struct r600_context *rctx)
1040 {
1041         unsigned i;
1042         int r;
1043
1044         /* free previous TODO determine what need to be updated, what
1045          * doesn't
1046          */
1047         //radeon_state_decref(rctx->hw_states.config);
1048         //radeon_state_decref(rctx->hw_states.cb_cntl);
1049         radeon_state_decref(rctx->hw_states.db);
1050         radeon_state_decref(rctx->hw_states.rasterizer);
1051         radeon_state_decref(rctx->hw_states.scissor);
1052         radeon_state_decref(rctx->hw_states.dsa);
1053         radeon_state_decref(rctx->hw_states.blend);
1054         radeon_state_decref(rctx->hw_states.viewport);
1055         radeon_state_decref(rctx->hw_states.cb0);
1056         for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
1057                 radeon_state_decref(rctx->hw_states.ps_resource[i]);
1058                 rctx->hw_states.ps_resource[i] = NULL;
1059         }
1060         rctx->hw_states.ps_nresource = 0;
1061         for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
1062                 radeon_state_decref(rctx->hw_states.ps_sampler[i]);
1063                 rctx->hw_states.ps_sampler[i] = NULL;
1064         }
1065         rctx->hw_states.ps_nsampler = 0;
1066
1067         /* build new states */
1068         rctx->hw_states.rasterizer = r600_rasterizer(rctx);
1069         rctx->hw_states.scissor = r600_scissor(rctx);
1070         rctx->hw_states.dsa = r600_dsa(rctx);
1071         rctx->hw_states.blend = r600_blend(rctx);
1072         rctx->hw_states.viewport = r600_viewport(rctx);
1073         rctx->hw_states.cb0 = r600_cb0(rctx);
1074         rctx->hw_states.db = r600_db(rctx);
1075         for (i = 0; i < rctx->ps_nsampler; i++) {
1076                 if (rctx->ps_sampler[i]) {
1077                         rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
1078                                                         &rctx->ps_sampler[i]->state.sampler,
1079                                                         R600_PS_SAMPLER + i);
1080                 }
1081         }
1082         rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
1083         for (i = 0; i < rctx->ps_nsampler_view; i++) {
1084                 if (rctx->ps_sampler_view[i]) {
1085                         rctx->hw_states.ps_resource[i] = r600_resource(rctx,
1086                                                         &rctx->ps_sampler_view[i]->state.sampler_view,
1087                                                         R600_PS_RESOURCE + i);
1088                 }
1089         }
1090         rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
1091
1092         /* bind states */
1093         r = radeon_draw_set(rctx->draw, rctx->hw_states.db);
1094         if (r)
1095                 return r;
1096         r = radeon_draw_set(rctx->draw, rctx->hw_states.rasterizer);
1097         if (r)
1098                 return r;
1099         r = radeon_draw_set(rctx->draw, rctx->hw_states.scissor);
1100         if (r)
1101                 return r;
1102         r = radeon_draw_set(rctx->draw, rctx->hw_states.dsa);
1103         if (r)
1104                 return r;
1105         r = radeon_draw_set(rctx->draw, rctx->hw_states.blend);
1106         if (r)
1107                 return r;
1108         r = radeon_draw_set(rctx->draw, rctx->hw_states.viewport);
1109         if (r)
1110                 return r;
1111         r = radeon_draw_set(rctx->draw, rctx->hw_states.cb0);
1112         if (r)
1113                 return r;
1114         r = radeon_draw_set(rctx->draw, rctx->hw_states.config);
1115         if (r)
1116                 return r;
1117         r = radeon_draw_set(rctx->draw, rctx->hw_states.cb_cntl);
1118         if (r)
1119                 return r;
1120         for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
1121                 if (rctx->hw_states.ps_resource[i]) {
1122                         r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_resource[i]);
1123                         if (r)
1124                                 return r;
1125                 }
1126         }
1127         for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
1128                 if (rctx->hw_states.ps_sampler[i]) {
1129                         r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_sampler[i]);
1130                         if (r)
1131                                 return r;
1132                 }
1133         }
1134         return 0;
1135 }