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r600: define some values for the fetch constant offsets.
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
145 {
146 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
147 }
148
149 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
150 {
151 return r600_translate_colorformat(chip, format) != ~0U &&
152 r600_translate_colorswap(format) != ~0U;
153 }
154
155 static bool r600_is_zs_format_supported(enum pipe_format format)
156 {
157 return r600_translate_dbformat(format) != ~0U;
158 }
159
160 boolean r600_is_format_supported(struct pipe_screen *screen,
161 enum pipe_format format,
162 enum pipe_texture_target target,
163 unsigned sample_count,
164 unsigned usage)
165 {
166 struct r600_screen *rscreen = (struct r600_screen*)screen;
167 unsigned retval = 0;
168
169 if (target >= PIPE_MAX_TEXTURE_TYPES) {
170 R600_ERR("r600: unsupported texture type %d\n", target);
171 return FALSE;
172 }
173
174 if (!util_format_is_supported(format, usage))
175 return FALSE;
176
177 if (sample_count > 1) {
178 if (!rscreen->has_msaa)
179 return FALSE;
180
181 /* R11G11B10 is broken on R6xx. */
182 if (rscreen->b.chip_class == R600 &&
183 format == PIPE_FORMAT_R11G11B10_FLOAT)
184 return FALSE;
185
186 /* MSAA integer colorbuffers hang. */
187 if (util_format_is_pure_integer(format) &&
188 !util_format_is_depth_or_stencil(format))
189 return FALSE;
190
191 switch (sample_count) {
192 case 2:
193 case 4:
194 case 8:
195 break;
196 default:
197 return FALSE;
198 }
199 }
200
201 if (usage & PIPE_BIND_SAMPLER_VIEW) {
202 if (target == PIPE_BUFFER) {
203 if (r600_is_vertex_format_supported(format))
204 retval |= PIPE_BIND_SAMPLER_VIEW;
205 } else {
206 if (r600_is_sampler_format_supported(screen, format))
207 retval |= PIPE_BIND_SAMPLER_VIEW;
208 }
209 }
210
211 if ((usage & (PIPE_BIND_RENDER_TARGET |
212 PIPE_BIND_DISPLAY_TARGET |
213 PIPE_BIND_SCANOUT |
214 PIPE_BIND_SHARED |
215 PIPE_BIND_BLENDABLE)) &&
216 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
217 retval |= usage &
218 (PIPE_BIND_RENDER_TARGET |
219 PIPE_BIND_DISPLAY_TARGET |
220 PIPE_BIND_SCANOUT |
221 PIPE_BIND_SHARED);
222 if (!util_format_is_pure_integer(format) &&
223 !util_format_is_depth_or_stencil(format))
224 retval |= usage & PIPE_BIND_BLENDABLE;
225 }
226
227 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
228 r600_is_zs_format_supported(format)) {
229 retval |= PIPE_BIND_DEPTH_STENCIL;
230 }
231
232 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
233 r600_is_vertex_format_supported(format)) {
234 retval |= PIPE_BIND_VERTEX_BUFFER;
235 }
236
237 if (usage & PIPE_BIND_TRANSFER_READ)
238 retval |= PIPE_BIND_TRANSFER_READ;
239 if (usage & PIPE_BIND_TRANSFER_WRITE)
240 retval |= PIPE_BIND_TRANSFER_WRITE;
241
242 return retval == usage;
243 }
244
245 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
246 {
247 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
248 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
249 float offset_units = state->offset_units;
250 float offset_scale = state->offset_scale;
251
252 switch (state->zs_format) {
253 case PIPE_FORMAT_Z24X8_UNORM:
254 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
255 offset_units *= 2.0f;
256 break;
257 case PIPE_FORMAT_Z16_UNORM:
258 offset_units *= 4.0f;
259 break;
260 default:;
261 }
262
263 radeon_set_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
264 radeon_emit(cs, fui(offset_scale));
265 radeon_emit(cs, fui(offset_units));
266 radeon_emit(cs, fui(offset_scale));
267 radeon_emit(cs, fui(offset_units));
268 }
269
270 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
271 {
272 int j = state->independent_blend_enable ? i : 0;
273
274 unsigned eqRGB = state->rt[j].rgb_func;
275 unsigned srcRGB = state->rt[j].rgb_src_factor;
276 unsigned dstRGB = state->rt[j].rgb_dst_factor;
277
278 unsigned eqA = state->rt[j].alpha_func;
279 unsigned srcA = state->rt[j].alpha_src_factor;
280 unsigned dstA = state->rt[j].alpha_dst_factor;
281 uint32_t bc = 0;
282
283 if (!state->rt[j].blend_enable)
284 return 0;
285
286 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
287 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
288 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
289
290 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
291 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
292 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
293 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
294 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
295 }
296 return bc;
297 }
298
299 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
300 const struct pipe_blend_state *state,
301 int mode)
302 {
303 struct r600_context *rctx = (struct r600_context *)ctx;
304 uint32_t color_control = 0, target_mask = 0;
305 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
306
307 if (!blend) {
308 return NULL;
309 }
310
311 r600_init_command_buffer(&blend->buffer, 20);
312 r600_init_command_buffer(&blend->buffer_no_blend, 20);
313
314 /* R600 does not support per-MRT blends */
315 if (rctx->b.family > CHIP_R600)
316 color_control |= S_028808_PER_MRT_BLEND(1);
317
318 if (state->logicop_enable) {
319 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
320 } else {
321 color_control |= (0xcc << 16);
322 }
323 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
324 if (state->independent_blend_enable) {
325 for (int i = 0; i < 8; i++) {
326 if (state->rt[i].blend_enable) {
327 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
328 }
329 target_mask |= (state->rt[i].colormask << (4 * i));
330 }
331 } else {
332 for (int i = 0; i < 8; i++) {
333 if (state->rt[0].blend_enable) {
334 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
335 }
336 target_mask |= (state->rt[0].colormask << (4 * i));
337 }
338 }
339
340 if (target_mask)
341 color_control |= S_028808_SPECIAL_OP(mode);
342 else
343 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
344
345 /* only MRT0 has dual src blend */
346 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
347 blend->cb_target_mask = target_mask;
348 blend->cb_color_control = color_control;
349 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
350 blend->alpha_to_one = state->alpha_to_one;
351
352 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
353 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
354 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
355 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
356 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
357 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
358
359 /* Copy over the registers set so far into buffer_no_blend. */
360 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
361 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
362
363 /* Only add blend registers if blending is enabled. */
364 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
365 return blend;
366 }
367
368 /* The first R600 does not support per-MRT blends */
369 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
370 r600_get_blend_control(state, 0));
371
372 if (rctx->b.family > CHIP_R600) {
373 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
374 for (int i = 0; i < 8; i++) {
375 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
376 }
377 }
378 return blend;
379 }
380
381 static void *r600_create_blend_state(struct pipe_context *ctx,
382 const struct pipe_blend_state *state)
383 {
384 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
385 }
386
387 static void *r600_create_dsa_state(struct pipe_context *ctx,
388 const struct pipe_depth_stencil_alpha_state *state)
389 {
390 unsigned db_depth_control, alpha_test_control, alpha_ref;
391 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
392
393 if (dsa == NULL) {
394 return NULL;
395 }
396
397 r600_init_command_buffer(&dsa->buffer, 3);
398
399 dsa->valuemask[0] = state->stencil[0].valuemask;
400 dsa->valuemask[1] = state->stencil[1].valuemask;
401 dsa->writemask[0] = state->stencil[0].writemask;
402 dsa->writemask[1] = state->stencil[1].writemask;
403 dsa->zwritemask = state->depth.writemask;
404
405 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
406 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
407 S_028800_ZFUNC(state->depth.func);
408
409 /* stencil */
410 if (state->stencil[0].enabled) {
411 db_depth_control |= S_028800_STENCIL_ENABLE(1);
412 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
413 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
414 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
415 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
416
417 if (state->stencil[1].enabled) {
418 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
419 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
420 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
421 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
422 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
423 }
424 }
425
426 /* alpha */
427 alpha_test_control = 0;
428 alpha_ref = 0;
429 if (state->alpha.enabled) {
430 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
431 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
432 alpha_ref = fui(state->alpha.ref_value);
433 }
434 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
435 dsa->alpha_ref = alpha_ref;
436
437 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
438 return dsa;
439 }
440
441 static void *r600_create_rs_state(struct pipe_context *ctx,
442 const struct pipe_rasterizer_state *state)
443 {
444 struct r600_context *rctx = (struct r600_context *)ctx;
445 unsigned tmp, sc_mode_cntl, spi_interp;
446 float psize_min, psize_max;
447 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
448
449 if (rs == NULL) {
450 return NULL;
451 }
452
453 r600_init_command_buffer(&rs->buffer, 30);
454
455 rs->flatshade = state->flatshade;
456 rs->sprite_coord_enable = state->sprite_coord_enable;
457 rs->two_side = state->light_twoside;
458 rs->clip_plane_enable = state->clip_plane_enable;
459 rs->pa_sc_line_stipple = state->line_stipple_enable ?
460 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
461 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
462 rs->pa_cl_clip_cntl =
463 S_028810_PS_UCP_MODE(3) |
464 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
465 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
466 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
467 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
468 if (rctx->b.chip_class == R700) {
469 rs->pa_cl_clip_cntl |=
470 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
471 }
472 rs->multisample_enable = state->multisample;
473
474 /* offset */
475 rs->offset_units = state->offset_units;
476 rs->offset_scale = state->offset_scale * 16.0f;
477 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
478
479 if (state->point_size_per_vertex) {
480 psize_min = util_get_min_point_size(state);
481 psize_max = 8192;
482 } else {
483 /* Force the point size to be as if the vertex output was disabled. */
484 psize_min = state->point_size;
485 psize_max = state->point_size;
486 }
487
488 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
489 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
490 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
491 S_028A4C_PS_ITER_SAMPLE(state->multisample && rctx->ps_iter_samples > 1);
492 if (rctx->b.family == CHIP_RV770) {
493 /* workaround possible rendering corruption on RV770 with hyperz together with sample shading */
494 sc_mode_cntl |= S_028A4C_TILE_COVER_DISABLE(state->multisample && rctx->ps_iter_samples > 1);
495 }
496 if (rctx->b.chip_class >= R700) {
497 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
498 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
499 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
500 } else {
501 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
502 rs->scissor_enable = state->scissor;
503 }
504
505 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
506 if (state->sprite_coord_enable) {
507 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
508 S_0286D4_PNT_SPRITE_OVRD_X(2) |
509 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
510 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
511 S_0286D4_PNT_SPRITE_OVRD_W(1);
512 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
513 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
514 }
515 }
516
517 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
518 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
519 tmp = r600_pack_float_12p4(state->point_size/2);
520 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
521 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
522 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
523 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
524 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
525 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
526 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
527
528 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
529 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
530 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
531 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
532 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
533 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
534
535 rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
536 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
537 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
538 S_028814_FACE(!state->front_ccw) |
539 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
540 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
541 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
542 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
543 state->fill_back != PIPE_POLYGON_MODE_FILL) |
544 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
545 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
546 if (rctx->b.chip_class == R700) {
547 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl);
548 }
549 if (rctx->b.chip_class == R600) {
550 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC,
551 S_028350_MULTIPASS(state->rasterizer_discard));
552 }
553 return rs;
554 }
555
556 static void *r600_create_sampler_state(struct pipe_context *ctx,
557 const struct pipe_sampler_state *state)
558 {
559 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
560 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
561
562 if (ss == NULL) {
563 return NULL;
564 }
565
566 ss->seamless_cube_map = state->seamless_cube_map;
567 ss->border_color_use = sampler_state_needs_border_color(state);
568
569 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
570 ss->tex_sampler_words[0] =
571 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
572 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
573 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
574 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
575 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
576 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
577 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
578 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
579 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
580 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
581 ss->tex_sampler_words[1] =
582 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
583 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
584 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
585 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
586 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
587
588 if (ss->border_color_use) {
589 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
590 }
591 return ss;
592 }
593
594 static struct pipe_sampler_view *
595 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
596 unsigned width0, unsigned height0)
597
598 {
599 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
600 int stride = util_format_get_blocksize(view->base.format);
601 unsigned format, num_format, format_comp, endian;
602 uint64_t offset = view->base.u.buf.first_element * stride;
603 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
604
605 r600_vertex_data_type(view->base.format,
606 &format, &num_format, &format_comp,
607 &endian);
608
609 view->tex_resource = &tmp->resource;
610 view->skip_mip_address_reloc = true;
611
612 view->tex_resource_words[0] = offset;
613 view->tex_resource_words[1] = size - 1;
614 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(offset >> 32UL) |
615 S_038008_STRIDE(stride) |
616 S_038008_DATA_FORMAT(format) |
617 S_038008_NUM_FORMAT_ALL(num_format) |
618 S_038008_FORMAT_COMP_ALL(format_comp) |
619 S_038008_ENDIAN_SWAP(endian);
620 view->tex_resource_words[3] = 0;
621 /*
622 * in theory dword 4 is for number of elements, for use with resinfo,
623 * but it seems to utterly fail to work, the amd gpu shader analyser
624 * uses a const buffer to store the element sizes for buffer txq
625 */
626 view->tex_resource_words[4] = 0;
627 view->tex_resource_words[5] = 0;
628 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
629 return &view->base;
630 }
631
632 struct pipe_sampler_view *
633 r600_create_sampler_view_custom(struct pipe_context *ctx,
634 struct pipe_resource *texture,
635 const struct pipe_sampler_view *state,
636 unsigned width_first_level, unsigned height_first_level)
637 {
638 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
639 struct r600_texture *tmp = (struct r600_texture*)texture;
640 unsigned format, endian;
641 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
642 unsigned char swizzle[4], array_mode = 0;
643 unsigned width, height, depth, offset_level, last_level;
644
645 if (view == NULL)
646 return NULL;
647
648 /* initialize base object */
649 view->base = *state;
650 view->base.texture = NULL;
651 pipe_reference(NULL, &texture->reference);
652 view->base.texture = texture;
653 view->base.reference.count = 1;
654 view->base.context = ctx;
655
656 if (texture->target == PIPE_BUFFER)
657 return texture_buffer_sampler_view(view, texture->width0, 1);
658
659 swizzle[0] = state->swizzle_r;
660 swizzle[1] = state->swizzle_g;
661 swizzle[2] = state->swizzle_b;
662 swizzle[3] = state->swizzle_a;
663
664 format = r600_translate_texformat(ctx->screen, state->format,
665 swizzle,
666 &word4, &yuv_format);
667 assert(format != ~0);
668 if (format == ~0) {
669 FREE(view);
670 return NULL;
671 }
672
673 if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) {
674 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
675 FREE(view);
676 return NULL;
677 }
678 tmp = tmp->flushed_depth_texture;
679 }
680
681 endian = r600_colorformat_endian_swap(format);
682
683 offset_level = state->u.tex.first_level;
684 last_level = state->u.tex.last_level - offset_level;
685 width = width_first_level;
686 height = height_first_level;
687 depth = u_minify(texture->depth0, offset_level);
688 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
689
690 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
691 height = 1;
692 depth = texture->array_size;
693 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
694 depth = texture->array_size;
695 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
696 depth = texture->array_size / 6;
697 switch (tmp->surface.level[offset_level].mode) {
698 case RADEON_SURF_MODE_LINEAR_ALIGNED:
699 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
700 break;
701 case RADEON_SURF_MODE_1D:
702 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
703 break;
704 case RADEON_SURF_MODE_2D:
705 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
706 break;
707 case RADEON_SURF_MODE_LINEAR:
708 default:
709 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
710 break;
711 }
712
713 view->tex_resource = &tmp->resource;
714 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
715 S_038000_TILE_MODE(array_mode) |
716 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
717 S_038000_PITCH((pitch / 8) - 1) |
718 S_038000_TEX_WIDTH(width - 1));
719 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
720 S_038004_TEX_DEPTH(depth - 1) |
721 S_038004_DATA_FORMAT(format));
722 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
723 if (offset_level >= tmp->surface.last_level) {
724 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
725 } else {
726 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
727 }
728 view->tex_resource_words[4] = (word4 |
729 S_038010_REQUEST_SIZE(1) |
730 S_038010_ENDIAN_SWAP(endian) |
731 S_038010_BASE_LEVEL(0));
732 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
733 S_038014_LAST_ARRAY(state->u.tex.last_layer));
734 if (texture->nr_samples > 1) {
735 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
736 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
737 } else {
738 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
739 }
740 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
741 S_038018_MAX_ANISO(4 /* max 16 samples */));
742 return &view->base;
743 }
744
745 static struct pipe_sampler_view *
746 r600_create_sampler_view(struct pipe_context *ctx,
747 struct pipe_resource *tex,
748 const struct pipe_sampler_view *state)
749 {
750 return r600_create_sampler_view_custom(ctx, tex, state,
751 u_minify(tex->width0, state->u.tex.first_level),
752 u_minify(tex->height0, state->u.tex.first_level));
753 }
754
755 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
756 {
757 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
758 struct pipe_clip_state *state = &rctx->clip_state.state;
759
760 radeon_set_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
761 radeon_emit_array(cs, (unsigned*)state, 6*4);
762 }
763
764 static void r600_set_polygon_stipple(struct pipe_context *ctx,
765 const struct pipe_poly_stipple *state)
766 {
767 }
768
769 static void r600_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
770 {
771 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
772 struct r600_scissor_state *rstate = &rctx->scissor;
773 struct pipe_scissor_state *state;
774 bool do_disable_workaround = false;
775 uint32_t dirty_mask;
776 unsigned i, offset;
777 uint32_t tl, br;
778
779 if (rctx->b.chip_class == R600 && !rctx->scissor.enable) {
780 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
781 br = S_028244_BR_X(8192) | S_028244_BR_Y(8192);
782 do_disable_workaround = true;
783 }
784
785 dirty_mask = rstate->dirty_mask;
786 while (dirty_mask != 0)
787 {
788 i = u_bit_scan(&dirty_mask);
789 offset = i * 4 * 2;
790 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + offset, 2);
791 if (!do_disable_workaround) {
792 state = &rstate->scissor[i];
793 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) |
794 S_028240_WINDOW_OFFSET_DISABLE(1);
795 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
796 }
797 radeon_emit(cs, tl);
798 radeon_emit(cs, br);
799 }
800 rstate->dirty_mask = 0;
801 rstate->atom.num_dw = 0;
802 }
803
804 static void r600_set_scissor_states(struct pipe_context *ctx,
805 unsigned start_slot,
806 unsigned num_scissors,
807 const struct pipe_scissor_state *state)
808 {
809 struct r600_context *rctx = (struct r600_context *)ctx;
810 struct r600_scissor_state *rstate = &rctx->scissor;
811 int i;
812
813 for (i = start_slot ; i < start_slot + num_scissors; i++)
814 rstate->scissor[i] = state[i - start_slot];
815 rstate->dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
816 rstate->atom.num_dw = util_bitcount(rstate->dirty_mask) * 4;
817
818 if (rctx->b.chip_class == R600 && !rstate->enable)
819 return;
820
821 r600_mark_atom_dirty(rctx, &rstate->atom);
822 }
823
824 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
825 unsigned size, unsigned alignment)
826 {
827 struct pipe_resource buffer;
828
829 memset(&buffer, 0, sizeof buffer);
830 buffer.target = PIPE_BUFFER;
831 buffer.format = PIPE_FORMAT_R8_UNORM;
832 buffer.bind = PIPE_BIND_CUSTOM;
833 buffer.usage = PIPE_USAGE_DEFAULT;
834 buffer.flags = 0;
835 buffer.width0 = size;
836 buffer.height0 = 1;
837 buffer.depth0 = 1;
838 buffer.array_size = 1;
839
840 return (struct r600_resource*)
841 r600_buffer_create(&rscreen->b.b, &buffer, alignment);
842 }
843
844 static void r600_init_color_surface(struct r600_context *rctx,
845 struct r600_surface *surf,
846 bool force_cmask_fmask)
847 {
848 struct r600_screen *rscreen = rctx->screen;
849 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
850 unsigned level = surf->base.u.tex.level;
851 unsigned pitch, slice;
852 unsigned color_info;
853 unsigned color_view;
854 unsigned format, swap, ntype, endian;
855 unsigned offset;
856 const struct util_format_description *desc;
857 int i;
858 bool blend_bypass = 0, blend_clamp = 1;
859
860 if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
861 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
862 rtex = rtex->flushed_depth_texture;
863 assert(rtex);
864 }
865
866 offset = rtex->surface.level[level].offset;
867 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
868 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
869 offset += rtex->surface.level[level].slice_size *
870 surf->base.u.tex.first_layer;
871 color_view = 0;
872 } else
873 color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
874 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
875
876 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
877 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
878 if (slice) {
879 slice = slice - 1;
880 }
881 color_info = 0;
882 switch (rtex->surface.level[level].mode) {
883 case RADEON_SURF_MODE_LINEAR_ALIGNED:
884 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
885 break;
886 case RADEON_SURF_MODE_1D:
887 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
888 break;
889 case RADEON_SURF_MODE_2D:
890 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
891 break;
892 case RADEON_SURF_MODE_LINEAR:
893 default:
894 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
895 break;
896 }
897
898 desc = util_format_description(surf->base.format);
899
900 for (i = 0; i < 4; i++) {
901 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
902 break;
903 }
904 }
905
906 ntype = V_0280A0_NUMBER_UNORM;
907 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
908 ntype = V_0280A0_NUMBER_SRGB;
909 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
910 if (desc->channel[i].normalized)
911 ntype = V_0280A0_NUMBER_SNORM;
912 else if (desc->channel[i].pure_integer)
913 ntype = V_0280A0_NUMBER_SINT;
914 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
915 if (desc->channel[i].normalized)
916 ntype = V_0280A0_NUMBER_UNORM;
917 else if (desc->channel[i].pure_integer)
918 ntype = V_0280A0_NUMBER_UINT;
919 }
920
921 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
922 assert(format != ~0);
923
924 swap = r600_translate_colorswap(surf->base.format);
925 assert(swap != ~0);
926
927 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
928 endian = ENDIAN_NONE;
929 } else {
930 endian = r600_colorformat_endian_swap(format);
931 }
932
933 /* set blend bypass according to docs if SINT/UINT or
934 8/24 COLOR variants */
935 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
936 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
937 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
938 blend_clamp = 0;
939 blend_bypass = 1;
940 }
941
942 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
943
944 color_info |= S_0280A0_FORMAT(format) |
945 S_0280A0_COMP_SWAP(swap) |
946 S_0280A0_BLEND_BYPASS(blend_bypass) |
947 S_0280A0_BLEND_CLAMP(blend_clamp) |
948 S_0280A0_NUMBER_TYPE(ntype) |
949 S_0280A0_ENDIAN(endian);
950
951 /* EXPORT_NORM is an optimzation that can be enabled for better
952 * performance in certain cases
953 */
954 if (rctx->b.chip_class == R600) {
955 /* EXPORT_NORM can be enabled if:
956 * - 11-bit or smaller UNORM/SNORM/SRGB
957 * - BLEND_CLAMP is enabled
958 * - BLEND_FLOAT32 is disabled
959 */
960 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
961 (desc->channel[i].size < 12 &&
962 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
963 ntype != V_0280A0_NUMBER_UINT &&
964 ntype != V_0280A0_NUMBER_SINT) &&
965 G_0280A0_BLEND_CLAMP(color_info) &&
966 !G_0280A0_BLEND_FLOAT32(color_info)) {
967 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
968 surf->export_16bpc = true;
969 }
970 } else {
971 /* EXPORT_NORM can be enabled if:
972 * - 11-bit or smaller UNORM/SNORM/SRGB
973 * - 16-bit or smaller FLOAT
974 */
975 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
976 ((desc->channel[i].size < 12 &&
977 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
978 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
979 (desc->channel[i].size < 17 &&
980 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
981 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
982 surf->export_16bpc = true;
983 }
984 }
985
986 /* These might not always be initialized to zero. */
987 surf->cb_color_base = offset >> 8;
988 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
989 S_028060_SLICE_TILE_MAX(slice);
990 surf->cb_color_fmask = surf->cb_color_base;
991 surf->cb_color_cmask = surf->cb_color_base;
992 surf->cb_color_mask = 0;
993
994 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
995 &rtex->resource.b.b);
996 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
997 &rtex->resource.b.b);
998
999 if (rtex->cmask.size) {
1000 surf->cb_color_cmask = rtex->cmask.offset >> 8;
1001 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
1002
1003 if (rtex->fmask.size) {
1004 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1005 surf->cb_color_fmask = rtex->fmask.offset >> 8;
1006 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
1007 } else { /* cmask only */
1008 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
1009 }
1010 } else if (force_cmask_fmask) {
1011 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1012 *
1013 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1014 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1015 * because it's not an MSAA buffer.
1016 */
1017 struct r600_cmask_info cmask;
1018 struct r600_fmask_info fmask;
1019
1020 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
1021 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
1022
1023 /* CMASK. */
1024 if (!rctx->dummy_cmask ||
1025 rctx->dummy_cmask->b.b.width0 < cmask.size ||
1026 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1027 struct pipe_transfer *transfer;
1028 void *ptr;
1029
1030 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1031 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1032
1033 /* Set the contents to 0xCC. */
1034 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1035 memset(ptr, 0xCC, cmask.size);
1036 pipe_buffer_unmap(&rctx->b.b, transfer);
1037 }
1038 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1039 &rctx->dummy_cmask->b.b);
1040
1041 /* FMASK. */
1042 if (!rctx->dummy_fmask ||
1043 rctx->dummy_fmask->b.b.width0 < fmask.size ||
1044 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1045 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1046 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1047
1048 }
1049 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1050 &rctx->dummy_fmask->b.b);
1051
1052 /* Init the registers. */
1053 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1054 surf->cb_color_cmask = 0;
1055 surf->cb_color_fmask = 0;
1056 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1057 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1058 }
1059
1060 surf->cb_color_info = color_info;
1061 surf->cb_color_view = color_view;
1062 surf->color_initialized = true;
1063 }
1064
1065 static void r600_init_depth_surface(struct r600_context *rctx,
1066 struct r600_surface *surf)
1067 {
1068 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1069 unsigned level, pitch, slice, format, offset, array_mode;
1070
1071 level = surf->base.u.tex.level;
1072 offset = rtex->surface.level[level].offset;
1073 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1074 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1075 if (slice) {
1076 slice = slice - 1;
1077 }
1078 switch (rtex->surface.level[level].mode) {
1079 case RADEON_SURF_MODE_2D:
1080 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1081 break;
1082 case RADEON_SURF_MODE_1D:
1083 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1084 case RADEON_SURF_MODE_LINEAR:
1085 default:
1086 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1087 break;
1088 }
1089
1090 format = r600_translate_dbformat(surf->base.format);
1091 assert(format != ~0);
1092
1093 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1094 surf->db_depth_base = offset >> 8;
1095 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1096 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1097 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1098 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1099
1100 switch (surf->base.format) {
1101 case PIPE_FORMAT_Z24X8_UNORM:
1102 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1103 surf->pa_su_poly_offset_db_fmt_cntl =
1104 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1105 break;
1106 case PIPE_FORMAT_Z32_FLOAT:
1107 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1108 surf->pa_su_poly_offset_db_fmt_cntl =
1109 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1110 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1111 break;
1112 case PIPE_FORMAT_Z16_UNORM:
1113 surf->pa_su_poly_offset_db_fmt_cntl =
1114 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1115 break;
1116 default:;
1117 }
1118
1119 /* use htile only for first level */
1120 if (rtex->htile_buffer && !level) {
1121 surf->db_htile_data_base = 0;
1122 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1123 S_028D24_HTILE_HEIGHT(1) |
1124 S_028D24_FULL_CACHE(1);
1125 /* preload is not working properly on r6xx/r7xx */
1126 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1127 }
1128
1129 surf->depth_initialized = true;
1130 }
1131
1132 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1133 const struct pipe_framebuffer_state *state)
1134 {
1135 struct r600_context *rctx = (struct r600_context *)ctx;
1136 struct r600_surface *surf;
1137 struct r600_texture *rtex;
1138 unsigned i;
1139
1140 if (rctx->framebuffer.state.nr_cbufs) {
1141 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1142 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1143 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1144 }
1145 if (rctx->framebuffer.state.zsbuf) {
1146 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1147 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1148
1149 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1150 if (rctx->b.chip_class >= R700 && rtex->htile_buffer) {
1151 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1152 }
1153 }
1154
1155 /* Set the new state. */
1156 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1157
1158 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1159 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1160 util_format_is_pure_integer(state->cbufs[0]->format);
1161 rctx->framebuffer.compressed_cb_mask = 0;
1162 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1163 state->cbufs[0] && state->cbufs[1] &&
1164 state->cbufs[0]->texture->nr_samples > 1 &&
1165 state->cbufs[1]->texture->nr_samples <= 1;
1166 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1167
1168 /* Colorbuffers. */
1169 for (i = 0; i < state->nr_cbufs; i++) {
1170 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1171 bool force_cmask_fmask = rctx->b.chip_class == R600 &&
1172 rctx->framebuffer.is_msaa_resolve &&
1173 i == 1;
1174
1175 surf = (struct r600_surface*)state->cbufs[i];
1176 if (!surf)
1177 continue;
1178
1179 rtex = (struct r600_texture*)surf->base.texture;
1180 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1181
1182 if (!surf->color_initialized || force_cmask_fmask) {
1183 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1184 if (force_cmask_fmask) {
1185 /* re-initialize later without compression */
1186 surf->color_initialized = false;
1187 }
1188 }
1189
1190 if (!surf->export_16bpc) {
1191 rctx->framebuffer.export_16bpc = false;
1192 }
1193
1194 if (rtex->fmask.size && rtex->cmask.size) {
1195 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1196 }
1197 }
1198
1199 /* Update alpha-test state dependencies.
1200 * Alpha-test is done on the first colorbuffer only. */
1201 if (state->nr_cbufs) {
1202 bool alphatest_bypass = false;
1203
1204 surf = (struct r600_surface*)state->cbufs[0];
1205 if (surf) {
1206 alphatest_bypass = surf->alphatest_bypass;
1207 }
1208
1209 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1210 rctx->alphatest_state.bypass = alphatest_bypass;
1211 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1212 }
1213 }
1214
1215 /* ZS buffer. */
1216 if (state->zsbuf) {
1217 surf = (struct r600_surface*)state->zsbuf;
1218
1219 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1220
1221 if (!surf->depth_initialized) {
1222 r600_init_depth_surface(rctx, surf);
1223 }
1224
1225 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1226 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1227 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1228 }
1229
1230 if (rctx->db_state.rsurf != surf) {
1231 rctx->db_state.rsurf = surf;
1232 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1233 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1234 }
1235 } else if (rctx->db_state.rsurf) {
1236 rctx->db_state.rsurf = NULL;
1237 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1238 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1239 }
1240
1241 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1242 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1243 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1244 }
1245
1246 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1247 rctx->alphatest_state.bypass = false;
1248 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1249 }
1250
1251 /* Calculate the CS size. */
1252 rctx->framebuffer.atom.num_dw =
1253 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1254
1255 if (rctx->framebuffer.state.nr_cbufs) {
1256 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
1257 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
1258 }
1259 if (rctx->framebuffer.state.zsbuf) {
1260 rctx->framebuffer.atom.num_dw += 16;
1261 } else if (rctx->screen->b.info.drm_minor >= 18) {
1262 rctx->framebuffer.atom.num_dw += 3;
1263 }
1264 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1265 rctx->framebuffer.atom.num_dw += 2;
1266 }
1267
1268 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1269
1270 r600_set_sample_locations_constant_buffer(rctx);
1271 }
1272
1273 static uint32_t sample_locs_2x[] = {
1274 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1275 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1276 };
1277 static unsigned max_dist_2x = 4;
1278
1279 static uint32_t sample_locs_4x[] = {
1280 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1281 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1282 };
1283 static unsigned max_dist_4x = 6;
1284 static uint32_t sample_locs_8x[] = {
1285 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1286 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1287 };
1288 static unsigned max_dist_8x = 7;
1289
1290 static void r600_get_sample_position(struct pipe_context *ctx,
1291 unsigned sample_count,
1292 unsigned sample_index,
1293 float *out_value)
1294 {
1295 int offset, index;
1296 struct {
1297 int idx:4;
1298 } val;
1299 switch (sample_count) {
1300 case 1:
1301 default:
1302 out_value[0] = out_value[1] = 0.5;
1303 break;
1304 case 2:
1305 offset = 4 * (sample_index * 2);
1306 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1307 out_value[0] = (float)(val.idx + 8) / 16.0f;
1308 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1309 out_value[1] = (float)(val.idx + 8) / 16.0f;
1310 break;
1311 case 4:
1312 offset = 4 * (sample_index * 2);
1313 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1314 out_value[0] = (float)(val.idx + 8) / 16.0f;
1315 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1316 out_value[1] = (float)(val.idx + 8) / 16.0f;
1317 break;
1318 case 8:
1319 offset = 4 * (sample_index % 4 * 2);
1320 index = (sample_index / 4);
1321 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1322 out_value[0] = (float)(val.idx + 8) / 16.0f;
1323 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1324 out_value[1] = (float)(val.idx + 8) / 16.0f;
1325 break;
1326 }
1327 }
1328
1329 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1330 {
1331 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1332 unsigned max_dist = 0;
1333
1334 if (rctx->b.family == CHIP_R600) {
1335 switch (nr_samples) {
1336 default:
1337 nr_samples = 0;
1338 break;
1339 case 2:
1340 radeon_set_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1341 max_dist = max_dist_2x;
1342 break;
1343 case 4:
1344 radeon_set_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1345 max_dist = max_dist_4x;
1346 break;
1347 case 8:
1348 radeon_set_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1349 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1350 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1351 max_dist = max_dist_8x;
1352 break;
1353 }
1354 } else {
1355 switch (nr_samples) {
1356 default:
1357 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1358 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1359 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1360 nr_samples = 0;
1361 break;
1362 case 2:
1363 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1364 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1365 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1366 max_dist = max_dist_2x;
1367 break;
1368 case 4:
1369 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1370 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1371 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1372 max_dist = max_dist_4x;
1373 break;
1374 case 8:
1375 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1376 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1377 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1378 max_dist = max_dist_8x;
1379 break;
1380 }
1381 }
1382
1383 if (nr_samples > 1) {
1384 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1385 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1386 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1387 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1388 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1389 } else {
1390 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1391 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1392 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1393 }
1394 }
1395
1396 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1397 {
1398 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1399 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1400 unsigned nr_cbufs = state->nr_cbufs;
1401 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1402 unsigned i, sbu = 0;
1403
1404 /* Colorbuffers. */
1405 radeon_set_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1406 for (i = 0; i < nr_cbufs; i++) {
1407 radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0);
1408 }
1409 /* set CB_COLOR1_INFO for possible dual-src blending */
1410 if (i == 1 && cb[0]) {
1411 radeon_emit(cs, cb[0]->cb_color_info);
1412 i++;
1413 }
1414 for (; i < 8; i++) {
1415 radeon_emit(cs, 0);
1416 }
1417
1418 if (nr_cbufs) {
1419 for (i = 0; i < nr_cbufs; i++) {
1420 unsigned reloc;
1421
1422 if (!cb[i])
1423 continue;
1424
1425 /* COLOR_BASE */
1426 radeon_set_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1427
1428 reloc = radeon_add_to_buffer_list(&rctx->b,
1429 &rctx->b.rings.gfx,
1430 (struct r600_resource*)cb[i]->base.texture,
1431 RADEON_USAGE_READWRITE,
1432 cb[i]->base.texture->nr_samples > 1 ?
1433 RADEON_PRIO_COLOR_BUFFER_MSAA :
1434 RADEON_PRIO_COLOR_BUFFER);
1435 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1436 radeon_emit(cs, reloc);
1437
1438 /* FMASK */
1439 radeon_set_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1440
1441 reloc = radeon_add_to_buffer_list(&rctx->b,
1442 &rctx->b.rings.gfx,
1443 cb[i]->cb_buffer_fmask,
1444 RADEON_USAGE_READWRITE,
1445 cb[i]->base.texture->nr_samples > 1 ?
1446 RADEON_PRIO_COLOR_BUFFER_MSAA :
1447 RADEON_PRIO_COLOR_BUFFER);
1448 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1449 radeon_emit(cs, reloc);
1450
1451 /* CMASK */
1452 radeon_set_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1453
1454 reloc = radeon_add_to_buffer_list(&rctx->b,
1455 &rctx->b.rings.gfx,
1456 cb[i]->cb_buffer_cmask,
1457 RADEON_USAGE_READWRITE,
1458 cb[i]->base.texture->nr_samples > 1 ?
1459 RADEON_PRIO_COLOR_BUFFER_MSAA :
1460 RADEON_PRIO_COLOR_BUFFER);
1461 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1462 radeon_emit(cs, reloc);
1463 }
1464
1465 radeon_set_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1466 for (i = 0; i < nr_cbufs; i++) {
1467 radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0);
1468 }
1469
1470 radeon_set_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1471 for (i = 0; i < nr_cbufs; i++) {
1472 radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0);
1473 }
1474
1475 radeon_set_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1476 for (i = 0; i < nr_cbufs; i++) {
1477 radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0);
1478 }
1479
1480 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1481 }
1482
1483 /* SURFACE_BASE_UPDATE */
1484 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1485 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1486 radeon_emit(cs, sbu);
1487 sbu = 0;
1488 }
1489
1490 /* Zbuffer. */
1491 if (state->zsbuf) {
1492 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1493 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1494 &rctx->b.rings.gfx,
1495 (struct r600_resource*)state->zsbuf->texture,
1496 RADEON_USAGE_READWRITE,
1497 surf->base.texture->nr_samples > 1 ?
1498 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1499 RADEON_PRIO_DEPTH_BUFFER);
1500
1501 radeon_set_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1502 surf->pa_su_poly_offset_db_fmt_cntl);
1503
1504 radeon_set_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1505 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1506 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1507 radeon_set_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1508 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1509 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1510
1511 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1512 radeon_emit(cs, reloc);
1513
1514 radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1515
1516 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1517 } else if (rctx->screen->b.info.drm_minor >= 18) {
1518 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1519 * Older kernels are out of luck. */
1520 radeon_set_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1521 }
1522
1523 /* SURFACE_BASE_UPDATE */
1524 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1525 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1526 radeon_emit(cs, sbu);
1527 sbu = 0;
1528 }
1529
1530 /* Framebuffer dimensions. */
1531 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1532 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1533 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1534 radeon_emit(cs, S_028244_BR_X(state->width) |
1535 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1536
1537 if (rctx->framebuffer.is_msaa_resolve) {
1538 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1539 } else {
1540 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1541 * will assure that the alpha-test will work even if there is
1542 * no colorbuffer bound. */
1543 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1544 (1ull << MAX2(nr_cbufs, 1)) - 1);
1545 }
1546
1547 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1548 }
1549
1550 static void r600_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1551 {
1552 struct r600_context *rctx = (struct r600_context *)ctx;
1553
1554 if (rctx->ps_iter_samples == min_samples)
1555 return;
1556
1557 rctx->ps_iter_samples = min_samples;
1558 if (rctx->framebuffer.nr_samples > 1) {
1559 r600_mark_atom_dirty(rctx, &rctx->rasterizer_state.atom);
1560 if (rctx->b.chip_class == R600)
1561 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1562 }
1563 }
1564
1565 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1566 {
1567 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1568 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1569
1570 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1571 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1572 if (rctx->b.chip_class == R600) {
1573 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1574 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1575 } else {
1576 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1577 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1578 }
1579 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1580 } else {
1581 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1582 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1583 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1584
1585 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1586 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1587 /* Always enable the first color output to make sure alpha-test works even without one. */
1588 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1589 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1590 a->cb_color_control |
1591 S_028808_MULTIWRITE_ENABLE(multiwrite));
1592 }
1593 }
1594
1595 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1596 {
1597 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1598 struct r600_db_state *a = (struct r600_db_state*)atom;
1599
1600 if (a->rsurf && a->rsurf->db_htile_surface) {
1601 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1602 unsigned reloc_idx;
1603
1604 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1605 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1606 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1607 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer,
1608 RADEON_USAGE_READWRITE, RADEON_PRIO_DEPTH_META);
1609 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1610 cs->buf[cs->cdw++] = reloc_idx;
1611 } else {
1612 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1613 }
1614 }
1615
1616 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1617 {
1618 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1619 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1620 unsigned db_render_control = 0;
1621 unsigned db_render_override =
1622 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1623 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1624
1625 if (a->occlusion_query_enabled) {
1626 if (rctx->b.chip_class >= R700) {
1627 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1628 }
1629 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1630 }
1631 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
1632 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1633 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1634 /* This is to fix a lockup when hyperz and alpha test are enabled at
1635 * the same time somehow GPU get confuse on which order to pick for
1636 * z test
1637 */
1638 if (rctx->alphatest_state.sx_alpha_test_control) {
1639 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
1640 }
1641 } else {
1642 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1643 }
1644 if (rctx->b.chip_class == R600 && rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) {
1645 /* sample shading and hyperz causes lockups on R6xx chips */
1646 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1647 }
1648 if (a->flush_depthstencil_through_cb) {
1649 assert(a->copy_depth || a->copy_stencil);
1650
1651 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1652 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1653 S_028D0C_COPY_CENTROID(1) |
1654 S_028D0C_COPY_SAMPLE(a->copy_sample);
1655
1656 if (rctx->b.chip_class == R600)
1657 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1658
1659 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
1660 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
1661 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1662 } else if (a->flush_depthstencil_in_place) {
1663 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(1) |
1664 S_028D0C_STENCIL_COMPRESS_DISABLE(1);
1665 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1666 }
1667 if (a->htile_clear) {
1668 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1669 }
1670
1671 /* RV770 workaround for a hang with 8x MSAA. */
1672 if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) {
1673 db_render_override |= S_028D10_MAX_TILES_IN_DTT(6);
1674 }
1675
1676 radeon_set_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1677 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1678 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1679 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1680 }
1681
1682 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1683 {
1684 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1685 struct r600_config_state *a = (struct r600_config_state*)atom;
1686
1687 radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1688 radeon_set_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
1689 }
1690
1691 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1692 {
1693 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1694 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1695
1696 while (dirty_mask) {
1697 struct pipe_vertex_buffer *vb;
1698 struct r600_resource *rbuffer;
1699 unsigned offset;
1700 unsigned buffer_index = u_bit_scan(&dirty_mask);
1701
1702 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1703 rbuffer = (struct r600_resource*)vb->buffer;
1704 assert(rbuffer);
1705
1706 offset = vb->buffer_offset;
1707
1708 /* fetch resources start at index 320 (OFFSET_FS) */
1709 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1710 radeon_emit(cs, (R600_FETCH_CONSTANTS_OFFSET_FS + buffer_index) * 7);
1711 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1712 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1713 radeon_emit(cs, /* RESOURCEi_WORD2 */
1714 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1715 S_038008_STRIDE(vb->stride));
1716 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1717 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1718 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1719 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1720
1721 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1722 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1723 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1724 }
1725 }
1726
1727 static void r600_emit_constant_buffers(struct r600_context *rctx,
1728 struct r600_constbuf_state *state,
1729 unsigned buffer_id_base,
1730 unsigned reg_alu_constbuf_size,
1731 unsigned reg_alu_const_cache)
1732 {
1733 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1734 uint32_t dirty_mask = state->dirty_mask;
1735
1736 while (dirty_mask) {
1737 struct pipe_constant_buffer *cb;
1738 struct r600_resource *rbuffer;
1739 unsigned offset;
1740 unsigned buffer_index = ffs(dirty_mask) - 1;
1741 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1742 cb = &state->cb[buffer_index];
1743 rbuffer = (struct r600_resource*)cb->buffer;
1744 assert(rbuffer);
1745
1746 offset = cb->buffer_offset;
1747
1748 if (!gs_ring_buffer) {
1749 radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1750 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1751 radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1752 }
1753
1754 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1755 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1756 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1757
1758 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1759 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
1760 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1761 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1762 radeon_emit(cs, /* RESOURCEi_WORD2 */
1763 S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1764 S_038008_STRIDE(gs_ring_buffer ? 4 : 16));
1765 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1766 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1767 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1768 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1769
1770 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1771 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1772 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1773
1774 dirty_mask &= ~(1 << buffer_index);
1775 }
1776 state->dirty_mask = 0;
1777 }
1778
1779 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1780 {
1781 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1782 R600_FETCH_CONSTANTS_OFFSET_VS,
1783 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1784 R_028980_ALU_CONST_CACHE_VS_0);
1785 }
1786
1787 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1788 {
1789 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1790 R600_FETCH_CONSTANTS_OFFSET_GS,
1791 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1792 R_0289C0_ALU_CONST_CACHE_GS_0);
1793 }
1794
1795 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1796 {
1797 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1798 R600_FETCH_CONSTANTS_OFFSET_PS,
1799 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1800 R_028940_ALU_CONST_CACHE_PS_0);
1801 }
1802
1803 static void r600_emit_sampler_views(struct r600_context *rctx,
1804 struct r600_samplerview_state *state,
1805 unsigned resource_id_base)
1806 {
1807 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1808 uint32_t dirty_mask = state->dirty_mask;
1809
1810 while (dirty_mask) {
1811 struct r600_pipe_sampler_view *rview;
1812 unsigned resource_index = u_bit_scan(&dirty_mask);
1813 unsigned reloc;
1814
1815 rview = state->views[resource_index];
1816 assert(rview);
1817
1818 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1819 radeon_emit(cs, (resource_id_base + resource_index) * 7);
1820 radeon_emit_array(cs, rview->tex_resource_words, 7);
1821
1822 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rview->tex_resource,
1823 RADEON_USAGE_READ,
1824 rview->tex_resource->b.b.nr_samples > 1 ?
1825 RADEON_PRIO_SHADER_TEXTURE_MSAA :
1826 RADEON_PRIO_SHADER_TEXTURE_RO);
1827 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1828 radeon_emit(cs, reloc);
1829 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1830 radeon_emit(cs, reloc);
1831 }
1832 state->dirty_mask = 0;
1833 }
1834
1835
1836 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1837 {
1838 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, R600_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS);
1839 }
1840
1841 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1842 {
1843 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, R600_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS);
1844 }
1845
1846 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1847 {
1848 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS);
1849 }
1850
1851 static void r600_emit_sampler_states(struct r600_context *rctx,
1852 struct r600_textures_info *texinfo,
1853 unsigned resource_id_base,
1854 unsigned border_color_reg)
1855 {
1856 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1857 uint32_t dirty_mask = texinfo->states.dirty_mask;
1858
1859 while (dirty_mask) {
1860 struct r600_pipe_sampler_state *rstate;
1861 struct r600_pipe_sampler_view *rview;
1862 unsigned i = u_bit_scan(&dirty_mask);
1863
1864 rstate = texinfo->states.states[i];
1865 assert(rstate);
1866 rview = texinfo->views.views[i];
1867
1868 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1869 * filtering between layers.
1870 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1871 */
1872 if (rview) {
1873 enum pipe_texture_target target = rview->base.texture->target;
1874 if (target == PIPE_TEXTURE_1D_ARRAY ||
1875 target == PIPE_TEXTURE_2D_ARRAY) {
1876 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1877 texinfo->is_array_sampler[i] = true;
1878 } else {
1879 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1880 texinfo->is_array_sampler[i] = false;
1881 }
1882 }
1883
1884 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1885 radeon_emit(cs, (resource_id_base + i) * 3);
1886 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
1887
1888 if (rstate->border_color_use) {
1889 unsigned offset;
1890
1891 offset = border_color_reg;
1892 offset += i * 16;
1893 radeon_set_config_reg_seq(cs, offset, 4);
1894 radeon_emit_array(cs, rstate->border_color.ui, 4);
1895 }
1896 }
1897 texinfo->states.dirty_mask = 0;
1898 }
1899
1900 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1901 {
1902 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1903 }
1904
1905 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1906 {
1907 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1908 }
1909
1910 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1911 {
1912 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1913 }
1914
1915 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1916 {
1917 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1918 unsigned tmp;
1919
1920 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1921 S_009508_SYNC_GRADIENT(1) |
1922 S_009508_SYNC_WALKER(1) |
1923 S_009508_SYNC_ALIGNER(1);
1924 if (!rctx->seamless_cube_map.enabled) {
1925 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1926 }
1927 radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1928 }
1929
1930 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1931 {
1932 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1933 uint8_t mask = s->sample_mask;
1934
1935 radeon_set_context_reg(rctx->b.rings.gfx.cs, R_028C48_PA_SC_AA_MASK,
1936 mask | (mask << 8) | (mask << 16) | (mask << 24));
1937 }
1938
1939 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
1940 {
1941 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1942 struct r600_cso_state *state = (struct r600_cso_state*)a;
1943 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
1944
1945 radeon_set_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
1946 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1947 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, shader->buffer,
1948 RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA));
1949 }
1950
1951 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
1952 {
1953 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1954 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
1955
1956 uint32_t v2 = 0, primid = 0;
1957
1958 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
1959 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1960 primid = 1;
1961 }
1962
1963 if (state->geom_enable) {
1964 uint32_t cut_val;
1965
1966 if (rctx->gs_shader->gs_max_out_vertices <= 128)
1967 cut_val = V_028A40_GS_CUT_128;
1968 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
1969 cut_val = V_028A40_GS_CUT_256;
1970 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
1971 cut_val = V_028A40_GS_CUT_512;
1972 else
1973 cut_val = V_028A40_GS_CUT_1024;
1974
1975 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1976 S_028A40_CUT_MODE(cut_val);
1977
1978 if (rctx->gs_shader->current->shader.gs_prim_id_input)
1979 primid = 1;
1980 }
1981
1982 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
1983 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
1984 }
1985
1986 static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
1987 {
1988 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1989 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
1990 struct r600_resource *rbuffer;
1991
1992 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1993 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1994 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1995
1996 if (state->enable) {
1997 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
1998 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
1999 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2000 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rbuffer,
2001 RADEON_USAGE_READWRITE,
2002 RADEON_PRIO_SHADER_RESOURCE_RW));
2003 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2004 state->esgs_ring.buffer_size >> 8);
2005
2006 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2007 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
2008 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2009 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.gfx, rbuffer,
2010 RADEON_USAGE_READWRITE,
2011 RADEON_PRIO_SHADER_RESOURCE_RW));
2012 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2013 state->gsvs_ring.buffer_size >> 8);
2014 } else {
2015 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2016 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2017 }
2018
2019 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2020 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2021 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2022 }
2023
2024 /* Adjust GPR allocation on R6xx/R7xx */
2025 bool r600_adjust_gprs(struct r600_context *rctx)
2026 {
2027 unsigned num_ps_gprs = rctx->ps_shader->current->shader.bc.ngpr;
2028 unsigned num_vs_gprs, num_es_gprs, num_gs_gprs;
2029 unsigned new_num_ps_gprs = num_ps_gprs;
2030 unsigned new_num_vs_gprs, new_num_es_gprs, new_num_gs_gprs;
2031 unsigned cur_num_ps_gprs = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2032 unsigned cur_num_vs_gprs = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2033 unsigned cur_num_gs_gprs = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2034 unsigned cur_num_es_gprs = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2035 unsigned def_num_ps_gprs = rctx->default_ps_gprs;
2036 unsigned def_num_vs_gprs = rctx->default_vs_gprs;
2037 unsigned def_num_gs_gprs = 0;
2038 unsigned def_num_es_gprs = 0;
2039 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
2040 /* hardware will reserve twice num_clause_temp_gprs */
2041 unsigned max_gprs = def_num_gs_gprs + def_num_es_gprs + def_num_ps_gprs + def_num_vs_gprs + def_num_clause_temp_gprs * 2;
2042 unsigned tmp, tmp2;
2043
2044 if (rctx->gs_shader) {
2045 num_es_gprs = rctx->vs_shader->current->shader.bc.ngpr;
2046 num_gs_gprs = rctx->gs_shader->current->shader.bc.ngpr;
2047 num_vs_gprs = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
2048 } else {
2049 num_es_gprs = 0;
2050 num_gs_gprs = 0;
2051 num_vs_gprs = rctx->vs_shader->current->shader.bc.ngpr;
2052 }
2053 new_num_vs_gprs = num_vs_gprs;
2054 new_num_es_gprs = num_es_gprs;
2055 new_num_gs_gprs = num_gs_gprs;
2056
2057 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2058 if (new_num_ps_gprs > cur_num_ps_gprs || new_num_vs_gprs > cur_num_vs_gprs ||
2059 new_num_es_gprs > cur_num_es_gprs || new_num_gs_gprs > cur_num_gs_gprs) {
2060 /* try to use switch back to default */
2061 if (new_num_ps_gprs > def_num_ps_gprs || new_num_vs_gprs > def_num_vs_gprs ||
2062 new_num_gs_gprs > def_num_gs_gprs || new_num_es_gprs > def_num_es_gprs) {
2063 /* always privilege vs stage so that at worst we have the
2064 * pixel stage producing wrong output (not the vertex
2065 * stage) */
2066 new_num_ps_gprs = max_gprs - ((new_num_vs_gprs + new_num_es_gprs + new_num_gs_gprs) + def_num_clause_temp_gprs * 2);
2067 new_num_vs_gprs = num_vs_gprs;
2068 new_num_gs_gprs = num_gs_gprs;
2069 new_num_es_gprs = num_es_gprs;
2070 } else {
2071 new_num_ps_gprs = def_num_ps_gprs;
2072 new_num_vs_gprs = def_num_vs_gprs;
2073 new_num_es_gprs = def_num_es_gprs;
2074 new_num_gs_gprs = def_num_gs_gprs;
2075 }
2076 } else {
2077 return true;
2078 }
2079
2080 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2081 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2082 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2083 * it will lockup. So in this case just discard the draw command
2084 * and don't change the current gprs repartitions.
2085 */
2086 if (num_ps_gprs > new_num_ps_gprs || num_vs_gprs > new_num_vs_gprs ||
2087 num_gs_gprs > new_num_gs_gprs || num_es_gprs > new_num_es_gprs) {
2088 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2089 "for a combined maximum of %d\n",
2090 num_ps_gprs, num_vs_gprs, num_es_gprs, num_gs_gprs, max_gprs);
2091 return false;
2092 }
2093
2094 /* in some case we endup recomputing the current value */
2095 tmp = S_008C04_NUM_PS_GPRS(new_num_ps_gprs) |
2096 S_008C04_NUM_VS_GPRS(new_num_vs_gprs) |
2097 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2098
2099 tmp2 = S_008C08_NUM_ES_GPRS(new_num_es_gprs) |
2100 S_008C08_NUM_GS_GPRS(new_num_gs_gprs);
2101 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2102 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2103 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2;
2104 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
2105 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2106 }
2107 return true;
2108 }
2109
2110 void r600_init_atom_start_cs(struct r600_context *rctx)
2111 {
2112 int ps_prio;
2113 int vs_prio;
2114 int gs_prio;
2115 int es_prio;
2116 int num_ps_gprs;
2117 int num_vs_gprs;
2118 int num_gs_gprs;
2119 int num_es_gprs;
2120 int num_temp_gprs;
2121 int num_ps_threads;
2122 int num_vs_threads;
2123 int num_gs_threads;
2124 int num_es_threads;
2125 int num_ps_stack_entries;
2126 int num_vs_stack_entries;
2127 int num_gs_stack_entries;
2128 int num_es_stack_entries;
2129 enum radeon_family family;
2130 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2131 uint32_t tmp, i;
2132
2133 r600_init_command_buffer(cb, 256);
2134
2135 /* R6xx requires this packet at the start of each command buffer */
2136 if (rctx->b.chip_class == R600) {
2137 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2138 r600_store_value(cb, 0);
2139 }
2140 /* All asics require this one */
2141 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2142 r600_store_value(cb, 0x80000000);
2143 r600_store_value(cb, 0x80000000);
2144
2145 /* We're setting config registers here. */
2146 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2147 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2148
2149 family = rctx->b.family;
2150 ps_prio = 0;
2151 vs_prio = 1;
2152 gs_prio = 2;
2153 es_prio = 3;
2154 switch (family) {
2155 case CHIP_R600:
2156 num_ps_gprs = 192;
2157 num_vs_gprs = 56;
2158 num_temp_gprs = 4;
2159 num_gs_gprs = 0;
2160 num_es_gprs = 0;
2161 num_ps_threads = 136;
2162 num_vs_threads = 48;
2163 num_gs_threads = 4;
2164 num_es_threads = 4;
2165 num_ps_stack_entries = 128;
2166 num_vs_stack_entries = 128;
2167 num_gs_stack_entries = 0;
2168 num_es_stack_entries = 0;
2169 break;
2170 case CHIP_RV630:
2171 case CHIP_RV635:
2172 num_ps_gprs = 84;
2173 num_vs_gprs = 36;
2174 num_temp_gprs = 4;
2175 num_gs_gprs = 0;
2176 num_es_gprs = 0;
2177 num_ps_threads = 144;
2178 num_vs_threads = 40;
2179 num_gs_threads = 4;
2180 num_es_threads = 4;
2181 num_ps_stack_entries = 40;
2182 num_vs_stack_entries = 40;
2183 num_gs_stack_entries = 32;
2184 num_es_stack_entries = 16;
2185 break;
2186 case CHIP_RV610:
2187 case CHIP_RV620:
2188 case CHIP_RS780:
2189 case CHIP_RS880:
2190 default:
2191 num_ps_gprs = 84;
2192 num_vs_gprs = 36;
2193 num_temp_gprs = 4;
2194 num_gs_gprs = 0;
2195 num_es_gprs = 0;
2196 num_ps_threads = 136;
2197 num_vs_threads = 48;
2198 num_gs_threads = 4;
2199 num_es_threads = 4;
2200 num_ps_stack_entries = 40;
2201 num_vs_stack_entries = 40;
2202 num_gs_stack_entries = 32;
2203 num_es_stack_entries = 16;
2204 break;
2205 case CHIP_RV670:
2206 num_ps_gprs = 144;
2207 num_vs_gprs = 40;
2208 num_temp_gprs = 4;
2209 num_gs_gprs = 0;
2210 num_es_gprs = 0;
2211 num_ps_threads = 136;
2212 num_vs_threads = 48;
2213 num_gs_threads = 4;
2214 num_es_threads = 4;
2215 num_ps_stack_entries = 40;
2216 num_vs_stack_entries = 40;
2217 num_gs_stack_entries = 32;
2218 num_es_stack_entries = 16;
2219 break;
2220 case CHIP_RV770:
2221 num_ps_gprs = 130;
2222 num_vs_gprs = 56;
2223 num_temp_gprs = 4;
2224 num_gs_gprs = 31;
2225 num_es_gprs = 31;
2226 num_ps_threads = 180;
2227 num_vs_threads = 60;
2228 num_gs_threads = 4;
2229 num_es_threads = 4;
2230 num_ps_stack_entries = 128;
2231 num_vs_stack_entries = 128;
2232 num_gs_stack_entries = 128;
2233 num_es_stack_entries = 128;
2234 break;
2235 case CHIP_RV730:
2236 case CHIP_RV740:
2237 num_ps_gprs = 84;
2238 num_vs_gprs = 36;
2239 num_temp_gprs = 4;
2240 num_gs_gprs = 0;
2241 num_es_gprs = 0;
2242 num_ps_threads = 180;
2243 num_vs_threads = 60;
2244 num_gs_threads = 4;
2245 num_es_threads = 4;
2246 num_ps_stack_entries = 128;
2247 num_vs_stack_entries = 128;
2248 num_gs_stack_entries = 0;
2249 num_es_stack_entries = 0;
2250 break;
2251 case CHIP_RV710:
2252 num_ps_gprs = 192;
2253 num_vs_gprs = 56;
2254 num_temp_gprs = 4;
2255 num_gs_gprs = 0;
2256 num_es_gprs = 0;
2257 num_ps_threads = 136;
2258 num_vs_threads = 48;
2259 num_gs_threads = 4;
2260 num_es_threads = 4;
2261 num_ps_stack_entries = 128;
2262 num_vs_stack_entries = 128;
2263 num_gs_stack_entries = 0;
2264 num_es_stack_entries = 0;
2265 break;
2266 }
2267
2268 rctx->default_ps_gprs = num_ps_gprs;
2269 rctx->default_vs_gprs = num_vs_gprs;
2270 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2271
2272 /* SQ_CONFIG */
2273 tmp = 0;
2274 switch (family) {
2275 case CHIP_RV610:
2276 case CHIP_RV620:
2277 case CHIP_RS780:
2278 case CHIP_RS880:
2279 case CHIP_RV710:
2280 break;
2281 default:
2282 tmp |= S_008C00_VC_ENABLE(1);
2283 break;
2284 }
2285 tmp |= S_008C00_DX9_CONSTS(0);
2286 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2287 tmp |= S_008C00_PS_PRIO(ps_prio);
2288 tmp |= S_008C00_VS_PRIO(vs_prio);
2289 tmp |= S_008C00_GS_PRIO(gs_prio);
2290 tmp |= S_008C00_ES_PRIO(es_prio);
2291 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2292
2293 /* SQ_GPR_RESOURCE_MGMT_2 */
2294 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2295 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2296 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2297 r600_store_value(cb, tmp);
2298
2299 /* SQ_THREAD_RESOURCE_MGMT */
2300 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2301 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2302 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2303 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2304 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2305
2306 /* SQ_STACK_RESOURCE_MGMT_1 */
2307 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2308 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2309 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2310
2311 /* SQ_STACK_RESOURCE_MGMT_2 */
2312 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2313 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2314 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2315
2316 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2317
2318 if (rctx->b.chip_class >= R700) {
2319 r600_store_context_reg(cb, R_028A50_VGT_ENHANCE, 4);
2320 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2321 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2322 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2323 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2324 } else {
2325 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2326 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2327 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2328 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2329 }
2330 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2331 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2332 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2333 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2334 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2335 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2336 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2337 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2338 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2339 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2340
2341 /* to avoid GPU doing any preloading of constant from random address */
2342 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2343 for (i = 0; i < 16; i++)
2344 r600_store_value(cb, 0);
2345
2346 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2347 for (i = 0; i < 16; i++)
2348 r600_store_value(cb, 0);
2349
2350 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2351 for (i = 0; i < 16; i++)
2352 r600_store_value(cb, 0);
2353
2354 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2355 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2356 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2357 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2358 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2359 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2360 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2361 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2362 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2363 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2364 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2365 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2366 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2367 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2368
2369 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2370 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2371 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2372
2373 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2374 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2375 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2376
2377 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2378
2379 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2380
2381 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2382
2383 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2384 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2385 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2386 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2387
2388 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2389 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2390 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2391 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2392
2393 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2394 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2395
2396 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2397 r600_store_value(cb, fui(1.0)); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2398 r600_store_value(cb, fui(1.0)); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2399 r600_store_value(cb, fui(1.0)); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2400 r600_store_value(cb, fui(1.0)); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2401
2402 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2403 for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2404 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2405 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2406 }
2407
2408 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2409 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2410
2411 if (rctx->b.chip_class >= R700) {
2412 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2413 }
2414
2415 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2416 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2417 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2418 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2419 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2420
2421 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2422 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2423 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2424
2425 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2426 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2427 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2428
2429 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5);
2430 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2431 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2432 r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2433 r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2434 r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2435
2436 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2437
2438 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2439 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2440 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2441
2442 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2443
2444 if (rctx->b.chip_class == R700)
2445 r600_store_context_reg(cb, R_028350_SX_MISC, 0);
2446 if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
2447 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2448
2449 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2450 if (rctx->screen->b.has_streamout) {
2451 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2452 }
2453
2454 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2455 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2456 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF);
2457 }
2458
2459 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2460 {
2461 struct r600_context *rctx = (struct r600_context *)ctx;
2462 struct r600_command_buffer *cb = &shader->command_buffer;
2463 struct r600_shader *rshader = &shader->shader;
2464 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2465 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2466 unsigned tmp, sid, ufi = 0;
2467 int need_linear = 0;
2468 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2469 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2470
2471 if (!cb->buf) {
2472 r600_init_command_buffer(cb, 64);
2473 } else {
2474 cb->num_dw = 0;
2475 }
2476
2477 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2478 for (i = 0; i < rshader->ninput; i++) {
2479 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2480 pos_index = i;
2481 if (rshader->input[i].name == TGSI_SEMANTIC_FACE && face_index == -1)
2482 face_index = i;
2483 if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID)
2484 fixed_pt_position_index = i;
2485
2486 sid = rshader->input[i].spi_sid;
2487
2488 tmp = S_028644_SEMANTIC(sid);
2489
2490 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2491 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2492 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2493 rctx->rasterizer && rctx->rasterizer->flatshade))
2494 tmp |= S_028644_FLAT_SHADE(1);
2495
2496 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2497 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2498 tmp |= S_028644_PT_SPRITE_TEX(1);
2499 }
2500
2501 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID)
2502 tmp |= S_028644_SEL_CENTROID(1);
2503
2504 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE)
2505 tmp |= S_028644_SEL_SAMPLE(1);
2506
2507 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2508 need_linear = 1;
2509 tmp |= S_028644_SEL_LINEAR(1);
2510 }
2511
2512 r600_store_value(cb, tmp);
2513 }
2514
2515 db_shader_control = 0;
2516 for (i = 0; i < rshader->noutput; i++) {
2517 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2518 z_export = 1;
2519 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2520 stencil_export = 1;
2521 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
2522 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
2523 mask_export = 1;
2524 }
2525 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2526 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2527 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
2528 if (rshader->uses_kill)
2529 db_shader_control |= S_02880C_KILL_ENABLE(1);
2530
2531 exports_ps = 0;
2532 for (i = 0; i < rshader->noutput; i++) {
2533 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2534 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
2535 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2536 exports_ps |= 1;
2537 }
2538 }
2539 num_cout = rshader->nr_ps_color_exports;
2540 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2541 if (!exports_ps) {
2542 /* always at least export 1 component per pixel */
2543 exports_ps = 2;
2544 }
2545
2546 shader->nr_ps_color_outputs = num_cout;
2547
2548 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2549 S_0286CC_PERSP_GRADIENT_ENA(1)|
2550 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2551 spi_input_z = 0;
2552 if (pos_index != -1) {
2553 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2554 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
2555 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2556 S_0286CC_BARYC_SAMPLE_CNTL(1)) |
2557 S_0286CC_POSITION_SAMPLE(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE);
2558 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2559 }
2560
2561 spi_ps_in_control_1 = 0;
2562 if (face_index != -1) {
2563 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2564 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2565 }
2566 if (fixed_pt_position_index != -1) {
2567 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
2568 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
2569 }
2570
2571 /* HW bug in original R600 */
2572 if (rctx->b.family == CHIP_R600)
2573 ufi = 1;
2574
2575 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2576 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2577 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2578
2579 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2580
2581 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2582 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2583 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2584 S_028850_STACK_SIZE(rshader->bc.nstack) |
2585 S_028850_UNCACHED_FIRST_INST(ufi));
2586 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2587
2588 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2589 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2590
2591 /* only set some bits here, the other bits are set in the dsa state */
2592 shader->db_shader_control = db_shader_control;
2593 shader->ps_depth_export = z_export | stencil_export | mask_export;
2594
2595 shader->sprite_coord_enable = sprite_coord_enable;
2596 if (rctx->rasterizer)
2597 shader->flatshade = rctx->rasterizer->flatshade;
2598 }
2599
2600 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2601 {
2602 struct r600_command_buffer *cb = &shader->command_buffer;
2603 struct r600_shader *rshader = &shader->shader;
2604 unsigned spi_vs_out_id[10] = {};
2605 unsigned i, tmp, nparams = 0;
2606
2607 for (i = 0; i < rshader->noutput; i++) {
2608 if (rshader->output[i].spi_sid) {
2609 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2610 spi_vs_out_id[nparams / 4] |= tmp;
2611 nparams++;
2612 }
2613 }
2614
2615 r600_init_command_buffer(cb, 32);
2616
2617 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2618 for (i = 0; i < 10; i++) {
2619 r600_store_value(cb, spi_vs_out_id[i]);
2620 }
2621
2622 /* Certain attributes (position, psize, etc.) don't count as params.
2623 * VS is required to export at least one param and r600_shader_from_tgsi()
2624 * takes care of adding a dummy export.
2625 */
2626 if (nparams < 1)
2627 nparams = 1;
2628
2629 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2630 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2631 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2632 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2633 S_028868_STACK_SIZE(rshader->bc.nstack));
2634 if (rshader->vs_position_window_space) {
2635 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2636 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
2637 } else {
2638 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2639 S_028818_VTX_W0_FMT(1) |
2640 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2641 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2642 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2643
2644 }
2645 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2646 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2647
2648 shader->pa_cl_vs_out_cntl =
2649 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2650 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2651 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2652 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
2653 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
2654 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) |
2655 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport);
2656 }
2657
2658 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2659 {
2660 struct r600_context *rctx = (struct r600_context *)ctx;
2661 struct r600_command_buffer *cb = &shader->command_buffer;
2662 struct r600_shader *rshader = &shader->shader;
2663 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
2664 unsigned gsvs_itemsize =
2665 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2;
2666
2667 r600_init_command_buffer(cb, 64);
2668
2669 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2670 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
2671
2672 if (rctx->b.chip_class >= R700) {
2673 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
2674 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
2675 }
2676 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
2677 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
2678
2679 r600_store_context_reg(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE,
2680 cp_shader->ring_item_sizes[0] >> 2);
2681
2682 r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
2683 (rshader->ring_item_sizes[0]) >> 2);
2684
2685 r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE,
2686 gsvs_itemsize);
2687
2688 /* FIXME calculate these values somehow ??? */
2689 r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2);
2690 r600_store_value(cb, 0x80); /* GS_PER_ES */
2691 r600_store_value(cb, 0x100); /* ES_PER_GS */
2692 r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1);
2693 r600_store_value(cb, 0x2); /* GS_PER_VS */
2694
2695 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS,
2696 S_02887C_NUM_GPRS(rshader->bc.ngpr) |
2697 S_02887C_STACK_SIZE(rshader->bc.nstack));
2698 r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, 0);
2699 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2700 }
2701
2702 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2703 {
2704 struct r600_command_buffer *cb = &shader->command_buffer;
2705 struct r600_shader *rshader = &shader->shader;
2706
2707 r600_init_command_buffer(cb, 32);
2708
2709 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
2710 S_028890_NUM_GPRS(rshader->bc.ngpr) |
2711 S_028890_STACK_SIZE(rshader->bc.nstack));
2712 r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, 0);
2713 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2714 }
2715
2716
2717 void *r600_create_resolve_blend(struct r600_context *rctx)
2718 {
2719 struct pipe_blend_state blend;
2720 unsigned i;
2721
2722 memset(&blend, 0, sizeof(blend));
2723 blend.independent_blend_enable = true;
2724 for (i = 0; i < 2; i++) {
2725 blend.rt[i].colormask = 0xf;
2726 blend.rt[i].blend_enable = 1;
2727 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2728 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2729 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2730 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2731 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2732 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2733 }
2734 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2735 }
2736
2737 void *r700_create_resolve_blend(struct r600_context *rctx)
2738 {
2739 struct pipe_blend_state blend;
2740
2741 memset(&blend, 0, sizeof(blend));
2742 blend.independent_blend_enable = true;
2743 blend.rt[0].colormask = 0xf;
2744 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2745 }
2746
2747 void *r600_create_decompress_blend(struct r600_context *rctx)
2748 {
2749 struct pipe_blend_state blend;
2750
2751 memset(&blend, 0, sizeof(blend));
2752 blend.independent_blend_enable = true;
2753 blend.rt[0].colormask = 0xf;
2754 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2755 }
2756
2757 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2758 {
2759 struct pipe_depth_stencil_alpha_state dsa;
2760 boolean quirk = false;
2761
2762 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2763 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2764 quirk = true;
2765
2766 memset(&dsa, 0, sizeof(dsa));
2767
2768 if (quirk) {
2769 dsa.depth.enabled = 1;
2770 dsa.depth.func = PIPE_FUNC_LEQUAL;
2771 dsa.stencil[0].enabled = 1;
2772 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2773 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2774 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2775 dsa.stencil[0].writemask = 0xff;
2776 }
2777
2778 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2779 }
2780
2781 void r600_update_db_shader_control(struct r600_context * rctx)
2782 {
2783 bool dual_export;
2784 unsigned db_shader_control;
2785
2786 if (!rctx->ps_shader) {
2787 return;
2788 }
2789
2790 dual_export = rctx->framebuffer.export_16bpc &&
2791 !rctx->ps_shader->current->ps_depth_export;
2792
2793 db_shader_control = rctx->ps_shader->current->db_shader_control |
2794 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2795
2796 /* When alpha test is enabled we can't trust the hw to make the proper
2797 * decision on the order in which ztest should be run related to fragment
2798 * shader execution.
2799 *
2800 * If alpha test is enabled perform z test after fragment. RE_Z (early
2801 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2802 */
2803 if (rctx->alphatest_state.sx_alpha_test_control) {
2804 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2805 } else {
2806 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2807 }
2808
2809 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
2810 rctx->db_misc_state.db_shader_control = db_shader_control;
2811 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
2812 }
2813 }
2814
2815 static inline unsigned r600_array_mode(unsigned mode)
2816 {
2817 switch (mode) {
2818 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
2819 break;
2820 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
2821 break;
2822 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
2823 default:
2824 case RADEON_SURF_MODE_LINEAR: return V_0280A0_ARRAY_LINEAR_GENERAL;
2825 }
2826 }
2827
2828 static boolean r600_dma_copy_tile(struct r600_context *rctx,
2829 struct pipe_resource *dst,
2830 unsigned dst_level,
2831 unsigned dst_x,
2832 unsigned dst_y,
2833 unsigned dst_z,
2834 struct pipe_resource *src,
2835 unsigned src_level,
2836 unsigned src_x,
2837 unsigned src_y,
2838 unsigned src_z,
2839 unsigned copy_height,
2840 unsigned pitch,
2841 unsigned bpp)
2842 {
2843 struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs;
2844 struct r600_texture *rsrc = (struct r600_texture*)src;
2845 struct r600_texture *rdst = (struct r600_texture*)dst;
2846 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
2847 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
2848 uint64_t base, addr;
2849
2850 dst_mode = rdst->surface.level[dst_level].mode;
2851 src_mode = rsrc->surface.level[src_level].mode;
2852 /* downcast linear aligned to linear to simplify test */
2853 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
2854 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
2855 assert(dst_mode != src_mode);
2856
2857 y = 0;
2858 lbpp = util_logbase2(bpp);
2859 pitch_tile_max = ((pitch / bpp) / 8) - 1;
2860
2861 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
2862 /* T2L */
2863 array_mode = r600_array_mode(src_mode);
2864 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
2865 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2866 /* linear height must be the same as the slice tile max height, it's ok even
2867 * if the linear destination/source have smaller heigh as the size of the
2868 * dma packet will be using the copy_height which is always smaller or equal
2869 * to the linear height
2870 */
2871 height = rsrc->surface.level[src_level].npix_y;
2872 detile = 1;
2873 x = src_x;
2874 y = src_y;
2875 z = src_z;
2876 base = rsrc->surface.level[src_level].offset;
2877 addr = rdst->surface.level[dst_level].offset;
2878 addr += rdst->surface.level[dst_level].slice_size * dst_z;
2879 addr += dst_y * pitch + dst_x * bpp;
2880 } else {
2881 /* L2T */
2882 array_mode = r600_array_mode(dst_mode);
2883 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
2884 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2885 /* linear height must be the same as the slice tile max height, it's ok even
2886 * if the linear destination/source have smaller heigh as the size of the
2887 * dma packet will be using the copy_height which is always smaller or equal
2888 * to the linear height
2889 */
2890 height = rdst->surface.level[dst_level].npix_y;
2891 detile = 0;
2892 x = dst_x;
2893 y = dst_y;
2894 z = dst_z;
2895 base = rdst->surface.level[dst_level].offset;
2896 addr = rsrc->surface.level[src_level].offset;
2897 addr += rsrc->surface.level[src_level].slice_size * src_z;
2898 addr += src_y * pitch + src_x * bpp;
2899 }
2900 /* check that we are in dw/base alignment constraint */
2901 if (addr % 4 || base % 256) {
2902 return FALSE;
2903 }
2904
2905 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2906 * line in the blit. Compute max 8 line we can copy in the size limit
2907 */
2908 cheight = ((R600_DMA_COPY_MAX_SIZE_DW * 4) / pitch) & 0xfffffff8;
2909 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
2910 r600_need_dma_space(&rctx->b, ncopy * 7);
2911
2912 for (i = 0; i < ncopy; i++) {
2913 cheight = cheight > copy_height ? copy_height : cheight;
2914 size = (cheight * pitch) / 4;
2915 /* emit reloc before writing cs so that cs is always in consistent state */
2916 radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.dma, &rsrc->resource, RADEON_USAGE_READ,
2917 RADEON_PRIO_MIN);
2918 radeon_add_to_buffer_list(&rctx->b, &rctx->b.rings.dma, &rdst->resource, RADEON_USAGE_WRITE,
2919 RADEON_PRIO_MIN);
2920 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 1, 0, size);
2921 cs->buf[cs->cdw++] = base >> 8;
2922 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
2923 (lbpp << 24) | ((height - 1) << 10) |
2924 pitch_tile_max;
2925 cs->buf[cs->cdw++] = (slice_tile_max << 12) | (z << 0);
2926 cs->buf[cs->cdw++] = (x << 3) | (y << 17);
2927 cs->buf[cs->cdw++] = addr & 0xfffffffc;
2928 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
2929 copy_height -= cheight;
2930 addr += cheight * pitch;
2931 y += cheight;
2932 }
2933 return TRUE;
2934 }
2935
2936 static void r600_dma_copy(struct pipe_context *ctx,
2937 struct pipe_resource *dst,
2938 unsigned dst_level,
2939 unsigned dstx, unsigned dsty, unsigned dstz,
2940 struct pipe_resource *src,
2941 unsigned src_level,
2942 const struct pipe_box *src_box)
2943 {
2944 struct r600_context *rctx = (struct r600_context *)ctx;
2945 struct r600_texture *rsrc = (struct r600_texture*)src;
2946 struct r600_texture *rdst = (struct r600_texture*)dst;
2947 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
2948 unsigned src_w, dst_w;
2949 unsigned src_x, src_y;
2950 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
2951
2952 if (rctx->b.rings.dma.cs == NULL) {
2953 goto fallback;
2954 }
2955
2956 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
2957 if (dst_x % 4 || src_box->x % 4 || src_box->width % 4)
2958 goto fallback;
2959
2960 r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
2961 return;
2962 }
2963
2964 if (src->format != dst->format || src_box->depth > 1) {
2965 goto fallback;
2966 }
2967
2968 src_x = util_format_get_nblocksx(src->format, src_box->x);
2969 dst_x = util_format_get_nblocksx(src->format, dst_x);
2970 src_y = util_format_get_nblocksy(src->format, src_box->y);
2971 dst_y = util_format_get_nblocksy(src->format, dst_y);
2972
2973 bpp = rdst->surface.bpe;
2974 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
2975 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
2976 src_w = rsrc->surface.level[src_level].npix_x;
2977 dst_w = rdst->surface.level[dst_level].npix_x;
2978 copy_height = src_box->height / rsrc->surface.blk_h;
2979
2980 dst_mode = rdst->surface.level[dst_level].mode;
2981 src_mode = rsrc->surface.level[src_level].mode;
2982 /* downcast linear aligned to linear to simplify test */
2983 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
2984 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
2985
2986 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
2987 /* strict requirement on r6xx/r7xx */
2988 goto fallback;
2989 }
2990 /* lot of constraint on alignment this should capture them all */
2991 if (src_pitch % 8 || src_box->y % 8 || dst_y % 8) {
2992 goto fallback;
2993 }
2994
2995 if (src_mode == dst_mode) {
2996 uint64_t dst_offset, src_offset, size;
2997
2998 /* simple dma blit would do NOTE code here assume :
2999 * src_box.x/y == 0
3000 * dst_x/y == 0
3001 * dst_pitch == src_pitch
3002 */
3003 src_offset= rsrc->surface.level[src_level].offset;
3004 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3005 src_offset += src_y * src_pitch + src_x * bpp;
3006 dst_offset = rdst->surface.level[dst_level].offset;
3007 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3008 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3009 size = src_box->height * src_pitch;
3010 /* must be dw aligned */
3011 if (dst_offset % 4 || src_offset % 4 || size % 4) {
3012 goto fallback;
3013 }
3014 r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size);
3015 } else {
3016 if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3017 src, src_level, src_x, src_y, src_box->z,
3018 copy_height, dst_pitch, bpp)) {
3019 goto fallback;
3020 }
3021 }
3022 return;
3023
3024 fallback:
3025 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3026 src, src_level, src_box);
3027 }
3028
3029 void r600_init_state_functions(struct r600_context *rctx)
3030 {
3031 unsigned id = 1;
3032
3033 /* !!!
3034 * To avoid GPU lockup registers must be emited in a specific order
3035 * (no kidding ...). The order below is important and have been
3036 * partialy infered from analyzing fglrx command stream.
3037 *
3038 * Don't reorder atom without carefully checking the effect (GPU lockup
3039 * or piglit regression).
3040 * !!!
3041 */
3042
3043 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
3044
3045 /* shader const */
3046 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
3047 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
3048 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
3049
3050 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3051 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
3052 */
3053 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
3054 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
3055 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
3056 /* resource */
3057 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
3058 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
3059 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
3060 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
3061
3062 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3063
3064 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3065 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3066 rctx->sample_mask.sample_mask = ~0;
3067
3068 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3069 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3070 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3071 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3072 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3073 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3074 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3075 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3076 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3077 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
3078 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3079 r600_init_atom(rctx, &rctx->scissor.atom, id++, r600_emit_scissor_state, 0);
3080 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 0);
3081 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3082 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3083 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3084 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3085 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3086 r600_init_atom(rctx, &rctx->vertex_shader.atom, id++, r600_emit_shader, 23);
3087 r600_init_atom(rctx, &rctx->pixel_shader.atom, id++, r600_emit_shader, 0);
3088 r600_init_atom(rctx, &rctx->geometry_shader.atom, id++, r600_emit_shader, 0);
3089 r600_init_atom(rctx, &rctx->export_shader.atom, id++, r600_emit_shader, 0);
3090 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0);
3091 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0);
3092
3093 rctx->b.b.create_blend_state = r600_create_blend_state;
3094 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3095 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3096 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3097 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3098 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3099 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3100 rctx->b.b.set_min_samples = r600_set_min_samples;
3101 rctx->b.b.set_scissor_states = r600_set_scissor_states;
3102 rctx->b.b.get_sample_position = r600_get_sample_position;
3103 rctx->b.dma_copy = r600_dma_copy;
3104 }
3105 /* this function must be last */