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gallium/radeon: add an env variable to force a level of aniso filtering
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
145 {
146 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
147 }
148
149 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
150 {
151 return r600_translate_colorformat(chip, format) != ~0U &&
152 r600_translate_colorswap(format) != ~0U;
153 }
154
155 static bool r600_is_zs_format_supported(enum pipe_format format)
156 {
157 return r600_translate_dbformat(format) != ~0U;
158 }
159
160 boolean r600_is_format_supported(struct pipe_screen *screen,
161 enum pipe_format format,
162 enum pipe_texture_target target,
163 unsigned sample_count,
164 unsigned usage)
165 {
166 struct r600_screen *rscreen = (struct r600_screen*)screen;
167 unsigned retval = 0;
168
169 if (target >= PIPE_MAX_TEXTURE_TYPES) {
170 R600_ERR("r600: unsupported texture type %d\n", target);
171 return FALSE;
172 }
173
174 if (!util_format_is_supported(format, usage))
175 return FALSE;
176
177 if (sample_count > 1) {
178 if (!rscreen->has_msaa)
179 return FALSE;
180
181 /* R11G11B10 is broken on R6xx. */
182 if (rscreen->b.chip_class == R600 &&
183 format == PIPE_FORMAT_R11G11B10_FLOAT)
184 return FALSE;
185
186 /* MSAA integer colorbuffers hang. */
187 if (util_format_is_pure_integer(format) &&
188 !util_format_is_depth_or_stencil(format))
189 return FALSE;
190
191 switch (sample_count) {
192 case 2:
193 case 4:
194 case 8:
195 break;
196 default:
197 return FALSE;
198 }
199 }
200
201 if (usage & PIPE_BIND_SAMPLER_VIEW) {
202 if (target == PIPE_BUFFER) {
203 if (r600_is_vertex_format_supported(format))
204 retval |= PIPE_BIND_SAMPLER_VIEW;
205 } else {
206 if (r600_is_sampler_format_supported(screen, format))
207 retval |= PIPE_BIND_SAMPLER_VIEW;
208 }
209 }
210
211 if ((usage & (PIPE_BIND_RENDER_TARGET |
212 PIPE_BIND_DISPLAY_TARGET |
213 PIPE_BIND_SCANOUT |
214 PIPE_BIND_SHARED |
215 PIPE_BIND_BLENDABLE)) &&
216 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
217 retval |= usage &
218 (PIPE_BIND_RENDER_TARGET |
219 PIPE_BIND_DISPLAY_TARGET |
220 PIPE_BIND_SCANOUT |
221 PIPE_BIND_SHARED);
222 if (!util_format_is_pure_integer(format) &&
223 !util_format_is_depth_or_stencil(format))
224 retval |= usage & PIPE_BIND_BLENDABLE;
225 }
226
227 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
228 r600_is_zs_format_supported(format)) {
229 retval |= PIPE_BIND_DEPTH_STENCIL;
230 }
231
232 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
233 r600_is_vertex_format_supported(format)) {
234 retval |= PIPE_BIND_VERTEX_BUFFER;
235 }
236
237 if (usage & PIPE_BIND_TRANSFER_READ)
238 retval |= PIPE_BIND_TRANSFER_READ;
239 if (usage & PIPE_BIND_TRANSFER_WRITE)
240 retval |= PIPE_BIND_TRANSFER_WRITE;
241
242 if ((usage & PIPE_BIND_LINEAR) &&
243 !util_format_is_compressed(format) &&
244 !(usage & PIPE_BIND_DEPTH_STENCIL))
245 retval |= PIPE_BIND_LINEAR;
246
247 return retval == usage;
248 }
249
250 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
251 {
252 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
253 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
254 float offset_units = state->offset_units;
255 float offset_scale = state->offset_scale;
256
257 switch (state->zs_format) {
258 case PIPE_FORMAT_Z24X8_UNORM:
259 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
260 offset_units *= 2.0f;
261 break;
262 case PIPE_FORMAT_Z16_UNORM:
263 offset_units *= 4.0f;
264 break;
265 default:;
266 }
267
268 radeon_set_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
269 radeon_emit(cs, fui(offset_scale));
270 radeon_emit(cs, fui(offset_units));
271 radeon_emit(cs, fui(offset_scale));
272 radeon_emit(cs, fui(offset_units));
273 }
274
275 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
276 {
277 int j = state->independent_blend_enable ? i : 0;
278
279 unsigned eqRGB = state->rt[j].rgb_func;
280 unsigned srcRGB = state->rt[j].rgb_src_factor;
281 unsigned dstRGB = state->rt[j].rgb_dst_factor;
282
283 unsigned eqA = state->rt[j].alpha_func;
284 unsigned srcA = state->rt[j].alpha_src_factor;
285 unsigned dstA = state->rt[j].alpha_dst_factor;
286 uint32_t bc = 0;
287
288 if (!state->rt[j].blend_enable)
289 return 0;
290
291 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
292 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
293 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
294
295 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
296 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
297 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
298 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
299 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
300 }
301 return bc;
302 }
303
304 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
305 const struct pipe_blend_state *state,
306 int mode)
307 {
308 struct r600_context *rctx = (struct r600_context *)ctx;
309 uint32_t color_control = 0, target_mask = 0;
310 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
311
312 if (!blend) {
313 return NULL;
314 }
315
316 r600_init_command_buffer(&blend->buffer, 20);
317 r600_init_command_buffer(&blend->buffer_no_blend, 20);
318
319 /* R600 does not support per-MRT blends */
320 if (rctx->b.family > CHIP_R600)
321 color_control |= S_028808_PER_MRT_BLEND(1);
322
323 if (state->logicop_enable) {
324 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
325 } else {
326 color_control |= (0xcc << 16);
327 }
328 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
329 if (state->independent_blend_enable) {
330 for (int i = 0; i < 8; i++) {
331 if (state->rt[i].blend_enable) {
332 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
333 }
334 target_mask |= (state->rt[i].colormask << (4 * i));
335 }
336 } else {
337 for (int i = 0; i < 8; i++) {
338 if (state->rt[0].blend_enable) {
339 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
340 }
341 target_mask |= (state->rt[0].colormask << (4 * i));
342 }
343 }
344
345 if (target_mask)
346 color_control |= S_028808_SPECIAL_OP(mode);
347 else
348 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
349
350 /* only MRT0 has dual src blend */
351 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
352 blend->cb_target_mask = target_mask;
353 blend->cb_color_control = color_control;
354 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
355 blend->alpha_to_one = state->alpha_to_one;
356
357 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
358 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
359 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
360 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
361 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
362 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
363
364 /* Copy over the registers set so far into buffer_no_blend. */
365 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
366 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
367
368 /* Only add blend registers if blending is enabled. */
369 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
370 return blend;
371 }
372
373 /* The first R600 does not support per-MRT blends */
374 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
375 r600_get_blend_control(state, 0));
376
377 if (rctx->b.family > CHIP_R600) {
378 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
379 for (int i = 0; i < 8; i++) {
380 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
381 }
382 }
383 return blend;
384 }
385
386 static void *r600_create_blend_state(struct pipe_context *ctx,
387 const struct pipe_blend_state *state)
388 {
389 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
390 }
391
392 static void *r600_create_dsa_state(struct pipe_context *ctx,
393 const struct pipe_depth_stencil_alpha_state *state)
394 {
395 unsigned db_depth_control, alpha_test_control, alpha_ref;
396 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
397
398 if (!dsa) {
399 return NULL;
400 }
401
402 r600_init_command_buffer(&dsa->buffer, 3);
403
404 dsa->valuemask[0] = state->stencil[0].valuemask;
405 dsa->valuemask[1] = state->stencil[1].valuemask;
406 dsa->writemask[0] = state->stencil[0].writemask;
407 dsa->writemask[1] = state->stencil[1].writemask;
408 dsa->zwritemask = state->depth.writemask;
409
410 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
411 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
412 S_028800_ZFUNC(state->depth.func);
413
414 /* stencil */
415 if (state->stencil[0].enabled) {
416 db_depth_control |= S_028800_STENCIL_ENABLE(1);
417 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
418 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
419 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
420 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
421
422 if (state->stencil[1].enabled) {
423 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
424 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
425 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
426 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
427 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
428 }
429 }
430
431 /* alpha */
432 alpha_test_control = 0;
433 alpha_ref = 0;
434 if (state->alpha.enabled) {
435 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
436 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
437 alpha_ref = fui(state->alpha.ref_value);
438 }
439 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
440 dsa->alpha_ref = alpha_ref;
441
442 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
443 return dsa;
444 }
445
446 static void *r600_create_rs_state(struct pipe_context *ctx,
447 const struct pipe_rasterizer_state *state)
448 {
449 struct r600_context *rctx = (struct r600_context *)ctx;
450 unsigned tmp, sc_mode_cntl, spi_interp;
451 float psize_min, psize_max;
452 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
453
454 if (!rs) {
455 return NULL;
456 }
457
458 r600_init_command_buffer(&rs->buffer, 30);
459
460 rs->scissor_enable = state->scissor;
461 rs->flatshade = state->flatshade;
462 rs->sprite_coord_enable = state->sprite_coord_enable;
463 rs->two_side = state->light_twoside;
464 rs->clip_plane_enable = state->clip_plane_enable;
465 rs->pa_sc_line_stipple = state->line_stipple_enable ?
466 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
467 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
468 rs->pa_cl_clip_cntl =
469 S_028810_PS_UCP_MODE(3) |
470 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
471 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
472 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
473 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
474 if (rctx->b.chip_class == R700) {
475 rs->pa_cl_clip_cntl |=
476 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
477 }
478 rs->multisample_enable = state->multisample;
479
480 /* offset */
481 rs->offset_units = state->offset_units;
482 rs->offset_scale = state->offset_scale * 16.0f;
483 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
484
485 if (state->point_size_per_vertex) {
486 psize_min = util_get_min_point_size(state);
487 psize_max = 8192;
488 } else {
489 /* Force the point size to be as if the vertex output was disabled. */
490 psize_min = state->point_size;
491 psize_max = state->point_size;
492 }
493
494 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
495 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
496 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
497 S_028A4C_PS_ITER_SAMPLE(state->multisample && rctx->ps_iter_samples > 1);
498 if (rctx->b.family == CHIP_RV770) {
499 /* workaround possible rendering corruption on RV770 with hyperz together with sample shading */
500 sc_mode_cntl |= S_028A4C_TILE_COVER_DISABLE(state->multisample && rctx->ps_iter_samples > 1);
501 }
502 if (rctx->b.chip_class >= R700) {
503 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
504 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
505 S_028A4C_R700_VPORT_SCISSOR_ENABLE(1);
506 } else {
507 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
508 }
509
510 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
511 if (state->sprite_coord_enable) {
512 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
513 S_0286D4_PNT_SPRITE_OVRD_X(2) |
514 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
515 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
516 S_0286D4_PNT_SPRITE_OVRD_W(1);
517 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
518 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
519 }
520 }
521
522 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
523 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
524 tmp = r600_pack_float_12p4(state->point_size/2);
525 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
526 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
527 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
528 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
529 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
530 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
531 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
532
533 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
534 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
535 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
536 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
537 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
538 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
539
540 rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
541 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
542 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
543 S_028814_FACE(!state->front_ccw) |
544 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
545 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
546 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
547 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
548 state->fill_back != PIPE_POLYGON_MODE_FILL) |
549 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
550 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
551 if (rctx->b.chip_class == R700) {
552 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl);
553 }
554 if (rctx->b.chip_class == R600) {
555 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC,
556 S_028350_MULTIPASS(state->rasterizer_discard));
557 }
558 return rs;
559 }
560
561 static unsigned r600_tex_filter(unsigned filter, unsigned max_aniso)
562 {
563 if (filter == PIPE_TEX_FILTER_LINEAR)
564 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_BILINEAR
565 : V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
566 else
567 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_POINT
568 : V_03C000_SQ_TEX_XY_FILTER_POINT;
569 }
570
571 static void *r600_create_sampler_state(struct pipe_context *ctx,
572 const struct pipe_sampler_state *state)
573 {
574 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
575 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
576 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
577 : state->max_anisotropy;
578 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
579
580 if (!ss) {
581 return NULL;
582 }
583
584 ss->seamless_cube_map = state->seamless_cube_map;
585 ss->border_color_use = sampler_state_needs_border_color(state);
586
587 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
588 ss->tex_sampler_words[0] =
589 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
590 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
591 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
592 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter, max_aniso)) |
593 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter, max_aniso)) |
594 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
595 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
596 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
597 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
598 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
599 ss->tex_sampler_words[1] =
600 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
601 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
602 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
603 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
604 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
605
606 if (ss->border_color_use) {
607 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
608 }
609 return ss;
610 }
611
612 static struct pipe_sampler_view *
613 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
614 unsigned width0, unsigned height0)
615
616 {
617 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
618 int stride = util_format_get_blocksize(view->base.format);
619 unsigned format, num_format, format_comp, endian;
620 uint64_t offset = view->base.u.buf.first_element * stride;
621 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
622
623 r600_vertex_data_type(view->base.format,
624 &format, &num_format, &format_comp,
625 &endian);
626
627 view->tex_resource = &tmp->resource;
628 view->skip_mip_address_reloc = true;
629
630 view->tex_resource_words[0] = offset;
631 view->tex_resource_words[1] = size - 1;
632 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(offset >> 32UL) |
633 S_038008_STRIDE(stride) |
634 S_038008_DATA_FORMAT(format) |
635 S_038008_NUM_FORMAT_ALL(num_format) |
636 S_038008_FORMAT_COMP_ALL(format_comp) |
637 S_038008_ENDIAN_SWAP(endian);
638 view->tex_resource_words[3] = 0;
639 /*
640 * in theory dword 4 is for number of elements, for use with resinfo,
641 * but it seems to utterly fail to work, the amd gpu shader analyser
642 * uses a const buffer to store the element sizes for buffer txq
643 */
644 view->tex_resource_words[4] = 0;
645 view->tex_resource_words[5] = 0;
646 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
647 return &view->base;
648 }
649
650 struct pipe_sampler_view *
651 r600_create_sampler_view_custom(struct pipe_context *ctx,
652 struct pipe_resource *texture,
653 const struct pipe_sampler_view *state,
654 unsigned width_first_level, unsigned height_first_level)
655 {
656 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
657 struct r600_texture *tmp = (struct r600_texture*)texture;
658 unsigned format, endian;
659 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
660 unsigned char swizzle[4], array_mode = 0;
661 unsigned width, height, depth, offset_level, last_level;
662
663 if (!view)
664 return NULL;
665
666 /* initialize base object */
667 view->base = *state;
668 view->base.texture = NULL;
669 pipe_reference(NULL, &texture->reference);
670 view->base.texture = texture;
671 view->base.reference.count = 1;
672 view->base.context = ctx;
673
674 if (texture->target == PIPE_BUFFER)
675 return texture_buffer_sampler_view(view, texture->width0, 1);
676
677 swizzle[0] = state->swizzle_r;
678 swizzle[1] = state->swizzle_g;
679 swizzle[2] = state->swizzle_b;
680 swizzle[3] = state->swizzle_a;
681
682 format = r600_translate_texformat(ctx->screen, state->format,
683 swizzle,
684 &word4, &yuv_format);
685 assert(format != ~0);
686 if (format == ~0) {
687 FREE(view);
688 return NULL;
689 }
690
691 if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) {
692 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
693 FREE(view);
694 return NULL;
695 }
696 tmp = tmp->flushed_depth_texture;
697 }
698
699 endian = r600_colorformat_endian_swap(format);
700
701 offset_level = state->u.tex.first_level;
702 last_level = state->u.tex.last_level - offset_level;
703 width = width_first_level;
704 height = height_first_level;
705 depth = u_minify(texture->depth0, offset_level);
706 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
707
708 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
709 height = 1;
710 depth = texture->array_size;
711 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
712 depth = texture->array_size;
713 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
714 depth = texture->array_size / 6;
715 switch (tmp->surface.level[offset_level].mode) {
716 case RADEON_SURF_MODE_LINEAR_ALIGNED:
717 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
718 break;
719 case RADEON_SURF_MODE_1D:
720 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
721 break;
722 case RADEON_SURF_MODE_2D:
723 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
724 break;
725 case RADEON_SURF_MODE_LINEAR:
726 default:
727 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
728 break;
729 }
730
731 if (state->format == PIPE_FORMAT_X24S8_UINT ||
732 state->format == PIPE_FORMAT_S8X24_UINT ||
733 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
734 state->format == PIPE_FORMAT_S8_UINT)
735 view->is_stencil_sampler = true;
736
737 view->tex_resource = &tmp->resource;
738 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
739 S_038000_TILE_MODE(array_mode) |
740 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
741 S_038000_PITCH((pitch / 8) - 1) |
742 S_038000_TEX_WIDTH(width - 1));
743 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
744 S_038004_TEX_DEPTH(depth - 1) |
745 S_038004_DATA_FORMAT(format));
746 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
747 if (offset_level >= tmp->surface.last_level) {
748 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
749 } else {
750 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
751 }
752 view->tex_resource_words[4] = (word4 |
753 S_038010_REQUEST_SIZE(1) |
754 S_038010_ENDIAN_SWAP(endian) |
755 S_038010_BASE_LEVEL(0));
756 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
757 S_038014_LAST_ARRAY(state->u.tex.last_layer));
758 if (texture->nr_samples > 1) {
759 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
760 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
761 } else {
762 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
763 }
764 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
765 S_038018_MAX_ANISO(4 /* max 16 samples */));
766 return &view->base;
767 }
768
769 static struct pipe_sampler_view *
770 r600_create_sampler_view(struct pipe_context *ctx,
771 struct pipe_resource *tex,
772 const struct pipe_sampler_view *state)
773 {
774 return r600_create_sampler_view_custom(ctx, tex, state,
775 u_minify(tex->width0, state->u.tex.first_level),
776 u_minify(tex->height0, state->u.tex.first_level));
777 }
778
779 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
780 {
781 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
782 struct pipe_clip_state *state = &rctx->clip_state.state;
783
784 radeon_set_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
785 radeon_emit_array(cs, (unsigned*)state, 6*4);
786 }
787
788 static void r600_set_polygon_stipple(struct pipe_context *ctx,
789 const struct pipe_poly_stipple *state)
790 {
791 }
792
793 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
794 unsigned size, unsigned alignment)
795 {
796 struct pipe_resource buffer;
797
798 memset(&buffer, 0, sizeof buffer);
799 buffer.target = PIPE_BUFFER;
800 buffer.format = PIPE_FORMAT_R8_UNORM;
801 buffer.bind = PIPE_BIND_CUSTOM;
802 buffer.usage = PIPE_USAGE_DEFAULT;
803 buffer.flags = 0;
804 buffer.width0 = size;
805 buffer.height0 = 1;
806 buffer.depth0 = 1;
807 buffer.array_size = 1;
808
809 return (struct r600_resource*)
810 r600_buffer_create(&rscreen->b.b, &buffer, alignment);
811 }
812
813 static void r600_init_color_surface(struct r600_context *rctx,
814 struct r600_surface *surf,
815 bool force_cmask_fmask)
816 {
817 struct r600_screen *rscreen = rctx->screen;
818 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
819 unsigned level = surf->base.u.tex.level;
820 unsigned pitch, slice;
821 unsigned color_info;
822 unsigned color_view;
823 unsigned format, swap, ntype, endian;
824 unsigned offset;
825 const struct util_format_description *desc;
826 int i;
827 bool blend_bypass = 0, blend_clamp = 1;
828
829 if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
830 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
831 rtex = rtex->flushed_depth_texture;
832 assert(rtex);
833 }
834
835 offset = rtex->surface.level[level].offset;
836 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
837 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
838 offset += rtex->surface.level[level].slice_size *
839 surf->base.u.tex.first_layer;
840 color_view = 0;
841 } else
842 color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
843 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
844
845 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
846 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
847 if (slice) {
848 slice = slice - 1;
849 }
850 color_info = 0;
851 switch (rtex->surface.level[level].mode) {
852 case RADEON_SURF_MODE_LINEAR_ALIGNED:
853 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
854 break;
855 case RADEON_SURF_MODE_1D:
856 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
857 break;
858 case RADEON_SURF_MODE_2D:
859 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
860 break;
861 case RADEON_SURF_MODE_LINEAR:
862 default:
863 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
864 break;
865 }
866
867 desc = util_format_description(surf->base.format);
868
869 for (i = 0; i < 4; i++) {
870 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
871 break;
872 }
873 }
874
875 ntype = V_0280A0_NUMBER_UNORM;
876 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
877 ntype = V_0280A0_NUMBER_SRGB;
878 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
879 if (desc->channel[i].normalized)
880 ntype = V_0280A0_NUMBER_SNORM;
881 else if (desc->channel[i].pure_integer)
882 ntype = V_0280A0_NUMBER_SINT;
883 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
884 if (desc->channel[i].normalized)
885 ntype = V_0280A0_NUMBER_UNORM;
886 else if (desc->channel[i].pure_integer)
887 ntype = V_0280A0_NUMBER_UINT;
888 }
889
890 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
891 assert(format != ~0);
892
893 swap = r600_translate_colorswap(surf->base.format);
894 assert(swap != ~0);
895
896 endian = r600_colorformat_endian_swap(format);
897
898 /* set blend bypass according to docs if SINT/UINT or
899 8/24 COLOR variants */
900 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
901 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
902 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
903 blend_clamp = 0;
904 blend_bypass = 1;
905 }
906
907 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
908
909 color_info |= S_0280A0_FORMAT(format) |
910 S_0280A0_COMP_SWAP(swap) |
911 S_0280A0_BLEND_BYPASS(blend_bypass) |
912 S_0280A0_BLEND_CLAMP(blend_clamp) |
913 S_0280A0_NUMBER_TYPE(ntype) |
914 S_0280A0_ENDIAN(endian);
915
916 /* EXPORT_NORM is an optimzation that can be enabled for better
917 * performance in certain cases
918 */
919 if (rctx->b.chip_class == R600) {
920 /* EXPORT_NORM can be enabled if:
921 * - 11-bit or smaller UNORM/SNORM/SRGB
922 * - BLEND_CLAMP is enabled
923 * - BLEND_FLOAT32 is disabled
924 */
925 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
926 (desc->channel[i].size < 12 &&
927 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
928 ntype != V_0280A0_NUMBER_UINT &&
929 ntype != V_0280A0_NUMBER_SINT) &&
930 G_0280A0_BLEND_CLAMP(color_info) &&
931 !G_0280A0_BLEND_FLOAT32(color_info)) {
932 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
933 surf->export_16bpc = true;
934 }
935 } else {
936 /* EXPORT_NORM can be enabled if:
937 * - 11-bit or smaller UNORM/SNORM/SRGB
938 * - 16-bit or smaller FLOAT
939 */
940 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
941 ((desc->channel[i].size < 12 &&
942 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
943 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
944 (desc->channel[i].size < 17 &&
945 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
946 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
947 surf->export_16bpc = true;
948 }
949 }
950
951 /* These might not always be initialized to zero. */
952 surf->cb_color_base = offset >> 8;
953 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
954 S_028060_SLICE_TILE_MAX(slice);
955 surf->cb_color_fmask = surf->cb_color_base;
956 surf->cb_color_cmask = surf->cb_color_base;
957 surf->cb_color_mask = 0;
958
959 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
960 &rtex->resource.b.b);
961 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
962 &rtex->resource.b.b);
963
964 if (rtex->cmask.size) {
965 surf->cb_color_cmask = rtex->cmask.offset >> 8;
966 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
967
968 if (rtex->fmask.size) {
969 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
970 surf->cb_color_fmask = rtex->fmask.offset >> 8;
971 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
972 } else { /* cmask only */
973 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
974 }
975 } else if (force_cmask_fmask) {
976 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
977 *
978 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
979 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
980 * because it's not an MSAA buffer.
981 */
982 struct r600_cmask_info cmask;
983 struct r600_fmask_info fmask;
984
985 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
986 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
987
988 /* CMASK. */
989 if (!rctx->dummy_cmask ||
990 rctx->dummy_cmask->b.b.width0 < cmask.size ||
991 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
992 struct pipe_transfer *transfer;
993 void *ptr;
994
995 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
996 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
997
998 /* Set the contents to 0xCC. */
999 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1000 memset(ptr, 0xCC, cmask.size);
1001 pipe_buffer_unmap(&rctx->b.b, transfer);
1002 }
1003 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1004 &rctx->dummy_cmask->b.b);
1005
1006 /* FMASK. */
1007 if (!rctx->dummy_fmask ||
1008 rctx->dummy_fmask->b.b.width0 < fmask.size ||
1009 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1010 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1011 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1012
1013 }
1014 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1015 &rctx->dummy_fmask->b.b);
1016
1017 /* Init the registers. */
1018 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1019 surf->cb_color_cmask = 0;
1020 surf->cb_color_fmask = 0;
1021 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1022 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1023 }
1024
1025 surf->cb_color_info = color_info;
1026 surf->cb_color_view = color_view;
1027 surf->color_initialized = true;
1028 }
1029
1030 static void r600_init_depth_surface(struct r600_context *rctx,
1031 struct r600_surface *surf)
1032 {
1033 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1034 unsigned level, pitch, slice, format, offset, array_mode;
1035
1036 level = surf->base.u.tex.level;
1037 offset = rtex->surface.level[level].offset;
1038 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1039 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1040 if (slice) {
1041 slice = slice - 1;
1042 }
1043 switch (rtex->surface.level[level].mode) {
1044 case RADEON_SURF_MODE_2D:
1045 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1046 break;
1047 case RADEON_SURF_MODE_1D:
1048 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1049 case RADEON_SURF_MODE_LINEAR:
1050 default:
1051 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1052 break;
1053 }
1054
1055 format = r600_translate_dbformat(surf->base.format);
1056 assert(format != ~0);
1057
1058 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1059 surf->db_depth_base = offset >> 8;
1060 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1061 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1062 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1063 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1064
1065 switch (surf->base.format) {
1066 case PIPE_FORMAT_Z24X8_UNORM:
1067 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1068 surf->pa_su_poly_offset_db_fmt_cntl =
1069 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1070 break;
1071 case PIPE_FORMAT_Z32_FLOAT:
1072 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1073 surf->pa_su_poly_offset_db_fmt_cntl =
1074 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1075 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1076 break;
1077 case PIPE_FORMAT_Z16_UNORM:
1078 surf->pa_su_poly_offset_db_fmt_cntl =
1079 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1080 break;
1081 default:;
1082 }
1083
1084 /* use htile only for first level */
1085 if (rtex->htile_buffer && !level) {
1086 surf->db_htile_data_base = 0;
1087 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1088 S_028D24_HTILE_HEIGHT(1) |
1089 S_028D24_FULL_CACHE(1);
1090 /* preload is not working properly on r6xx/r7xx */
1091 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1092 }
1093
1094 surf->depth_initialized = true;
1095 }
1096
1097 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1098 const struct pipe_framebuffer_state *state)
1099 {
1100 struct r600_context *rctx = (struct r600_context *)ctx;
1101 struct r600_surface *surf;
1102 struct r600_texture *rtex;
1103 unsigned i;
1104
1105 if (rctx->framebuffer.state.nr_cbufs) {
1106 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1107 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1108 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1109 }
1110 if (rctx->framebuffer.state.zsbuf) {
1111 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1112 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1113
1114 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1115 if (rctx->b.chip_class >= R700 && rtex->htile_buffer) {
1116 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1117 }
1118 }
1119
1120 /* Set the new state. */
1121 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1122
1123 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1124 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1125 util_format_is_pure_integer(state->cbufs[0]->format);
1126 rctx->framebuffer.compressed_cb_mask = 0;
1127 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1128 state->cbufs[0] && state->cbufs[1] &&
1129 state->cbufs[0]->texture->nr_samples > 1 &&
1130 state->cbufs[1]->texture->nr_samples <= 1;
1131 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1132
1133 /* Colorbuffers. */
1134 for (i = 0; i < state->nr_cbufs; i++) {
1135 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1136 bool force_cmask_fmask = rctx->b.chip_class == R600 &&
1137 rctx->framebuffer.is_msaa_resolve &&
1138 i == 1;
1139
1140 surf = (struct r600_surface*)state->cbufs[i];
1141 if (!surf)
1142 continue;
1143
1144 rtex = (struct r600_texture*)surf->base.texture;
1145 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1146
1147 if (!surf->color_initialized || force_cmask_fmask) {
1148 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1149 if (force_cmask_fmask) {
1150 /* re-initialize later without compression */
1151 surf->color_initialized = false;
1152 }
1153 }
1154
1155 if (!surf->export_16bpc) {
1156 rctx->framebuffer.export_16bpc = false;
1157 }
1158
1159 if (rtex->fmask.size && rtex->cmask.size) {
1160 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1161 }
1162 }
1163
1164 /* Update alpha-test state dependencies.
1165 * Alpha-test is done on the first colorbuffer only. */
1166 if (state->nr_cbufs) {
1167 bool alphatest_bypass = false;
1168
1169 surf = (struct r600_surface*)state->cbufs[0];
1170 if (surf) {
1171 alphatest_bypass = surf->alphatest_bypass;
1172 }
1173
1174 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1175 rctx->alphatest_state.bypass = alphatest_bypass;
1176 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1177 }
1178 }
1179
1180 /* ZS buffer. */
1181 if (state->zsbuf) {
1182 surf = (struct r600_surface*)state->zsbuf;
1183
1184 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1185
1186 if (!surf->depth_initialized) {
1187 r600_init_depth_surface(rctx, surf);
1188 }
1189
1190 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1191 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1192 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1193 }
1194
1195 if (rctx->db_state.rsurf != surf) {
1196 rctx->db_state.rsurf = surf;
1197 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1198 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1199 }
1200 } else if (rctx->db_state.rsurf) {
1201 rctx->db_state.rsurf = NULL;
1202 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1203 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1204 }
1205
1206 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1207 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1208 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1209 }
1210
1211 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1212 rctx->alphatest_state.bypass = false;
1213 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1214 }
1215
1216 /* Calculate the CS size. */
1217 rctx->framebuffer.atom.num_dw =
1218 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1219
1220 if (rctx->framebuffer.state.nr_cbufs) {
1221 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
1222 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
1223 }
1224 if (rctx->framebuffer.state.zsbuf) {
1225 rctx->framebuffer.atom.num_dw += 16;
1226 } else if (rctx->screen->b.info.drm_minor >= 18) {
1227 rctx->framebuffer.atom.num_dw += 3;
1228 }
1229 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1230 rctx->framebuffer.atom.num_dw += 2;
1231 }
1232
1233 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1234
1235 r600_set_sample_locations_constant_buffer(rctx);
1236 }
1237
1238 static uint32_t sample_locs_2x[] = {
1239 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1240 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1241 };
1242 static unsigned max_dist_2x = 4;
1243
1244 static uint32_t sample_locs_4x[] = {
1245 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1246 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1247 };
1248 static unsigned max_dist_4x = 6;
1249 static uint32_t sample_locs_8x[] = {
1250 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1251 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1252 };
1253 static unsigned max_dist_8x = 7;
1254
1255 static void r600_get_sample_position(struct pipe_context *ctx,
1256 unsigned sample_count,
1257 unsigned sample_index,
1258 float *out_value)
1259 {
1260 int offset, index;
1261 struct {
1262 int idx:4;
1263 } val;
1264 switch (sample_count) {
1265 case 1:
1266 default:
1267 out_value[0] = out_value[1] = 0.5;
1268 break;
1269 case 2:
1270 offset = 4 * (sample_index * 2);
1271 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1272 out_value[0] = (float)(val.idx + 8) / 16.0f;
1273 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1274 out_value[1] = (float)(val.idx + 8) / 16.0f;
1275 break;
1276 case 4:
1277 offset = 4 * (sample_index * 2);
1278 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1279 out_value[0] = (float)(val.idx + 8) / 16.0f;
1280 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1281 out_value[1] = (float)(val.idx + 8) / 16.0f;
1282 break;
1283 case 8:
1284 offset = 4 * (sample_index % 4 * 2);
1285 index = (sample_index / 4);
1286 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1287 out_value[0] = (float)(val.idx + 8) / 16.0f;
1288 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1289 out_value[1] = (float)(val.idx + 8) / 16.0f;
1290 break;
1291 }
1292 }
1293
1294 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1295 {
1296 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1297 unsigned max_dist = 0;
1298
1299 if (rctx->b.family == CHIP_R600) {
1300 switch (nr_samples) {
1301 default:
1302 nr_samples = 0;
1303 break;
1304 case 2:
1305 radeon_set_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1306 max_dist = max_dist_2x;
1307 break;
1308 case 4:
1309 radeon_set_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1310 max_dist = max_dist_4x;
1311 break;
1312 case 8:
1313 radeon_set_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1314 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1315 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1316 max_dist = max_dist_8x;
1317 break;
1318 }
1319 } else {
1320 switch (nr_samples) {
1321 default:
1322 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1323 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1324 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1325 nr_samples = 0;
1326 break;
1327 case 2:
1328 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1329 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1330 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1331 max_dist = max_dist_2x;
1332 break;
1333 case 4:
1334 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1335 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1336 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1337 max_dist = max_dist_4x;
1338 break;
1339 case 8:
1340 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1341 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1342 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1343 max_dist = max_dist_8x;
1344 break;
1345 }
1346 }
1347
1348 if (nr_samples > 1) {
1349 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1350 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1351 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1352 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1353 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1354 } else {
1355 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1356 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1357 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1358 }
1359 }
1360
1361 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1362 {
1363 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1364 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1365 unsigned nr_cbufs = state->nr_cbufs;
1366 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1367 unsigned i, sbu = 0;
1368
1369 /* Colorbuffers. */
1370 radeon_set_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1371 for (i = 0; i < nr_cbufs; i++) {
1372 radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0);
1373 }
1374 /* set CB_COLOR1_INFO for possible dual-src blending */
1375 if (i == 1 && cb[0]) {
1376 radeon_emit(cs, cb[0]->cb_color_info);
1377 i++;
1378 }
1379 for (; i < 8; i++) {
1380 radeon_emit(cs, 0);
1381 }
1382
1383 if (nr_cbufs) {
1384 for (i = 0; i < nr_cbufs; i++) {
1385 unsigned reloc;
1386
1387 if (!cb[i])
1388 continue;
1389
1390 /* COLOR_BASE */
1391 radeon_set_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1392
1393 reloc = radeon_add_to_buffer_list(&rctx->b,
1394 &rctx->b.gfx,
1395 (struct r600_resource*)cb[i]->base.texture,
1396 RADEON_USAGE_READWRITE,
1397 cb[i]->base.texture->nr_samples > 1 ?
1398 RADEON_PRIO_COLOR_BUFFER_MSAA :
1399 RADEON_PRIO_COLOR_BUFFER);
1400 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1401 radeon_emit(cs, reloc);
1402
1403 /* FMASK */
1404 radeon_set_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1405
1406 reloc = radeon_add_to_buffer_list(&rctx->b,
1407 &rctx->b.gfx,
1408 cb[i]->cb_buffer_fmask,
1409 RADEON_USAGE_READWRITE,
1410 cb[i]->base.texture->nr_samples > 1 ?
1411 RADEON_PRIO_COLOR_BUFFER_MSAA :
1412 RADEON_PRIO_COLOR_BUFFER);
1413 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1414 radeon_emit(cs, reloc);
1415
1416 /* CMASK */
1417 radeon_set_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1418
1419 reloc = radeon_add_to_buffer_list(&rctx->b,
1420 &rctx->b.gfx,
1421 cb[i]->cb_buffer_cmask,
1422 RADEON_USAGE_READWRITE,
1423 cb[i]->base.texture->nr_samples > 1 ?
1424 RADEON_PRIO_COLOR_BUFFER_MSAA :
1425 RADEON_PRIO_COLOR_BUFFER);
1426 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1427 radeon_emit(cs, reloc);
1428 }
1429
1430 radeon_set_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1431 for (i = 0; i < nr_cbufs; i++) {
1432 radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0);
1433 }
1434
1435 radeon_set_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1436 for (i = 0; i < nr_cbufs; i++) {
1437 radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0);
1438 }
1439
1440 radeon_set_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1441 for (i = 0; i < nr_cbufs; i++) {
1442 radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0);
1443 }
1444
1445 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1446 }
1447
1448 /* SURFACE_BASE_UPDATE */
1449 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1450 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1451 radeon_emit(cs, sbu);
1452 sbu = 0;
1453 }
1454
1455 /* Zbuffer. */
1456 if (state->zsbuf) {
1457 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1458 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1459 &rctx->b.gfx,
1460 (struct r600_resource*)state->zsbuf->texture,
1461 RADEON_USAGE_READWRITE,
1462 surf->base.texture->nr_samples > 1 ?
1463 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1464 RADEON_PRIO_DEPTH_BUFFER);
1465
1466 radeon_set_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1467 surf->pa_su_poly_offset_db_fmt_cntl);
1468
1469 radeon_set_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1470 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1471 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1472 radeon_set_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1473 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1474 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1475
1476 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1477 radeon_emit(cs, reloc);
1478
1479 radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1480
1481 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1482 } else if (rctx->screen->b.info.drm_minor >= 18) {
1483 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1484 * Older kernels are out of luck. */
1485 radeon_set_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1486 }
1487
1488 /* SURFACE_BASE_UPDATE */
1489 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1490 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1491 radeon_emit(cs, sbu);
1492 sbu = 0;
1493 }
1494
1495 /* Framebuffer dimensions. */
1496 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1497 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1498 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1499 radeon_emit(cs, S_028244_BR_X(state->width) |
1500 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1501
1502 if (rctx->framebuffer.is_msaa_resolve) {
1503 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1504 } else {
1505 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1506 * will assure that the alpha-test will work even if there is
1507 * no colorbuffer bound. */
1508 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1509 (1ull << MAX2(nr_cbufs, 1)) - 1);
1510 }
1511
1512 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1513 }
1514
1515 static void r600_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1516 {
1517 struct r600_context *rctx = (struct r600_context *)ctx;
1518
1519 if (rctx->ps_iter_samples == min_samples)
1520 return;
1521
1522 rctx->ps_iter_samples = min_samples;
1523 if (rctx->framebuffer.nr_samples > 1) {
1524 r600_mark_atom_dirty(rctx, &rctx->rasterizer_state.atom);
1525 if (rctx->b.chip_class == R600)
1526 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1527 }
1528 }
1529
1530 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1531 {
1532 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1533 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1534
1535 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1536 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1537 if (rctx->b.chip_class == R600) {
1538 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1539 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1540 } else {
1541 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1542 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1543 }
1544 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1545 } else {
1546 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1547 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1548 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1549
1550 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1551 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1552 /* Always enable the first color output to make sure alpha-test works even without one. */
1553 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1554 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1555 a->cb_color_control |
1556 S_028808_MULTIWRITE_ENABLE(multiwrite));
1557 }
1558 }
1559
1560 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1561 {
1562 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1563 struct r600_db_state *a = (struct r600_db_state*)atom;
1564
1565 if (a->rsurf && a->rsurf->db_htile_surface) {
1566 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1567 unsigned reloc_idx;
1568
1569 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1570 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1571 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1572 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
1573 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1574 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1575 cs->buf[cs->cdw++] = reloc_idx;
1576 } else {
1577 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1578 }
1579 }
1580
1581 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1582 {
1583 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1584 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1585 unsigned db_render_control = 0;
1586 unsigned db_render_override =
1587 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1588 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1589
1590 if (rctx->b.chip_class >= R700) {
1591 switch (a->ps_conservative_z) {
1592 default: /* fall through */
1593 case TGSI_FS_DEPTH_LAYOUT_ANY:
1594 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_ANY_Z);
1595 break;
1596 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1597 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_GREATER_THAN_Z);
1598 break;
1599 case TGSI_FS_DEPTH_LAYOUT_LESS:
1600 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_LESS_THAN_Z);
1601 break;
1602 }
1603 }
1604
1605 if (rctx->b.num_occlusion_queries > 0 &&
1606 !a->occlusion_queries_disabled) {
1607 if (rctx->b.chip_class >= R700) {
1608 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1609 }
1610 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1611 } else {
1612 db_render_control |= S_028D0C_ZPASS_INCREMENT_DISABLE(1);
1613 }
1614
1615 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
1616 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1617 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1618 /* This is to fix a lockup when hyperz and alpha test are enabled at
1619 * the same time somehow GPU get confuse on which order to pick for
1620 * z test
1621 */
1622 if (rctx->alphatest_state.sx_alpha_test_control) {
1623 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
1624 }
1625 } else {
1626 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1627 }
1628 if (rctx->b.chip_class == R600 && rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) {
1629 /* sample shading and hyperz causes lockups on R6xx chips */
1630 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1631 }
1632 if (a->flush_depthstencil_through_cb) {
1633 assert(a->copy_depth || a->copy_stencil);
1634
1635 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1636 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1637 S_028D0C_COPY_CENTROID(1) |
1638 S_028D0C_COPY_SAMPLE(a->copy_sample);
1639
1640 if (rctx->b.chip_class == R600)
1641 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1642
1643 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
1644 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
1645 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1646 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1647 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1648 S_028D0C_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1649 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1650 }
1651 if (a->htile_clear) {
1652 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1653 }
1654
1655 /* RV770 workaround for a hang with 8x MSAA. */
1656 if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) {
1657 db_render_override |= S_028D10_MAX_TILES_IN_DTT(6);
1658 }
1659
1660 radeon_set_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1661 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1662 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1663 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1664 }
1665
1666 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1667 {
1668 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1669 struct r600_config_state *a = (struct r600_config_state*)atom;
1670
1671 radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1672 radeon_set_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
1673 }
1674
1675 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1676 {
1677 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1678 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1679
1680 while (dirty_mask) {
1681 struct pipe_vertex_buffer *vb;
1682 struct r600_resource *rbuffer;
1683 unsigned offset;
1684 unsigned buffer_index = u_bit_scan(&dirty_mask);
1685
1686 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1687 rbuffer = (struct r600_resource*)vb->buffer;
1688 assert(rbuffer);
1689
1690 offset = vb->buffer_offset;
1691
1692 /* fetch resources start at index 320 (OFFSET_FS) */
1693 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1694 radeon_emit(cs, (R600_FETCH_CONSTANTS_OFFSET_FS + buffer_index) * 7);
1695 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1696 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1697 radeon_emit(cs, /* RESOURCEi_WORD2 */
1698 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1699 S_038008_STRIDE(vb->stride));
1700 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1701 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1702 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1703 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1704
1705 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1706 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1707 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1708 }
1709 }
1710
1711 static void r600_emit_constant_buffers(struct r600_context *rctx,
1712 struct r600_constbuf_state *state,
1713 unsigned buffer_id_base,
1714 unsigned reg_alu_constbuf_size,
1715 unsigned reg_alu_const_cache)
1716 {
1717 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1718 uint32_t dirty_mask = state->dirty_mask;
1719
1720 while (dirty_mask) {
1721 struct pipe_constant_buffer *cb;
1722 struct r600_resource *rbuffer;
1723 unsigned offset;
1724 unsigned buffer_index = ffs(dirty_mask) - 1;
1725 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1726 cb = &state->cb[buffer_index];
1727 rbuffer = (struct r600_resource*)cb->buffer;
1728 assert(rbuffer);
1729
1730 offset = cb->buffer_offset;
1731
1732 if (!gs_ring_buffer) {
1733 radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1734 DIV_ROUND_UP(cb->buffer_size, 256));
1735 radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1736 }
1737
1738 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1739 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1740 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1741
1742 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1743 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
1744 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1745 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1746 radeon_emit(cs, /* RESOURCEi_WORD2 */
1747 S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1748 S_038008_STRIDE(gs_ring_buffer ? 4 : 16));
1749 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1750 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1751 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1752 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1753
1754 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1755 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1756 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1757
1758 dirty_mask &= ~(1 << buffer_index);
1759 }
1760 state->dirty_mask = 0;
1761 }
1762
1763 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1764 {
1765 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1766 R600_FETCH_CONSTANTS_OFFSET_VS,
1767 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1768 R_028980_ALU_CONST_CACHE_VS_0);
1769 }
1770
1771 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1772 {
1773 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1774 R600_FETCH_CONSTANTS_OFFSET_GS,
1775 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1776 R_0289C0_ALU_CONST_CACHE_GS_0);
1777 }
1778
1779 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1780 {
1781 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1782 R600_FETCH_CONSTANTS_OFFSET_PS,
1783 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1784 R_028940_ALU_CONST_CACHE_PS_0);
1785 }
1786
1787 static void r600_emit_sampler_views(struct r600_context *rctx,
1788 struct r600_samplerview_state *state,
1789 unsigned resource_id_base)
1790 {
1791 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1792 uint32_t dirty_mask = state->dirty_mask;
1793
1794 while (dirty_mask) {
1795 struct r600_pipe_sampler_view *rview;
1796 unsigned resource_index = u_bit_scan(&dirty_mask);
1797 unsigned reloc;
1798
1799 rview = state->views[resource_index];
1800 assert(rview);
1801
1802 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1803 radeon_emit(cs, (resource_id_base + resource_index) * 7);
1804 radeon_emit_array(cs, rview->tex_resource_words, 7);
1805
1806 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
1807 RADEON_USAGE_READ,
1808 r600_get_sampler_view_priority(rview->tex_resource));
1809 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1810 radeon_emit(cs, reloc);
1811 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1812 radeon_emit(cs, reloc);
1813 }
1814 state->dirty_mask = 0;
1815 }
1816
1817
1818 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1819 {
1820 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, R600_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS);
1821 }
1822
1823 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1824 {
1825 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, R600_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS);
1826 }
1827
1828 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1829 {
1830 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS);
1831 }
1832
1833 static void r600_emit_sampler_states(struct r600_context *rctx,
1834 struct r600_textures_info *texinfo,
1835 unsigned resource_id_base,
1836 unsigned border_color_reg)
1837 {
1838 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1839 uint32_t dirty_mask = texinfo->states.dirty_mask;
1840
1841 while (dirty_mask) {
1842 struct r600_pipe_sampler_state *rstate;
1843 struct r600_pipe_sampler_view *rview;
1844 unsigned i = u_bit_scan(&dirty_mask);
1845
1846 rstate = texinfo->states.states[i];
1847 assert(rstate);
1848 rview = texinfo->views.views[i];
1849
1850 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1851 * filtering between layers.
1852 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1853 */
1854 if (rview) {
1855 enum pipe_texture_target target = rview->base.texture->target;
1856 if (target == PIPE_TEXTURE_1D_ARRAY ||
1857 target == PIPE_TEXTURE_2D_ARRAY) {
1858 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1859 texinfo->is_array_sampler[i] = true;
1860 } else {
1861 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1862 texinfo->is_array_sampler[i] = false;
1863 }
1864 }
1865
1866 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1867 radeon_emit(cs, (resource_id_base + i) * 3);
1868 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
1869
1870 if (rstate->border_color_use) {
1871 unsigned offset;
1872
1873 offset = border_color_reg;
1874 offset += i * 16;
1875 radeon_set_config_reg_seq(cs, offset, 4);
1876 radeon_emit_array(cs, rstate->border_color.ui, 4);
1877 }
1878 }
1879 texinfo->states.dirty_mask = 0;
1880 }
1881
1882 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1883 {
1884 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1885 }
1886
1887 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1888 {
1889 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1890 }
1891
1892 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1893 {
1894 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1895 }
1896
1897 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1898 {
1899 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1900 unsigned tmp;
1901
1902 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1903 S_009508_SYNC_GRADIENT(1) |
1904 S_009508_SYNC_WALKER(1) |
1905 S_009508_SYNC_ALIGNER(1);
1906 if (!rctx->seamless_cube_map.enabled) {
1907 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1908 }
1909 radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1910 }
1911
1912 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1913 {
1914 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1915 uint8_t mask = s->sample_mask;
1916
1917 radeon_set_context_reg(rctx->b.gfx.cs, R_028C48_PA_SC_AA_MASK,
1918 mask | (mask << 8) | (mask << 16) | (mask << 24));
1919 }
1920
1921 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
1922 {
1923 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1924 struct r600_cso_state *state = (struct r600_cso_state*)a;
1925 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
1926
1927 radeon_set_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
1928 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1929 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
1930 RADEON_USAGE_READ,
1931 RADEON_PRIO_INTERNAL_SHADER));
1932 }
1933
1934 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
1935 {
1936 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1937 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
1938
1939 uint32_t v2 = 0, primid = 0;
1940
1941 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
1942 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1943 primid = 1;
1944 }
1945
1946 if (state->geom_enable) {
1947 uint32_t cut_val;
1948
1949 if (rctx->gs_shader->gs_max_out_vertices <= 128)
1950 cut_val = V_028A40_GS_CUT_128;
1951 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
1952 cut_val = V_028A40_GS_CUT_256;
1953 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
1954 cut_val = V_028A40_GS_CUT_512;
1955 else
1956 cut_val = V_028A40_GS_CUT_1024;
1957
1958 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1959 S_028A40_CUT_MODE(cut_val);
1960
1961 if (rctx->gs_shader->current->shader.gs_prim_id_input)
1962 primid = 1;
1963 }
1964
1965 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
1966 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
1967 }
1968
1969 static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
1970 {
1971 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1972 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
1973 struct r600_resource *rbuffer;
1974
1975 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1976 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1977 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1978
1979 if (state->enable) {
1980 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
1981 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
1982 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1983 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1984 RADEON_USAGE_READWRITE,
1985 RADEON_PRIO_RINGS_STREAMOUT));
1986 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
1987 state->esgs_ring.buffer_size >> 8);
1988
1989 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
1990 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
1991 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1992 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1993 RADEON_USAGE_READWRITE,
1994 RADEON_PRIO_RINGS_STREAMOUT));
1995 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
1996 state->gsvs_ring.buffer_size >> 8);
1997 } else {
1998 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
1999 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2000 }
2001
2002 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2003 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2004 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2005 }
2006
2007 /* Adjust GPR allocation on R6xx/R7xx */
2008 bool r600_adjust_gprs(struct r600_context *rctx)
2009 {
2010 unsigned num_gprs[R600_NUM_HW_STAGES];
2011 unsigned new_gprs[R600_NUM_HW_STAGES];
2012 unsigned cur_gprs[R600_NUM_HW_STAGES];
2013 unsigned def_gprs[R600_NUM_HW_STAGES];
2014 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
2015 unsigned max_gprs;
2016 unsigned tmp, tmp2;
2017 unsigned i;
2018 bool need_recalc = false, use_default = true;
2019
2020 /* hardware will reserve twice num_clause_temp_gprs */
2021 max_gprs = def_num_clause_temp_gprs * 2;
2022 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2023 def_gprs[i] = rctx->default_gprs[i];
2024 max_gprs += def_gprs[i];
2025 }
2026
2027 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2028 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2029 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2030 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2031
2032 num_gprs[R600_HW_STAGE_PS] = rctx->ps_shader->current->shader.bc.ngpr;
2033 if (rctx->gs_shader) {
2034 num_gprs[R600_HW_STAGE_ES] = rctx->vs_shader->current->shader.bc.ngpr;
2035 num_gprs[R600_HW_STAGE_GS] = rctx->gs_shader->current->shader.bc.ngpr;
2036 num_gprs[R600_HW_STAGE_VS] = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
2037 } else {
2038 num_gprs[R600_HW_STAGE_ES] = 0;
2039 num_gprs[R600_HW_STAGE_GS] = 0;
2040 num_gprs[R600_HW_STAGE_VS] = rctx->vs_shader->current->shader.bc.ngpr;
2041 }
2042
2043 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2044 new_gprs[i] = num_gprs[i];
2045 if (new_gprs[i] > cur_gprs[i])
2046 need_recalc = true;
2047 if (new_gprs[i] > def_gprs[i])
2048 use_default = false;
2049 }
2050
2051 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2052 if (!need_recalc)
2053 return true;
2054
2055 /* try to use switch back to default */
2056 if (!use_default) {
2057 /* always privilege vs stage so that at worst we have the
2058 * pixel stage producing wrong output (not the vertex
2059 * stage) */
2060 new_gprs[R600_HW_STAGE_PS] = max_gprs - def_num_clause_temp_gprs * 2;
2061 for (i = R600_HW_STAGE_VS; i < R600_NUM_HW_STAGES; i++)
2062 new_gprs[R600_HW_STAGE_PS] -= new_gprs[i];
2063 } else {
2064 for (i = 0; i < R600_NUM_HW_STAGES; i++)
2065 new_gprs[i] = def_gprs[i];
2066 }
2067
2068 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2069 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2070 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2071 * it will lockup. So in this case just discard the draw command
2072 * and don't change the current gprs repartitions.
2073 */
2074 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2075 if (num_gprs[i] > new_gprs[i]) {
2076 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2077 "for a combined maximum of %d\n",
2078 num_gprs[R600_HW_STAGE_PS], num_gprs[R600_HW_STAGE_VS], num_gprs[R600_HW_STAGE_ES], num_gprs[R600_HW_STAGE_GS], max_gprs);
2079 return false;
2080 }
2081 }
2082
2083 /* in some case we endup recomputing the current value */
2084 tmp = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
2085 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
2086 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2087
2088 tmp2 = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
2089 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
2090 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2091 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2092 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2;
2093 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
2094 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2095 }
2096 return true;
2097 }
2098
2099 void r600_init_atom_start_cs(struct r600_context *rctx)
2100 {
2101 int ps_prio;
2102 int vs_prio;
2103 int gs_prio;
2104 int es_prio;
2105 int num_ps_gprs;
2106 int num_vs_gprs;
2107 int num_gs_gprs;
2108 int num_es_gprs;
2109 int num_temp_gprs;
2110 int num_ps_threads;
2111 int num_vs_threads;
2112 int num_gs_threads;
2113 int num_es_threads;
2114 int num_ps_stack_entries;
2115 int num_vs_stack_entries;
2116 int num_gs_stack_entries;
2117 int num_es_stack_entries;
2118 enum radeon_family family;
2119 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2120 uint32_t tmp, i;
2121
2122 r600_init_command_buffer(cb, 256);
2123
2124 /* R6xx requires this packet at the start of each command buffer */
2125 if (rctx->b.chip_class == R600) {
2126 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2127 r600_store_value(cb, 0);
2128 }
2129 /* All asics require this one */
2130 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2131 r600_store_value(cb, 0x80000000);
2132 r600_store_value(cb, 0x80000000);
2133
2134 /* We're setting config registers here. */
2135 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2136 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2137
2138 /* This enables pipeline stat & streamout queries.
2139 * They are only disabled by blits.
2140 */
2141 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2142 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2143
2144 family = rctx->b.family;
2145 ps_prio = 0;
2146 vs_prio = 1;
2147 gs_prio = 2;
2148 es_prio = 3;
2149 switch (family) {
2150 case CHIP_R600:
2151 num_ps_gprs = 192;
2152 num_vs_gprs = 56;
2153 num_temp_gprs = 4;
2154 num_gs_gprs = 0;
2155 num_es_gprs = 0;
2156 num_ps_threads = 136;
2157 num_vs_threads = 48;
2158 num_gs_threads = 4;
2159 num_es_threads = 4;
2160 num_ps_stack_entries = 128;
2161 num_vs_stack_entries = 128;
2162 num_gs_stack_entries = 0;
2163 num_es_stack_entries = 0;
2164 break;
2165 case CHIP_RV630:
2166 case CHIP_RV635:
2167 num_ps_gprs = 84;
2168 num_vs_gprs = 36;
2169 num_temp_gprs = 4;
2170 num_gs_gprs = 0;
2171 num_es_gprs = 0;
2172 num_ps_threads = 144;
2173 num_vs_threads = 40;
2174 num_gs_threads = 4;
2175 num_es_threads = 4;
2176 num_ps_stack_entries = 40;
2177 num_vs_stack_entries = 40;
2178 num_gs_stack_entries = 32;
2179 num_es_stack_entries = 16;
2180 break;
2181 case CHIP_RV610:
2182 case CHIP_RV620:
2183 case CHIP_RS780:
2184 case CHIP_RS880:
2185 default:
2186 num_ps_gprs = 84;
2187 num_vs_gprs = 36;
2188 num_temp_gprs = 4;
2189 num_gs_gprs = 0;
2190 num_es_gprs = 0;
2191 /* use limits 40 VS and at least 16 ES/GS */
2192 num_ps_threads = 120;
2193 num_vs_threads = 40;
2194 num_gs_threads = 16;
2195 num_es_threads = 16;
2196 num_ps_stack_entries = 40;
2197 num_vs_stack_entries = 40;
2198 num_gs_stack_entries = 32;
2199 num_es_stack_entries = 16;
2200 break;
2201 case CHIP_RV670:
2202 num_ps_gprs = 144;
2203 num_vs_gprs = 40;
2204 num_temp_gprs = 4;
2205 num_gs_gprs = 0;
2206 num_es_gprs = 0;
2207 num_ps_threads = 136;
2208 num_vs_threads = 48;
2209 num_gs_threads = 4;
2210 num_es_threads = 4;
2211 num_ps_stack_entries = 40;
2212 num_vs_stack_entries = 40;
2213 num_gs_stack_entries = 32;
2214 num_es_stack_entries = 16;
2215 break;
2216 case CHIP_RV770:
2217 num_ps_gprs = 130;
2218 num_vs_gprs = 56;
2219 num_temp_gprs = 4;
2220 num_gs_gprs = 31;
2221 num_es_gprs = 31;
2222 num_ps_threads = 180;
2223 num_vs_threads = 60;
2224 num_gs_threads = 4;
2225 num_es_threads = 4;
2226 num_ps_stack_entries = 128;
2227 num_vs_stack_entries = 128;
2228 num_gs_stack_entries = 128;
2229 num_es_stack_entries = 128;
2230 break;
2231 case CHIP_RV730:
2232 case CHIP_RV740:
2233 num_ps_gprs = 84;
2234 num_vs_gprs = 36;
2235 num_temp_gprs = 4;
2236 num_gs_gprs = 0;
2237 num_es_gprs = 0;
2238 num_ps_threads = 180;
2239 num_vs_threads = 60;
2240 num_gs_threads = 4;
2241 num_es_threads = 4;
2242 num_ps_stack_entries = 128;
2243 num_vs_stack_entries = 128;
2244 num_gs_stack_entries = 0;
2245 num_es_stack_entries = 0;
2246 break;
2247 case CHIP_RV710:
2248 num_ps_gprs = 192;
2249 num_vs_gprs = 56;
2250 num_temp_gprs = 4;
2251 num_gs_gprs = 0;
2252 num_es_gprs = 0;
2253 num_ps_threads = 136;
2254 num_vs_threads = 48;
2255 num_gs_threads = 4;
2256 num_es_threads = 4;
2257 num_ps_stack_entries = 128;
2258 num_vs_stack_entries = 128;
2259 num_gs_stack_entries = 0;
2260 num_es_stack_entries = 0;
2261 break;
2262 }
2263
2264 rctx->default_gprs[R600_HW_STAGE_PS] = num_ps_gprs;
2265 rctx->default_gprs[R600_HW_STAGE_VS] = num_vs_gprs;
2266 rctx->default_gprs[R600_HW_STAGE_GS] = 0;
2267 rctx->default_gprs[R600_HW_STAGE_ES] = 0;
2268
2269 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2270
2271 /* SQ_CONFIG */
2272 tmp = 0;
2273 switch (family) {
2274 case CHIP_RV610:
2275 case CHIP_RV620:
2276 case CHIP_RS780:
2277 case CHIP_RS880:
2278 case CHIP_RV710:
2279 break;
2280 default:
2281 tmp |= S_008C00_VC_ENABLE(1);
2282 break;
2283 }
2284 tmp |= S_008C00_DX9_CONSTS(0);
2285 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2286 tmp |= S_008C00_PS_PRIO(ps_prio);
2287 tmp |= S_008C00_VS_PRIO(vs_prio);
2288 tmp |= S_008C00_GS_PRIO(gs_prio);
2289 tmp |= S_008C00_ES_PRIO(es_prio);
2290 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2291
2292 /* SQ_GPR_RESOURCE_MGMT_2 */
2293 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2294 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2295 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2296 r600_store_value(cb, tmp);
2297
2298 /* SQ_THREAD_RESOURCE_MGMT */
2299 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2300 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2301 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2302 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2303 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2304
2305 /* SQ_STACK_RESOURCE_MGMT_1 */
2306 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2307 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2308 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2309
2310 /* SQ_STACK_RESOURCE_MGMT_2 */
2311 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2312 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2313 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2314
2315 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2316
2317 if (rctx->b.chip_class >= R700) {
2318 r600_store_context_reg(cb, R_028A50_VGT_ENHANCE, 4);
2319 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2320 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2321 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2322 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2323 } else {
2324 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2325 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2326 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2327 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2328 }
2329 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2330 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2331 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2332 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2333 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2334 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2335 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2336 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2337 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2338 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2339
2340 /* to avoid GPU doing any preloading of constant from random address */
2341 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2342 for (i = 0; i < 16; i++)
2343 r600_store_value(cb, 0);
2344
2345 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2346 for (i = 0; i < 16; i++)
2347 r600_store_value(cb, 0);
2348
2349 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2350 for (i = 0; i < 16; i++)
2351 r600_store_value(cb, 0);
2352
2353 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2354 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2355 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2356 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2357 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2358 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2359 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2360 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2361 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2362 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2363 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2364 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2365 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2366 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2367
2368 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2369 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2370 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2371
2372 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2373 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2374 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2375
2376 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2377
2378 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2379
2380 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2381
2382 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2383 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2384 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2385 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2386
2387 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2388 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2389 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2390 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2391
2392 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2393 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2394
2395 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2396 for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2397 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2398 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2399 }
2400
2401 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2402 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2403
2404 if (rctx->b.chip_class >= R700) {
2405 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2406 }
2407
2408 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2409 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2410 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2411 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2412 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2413
2414 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2415 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2416 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2417
2418 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2419 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2420 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2421
2422 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5);
2423 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2424 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2425 r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2426 r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2427 r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2428
2429 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2430
2431 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2432 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2433 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2434
2435 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2436
2437 if (rctx->b.chip_class == R700)
2438 r600_store_context_reg(cb, R_028350_SX_MISC, 0);
2439 if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
2440 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2441
2442 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2443 if (rctx->screen->b.has_streamout) {
2444 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2445 }
2446
2447 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2448 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2449 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF);
2450 }
2451
2452 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2453 {
2454 struct r600_context *rctx = (struct r600_context *)ctx;
2455 struct r600_command_buffer *cb = &shader->command_buffer;
2456 struct r600_shader *rshader = &shader->shader;
2457 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2458 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2459 unsigned tmp, sid, ufi = 0;
2460 int need_linear = 0;
2461 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2462 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2463
2464 if (!cb->buf) {
2465 r600_init_command_buffer(cb, 64);
2466 } else {
2467 cb->num_dw = 0;
2468 }
2469
2470 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2471 for (i = 0; i < rshader->ninput; i++) {
2472 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2473 pos_index = i;
2474 if (rshader->input[i].name == TGSI_SEMANTIC_FACE && face_index == -1)
2475 face_index = i;
2476 if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID)
2477 fixed_pt_position_index = i;
2478
2479 sid = rshader->input[i].spi_sid;
2480
2481 tmp = S_028644_SEMANTIC(sid);
2482
2483 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2484 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2485 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2486 rctx->rasterizer && rctx->rasterizer->flatshade))
2487 tmp |= S_028644_FLAT_SHADE(1);
2488
2489 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2490 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2491 tmp |= S_028644_PT_SPRITE_TEX(1);
2492 }
2493
2494 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID)
2495 tmp |= S_028644_SEL_CENTROID(1);
2496
2497 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE)
2498 tmp |= S_028644_SEL_SAMPLE(1);
2499
2500 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2501 need_linear = 1;
2502 tmp |= S_028644_SEL_LINEAR(1);
2503 }
2504
2505 r600_store_value(cb, tmp);
2506 }
2507
2508 db_shader_control = 0;
2509 for (i = 0; i < rshader->noutput; i++) {
2510 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2511 z_export = 1;
2512 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2513 stencil_export = 1;
2514 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
2515 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
2516 mask_export = 1;
2517 }
2518 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2519 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2520 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
2521 if (rshader->uses_kill)
2522 db_shader_control |= S_02880C_KILL_ENABLE(1);
2523
2524 exports_ps = 0;
2525 for (i = 0; i < rshader->noutput; i++) {
2526 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2527 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
2528 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2529 exports_ps |= 1;
2530 }
2531 }
2532 num_cout = rshader->nr_ps_color_exports;
2533 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2534 if (!exports_ps) {
2535 /* always at least export 1 component per pixel */
2536 exports_ps = 2;
2537 }
2538
2539 shader->nr_ps_color_outputs = num_cout;
2540
2541 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2542 S_0286CC_PERSP_GRADIENT_ENA(1)|
2543 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2544 spi_input_z = 0;
2545 if (pos_index != -1) {
2546 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2547 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
2548 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2549 S_0286CC_BARYC_SAMPLE_CNTL(1)) |
2550 S_0286CC_POSITION_SAMPLE(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE);
2551 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2552 }
2553
2554 spi_ps_in_control_1 = 0;
2555 if (face_index != -1) {
2556 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2557 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2558 }
2559 if (fixed_pt_position_index != -1) {
2560 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
2561 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
2562 }
2563
2564 /* HW bug in original R600 */
2565 if (rctx->b.family == CHIP_R600)
2566 ufi = 1;
2567
2568 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2569 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2570 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2571
2572 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2573
2574 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2575 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2576 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2577 S_028850_STACK_SIZE(rshader->bc.nstack) |
2578 S_028850_UNCACHED_FIRST_INST(ufi));
2579 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2580
2581 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2582 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2583
2584 /* only set some bits here, the other bits are set in the dsa state */
2585 shader->db_shader_control = db_shader_control;
2586 shader->ps_depth_export = z_export | stencil_export | mask_export;
2587
2588 shader->sprite_coord_enable = sprite_coord_enable;
2589 if (rctx->rasterizer)
2590 shader->flatshade = rctx->rasterizer->flatshade;
2591 }
2592
2593 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2594 {
2595 struct r600_command_buffer *cb = &shader->command_buffer;
2596 struct r600_shader *rshader = &shader->shader;
2597 unsigned spi_vs_out_id[10] = {};
2598 unsigned i, tmp, nparams = 0;
2599
2600 for (i = 0; i < rshader->noutput; i++) {
2601 if (rshader->output[i].spi_sid) {
2602 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2603 spi_vs_out_id[nparams / 4] |= tmp;
2604 nparams++;
2605 }
2606 }
2607
2608 r600_init_command_buffer(cb, 32);
2609
2610 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2611 for (i = 0; i < 10; i++) {
2612 r600_store_value(cb, spi_vs_out_id[i]);
2613 }
2614
2615 /* Certain attributes (position, psize, etc.) don't count as params.
2616 * VS is required to export at least one param and r600_shader_from_tgsi()
2617 * takes care of adding a dummy export.
2618 */
2619 if (nparams < 1)
2620 nparams = 1;
2621
2622 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2623 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2624 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2625 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2626 S_028868_STACK_SIZE(rshader->bc.nstack));
2627 if (rshader->vs_position_window_space) {
2628 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2629 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
2630 } else {
2631 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2632 S_028818_VTX_W0_FMT(1) |
2633 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2634 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2635 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2636
2637 }
2638 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2639 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2640
2641 shader->pa_cl_vs_out_cntl =
2642 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2643 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2644 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2645 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
2646 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
2647 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) |
2648 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport);
2649 }
2650
2651 #define RV610_GSVS_ALIGN 32
2652 #define R600_GSVS_ALIGN 16
2653
2654 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2655 {
2656 struct r600_context *rctx = (struct r600_context *)ctx;
2657 struct r600_command_buffer *cb = &shader->command_buffer;
2658 struct r600_shader *rshader = &shader->shader;
2659 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
2660 unsigned gsvs_itemsize =
2661 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2;
2662
2663 /* some r600s needs gsvs itemsize aligned to cacheline size
2664 this was fixed in rs780 and above. */
2665 switch (rctx->b.family) {
2666 case CHIP_RV610:
2667 gsvs_itemsize = align(gsvs_itemsize, RV610_GSVS_ALIGN);
2668 break;
2669 case CHIP_R600:
2670 case CHIP_RV630:
2671 case CHIP_RV670:
2672 case CHIP_RV620:
2673 case CHIP_RV635:
2674 gsvs_itemsize = align(gsvs_itemsize, R600_GSVS_ALIGN);
2675 break;
2676 default:
2677 break;
2678 }
2679
2680 r600_init_command_buffer(cb, 64);
2681
2682 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2683 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
2684
2685 if (rctx->b.chip_class >= R700) {
2686 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
2687 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
2688 }
2689 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
2690 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
2691
2692 r600_store_context_reg(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE,
2693 cp_shader->ring_item_sizes[0] >> 2);
2694
2695 r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
2696 (rshader->ring_item_sizes[0]) >> 2);
2697
2698 r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE,
2699 gsvs_itemsize);
2700
2701 /* FIXME calculate these values somehow ??? */
2702 r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2);
2703 r600_store_value(cb, 0x80); /* GS_PER_ES */
2704 r600_store_value(cb, 0x100); /* ES_PER_GS */
2705 r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1);
2706 r600_store_value(cb, 0x2); /* GS_PER_VS */
2707
2708 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS,
2709 S_02887C_NUM_GPRS(rshader->bc.ngpr) |
2710 S_02887C_STACK_SIZE(rshader->bc.nstack));
2711 r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, 0);
2712 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2713 }
2714
2715 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2716 {
2717 struct r600_command_buffer *cb = &shader->command_buffer;
2718 struct r600_shader *rshader = &shader->shader;
2719
2720 r600_init_command_buffer(cb, 32);
2721
2722 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
2723 S_028890_NUM_GPRS(rshader->bc.ngpr) |
2724 S_028890_STACK_SIZE(rshader->bc.nstack));
2725 r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, 0);
2726 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2727 }
2728
2729
2730 void *r600_create_resolve_blend(struct r600_context *rctx)
2731 {
2732 struct pipe_blend_state blend;
2733 unsigned i;
2734
2735 memset(&blend, 0, sizeof(blend));
2736 blend.independent_blend_enable = true;
2737 for (i = 0; i < 2; i++) {
2738 blend.rt[i].colormask = 0xf;
2739 blend.rt[i].blend_enable = 1;
2740 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2741 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2742 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2743 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2744 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2745 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2746 }
2747 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2748 }
2749
2750 void *r700_create_resolve_blend(struct r600_context *rctx)
2751 {
2752 struct pipe_blend_state blend;
2753
2754 memset(&blend, 0, sizeof(blend));
2755 blend.independent_blend_enable = true;
2756 blend.rt[0].colormask = 0xf;
2757 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2758 }
2759
2760 void *r600_create_decompress_blend(struct r600_context *rctx)
2761 {
2762 struct pipe_blend_state blend;
2763
2764 memset(&blend, 0, sizeof(blend));
2765 blend.independent_blend_enable = true;
2766 blend.rt[0].colormask = 0xf;
2767 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2768 }
2769
2770 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2771 {
2772 struct pipe_depth_stencil_alpha_state dsa;
2773 boolean quirk = false;
2774
2775 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2776 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2777 quirk = true;
2778
2779 memset(&dsa, 0, sizeof(dsa));
2780
2781 if (quirk) {
2782 dsa.depth.enabled = 1;
2783 dsa.depth.func = PIPE_FUNC_LEQUAL;
2784 dsa.stencil[0].enabled = 1;
2785 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2786 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2787 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2788 dsa.stencil[0].writemask = 0xff;
2789 }
2790
2791 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2792 }
2793
2794 void r600_update_db_shader_control(struct r600_context * rctx)
2795 {
2796 bool dual_export;
2797 unsigned db_shader_control;
2798 uint8_t ps_conservative_z;
2799
2800 if (!rctx->ps_shader) {
2801 return;
2802 }
2803
2804 dual_export = rctx->framebuffer.export_16bpc &&
2805 !rctx->ps_shader->current->ps_depth_export;
2806
2807 db_shader_control = rctx->ps_shader->current->db_shader_control |
2808 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2809
2810 ps_conservative_z = rctx->ps_shader->current->shader.ps_conservative_z;
2811
2812 /* When alpha test is enabled we can't trust the hw to make the proper
2813 * decision on the order in which ztest should be run related to fragment
2814 * shader execution.
2815 *
2816 * If alpha test is enabled perform z test after fragment. RE_Z (early
2817 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2818 */
2819 if (rctx->alphatest_state.sx_alpha_test_control) {
2820 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2821 } else {
2822 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2823 }
2824
2825 if (db_shader_control != rctx->db_misc_state.db_shader_control ||
2826 ps_conservative_z != rctx->db_misc_state.ps_conservative_z) {
2827 rctx->db_misc_state.db_shader_control = db_shader_control;
2828 rctx->db_misc_state.ps_conservative_z = ps_conservative_z;
2829 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
2830 }
2831 }
2832
2833 static inline unsigned r600_array_mode(unsigned mode)
2834 {
2835 switch (mode) {
2836 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
2837 break;
2838 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
2839 break;
2840 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
2841 default:
2842 case RADEON_SURF_MODE_LINEAR: return V_0280A0_ARRAY_LINEAR_GENERAL;
2843 }
2844 }
2845
2846 static boolean r600_dma_copy_tile(struct r600_context *rctx,
2847 struct pipe_resource *dst,
2848 unsigned dst_level,
2849 unsigned dst_x,
2850 unsigned dst_y,
2851 unsigned dst_z,
2852 struct pipe_resource *src,
2853 unsigned src_level,
2854 unsigned src_x,
2855 unsigned src_y,
2856 unsigned src_z,
2857 unsigned copy_height,
2858 unsigned pitch,
2859 unsigned bpp)
2860 {
2861 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
2862 struct r600_texture *rsrc = (struct r600_texture*)src;
2863 struct r600_texture *rdst = (struct r600_texture*)dst;
2864 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
2865 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
2866 uint64_t base, addr;
2867
2868 dst_mode = rdst->surface.level[dst_level].mode;
2869 src_mode = rsrc->surface.level[src_level].mode;
2870 /* downcast linear aligned to linear to simplify test */
2871 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
2872 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
2873 assert(dst_mode != src_mode);
2874
2875 y = 0;
2876 lbpp = util_logbase2(bpp);
2877 pitch_tile_max = ((pitch / bpp) / 8) - 1;
2878
2879 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
2880 /* T2L */
2881 array_mode = r600_array_mode(src_mode);
2882 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
2883 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2884 /* linear height must be the same as the slice tile max height, it's ok even
2885 * if the linear destination/source have smaller heigh as the size of the
2886 * dma packet will be using the copy_height which is always smaller or equal
2887 * to the linear height
2888 */
2889 height = rsrc->surface.level[src_level].npix_y;
2890 detile = 1;
2891 x = src_x;
2892 y = src_y;
2893 z = src_z;
2894 base = rsrc->surface.level[src_level].offset;
2895 addr = rdst->surface.level[dst_level].offset;
2896 addr += rdst->surface.level[dst_level].slice_size * dst_z;
2897 addr += dst_y * pitch + dst_x * bpp;
2898 } else {
2899 /* L2T */
2900 array_mode = r600_array_mode(dst_mode);
2901 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
2902 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2903 /* linear height must be the same as the slice tile max height, it's ok even
2904 * if the linear destination/source have smaller heigh as the size of the
2905 * dma packet will be using the copy_height which is always smaller or equal
2906 * to the linear height
2907 */
2908 height = rdst->surface.level[dst_level].npix_y;
2909 detile = 0;
2910 x = dst_x;
2911 y = dst_y;
2912 z = dst_z;
2913 base = rdst->surface.level[dst_level].offset;
2914 addr = rsrc->surface.level[src_level].offset;
2915 addr += rsrc->surface.level[src_level].slice_size * src_z;
2916 addr += src_y * pitch + src_x * bpp;
2917 }
2918 /* check that we are in dw/base alignment constraint */
2919 if (addr % 4 || base % 256) {
2920 return FALSE;
2921 }
2922
2923 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2924 * line in the blit. Compute max 8 line we can copy in the size limit
2925 */
2926 cheight = ((R600_DMA_COPY_MAX_SIZE_DW * 4) / pitch) & 0xfffffff8;
2927 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
2928 r600_need_dma_space(&rctx->b, ncopy * 7);
2929
2930 for (i = 0; i < ncopy; i++) {
2931 cheight = cheight > copy_height ? copy_height : cheight;
2932 size = (cheight * pitch) / 4;
2933 /* emit reloc before writing cs so that cs is always in consistent state */
2934 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, RADEON_USAGE_READ,
2935 RADEON_PRIO_SDMA_TEXTURE);
2936 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE,
2937 RADEON_PRIO_SDMA_TEXTURE);
2938 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 1, 0, size);
2939 cs->buf[cs->cdw++] = base >> 8;
2940 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
2941 (lbpp << 24) | ((height - 1) << 10) |
2942 pitch_tile_max;
2943 cs->buf[cs->cdw++] = (slice_tile_max << 12) | (z << 0);
2944 cs->buf[cs->cdw++] = (x << 3) | (y << 17);
2945 cs->buf[cs->cdw++] = addr & 0xfffffffc;
2946 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
2947 copy_height -= cheight;
2948 addr += cheight * pitch;
2949 y += cheight;
2950 }
2951 return TRUE;
2952 }
2953
2954 static void r600_dma_copy(struct pipe_context *ctx,
2955 struct pipe_resource *dst,
2956 unsigned dst_level,
2957 unsigned dstx, unsigned dsty, unsigned dstz,
2958 struct pipe_resource *src,
2959 unsigned src_level,
2960 const struct pipe_box *src_box)
2961 {
2962 struct r600_context *rctx = (struct r600_context *)ctx;
2963 struct r600_texture *rsrc = (struct r600_texture*)src;
2964 struct r600_texture *rdst = (struct r600_texture*)dst;
2965 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
2966 unsigned src_w, dst_w;
2967 unsigned src_x, src_y;
2968 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
2969
2970 if (rctx->b.dma.cs == NULL) {
2971 goto fallback;
2972 }
2973
2974 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
2975 if (dst_x % 4 || src_box->x % 4 || src_box->width % 4)
2976 goto fallback;
2977
2978 r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
2979 return;
2980 }
2981
2982 if (src->format != dst->format || src_box->depth > 1) {
2983 goto fallback;
2984 }
2985
2986 src_x = util_format_get_nblocksx(src->format, src_box->x);
2987 dst_x = util_format_get_nblocksx(src->format, dst_x);
2988 src_y = util_format_get_nblocksy(src->format, src_box->y);
2989 dst_y = util_format_get_nblocksy(src->format, dst_y);
2990
2991 bpp = rdst->surface.bpe;
2992 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
2993 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
2994 src_w = rsrc->surface.level[src_level].npix_x;
2995 dst_w = rdst->surface.level[dst_level].npix_x;
2996 copy_height = src_box->height / rsrc->surface.blk_h;
2997
2998 dst_mode = rdst->surface.level[dst_level].mode;
2999 src_mode = rsrc->surface.level[src_level].mode;
3000 /* downcast linear aligned to linear to simplify test */
3001 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3002 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3003
3004 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3005 /* strict requirement on r6xx/r7xx */
3006 goto fallback;
3007 }
3008 /* lot of constraint on alignment this should capture them all */
3009 if (src_pitch % 8 || src_box->y % 8 || dst_y % 8) {
3010 goto fallback;
3011 }
3012
3013 if (src_mode == dst_mode) {
3014 uint64_t dst_offset, src_offset, size;
3015
3016 /* simple dma blit would do NOTE code here assume :
3017 * src_box.x/y == 0
3018 * dst_x/y == 0
3019 * dst_pitch == src_pitch
3020 */
3021 src_offset= rsrc->surface.level[src_level].offset;
3022 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3023 src_offset += src_y * src_pitch + src_x * bpp;
3024 dst_offset = rdst->surface.level[dst_level].offset;
3025 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3026 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3027 size = src_box->height * src_pitch;
3028 /* must be dw aligned */
3029 if (dst_offset % 4 || src_offset % 4 || size % 4) {
3030 goto fallback;
3031 }
3032 r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size);
3033 } else {
3034 if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3035 src, src_level, src_x, src_y, src_box->z,
3036 copy_height, dst_pitch, bpp)) {
3037 goto fallback;
3038 }
3039 }
3040 return;
3041
3042 fallback:
3043 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3044 src, src_level, src_box);
3045 }
3046
3047 void r600_init_state_functions(struct r600_context *rctx)
3048 {
3049 unsigned id = 1;
3050 unsigned i;
3051 /* !!!
3052 * To avoid GPU lockup registers must be emited in a specific order
3053 * (no kidding ...). The order below is important and have been
3054 * partialy infered from analyzing fglrx command stream.
3055 *
3056 * Don't reorder atom without carefully checking the effect (GPU lockup
3057 * or piglit regression).
3058 * !!!
3059 */
3060
3061 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
3062
3063 /* shader const */
3064 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
3065 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
3066 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
3067
3068 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3069 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
3070 */
3071 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
3072 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
3073 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
3074 /* resource */
3075 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
3076 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
3077 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
3078 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
3079
3080 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3081
3082 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3083 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3084 rctx->sample_mask.sample_mask = ~0;
3085
3086 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3087 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3088 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3089 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3090 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3091 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3092 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3093 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3094 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3095 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
3096 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3097 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
3098 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
3099 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3100 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3101 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3102 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3103 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3104 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3105 for (i = 0; i < R600_NUM_HW_STAGES; i++)
3106 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3107 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0);
3108 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0);
3109
3110 rctx->b.b.create_blend_state = r600_create_blend_state;
3111 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3112 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3113 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3114 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3115 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3116 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3117 rctx->b.b.set_min_samples = r600_set_min_samples;
3118 rctx->b.b.get_sample_position = r600_get_sample_position;
3119 rctx->b.dma_copy = r600_dma_copy;
3120 }
3121 /* this function must be last */