2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
24 #include "r600_shader.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
33 static uint32_t r600_translate_blend_function(int blend_func
)
37 return V_028804_COMB_DST_PLUS_SRC
;
38 case PIPE_BLEND_SUBTRACT
:
39 return V_028804_COMB_SRC_MINUS_DST
;
40 case PIPE_BLEND_REVERSE_SUBTRACT
:
41 return V_028804_COMB_DST_MINUS_SRC
;
43 return V_028804_COMB_MIN_DST_SRC
;
45 return V_028804_COMB_MAX_DST_SRC
;
47 R600_ERR("Unknown blend function %d\n", blend_func
);
54 static uint32_t r600_translate_blend_factor(int blend_fact
)
57 case PIPE_BLENDFACTOR_ONE
:
58 return V_028804_BLEND_ONE
;
59 case PIPE_BLENDFACTOR_SRC_COLOR
:
60 return V_028804_BLEND_SRC_COLOR
;
61 case PIPE_BLENDFACTOR_SRC_ALPHA
:
62 return V_028804_BLEND_SRC_ALPHA
;
63 case PIPE_BLENDFACTOR_DST_ALPHA
:
64 return V_028804_BLEND_DST_ALPHA
;
65 case PIPE_BLENDFACTOR_DST_COLOR
:
66 return V_028804_BLEND_DST_COLOR
;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE
;
69 case PIPE_BLENDFACTOR_CONST_COLOR
:
70 return V_028804_BLEND_CONST_COLOR
;
71 case PIPE_BLENDFACTOR_CONST_ALPHA
:
72 return V_028804_BLEND_CONST_ALPHA
;
73 case PIPE_BLENDFACTOR_ZERO
:
74 return V_028804_BLEND_ZERO
;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR
;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA
;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA
;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR
;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR
;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA
;
87 case PIPE_BLENDFACTOR_SRC1_COLOR
:
88 return V_028804_BLEND_SRC1_COLOR
;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
90 return V_028804_BLEND_SRC1_ALPHA
;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
92 return V_028804_BLEND_INV_SRC1_COLOR
;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
94 return V_028804_BLEND_INV_SRC1_ALPHA
;
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
103 static unsigned r600_tex_dim(unsigned dim
, unsigned nr_samples
)
107 case PIPE_TEXTURE_1D
:
108 return V_038000_SQ_TEX_DIM_1D
;
109 case PIPE_TEXTURE_1D_ARRAY
:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY
;
111 case PIPE_TEXTURE_2D
:
112 case PIPE_TEXTURE_RECT
:
113 return nr_samples
> 1 ? V_038000_SQ_TEX_DIM_2D_MSAA
:
114 V_038000_SQ_TEX_DIM_2D
;
115 case PIPE_TEXTURE_2D_ARRAY
:
116 return nr_samples
> 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
117 V_038000_SQ_TEX_DIM_2D_ARRAY
;
118 case PIPE_TEXTURE_3D
:
119 return V_038000_SQ_TEX_DIM_3D
;
120 case PIPE_TEXTURE_CUBE
:
121 case PIPE_TEXTURE_CUBE_ARRAY
:
122 return V_038000_SQ_TEX_DIM_CUBEMAP
;
126 static uint32_t r600_translate_dbformat(enum pipe_format format
)
129 case PIPE_FORMAT_Z16_UNORM
:
130 return V_028010_DEPTH_16
;
131 case PIPE_FORMAT_Z24X8_UNORM
:
132 return V_028010_DEPTH_X8_24
;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
134 return V_028010_DEPTH_8_24
;
135 case PIPE_FORMAT_Z32_FLOAT
:
136 return V_028010_DEPTH_32_FLOAT
;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
138 return V_028010_DEPTH_X24_8_32_FLOAT
;
144 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
146 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
,
150 static bool r600_is_colorbuffer_format_supported(enum chip_class chip
, enum pipe_format format
)
152 return r600_translate_colorformat(chip
, format
, FALSE
) != ~0U &&
153 r600_translate_colorswap(format
, FALSE
) != ~0U;
156 static bool r600_is_zs_format_supported(enum pipe_format format
)
158 return r600_translate_dbformat(format
) != ~0U;
161 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
162 enum pipe_format format
,
163 enum pipe_texture_target target
,
164 unsigned sample_count
,
167 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
170 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
171 R600_ERR("r600: unsupported texture type %d\n", target
);
175 if (!util_format_is_supported(format
, usage
))
178 if (sample_count
> 1) {
179 if (!rscreen
->has_msaa
)
182 /* R11G11B10 is broken on R6xx. */
183 if (rscreen
->b
.chip_class
== R600
&&
184 format
== PIPE_FORMAT_R11G11B10_FLOAT
)
187 /* MSAA integer colorbuffers hang. */
188 if (util_format_is_pure_integer(format
) &&
189 !util_format_is_depth_or_stencil(format
))
192 switch (sample_count
) {
202 if (usage
& PIPE_BIND_SAMPLER_VIEW
) {
203 if (target
== PIPE_BUFFER
) {
204 if (r600_is_vertex_format_supported(format
))
205 retval
|= PIPE_BIND_SAMPLER_VIEW
;
207 if (r600_is_sampler_format_supported(screen
, format
))
208 retval
|= PIPE_BIND_SAMPLER_VIEW
;
212 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
213 PIPE_BIND_DISPLAY_TARGET
|
216 PIPE_BIND_BLENDABLE
)) &&
217 r600_is_colorbuffer_format_supported(rscreen
->b
.chip_class
, format
)) {
219 (PIPE_BIND_RENDER_TARGET
|
220 PIPE_BIND_DISPLAY_TARGET
|
223 if (!util_format_is_pure_integer(format
) &&
224 !util_format_is_depth_or_stencil(format
))
225 retval
|= usage
& PIPE_BIND_BLENDABLE
;
228 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
229 r600_is_zs_format_supported(format
)) {
230 retval
|= PIPE_BIND_DEPTH_STENCIL
;
233 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
234 r600_is_vertex_format_supported(format
)) {
235 retval
|= PIPE_BIND_VERTEX_BUFFER
;
238 if (usage
& PIPE_BIND_TRANSFER_READ
)
239 retval
|= PIPE_BIND_TRANSFER_READ
;
240 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
241 retval
|= PIPE_BIND_TRANSFER_WRITE
;
243 if ((usage
& PIPE_BIND_LINEAR
) &&
244 !util_format_is_compressed(format
) &&
245 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
246 retval
|= PIPE_BIND_LINEAR
;
248 return retval
== usage
;
251 static void r600_emit_polygon_offset(struct r600_context
*rctx
, struct r600_atom
*a
)
253 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
254 struct r600_poly_offset_state
*state
= (struct r600_poly_offset_state
*)a
;
255 float offset_units
= state
->offset_units
;
256 float offset_scale
= state
->offset_scale
;
257 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
259 if (!state
->offset_units_unscaled
) {
260 switch (state
->zs_format
) {
261 case PIPE_FORMAT_Z24X8_UNORM
:
262 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
263 offset_units
*= 2.0f
;
264 pa_su_poly_offset_db_fmt_cntl
=
265 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
267 case PIPE_FORMAT_Z16_UNORM
:
268 offset_units
*= 4.0f
;
269 pa_su_poly_offset_db_fmt_cntl
=
270 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
273 pa_su_poly_offset_db_fmt_cntl
=
274 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
275 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
279 radeon_set_context_reg_seq(cs
, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE
, 4);
280 radeon_emit(cs
, fui(offset_scale
));
281 radeon_emit(cs
, fui(offset_units
));
282 radeon_emit(cs
, fui(offset_scale
));
283 radeon_emit(cs
, fui(offset_units
));
285 radeon_set_context_reg(cs
, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
286 pa_su_poly_offset_db_fmt_cntl
);
289 static uint32_t r600_get_blend_control(const struct pipe_blend_state
*state
, unsigned i
)
291 int j
= state
->independent_blend_enable
? i
: 0;
293 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
294 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
295 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
297 unsigned eqA
= state
->rt
[j
].alpha_func
;
298 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
299 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
302 if (!state
->rt
[j
].blend_enable
)
305 bc
|= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
306 bc
|= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
307 bc
|= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
309 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
310 bc
|= S_028804_SEPARATE_ALPHA_BLEND(1);
311 bc
|= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
312 bc
|= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
313 bc
|= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
318 static void *r600_create_blend_state_mode(struct pipe_context
*ctx
,
319 const struct pipe_blend_state
*state
,
322 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
323 uint32_t color_control
= 0, target_mask
= 0;
324 struct r600_blend_state
*blend
= CALLOC_STRUCT(r600_blend_state
);
330 r600_init_command_buffer(&blend
->buffer
, 20);
331 r600_init_command_buffer(&blend
->buffer_no_blend
, 20);
333 /* R600 does not support per-MRT blends */
334 if (rctx
->b
.family
> CHIP_R600
)
335 color_control
|= S_028808_PER_MRT_BLEND(1);
337 if (state
->logicop_enable
) {
338 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
340 color_control
|= (0xcc << 16);
342 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
343 if (state
->independent_blend_enable
) {
344 for (int i
= 0; i
< 8; i
++) {
345 if (state
->rt
[i
].blend_enable
) {
346 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
348 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
351 for (int i
= 0; i
< 8; i
++) {
352 if (state
->rt
[0].blend_enable
) {
353 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
355 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
360 color_control
|= S_028808_SPECIAL_OP(mode
);
362 color_control
|= S_028808_SPECIAL_OP(V_028808_DISABLE
);
364 /* only MRT0 has dual src blend */
365 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
366 blend
->cb_target_mask
= target_mask
;
367 blend
->cb_color_control
= color_control
;
368 blend
->cb_color_control_no_blend
= color_control
& C_028808_TARGET_BLEND_ENABLE
;
369 blend
->alpha_to_one
= state
->alpha_to_one
;
371 r600_store_context_reg(&blend
->buffer
, R_028D44_DB_ALPHA_TO_MASK
,
372 S_028D44_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
373 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
374 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
375 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
376 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
378 /* Copy over the registers set so far into buffer_no_blend. */
379 memcpy(blend
->buffer_no_blend
.buf
, blend
->buffer
.buf
, blend
->buffer
.num_dw
* 4);
380 blend
->buffer_no_blend
.num_dw
= blend
->buffer
.num_dw
;
382 /* Only add blend registers if blending is enabled. */
383 if (!G_028808_TARGET_BLEND_ENABLE(color_control
)) {
387 /* The first R600 does not support per-MRT blends */
388 r600_store_context_reg(&blend
->buffer
, R_028804_CB_BLEND_CONTROL
,
389 r600_get_blend_control(state
, 0));
391 if (rctx
->b
.family
> CHIP_R600
) {
392 r600_store_context_reg_seq(&blend
->buffer
, R_028780_CB_BLEND0_CONTROL
, 8);
393 for (int i
= 0; i
< 8; i
++) {
394 r600_store_value(&blend
->buffer
, r600_get_blend_control(state
, i
));
400 static void *r600_create_blend_state(struct pipe_context
*ctx
,
401 const struct pipe_blend_state
*state
)
403 return r600_create_blend_state_mode(ctx
, state
, V_028808_SPECIAL_NORMAL
);
406 static void *r600_create_dsa_state(struct pipe_context
*ctx
,
407 const struct pipe_depth_stencil_alpha_state
*state
)
409 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
410 struct r600_dsa_state
*dsa
= CALLOC_STRUCT(r600_dsa_state
);
416 r600_init_command_buffer(&dsa
->buffer
, 3);
418 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
419 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
420 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
421 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
422 dsa
->zwritemask
= state
->depth
.writemask
;
424 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
425 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
426 S_028800_ZFUNC(state
->depth
.func
);
429 if (state
->stencil
[0].enabled
) {
430 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
431 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
432 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
433 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
434 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
436 if (state
->stencil
[1].enabled
) {
437 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
438 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
439 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
440 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
441 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
446 alpha_test_control
= 0;
448 if (state
->alpha
.enabled
) {
449 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
450 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
451 alpha_ref
= fui(state
->alpha
.ref_value
);
453 dsa
->sx_alpha_test_control
= alpha_test_control
& 0xff;
454 dsa
->alpha_ref
= alpha_ref
;
456 r600_store_context_reg(&dsa
->buffer
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
460 static void *r600_create_rs_state(struct pipe_context
*ctx
,
461 const struct pipe_rasterizer_state
*state
)
463 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
464 unsigned tmp
, sc_mode_cntl
, spi_interp
;
465 float psize_min
, psize_max
;
466 struct r600_rasterizer_state
*rs
= CALLOC_STRUCT(r600_rasterizer_state
);
472 r600_init_command_buffer(&rs
->buffer
, 30);
474 rs
->scissor_enable
= state
->scissor
;
475 rs
->clip_halfz
= state
->clip_halfz
;
476 rs
->flatshade
= state
->flatshade
;
477 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
478 rs
->two_side
= state
->light_twoside
;
479 rs
->clip_plane_enable
= state
->clip_plane_enable
;
480 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
481 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
482 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
483 rs
->pa_cl_clip_cntl
=
484 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
485 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
486 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
487 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
488 if (rctx
->b
.chip_class
== R700
) {
489 rs
->pa_cl_clip_cntl
|=
490 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
);
492 rs
->multisample_enable
= state
->multisample
;
495 rs
->offset_units
= state
->offset_units
;
496 rs
->offset_scale
= state
->offset_scale
* 16.0f
;
497 rs
->offset_enable
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
498 rs
->offset_units_unscaled
= state
->offset_units_unscaled
;
500 if (state
->point_size_per_vertex
) {
501 psize_min
= util_get_min_point_size(state
);
504 /* Force the point size to be as if the vertex output was disabled. */
505 psize_min
= state
->point_size
;
506 psize_max
= state
->point_size
;
509 sc_mode_cntl
= S_028A4C_MSAA_ENABLE(state
->multisample
) |
510 S_028A4C_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
511 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
512 S_028A4C_PS_ITER_SAMPLE(state
->multisample
&& rctx
->ps_iter_samples
> 1);
513 if (rctx
->b
.family
== CHIP_RV770
) {
514 /* workaround possible rendering corruption on RV770 with hyperz together with sample shading */
515 sc_mode_cntl
|= S_028A4C_TILE_COVER_DISABLE(state
->multisample
&& rctx
->ps_iter_samples
> 1);
517 if (rctx
->b
.chip_class
>= R700
) {
518 sc_mode_cntl
|= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
519 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
520 S_028A4C_R700_VPORT_SCISSOR_ENABLE(1);
522 sc_mode_cntl
|= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
525 spi_interp
= S_0286D4_FLAT_SHADE_ENA(1);
526 if (state
->sprite_coord_enable
) {
527 spi_interp
|= S_0286D4_PNT_SPRITE_ENA(1) |
528 S_0286D4_PNT_SPRITE_OVRD_X(2) |
529 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
530 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
531 S_0286D4_PNT_SPRITE_OVRD_W(1);
532 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
533 spi_interp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
537 r600_store_context_reg_seq(&rs
->buffer
, R_028A00_PA_SU_POINT_SIZE
, 3);
538 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
539 tmp
= r600_pack_float_12p4(state
->point_size
/2);
540 r600_store_value(&rs
->buffer
, /* R_028A00_PA_SU_POINT_SIZE */
541 S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
542 r600_store_value(&rs
->buffer
, /* R_028A04_PA_SU_POINT_MINMAX */
543 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
544 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
545 r600_store_value(&rs
->buffer
, /* R_028A08_PA_SU_LINE_CNTL */
546 S_028A08_WIDTH(r600_pack_float_12p4(state
->line_width
/2)));
548 r600_store_context_reg(&rs
->buffer
, R_0286D4_SPI_INTERP_CONTROL_0
, spi_interp
);
549 r600_store_context_reg(&rs
->buffer
, R_028A4C_PA_SC_MODE_CNTL
, sc_mode_cntl
);
550 r600_store_context_reg(&rs
->buffer
, R_028C08_PA_SU_VTX_CNTL
,
551 S_028C08_PIX_CENTER_HALF(state
->half_pixel_center
) |
552 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
553 r600_store_context_reg(&rs
->buffer
, R_028DFC_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
555 rs
->pa_su_sc_mode_cntl
= S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
556 S_028814_CULL_FRONT(state
->cull_face
& PIPE_FACE_FRONT
? 1 : 0) |
557 S_028814_CULL_BACK(state
->cull_face
& PIPE_FACE_BACK
? 1 : 0) |
558 S_028814_FACE(!state
->front_ccw
) |
559 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
560 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
561 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
562 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
563 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
564 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
565 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
));
566 if (rctx
->b
.chip_class
== R700
) {
567 r600_store_context_reg(&rs
->buffer
, R_028814_PA_SU_SC_MODE_CNTL
, rs
->pa_su_sc_mode_cntl
);
569 if (rctx
->b
.chip_class
== R600
) {
570 r600_store_context_reg(&rs
->buffer
, R_028350_SX_MISC
,
571 S_028350_MULTIPASS(state
->rasterizer_discard
));
576 static unsigned r600_tex_filter(unsigned filter
, unsigned max_aniso
)
578 if (filter
== PIPE_TEX_FILTER_LINEAR
)
579 return max_aniso
> 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_BILINEAR
580 : V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
582 return max_aniso
> 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_POINT
583 : V_03C000_SQ_TEX_XY_FILTER_POINT
;
586 static void *r600_create_sampler_state(struct pipe_context
*ctx
,
587 const struct pipe_sampler_state
*state
)
589 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)ctx
->screen
;
590 struct r600_pipe_sampler_state
*ss
= CALLOC_STRUCT(r600_pipe_sampler_state
);
591 unsigned max_aniso
= rscreen
->force_aniso
>= 0 ? rscreen
->force_aniso
592 : state
->max_anisotropy
;
593 unsigned max_aniso_ratio
= r600_tex_aniso_filter(max_aniso
);
599 ss
->seamless_cube_map
= state
->seamless_cube_map
;
600 ss
->border_color_use
= sampler_state_needs_border_color(state
);
602 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
603 ss
->tex_sampler_words
[0] =
604 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
605 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
606 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
607 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
, max_aniso
)) |
608 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
, max_aniso
)) |
609 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
610 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio
) |
611 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
612 S_03C000_BORDER_COLOR_TYPE(ss
->border_color_use
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0);
613 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
614 ss
->tex_sampler_words
[1] =
615 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 6)) |
616 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 6)) |
617 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 6));
618 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
619 ss
->tex_sampler_words
[2] = S_03C008_TYPE(1);
621 if (ss
->border_color_use
) {
622 memcpy(&ss
->border_color
, &state
->border_color
, sizeof(state
->border_color
));
627 static struct pipe_sampler_view
*
628 texture_buffer_sampler_view(struct r600_pipe_sampler_view
*view
,
629 unsigned width0
, unsigned height0
)
632 struct r600_texture
*tmp
= (struct r600_texture
*)view
->base
.texture
;
633 int stride
= util_format_get_blocksize(view
->base
.format
);
634 unsigned format
, num_format
, format_comp
, endian
;
635 uint64_t offset
= view
->base
.u
.buf
.offset
;
636 unsigned size
= view
->base
.u
.buf
.size
;
638 r600_vertex_data_type(view
->base
.format
,
639 &format
, &num_format
, &format_comp
,
642 view
->tex_resource
= &tmp
->resource
;
643 view
->skip_mip_address_reloc
= true;
645 view
->tex_resource_words
[0] = offset
;
646 view
->tex_resource_words
[1] = size
- 1;
647 view
->tex_resource_words
[2] = S_038008_BASE_ADDRESS_HI(offset
>> 32UL) |
648 S_038008_STRIDE(stride
) |
649 S_038008_DATA_FORMAT(format
) |
650 S_038008_NUM_FORMAT_ALL(num_format
) |
651 S_038008_FORMAT_COMP_ALL(format_comp
) |
652 S_038008_ENDIAN_SWAP(endian
);
653 view
->tex_resource_words
[3] = 0;
655 * in theory dword 4 is for number of elements, for use with resinfo,
656 * but it seems to utterly fail to work, the amd gpu shader analyser
657 * uses a const buffer to store the element sizes for buffer txq
659 view
->tex_resource_words
[4] = 0;
660 view
->tex_resource_words
[5] = 0;
661 view
->tex_resource_words
[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER
);
665 struct pipe_sampler_view
*
666 r600_create_sampler_view_custom(struct pipe_context
*ctx
,
667 struct pipe_resource
*texture
,
668 const struct pipe_sampler_view
*state
,
669 unsigned width_first_level
, unsigned height_first_level
)
671 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
672 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
673 unsigned format
, endian
;
674 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
675 unsigned char swizzle
[4], array_mode
= 0;
676 unsigned width
, height
, depth
, offset_level
, last_level
;
677 bool do_endian_swap
= FALSE
;
682 /* initialize base object */
684 view
->base
.texture
= NULL
;
685 pipe_reference(NULL
, &texture
->reference
);
686 view
->base
.texture
= texture
;
687 view
->base
.reference
.count
= 1;
688 view
->base
.context
= ctx
;
690 if (texture
->target
== PIPE_BUFFER
)
691 return texture_buffer_sampler_view(view
, texture
->width0
, 1);
693 swizzle
[0] = state
->swizzle_r
;
694 swizzle
[1] = state
->swizzle_g
;
695 swizzle
[2] = state
->swizzle_b
;
696 swizzle
[3] = state
->swizzle_a
;
699 do_endian_swap
= !tmp
->db_compatible
;
701 format
= r600_translate_texformat(ctx
->screen
, state
->format
,
703 &word4
, &yuv_format
, do_endian_swap
);
704 assert(format
!= ~0);
710 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
711 state
->format
== PIPE_FORMAT_S8X24_UINT
||
712 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
713 state
->format
== PIPE_FORMAT_S8_UINT
)
714 view
->is_stencil_sampler
= true;
716 if (tmp
->is_depth
&& !r600_can_sample_zs(tmp
, view
->is_stencil_sampler
)) {
717 if (!r600_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
721 tmp
= tmp
->flushed_depth_texture
;
724 endian
= r600_colorformat_endian_swap(format
, do_endian_swap
);
726 offset_level
= state
->u
.tex
.first_level
;
727 last_level
= state
->u
.tex
.last_level
- offset_level
;
728 width
= width_first_level
;
729 height
= height_first_level
;
730 depth
= u_minify(texture
->depth0
, offset_level
);
731 pitch
= tmp
->surface
.level
[offset_level
].nblk_x
* util_format_get_blockwidth(state
->format
);
733 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
735 depth
= texture
->array_size
;
736 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
737 depth
= texture
->array_size
;
738 } else if (texture
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
739 depth
= texture
->array_size
/ 6;
741 switch (tmp
->surface
.level
[offset_level
].mode
) {
743 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
744 array_mode
= V_038000_ARRAY_LINEAR_ALIGNED
;
746 case RADEON_SURF_MODE_1D
:
747 array_mode
= V_038000_ARRAY_1D_TILED_THIN1
;
749 case RADEON_SURF_MODE_2D
:
750 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
754 view
->tex_resource
= &tmp
->resource
;
755 view
->tex_resource_words
[0] = (S_038000_DIM(r600_tex_dim(texture
->target
, texture
->nr_samples
)) |
756 S_038000_TILE_MODE(array_mode
) |
757 S_038000_TILE_TYPE(tmp
->non_disp_tiling
) |
758 S_038000_PITCH((pitch
/ 8) - 1) |
759 S_038000_TEX_WIDTH(width
- 1));
760 view
->tex_resource_words
[1] = (S_038004_TEX_HEIGHT(height
- 1) |
761 S_038004_TEX_DEPTH(depth
- 1) |
762 S_038004_DATA_FORMAT(format
));
763 view
->tex_resource_words
[2] = tmp
->surface
.level
[offset_level
].offset
>> 8;
764 if (offset_level
>= tmp
->surface
.last_level
) {
765 view
->tex_resource_words
[3] = tmp
->surface
.level
[offset_level
].offset
>> 8;
767 view
->tex_resource_words
[3] = tmp
->surface
.level
[offset_level
+ 1].offset
>> 8;
769 view
->tex_resource_words
[4] = (word4
|
770 S_038010_REQUEST_SIZE(1) |
771 S_038010_ENDIAN_SWAP(endian
) |
772 S_038010_BASE_LEVEL(0));
773 view
->tex_resource_words
[5] = (S_038014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
774 S_038014_LAST_ARRAY(state
->u
.tex
.last_layer
));
775 if (texture
->nr_samples
> 1) {
776 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
777 view
->tex_resource_words
[5] |= S_038014_LAST_LEVEL(util_logbase2(texture
->nr_samples
));
779 view
->tex_resource_words
[5] |= S_038014_LAST_LEVEL(last_level
);
781 view
->tex_resource_words
[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE
) |
782 S_038018_MAX_ANISO(4 /* max 16 samples */));
786 static struct pipe_sampler_view
*
787 r600_create_sampler_view(struct pipe_context
*ctx
,
788 struct pipe_resource
*tex
,
789 const struct pipe_sampler_view
*state
)
791 return r600_create_sampler_view_custom(ctx
, tex
, state
,
792 u_minify(tex
->width0
, state
->u
.tex
.first_level
),
793 u_minify(tex
->height0
, state
->u
.tex
.first_level
));
796 static void r600_emit_clip_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
798 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
799 struct pipe_clip_state
*state
= &rctx
->clip_state
.state
;
801 radeon_set_context_reg_seq(cs
, R_028E20_PA_CL_UCP0_X
, 6*4);
802 radeon_emit_array(cs
, (unsigned*)state
, 6*4);
805 static void r600_set_polygon_stipple(struct pipe_context
*ctx
,
806 const struct pipe_poly_stipple
*state
)
810 static struct r600_resource
*r600_buffer_create_helper(struct r600_screen
*rscreen
,
811 unsigned size
, unsigned alignment
)
813 struct pipe_resource buffer
;
815 memset(&buffer
, 0, sizeof buffer
);
816 buffer
.target
= PIPE_BUFFER
;
817 buffer
.format
= PIPE_FORMAT_R8_UNORM
;
818 buffer
.bind
= PIPE_BIND_CUSTOM
;
819 buffer
.usage
= PIPE_USAGE_DEFAULT
;
821 buffer
.width0
= size
;
824 buffer
.array_size
= 1;
826 return (struct r600_resource
*)
827 r600_buffer_create(&rscreen
->b
.b
, &buffer
, alignment
);
830 static void r600_init_color_surface(struct r600_context
*rctx
,
831 struct r600_surface
*surf
,
832 bool force_cmask_fmask
)
834 struct r600_screen
*rscreen
= rctx
->screen
;
835 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
836 unsigned level
= surf
->base
.u
.tex
.level
;
837 unsigned pitch
, slice
;
840 unsigned format
, swap
, ntype
, endian
;
842 const struct util_format_description
*desc
;
844 bool blend_bypass
= 0, blend_clamp
= 1, do_endian_swap
= FALSE
;
846 if (rtex
->db_compatible
&& !r600_can_sample_zs(rtex
, false)) {
847 r600_init_flushed_depth_texture(&rctx
->b
.b
, surf
->base
.texture
, NULL
);
848 rtex
= rtex
->flushed_depth_texture
;
852 offset
= rtex
->surface
.level
[level
].offset
;
853 color_view
= S_028080_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
854 S_028080_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
856 pitch
= rtex
->surface
.level
[level
].nblk_x
/ 8 - 1;
857 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
862 switch (rtex
->surface
.level
[level
].mode
) {
864 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
865 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED
);
867 case RADEON_SURF_MODE_1D
:
868 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1
);
870 case RADEON_SURF_MODE_2D
:
871 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1
);
875 desc
= util_format_description(surf
->base
.format
);
877 for (i
= 0; i
< 4; i
++) {
878 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
883 ntype
= V_0280A0_NUMBER_UNORM
;
884 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
885 ntype
= V_0280A0_NUMBER_SRGB
;
886 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
887 if (desc
->channel
[i
].normalized
)
888 ntype
= V_0280A0_NUMBER_SNORM
;
889 else if (desc
->channel
[i
].pure_integer
)
890 ntype
= V_0280A0_NUMBER_SINT
;
891 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
892 if (desc
->channel
[i
].normalized
)
893 ntype
= V_0280A0_NUMBER_UNORM
;
894 else if (desc
->channel
[i
].pure_integer
)
895 ntype
= V_0280A0_NUMBER_UINT
;
899 do_endian_swap
= !rtex
->db_compatible
;
901 format
= r600_translate_colorformat(rctx
->b
.chip_class
, surf
->base
.format
,
903 assert(format
!= ~0);
905 swap
= r600_translate_colorswap(surf
->base
.format
, do_endian_swap
);
908 endian
= r600_colorformat_endian_swap(format
, do_endian_swap
);
910 /* set blend bypass according to docs if SINT/UINT or
911 8/24 COLOR variants */
912 if (ntype
== V_0280A0_NUMBER_UINT
|| ntype
== V_0280A0_NUMBER_SINT
||
913 format
== V_0280A0_COLOR_8_24
|| format
== V_0280A0_COLOR_24_8
||
914 format
== V_0280A0_COLOR_X24_8_32_FLOAT
) {
919 surf
->alphatest_bypass
= ntype
== V_0280A0_NUMBER_UINT
|| ntype
== V_0280A0_NUMBER_SINT
;
921 color_info
|= S_0280A0_FORMAT(format
) |
922 S_0280A0_COMP_SWAP(swap
) |
923 S_0280A0_BLEND_BYPASS(blend_bypass
) |
924 S_0280A0_BLEND_CLAMP(blend_clamp
) |
925 S_0280A0_NUMBER_TYPE(ntype
) |
926 S_0280A0_ENDIAN(endian
);
928 /* EXPORT_NORM is an optimzation that can be enabled for better
929 * performance in certain cases
931 if (rctx
->b
.chip_class
== R600
) {
932 /* EXPORT_NORM can be enabled if:
933 * - 11-bit or smaller UNORM/SNORM/SRGB
934 * - BLEND_CLAMP is enabled
935 * - BLEND_FLOAT32 is disabled
937 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
938 (desc
->channel
[i
].size
< 12 &&
939 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
940 ntype
!= V_0280A0_NUMBER_UINT
&&
941 ntype
!= V_0280A0_NUMBER_SINT
) &&
942 G_0280A0_BLEND_CLAMP(color_info
) &&
943 !G_0280A0_BLEND_FLOAT32(color_info
)) {
944 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
945 surf
->export_16bpc
= true;
948 /* EXPORT_NORM can be enabled if:
949 * - 11-bit or smaller UNORM/SNORM/SRGB
950 * - 16-bit or smaller FLOAT
952 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
953 ((desc
->channel
[i
].size
< 12 &&
954 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
955 ntype
!= V_0280A0_NUMBER_UINT
&& ntype
!= V_0280A0_NUMBER_SINT
) ||
956 (desc
->channel
[i
].size
< 17 &&
957 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
958 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
959 surf
->export_16bpc
= true;
963 /* These might not always be initialized to zero. */
964 surf
->cb_color_base
= offset
>> 8;
965 surf
->cb_color_size
= S_028060_PITCH_TILE_MAX(pitch
) |
966 S_028060_SLICE_TILE_MAX(slice
);
967 surf
->cb_color_fmask
= surf
->cb_color_base
;
968 surf
->cb_color_cmask
= surf
->cb_color_base
;
969 surf
->cb_color_mask
= 0;
971 r600_resource_reference(&surf
->cb_buffer_cmask
, &rtex
->resource
);
972 r600_resource_reference(&surf
->cb_buffer_fmask
, &rtex
->resource
);
974 if (rtex
->cmask
.size
) {
975 surf
->cb_color_cmask
= rtex
->cmask
.offset
>> 8;
976 surf
->cb_color_mask
|= S_028100_CMASK_BLOCK_MAX(rtex
->cmask
.slice_tile_max
);
978 if (rtex
->fmask
.size
) {
979 color_info
|= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE
);
980 surf
->cb_color_fmask
= rtex
->fmask
.offset
>> 8;
981 surf
->cb_color_mask
|= S_028100_FMASK_TILE_MAX(rtex
->fmask
.slice_tile_max
);
982 } else { /* cmask only */
983 color_info
|= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE
);
985 } else if (force_cmask_fmask
) {
986 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
988 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
989 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
990 * because it's not an MSAA buffer.
992 struct r600_cmask_info cmask
;
993 struct r600_fmask_info fmask
;
995 r600_texture_get_cmask_info(&rscreen
->b
, rtex
, &cmask
);
996 r600_texture_get_fmask_info(&rscreen
->b
, rtex
, 8, &fmask
);
999 if (!rctx
->dummy_cmask
||
1000 rctx
->dummy_cmask
->b
.b
.width0
< cmask
.size
||
1001 rctx
->dummy_cmask
->buf
->alignment
% cmask
.alignment
!= 0) {
1002 struct pipe_transfer
*transfer
;
1005 r600_resource_reference(&rctx
->dummy_cmask
, NULL
);
1006 rctx
->dummy_cmask
= r600_buffer_create_helper(rscreen
, cmask
.size
, cmask
.alignment
);
1008 /* Set the contents to 0xCC. */
1009 ptr
= pipe_buffer_map(&rctx
->b
.b
, &rctx
->dummy_cmask
->b
.b
, PIPE_TRANSFER_WRITE
, &transfer
);
1010 memset(ptr
, 0xCC, cmask
.size
);
1011 pipe_buffer_unmap(&rctx
->b
.b
, transfer
);
1013 r600_resource_reference(&surf
->cb_buffer_cmask
, rctx
->dummy_cmask
);
1016 if (!rctx
->dummy_fmask
||
1017 rctx
->dummy_fmask
->b
.b
.width0
< fmask
.size
||
1018 rctx
->dummy_fmask
->buf
->alignment
% fmask
.alignment
!= 0) {
1019 r600_resource_reference(&rctx
->dummy_fmask
, NULL
);
1020 rctx
->dummy_fmask
= r600_buffer_create_helper(rscreen
, fmask
.size
, fmask
.alignment
);
1023 r600_resource_reference(&surf
->cb_buffer_fmask
, rctx
->dummy_fmask
);
1025 /* Init the registers. */
1026 color_info
|= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE
);
1027 surf
->cb_color_cmask
= 0;
1028 surf
->cb_color_fmask
= 0;
1029 surf
->cb_color_mask
= S_028100_CMASK_BLOCK_MAX(cmask
.slice_tile_max
) |
1030 S_028100_FMASK_TILE_MAX(fmask
.slice_tile_max
);
1033 surf
->cb_color_info
= color_info
;
1034 surf
->cb_color_view
= color_view
;
1035 surf
->color_initialized
= true;
1038 static void r600_init_depth_surface(struct r600_context
*rctx
,
1039 struct r600_surface
*surf
)
1041 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1042 unsigned level
, pitch
, slice
, format
, offset
, array_mode
;
1044 level
= surf
->base
.u
.tex
.level
;
1045 offset
= rtex
->surface
.level
[level
].offset
;
1046 pitch
= rtex
->surface
.level
[level
].nblk_x
/ 8 - 1;
1047 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1051 switch (rtex
->surface
.level
[level
].mode
) {
1052 case RADEON_SURF_MODE_2D
:
1053 array_mode
= V_0280A0_ARRAY_2D_TILED_THIN1
;
1055 case RADEON_SURF_MODE_1D
:
1056 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1058 array_mode
= V_0280A0_ARRAY_1D_TILED_THIN1
;
1062 format
= r600_translate_dbformat(surf
->base
.format
);
1063 assert(format
!= ~0);
1065 surf
->db_depth_info
= S_028010_ARRAY_MODE(array_mode
) | S_028010_FORMAT(format
);
1066 surf
->db_depth_base
= offset
>> 8;
1067 surf
->db_depth_view
= S_028004_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1068 S_028004_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1069 surf
->db_depth_size
= S_028000_PITCH_TILE_MAX(pitch
) | S_028000_SLICE_TILE_MAX(slice
);
1070 surf
->db_prefetch_limit
= (rtex
->surface
.level
[level
].nblk_y
/ 8) - 1;
1072 /* use htile only for first level */
1073 if (rtex
->htile_buffer
&& !level
) {
1074 surf
->db_htile_data_base
= 0;
1075 surf
->db_htile_surface
= S_028D24_HTILE_WIDTH(1) |
1076 S_028D24_HTILE_HEIGHT(1) |
1077 S_028D24_FULL_CACHE(1);
1078 /* preload is not working properly on r6xx/r7xx */
1079 surf
->db_depth_info
|= S_028010_TILE_SURFACE_ENABLE(1);
1082 surf
->depth_initialized
= true;
1085 static void r600_set_framebuffer_state(struct pipe_context
*ctx
,
1086 const struct pipe_framebuffer_state
*state
)
1088 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1089 struct r600_surface
*surf
;
1090 struct r600_texture
*rtex
;
1093 /* Flush TC when changing the framebuffer state, because the only
1094 * client not using TC that can change textures is the framebuffer.
1095 * Other places don't typically have to flush TC.
1097 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
|
1098 R600_CONTEXT_FLUSH_AND_INV
|
1099 R600_CONTEXT_FLUSH_AND_INV_CB
|
1100 R600_CONTEXT_FLUSH_AND_INV_CB_META
|
1101 R600_CONTEXT_FLUSH_AND_INV_DB
|
1102 R600_CONTEXT_FLUSH_AND_INV_DB_META
|
1103 R600_CONTEXT_INV_TEX_CACHE
;
1105 /* Set the new state. */
1106 util_copy_framebuffer_state(&rctx
->framebuffer
.state
, state
);
1108 rctx
->framebuffer
.export_16bpc
= state
->nr_cbufs
!= 0;
1109 rctx
->framebuffer
.cb0_is_integer
= state
->nr_cbufs
&& state
->cbufs
[0] &&
1110 util_format_is_pure_integer(state
->cbufs
[0]->format
);
1111 rctx
->framebuffer
.compressed_cb_mask
= 0;
1112 rctx
->framebuffer
.is_msaa_resolve
= state
->nr_cbufs
== 2 &&
1113 state
->cbufs
[0] && state
->cbufs
[1] &&
1114 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
1115 state
->cbufs
[1]->texture
->nr_samples
<= 1;
1116 rctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
1119 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
1120 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1121 bool force_cmask_fmask
= rctx
->b
.chip_class
== R600
&&
1122 rctx
->framebuffer
.is_msaa_resolve
&&
1125 surf
= (struct r600_surface
*)state
->cbufs
[i
];
1129 rtex
= (struct r600_texture
*)surf
->base
.texture
;
1130 r600_context_add_resource_size(ctx
, state
->cbufs
[i
]->texture
);
1132 if (!surf
->color_initialized
|| force_cmask_fmask
) {
1133 r600_init_color_surface(rctx
, surf
, force_cmask_fmask
);
1134 if (force_cmask_fmask
) {
1135 /* re-initialize later without compression */
1136 surf
->color_initialized
= false;
1140 if (!surf
->export_16bpc
) {
1141 rctx
->framebuffer
.export_16bpc
= false;
1144 if (rtex
->fmask
.size
&& rtex
->cmask
.size
) {
1145 rctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
1149 /* Update alpha-test state dependencies.
1150 * Alpha-test is done on the first colorbuffer only. */
1151 if (state
->nr_cbufs
) {
1152 bool alphatest_bypass
= false;
1154 surf
= (struct r600_surface
*)state
->cbufs
[0];
1156 alphatest_bypass
= surf
->alphatest_bypass
;
1159 if (rctx
->alphatest_state
.bypass
!= alphatest_bypass
) {
1160 rctx
->alphatest_state
.bypass
= alphatest_bypass
;
1161 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1167 surf
= (struct r600_surface
*)state
->zsbuf
;
1169 r600_context_add_resource_size(ctx
, state
->zsbuf
->texture
);
1171 if (!surf
->depth_initialized
) {
1172 r600_init_depth_surface(rctx
, surf
);
1175 if (state
->zsbuf
->format
!= rctx
->poly_offset_state
.zs_format
) {
1176 rctx
->poly_offset_state
.zs_format
= state
->zsbuf
->format
;
1177 r600_mark_atom_dirty(rctx
, &rctx
->poly_offset_state
.atom
);
1180 if (rctx
->db_state
.rsurf
!= surf
) {
1181 rctx
->db_state
.rsurf
= surf
;
1182 r600_mark_atom_dirty(rctx
, &rctx
->db_state
.atom
);
1183 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1185 } else if (rctx
->db_state
.rsurf
) {
1186 rctx
->db_state
.rsurf
= NULL
;
1187 r600_mark_atom_dirty(rctx
, &rctx
->db_state
.atom
);
1188 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1191 if (rctx
->cb_misc_state
.nr_cbufs
!= state
->nr_cbufs
) {
1192 rctx
->cb_misc_state
.nr_cbufs
= state
->nr_cbufs
;
1193 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1196 if (state
->nr_cbufs
== 0 && rctx
->alphatest_state
.bypass
) {
1197 rctx
->alphatest_state
.bypass
= false;
1198 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1201 /* Calculate the CS size. */
1202 rctx
->framebuffer
.atom
.num_dw
=
1203 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1205 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1206 rctx
->framebuffer
.atom
.num_dw
+= 15 * rctx
->framebuffer
.state
.nr_cbufs
;
1207 rctx
->framebuffer
.atom
.num_dw
+= 3 * (2 + rctx
->framebuffer
.state
.nr_cbufs
);
1209 if (rctx
->framebuffer
.state
.zsbuf
) {
1210 rctx
->framebuffer
.atom
.num_dw
+= 16;
1211 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1212 rctx
->framebuffer
.atom
.num_dw
+= 3;
1214 if (rctx
->b
.family
> CHIP_R600
&& rctx
->b
.family
< CHIP_RV770
) {
1215 rctx
->framebuffer
.atom
.num_dw
+= 2;
1218 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
1220 r600_set_sample_locations_constant_buffer(rctx
);
1223 static uint32_t sample_locs_2x
[] = {
1224 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1225 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1227 static unsigned max_dist_2x
= 4;
1229 static uint32_t sample_locs_4x
[] = {
1230 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1231 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1233 static unsigned max_dist_4x
= 6;
1234 static uint32_t sample_locs_8x
[] = {
1235 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1236 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1238 static unsigned max_dist_8x
= 7;
1240 static void r600_get_sample_position(struct pipe_context
*ctx
,
1241 unsigned sample_count
,
1242 unsigned sample_index
,
1249 switch (sample_count
) {
1252 out_value
[0] = out_value
[1] = 0.5;
1255 offset
= 4 * (sample_index
* 2);
1256 val
.idx
= (sample_locs_2x
[0] >> offset
) & 0xf;
1257 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1258 val
.idx
= (sample_locs_2x
[0] >> (offset
+ 4)) & 0xf;
1259 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1262 offset
= 4 * (sample_index
* 2);
1263 val
.idx
= (sample_locs_4x
[0] >> offset
) & 0xf;
1264 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1265 val
.idx
= (sample_locs_4x
[0] >> (offset
+ 4)) & 0xf;
1266 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1269 offset
= 4 * (sample_index
% 4 * 2);
1270 index
= (sample_index
/ 4);
1271 val
.idx
= (sample_locs_8x
[index
] >> offset
) & 0xf;
1272 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1273 val
.idx
= (sample_locs_8x
[index
] >> (offset
+ 4)) & 0xf;
1274 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1279 static void r600_emit_msaa_state(struct r600_context
*rctx
, int nr_samples
)
1281 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1282 unsigned max_dist
= 0;
1284 if (rctx
->b
.family
== CHIP_R600
) {
1285 switch (nr_samples
) {
1290 radeon_set_config_reg(cs
, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S
, sample_locs_2x
[0]);
1291 max_dist
= max_dist_2x
;
1294 radeon_set_config_reg(cs
, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S
, sample_locs_4x
[0]);
1295 max_dist
= max_dist_4x
;
1298 radeon_set_config_reg_seq(cs
, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0
, 2);
1299 radeon_emit(cs
, sample_locs_8x
[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1300 radeon_emit(cs
, sample_locs_8x
[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1301 max_dist
= max_dist_8x
;
1305 switch (nr_samples
) {
1307 radeon_set_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1308 radeon_emit(cs
, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1309 radeon_emit(cs
, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1313 radeon_set_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1314 radeon_emit(cs
, sample_locs_2x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1315 radeon_emit(cs
, sample_locs_2x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1316 max_dist
= max_dist_2x
;
1319 radeon_set_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1320 radeon_emit(cs
, sample_locs_4x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1321 radeon_emit(cs
, sample_locs_4x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1322 max_dist
= max_dist_4x
;
1325 radeon_set_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1326 radeon_emit(cs
, sample_locs_8x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1327 radeon_emit(cs
, sample_locs_8x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1328 max_dist
= max_dist_8x
;
1333 if (nr_samples
> 1) {
1334 radeon_set_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1335 radeon_emit(cs
, S_028C00_LAST_PIXEL(1) |
1336 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1337 radeon_emit(cs
, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples
)) |
1338 S_028C04_MAX_SAMPLE_DIST(max_dist
)); /* R_028C04_PA_SC_AA_CONFIG */
1340 radeon_set_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1341 radeon_emit(cs
, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1342 radeon_emit(cs
, 0); /* R_028C04_PA_SC_AA_CONFIG */
1346 static void r600_emit_framebuffer_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1348 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1349 struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
.state
;
1350 unsigned nr_cbufs
= state
->nr_cbufs
;
1351 struct r600_surface
**cb
= (struct r600_surface
**)&state
->cbufs
[0];
1352 unsigned i
, sbu
= 0;
1355 radeon_set_context_reg_seq(cs
, R_0280A0_CB_COLOR0_INFO
, 8);
1356 for (i
= 0; i
< nr_cbufs
; i
++) {
1357 radeon_emit(cs
, cb
[i
] ? cb
[i
]->cb_color_info
: 0);
1359 /* set CB_COLOR1_INFO for possible dual-src blending */
1360 if (i
== 1 && cb
[0]) {
1361 radeon_emit(cs
, cb
[0]->cb_color_info
);
1364 for (; i
< 8; i
++) {
1369 for (i
= 0; i
< nr_cbufs
; i
++) {
1376 radeon_set_context_reg(cs
, R_028040_CB_COLOR0_BASE
+ i
*4, cb
[i
]->cb_color_base
);
1378 reloc
= radeon_add_to_buffer_list(&rctx
->b
,
1380 (struct r600_resource
*)cb
[i
]->base
.texture
,
1381 RADEON_USAGE_READWRITE
,
1382 cb
[i
]->base
.texture
->nr_samples
> 1 ?
1383 RADEON_PRIO_COLOR_BUFFER_MSAA
:
1384 RADEON_PRIO_COLOR_BUFFER
);
1385 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1386 radeon_emit(cs
, reloc
);
1389 radeon_set_context_reg(cs
, R_0280E0_CB_COLOR0_FRAG
+ i
*4, cb
[i
]->cb_color_fmask
);
1391 reloc
= radeon_add_to_buffer_list(&rctx
->b
,
1393 cb
[i
]->cb_buffer_fmask
,
1394 RADEON_USAGE_READWRITE
,
1395 cb
[i
]->base
.texture
->nr_samples
> 1 ?
1396 RADEON_PRIO_COLOR_BUFFER_MSAA
:
1397 RADEON_PRIO_COLOR_BUFFER
);
1398 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1399 radeon_emit(cs
, reloc
);
1402 radeon_set_context_reg(cs
, R_0280C0_CB_COLOR0_TILE
+ i
*4, cb
[i
]->cb_color_cmask
);
1404 reloc
= radeon_add_to_buffer_list(&rctx
->b
,
1406 cb
[i
]->cb_buffer_cmask
,
1407 RADEON_USAGE_READWRITE
,
1408 cb
[i
]->base
.texture
->nr_samples
> 1 ?
1409 RADEON_PRIO_COLOR_BUFFER_MSAA
:
1410 RADEON_PRIO_COLOR_BUFFER
);
1411 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1412 radeon_emit(cs
, reloc
);
1415 radeon_set_context_reg_seq(cs
, R_028060_CB_COLOR0_SIZE
, nr_cbufs
);
1416 for (i
= 0; i
< nr_cbufs
; i
++) {
1417 radeon_emit(cs
, cb
[i
] ? cb
[i
]->cb_color_size
: 0);
1420 radeon_set_context_reg_seq(cs
, R_028080_CB_COLOR0_VIEW
, nr_cbufs
);
1421 for (i
= 0; i
< nr_cbufs
; i
++) {
1422 radeon_emit(cs
, cb
[i
] ? cb
[i
]->cb_color_view
: 0);
1425 radeon_set_context_reg_seq(cs
, R_028100_CB_COLOR0_MASK
, nr_cbufs
);
1426 for (i
= 0; i
< nr_cbufs
; i
++) {
1427 radeon_emit(cs
, cb
[i
] ? cb
[i
]->cb_color_mask
: 0);
1430 sbu
|= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs
);
1433 /* SURFACE_BASE_UPDATE */
1434 if (rctx
->b
.family
> CHIP_R600
&& rctx
->b
.family
< CHIP_RV770
&& sbu
) {
1435 radeon_emit(cs
, PKT3(PKT3_SURFACE_BASE_UPDATE
, 0, 0));
1436 radeon_emit(cs
, sbu
);
1442 struct r600_surface
*surf
= (struct r600_surface
*)state
->zsbuf
;
1443 unsigned reloc
= radeon_add_to_buffer_list(&rctx
->b
,
1445 (struct r600_resource
*)state
->zsbuf
->texture
,
1446 RADEON_USAGE_READWRITE
,
1447 surf
->base
.texture
->nr_samples
> 1 ?
1448 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
1449 RADEON_PRIO_DEPTH_BUFFER
);
1451 radeon_set_context_reg_seq(cs
, R_028000_DB_DEPTH_SIZE
, 2);
1452 radeon_emit(cs
, surf
->db_depth_size
); /* R_028000_DB_DEPTH_SIZE */
1453 radeon_emit(cs
, surf
->db_depth_view
); /* R_028004_DB_DEPTH_VIEW */
1454 radeon_set_context_reg_seq(cs
, R_02800C_DB_DEPTH_BASE
, 2);
1455 radeon_emit(cs
, surf
->db_depth_base
); /* R_02800C_DB_DEPTH_BASE */
1456 radeon_emit(cs
, surf
->db_depth_info
); /* R_028010_DB_DEPTH_INFO */
1458 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1459 radeon_emit(cs
, reloc
);
1461 radeon_set_context_reg(cs
, R_028D34_DB_PREFETCH_LIMIT
, surf
->db_prefetch_limit
);
1463 sbu
|= SURFACE_BASE_UPDATE_DEPTH
;
1464 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1465 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1466 * Older kernels are out of luck. */
1467 radeon_set_context_reg(cs
, R_028010_DB_DEPTH_INFO
, S_028010_FORMAT(V_028010_DEPTH_INVALID
));
1470 /* SURFACE_BASE_UPDATE */
1471 if (rctx
->b
.family
> CHIP_R600
&& rctx
->b
.family
< CHIP_RV770
&& sbu
) {
1472 radeon_emit(cs
, PKT3(PKT3_SURFACE_BASE_UPDATE
, 0, 0));
1473 radeon_emit(cs
, sbu
);
1477 /* Framebuffer dimensions. */
1478 radeon_set_context_reg_seq(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, 2);
1479 radeon_emit(cs
, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1480 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1481 radeon_emit(cs
, S_028244_BR_X(state
->width
) |
1482 S_028244_BR_Y(state
->height
)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1484 if (rctx
->framebuffer
.is_msaa_resolve
) {
1485 radeon_set_context_reg(cs
, R_0287A0_CB_SHADER_CONTROL
, 1);
1487 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1488 * will assure that the alpha-test will work even if there is
1489 * no colorbuffer bound. */
1490 radeon_set_context_reg(cs
, R_0287A0_CB_SHADER_CONTROL
,
1491 (1ull << MAX2(nr_cbufs
, 1)) - 1);
1494 r600_emit_msaa_state(rctx
, rctx
->framebuffer
.nr_samples
);
1497 static void r600_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
1499 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1501 if (rctx
->ps_iter_samples
== min_samples
)
1504 rctx
->ps_iter_samples
= min_samples
;
1505 if (rctx
->framebuffer
.nr_samples
> 1) {
1506 r600_mark_atom_dirty(rctx
, &rctx
->rasterizer_state
.atom
);
1507 if (rctx
->b
.chip_class
== R600
)
1508 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1512 static void r600_emit_cb_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1514 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1515 struct r600_cb_misc_state
*a
= (struct r600_cb_misc_state
*)atom
;
1517 if (G_028808_SPECIAL_OP(a
->cb_color_control
) == V_028808_SPECIAL_RESOLVE_BOX
) {
1518 radeon_set_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1519 if (rctx
->b
.chip_class
== R600
) {
1520 radeon_emit(cs
, 0xff); /* R_028238_CB_TARGET_MASK */
1521 radeon_emit(cs
, 0xff); /* R_02823C_CB_SHADER_MASK */
1523 radeon_emit(cs
, 0xf); /* R_028238_CB_TARGET_MASK */
1524 radeon_emit(cs
, 0xf); /* R_02823C_CB_SHADER_MASK */
1526 radeon_set_context_reg(cs
, R_028808_CB_COLOR_CONTROL
, a
->cb_color_control
);
1528 unsigned fb_colormask
= (1ULL << ((unsigned)a
->nr_cbufs
* 4)) - 1;
1529 unsigned ps_colormask
= (1ULL << ((unsigned)a
->nr_ps_color_outputs
* 4)) - 1;
1530 unsigned multiwrite
= a
->multiwrite
&& a
->nr_cbufs
> 1;
1532 radeon_set_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1533 radeon_emit(cs
, a
->blend_colormask
& fb_colormask
); /* R_028238_CB_TARGET_MASK */
1534 /* Always enable the first color output to make sure alpha-test works even without one. */
1535 radeon_emit(cs
, 0xf | (multiwrite
? fb_colormask
: ps_colormask
)); /* R_02823C_CB_SHADER_MASK */
1536 radeon_set_context_reg(cs
, R_028808_CB_COLOR_CONTROL
,
1537 a
->cb_color_control
|
1538 S_028808_MULTIWRITE_ENABLE(multiwrite
));
1542 static void r600_emit_db_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1544 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1545 struct r600_db_state
*a
= (struct r600_db_state
*)atom
;
1547 if (a
->rsurf
&& a
->rsurf
->db_htile_surface
) {
1548 struct r600_texture
*rtex
= (struct r600_texture
*)a
->rsurf
->base
.texture
;
1551 radeon_set_context_reg(cs
, R_02802C_DB_DEPTH_CLEAR
, fui(rtex
->depth_clear_value
));
1552 radeon_set_context_reg(cs
, R_028D24_DB_HTILE_SURFACE
, a
->rsurf
->db_htile_surface
);
1553 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, a
->rsurf
->db_htile_data_base
);
1554 reloc_idx
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rtex
->htile_buffer
,
1555 RADEON_USAGE_READWRITE
, RADEON_PRIO_HTILE
);
1556 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1557 radeon_emit(cs
, reloc_idx
);
1559 radeon_set_context_reg(cs
, R_028D24_DB_HTILE_SURFACE
, 0);
1563 static void r600_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1565 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1566 struct r600_db_misc_state
*a
= (struct r600_db_misc_state
*)atom
;
1567 unsigned db_render_control
= 0;
1568 unsigned db_render_override
=
1569 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE
) |
1570 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE
);
1572 if (rctx
->b
.chip_class
>= R700
) {
1573 switch (a
->ps_conservative_z
) {
1574 default: /* fall through */
1575 case TGSI_FS_DEPTH_LAYOUT_ANY
:
1576 db_render_control
|= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_ANY_Z
);
1578 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
1579 db_render_control
|= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_GREATER_THAN_Z
);
1581 case TGSI_FS_DEPTH_LAYOUT_LESS
:
1582 db_render_control
|= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_LESS_THAN_Z
);
1587 if (rctx
->b
.num_occlusion_queries
> 0 &&
1588 !a
->occlusion_queries_disabled
) {
1589 if (rctx
->b
.chip_class
>= R700
) {
1590 db_render_control
|= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1592 db_render_override
|= S_028D10_NOOP_CULL_DISABLE(1);
1594 db_render_control
|= S_028D0C_ZPASS_INCREMENT_DISABLE(1);
1597 if (rctx
->db_state
.rsurf
&& rctx
->db_state
.rsurf
->db_htile_surface
) {
1598 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1599 db_render_override
|= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF
);
1600 /* This is to fix a lockup when hyperz and alpha test are enabled at
1601 * the same time somehow GPU get confuse on which order to pick for
1604 if (rctx
->alphatest_state
.sx_alpha_test_control
) {
1605 db_render_override
|= S_028D10_FORCE_SHADER_Z_ORDER(1);
1608 db_render_override
|= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE
);
1610 if (rctx
->b
.chip_class
== R600
&& rctx
->framebuffer
.nr_samples
> 1 && rctx
->ps_iter_samples
> 0) {
1611 /* sample shading and hyperz causes lockups on R6xx chips */
1612 db_render_override
|= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE
);
1614 if (a
->flush_depthstencil_through_cb
) {
1615 assert(a
->copy_depth
|| a
->copy_stencil
);
1617 db_render_control
|= S_028D0C_DEPTH_COPY_ENABLE(a
->copy_depth
) |
1618 S_028D0C_STENCIL_COPY_ENABLE(a
->copy_stencil
) |
1619 S_028D0C_COPY_CENTROID(1) |
1620 S_028D0C_COPY_SAMPLE(a
->copy_sample
);
1622 if (rctx
->b
.chip_class
== R600
)
1623 db_render_override
|= S_028D10_NOOP_CULL_DISABLE(1);
1625 if (rctx
->b
.family
== CHIP_RV610
|| rctx
->b
.family
== CHIP_RV630
||
1626 rctx
->b
.family
== CHIP_RV620
|| rctx
->b
.family
== CHIP_RV635
)
1627 db_render_override
|= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE
);
1628 } else if (a
->flush_depth_inplace
|| a
->flush_stencil_inplace
) {
1629 db_render_control
|= S_028D0C_DEPTH_COMPRESS_DISABLE(a
->flush_depth_inplace
) |
1630 S_028D0C_STENCIL_COMPRESS_DISABLE(a
->flush_stencil_inplace
);
1631 db_render_override
|= S_028D10_NOOP_CULL_DISABLE(1);
1633 if (a
->htile_clear
) {
1634 db_render_control
|= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1637 /* RV770 workaround for a hang with 8x MSAA. */
1638 if (rctx
->b
.family
== CHIP_RV770
&& a
->log_samples
== 3) {
1639 db_render_override
|= S_028D10_MAX_TILES_IN_DTT(6);
1642 radeon_set_context_reg_seq(cs
, R_028D0C_DB_RENDER_CONTROL
, 2);
1643 radeon_emit(cs
, db_render_control
); /* R_028D0C_DB_RENDER_CONTROL */
1644 radeon_emit(cs
, db_render_override
); /* R_028D10_DB_RENDER_OVERRIDE */
1645 radeon_set_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
, a
->db_shader_control
);
1648 static void r600_emit_config_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1650 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1651 struct r600_config_state
*a
= (struct r600_config_state
*)atom
;
1653 radeon_set_config_reg(cs
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, a
->sq_gpr_resource_mgmt_1
);
1654 radeon_set_config_reg(cs
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, a
->sq_gpr_resource_mgmt_2
);
1657 static void r600_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1659 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1660 uint32_t dirty_mask
= rctx
->vertex_buffer_state
.dirty_mask
;
1662 while (dirty_mask
) {
1663 struct pipe_vertex_buffer
*vb
;
1664 struct r600_resource
*rbuffer
;
1666 unsigned buffer_index
= u_bit_scan(&dirty_mask
);
1668 vb
= &rctx
->vertex_buffer_state
.vb
[buffer_index
];
1669 rbuffer
= (struct r600_resource
*)vb
->buffer
;
1672 offset
= vb
->buffer_offset
;
1674 /* fetch resources start at index 320 (OFFSET_FS) */
1675 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1676 radeon_emit(cs
, (R600_FETCH_CONSTANTS_OFFSET_FS
+ buffer_index
) * 7);
1677 radeon_emit(cs
, offset
); /* RESOURCEi_WORD0 */
1678 radeon_emit(cs
, rbuffer
->b
.b
.width0
- offset
- 1); /* RESOURCEi_WORD1 */
1679 radeon_emit(cs
, /* RESOURCEi_WORD2 */
1680 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1681 S_038008_STRIDE(vb
->stride
));
1682 radeon_emit(cs
, 0); /* RESOURCEi_WORD3 */
1683 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
1684 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
1685 radeon_emit(cs
, 0xc0000000); /* RESOURCEi_WORD6 */
1687 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1688 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
1689 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
));
1693 static void r600_emit_constant_buffers(struct r600_context
*rctx
,
1694 struct r600_constbuf_state
*state
,
1695 unsigned buffer_id_base
,
1696 unsigned reg_alu_constbuf_size
,
1697 unsigned reg_alu_const_cache
)
1699 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1700 uint32_t dirty_mask
= state
->dirty_mask
;
1702 while (dirty_mask
) {
1703 struct pipe_constant_buffer
*cb
;
1704 struct r600_resource
*rbuffer
;
1706 unsigned buffer_index
= ffs(dirty_mask
) - 1;
1707 unsigned gs_ring_buffer
= (buffer_index
== R600_GS_RING_CONST_BUFFER
);
1708 cb
= &state
->cb
[buffer_index
];
1709 rbuffer
= (struct r600_resource
*)cb
->buffer
;
1712 offset
= cb
->buffer_offset
;
1714 if (!gs_ring_buffer
) {
1715 radeon_set_context_reg(cs
, reg_alu_constbuf_size
+ buffer_index
* 4,
1716 DIV_ROUND_UP(cb
->buffer_size
, 256));
1717 radeon_set_context_reg(cs
, reg_alu_const_cache
+ buffer_index
* 4, offset
>> 8);
1720 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1721 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
1722 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
));
1724 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1725 radeon_emit(cs
, (buffer_id_base
+ buffer_index
) * 7);
1726 radeon_emit(cs
, offset
); /* RESOURCEi_WORD0 */
1727 radeon_emit(cs
, rbuffer
->b
.b
.width0
- offset
- 1); /* RESOURCEi_WORD1 */
1728 radeon_emit(cs
, /* RESOURCEi_WORD2 */
1729 S_038008_ENDIAN_SWAP(gs_ring_buffer
? ENDIAN_NONE
: r600_endian_swap(32)) |
1730 S_038008_STRIDE(gs_ring_buffer
? 4 : 16));
1731 radeon_emit(cs
, 0); /* RESOURCEi_WORD3 */
1732 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
1733 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
1734 radeon_emit(cs
, 0xc0000000); /* RESOURCEi_WORD6 */
1736 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1737 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
1738 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
));
1740 dirty_mask
&= ~(1 << buffer_index
);
1742 state
->dirty_mask
= 0;
1745 static void r600_emit_vs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1747 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
],
1748 R600_FETCH_CONSTANTS_OFFSET_VS
,
1749 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
1750 R_028980_ALU_CONST_CACHE_VS_0
);
1753 static void r600_emit_gs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1755 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
],
1756 R600_FETCH_CONSTANTS_OFFSET_GS
,
1757 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
,
1758 R_0289C0_ALU_CONST_CACHE_GS_0
);
1761 static void r600_emit_ps_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1763 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
],
1764 R600_FETCH_CONSTANTS_OFFSET_PS
,
1765 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
1766 R_028940_ALU_CONST_CACHE_PS_0
);
1769 static void r600_emit_sampler_views(struct r600_context
*rctx
,
1770 struct r600_samplerview_state
*state
,
1771 unsigned resource_id_base
)
1773 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1774 uint32_t dirty_mask
= state
->dirty_mask
;
1776 while (dirty_mask
) {
1777 struct r600_pipe_sampler_view
*rview
;
1778 unsigned resource_index
= u_bit_scan(&dirty_mask
);
1781 rview
= state
->views
[resource_index
];
1784 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1785 radeon_emit(cs
, (resource_id_base
+ resource_index
) * 7);
1786 radeon_emit_array(cs
, rview
->tex_resource_words
, 7);
1788 reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rview
->tex_resource
,
1790 r600_get_sampler_view_priority(rview
->tex_resource
));
1791 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1792 radeon_emit(cs
, reloc
);
1793 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1794 radeon_emit(cs
, reloc
);
1796 state
->dirty_mask
= 0;
1800 static void r600_emit_vs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
1802 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
, R600_FETCH_CONSTANTS_OFFSET_VS
+ R600_MAX_CONST_BUFFERS
);
1805 static void r600_emit_gs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
1807 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
, R600_FETCH_CONSTANTS_OFFSET_GS
+ R600_MAX_CONST_BUFFERS
);
1810 static void r600_emit_ps_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
1812 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
, R600_FETCH_CONSTANTS_OFFSET_PS
+ R600_MAX_CONST_BUFFERS
);
1815 static void r600_emit_sampler_states(struct r600_context
*rctx
,
1816 struct r600_textures_info
*texinfo
,
1817 unsigned resource_id_base
,
1818 unsigned border_color_reg
)
1820 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1821 uint32_t dirty_mask
= texinfo
->states
.dirty_mask
;
1823 while (dirty_mask
) {
1824 struct r600_pipe_sampler_state
*rstate
;
1825 struct r600_pipe_sampler_view
*rview
;
1826 unsigned i
= u_bit_scan(&dirty_mask
);
1828 rstate
= texinfo
->states
.states
[i
];
1830 rview
= texinfo
->views
.views
[i
];
1832 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1833 * filtering between layers.
1834 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1837 enum pipe_texture_target target
= rview
->base
.texture
->target
;
1838 if (target
== PIPE_TEXTURE_1D_ARRAY
||
1839 target
== PIPE_TEXTURE_2D_ARRAY
) {
1840 rstate
->tex_sampler_words
[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1841 texinfo
->is_array_sampler
[i
] = true;
1843 rstate
->tex_sampler_words
[0] &= C_03C000_TEX_ARRAY_OVERRIDE
;
1844 texinfo
->is_array_sampler
[i
] = false;
1848 radeon_emit(cs
, PKT3(PKT3_SET_SAMPLER
, 3, 0));
1849 radeon_emit(cs
, (resource_id_base
+ i
) * 3);
1850 radeon_emit_array(cs
, rstate
->tex_sampler_words
, 3);
1852 if (rstate
->border_color_use
) {
1855 offset
= border_color_reg
;
1857 radeon_set_config_reg_seq(cs
, offset
, 4);
1858 radeon_emit_array(cs
, rstate
->border_color
.ui
, 4);
1861 texinfo
->states
.dirty_mask
= 0;
1864 static void r600_emit_vs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
1866 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED
);
1869 static void r600_emit_gs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
1871 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED
);
1874 static void r600_emit_ps_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
1876 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED
);
1879 static void r600_emit_seamless_cube_map(struct r600_context
*rctx
, struct r600_atom
*atom
)
1881 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1884 tmp
= S_009508_DISABLE_CUBE_ANISO(1) |
1885 S_009508_SYNC_GRADIENT(1) |
1886 S_009508_SYNC_WALKER(1) |
1887 S_009508_SYNC_ALIGNER(1);
1888 if (!rctx
->seamless_cube_map
.enabled
) {
1889 tmp
|= S_009508_DISABLE_CUBE_WRAP(1);
1891 radeon_set_config_reg(cs
, R_009508_TA_CNTL_AUX
, tmp
);
1894 static void r600_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
1896 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
1897 uint8_t mask
= s
->sample_mask
;
1899 radeon_set_context_reg(rctx
->b
.gfx
.cs
, R_028C48_PA_SC_AA_MASK
,
1900 mask
| (mask
<< 8) | (mask
<< 16) | (mask
<< 24));
1903 static void r600_emit_vertex_fetch_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
1905 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1906 struct r600_cso_state
*state
= (struct r600_cso_state
*)a
;
1907 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
->cso
;
1909 radeon_set_context_reg(cs
, R_028894_SQ_PGM_START_FS
, shader
->offset
>> 8);
1910 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1911 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, shader
->buffer
,
1913 RADEON_PRIO_SHADER_BINARY
));
1916 static void r600_emit_shader_stages(struct r600_context
*rctx
, struct r600_atom
*a
)
1918 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1919 struct r600_shader_stages_state
*state
= (struct r600_shader_stages_state
*)a
;
1921 uint32_t v2
= 0, primid
= 0;
1923 if (rctx
->vs_shader
->current
->shader
.vs_as_gs_a
) {
1924 v2
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
1928 if (state
->geom_enable
) {
1931 if (rctx
->gs_shader
->gs_max_out_vertices
<= 128)
1932 cut_val
= V_028A40_GS_CUT_128
;
1933 else if (rctx
->gs_shader
->gs_max_out_vertices
<= 256)
1934 cut_val
= V_028A40_GS_CUT_256
;
1935 else if (rctx
->gs_shader
->gs_max_out_vertices
<= 512)
1936 cut_val
= V_028A40_GS_CUT_512
;
1938 cut_val
= V_028A40_GS_CUT_1024
;
1940 v2
= S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
1941 S_028A40_CUT_MODE(cut_val
);
1943 if (rctx
->gs_shader
->current
->shader
.gs_prim_id_input
)
1947 radeon_set_context_reg(cs
, R_028A40_VGT_GS_MODE
, v2
);
1948 radeon_set_context_reg(cs
, R_028A84_VGT_PRIMITIVEID_EN
, primid
);
1951 static void r600_emit_gs_rings(struct r600_context
*rctx
, struct r600_atom
*a
)
1953 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1954 struct r600_gs_rings_state
*state
= (struct r600_gs_rings_state
*)a
;
1955 struct r600_resource
*rbuffer
;
1957 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
1958 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1959 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
1961 if (state
->enable
) {
1962 rbuffer
=(struct r600_resource
*)state
->esgs_ring
.buffer
;
1963 radeon_set_config_reg(cs
, R_008C40_SQ_ESGS_RING_BASE
, 0);
1964 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1965 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
1966 RADEON_USAGE_READWRITE
,
1967 RADEON_PRIO_SHADER_RINGS
));
1968 radeon_set_config_reg(cs
, R_008C44_SQ_ESGS_RING_SIZE
,
1969 state
->esgs_ring
.buffer_size
>> 8);
1971 rbuffer
=(struct r600_resource
*)state
->gsvs_ring
.buffer
;
1972 radeon_set_config_reg(cs
, R_008C48_SQ_GSVS_RING_BASE
, 0);
1973 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1974 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
1975 RADEON_USAGE_READWRITE
,
1976 RADEON_PRIO_SHADER_RINGS
));
1977 radeon_set_config_reg(cs
, R_008C4C_SQ_GSVS_RING_SIZE
,
1978 state
->gsvs_ring
.buffer_size
>> 8);
1980 radeon_set_config_reg(cs
, R_008C44_SQ_ESGS_RING_SIZE
, 0);
1981 radeon_set_config_reg(cs
, R_008C4C_SQ_GSVS_RING_SIZE
, 0);
1984 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
1985 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1986 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
1989 /* Adjust GPR allocation on R6xx/R7xx */
1990 bool r600_adjust_gprs(struct r600_context
*rctx
)
1992 unsigned num_gprs
[R600_NUM_HW_STAGES
];
1993 unsigned new_gprs
[R600_NUM_HW_STAGES
];
1994 unsigned cur_gprs
[R600_NUM_HW_STAGES
];
1995 unsigned def_gprs
[R600_NUM_HW_STAGES
];
1996 unsigned def_num_clause_temp_gprs
= rctx
->r6xx_num_clause_temp_gprs
;
2000 bool need_recalc
= false, use_default
= true;
2002 /* hardware will reserve twice num_clause_temp_gprs */
2003 max_gprs
= def_num_clause_temp_gprs
* 2;
2004 for (i
= 0; i
< R600_NUM_HW_STAGES
; i
++) {
2005 def_gprs
[i
] = rctx
->default_gprs
[i
];
2006 max_gprs
+= def_gprs
[i
];
2009 cur_gprs
[R600_HW_STAGE_PS
] = G_008C04_NUM_PS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_1
);
2010 cur_gprs
[R600_HW_STAGE_VS
] = G_008C04_NUM_VS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_1
);
2011 cur_gprs
[R600_HW_STAGE_GS
] = G_008C08_NUM_GS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_2
);
2012 cur_gprs
[R600_HW_STAGE_ES
] = G_008C08_NUM_ES_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_2
);
2014 num_gprs
[R600_HW_STAGE_PS
] = rctx
->ps_shader
->current
->shader
.bc
.ngpr
;
2015 if (rctx
->gs_shader
) {
2016 num_gprs
[R600_HW_STAGE_ES
] = rctx
->vs_shader
->current
->shader
.bc
.ngpr
;
2017 num_gprs
[R600_HW_STAGE_GS
] = rctx
->gs_shader
->current
->shader
.bc
.ngpr
;
2018 num_gprs
[R600_HW_STAGE_VS
] = rctx
->gs_shader
->current
->gs_copy_shader
->shader
.bc
.ngpr
;
2020 num_gprs
[R600_HW_STAGE_ES
] = 0;
2021 num_gprs
[R600_HW_STAGE_GS
] = 0;
2022 num_gprs
[R600_HW_STAGE_VS
] = rctx
->vs_shader
->current
->shader
.bc
.ngpr
;
2025 for (i
= 0; i
< R600_NUM_HW_STAGES
; i
++) {
2026 new_gprs
[i
] = num_gprs
[i
];
2027 if (new_gprs
[i
] > cur_gprs
[i
])
2029 if (new_gprs
[i
] > def_gprs
[i
])
2030 use_default
= false;
2033 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2037 /* try to use switch back to default */
2039 /* always privilege vs stage so that at worst we have the
2040 * pixel stage producing wrong output (not the vertex
2042 new_gprs
[R600_HW_STAGE_PS
] = max_gprs
- def_num_clause_temp_gprs
* 2;
2043 for (i
= R600_HW_STAGE_VS
; i
< R600_NUM_HW_STAGES
; i
++)
2044 new_gprs
[R600_HW_STAGE_PS
] -= new_gprs
[i
];
2046 for (i
= 0; i
< R600_NUM_HW_STAGES
; i
++)
2047 new_gprs
[i
] = def_gprs
[i
];
2050 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2051 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2052 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2053 * it will lockup. So in this case just discard the draw command
2054 * and don't change the current gprs repartitions.
2056 for (i
= 0; i
< R600_NUM_HW_STAGES
; i
++) {
2057 if (num_gprs
[i
] > new_gprs
[i
]) {
2058 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2059 "for a combined maximum of %d\n",
2060 num_gprs
[R600_HW_STAGE_PS
], num_gprs
[R600_HW_STAGE_VS
], num_gprs
[R600_HW_STAGE_ES
], num_gprs
[R600_HW_STAGE_GS
], max_gprs
);
2065 /* in some case we endup recomputing the current value */
2066 tmp
= S_008C04_NUM_PS_GPRS(new_gprs
[R600_HW_STAGE_PS
]) |
2067 S_008C04_NUM_VS_GPRS(new_gprs
[R600_HW_STAGE_VS
]) |
2068 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs
);
2070 tmp2
= S_008C08_NUM_ES_GPRS(new_gprs
[R600_HW_STAGE_ES
]) |
2071 S_008C08_NUM_GS_GPRS(new_gprs
[R600_HW_STAGE_GS
]);
2072 if (rctx
->config_state
.sq_gpr_resource_mgmt_1
!= tmp
|| rctx
->config_state
.sq_gpr_resource_mgmt_2
!= tmp2
) {
2073 rctx
->config_state
.sq_gpr_resource_mgmt_1
= tmp
;
2074 rctx
->config_state
.sq_gpr_resource_mgmt_2
= tmp2
;
2075 r600_mark_atom_dirty(rctx
, &rctx
->config_state
.atom
);
2076 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
2081 void r600_init_atom_start_cs(struct r600_context
*rctx
)
2096 int num_ps_stack_entries
;
2097 int num_vs_stack_entries
;
2098 int num_gs_stack_entries
;
2099 int num_es_stack_entries
;
2100 enum radeon_family family
;
2101 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2104 r600_init_command_buffer(cb
, 256);
2106 /* R6xx requires this packet at the start of each command buffer */
2107 if (rctx
->b
.chip_class
== R600
) {
2108 r600_store_value(cb
, PKT3(PKT3_START_3D_CMDBUF
, 0, 0));
2109 r600_store_value(cb
, 0);
2111 /* All asics require this one */
2112 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2113 r600_store_value(cb
, 0x80000000);
2114 r600_store_value(cb
, 0x80000000);
2116 /* We're setting config registers here. */
2117 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2118 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2120 /* This enables pipeline stat & streamout queries.
2121 * They are only disabled by blits.
2123 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2124 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START
) | EVENT_INDEX(0));
2126 family
= rctx
->b
.family
;
2138 num_ps_threads
= 136;
2139 num_vs_threads
= 48;
2142 num_ps_stack_entries
= 128;
2143 num_vs_stack_entries
= 128;
2144 num_gs_stack_entries
= 0;
2145 num_es_stack_entries
= 0;
2154 num_ps_threads
= 144;
2155 num_vs_threads
= 40;
2158 num_ps_stack_entries
= 40;
2159 num_vs_stack_entries
= 40;
2160 num_gs_stack_entries
= 32;
2161 num_es_stack_entries
= 16;
2173 /* use limits 40 VS and at least 16 ES/GS */
2174 num_ps_threads
= 120;
2175 num_vs_threads
= 40;
2176 num_gs_threads
= 16;
2177 num_es_threads
= 16;
2178 num_ps_stack_entries
= 40;
2179 num_vs_stack_entries
= 40;
2180 num_gs_stack_entries
= 32;
2181 num_es_stack_entries
= 16;
2189 num_ps_threads
= 136;
2190 num_vs_threads
= 48;
2193 num_ps_stack_entries
= 40;
2194 num_vs_stack_entries
= 40;
2195 num_gs_stack_entries
= 32;
2196 num_es_stack_entries
= 16;
2204 num_ps_threads
= 180;
2205 num_vs_threads
= 60;
2208 num_ps_stack_entries
= 128;
2209 num_vs_stack_entries
= 128;
2210 num_gs_stack_entries
= 128;
2211 num_es_stack_entries
= 128;
2220 num_ps_threads
= 180;
2221 num_vs_threads
= 60;
2224 num_ps_stack_entries
= 128;
2225 num_vs_stack_entries
= 128;
2226 num_gs_stack_entries
= 0;
2227 num_es_stack_entries
= 0;
2235 num_ps_threads
= 136;
2236 num_vs_threads
= 48;
2239 num_ps_stack_entries
= 128;
2240 num_vs_stack_entries
= 128;
2241 num_gs_stack_entries
= 0;
2242 num_es_stack_entries
= 0;
2246 rctx
->default_gprs
[R600_HW_STAGE_PS
] = num_ps_gprs
;
2247 rctx
->default_gprs
[R600_HW_STAGE_VS
] = num_vs_gprs
;
2248 rctx
->default_gprs
[R600_HW_STAGE_GS
] = 0;
2249 rctx
->default_gprs
[R600_HW_STAGE_ES
] = 0;
2251 rctx
->r6xx_num_clause_temp_gprs
= num_temp_gprs
;
2263 tmp
|= S_008C00_VC_ENABLE(1);
2266 tmp
|= S_008C00_DX9_CONSTS(0);
2267 tmp
|= S_008C00_ALU_INST_PREFER_VECTOR(1);
2268 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2269 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2270 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2271 tmp
|= S_008C00_ES_PRIO(es_prio
);
2272 r600_store_config_reg(cb
, R_008C00_SQ_CONFIG
, tmp
);
2274 /* SQ_GPR_RESOURCE_MGMT_2 */
2275 tmp
= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
2276 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
2277 r600_store_config_reg_seq(cb
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, 4);
2278 r600_store_value(cb
, tmp
);
2280 /* SQ_THREAD_RESOURCE_MGMT */
2281 tmp
= S_008C0C_NUM_PS_THREADS(num_ps_threads
);
2282 tmp
|= S_008C0C_NUM_VS_THREADS(num_vs_threads
);
2283 tmp
|= S_008C0C_NUM_GS_THREADS(num_gs_threads
);
2284 tmp
|= S_008C0C_NUM_ES_THREADS(num_es_threads
);
2285 r600_store_value(cb
, tmp
); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2287 /* SQ_STACK_RESOURCE_MGMT_1 */
2288 tmp
= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
2289 tmp
|= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
2290 r600_store_value(cb
, tmp
); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2292 /* SQ_STACK_RESOURCE_MGMT_2 */
2293 tmp
= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
2294 tmp
|= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
2295 r600_store_value(cb
, tmp
); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2297 r600_store_config_reg(cb
, R_009714_VC_ENHANCE
, 0);
2299 if (rctx
->b
.chip_class
>= R700
) {
2300 r600_store_context_reg(cb
, R_028A50_VGT_ENHANCE
, 4);
2301 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0x00004000);
2302 r600_store_config_reg(cb
, R_009830_DB_DEBUG
, 0);
2303 r600_store_config_reg(cb
, R_009838_DB_WATERMARKS
, 0x00420204);
2304 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2306 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0);
2307 r600_store_config_reg(cb
, R_009830_DB_DEBUG
, 0x82000000);
2308 r600_store_config_reg(cb
, R_009838_DB_WATERMARKS
, 0x01020204);
2309 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 1);
2311 r600_store_context_reg_seq(cb
, R_0288A8_SQ_ESGS_RING_ITEMSIZE
, 9);
2312 r600_store_value(cb
, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2313 r600_store_value(cb
, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2314 r600_store_value(cb
, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2315 r600_store_value(cb
, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2316 r600_store_value(cb
, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2317 r600_store_value(cb
, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2318 r600_store_value(cb
, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2319 r600_store_value(cb
, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2320 r600_store_value(cb
, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2322 /* to avoid GPU doing any preloading of constant from random address */
2323 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
2324 for (i
= 0; i
< 16; i
++)
2325 r600_store_value(cb
, 0);
2327 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
2328 for (i
= 0; i
< 16; i
++)
2329 r600_store_value(cb
, 0);
2331 r600_store_context_reg_seq(cb
, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
, 16);
2332 for (i
= 0; i
< 16; i
++)
2333 r600_store_value(cb
, 0);
2335 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2336 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2337 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2338 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2339 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2340 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2341 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2342 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2343 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2344 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2345 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2346 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2347 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2348 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE, 0); */
2350 r600_store_context_reg(cb
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
2351 r600_store_context_reg(cb
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 0);
2352 r600_store_context_reg(cb
, R_028AA4_VGT_INSTANCE_STEP_RATE_1
, 0);
2354 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
2355 r600_store_value(cb
, 1); /* R_028AB4_VGT_REUSE_OFF */
2356 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2358 r600_store_context_reg(cb
, R_028B20_VGT_STRMOUT_BUFFER_EN
, 0);
2360 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2362 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
2364 r600_store_context_reg_seq(cb
, R_0286DC_SPI_FOG_CNTL
, 3);
2365 r600_store_value(cb
, 0); /* R_0286DC_SPI_FOG_CNTL */
2366 r600_store_value(cb
, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2367 r600_store_value(cb
, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2369 r600_store_context_reg_seq(cb
, R_028D28_DB_SRESULTS_COMPARE_STATE0
, 3);
2370 r600_store_value(cb
, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2371 r600_store_value(cb
, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2372 r600_store_value(cb
, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2374 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2375 r600_store_context_reg(cb
, R_028A48_PA_SC_MPASS_PS_CNTL
, 0);
2377 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2378 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2380 if (rctx
->b
.chip_class
>= R700
) {
2381 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2384 r600_store_context_reg_seq(cb
, R_028C30_CB_CLRCMP_CONTROL
, 4);
2385 r600_store_value(cb
, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2386 r600_store_value(cb
, 0); /* R_028C34_CB_CLRCMP_SRC */
2387 r600_store_value(cb
, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2388 r600_store_value(cb
, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2390 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2391 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2392 r600_store_value(cb
, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2394 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2395 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2396 r600_store_value(cb
, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2398 r600_store_context_reg_seq(cb
, R_0288CC_SQ_PGM_CF_OFFSET_PS
, 5);
2399 r600_store_value(cb
, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2400 r600_store_value(cb
, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2401 r600_store_value(cb
, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2402 r600_store_value(cb
, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2403 r600_store_value(cb
, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2405 r600_store_context_reg(cb
, R_0288E0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
2407 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2408 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2409 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2411 r600_store_context_reg(cb
, R_0288A4_SQ_PGM_RESOURCES_FS
, 0);
2413 if (rctx
->b
.chip_class
== R700
)
2414 r600_store_context_reg(cb
, R_028350_SX_MISC
, 0);
2415 if (rctx
->b
.chip_class
== R700
&& rctx
->screen
->b
.has_streamout
)
2416 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
2418 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2419 if (rctx
->screen
->b
.has_streamout
) {
2420 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2423 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
, 0x1000FFF);
2424 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
+ (32 * 4), 0x1000FFF);
2425 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
+ (64 * 4), 0x1000FFF);
2428 void r600_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2430 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2431 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2432 struct r600_shader
*rshader
= &shader
->shader
;
2433 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
;
2434 int pos_index
= -1, face_index
= -1, fixed_pt_position_index
= -1;
2435 unsigned tmp
, sid
, ufi
= 0;
2436 int need_linear
= 0;
2437 unsigned z_export
= 0, stencil_export
= 0, mask_export
= 0;
2438 unsigned sprite_coord_enable
= rctx
->rasterizer
? rctx
->rasterizer
->sprite_coord_enable
: 0;
2441 r600_init_command_buffer(cb
, 64);
2446 r600_store_context_reg_seq(cb
, R_028644_SPI_PS_INPUT_CNTL_0
, rshader
->ninput
);
2447 for (i
= 0; i
< rshader
->ninput
; i
++) {
2448 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
2450 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
&& face_index
== -1)
2452 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_SAMPLEID
)
2453 fixed_pt_position_index
= i
;
2455 sid
= rshader
->input
[i
].spi_sid
;
2457 tmp
= S_028644_SEMANTIC(sid
);
2459 /* D3D 9 behaviour. GL is undefined */
2460 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
&& rshader
->input
[i
].sid
== 0)
2461 tmp
|= S_028644_DEFAULT_VAL(3);
2463 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
2464 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2465 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
2466 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
))
2467 tmp
|= S_028644_FLAT_SHADE(1);
2469 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
2470 sprite_coord_enable
& (1 << rshader
->input
[i
].sid
)) {
2471 tmp
|= S_028644_PT_SPRITE_TEX(1);
2474 if (rshader
->input
[i
].interpolate_location
== TGSI_INTERPOLATE_LOC_CENTROID
)
2475 tmp
|= S_028644_SEL_CENTROID(1);
2477 if (rshader
->input
[i
].interpolate_location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
2478 tmp
|= S_028644_SEL_SAMPLE(1);
2480 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
) {
2482 tmp
|= S_028644_SEL_LINEAR(1);
2485 r600_store_value(cb
, tmp
);
2488 db_shader_control
= 0;
2489 for (i
= 0; i
< rshader
->noutput
; i
++) {
2490 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2492 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2494 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
&&
2495 rctx
->framebuffer
.nr_samples
> 1 && rctx
->ps_iter_samples
> 0)
2498 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(z_export
);
2499 db_shader_control
|= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export
);
2500 db_shader_control
|= S_02880C_MASK_EXPORT_ENABLE(mask_export
);
2501 if (rshader
->uses_kill
)
2502 db_shader_control
|= S_02880C_KILL_ENABLE(1);
2505 for (i
= 0; i
< rshader
->noutput
; i
++) {
2506 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
2507 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
||
2508 rshader
->output
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
) {
2512 num_cout
= rshader
->nr_ps_color_exports
;
2513 exports_ps
|= S_028854_EXPORT_COLORS(num_cout
);
2515 /* always at least export 1 component per pixel */
2519 shader
->nr_ps_color_outputs
= num_cout
;
2521 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(rshader
->ninput
) |
2522 S_0286CC_PERSP_GRADIENT_ENA(1)|
2523 S_0286CC_LINEAR_GRADIENT_ENA(need_linear
);
2525 if (pos_index
!= -1) {
2526 spi_ps_in_control_0
|= (S_0286CC_POSITION_ENA(1) |
2527 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].interpolate_location
== TGSI_INTERPOLATE_LOC_CENTROID
) |
2528 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
) |
2529 S_0286CC_BARYC_SAMPLE_CNTL(1)) |
2530 S_0286CC_POSITION_SAMPLE(rshader
->input
[pos_index
].interpolate_location
== TGSI_INTERPOLATE_LOC_SAMPLE
);
2531 spi_input_z
|= S_0286D8_PROVIDE_Z_TO_SPI(1);
2534 spi_ps_in_control_1
= 0;
2535 if (face_index
!= -1) {
2536 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
2537 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
2539 if (fixed_pt_position_index
!= -1) {
2540 spi_ps_in_control_1
|= S_0286D0_FIXED_PT_POSITION_ENA(1) |
2541 S_0286D0_FIXED_PT_POSITION_ADDR(rshader
->input
[fixed_pt_position_index
].gpr
);
2544 /* HW bug in original R600 */
2545 if (rctx
->b
.family
== CHIP_R600
)
2548 r600_store_context_reg_seq(cb
, R_0286CC_SPI_PS_IN_CONTROL_0
, 2);
2549 r600_store_value(cb
, spi_ps_in_control_0
); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2550 r600_store_value(cb
, spi_ps_in_control_1
); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2552 r600_store_context_reg(cb
, R_0286D8_SPI_INPUT_Z
, spi_input_z
);
2554 r600_store_context_reg_seq(cb
, R_028850_SQ_PGM_RESOURCES_PS
, 2);
2555 r600_store_value(cb
, /* R_028850_SQ_PGM_RESOURCES_PS*/
2556 S_028850_NUM_GPRS(rshader
->bc
.ngpr
) |
2557 S_028850_STACK_SIZE(rshader
->bc
.nstack
) |
2558 S_028850_UNCACHED_FIRST_INST(ufi
));
2559 r600_store_value(cb
, exports_ps
); /* R_028854_SQ_PGM_EXPORTS_PS */
2561 r600_store_context_reg(cb
, R_028840_SQ_PGM_START_PS
, 0);
2562 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2564 /* only set some bits here, the other bits are set in the dsa state */
2565 shader
->db_shader_control
= db_shader_control
;
2566 shader
->ps_depth_export
= z_export
| stencil_export
| mask_export
;
2568 shader
->sprite_coord_enable
= sprite_coord_enable
;
2569 if (rctx
->rasterizer
)
2570 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
2573 void r600_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2575 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2576 struct r600_shader
*rshader
= &shader
->shader
;
2577 unsigned spi_vs_out_id
[10] = {};
2578 unsigned i
, tmp
, nparams
= 0;
2580 for (i
= 0; i
< rshader
->noutput
; i
++) {
2581 if (rshader
->output
[i
].spi_sid
) {
2582 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
2583 spi_vs_out_id
[nparams
/ 4] |= tmp
;
2588 r600_init_command_buffer(cb
, 32);
2590 r600_store_context_reg_seq(cb
, R_028614_SPI_VS_OUT_ID_0
, 10);
2591 for (i
= 0; i
< 10; i
++) {
2592 r600_store_value(cb
, spi_vs_out_id
[i
]);
2595 /* Certain attributes (position, psize, etc.) don't count as params.
2596 * VS is required to export at least one param and r600_shader_from_tgsi()
2597 * takes care of adding a dummy export.
2602 r600_store_context_reg(cb
, R_0286C4_SPI_VS_OUT_CONFIG
,
2603 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
2604 r600_store_context_reg(cb
, R_028868_SQ_PGM_RESOURCES_VS
,
2605 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
2606 S_028868_STACK_SIZE(rshader
->bc
.nstack
));
2607 if (rshader
->vs_position_window_space
) {
2608 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
,
2609 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
2611 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
,
2612 S_028818_VTX_W0_FMT(1) |
2613 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2614 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2615 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2618 r600_store_context_reg(cb
, R_028858_SQ_PGM_START_VS
, 0);
2619 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2621 shader
->pa_cl_vs_out_cntl
=
2622 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
2623 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
2624 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
2625 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
) |
2626 S_02881C_USE_VTX_EDGE_FLAG(rshader
->vs_out_edgeflag
) |
2627 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader
->vs_out_layer
) |
2628 S_02881C_USE_VTX_VIEWPORT_INDX(rshader
->vs_out_viewport
);
2631 #define RV610_GSVS_ALIGN 32
2632 #define R600_GSVS_ALIGN 16
2634 void r600_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2636 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2637 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2638 struct r600_shader
*rshader
= &shader
->shader
;
2639 struct r600_shader
*cp_shader
= &shader
->gs_copy_shader
->shader
;
2640 unsigned gsvs_itemsize
=
2641 (cp_shader
->ring_item_sizes
[0] * shader
->selector
->gs_max_out_vertices
) >> 2;
2643 /* some r600s needs gsvs itemsize aligned to cacheline size
2644 this was fixed in rs780 and above. */
2645 switch (rctx
->b
.family
) {
2647 gsvs_itemsize
= align(gsvs_itemsize
, RV610_GSVS_ALIGN
);
2654 gsvs_itemsize
= align(gsvs_itemsize
, R600_GSVS_ALIGN
);
2660 r600_init_command_buffer(cb
, 64);
2662 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2663 r600_store_context_reg(cb
, R_028AB8_VGT_VTX_CNT_EN
, 1);
2665 if (rctx
->b
.chip_class
>= R700
) {
2666 r600_store_context_reg(cb
, R_028B38_VGT_GS_MAX_VERT_OUT
,
2667 S_028B38_MAX_VERT_OUT(shader
->selector
->gs_max_out_vertices
));
2669 r600_store_context_reg(cb
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
,
2670 r600_conv_prim_to_gs_out(shader
->selector
->gs_output_prim
));
2672 r600_store_context_reg(cb
, R_0288C8_SQ_GS_VERT_ITEMSIZE
,
2673 cp_shader
->ring_item_sizes
[0] >> 2);
2675 r600_store_context_reg(cb
, R_0288A8_SQ_ESGS_RING_ITEMSIZE
,
2676 (rshader
->ring_item_sizes
[0]) >> 2);
2678 r600_store_context_reg(cb
, R_0288AC_SQ_GSVS_RING_ITEMSIZE
,
2681 /* FIXME calculate these values somehow ??? */
2682 r600_store_config_reg_seq(cb
, R_0088C8_VGT_GS_PER_ES
, 2);
2683 r600_store_value(cb
, 0x80); /* GS_PER_ES */
2684 r600_store_value(cb
, 0x100); /* ES_PER_GS */
2685 r600_store_config_reg_seq(cb
, R_0088E8_VGT_GS_PER_VS
, 1);
2686 r600_store_value(cb
, 0x2); /* GS_PER_VS */
2688 r600_store_context_reg(cb
, R_02887C_SQ_PGM_RESOURCES_GS
,
2689 S_02887C_NUM_GPRS(rshader
->bc
.ngpr
) |
2690 S_02887C_STACK_SIZE(rshader
->bc
.nstack
));
2691 r600_store_context_reg(cb
, R_02886C_SQ_PGM_START_GS
, 0);
2692 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2695 void r600_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2697 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2698 struct r600_shader
*rshader
= &shader
->shader
;
2700 r600_init_command_buffer(cb
, 32);
2702 r600_store_context_reg(cb
, R_028890_SQ_PGM_RESOURCES_ES
,
2703 S_028890_NUM_GPRS(rshader
->bc
.ngpr
) |
2704 S_028890_STACK_SIZE(rshader
->bc
.nstack
));
2705 r600_store_context_reg(cb
, R_028880_SQ_PGM_START_ES
, 0);
2706 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2710 void *r600_create_resolve_blend(struct r600_context
*rctx
)
2712 struct pipe_blend_state blend
;
2715 memset(&blend
, 0, sizeof(blend
));
2716 blend
.independent_blend_enable
= true;
2717 for (i
= 0; i
< 2; i
++) {
2718 blend
.rt
[i
].colormask
= 0xf;
2719 blend
.rt
[i
].blend_enable
= 1;
2720 blend
.rt
[i
].rgb_func
= PIPE_BLEND_ADD
;
2721 blend
.rt
[i
].alpha_func
= PIPE_BLEND_ADD
;
2722 blend
.rt
[i
].rgb_src_factor
= PIPE_BLENDFACTOR_ZERO
;
2723 blend
.rt
[i
].rgb_dst_factor
= PIPE_BLENDFACTOR_ZERO
;
2724 blend
.rt
[i
].alpha_src_factor
= PIPE_BLENDFACTOR_ZERO
;
2725 blend
.rt
[i
].alpha_dst_factor
= PIPE_BLENDFACTOR_ZERO
;
2727 return r600_create_blend_state_mode(&rctx
->b
.b
, &blend
, V_028808_SPECIAL_RESOLVE_BOX
);
2730 void *r700_create_resolve_blend(struct r600_context
*rctx
)
2732 struct pipe_blend_state blend
;
2734 memset(&blend
, 0, sizeof(blend
));
2735 blend
.independent_blend_enable
= true;
2736 blend
.rt
[0].colormask
= 0xf;
2737 return r600_create_blend_state_mode(&rctx
->b
.b
, &blend
, V_028808_SPECIAL_RESOLVE_BOX
);
2740 void *r600_create_decompress_blend(struct r600_context
*rctx
)
2742 struct pipe_blend_state blend
;
2744 memset(&blend
, 0, sizeof(blend
));
2745 blend
.independent_blend_enable
= true;
2746 blend
.rt
[0].colormask
= 0xf;
2747 return r600_create_blend_state_mode(&rctx
->b
.b
, &blend
, V_028808_SPECIAL_EXPAND_SAMPLES
);
2750 void *r600_create_db_flush_dsa(struct r600_context
*rctx
)
2752 struct pipe_depth_stencil_alpha_state dsa
;
2753 boolean quirk
= false;
2755 if (rctx
->b
.family
== CHIP_RV610
|| rctx
->b
.family
== CHIP_RV630
||
2756 rctx
->b
.family
== CHIP_RV620
|| rctx
->b
.family
== CHIP_RV635
)
2759 memset(&dsa
, 0, sizeof(dsa
));
2762 dsa
.depth
.enabled
= 1;
2763 dsa
.depth
.func
= PIPE_FUNC_LEQUAL
;
2764 dsa
.stencil
[0].enabled
= 1;
2765 dsa
.stencil
[0].func
= PIPE_FUNC_ALWAYS
;
2766 dsa
.stencil
[0].zpass_op
= PIPE_STENCIL_OP_KEEP
;
2767 dsa
.stencil
[0].zfail_op
= PIPE_STENCIL_OP_INCR
;
2768 dsa
.stencil
[0].writemask
= 0xff;
2771 return rctx
->b
.b
.create_depth_stencil_alpha_state(&rctx
->b
.b
, &dsa
);
2774 void r600_update_db_shader_control(struct r600_context
* rctx
)
2777 unsigned db_shader_control
;
2778 uint8_t ps_conservative_z
;
2780 if (!rctx
->ps_shader
) {
2784 dual_export
= rctx
->framebuffer
.export_16bpc
&&
2785 !rctx
->ps_shader
->current
->ps_depth_export
;
2787 db_shader_control
= rctx
->ps_shader
->current
->db_shader_control
|
2788 S_02880C_DUAL_EXPORT_ENABLE(dual_export
);
2790 ps_conservative_z
= rctx
->ps_shader
->current
->shader
.ps_conservative_z
;
2792 /* When alpha test is enabled we can't trust the hw to make the proper
2793 * decision on the order in which ztest should be run related to fragment
2796 * If alpha test is enabled perform z test after fragment. RE_Z (early
2797 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2799 if (rctx
->alphatest_state
.sx_alpha_test_control
) {
2800 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
2802 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2805 if (db_shader_control
!= rctx
->db_misc_state
.db_shader_control
||
2806 ps_conservative_z
!= rctx
->db_misc_state
.ps_conservative_z
) {
2807 rctx
->db_misc_state
.db_shader_control
= db_shader_control
;
2808 rctx
->db_misc_state
.ps_conservative_z
= ps_conservative_z
;
2809 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
2813 static inline unsigned r600_array_mode(unsigned mode
)
2817 case RADEON_SURF_MODE_LINEAR_ALIGNED
: return V_0280A0_ARRAY_LINEAR_ALIGNED
;
2819 case RADEON_SURF_MODE_1D
: return V_0280A0_ARRAY_1D_TILED_THIN1
;
2821 case RADEON_SURF_MODE_2D
: return V_0280A0_ARRAY_2D_TILED_THIN1
;
2825 static boolean
r600_dma_copy_tile(struct r600_context
*rctx
,
2826 struct pipe_resource
*dst
,
2831 struct pipe_resource
*src
,
2836 unsigned copy_height
,
2840 struct radeon_winsys_cs
*cs
= rctx
->b
.dma
.cs
;
2841 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
2842 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
2843 unsigned array_mode
, lbpp
, pitch_tile_max
, slice_tile_max
, size
;
2844 unsigned ncopy
, height
, cheight
, detile
, i
, x
, y
, z
, src_mode
, dst_mode
;
2845 uint64_t base
, addr
;
2847 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
2848 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
2849 assert(dst_mode
!= src_mode
);
2852 lbpp
= util_logbase2(bpp
);
2853 pitch_tile_max
= ((pitch
/ bpp
) / 8) - 1;
2855 if (dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
) {
2857 array_mode
= r600_array_mode(src_mode
);
2858 slice_tile_max
= (rsrc
->surface
.level
[src_level
].nblk_x
* rsrc
->surface
.level
[src_level
].nblk_y
) / (8*8);
2859 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
2860 /* linear height must be the same as the slice tile max height, it's ok even
2861 * if the linear destination/source have smaller heigh as the size of the
2862 * dma packet will be using the copy_height which is always smaller or equal
2863 * to the linear height
2865 height
= rsrc
->surface
.level
[src_level
].npix_y
;
2870 base
= rsrc
->surface
.level
[src_level
].offset
;
2871 addr
= rdst
->surface
.level
[dst_level
].offset
;
2872 addr
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
2873 addr
+= dst_y
* pitch
+ dst_x
* bpp
;
2876 array_mode
= r600_array_mode(dst_mode
);
2877 slice_tile_max
= (rdst
->surface
.level
[dst_level
].nblk_x
* rdst
->surface
.level
[dst_level
].nblk_y
) / (8*8);
2878 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
2879 /* linear height must be the same as the slice tile max height, it's ok even
2880 * if the linear destination/source have smaller heigh as the size of the
2881 * dma packet will be using the copy_height which is always smaller or equal
2882 * to the linear height
2884 height
= rdst
->surface
.level
[dst_level
].npix_y
;
2889 base
= rdst
->surface
.level
[dst_level
].offset
;
2890 addr
= rsrc
->surface
.level
[src_level
].offset
;
2891 addr
+= rsrc
->surface
.level
[src_level
].slice_size
* src_z
;
2892 addr
+= src_y
* pitch
+ src_x
* bpp
;
2894 /* check that we are in dw/base alignment constraint */
2895 if (addr
% 4 || base
% 256) {
2899 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2900 * line in the blit. Compute max 8 line we can copy in the size limit
2902 cheight
= ((R600_DMA_COPY_MAX_SIZE_DW
* 4) / pitch
) & 0xfffffff8;
2903 ncopy
= (copy_height
/ cheight
) + !!(copy_height
% cheight
);
2904 r600_need_dma_space(&rctx
->b
, ncopy
* 7, &rdst
->resource
, &rsrc
->resource
);
2906 for (i
= 0; i
< ncopy
; i
++) {
2907 cheight
= cheight
> copy_height
? copy_height
: cheight
;
2908 size
= (cheight
* pitch
) / 4;
2909 /* emit reloc before writing cs so that cs is always in consistent state */
2910 radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.dma
, &rsrc
->resource
, RADEON_USAGE_READ
,
2911 RADEON_PRIO_SDMA_TEXTURE
);
2912 radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.dma
, &rdst
->resource
, RADEON_USAGE_WRITE
,
2913 RADEON_PRIO_SDMA_TEXTURE
);
2914 radeon_emit(cs
, DMA_PACKET(DMA_PACKET_COPY
, 1, 0, size
));
2915 radeon_emit(cs
, base
>> 8);
2916 radeon_emit(cs
, (detile
<< 31) | (array_mode
<< 27) |
2917 (lbpp
<< 24) | ((height
- 1) << 10) |
2919 radeon_emit(cs
, (slice_tile_max
<< 12) | (z
<< 0));
2920 radeon_emit(cs
, (x
<< 3) | (y
<< 17));
2921 radeon_emit(cs
, addr
& 0xfffffffc);
2922 radeon_emit(cs
, (addr
>> 32UL) & 0xff);
2923 copy_height
-= cheight
;
2924 addr
+= cheight
* pitch
;
2927 r600_dma_emit_wait_idle(&rctx
->b
);
2931 static void r600_dma_copy(struct pipe_context
*ctx
,
2932 struct pipe_resource
*dst
,
2934 unsigned dstx
, unsigned dsty
, unsigned dstz
,
2935 struct pipe_resource
*src
,
2937 const struct pipe_box
*src_box
)
2939 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2940 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
2941 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
2942 unsigned dst_pitch
, src_pitch
, bpp
, dst_mode
, src_mode
, copy_height
;
2943 unsigned src_w
, dst_w
;
2944 unsigned src_x
, src_y
;
2945 unsigned dst_x
= dstx
, dst_y
= dsty
, dst_z
= dstz
;
2947 if (rctx
->b
.dma
.cs
== NULL
) {
2951 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
2952 if (dst_x
% 4 || src_box
->x
% 4 || src_box
->width
% 4)
2955 r600_dma_copy_buffer(rctx
, dst
, src
, dst_x
, src_box
->x
, src_box
->width
);
2959 if (src_box
->depth
> 1 ||
2960 !r600_prepare_for_dma_blit(&rctx
->b
, rdst
, dst_level
, dstx
, dsty
,
2961 dstz
, rsrc
, src_level
, src_box
))
2964 src_x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
2965 dst_x
= util_format_get_nblocksx(src
->format
, dst_x
);
2966 src_y
= util_format_get_nblocksy(src
->format
, src_box
->y
);
2967 dst_y
= util_format_get_nblocksy(src
->format
, dst_y
);
2969 bpp
= rdst
->surface
.bpe
;
2970 dst_pitch
= rdst
->surface
.level
[dst_level
].pitch_bytes
;
2971 src_pitch
= rsrc
->surface
.level
[src_level
].pitch_bytes
;
2972 src_w
= rsrc
->surface
.level
[src_level
].npix_x
;
2973 dst_w
= rdst
->surface
.level
[dst_level
].npix_x
;
2974 copy_height
= src_box
->height
/ rsrc
->surface
.blk_h
;
2976 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
2977 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
2979 if (src_pitch
!= dst_pitch
|| src_box
->x
|| dst_x
|| src_w
!= dst_w
) {
2980 /* strict requirement on r6xx/r7xx */
2983 /* lot of constraint on alignment this should capture them all */
2984 if (src_pitch
% 8 || src_box
->y
% 8 || dst_y
% 8) {
2988 if (src_mode
== dst_mode
) {
2989 uint64_t dst_offset
, src_offset
, size
;
2991 /* simple dma blit would do NOTE code here assume :
2994 * dst_pitch == src_pitch
2996 src_offset
= rsrc
->surface
.level
[src_level
].offset
;
2997 src_offset
+= rsrc
->surface
.level
[src_level
].slice_size
* src_box
->z
;
2998 src_offset
+= src_y
* src_pitch
+ src_x
* bpp
;
2999 dst_offset
= rdst
->surface
.level
[dst_level
].offset
;
3000 dst_offset
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
3001 dst_offset
+= dst_y
* dst_pitch
+ dst_x
* bpp
;
3002 size
= src_box
->height
* src_pitch
;
3003 /* must be dw aligned */
3004 if (dst_offset
% 4 || src_offset
% 4 || size
% 4) {
3007 r600_dma_copy_buffer(rctx
, dst
, src
, dst_offset
, src_offset
, size
);
3009 if (!r600_dma_copy_tile(rctx
, dst
, dst_level
, dst_x
, dst_y
, dst_z
,
3010 src
, src_level
, src_x
, src_y
, src_box
->z
,
3011 copy_height
, dst_pitch
, bpp
)) {
3018 r600_resource_copy_region(ctx
, dst
, dst_level
, dstx
, dsty
, dstz
,
3019 src
, src_level
, src_box
);
3022 void r600_init_state_functions(struct r600_context
*rctx
)
3027 * To avoid GPU lockup registers must be emited in a specific order
3028 * (no kidding ...). The order below is important and have been
3029 * partialy infered from analyzing fglrx command stream.
3031 * Don't reorder atom without carefully checking the effect (GPU lockup
3032 * or piglit regression).
3036 r600_init_atom(rctx
, &rctx
->framebuffer
.atom
, id
++, r600_emit_framebuffer_state
, 0);
3039 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
].atom
, id
++, r600_emit_vs_constant_buffers
, 0);
3040 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
].atom
, id
++, r600_emit_gs_constant_buffers
, 0);
3041 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
].atom
, id
++, r600_emit_ps_constant_buffers
, 0);
3043 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3044 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
3046 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].states
.atom
, id
++, r600_emit_vs_sampler_states
, 0);
3047 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].states
.atom
, id
++, r600_emit_gs_sampler_states
, 0);
3048 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].states
.atom
, id
++, r600_emit_ps_sampler_states
, 0);
3050 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
.atom
, id
++, r600_emit_vs_sampler_views
, 0);
3051 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
.atom
, id
++, r600_emit_gs_sampler_views
, 0);
3052 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.atom
, id
++, r600_emit_ps_sampler_views
, 0);
3053 r600_init_atom(rctx
, &rctx
->vertex_buffer_state
.atom
, id
++, r600_emit_vertex_buffers
, 0);
3055 r600_init_atom(rctx
, &rctx
->vgt_state
.atom
, id
++, r600_emit_vgt_state
, 10);
3057 r600_init_atom(rctx
, &rctx
->seamless_cube_map
.atom
, id
++, r600_emit_seamless_cube_map
, 3);
3058 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, r600_emit_sample_mask
, 3);
3059 rctx
->sample_mask
.sample_mask
= ~0;
3061 r600_init_atom(rctx
, &rctx
->alphatest_state
.atom
, id
++, r600_emit_alphatest_state
, 6);
3062 r600_init_atom(rctx
, &rctx
->blend_color
.atom
, id
++, r600_emit_blend_color
, 6);
3063 r600_init_atom(rctx
, &rctx
->blend_state
.atom
, id
++, r600_emit_cso_state
, 0);
3064 r600_init_atom(rctx
, &rctx
->cb_misc_state
.atom
, id
++, r600_emit_cb_misc_state
, 7);
3065 r600_init_atom(rctx
, &rctx
->clip_misc_state
.atom
, id
++, r600_emit_clip_misc_state
, 6);
3066 r600_init_atom(rctx
, &rctx
->clip_state
.atom
, id
++, r600_emit_clip_state
, 26);
3067 r600_init_atom(rctx
, &rctx
->db_misc_state
.atom
, id
++, r600_emit_db_misc_state
, 7);
3068 r600_init_atom(rctx
, &rctx
->db_state
.atom
, id
++, r600_emit_db_state
, 11);
3069 r600_init_atom(rctx
, &rctx
->dsa_state
.atom
, id
++, r600_emit_cso_state
, 0);
3070 r600_init_atom(rctx
, &rctx
->poly_offset_state
.atom
, id
++, r600_emit_polygon_offset
, 9);
3071 r600_init_atom(rctx
, &rctx
->rasterizer_state
.atom
, id
++, r600_emit_cso_state
, 0);
3072 r600_add_atom(rctx
, &rctx
->b
.scissors
.atom
, id
++);
3073 r600_add_atom(rctx
, &rctx
->b
.viewports
.atom
, id
++);
3074 r600_init_atom(rctx
, &rctx
->config_state
.atom
, id
++, r600_emit_config_state
, 3);
3075 r600_init_atom(rctx
, &rctx
->stencil_ref
.atom
, id
++, r600_emit_stencil_ref
, 4);
3076 r600_init_atom(rctx
, &rctx
->vertex_fetch_shader
.atom
, id
++, r600_emit_vertex_fetch_shader
, 5);
3077 r600_add_atom(rctx
, &rctx
->b
.render_cond_atom
, id
++);
3078 r600_add_atom(rctx
, &rctx
->b
.streamout
.begin_atom
, id
++);
3079 r600_add_atom(rctx
, &rctx
->b
.streamout
.enable_atom
, id
++);
3080 for (i
= 0; i
< R600_NUM_HW_STAGES
; i
++)
3081 r600_init_atom(rctx
, &rctx
->hw_shader_stages
[i
].atom
, id
++, r600_emit_shader
, 0);
3082 r600_init_atom(rctx
, &rctx
->shader_stages
.atom
, id
++, r600_emit_shader_stages
, 0);
3083 r600_init_atom(rctx
, &rctx
->gs_rings
.atom
, id
++, r600_emit_gs_rings
, 0);
3085 rctx
->b
.b
.create_blend_state
= r600_create_blend_state
;
3086 rctx
->b
.b
.create_depth_stencil_alpha_state
= r600_create_dsa_state
;
3087 rctx
->b
.b
.create_rasterizer_state
= r600_create_rs_state
;
3088 rctx
->b
.b
.create_sampler_state
= r600_create_sampler_state
;
3089 rctx
->b
.b
.create_sampler_view
= r600_create_sampler_view
;
3090 rctx
->b
.b
.set_framebuffer_state
= r600_set_framebuffer_state
;
3091 rctx
->b
.b
.set_polygon_stipple
= r600_set_polygon_stipple
;
3092 rctx
->b
.b
.set_min_samples
= r600_set_min_samples
;
3093 rctx
->b
.b
.get_sample_position
= r600_get_sample_position
;
3094 rctx
->b
.dma_copy
= r600_dma_copy
;
3096 /* this function must be last */