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r600g: Properly update MULTIWRITE_ENABLE in r600_pipe_shader_ps().
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_double_list.h>
36 #include <util/u_pack_color.h>
37 #include <util/u_memory.h>
38 #include <util/u_inlines.h>
39 #include <util/u_framebuffer.h>
40 #include "util/u_transfer.h"
41 #include <pipebuffer/pb_buffer.h>
42 #include "r600.h"
43 #include "r600d.h"
44 #include "r600_resource.h"
45 #include "r600_shader.h"
46 #include "r600_pipe.h"
47 #include "r600_state_inlines.h"
48
49 void r600_polygon_offset_update(struct r600_pipe_context *rctx)
50 {
51 struct r600_pipe_state state;
52
53 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
54 state.nregs = 0;
55 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
56 float offset_units = rctx->rasterizer->offset_units;
57 unsigned offset_db_fmt_cntl = 0, depth;
58
59 switch (rctx->framebuffer.zsbuf->texture->format) {
60 case PIPE_FORMAT_Z24X8_UNORM:
61 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
62 depth = -24;
63 offset_units *= 2.0f;
64 break;
65 case PIPE_FORMAT_Z32_FLOAT:
66 depth = -23;
67 offset_units *= 1.0f;
68 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
69 break;
70 case PIPE_FORMAT_Z16_UNORM:
71 depth = -16;
72 offset_units *= 4.0f;
73 break;
74 default:
75 return;
76 }
77 /* FIXME some of those reg can be computed with cso */
78 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
79 r600_pipe_state_add_reg(&state,
80 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
81 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
82 r600_pipe_state_add_reg(&state,
83 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
84 fui(offset_units), 0xFFFFFFFF, NULL);
85 r600_pipe_state_add_reg(&state,
86 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
87 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
88 r600_pipe_state_add_reg(&state,
89 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
90 fui(offset_units), 0xFFFFFFFF, NULL);
91 r600_pipe_state_add_reg(&state,
92 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
93 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
94 r600_context_pipe_state_set(&rctx->ctx, &state);
95 }
96 }
97
98 static void r600_set_blend_color(struct pipe_context *ctx,
99 const struct pipe_blend_color *state)
100 {
101 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
102 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
103
104 if (rstate == NULL)
105 return;
106
107 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
108 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
109 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
110 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
111 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
112 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
113 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
114 r600_context_pipe_state_set(&rctx->ctx, rstate);
115 }
116
117 static void *r600_create_blend_state(struct pipe_context *ctx,
118 const struct pipe_blend_state *state)
119 {
120 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
121 struct r600_pipe_state *rstate;
122 u32 color_control, target_mask;
123
124 if (blend == NULL) {
125 return NULL;
126 }
127 rstate = &blend->rstate;
128
129 rstate->id = R600_PIPE_STATE_BLEND;
130
131 target_mask = 0;
132 color_control = S_028808_PER_MRT_BLEND(1);
133 if (state->logicop_enable) {
134 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
135 } else {
136 color_control |= (0xcc << 16);
137 }
138 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
139 if (state->independent_blend_enable) {
140 for (int i = 0; i < 8; i++) {
141 if (state->rt[i].blend_enable) {
142 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
143 }
144 target_mask |= (state->rt[i].colormask << (4 * i));
145 }
146 } else {
147 for (int i = 0; i < 8; i++) {
148 if (state->rt[0].blend_enable) {
149 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
150 }
151 target_mask |= (state->rt[0].colormask << (4 * i));
152 }
153 }
154 blend->cb_target_mask = target_mask;
155 /* MULTIWRITE_ENABLE is controlled by r600_pipe_shader_ps(). */
156 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
157 color_control, 0xFFFFFFFD, NULL);
158
159 for (int i = 0; i < 8; i++) {
160 unsigned eqRGB = state->rt[i].rgb_func;
161 unsigned srcRGB = state->rt[i].rgb_src_factor;
162 unsigned dstRGB = state->rt[i].rgb_dst_factor;
163
164 unsigned eqA = state->rt[i].alpha_func;
165 unsigned srcA = state->rt[i].alpha_src_factor;
166 unsigned dstA = state->rt[i].alpha_dst_factor;
167 uint32_t bc = 0;
168
169 if (!state->rt[i].blend_enable)
170 continue;
171
172 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
173 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
174 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
175
176 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
177 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
178 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
179 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
180 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
181 }
182
183 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
184 if (i == 0) {
185 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
186 }
187 }
188 return rstate;
189 }
190
191 static void *r600_create_dsa_state(struct pipe_context *ctx,
192 const struct pipe_depth_stencil_alpha_state *state)
193 {
194 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
195 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
196 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
197
198 if (rstate == NULL) {
199 return NULL;
200 }
201
202 rstate->id = R600_PIPE_STATE_DSA;
203 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
204 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
205 stencil_ref_mask = 0;
206 stencil_ref_mask_bf = 0;
207 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
208 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
209 S_028800_ZFUNC(state->depth.func);
210
211 /* stencil */
212 if (state->stencil[0].enabled) {
213 db_depth_control |= S_028800_STENCIL_ENABLE(1);
214 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
215 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
216 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
217 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
218
219
220 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
221 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
222 if (state->stencil[1].enabled) {
223 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
224 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
225 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
226 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
227 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
228 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
229 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
230 }
231 }
232
233 /* alpha */
234 alpha_test_control = 0;
235 alpha_ref = 0;
236 if (state->alpha.enabled) {
237 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
238 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
239 alpha_ref = fui(state->alpha.ref_value);
240 }
241
242 /* misc */
243 db_render_control = 0;
244 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
245 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
246 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
247 /* TODO db_render_override depends on query */
248 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
249 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
250 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
251 r600_pipe_state_add_reg(rstate,
252 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
253 0xFFFFFFFF & C_028430_STENCILREF, NULL);
254 r600_pipe_state_add_reg(rstate,
255 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
256 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
257 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
258 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
259 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
260 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
261 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
262 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
263 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
264 * r600_pipe_shader_ps().*/
265 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL);
266 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
267 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
268 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
269 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
270 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
271
272 return rstate;
273 }
274
275 static void *r600_create_rs_state(struct pipe_context *ctx,
276 const struct pipe_rasterizer_state *state)
277 {
278 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
279 struct r600_pipe_state *rstate;
280 unsigned tmp;
281 unsigned prov_vtx = 1, polygon_dual_mode;
282 unsigned clip_rule;
283
284 if (rs == NULL) {
285 return NULL;
286 }
287
288 rstate = &rs->rstate;
289 rs->flatshade = state->flatshade;
290 rs->sprite_coord_enable = state->sprite_coord_enable;
291
292 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
293 /* offset */
294 rs->offset_units = state->offset_units;
295 rs->offset_scale = state->offset_scale * 12.0f;
296
297 rstate->id = R600_PIPE_STATE_RASTERIZER;
298 if (state->flatshade_first)
299 prov_vtx = 0;
300 tmp = S_0286D4_FLAT_SHADE_ENA(1);
301 if (state->sprite_coord_enable) {
302 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
303 S_0286D4_PNT_SPRITE_OVRD_X(2) |
304 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
305 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
306 S_0286D4_PNT_SPRITE_OVRD_W(1);
307 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
308 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
309 }
310 }
311 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
312
313 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
314 state->fill_back != PIPE_POLYGON_MODE_FILL);
315 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
316 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
317 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
318 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
319 S_028814_FACE(!state->front_ccw) |
320 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
321 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
322 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
323 S_028814_POLY_MODE(polygon_dual_mode) |
324 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
325 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
326 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
327 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
328 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
329 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
330 /* point size 12.4 fixed point */
331 tmp = (unsigned)(state->point_size * 8.0);
332 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
333 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
334
335 tmp = (unsigned)state->line_width * 8;
336 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
337
338 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
339 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
340 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
341
342 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
343 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
344 0xFFFFFFFF, NULL);
345
346 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
347 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
348 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
349 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
350 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
351 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
352
353 return rstate;
354 }
355
356 static void *r600_create_sampler_state(struct pipe_context *ctx,
357 const struct pipe_sampler_state *state)
358 {
359 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
360 union util_color uc;
361 uint32_t coord_trunc = 0;
362
363 if (rstate == NULL) {
364 return NULL;
365 }
366
367 if ((state->mag_img_filter == PIPE_TEX_FILTER_NEAREST) ||
368 (state->min_img_filter == PIPE_TEX_FILTER_NEAREST))
369 coord_trunc = 1;
370
371 rstate->id = R600_PIPE_STATE_SAMPLER;
372 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
373 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
374 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
375 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
376 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
377 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
378 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
379 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
380 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
381 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
382 /* FIXME LOD it depends on texture base level ... */
383 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
384 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
385 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
386 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
387 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
388 S_03C008_MC_COORD_TRUNCATE(coord_trunc) |
389 S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
390 if (uc.ui) {
391 r600_pipe_state_add_reg(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
392 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
393 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
394 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
395 }
396 return rstate;
397 }
398
399 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
400 struct pipe_resource *texture,
401 const struct pipe_sampler_view *state)
402 {
403 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
404 struct r600_pipe_state *rstate;
405 const struct util_format_description *desc;
406 struct r600_resource_texture *tmp;
407 struct r600_resource *rbuffer;
408 unsigned format;
409 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
410 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
411 struct r600_bo *bo[2];
412 unsigned height, depth;
413
414 if (resource == NULL)
415 return NULL;
416 rstate = &resource->state;
417
418 /* initialize base object */
419 resource->base = *state;
420 resource->base.texture = NULL;
421 pipe_reference(NULL, &texture->reference);
422 resource->base.texture = texture;
423 resource->base.reference.count = 1;
424 resource->base.context = ctx;
425
426 swizzle[0] = state->swizzle_r;
427 swizzle[1] = state->swizzle_g;
428 swizzle[2] = state->swizzle_b;
429 swizzle[3] = state->swizzle_a;
430 format = r600_translate_texformat(ctx->screen, state->format,
431 swizzle,
432 &word4, &yuv_format);
433 if (format == ~0) {
434 format = 0;
435 }
436 desc = util_format_description(state->format);
437 if (desc == NULL) {
438 R600_ERR("unknow format %d\n", state->format);
439 }
440 tmp = (struct r600_resource_texture *)texture;
441 if (tmp->depth && !tmp->is_flushing_texture) {
442 r600_texture_depth_flush(ctx, texture, TRUE);
443 tmp = tmp->flushed_depth_texture;
444 }
445
446 if (tmp->force_int_type) {
447 word4 &= C_038010_NUM_FORMAT_ALL;
448 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
449 }
450 rbuffer = &tmp->resource;
451 bo[0] = rbuffer->bo;
452 bo[1] = rbuffer->bo;
453 pitch = align(tmp->pitch_in_blocks[0] * util_format_get_blockwidth(state->format), 8);
454 array_mode = tmp->array_mode[0];
455 tile_type = tmp->tile_type;
456
457 height = texture->height0;
458 depth = texture->depth0;
459 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
460 height = 1;
461 depth = texture->array_size;
462 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
463 depth = texture->array_size;
464 }
465
466 /* FIXME properly handle first level != 0 */
467 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
468 S_038000_DIM(r600_tex_dim(texture->target)) |
469 S_038000_TILE_MODE(array_mode) |
470 S_038000_TILE_TYPE(tile_type) |
471 S_038000_PITCH((pitch / 8) - 1) |
472 S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
473 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
474 S_038004_TEX_HEIGHT(height - 1) |
475 S_038004_TEX_DEPTH(depth - 1) |
476 S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
477 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
478 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
479 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
480 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
481 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
482 word4 |
483 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_NO_ZERO) |
484 S_038010_REQUEST_SIZE(1) |
485 S_038010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
486 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
487 S_038014_LAST_LEVEL(state->u.tex.last_level) |
488 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
489 S_038014_LAST_ARRAY(state->u.tex.last_layer), 0xFFFFFFFF, NULL);
490 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
491 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
492
493 return &resource->base;
494 }
495
496 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
497 struct pipe_sampler_view **views)
498 {
499 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
500 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
501
502 for (int i = 0; i < count; i++) {
503 if (resource[i]) {
504 r600_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
505 i + R600_MAX_CONST_BUFFERS);
506 }
507 }
508 }
509
510 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
511 struct pipe_sampler_view **views)
512 {
513 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
514 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
515 int i;
516
517 for (i = 0; i < count; i++) {
518 if (&rctx->ps_samplers.views[i]->base != views[i]) {
519 if (resource[i])
520 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
521 i + R600_MAX_CONST_BUFFERS);
522 else
523 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
524 i + R600_MAX_CONST_BUFFERS);
525
526 pipe_sampler_view_reference(
527 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
528 views[i]);
529
530 }
531 }
532 for (i = count; i < NUM_TEX_UNITS; i++) {
533 if (rctx->ps_samplers.views[i]) {
534 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
535 i + R600_MAX_CONST_BUFFERS);
536 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
537 }
538 }
539 rctx->ps_samplers.n_views = count;
540 }
541
542 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
543 {
544 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
545 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
546
547 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
548 rctx->ps_samplers.n_samplers = count;
549
550 for (int i = 0; i < count; i++) {
551 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
552 }
553 }
554
555 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
556 {
557 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
558 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
559
560 for (int i = 0; i < count; i++) {
561 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
562 }
563 }
564
565 static void r600_set_clip_state(struct pipe_context *ctx,
566 const struct pipe_clip_state *state)
567 {
568 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
569 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
570
571 if (rstate == NULL)
572 return;
573
574 rctx->clip = *state;
575 rstate->id = R600_PIPE_STATE_CLIP;
576 for (int i = 0; i < state->nr; i++) {
577 r600_pipe_state_add_reg(rstate,
578 R_028E20_PA_CL_UCP0_X + i * 16,
579 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
580 r600_pipe_state_add_reg(rstate,
581 R_028E24_PA_CL_UCP0_Y + i * 16,
582 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
583 r600_pipe_state_add_reg(rstate,
584 R_028E28_PA_CL_UCP0_Z + i * 16,
585 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
586 r600_pipe_state_add_reg(rstate,
587 R_028E2C_PA_CL_UCP0_W + i * 16,
588 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
589 }
590 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
591 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
592 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
593 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
594
595 free(rctx->states[R600_PIPE_STATE_CLIP]);
596 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
597 r600_context_pipe_state_set(&rctx->ctx, rstate);
598 }
599
600 static void r600_set_polygon_stipple(struct pipe_context *ctx,
601 const struct pipe_poly_stipple *state)
602 {
603 }
604
605 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
606 {
607 }
608
609 static void r600_set_scissor_state(struct pipe_context *ctx,
610 const struct pipe_scissor_state *state)
611 {
612 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
613 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
614 u32 tl, br;
615
616 if (rstate == NULL)
617 return;
618
619 rstate->id = R600_PIPE_STATE_SCISSOR;
620 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
621 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
622 r600_pipe_state_add_reg(rstate,
623 R_028210_PA_SC_CLIPRECT_0_TL, tl,
624 0xFFFFFFFF, NULL);
625 r600_pipe_state_add_reg(rstate,
626 R_028214_PA_SC_CLIPRECT_0_BR, br,
627 0xFFFFFFFF, NULL);
628 r600_pipe_state_add_reg(rstate,
629 R_028218_PA_SC_CLIPRECT_1_TL, tl,
630 0xFFFFFFFF, NULL);
631 r600_pipe_state_add_reg(rstate,
632 R_02821C_PA_SC_CLIPRECT_1_BR, br,
633 0xFFFFFFFF, NULL);
634 r600_pipe_state_add_reg(rstate,
635 R_028220_PA_SC_CLIPRECT_2_TL, tl,
636 0xFFFFFFFF, NULL);
637 r600_pipe_state_add_reg(rstate,
638 R_028224_PA_SC_CLIPRECT_2_BR, br,
639 0xFFFFFFFF, NULL);
640 r600_pipe_state_add_reg(rstate,
641 R_028228_PA_SC_CLIPRECT_3_TL, tl,
642 0xFFFFFFFF, NULL);
643 r600_pipe_state_add_reg(rstate,
644 R_02822C_PA_SC_CLIPRECT_3_BR, br,
645 0xFFFFFFFF, NULL);
646
647 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
648 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
649 r600_context_pipe_state_set(&rctx->ctx, rstate);
650 }
651
652 static void r600_set_stencil_ref(struct pipe_context *ctx,
653 const struct pipe_stencil_ref *state)
654 {
655 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
656 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
657 u32 tmp;
658
659 if (rstate == NULL)
660 return;
661
662 rctx->stencil_ref = *state;
663 rstate->id = R600_PIPE_STATE_STENCIL_REF;
664 tmp = S_028430_STENCILREF(state->ref_value[0]);
665 r600_pipe_state_add_reg(rstate,
666 R_028430_DB_STENCILREFMASK, tmp,
667 ~C_028430_STENCILREF, NULL);
668 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
669 r600_pipe_state_add_reg(rstate,
670 R_028434_DB_STENCILREFMASK_BF, tmp,
671 ~C_028434_STENCILREF_BF, NULL);
672
673 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
674 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
675 r600_context_pipe_state_set(&rctx->ctx, rstate);
676 }
677
678 static void r600_set_viewport_state(struct pipe_context *ctx,
679 const struct pipe_viewport_state *state)
680 {
681 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
682 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
683
684 if (rstate == NULL)
685 return;
686
687 rctx->viewport = *state;
688 rstate->id = R600_PIPE_STATE_VIEWPORT;
689 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
690 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
691 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
692 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
693 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
694 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
695 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
696 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
697 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
698
699 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
700 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
701 r600_context_pipe_state_set(&rctx->ctx, rstate);
702 }
703
704 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
705 const struct pipe_framebuffer_state *state, int cb)
706 {
707 struct r600_resource_texture *rtex;
708 struct r600_resource *rbuffer;
709 struct r600_surface *surf;
710 unsigned level = state->cbufs[cb]->u.tex.level;
711 unsigned pitch, slice;
712 unsigned color_info;
713 unsigned format, swap, ntype;
714 unsigned offset;
715 const struct util_format_description *desc;
716 struct r600_bo *bo[3];
717 int i;
718
719 surf = (struct r600_surface *)state->cbufs[cb];
720 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
721
722 if (rtex->depth && !rtex->is_flushing_texture) {
723 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
724 rtex = rtex->flushed_depth_texture;
725 }
726
727 rbuffer = &rtex->resource;
728 bo[0] = rbuffer->bo;
729 bo[1] = rbuffer->bo;
730 bo[2] = rbuffer->bo;
731
732 /* XXX quite sure for dx10+ hw don't need any offset hacks */
733 offset = r600_texture_get_offset(rtex,
734 level, state->cbufs[cb]->u.tex.first_layer);
735 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
736 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
737 ntype = 0;
738 desc = util_format_description(surf->base.format);
739 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
740 ntype = V_0280A0_NUMBER_SRGB;
741
742 for (i = 0; i < 4; i++) {
743 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
744 break;
745 }
746 }
747
748 format = r600_translate_colorformat(surf->base.format);
749 swap = r600_translate_colorswap(surf->base.format);
750
751 /* disable when gallium grows int textures */
752 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
753 ntype = 4;
754
755 color_info = S_0280A0_FORMAT(format) |
756 S_0280A0_COMP_SWAP(swap) |
757 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
758 S_0280A0_BLEND_CLAMP(1) |
759 S_0280A0_NUMBER_TYPE(ntype);
760
761 /* on R600 this can't be set if BLEND_CLAMP isn't set,
762 if BLEND_FLOAT32 is set of > 11 bits in a UNORM or SNORM */
763 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
764 desc->channel[i].size < 12)
765 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
766
767 r600_pipe_state_add_reg(rstate,
768 R_028040_CB_COLOR0_BASE + cb * 4,
769 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
770 r600_pipe_state_add_reg(rstate,
771 R_0280A0_CB_COLOR0_INFO + cb * 4,
772 color_info, 0xFFFFFFFF, bo[0]);
773 r600_pipe_state_add_reg(rstate,
774 R_028060_CB_COLOR0_SIZE + cb * 4,
775 S_028060_PITCH_TILE_MAX(pitch) |
776 S_028060_SLICE_TILE_MAX(slice),
777 0xFFFFFFFF, NULL);
778 r600_pipe_state_add_reg(rstate,
779 R_028080_CB_COLOR0_VIEW + cb * 4,
780 0x00000000, 0xFFFFFFFF, NULL);
781 r600_pipe_state_add_reg(rstate,
782 R_0280E0_CB_COLOR0_FRAG + cb * 4,
783 r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]);
784 r600_pipe_state_add_reg(rstate,
785 R_0280C0_CB_COLOR0_TILE + cb * 4,
786 r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]);
787 r600_pipe_state_add_reg(rstate,
788 R_028100_CB_COLOR0_MASK + cb * 4,
789 0x00000000, 0xFFFFFFFF, NULL);
790 }
791
792 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
793 const struct pipe_framebuffer_state *state)
794 {
795 struct r600_resource_texture *rtex;
796 struct r600_resource *rbuffer;
797 struct r600_surface *surf;
798 unsigned level;
799 unsigned pitch, slice, format;
800 unsigned offset;
801
802 if (state->zsbuf == NULL)
803 return;
804
805 level = state->zsbuf->u.tex.level;
806
807 surf = (struct r600_surface *)state->zsbuf;
808 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
809
810 rbuffer = &rtex->resource;
811
812 /* XXX quite sure for dx10+ hw don't need any offset hacks */
813 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
814 level, state->zsbuf->u.tex.first_layer);
815 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
816 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
817 format = r600_translate_dbformat(state->zsbuf->texture->format);
818
819 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
820 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
821 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
822 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
823 0xFFFFFFFF, NULL);
824 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
825 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
826 S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format),
827 0xFFFFFFFF, rbuffer->bo);
828 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
829 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL);
830 }
831
832 static void r600_set_framebuffer_state(struct pipe_context *ctx,
833 const struct pipe_framebuffer_state *state)
834 {
835 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
836 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
837 u32 shader_mask, tl, br, shader_control, target_mask;
838
839 if (rstate == NULL)
840 return;
841
842 /* unreference old buffer and reference new one */
843 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
844
845 util_copy_framebuffer_state(&rctx->framebuffer, state);
846
847 /* build states */
848 for (int i = 0; i < state->nr_cbufs; i++) {
849 r600_cb(rctx, rstate, state, i);
850 }
851 if (state->zsbuf) {
852 r600_db(rctx, rstate, state);
853 }
854
855 target_mask = 0x00000000;
856 target_mask = 0xFFFFFFFF;
857 shader_mask = 0;
858 shader_control = 0;
859 for (int i = 0; i < state->nr_cbufs; i++) {
860 target_mask ^= 0xf << (i * 4);
861 shader_mask |= 0xf << (i * 4);
862 shader_control |= 1 << i;
863 }
864 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
865 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
866
867 r600_pipe_state_add_reg(rstate,
868 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
869 0xFFFFFFFF, NULL);
870 r600_pipe_state_add_reg(rstate,
871 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
872 0xFFFFFFFF, NULL);
873 r600_pipe_state_add_reg(rstate,
874 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
875 0xFFFFFFFF, NULL);
876 r600_pipe_state_add_reg(rstate,
877 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
878 0xFFFFFFFF, NULL);
879 r600_pipe_state_add_reg(rstate,
880 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
881 0xFFFFFFFF, NULL);
882 r600_pipe_state_add_reg(rstate,
883 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
884 0xFFFFFFFF, NULL);
885 r600_pipe_state_add_reg(rstate,
886 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
887 0xFFFFFFFF, NULL);
888 r600_pipe_state_add_reg(rstate,
889 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
890 0xFFFFFFFF, NULL);
891 r600_pipe_state_add_reg(rstate,
892 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
893 0xFFFFFFFF, NULL);
894 if (rctx->family >= CHIP_RV770) {
895 r600_pipe_state_add_reg(rstate,
896 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
897 0xFFFFFFFF, NULL);
898 }
899
900 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
901 shader_control, 0xFFFFFFFF, NULL);
902 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
903 0x00000000, target_mask, NULL);
904 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
905 shader_mask, 0xFFFFFFFF, NULL);
906 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
907 0x00000000, 0xFFFFFFFF, NULL);
908 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
909 0x00000000, 0xFFFFFFFF, NULL);
910 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
911 0x00000000, 0xFFFFFFFF, NULL);
912 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
913 0x01000000, 0xFFFFFFFF, NULL);
914 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
915 0x00000000, 0xFFFFFFFF, NULL);
916 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
917 0x000000FF, 0xFFFFFFFF, NULL);
918 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
919 0xFFFFFFFF, 0xFFFFFFFF, NULL);
920 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
921 0xFFFFFFFF, 0xFFFFFFFF, NULL);
922
923 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
924 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
925 r600_context_pipe_state_set(&rctx->ctx, rstate);
926
927 if (state->zsbuf) {
928 r600_polygon_offset_update(rctx);
929 }
930 }
931
932 void r600_init_state_functions(struct r600_pipe_context *rctx)
933 {
934 rctx->context.create_blend_state = r600_create_blend_state;
935 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
936 rctx->context.create_fs_state = r600_create_shader_state;
937 rctx->context.create_rasterizer_state = r600_create_rs_state;
938 rctx->context.create_sampler_state = r600_create_sampler_state;
939 rctx->context.create_sampler_view = r600_create_sampler_view;
940 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
941 rctx->context.create_vs_state = r600_create_shader_state;
942 rctx->context.bind_blend_state = r600_bind_blend_state;
943 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
944 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
945 rctx->context.bind_fs_state = r600_bind_ps_shader;
946 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
947 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
948 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
949 rctx->context.bind_vs_state = r600_bind_vs_shader;
950 rctx->context.delete_blend_state = r600_delete_state;
951 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
952 rctx->context.delete_fs_state = r600_delete_ps_shader;
953 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
954 rctx->context.delete_sampler_state = r600_delete_state;
955 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
956 rctx->context.delete_vs_state = r600_delete_vs_shader;
957 rctx->context.set_blend_color = r600_set_blend_color;
958 rctx->context.set_clip_state = r600_set_clip_state;
959 rctx->context.set_constant_buffer = r600_set_constant_buffer;
960 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
961 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
962 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
963 rctx->context.set_sample_mask = r600_set_sample_mask;
964 rctx->context.set_scissor_state = r600_set_scissor_state;
965 rctx->context.set_stencil_ref = r600_set_stencil_ref;
966 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
967 rctx->context.set_index_buffer = r600_set_index_buffer;
968 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
969 rctx->context.set_viewport_state = r600_set_viewport_state;
970 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
971 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
972 }
973
974 void r600_init_config(struct r600_pipe_context *rctx)
975 {
976 int ps_prio;
977 int vs_prio;
978 int gs_prio;
979 int es_prio;
980 int num_ps_gprs;
981 int num_vs_gprs;
982 int num_gs_gprs;
983 int num_es_gprs;
984 int num_temp_gprs;
985 int num_ps_threads;
986 int num_vs_threads;
987 int num_gs_threads;
988 int num_es_threads;
989 int num_ps_stack_entries;
990 int num_vs_stack_entries;
991 int num_gs_stack_entries;
992 int num_es_stack_entries;
993 enum radeon_family family;
994 struct r600_pipe_state *rstate = &rctx->config;
995 u32 tmp;
996
997 family = r600_get_family(rctx->radeon);
998 ps_prio = 0;
999 vs_prio = 1;
1000 gs_prio = 2;
1001 es_prio = 3;
1002 switch (family) {
1003 case CHIP_R600:
1004 num_ps_gprs = 192;
1005 num_vs_gprs = 56;
1006 num_temp_gprs = 4;
1007 num_gs_gprs = 0;
1008 num_es_gprs = 0;
1009 num_ps_threads = 136;
1010 num_vs_threads = 48;
1011 num_gs_threads = 4;
1012 num_es_threads = 4;
1013 num_ps_stack_entries = 128;
1014 num_vs_stack_entries = 128;
1015 num_gs_stack_entries = 0;
1016 num_es_stack_entries = 0;
1017 break;
1018 case CHIP_RV630:
1019 case CHIP_RV635:
1020 num_ps_gprs = 84;
1021 num_vs_gprs = 36;
1022 num_temp_gprs = 4;
1023 num_gs_gprs = 0;
1024 num_es_gprs = 0;
1025 num_ps_threads = 144;
1026 num_vs_threads = 40;
1027 num_gs_threads = 4;
1028 num_es_threads = 4;
1029 num_ps_stack_entries = 40;
1030 num_vs_stack_entries = 40;
1031 num_gs_stack_entries = 32;
1032 num_es_stack_entries = 16;
1033 break;
1034 case CHIP_RV610:
1035 case CHIP_RV620:
1036 case CHIP_RS780:
1037 case CHIP_RS880:
1038 default:
1039 num_ps_gprs = 84;
1040 num_vs_gprs = 36;
1041 num_temp_gprs = 4;
1042 num_gs_gprs = 0;
1043 num_es_gprs = 0;
1044 num_ps_threads = 136;
1045 num_vs_threads = 48;
1046 num_gs_threads = 4;
1047 num_es_threads = 4;
1048 num_ps_stack_entries = 40;
1049 num_vs_stack_entries = 40;
1050 num_gs_stack_entries = 32;
1051 num_es_stack_entries = 16;
1052 break;
1053 case CHIP_RV670:
1054 num_ps_gprs = 144;
1055 num_vs_gprs = 40;
1056 num_temp_gprs = 4;
1057 num_gs_gprs = 0;
1058 num_es_gprs = 0;
1059 num_ps_threads = 136;
1060 num_vs_threads = 48;
1061 num_gs_threads = 4;
1062 num_es_threads = 4;
1063 num_ps_stack_entries = 40;
1064 num_vs_stack_entries = 40;
1065 num_gs_stack_entries = 32;
1066 num_es_stack_entries = 16;
1067 break;
1068 case CHIP_RV770:
1069 num_ps_gprs = 192;
1070 num_vs_gprs = 56;
1071 num_temp_gprs = 4;
1072 num_gs_gprs = 0;
1073 num_es_gprs = 0;
1074 num_ps_threads = 188;
1075 num_vs_threads = 60;
1076 num_gs_threads = 0;
1077 num_es_threads = 0;
1078 num_ps_stack_entries = 256;
1079 num_vs_stack_entries = 256;
1080 num_gs_stack_entries = 0;
1081 num_es_stack_entries = 0;
1082 break;
1083 case CHIP_RV730:
1084 case CHIP_RV740:
1085 num_ps_gprs = 84;
1086 num_vs_gprs = 36;
1087 num_temp_gprs = 4;
1088 num_gs_gprs = 0;
1089 num_es_gprs = 0;
1090 num_ps_threads = 188;
1091 num_vs_threads = 60;
1092 num_gs_threads = 0;
1093 num_es_threads = 0;
1094 num_ps_stack_entries = 128;
1095 num_vs_stack_entries = 128;
1096 num_gs_stack_entries = 0;
1097 num_es_stack_entries = 0;
1098 break;
1099 case CHIP_RV710:
1100 num_ps_gprs = 192;
1101 num_vs_gprs = 56;
1102 num_temp_gprs = 4;
1103 num_gs_gprs = 0;
1104 num_es_gprs = 0;
1105 num_ps_threads = 144;
1106 num_vs_threads = 48;
1107 num_gs_threads = 0;
1108 num_es_threads = 0;
1109 num_ps_stack_entries = 128;
1110 num_vs_stack_entries = 128;
1111 num_gs_stack_entries = 0;
1112 num_es_stack_entries = 0;
1113 break;
1114 }
1115
1116 rstate->id = R600_PIPE_STATE_CONFIG;
1117
1118 /* SQ_CONFIG */
1119 tmp = 0;
1120 switch (family) {
1121 case CHIP_RV610:
1122 case CHIP_RV620:
1123 case CHIP_RS780:
1124 case CHIP_RS880:
1125 case CHIP_RV710:
1126 break;
1127 default:
1128 tmp |= S_008C00_VC_ENABLE(1);
1129 break;
1130 }
1131 tmp |= S_008C00_DX9_CONSTS(0);
1132 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1133 tmp |= S_008C00_PS_PRIO(ps_prio);
1134 tmp |= S_008C00_VS_PRIO(vs_prio);
1135 tmp |= S_008C00_GS_PRIO(gs_prio);
1136 tmp |= S_008C00_ES_PRIO(es_prio);
1137 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1138
1139 /* SQ_GPR_RESOURCE_MGMT_1 */
1140 tmp = 0;
1141 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1142 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1143 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1144 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1145
1146 /* SQ_GPR_RESOURCE_MGMT_2 */
1147 tmp = 0;
1148 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1149 tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
1150 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1151
1152 /* SQ_THREAD_RESOURCE_MGMT */
1153 tmp = 0;
1154 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1155 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1156 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1157 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1158 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1159
1160 /* SQ_STACK_RESOURCE_MGMT_1 */
1161 tmp = 0;
1162 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1163 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1164 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1165
1166 /* SQ_STACK_RESOURCE_MGMT_2 */
1167 tmp = 0;
1168 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1169 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1170 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1171
1172 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1173 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1174
1175 if (family >= CHIP_RV770) {
1176 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1177 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
1178 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1179 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1180 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1181 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL);
1182 } else {
1183 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1184 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
1185 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1186 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1187 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1188 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL);
1189 }
1190 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1191 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1192 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1193 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1194 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1195 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1196 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1197 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1198 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1199 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1200 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1201 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1202 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1203 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
1204 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
1205 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1206 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1207 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1208 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1209 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1210 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1211 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
1212 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1213 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1214 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1215 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
1216
1217 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1218 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
1219 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
1220 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
1221 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
1222 r600_context_pipe_state_set(&rctx->ctx, rstate);
1223 }
1224
1225 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1226 {
1227 struct r600_pipe_state *rstate = &shader->rstate;
1228 struct r600_shader *rshader = &shader->shader;
1229 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
1230 int pos_index = -1, face_index = -1;
1231
1232 rstate->nregs = 0;
1233
1234 for (i = 0; i < rshader->ninput; i++) {
1235 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1236 pos_index = i;
1237 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1238 face_index = i;
1239 }
1240
1241 db_shader_control = 0;
1242 for (i = 0; i < rshader->noutput; i++) {
1243 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1244 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1245 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1246 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1);
1247 }
1248 if (rshader->uses_kill)
1249 db_shader_control |= S_02880C_KILL_ENABLE(1);
1250
1251 exports_ps = 0;
1252 num_cout = 0;
1253 for (i = 0; i < rshader->noutput; i++) {
1254 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1255 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1256 exports_ps |= 1;
1257 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1258 num_cout++;
1259 }
1260 }
1261 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
1262 if (!exports_ps) {
1263 /* always at least export 1 component per pixel */
1264 exports_ps = 2;
1265 }
1266
1267 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
1268 S_0286CC_PERSP_GRADIENT_ENA(1);
1269 spi_input_z = 0;
1270 if (pos_index != -1) {
1271 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
1272 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
1273 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
1274 S_0286CC_BARYC_SAMPLE_CNTL(1));
1275 spi_input_z |= 1;
1276 }
1277
1278 spi_ps_in_control_1 = 0;
1279 if (face_index != -1) {
1280 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
1281 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
1282 }
1283
1284 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1285 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL);
1286 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1287 r600_pipe_state_add_reg(rstate,
1288 R_028840_SQ_PGM_START_PS,
1289 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
1290 r600_pipe_state_add_reg(rstate,
1291 R_028850_SQ_PGM_RESOURCES_PS,
1292 S_028868_NUM_GPRS(rshader->bc.ngpr) |
1293 S_028868_STACK_SIZE(rshader->bc.nstack),
1294 0xFFFFFFFF, NULL);
1295 r600_pipe_state_add_reg(rstate,
1296 R_028854_SQ_PGM_EXPORTS_PS,
1297 exports_ps, 0xFFFFFFFF, NULL);
1298 r600_pipe_state_add_reg(rstate,
1299 R_0288CC_SQ_PGM_CF_OFFSET_PS,
1300 0x00000000, 0xFFFFFFFF, NULL);
1301 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
1302 S_028808_MULTIWRITE_ENABLE(!!rshader->fs_write_all),
1303 S_028808_MULTIWRITE_ENABLE(1),
1304 NULL);
1305 /* only set some bits here, the other bits are set in the dsa state */
1306 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
1307 db_shader_control,
1308 S_02880C_Z_EXPORT_ENABLE(1) |
1309 S_02880C_STENCIL_REF_EXPORT_ENABLE(1) |
1310 S_02880C_KILL_ENABLE(1),
1311 NULL);
1312
1313 r600_pipe_state_add_reg(rstate,
1314 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
1315 0xFFFFFFFF, NULL);
1316 }
1317
1318 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1319 {
1320 struct r600_pipe_state *rstate = &shader->rstate;
1321 struct r600_shader *rshader = &shader->shader;
1322 unsigned spi_vs_out_id[10];
1323 unsigned i, tmp;
1324
1325 /* clear previous register */
1326 rstate->nregs = 0;
1327
1328 /* so far never got proper semantic id from tgsi */
1329 /* FIXME better to move this in config things so they get emited
1330 * only one time per cs
1331 */
1332 for (i = 0; i < 10; i++) {
1333 spi_vs_out_id[i] = 0;
1334 }
1335 for (i = 0; i < 32; i++) {
1336 tmp = i << ((i & 3) * 8);
1337 spi_vs_out_id[i / 4] |= tmp;
1338 }
1339 for (i = 0; i < 10; i++) {
1340 r600_pipe_state_add_reg(rstate,
1341 R_028614_SPI_VS_OUT_ID_0 + i * 4,
1342 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1343 }
1344
1345 r600_pipe_state_add_reg(rstate,
1346 R_0286C4_SPI_VS_OUT_CONFIG,
1347 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1348 0xFFFFFFFF, NULL);
1349 r600_pipe_state_add_reg(rstate,
1350 R_028868_SQ_PGM_RESOURCES_VS,
1351 S_028868_NUM_GPRS(rshader->bc.ngpr) |
1352 S_028868_STACK_SIZE(rshader->bc.nstack),
1353 0xFFFFFFFF, NULL);
1354 r600_pipe_state_add_reg(rstate,
1355 R_0288D0_SQ_PGM_CF_OFFSET_VS,
1356 0x00000000, 0xFFFFFFFF, NULL);
1357 r600_pipe_state_add_reg(rstate,
1358 R_028858_SQ_PGM_START_VS,
1359 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
1360
1361 r600_pipe_state_add_reg(rstate,
1362 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
1363 0xFFFFFFFF, NULL);
1364 }
1365
1366 void r600_fetch_shader(struct r600_vertex_element *ve)
1367 {
1368 struct r600_pipe_state *rstate;
1369
1370 rstate = &ve->rstate;
1371 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1372 rstate->nregs = 0;
1373 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
1374 0x00000000, 0xFFFFFFFF, NULL);
1375 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
1376 0x00000000, 0xFFFFFFFF, NULL);
1377 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
1378 r600_bo_offset(ve->fetch_shader) >> 8,
1379 0xFFFFFFFF, ve->fetch_shader);
1380 }
1381
1382 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
1383 {
1384 struct pipe_depth_stencil_alpha_state dsa;
1385 struct r600_pipe_state *rstate;
1386 boolean quirk = false;
1387
1388 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
1389 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
1390 quirk = true;
1391
1392 memset(&dsa, 0, sizeof(dsa));
1393
1394 if (quirk) {
1395 dsa.depth.enabled = 1;
1396 dsa.depth.func = PIPE_FUNC_LEQUAL;
1397 dsa.stencil[0].enabled = 1;
1398 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
1399 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
1400 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
1401 dsa.stencil[0].writemask = 0xff;
1402 }
1403
1404 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1405 r600_pipe_state_add_reg(rstate,
1406 R_02880C_DB_SHADER_CONTROL,
1407 0x0,
1408 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1409 r600_pipe_state_add_reg(rstate,
1410 R_028D0C_DB_RENDER_CONTROL,
1411 S_028D0C_DEPTH_COPY_ENABLE(1) |
1412 S_028D0C_STENCIL_COPY_ENABLE(1) |
1413 S_028D0C_COPY_CENTROID(1),
1414 S_028D0C_DEPTH_COPY_ENABLE(1) |
1415 S_028D0C_STENCIL_COPY_ENABLE(1) |
1416 S_028D0C_COPY_CENTROID(1), NULL);
1417 return rstate;
1418 }
1419
1420 void r600_pipe_set_buffer_resource(struct r600_pipe_context *rctx,
1421 struct r600_pipe_state *rstate,
1422 struct r600_resource *rbuffer,
1423 unsigned offset, unsigned stride)
1424 {
1425 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
1426 offset, 0xFFFFFFFF, rbuffer->bo);
1427 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
1428 rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
1429 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
1430 S_038008_STRIDE(stride),
1431 0xFFFFFFFF, NULL);
1432 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
1433 0x00000000, 0xFFFFFFFF, NULL);
1434 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
1435 0x00000000, 0xFFFFFFFF, NULL);
1436 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
1437 0x00000000, 0xFFFFFFFF, NULL);
1438 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
1439 0xC0000000, 0xFFFFFFFF, NULL);
1440 }