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r600g: convert the remnants of VGT state into immediate register writes/atoms v4
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600d.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31
32 static uint32_t r600_translate_blend_function(int blend_func)
33 {
34 switch (blend_func) {
35 case PIPE_BLEND_ADD:
36 return V_028804_COMB_DST_PLUS_SRC;
37 case PIPE_BLEND_SUBTRACT:
38 return V_028804_COMB_SRC_MINUS_DST;
39 case PIPE_BLEND_REVERSE_SUBTRACT:
40 return V_028804_COMB_DST_MINUS_SRC;
41 case PIPE_BLEND_MIN:
42 return V_028804_COMB_MIN_DST_SRC;
43 case PIPE_BLEND_MAX:
44 return V_028804_COMB_MAX_DST_SRC;
45 default:
46 R600_ERR("Unknown blend function %d\n", blend_func);
47 assert(0);
48 break;
49 }
50 return 0;
51 }
52
53 static uint32_t r600_translate_blend_factor(int blend_fact)
54 {
55 switch (blend_fact) {
56 case PIPE_BLENDFACTOR_ONE:
57 return V_028804_BLEND_ONE;
58 case PIPE_BLENDFACTOR_SRC_COLOR:
59 return V_028804_BLEND_SRC_COLOR;
60 case PIPE_BLENDFACTOR_SRC_ALPHA:
61 return V_028804_BLEND_SRC_ALPHA;
62 case PIPE_BLENDFACTOR_DST_ALPHA:
63 return V_028804_BLEND_DST_ALPHA;
64 case PIPE_BLENDFACTOR_DST_COLOR:
65 return V_028804_BLEND_DST_COLOR;
66 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
67 return V_028804_BLEND_SRC_ALPHA_SATURATE;
68 case PIPE_BLENDFACTOR_CONST_COLOR:
69 return V_028804_BLEND_CONST_COLOR;
70 case PIPE_BLENDFACTOR_CONST_ALPHA:
71 return V_028804_BLEND_CONST_ALPHA;
72 case PIPE_BLENDFACTOR_ZERO:
73 return V_028804_BLEND_ZERO;
74 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
75 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
76 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
77 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
78 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
79 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
80 case PIPE_BLENDFACTOR_INV_DST_COLOR:
81 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
82 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
83 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
84 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
85 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
86 case PIPE_BLENDFACTOR_SRC1_COLOR:
87 return V_028804_BLEND_SRC1_COLOR;
88 case PIPE_BLENDFACTOR_SRC1_ALPHA:
89 return V_028804_BLEND_SRC1_ALPHA;
90 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
91 return V_028804_BLEND_INV_SRC1_COLOR;
92 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
93 return V_028804_BLEND_INV_SRC1_ALPHA;
94 default:
95 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
96 assert(0);
97 break;
98 }
99 return 0;
100 }
101
102 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
103 {
104 switch (dim) {
105 default:
106 case PIPE_TEXTURE_1D:
107 return V_038000_SQ_TEX_DIM_1D;
108 case PIPE_TEXTURE_1D_ARRAY:
109 return V_038000_SQ_TEX_DIM_1D_ARRAY;
110 case PIPE_TEXTURE_2D:
111 case PIPE_TEXTURE_RECT:
112 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
113 V_038000_SQ_TEX_DIM_2D;
114 case PIPE_TEXTURE_2D_ARRAY:
115 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
116 V_038000_SQ_TEX_DIM_2D_ARRAY;
117 case PIPE_TEXTURE_3D:
118 return V_038000_SQ_TEX_DIM_3D;
119 case PIPE_TEXTURE_CUBE:
120 return V_038000_SQ_TEX_DIM_CUBEMAP;
121 }
122 }
123
124 static uint32_t r600_translate_dbformat(enum pipe_format format)
125 {
126 switch (format) {
127 case PIPE_FORMAT_Z16_UNORM:
128 return V_028010_DEPTH_16;
129 case PIPE_FORMAT_Z24X8_UNORM:
130 return V_028010_DEPTH_X8_24;
131 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
132 return V_028010_DEPTH_8_24;
133 case PIPE_FORMAT_Z32_FLOAT:
134 return V_028010_DEPTH_32_FLOAT;
135 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
136 return V_028010_DEPTH_X24_8_32_FLOAT;
137 default:
138 return ~0U;
139 }
140 }
141
142 static uint32_t r600_translate_colorswap(enum pipe_format format)
143 {
144 switch (format) {
145 /* 8-bit buffers. */
146 case PIPE_FORMAT_A8_UNORM:
147 case PIPE_FORMAT_A8_SNORM:
148 case PIPE_FORMAT_A8_UINT:
149 case PIPE_FORMAT_A8_SINT:
150 case PIPE_FORMAT_A16_UNORM:
151 case PIPE_FORMAT_A16_SNORM:
152 case PIPE_FORMAT_A16_UINT:
153 case PIPE_FORMAT_A16_SINT:
154 case PIPE_FORMAT_A16_FLOAT:
155 case PIPE_FORMAT_A32_UINT:
156 case PIPE_FORMAT_A32_SINT:
157 case PIPE_FORMAT_A32_FLOAT:
158 case PIPE_FORMAT_R4A4_UNORM:
159 return V_0280A0_SWAP_ALT_REV;
160 case PIPE_FORMAT_I8_UNORM:
161 case PIPE_FORMAT_I8_SNORM:
162 case PIPE_FORMAT_I8_UINT:
163 case PIPE_FORMAT_I8_SINT:
164 case PIPE_FORMAT_L8_UNORM:
165 case PIPE_FORMAT_L8_SNORM:
166 case PIPE_FORMAT_L8_UINT:
167 case PIPE_FORMAT_L8_SINT:
168 case PIPE_FORMAT_L8_SRGB:
169 case PIPE_FORMAT_L16_UNORM:
170 case PIPE_FORMAT_L16_SNORM:
171 case PIPE_FORMAT_L16_UINT:
172 case PIPE_FORMAT_L16_SINT:
173 case PIPE_FORMAT_L16_FLOAT:
174 case PIPE_FORMAT_L32_UINT:
175 case PIPE_FORMAT_L32_SINT:
176 case PIPE_FORMAT_L32_FLOAT:
177 case PIPE_FORMAT_I16_UNORM:
178 case PIPE_FORMAT_I16_SNORM:
179 case PIPE_FORMAT_I16_UINT:
180 case PIPE_FORMAT_I16_SINT:
181 case PIPE_FORMAT_I16_FLOAT:
182 case PIPE_FORMAT_I32_UINT:
183 case PIPE_FORMAT_I32_SINT:
184 case PIPE_FORMAT_I32_FLOAT:
185 case PIPE_FORMAT_R8_UNORM:
186 case PIPE_FORMAT_R8_SNORM:
187 case PIPE_FORMAT_R8_UINT:
188 case PIPE_FORMAT_R8_SINT:
189 return V_0280A0_SWAP_STD;
190
191 case PIPE_FORMAT_L4A4_UNORM:
192 case PIPE_FORMAT_A4R4_UNORM:
193 return V_0280A0_SWAP_ALT;
194
195 /* 16-bit buffers. */
196 case PIPE_FORMAT_B5G6R5_UNORM:
197 return V_0280A0_SWAP_STD_REV;
198
199 case PIPE_FORMAT_B5G5R5A1_UNORM:
200 case PIPE_FORMAT_B5G5R5X1_UNORM:
201 return V_0280A0_SWAP_ALT;
202
203 case PIPE_FORMAT_B4G4R4A4_UNORM:
204 case PIPE_FORMAT_B4G4R4X4_UNORM:
205 return V_0280A0_SWAP_ALT;
206
207 case PIPE_FORMAT_Z16_UNORM:
208 return V_0280A0_SWAP_STD;
209
210 case PIPE_FORMAT_L8A8_UNORM:
211 case PIPE_FORMAT_L8A8_SNORM:
212 case PIPE_FORMAT_L8A8_UINT:
213 case PIPE_FORMAT_L8A8_SINT:
214 case PIPE_FORMAT_L8A8_SRGB:
215 case PIPE_FORMAT_L16A16_UNORM:
216 case PIPE_FORMAT_L16A16_SNORM:
217 case PIPE_FORMAT_L16A16_UINT:
218 case PIPE_FORMAT_L16A16_SINT:
219 case PIPE_FORMAT_L16A16_FLOAT:
220 case PIPE_FORMAT_L32A32_UINT:
221 case PIPE_FORMAT_L32A32_SINT:
222 case PIPE_FORMAT_L32A32_FLOAT:
223 return V_0280A0_SWAP_ALT;
224 case PIPE_FORMAT_R8G8_UNORM:
225 case PIPE_FORMAT_R8G8_SNORM:
226 case PIPE_FORMAT_R8G8_UINT:
227 case PIPE_FORMAT_R8G8_SINT:
228 return V_0280A0_SWAP_STD;
229
230 case PIPE_FORMAT_R16_UNORM:
231 case PIPE_FORMAT_R16_SNORM:
232 case PIPE_FORMAT_R16_UINT:
233 case PIPE_FORMAT_R16_SINT:
234 case PIPE_FORMAT_R16_FLOAT:
235 return V_0280A0_SWAP_STD;
236
237 /* 32-bit buffers. */
238
239 case PIPE_FORMAT_A8B8G8R8_SRGB:
240 return V_0280A0_SWAP_STD_REV;
241 case PIPE_FORMAT_B8G8R8A8_SRGB:
242 return V_0280A0_SWAP_ALT;
243
244 case PIPE_FORMAT_B8G8R8A8_UNORM:
245 case PIPE_FORMAT_B8G8R8X8_UNORM:
246 return V_0280A0_SWAP_ALT;
247
248 case PIPE_FORMAT_A8R8G8B8_UNORM:
249 case PIPE_FORMAT_X8R8G8B8_UNORM:
250 return V_0280A0_SWAP_ALT_REV;
251 case PIPE_FORMAT_R8G8B8A8_SNORM:
252 case PIPE_FORMAT_R8G8B8A8_UNORM:
253 case PIPE_FORMAT_R8G8B8X8_UNORM:
254 case PIPE_FORMAT_R8G8B8A8_SINT:
255 case PIPE_FORMAT_R8G8B8A8_UINT:
256 return V_0280A0_SWAP_STD;
257
258 case PIPE_FORMAT_A8B8G8R8_UNORM:
259 case PIPE_FORMAT_X8B8G8R8_UNORM:
260 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
261 return V_0280A0_SWAP_STD_REV;
262
263 case PIPE_FORMAT_Z24X8_UNORM:
264 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
265 return V_0280A0_SWAP_STD;
266
267 case PIPE_FORMAT_X8Z24_UNORM:
268 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
269 return V_0280A0_SWAP_STD;
270
271 case PIPE_FORMAT_R10G10B10A2_UNORM:
272 case PIPE_FORMAT_R10G10B10X2_SNORM:
273 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
274 return V_0280A0_SWAP_STD;
275
276 case PIPE_FORMAT_B10G10R10A2_UNORM:
277 case PIPE_FORMAT_B10G10R10A2_UINT:
278 return V_0280A0_SWAP_ALT;
279
280 case PIPE_FORMAT_R11G11B10_FLOAT:
281 case PIPE_FORMAT_R16G16_UNORM:
282 case PIPE_FORMAT_R16G16_SNORM:
283 case PIPE_FORMAT_R16G16_FLOAT:
284 case PIPE_FORMAT_R16G16_UINT:
285 case PIPE_FORMAT_R16G16_SINT:
286 case PIPE_FORMAT_R32_UINT:
287 case PIPE_FORMAT_R32_SINT:
288 case PIPE_FORMAT_R32_FLOAT:
289 case PIPE_FORMAT_Z32_FLOAT:
290 return V_0280A0_SWAP_STD;
291
292 /* 64-bit buffers. */
293 case PIPE_FORMAT_R32G32_FLOAT:
294 case PIPE_FORMAT_R32G32_UINT:
295 case PIPE_FORMAT_R32G32_SINT:
296 case PIPE_FORMAT_R16G16B16A16_UNORM:
297 case PIPE_FORMAT_R16G16B16A16_SNORM:
298 case PIPE_FORMAT_R16G16B16A16_UINT:
299 case PIPE_FORMAT_R16G16B16A16_SINT:
300 case PIPE_FORMAT_R16G16B16A16_FLOAT:
301 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
302
303 /* 128-bit buffers. */
304 case PIPE_FORMAT_R32G32B32A32_FLOAT:
305 case PIPE_FORMAT_R32G32B32A32_SNORM:
306 case PIPE_FORMAT_R32G32B32A32_UNORM:
307 case PIPE_FORMAT_R32G32B32A32_SINT:
308 case PIPE_FORMAT_R32G32B32A32_UINT:
309 return V_0280A0_SWAP_STD;
310 default:
311 R600_ERR("unsupported colorswap format %d\n", format);
312 return ~0U;
313 }
314 return ~0U;
315 }
316
317 static uint32_t r600_translate_colorformat(enum pipe_format format)
318 {
319 switch (format) {
320 case PIPE_FORMAT_L4A4_UNORM:
321 case PIPE_FORMAT_R4A4_UNORM:
322 case PIPE_FORMAT_A4R4_UNORM:
323 return V_0280A0_COLOR_4_4;
324
325 /* 8-bit buffers. */
326 case PIPE_FORMAT_A8_UNORM:
327 case PIPE_FORMAT_A8_SNORM:
328 case PIPE_FORMAT_A8_UINT:
329 case PIPE_FORMAT_A8_SINT:
330 case PIPE_FORMAT_I8_UNORM:
331 case PIPE_FORMAT_I8_SNORM:
332 case PIPE_FORMAT_I8_UINT:
333 case PIPE_FORMAT_I8_SINT:
334 case PIPE_FORMAT_L8_UNORM:
335 case PIPE_FORMAT_L8_SNORM:
336 case PIPE_FORMAT_L8_UINT:
337 case PIPE_FORMAT_L8_SINT:
338 case PIPE_FORMAT_L8_SRGB:
339 case PIPE_FORMAT_R8_UNORM:
340 case PIPE_FORMAT_R8_SNORM:
341 case PIPE_FORMAT_R8_UINT:
342 case PIPE_FORMAT_R8_SINT:
343 return V_0280A0_COLOR_8;
344
345 /* 16-bit buffers. */
346 case PIPE_FORMAT_B5G6R5_UNORM:
347 return V_0280A0_COLOR_5_6_5;
348
349 case PIPE_FORMAT_B5G5R5A1_UNORM:
350 case PIPE_FORMAT_B5G5R5X1_UNORM:
351 return V_0280A0_COLOR_1_5_5_5;
352
353 case PIPE_FORMAT_B4G4R4A4_UNORM:
354 case PIPE_FORMAT_B4G4R4X4_UNORM:
355 return V_0280A0_COLOR_4_4_4_4;
356
357 case PIPE_FORMAT_Z16_UNORM:
358 return V_0280A0_COLOR_16;
359
360 case PIPE_FORMAT_L8A8_UNORM:
361 case PIPE_FORMAT_L8A8_SNORM:
362 case PIPE_FORMAT_L8A8_UINT:
363 case PIPE_FORMAT_L8A8_SINT:
364 case PIPE_FORMAT_L8A8_SRGB:
365 case PIPE_FORMAT_R8G8_UNORM:
366 case PIPE_FORMAT_R8G8_SNORM:
367 case PIPE_FORMAT_R8G8_UINT:
368 case PIPE_FORMAT_R8G8_SINT:
369 return V_0280A0_COLOR_8_8;
370
371 case PIPE_FORMAT_R16_UNORM:
372 case PIPE_FORMAT_R16_SNORM:
373 case PIPE_FORMAT_R16_UINT:
374 case PIPE_FORMAT_R16_SINT:
375 case PIPE_FORMAT_A16_UNORM:
376 case PIPE_FORMAT_A16_SNORM:
377 case PIPE_FORMAT_A16_UINT:
378 case PIPE_FORMAT_A16_SINT:
379 case PIPE_FORMAT_L16_UNORM:
380 case PIPE_FORMAT_L16_SNORM:
381 case PIPE_FORMAT_L16_UINT:
382 case PIPE_FORMAT_L16_SINT:
383 case PIPE_FORMAT_I16_UNORM:
384 case PIPE_FORMAT_I16_SNORM:
385 case PIPE_FORMAT_I16_UINT:
386 case PIPE_FORMAT_I16_SINT:
387 return V_0280A0_COLOR_16;
388
389 case PIPE_FORMAT_R16_FLOAT:
390 case PIPE_FORMAT_A16_FLOAT:
391 case PIPE_FORMAT_L16_FLOAT:
392 case PIPE_FORMAT_I16_FLOAT:
393 return V_0280A0_COLOR_16_FLOAT;
394
395 /* 32-bit buffers. */
396 case PIPE_FORMAT_A8B8G8R8_SRGB:
397 case PIPE_FORMAT_A8B8G8R8_UNORM:
398 case PIPE_FORMAT_A8R8G8B8_UNORM:
399 case PIPE_FORMAT_B8G8R8A8_SRGB:
400 case PIPE_FORMAT_B8G8R8A8_UNORM:
401 case PIPE_FORMAT_B8G8R8X8_UNORM:
402 case PIPE_FORMAT_R8G8B8A8_SNORM:
403 case PIPE_FORMAT_R8G8B8A8_UNORM:
404 case PIPE_FORMAT_R8G8B8X8_UNORM:
405 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
406 case PIPE_FORMAT_X8B8G8R8_UNORM:
407 case PIPE_FORMAT_X8R8G8B8_UNORM:
408 case PIPE_FORMAT_R8G8B8A8_SINT:
409 case PIPE_FORMAT_R8G8B8A8_UINT:
410 return V_0280A0_COLOR_8_8_8_8;
411
412 case PIPE_FORMAT_R10G10B10A2_UNORM:
413 case PIPE_FORMAT_R10G10B10X2_SNORM:
414 case PIPE_FORMAT_B10G10R10A2_UNORM:
415 case PIPE_FORMAT_B10G10R10A2_UINT:
416 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
417 return V_0280A0_COLOR_2_10_10_10;
418
419 case PIPE_FORMAT_Z24X8_UNORM:
420 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
421 return V_0280A0_COLOR_8_24;
422
423 case PIPE_FORMAT_X8Z24_UNORM:
424 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
425 return V_0280A0_COLOR_24_8;
426
427 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
428 return V_0280A0_COLOR_X24_8_32_FLOAT;
429
430 case PIPE_FORMAT_R32_UINT:
431 case PIPE_FORMAT_R32_SINT:
432 case PIPE_FORMAT_A32_UINT:
433 case PIPE_FORMAT_A32_SINT:
434 case PIPE_FORMAT_L32_UINT:
435 case PIPE_FORMAT_L32_SINT:
436 case PIPE_FORMAT_I32_UINT:
437 case PIPE_FORMAT_I32_SINT:
438 return V_0280A0_COLOR_32;
439
440 case PIPE_FORMAT_R32_FLOAT:
441 case PIPE_FORMAT_A32_FLOAT:
442 case PIPE_FORMAT_L32_FLOAT:
443 case PIPE_FORMAT_I32_FLOAT:
444 case PIPE_FORMAT_Z32_FLOAT:
445 return V_0280A0_COLOR_32_FLOAT;
446
447 case PIPE_FORMAT_R16G16_FLOAT:
448 case PIPE_FORMAT_L16A16_FLOAT:
449 return V_0280A0_COLOR_16_16_FLOAT;
450
451 case PIPE_FORMAT_R16G16_UNORM:
452 case PIPE_FORMAT_R16G16_SNORM:
453 case PIPE_FORMAT_R16G16_UINT:
454 case PIPE_FORMAT_R16G16_SINT:
455 case PIPE_FORMAT_L16A16_UNORM:
456 case PIPE_FORMAT_L16A16_SNORM:
457 case PIPE_FORMAT_L16A16_UINT:
458 case PIPE_FORMAT_L16A16_SINT:
459 return V_0280A0_COLOR_16_16;
460
461 case PIPE_FORMAT_R11G11B10_FLOAT:
462 return V_0280A0_COLOR_10_11_11_FLOAT;
463
464 /* 64-bit buffers. */
465 case PIPE_FORMAT_R16G16B16A16_UINT:
466 case PIPE_FORMAT_R16G16B16A16_SINT:
467 case PIPE_FORMAT_R16G16B16A16_UNORM:
468 case PIPE_FORMAT_R16G16B16A16_SNORM:
469 return V_0280A0_COLOR_16_16_16_16;
470
471 case PIPE_FORMAT_R16G16B16A16_FLOAT:
472 return V_0280A0_COLOR_16_16_16_16_FLOAT;
473
474 case PIPE_FORMAT_R32G32_FLOAT:
475 case PIPE_FORMAT_L32A32_FLOAT:
476 return V_0280A0_COLOR_32_32_FLOAT;
477
478 case PIPE_FORMAT_R32G32_SINT:
479 case PIPE_FORMAT_R32G32_UINT:
480 case PIPE_FORMAT_L32A32_UINT:
481 case PIPE_FORMAT_L32A32_SINT:
482 return V_0280A0_COLOR_32_32;
483
484 /* 128-bit buffers. */
485 case PIPE_FORMAT_R32G32B32A32_FLOAT:
486 return V_0280A0_COLOR_32_32_32_32_FLOAT;
487 case PIPE_FORMAT_R32G32B32A32_SNORM:
488 case PIPE_FORMAT_R32G32B32A32_UNORM:
489 case PIPE_FORMAT_R32G32B32A32_SINT:
490 case PIPE_FORMAT_R32G32B32A32_UINT:
491 return V_0280A0_COLOR_32_32_32_32;
492
493 /* YUV buffers. */
494 case PIPE_FORMAT_UYVY:
495 case PIPE_FORMAT_YUYV:
496 default:
497 return ~0U; /* Unsupported. */
498 }
499 }
500
501 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
502 {
503 if (R600_BIG_ENDIAN) {
504 switch(colorformat) {
505 case V_0280A0_COLOR_4_4:
506 return ENDIAN_NONE;
507
508 /* 8-bit buffers. */
509 case V_0280A0_COLOR_8:
510 return ENDIAN_NONE;
511
512 /* 16-bit buffers. */
513 case V_0280A0_COLOR_5_6_5:
514 case V_0280A0_COLOR_1_5_5_5:
515 case V_0280A0_COLOR_4_4_4_4:
516 case V_0280A0_COLOR_16:
517 case V_0280A0_COLOR_8_8:
518 return ENDIAN_8IN16;
519
520 /* 32-bit buffers. */
521 case V_0280A0_COLOR_8_8_8_8:
522 case V_0280A0_COLOR_2_10_10_10:
523 case V_0280A0_COLOR_8_24:
524 case V_0280A0_COLOR_24_8:
525 case V_0280A0_COLOR_32_FLOAT:
526 case V_0280A0_COLOR_16_16_FLOAT:
527 case V_0280A0_COLOR_16_16:
528 return ENDIAN_8IN32;
529
530 /* 64-bit buffers. */
531 case V_0280A0_COLOR_16_16_16_16:
532 case V_0280A0_COLOR_16_16_16_16_FLOAT:
533 return ENDIAN_8IN16;
534
535 case V_0280A0_COLOR_32_32_FLOAT:
536 case V_0280A0_COLOR_32_32:
537 case V_0280A0_COLOR_X24_8_32_FLOAT:
538 return ENDIAN_8IN32;
539
540 /* 128-bit buffers. */
541 case V_0280A0_COLOR_32_32_32_FLOAT:
542 case V_0280A0_COLOR_32_32_32_32_FLOAT:
543 case V_0280A0_COLOR_32_32_32_32:
544 return ENDIAN_8IN32;
545 default:
546 return ENDIAN_NONE; /* Unsupported. */
547 }
548 } else {
549 return ENDIAN_NONE;
550 }
551 }
552
553 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
554 {
555 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
556 }
557
558 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
559 {
560 return r600_translate_colorformat(format) != ~0U &&
561 r600_translate_colorswap(format) != ~0U;
562 }
563
564 static bool r600_is_zs_format_supported(enum pipe_format format)
565 {
566 return r600_translate_dbformat(format) != ~0U;
567 }
568
569 boolean r600_is_format_supported(struct pipe_screen *screen,
570 enum pipe_format format,
571 enum pipe_texture_target target,
572 unsigned sample_count,
573 unsigned usage)
574 {
575 struct r600_screen *rscreen = (struct r600_screen*)screen;
576 unsigned retval = 0;
577
578 if (target >= PIPE_MAX_TEXTURE_TYPES) {
579 R600_ERR("r600: unsupported texture type %d\n", target);
580 return FALSE;
581 }
582
583 if (!util_format_is_supported(format, usage))
584 return FALSE;
585
586 if (sample_count > 1) {
587 if (rscreen->info.drm_minor < 22)
588 return FALSE;
589
590 /* R11G11B10 is broken on R6xx. */
591 if (rscreen->chip_class == R600 &&
592 format == PIPE_FORMAT_R11G11B10_FLOAT)
593 return FALSE;
594
595 switch (sample_count) {
596 case 2:
597 case 4:
598 case 8:
599 break;
600 default:
601 return FALSE;
602 }
603
604 /* require render-target support for multisample resources */
605 if (util_format_is_depth_or_stencil(format)) {
606 usage |= PIPE_BIND_DEPTH_STENCIL;
607 } else if (util_format_is_pure_integer(format)) {
608 return FALSE; /* no integer textures */
609 } else {
610 usage |= PIPE_BIND_RENDER_TARGET;
611 }
612 }
613
614 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
615 r600_is_sampler_format_supported(screen, format)) {
616 retval |= PIPE_BIND_SAMPLER_VIEW;
617 }
618
619 if ((usage & (PIPE_BIND_RENDER_TARGET |
620 PIPE_BIND_DISPLAY_TARGET |
621 PIPE_BIND_SCANOUT |
622 PIPE_BIND_SHARED)) &&
623 r600_is_colorbuffer_format_supported(format)) {
624 retval |= usage &
625 (PIPE_BIND_RENDER_TARGET |
626 PIPE_BIND_DISPLAY_TARGET |
627 PIPE_BIND_SCANOUT |
628 PIPE_BIND_SHARED);
629 }
630
631 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
632 r600_is_zs_format_supported(format)) {
633 retval |= PIPE_BIND_DEPTH_STENCIL;
634 }
635
636 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
637 r600_is_vertex_format_supported(format)) {
638 retval |= PIPE_BIND_VERTEX_BUFFER;
639 }
640
641 if (usage & PIPE_BIND_TRANSFER_READ)
642 retval |= PIPE_BIND_TRANSFER_READ;
643 if (usage & PIPE_BIND_TRANSFER_WRITE)
644 retval |= PIPE_BIND_TRANSFER_WRITE;
645
646 return retval == usage;
647 }
648
649 void r600_polygon_offset_update(struct r600_context *rctx)
650 {
651 struct r600_pipe_state state;
652
653 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
654 state.nregs = 0;
655 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
656 float offset_units = rctx->rasterizer->offset_units;
657 unsigned offset_db_fmt_cntl = 0, depth;
658
659 switch (rctx->framebuffer.zsbuf->format) {
660 case PIPE_FORMAT_Z24X8_UNORM:
661 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
662 depth = -24;
663 offset_units *= 2.0f;
664 break;
665 case PIPE_FORMAT_Z32_FLOAT:
666 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
667 depth = -23;
668 offset_units *= 1.0f;
669 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
670 break;
671 case PIPE_FORMAT_Z16_UNORM:
672 depth = -16;
673 offset_units *= 4.0f;
674 break;
675 default:
676 return;
677 }
678 /* XXX some of those reg can be computed with cso */
679 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
680 r600_pipe_state_add_reg(&state,
681 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
682 fui(rctx->rasterizer->offset_scale));
683 r600_pipe_state_add_reg(&state,
684 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
685 fui(offset_units));
686 r600_pipe_state_add_reg(&state,
687 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
688 fui(rctx->rasterizer->offset_scale));
689 r600_pipe_state_add_reg(&state,
690 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
691 fui(offset_units));
692 r600_pipe_state_add_reg(&state,
693 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
694 offset_db_fmt_cntl);
695 r600_context_pipe_state_set(rctx, &state);
696 }
697 }
698
699 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
700 const struct pipe_blend_state *state,
701 int mode)
702 {
703 struct r600_context *rctx = (struct r600_context *)ctx;
704 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
705 struct r600_pipe_state *rstate;
706 uint32_t color_control = 0, target_mask = 0;
707
708 if (blend == NULL) {
709 return NULL;
710 }
711 rstate = &blend->rstate;
712
713 rstate->id = R600_PIPE_STATE_BLEND;
714
715 /* R600 does not support per-MRT blends */
716 if (rctx->family > CHIP_R600)
717 color_control |= S_028808_PER_MRT_BLEND(1);
718
719 if (state->logicop_enable) {
720 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
721 } else {
722 color_control |= (0xcc << 16);
723 }
724 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
725 if (state->independent_blend_enable) {
726 for (int i = 0; i < 8; i++) {
727 if (state->rt[i].blend_enable) {
728 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
729 }
730 target_mask |= (state->rt[i].colormask << (4 * i));
731 }
732 } else {
733 for (int i = 0; i < 8; i++) {
734 if (state->rt[0].blend_enable) {
735 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
736 }
737 target_mask |= (state->rt[0].colormask << (4 * i));
738 }
739 }
740
741 if (target_mask)
742 color_control |= S_028808_SPECIAL_OP(mode);
743 else
744 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
745
746 blend->cb_target_mask = target_mask;
747 blend->cb_color_control = color_control;
748 /* only MRT0 has dual src blend */
749 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
750 for (int i = 0; i < 8; i++) {
751 /* state->rt entries > 0 only written if independent blending */
752 const int j = state->independent_blend_enable ? i : 0;
753
754 unsigned eqRGB = state->rt[j].rgb_func;
755 unsigned srcRGB = state->rt[j].rgb_src_factor;
756 unsigned dstRGB = state->rt[j].rgb_dst_factor;
757
758 unsigned eqA = state->rt[j].alpha_func;
759 unsigned srcA = state->rt[j].alpha_src_factor;
760 unsigned dstA = state->rt[j].alpha_dst_factor;
761 uint32_t bc = 0;
762
763 if (!state->rt[j].blend_enable)
764 continue;
765
766 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
767 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
768 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
769
770 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
771 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
772 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
773 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
774 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
775 }
776
777 /* R600 does not support per-MRT blends */
778 if (rctx->family > CHIP_R600)
779 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc);
780 if (i == 0)
781 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc);
782 }
783
784 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK,
785 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
786 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
787 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
788 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
789 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
790
791 blend->alpha_to_one = state->alpha_to_one;
792 return rstate;
793 }
794
795
796 static void *r600_create_blend_state(struct pipe_context *ctx,
797 const struct pipe_blend_state *state)
798 {
799 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
800 }
801
802 static void *r600_create_dsa_state(struct pipe_context *ctx,
803 const struct pipe_depth_stencil_alpha_state *state)
804 {
805 struct r600_context *rctx = (struct r600_context *)ctx;
806 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
807 unsigned db_depth_control, alpha_test_control, alpha_ref;
808 struct r600_pipe_state *rstate;
809
810 if (dsa == NULL) {
811 return NULL;
812 }
813
814 dsa->valuemask[0] = state->stencil[0].valuemask;
815 dsa->valuemask[1] = state->stencil[1].valuemask;
816 dsa->writemask[0] = state->stencil[0].writemask;
817 dsa->writemask[1] = state->stencil[1].writemask;
818
819 rstate = &dsa->rstate;
820
821 rstate->id = R600_PIPE_STATE_DSA;
822 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
823 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
824 S_028800_ZFUNC(state->depth.func);
825
826 /* stencil */
827 if (state->stencil[0].enabled) {
828 db_depth_control |= S_028800_STENCIL_ENABLE(1);
829 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
830 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
831 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
832 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
833
834 if (state->stencil[1].enabled) {
835 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
836 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
837 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
838 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
839 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
840 }
841 }
842
843 /* alpha */
844 alpha_test_control = 0;
845 alpha_ref = 0;
846 if (state->alpha.enabled) {
847 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
848 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
849 alpha_ref = fui(state->alpha.ref_value);
850 }
851 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
852 dsa->alpha_ref = alpha_ref;
853
854 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
855 return rstate;
856 }
857
858 static void *r600_create_rs_state(struct pipe_context *ctx,
859 const struct pipe_rasterizer_state *state)
860 {
861 struct r600_context *rctx = (struct r600_context *)ctx;
862 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
863 struct r600_pipe_state *rstate;
864 unsigned tmp;
865 unsigned prov_vtx = 1, polygon_dual_mode;
866 unsigned sc_mode_cntl;
867 float psize_min, psize_max;
868
869 if (rs == NULL) {
870 return NULL;
871 }
872
873 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
874 state->fill_back != PIPE_POLYGON_MODE_FILL);
875
876 if (state->flatshade_first)
877 prov_vtx = 0;
878
879 rstate = &rs->rstate;
880 rs->flatshade = state->flatshade;
881 rs->sprite_coord_enable = state->sprite_coord_enable;
882 rs->two_side = state->light_twoside;
883 rs->clip_plane_enable = state->clip_plane_enable;
884 rs->pa_sc_line_stipple = state->line_stipple_enable ?
885 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
886 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
887 rs->pa_cl_clip_cntl =
888 S_028810_PS_UCP_MODE(3) |
889 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
890 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
891 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
892 rs->multisample_enable = state->multisample;
893
894 /* offset */
895 rs->offset_units = state->offset_units;
896 rs->offset_scale = state->offset_scale * 12.0f;
897
898 rstate->id = R600_PIPE_STATE_RASTERIZER;
899 tmp = S_0286D4_FLAT_SHADE_ENA(1);
900 if (state->sprite_coord_enable) {
901 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
902 S_0286D4_PNT_SPRITE_OVRD_X(2) |
903 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
904 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
905 S_0286D4_PNT_SPRITE_OVRD_W(1);
906 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
907 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
908 }
909 }
910 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
911
912 /* point size 12.4 fixed point */
913 tmp = r600_pack_float_12p4(state->point_size/2);
914 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
915
916 if (state->point_size_per_vertex) {
917 psize_min = util_get_min_point_size(state);
918 psize_max = 8192;
919 } else {
920 /* Force the point size to be as if the vertex output was disabled. */
921 psize_min = state->point_size;
922 psize_max = state->point_size;
923 }
924 /* Divide by two, because 0.5 = 1 pixel. */
925 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
926 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
927 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
928
929 tmp = r600_pack_float_12p4(state->line_width/2);
930 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
931
932 if (rctx->chip_class >= R700) {
933 sc_mode_cntl =
934 S_028A4C_MSAA_ENABLE(state->multisample) |
935 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
936 S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
937 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
938 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
939 } else {
940 sc_mode_cntl =
941 S_028A4C_MSAA_ENABLE(state->multisample) |
942 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
943 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
944 rs->scissor_enable = state->scissor;
945 }
946 sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
947
948 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
949
950 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
951 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
952 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
953
954 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
955 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
956 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
957 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
958 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
959 S_028814_FACE(!state->front_ccw) |
960 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
961 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
962 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
963 S_028814_POLY_MODE(polygon_dual_mode) |
964 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
965 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
966 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
967 return rstate;
968 }
969
970 static void *r600_create_sampler_state(struct pipe_context *ctx,
971 const struct pipe_sampler_state *state)
972 {
973 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
974 union util_color uc;
975 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
976
977 if (ss == NULL) {
978 return NULL;
979 }
980
981 ss->seamless_cube_map = state->seamless_cube_map;
982 ss->border_color_use = false;
983 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
984 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
985 ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
986 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
987 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
988 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
989 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
990 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
991 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
992 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
993 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
994 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
995 ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
996 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
997 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
998 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
999 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
1000 if (uc.ui) {
1001 ss->border_color_use = true;
1002 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
1003 ss->border_color[0] = fui(state->border_color.f[0]);
1004 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
1005 ss->border_color[1] = fui(state->border_color.f[1]);
1006 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
1007 ss->border_color[2] = fui(state->border_color.f[2]);
1008 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
1009 ss->border_color[3] = fui(state->border_color.f[3]);
1010 }
1011 return ss;
1012 }
1013
1014 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
1015 struct pipe_resource *texture,
1016 const struct pipe_sampler_view *state)
1017 {
1018 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1019 struct r600_texture *tmp = (struct r600_texture*)texture;
1020 unsigned format, endian;
1021 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1022 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1023 unsigned width, height, depth, offset_level, last_level;
1024
1025 if (view == NULL)
1026 return NULL;
1027
1028 /* initialize base object */
1029 view->base = *state;
1030 view->base.texture = NULL;
1031 pipe_reference(NULL, &texture->reference);
1032 view->base.texture = texture;
1033 view->base.reference.count = 1;
1034 view->base.context = ctx;
1035
1036 swizzle[0] = state->swizzle_r;
1037 swizzle[1] = state->swizzle_g;
1038 swizzle[2] = state->swizzle_b;
1039 swizzle[3] = state->swizzle_a;
1040
1041 format = r600_translate_texformat(ctx->screen, state->format,
1042 swizzle,
1043 &word4, &yuv_format);
1044 assert(format != ~0);
1045 if (format == ~0) {
1046 FREE(view);
1047 return NULL;
1048 }
1049
1050 if (tmp->is_depth && !tmp->is_flushing_texture) {
1051 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1052 FREE(view);
1053 return NULL;
1054 }
1055 tmp = tmp->flushed_depth_texture;
1056 }
1057
1058 endian = r600_colorformat_endian_swap(format);
1059
1060 offset_level = state->u.tex.first_level;
1061 last_level = state->u.tex.last_level - offset_level;
1062 width = tmp->surface.level[offset_level].npix_x;
1063 height = tmp->surface.level[offset_level].npix_y;
1064 depth = tmp->surface.level[offset_level].npix_z;
1065 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1066 tile_type = tmp->tile_type;
1067
1068 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1069 height = 1;
1070 depth = texture->array_size;
1071 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1072 depth = texture->array_size;
1073 }
1074 switch (tmp->surface.level[offset_level].mode) {
1075 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1076 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1077 break;
1078 case RADEON_SURF_MODE_1D:
1079 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1080 break;
1081 case RADEON_SURF_MODE_2D:
1082 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1083 break;
1084 case RADEON_SURF_MODE_LINEAR:
1085 default:
1086 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1087 break;
1088 }
1089
1090 view->tex_resource = &tmp->resource;
1091 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1092 S_038000_TILE_MODE(array_mode) |
1093 S_038000_TILE_TYPE(tile_type) |
1094 S_038000_PITCH((pitch / 8) - 1) |
1095 S_038000_TEX_WIDTH(width - 1));
1096 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
1097 S_038004_TEX_DEPTH(depth - 1) |
1098 S_038004_DATA_FORMAT(format));
1099 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
1100 if (offset_level >= tmp->surface.last_level) {
1101 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
1102 } else {
1103 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1104 }
1105 view->tex_resource_words[4] = (word4 |
1106 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1107 S_038010_REQUEST_SIZE(1) |
1108 S_038010_ENDIAN_SWAP(endian) |
1109 S_038010_BASE_LEVEL(0));
1110 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1111 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1112 if (texture->nr_samples > 1) {
1113 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1114 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
1115 } else {
1116 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
1117 }
1118 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1119 S_038018_MAX_ANISO(4 /* max 16 samples */));
1120 return &view->base;
1121 }
1122
1123 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1124 {
1125 struct radeon_winsys_cs *cs = rctx->cs;
1126 struct pipe_clip_state *state = &rctx->clip_state.state;
1127
1128 r600_write_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
1129 r600_write_array(cs, 6*4, (unsigned*)state);
1130 }
1131
1132 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1133 const struct pipe_poly_stipple *state)
1134 {
1135 }
1136
1137 void r600_set_scissor_state(struct r600_context *rctx,
1138 const struct pipe_scissor_state *state)
1139 {
1140 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1141 uint32_t tl, br;
1142
1143 if (rstate == NULL)
1144 return;
1145
1146 rstate->id = R600_PIPE_STATE_SCISSOR;
1147 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1148 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1149 r600_pipe_state_add_reg(rstate,
1150 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1151 r600_pipe_state_add_reg(rstate,
1152 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1153
1154 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1155 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1156 r600_context_pipe_state_set(rctx, rstate);
1157 }
1158
1159 static void r600_pipe_set_scissor_state(struct pipe_context *ctx,
1160 const struct pipe_scissor_state *state)
1161 {
1162 struct r600_context *rctx = (struct r600_context *)ctx;
1163
1164 if (rctx->chip_class == R600) {
1165 rctx->scissor_state = *state;
1166
1167 if (!rctx->scissor_enable)
1168 return;
1169 }
1170
1171 r600_set_scissor_state(rctx, state);
1172 }
1173
1174 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
1175 unsigned size, unsigned alignment)
1176 {
1177 struct pipe_resource buffer;
1178
1179 memset(&buffer, 0, sizeof buffer);
1180 buffer.target = PIPE_BUFFER;
1181 buffer.format = PIPE_FORMAT_R8_UNORM;
1182 buffer.bind = PIPE_BIND_CUSTOM;
1183 buffer.usage = PIPE_USAGE_STATIC;
1184 buffer.flags = 0;
1185 buffer.width0 = size;
1186 buffer.height0 = 1;
1187 buffer.depth0 = 1;
1188 buffer.array_size = 1;
1189
1190 return (struct r600_resource*)
1191 r600_buffer_create(&rscreen->screen, &buffer, alignment);
1192 }
1193
1194 static void r600_init_color_surface(struct r600_context *rctx,
1195 struct r600_surface *surf,
1196 bool force_cmask_fmask)
1197 {
1198 struct r600_screen *rscreen = rctx->screen;
1199 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1200 unsigned level = surf->base.u.tex.level;
1201 unsigned pitch, slice;
1202 unsigned color_info;
1203 unsigned format, swap, ntype, endian;
1204 unsigned offset;
1205 const struct util_format_description *desc;
1206 int i;
1207 bool blend_bypass = 0, blend_clamp = 1;
1208
1209 if (rtex->is_depth && !rtex->is_flushing_texture) {
1210 r600_init_flushed_depth_texture(&rctx->context, surf->base.texture, NULL);
1211 rtex = rtex->flushed_depth_texture;
1212 assert(rtex);
1213 }
1214
1215 offset = rtex->surface.level[level].offset;
1216 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1217 offset += rtex->surface.level[level].slice_size *
1218 surf->base.u.tex.first_layer;
1219 }
1220 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1221 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1222 if (slice) {
1223 slice = slice - 1;
1224 }
1225 color_info = 0;
1226 switch (rtex->surface.level[level].mode) {
1227 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1228 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1229 break;
1230 case RADEON_SURF_MODE_1D:
1231 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1232 break;
1233 case RADEON_SURF_MODE_2D:
1234 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1235 break;
1236 case RADEON_SURF_MODE_LINEAR:
1237 default:
1238 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1239 break;
1240 }
1241
1242 desc = util_format_description(surf->base.format);
1243
1244 for (i = 0; i < 4; i++) {
1245 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1246 break;
1247 }
1248 }
1249
1250 ntype = V_0280A0_NUMBER_UNORM;
1251 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1252 ntype = V_0280A0_NUMBER_SRGB;
1253 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1254 if (desc->channel[i].normalized)
1255 ntype = V_0280A0_NUMBER_SNORM;
1256 else if (desc->channel[i].pure_integer)
1257 ntype = V_0280A0_NUMBER_SINT;
1258 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1259 if (desc->channel[i].normalized)
1260 ntype = V_0280A0_NUMBER_UNORM;
1261 else if (desc->channel[i].pure_integer)
1262 ntype = V_0280A0_NUMBER_UINT;
1263 }
1264
1265 format = r600_translate_colorformat(surf->base.format);
1266 assert(format != ~0);
1267
1268 swap = r600_translate_colorswap(surf->base.format);
1269 assert(swap != ~0);
1270
1271 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1272 endian = ENDIAN_NONE;
1273 } else {
1274 endian = r600_colorformat_endian_swap(format);
1275 }
1276
1277 /* set blend bypass according to docs if SINT/UINT or
1278 8/24 COLOR variants */
1279 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1280 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1281 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1282 blend_clamp = 0;
1283 blend_bypass = 1;
1284 }
1285
1286 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
1287
1288 color_info |= S_0280A0_FORMAT(format) |
1289 S_0280A0_COMP_SWAP(swap) |
1290 S_0280A0_BLEND_BYPASS(blend_bypass) |
1291 S_0280A0_BLEND_CLAMP(blend_clamp) |
1292 S_0280A0_NUMBER_TYPE(ntype) |
1293 S_0280A0_ENDIAN(endian);
1294
1295 /* EXPORT_NORM is an optimzation that can be enabled for better
1296 * performance in certain cases
1297 */
1298 if (rctx->chip_class == R600) {
1299 /* EXPORT_NORM can be enabled if:
1300 * - 11-bit or smaller UNORM/SNORM/SRGB
1301 * - BLEND_CLAMP is enabled
1302 * - BLEND_FLOAT32 is disabled
1303 */
1304 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1305 (desc->channel[i].size < 12 &&
1306 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1307 ntype != V_0280A0_NUMBER_UINT &&
1308 ntype != V_0280A0_NUMBER_SINT) &&
1309 G_0280A0_BLEND_CLAMP(color_info) &&
1310 !G_0280A0_BLEND_FLOAT32(color_info)) {
1311 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1312 surf->export_16bpc = true;
1313 }
1314 } else {
1315 /* EXPORT_NORM can be enabled if:
1316 * - 11-bit or smaller UNORM/SNORM/SRGB
1317 * - 16-bit or smaller FLOAT
1318 */
1319 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1320 ((desc->channel[i].size < 12 &&
1321 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1322 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1323 (desc->channel[i].size < 17 &&
1324 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1325 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1326 surf->export_16bpc = true;
1327 }
1328 }
1329
1330 /* These might not always be initialized to zero. */
1331 surf->cb_color_base = offset >> 8;
1332 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
1333 S_028060_SLICE_TILE_MAX(slice);
1334 surf->cb_color_fmask = surf->cb_color_base;
1335 surf->cb_color_cmask = surf->cb_color_base;
1336 surf->cb_color_mask = 0;
1337
1338 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1339 &rtex->resource.b.b);
1340 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1341 &rtex->resource.b.b);
1342
1343 if (rtex->cmask_size) {
1344 surf->cb_color_cmask = rtex->cmask_offset >> 8;
1345 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask_slice_tile_max);
1346
1347 if (rtex->fmask_size) {
1348 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1349 surf->cb_color_fmask = rtex->fmask_offset >> 8;
1350 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(slice);
1351 } else { /* cmask only */
1352 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
1353 }
1354 } else if (force_cmask_fmask) {
1355 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1356 *
1357 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1358 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1359 * because it's not an MSAA buffer.
1360 */
1361 struct r600_cmask_info cmask;
1362 struct r600_fmask_info fmask;
1363
1364 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
1365 r600_texture_get_fmask_info(rscreen, rtex, 8, &fmask);
1366
1367 /* CMASK. */
1368 if (!rctx->dummy_cmask ||
1369 rctx->dummy_cmask->buf->size < cmask.size ||
1370 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1371 struct pipe_transfer *transfer;
1372 void *ptr;
1373
1374 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1375 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1376
1377 /* Set the contents to 0xCC. */
1378 ptr = pipe_buffer_map(&rctx->context, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1379 memset(ptr, 0xCC, cmask.size);
1380 pipe_buffer_unmap(&rctx->context, transfer);
1381 }
1382 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1383 &rctx->dummy_cmask->b.b);
1384
1385 /* FMASK. */
1386 if (!rctx->dummy_fmask ||
1387 rctx->dummy_fmask->buf->size < fmask.size ||
1388 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1389 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1390 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1391
1392 }
1393 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1394 &rctx->dummy_fmask->b.b);
1395
1396 /* Init the registers. */
1397 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1398 surf->cb_color_cmask = 0;
1399 surf->cb_color_fmask = 0;
1400 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1401 S_028100_FMASK_TILE_MAX(slice);
1402 }
1403
1404 surf->cb_color_info = color_info;
1405
1406 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1407 surf->cb_color_view = 0;
1408 } else {
1409 surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
1410 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
1411 }
1412
1413 surf->color_initialized = true;
1414 }
1415
1416 static void r600_init_depth_surface(struct r600_context *rctx,
1417 struct r600_surface *surf)
1418 {
1419 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1420 unsigned level, pitch, slice, format, offset, array_mode;
1421
1422 level = surf->base.u.tex.level;
1423 offset = rtex->surface.level[level].offset;
1424 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1425 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1426 if (slice) {
1427 slice = slice - 1;
1428 }
1429 switch (rtex->surface.level[level].mode) {
1430 case RADEON_SURF_MODE_2D:
1431 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1432 break;
1433 case RADEON_SURF_MODE_1D:
1434 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1435 case RADEON_SURF_MODE_LINEAR:
1436 default:
1437 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1438 break;
1439 }
1440
1441 format = r600_translate_dbformat(surf->base.format);
1442 assert(format != ~0);
1443
1444 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1445 surf->db_depth_base = offset >> 8;
1446 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1447 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1448 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1449 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1450
1451 surf->depth_initialized = true;
1452 }
1453
1454 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1455 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1456 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1457 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1458 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1459
1460 static uint32_t r600_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
1461 {
1462 static uint32_t sample_locs_2x[] = {
1463 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1464 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1465 };
1466 static unsigned max_dist_2x = 4;
1467 static uint32_t sample_locs_4x[] = {
1468 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1469 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1470 };
1471 static unsigned max_dist_4x = 6;
1472 static uint32_t sample_locs_8x[] = {
1473 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1474 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1475 };
1476 static unsigned max_dist_8x = 8;
1477 struct r600_context *rctx = (struct r600_context *)ctx;
1478
1479 if (rctx->family == CHIP_R600) {
1480 switch (nsample) {
1481 case 0:
1482 case 1:
1483 return 0;
1484 case 2:
1485 r600_pipe_state_add_reg(rstate, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1486 return max_dist_2x;
1487 case 4:
1488 r600_pipe_state_add_reg(rstate, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1489 return max_dist_4x;
1490 case 8:
1491 r600_pipe_state_add_reg(rstate, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, sample_locs_8x[0]);
1492 r600_pipe_state_add_reg(rstate, R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1, sample_locs_8x[1]);
1493 return max_dist_8x;
1494 }
1495 } else {
1496 switch (nsample) {
1497 case 0:
1498 case 1:
1499 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0);
1500 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, 0);
1501 return 0;
1502 case 2:
1503 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_2x[0]);
1504 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_2x[1]);
1505 return max_dist_2x;
1506 case 4:
1507 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_4x[0]);
1508 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_4x[1]);
1509 return max_dist_4x;
1510 case 8:
1511 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_8x[0]);
1512 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_8x[1]);
1513 return max_dist_8x;
1514 }
1515 }
1516 R600_ERR("Invalid nr_samples %i\n", nsample);
1517 return 0;
1518 }
1519
1520 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1521 const struct pipe_framebuffer_state *state)
1522 {
1523 struct r600_context *rctx = (struct r600_context *)ctx;
1524 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1525 struct r600_surface *surf;
1526 struct r600_resource *res;
1527 struct r600_texture *rtex;
1528 uint32_t tl, br, i, nr_samples, max_dist;
1529 bool is_resolve = state->nr_cbufs == 2 &&
1530 state->cbufs[0]->texture->nr_samples > 1 &&
1531 state->cbufs[1]->texture->nr_samples <= 1;
1532 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1533 bool cb1_force_cmask_fmask = rctx->chip_class == R600 && is_resolve;
1534
1535 if (rstate == NULL)
1536 return;
1537
1538 if (rctx->framebuffer.nr_cbufs) {
1539 rctx->flags |= R600_CONTEXT_CB_FLUSH;
1540 }
1541 if (rctx->framebuffer.zsbuf) {
1542 rctx->flags |= R600_CONTEXT_DB_FLUSH;
1543 }
1544 /* R6xx errata */
1545 if (rctx->chip_class == R600) {
1546 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
1547 }
1548
1549 /* unreference old buffer and reference new one */
1550 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1551
1552 util_copy_framebuffer_state(&rctx->framebuffer, state);
1553
1554
1555 /* Colorbuffers. */
1556 rctx->export_16bpc = true;
1557 rctx->nr_cbufs = state->nr_cbufs;
1558 rctx->cb0_is_integer = state->nr_cbufs &&
1559 util_format_is_pure_integer(state->cbufs[0]->format);
1560 rctx->compressed_cb_mask = 0;
1561
1562 for (i = 0; i < state->nr_cbufs; i++) {
1563 bool force_cmask_fmask = cb1_force_cmask_fmask && i == 1;
1564 surf = (struct r600_surface*)state->cbufs[i];
1565 res = (struct r600_resource*)surf->base.texture;
1566 rtex = (struct r600_texture*)res;
1567
1568 if (!surf->color_initialized || force_cmask_fmask) {
1569 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1570 if (force_cmask_fmask) {
1571 /* re-initialize later without compression */
1572 surf->color_initialized = false;
1573 }
1574 }
1575
1576 if (!surf->export_16bpc) {
1577 rctx->export_16bpc = false;
1578 }
1579
1580 r600_pipe_state_add_reg_bo(rstate, R_028040_CB_COLOR0_BASE + i * 4,
1581 surf->cb_color_base, res, RADEON_USAGE_READWRITE);
1582 r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + i * 4,
1583 surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1584 r600_pipe_state_add_reg(rstate, R_028060_CB_COLOR0_SIZE + i * 4,
1585 surf->cb_color_size);
1586 r600_pipe_state_add_reg(rstate, R_028080_CB_COLOR0_VIEW + i * 4,
1587 surf->cb_color_view);
1588 r600_pipe_state_add_reg_bo(rstate, R_0280E0_CB_COLOR0_FRAG + i * 4,
1589 surf->cb_color_fmask, surf->cb_buffer_fmask,
1590 RADEON_USAGE_READWRITE);
1591 r600_pipe_state_add_reg_bo(rstate, R_0280C0_CB_COLOR0_TILE + i * 4,
1592 surf->cb_color_cmask, surf->cb_buffer_cmask,
1593 RADEON_USAGE_READWRITE);
1594 r600_pipe_state_add_reg(rstate, R_028100_CB_COLOR0_MASK + i * 4,
1595 surf->cb_color_mask);
1596
1597 if (rtex->fmask_size && rtex->cmask_size) {
1598 rctx->compressed_cb_mask |= 1 << i;
1599 }
1600 }
1601 /* set CB_COLOR1_INFO for possible dual-src blending */
1602 if (i == 1) {
1603 r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + 1 * 4,
1604 surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1605 i++;
1606 }
1607 for (; i < 8 ; i++) {
1608 r600_pipe_state_add_reg(rstate, R_0280A0_CB_COLOR0_INFO + i * 4, 0);
1609 }
1610
1611 /* Update alpha-test state dependencies.
1612 * Alpha-test is done on the first colorbuffer only. */
1613 if (state->nr_cbufs) {
1614 surf = (struct r600_surface*)state->cbufs[0];
1615 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1616 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1617 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1618 }
1619 }
1620
1621 /* ZS buffer. */
1622 if (state->zsbuf) {
1623 surf = (struct r600_surface*)state->zsbuf;
1624 res = (struct r600_resource*)surf->base.texture;
1625
1626 if (!surf->depth_initialized) {
1627 r600_init_depth_surface(rctx, surf);
1628 }
1629
1630 r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE, surf->db_depth_base,
1631 res, RADEON_USAGE_READWRITE);
1632 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE, surf->db_depth_size);
1633 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, surf->db_depth_view);
1634 r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO, surf->db_depth_info,
1635 res, RADEON_USAGE_READWRITE);
1636 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1637 }
1638
1639 /* Framebuffer dimensions. */
1640 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1641 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1642
1643 r600_pipe_state_add_reg(rstate,
1644 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1645 r600_pipe_state_add_reg(rstate,
1646 R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1647
1648 /* If we're doing MSAA resolve... */
1649 if (is_resolve) {
1650 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL, 1);
1651 } else {
1652 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1653 * will assure that the alpha-test will work even if there is
1654 * no colorbuffer bound. */
1655 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1656 (1ull << MAX2(state->nr_cbufs, 1)) - 1);
1657 }
1658
1659 /* Multisampling */
1660 if (state->nr_cbufs)
1661 nr_samples = state->cbufs[0]->texture->nr_samples;
1662 else if (state->zsbuf)
1663 nr_samples = state->zsbuf->texture->nr_samples;
1664 else
1665 nr_samples = 0;
1666
1667 max_dist = r600_set_ms_pos(ctx, rstate, nr_samples);
1668
1669 if (nr_samples > 1) {
1670 unsigned log_samples = util_logbase2(nr_samples);
1671
1672 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL,
1673 S_028C00_LAST_PIXEL(1) |
1674 S_028C00_EXPAND_LINE_WIDTH(1));
1675 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1676 S_028C04_MSAA_NUM_SAMPLES(log_samples) |
1677 S_028C04_MAX_SAMPLE_DIST(max_dist));
1678 } else {
1679 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
1680 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 0);
1681 }
1682
1683 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1684 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1685 r600_context_pipe_state_set(rctx, rstate);
1686
1687 if (state->zsbuf) {
1688 r600_polygon_offset_update(rctx);
1689 }
1690
1691 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1692 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1693 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1694 }
1695
1696 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1697 rctx->alphatest_state.bypass = false;
1698 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1699 }
1700 }
1701
1702 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1703 {
1704 struct radeon_winsys_cs *cs = rctx->cs;
1705 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1706
1707 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1708 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1709 if (rctx->chip_class == R600) {
1710 r600_write_value(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1711 r600_write_value(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1712 } else {
1713 r600_write_value(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1714 r600_write_value(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1715 }
1716 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1717 } else {
1718 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1719 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1720 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1721
1722 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1723 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1724 /* Always enable the first color output to make sure alpha-test works even without one. */
1725 r600_write_value(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1726 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1727 a->cb_color_control |
1728 S_028808_MULTIWRITE_ENABLE(multiwrite));
1729 }
1730 }
1731
1732 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1733 {
1734 struct radeon_winsys_cs *cs = rctx->cs;
1735 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1736 unsigned db_render_control = 0;
1737 unsigned db_render_override =
1738 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
1739 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1740 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1741
1742 if (a->occlusion_query_enabled) {
1743 if (rctx->chip_class >= R700) {
1744 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1745 }
1746 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1747 }
1748 if (a->flush_depthstencil_through_cb) {
1749 assert(a->copy_depth || a->copy_stencil);
1750
1751 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1752 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1753 S_028D0C_COPY_CENTROID(1) |
1754 S_028D0C_COPY_SAMPLE(a->copy_sample);
1755 }
1756
1757 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1758 r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1759 r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1760 }
1761
1762 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1763 {
1764 struct radeon_winsys_cs *cs = rctx->cs;
1765 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1766
1767 while (dirty_mask) {
1768 struct pipe_vertex_buffer *vb;
1769 struct r600_resource *rbuffer;
1770 unsigned offset;
1771 unsigned buffer_index = u_bit_scan(&dirty_mask);
1772
1773 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1774 rbuffer = (struct r600_resource*)vb->buffer;
1775 assert(rbuffer);
1776
1777 offset = vb->buffer_offset;
1778
1779 /* fetch resources start at index 320 */
1780 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1781 r600_write_value(cs, (320 + buffer_index) * 7);
1782 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1783 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1784 r600_write_value(cs, /* RESOURCEi_WORD2 */
1785 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1786 S_038008_STRIDE(vb->stride));
1787 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1788 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1789 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1790 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1791
1792 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1793 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1794 }
1795 }
1796
1797 static void r600_emit_constant_buffers(struct r600_context *rctx,
1798 struct r600_constbuf_state *state,
1799 unsigned buffer_id_base,
1800 unsigned reg_alu_constbuf_size,
1801 unsigned reg_alu_const_cache)
1802 {
1803 struct radeon_winsys_cs *cs = rctx->cs;
1804 uint32_t dirty_mask = state->dirty_mask;
1805
1806 while (dirty_mask) {
1807 struct pipe_constant_buffer *cb;
1808 struct r600_resource *rbuffer;
1809 unsigned offset;
1810 unsigned buffer_index = ffs(dirty_mask) - 1;
1811
1812 cb = &state->cb[buffer_index];
1813 rbuffer = (struct r600_resource*)cb->buffer;
1814 assert(rbuffer);
1815
1816 offset = cb->buffer_offset;
1817
1818 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1819 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1820 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1821
1822 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1823 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1824
1825 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1826 r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
1827 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1828 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1829 r600_write_value(cs, /* RESOURCEi_WORD2 */
1830 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1831 S_038008_STRIDE(16));
1832 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1833 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1834 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1835 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1836
1837 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1838 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1839
1840 dirty_mask &= ~(1 << buffer_index);
1841 }
1842 state->dirty_mask = 0;
1843 }
1844
1845 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1846 {
1847 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 160,
1848 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1849 R_028980_ALU_CONST_CACHE_VS_0);
1850 }
1851
1852 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1853 {
1854 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
1855 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1856 R_0289C0_ALU_CONST_CACHE_GS_0);
1857 }
1858
1859 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1860 {
1861 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
1862 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1863 R_028940_ALU_CONST_CACHE_PS_0);
1864 }
1865
1866 static void r600_emit_sampler_views(struct r600_context *rctx,
1867 struct r600_samplerview_state *state,
1868 unsigned resource_id_base)
1869 {
1870 struct radeon_winsys_cs *cs = rctx->cs;
1871 uint32_t dirty_mask = state->dirty_mask;
1872
1873 while (dirty_mask) {
1874 struct r600_pipe_sampler_view *rview;
1875 unsigned resource_index = u_bit_scan(&dirty_mask);
1876 unsigned reloc;
1877
1878 rview = state->views[resource_index];
1879 assert(rview);
1880
1881 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1882 r600_write_value(cs, (resource_id_base + resource_index) * 7);
1883 r600_write_array(cs, 7, rview->tex_resource_words);
1884
1885 /* XXX The kernel needs two relocations. This is stupid. */
1886 reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
1887 RADEON_USAGE_READ);
1888 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1889 r600_write_value(cs, reloc);
1890 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1891 r600_write_value(cs, reloc);
1892 }
1893 state->dirty_mask = 0;
1894 }
1895
1896 /* Resource IDs:
1897 * PS: 0 .. +160
1898 * VS: 160 .. +160
1899 * FS: 320 .. +16
1900 * GS: 336 .. +160
1901 */
1902
1903 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1904 {
1905 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 160 + R600_MAX_CONST_BUFFERS);
1906 }
1907
1908 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1909 {
1910 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
1911 }
1912
1913 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1914 {
1915 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
1916 }
1917
1918 static void r600_emit_sampler_states(struct r600_context *rctx,
1919 struct r600_textures_info *texinfo,
1920 unsigned resource_id_base,
1921 unsigned border_color_reg)
1922 {
1923 struct radeon_winsys_cs *cs = rctx->cs;
1924 uint32_t dirty_mask = texinfo->states.dirty_mask;
1925
1926 while (dirty_mask) {
1927 struct r600_pipe_sampler_state *rstate;
1928 struct r600_pipe_sampler_view *rview;
1929 unsigned i = u_bit_scan(&dirty_mask);
1930
1931 rstate = texinfo->states.states[i];
1932 assert(rstate);
1933 rview = texinfo->views.views[i];
1934
1935 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1936 * filtering between layers.
1937 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1938 */
1939 if (rview) {
1940 enum pipe_texture_target target = rview->base.texture->target;
1941 if (target == PIPE_TEXTURE_1D_ARRAY ||
1942 target == PIPE_TEXTURE_2D_ARRAY) {
1943 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1944 texinfo->is_array_sampler[i] = true;
1945 } else {
1946 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1947 texinfo->is_array_sampler[i] = false;
1948 }
1949 }
1950
1951 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1952 r600_write_value(cs, (resource_id_base + i) * 3);
1953 r600_write_array(cs, 3, rstate->tex_sampler_words);
1954
1955 if (rstate->border_color_use) {
1956 unsigned offset;
1957
1958 offset = border_color_reg;
1959 offset += i * 16;
1960 r600_write_config_reg_seq(cs, offset, 4);
1961 r600_write_array(cs, 4, rstate->border_color);
1962 }
1963 }
1964 texinfo->states.dirty_mask = 0;
1965 }
1966
1967 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1968 {
1969 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1970 }
1971
1972 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1973 {
1974 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1975 }
1976
1977 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1978 {
1979 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1980 }
1981
1982 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1983 {
1984 struct radeon_winsys_cs *cs = rctx->cs;
1985 unsigned tmp;
1986
1987 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1988 S_009508_SYNC_GRADIENT(1) |
1989 S_009508_SYNC_WALKER(1) |
1990 S_009508_SYNC_ALIGNER(1);
1991 if (!rctx->seamless_cube_map.enabled) {
1992 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1993 }
1994 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1995 }
1996
1997 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1998 {
1999 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2000 uint8_t mask = s->sample_mask;
2001
2002 r600_write_context_reg(rctx->cs, R_028C48_PA_SC_AA_MASK,
2003 mask | (mask << 8) | (mask << 16) | (mask << 24));
2004 }
2005
2006 void r600_init_state_functions(struct r600_context *rctx)
2007 {
2008 unsigned id = 4;
2009
2010 /* !!!
2011 * To avoid GPU lockup registers must be emited in a specific order
2012 * (no kidding ...). The order below is important and have been
2013 * partialy infered from analyzing fglrx command stream.
2014 *
2015 * Don't reorder atom without carefully checking the effect (GPU lockup
2016 * or piglit regression).
2017 * !!!
2018 */
2019
2020 /* shader const */
2021 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
2022 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
2023 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
2024
2025 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2026 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
2027 */
2028 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
2029 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
2030 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
2031 /* resource */
2032 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
2033 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
2034 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
2035 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
2036
2037 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 6);
2038 r600_init_atom(rctx, &rctx->vgt2_state.atom, id++, r600_emit_vgt2_state, 3);
2039
2040 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
2041 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
2042 rctx->sample_mask.sample_mask = ~0;
2043
2044 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
2045 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
2046 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
2047 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
2048 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
2049 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 4);
2050 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
2051 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
2052
2053 rctx->context.create_blend_state = r600_create_blend_state;
2054 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
2055 rctx->context.create_rasterizer_state = r600_create_rs_state;
2056 rctx->context.create_sampler_state = r600_create_sampler_state;
2057 rctx->context.create_sampler_view = r600_create_sampler_view;
2058 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
2059 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
2060 rctx->context.set_scissor_state = r600_pipe_set_scissor_state;
2061 }
2062
2063 /* Adjust GPR allocation on R6xx/R7xx */
2064 void r600_adjust_gprs(struct r600_context *rctx)
2065 {
2066 struct r600_pipe_state rstate;
2067 unsigned num_ps_gprs = rctx->default_ps_gprs;
2068 unsigned num_vs_gprs = rctx->default_vs_gprs;
2069 unsigned tmp;
2070 int diff;
2071
2072 if (rctx->ps_shader->current->shader.bc.ngpr > rctx->default_ps_gprs) {
2073 diff = rctx->ps_shader->current->shader.bc.ngpr - rctx->default_ps_gprs;
2074 num_vs_gprs -= diff;
2075 num_ps_gprs += diff;
2076 }
2077
2078 if (rctx->vs_shader->current->shader.bc.ngpr > rctx->default_vs_gprs)
2079 {
2080 diff = rctx->vs_shader->current->shader.bc.ngpr - rctx->default_vs_gprs;
2081 num_ps_gprs -= diff;
2082 num_vs_gprs += diff;
2083 }
2084
2085 tmp = 0;
2086 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2087 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2088 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
2089 rstate.nregs = 0;
2090 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp);
2091
2092 r600_context_pipe_state_set(rctx, &rstate);
2093 }
2094
2095 void r600_init_atom_start_cs(struct r600_context *rctx)
2096 {
2097 int ps_prio;
2098 int vs_prio;
2099 int gs_prio;
2100 int es_prio;
2101 int num_ps_gprs;
2102 int num_vs_gprs;
2103 int num_gs_gprs;
2104 int num_es_gprs;
2105 int num_temp_gprs;
2106 int num_ps_threads;
2107 int num_vs_threads;
2108 int num_gs_threads;
2109 int num_es_threads;
2110 int num_ps_stack_entries;
2111 int num_vs_stack_entries;
2112 int num_gs_stack_entries;
2113 int num_es_stack_entries;
2114 enum radeon_family family;
2115 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2116 uint32_t tmp;
2117
2118 r600_init_command_buffer(rctx, cb, 0, 256);
2119
2120 /* R6xx requires this packet at the start of each command buffer */
2121 if (rctx->chip_class == R600) {
2122 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2123 r600_store_value(cb, 0);
2124 }
2125 /* All asics require this one */
2126 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2127 r600_store_value(cb, 0x80000000);
2128 r600_store_value(cb, 0x80000000);
2129
2130 family = rctx->family;
2131 ps_prio = 0;
2132 vs_prio = 1;
2133 gs_prio = 2;
2134 es_prio = 3;
2135 switch (family) {
2136 case CHIP_R600:
2137 num_ps_gprs = 192;
2138 num_vs_gprs = 56;
2139 num_temp_gprs = 4;
2140 num_gs_gprs = 0;
2141 num_es_gprs = 0;
2142 num_ps_threads = 136;
2143 num_vs_threads = 48;
2144 num_gs_threads = 4;
2145 num_es_threads = 4;
2146 num_ps_stack_entries = 128;
2147 num_vs_stack_entries = 128;
2148 num_gs_stack_entries = 0;
2149 num_es_stack_entries = 0;
2150 break;
2151 case CHIP_RV630:
2152 case CHIP_RV635:
2153 num_ps_gprs = 84;
2154 num_vs_gprs = 36;
2155 num_temp_gprs = 4;
2156 num_gs_gprs = 0;
2157 num_es_gprs = 0;
2158 num_ps_threads = 144;
2159 num_vs_threads = 40;
2160 num_gs_threads = 4;
2161 num_es_threads = 4;
2162 num_ps_stack_entries = 40;
2163 num_vs_stack_entries = 40;
2164 num_gs_stack_entries = 32;
2165 num_es_stack_entries = 16;
2166 break;
2167 case CHIP_RV610:
2168 case CHIP_RV620:
2169 case CHIP_RS780:
2170 case CHIP_RS880:
2171 default:
2172 num_ps_gprs = 84;
2173 num_vs_gprs = 36;
2174 num_temp_gprs = 4;
2175 num_gs_gprs = 0;
2176 num_es_gprs = 0;
2177 num_ps_threads = 136;
2178 num_vs_threads = 48;
2179 num_gs_threads = 4;
2180 num_es_threads = 4;
2181 num_ps_stack_entries = 40;
2182 num_vs_stack_entries = 40;
2183 num_gs_stack_entries = 32;
2184 num_es_stack_entries = 16;
2185 break;
2186 case CHIP_RV670:
2187 num_ps_gprs = 144;
2188 num_vs_gprs = 40;
2189 num_temp_gprs = 4;
2190 num_gs_gprs = 0;
2191 num_es_gprs = 0;
2192 num_ps_threads = 136;
2193 num_vs_threads = 48;
2194 num_gs_threads = 4;
2195 num_es_threads = 4;
2196 num_ps_stack_entries = 40;
2197 num_vs_stack_entries = 40;
2198 num_gs_stack_entries = 32;
2199 num_es_stack_entries = 16;
2200 break;
2201 case CHIP_RV770:
2202 num_ps_gprs = 192;
2203 num_vs_gprs = 56;
2204 num_temp_gprs = 4;
2205 num_gs_gprs = 0;
2206 num_es_gprs = 0;
2207 num_ps_threads = 188;
2208 num_vs_threads = 60;
2209 num_gs_threads = 0;
2210 num_es_threads = 0;
2211 num_ps_stack_entries = 256;
2212 num_vs_stack_entries = 256;
2213 num_gs_stack_entries = 0;
2214 num_es_stack_entries = 0;
2215 break;
2216 case CHIP_RV730:
2217 case CHIP_RV740:
2218 num_ps_gprs = 84;
2219 num_vs_gprs = 36;
2220 num_temp_gprs = 4;
2221 num_gs_gprs = 0;
2222 num_es_gprs = 0;
2223 num_ps_threads = 188;
2224 num_vs_threads = 60;
2225 num_gs_threads = 0;
2226 num_es_threads = 0;
2227 num_ps_stack_entries = 128;
2228 num_vs_stack_entries = 128;
2229 num_gs_stack_entries = 0;
2230 num_es_stack_entries = 0;
2231 break;
2232 case CHIP_RV710:
2233 num_ps_gprs = 192;
2234 num_vs_gprs = 56;
2235 num_temp_gprs = 4;
2236 num_gs_gprs = 0;
2237 num_es_gprs = 0;
2238 num_ps_threads = 144;
2239 num_vs_threads = 48;
2240 num_gs_threads = 0;
2241 num_es_threads = 0;
2242 num_ps_stack_entries = 128;
2243 num_vs_stack_entries = 128;
2244 num_gs_stack_entries = 0;
2245 num_es_stack_entries = 0;
2246 break;
2247 }
2248
2249 rctx->default_ps_gprs = num_ps_gprs;
2250 rctx->default_vs_gprs = num_vs_gprs;
2251 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2252
2253 /* SQ_CONFIG */
2254 tmp = 0;
2255 switch (family) {
2256 case CHIP_RV610:
2257 case CHIP_RV620:
2258 case CHIP_RS780:
2259 case CHIP_RS880:
2260 case CHIP_RV710:
2261 break;
2262 default:
2263 tmp |= S_008C00_VC_ENABLE(1);
2264 break;
2265 }
2266 tmp |= S_008C00_DX9_CONSTS(0);
2267 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2268 tmp |= S_008C00_PS_PRIO(ps_prio);
2269 tmp |= S_008C00_VS_PRIO(vs_prio);
2270 tmp |= S_008C00_GS_PRIO(gs_prio);
2271 tmp |= S_008C00_ES_PRIO(es_prio);
2272 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2273
2274 /* SQ_GPR_RESOURCE_MGMT_2 */
2275 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2276 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2277 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2278 r600_store_value(cb, tmp);
2279
2280 /* SQ_THREAD_RESOURCE_MGMT */
2281 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2282 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2283 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2284 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2285 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2286
2287 /* SQ_STACK_RESOURCE_MGMT_1 */
2288 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2289 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2290 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2291
2292 /* SQ_STACK_RESOURCE_MGMT_2 */
2293 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2294 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2295 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2296
2297 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2298
2299 if (rctx->chip_class >= R700) {
2300 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2301 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2302 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2303 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2304 } else {
2305 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2306 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2307 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2308 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2309 }
2310 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2311 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2312 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2313 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2314 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2315 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2316 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2317 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2318 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2319 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2320
2321 /* to avoid GPU doing any preloading of constant from random address */
2322 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2323 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2324 r600_store_value(cb, 0);
2325 r600_store_value(cb, 0);
2326 r600_store_value(cb, 0);
2327 r600_store_value(cb, 0);
2328 r600_store_value(cb, 0);
2329 r600_store_value(cb, 0);
2330 r600_store_value(cb, 0);
2331 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2332 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2333 r600_store_value(cb, 0);
2334 r600_store_value(cb, 0);
2335 r600_store_value(cb, 0);
2336 r600_store_value(cb, 0);
2337 r600_store_value(cb, 0);
2338 r600_store_value(cb, 0);
2339 r600_store_value(cb, 0);
2340
2341 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2342 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2343 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2344 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2345 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2346 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2347 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2348 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2349 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2350 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2351 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2352 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2353 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2354 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2355
2356 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2357 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2358 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2359
2360 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2361 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2362 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2363 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2364
2365 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2366
2367 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2368 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2369 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2370
2371 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2372
2373 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2374 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2375 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2376
2377 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2378 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2379 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2380 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2381
2382 r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2383 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2384 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2385
2386 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2387 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2388
2389 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2390 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2391 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2392 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2393 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2394
2395 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2396 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2397 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2398
2399 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2400
2401 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2402 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2403
2404 if (rctx->chip_class >= R700) {
2405 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2406 }
2407
2408 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2409 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2410 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2411 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2412 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2413
2414 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2415 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2416 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2417
2418 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2419 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2420 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2421
2422 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2423 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2424 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2425
2426 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2427 r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2428
2429 if (rctx->chip_class == R700 && rctx->screen->has_streamout)
2430 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2431 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2432 if (rctx->screen->has_streamout) {
2433 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2434 }
2435
2436 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2437 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2438 }
2439
2440 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2441 {
2442 struct r600_context *rctx = (struct r600_context *)ctx;
2443 struct r600_pipe_state *rstate = &shader->rstate;
2444 struct r600_shader *rshader = &shader->shader;
2445 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2446 int pos_index = -1, face_index = -1;
2447 unsigned tmp, sid, ufi = 0;
2448 int need_linear = 0;
2449 unsigned z_export = 0, stencil_export = 0;
2450
2451 rstate->nregs = 0;
2452
2453 for (i = 0; i < rshader->ninput; i++) {
2454 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2455 pos_index = i;
2456 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2457 face_index = i;
2458
2459 sid = rshader->input[i].spi_sid;
2460
2461 tmp = S_028644_SEMANTIC(sid);
2462
2463 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2464 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2465 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2466 rctx->rasterizer && rctx->rasterizer->flatshade))
2467 tmp |= S_028644_FLAT_SHADE(1);
2468
2469 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2470 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2471 tmp |= S_028644_PT_SPRITE_TEX(1);
2472 }
2473
2474 if (rshader->input[i].centroid)
2475 tmp |= S_028644_SEL_CENTROID(1);
2476
2477 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2478 need_linear = 1;
2479 tmp |= S_028644_SEL_LINEAR(1);
2480 }
2481
2482 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2483 tmp);
2484 }
2485
2486 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2487 for (i = 0; i < rshader->noutput; i++) {
2488 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2489 z_export = 1;
2490 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2491 stencil_export = 1;
2492 }
2493 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2494 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2495 if (rshader->uses_kill)
2496 db_shader_control |= S_02880C_KILL_ENABLE(1);
2497
2498 exports_ps = 0;
2499 for (i = 0; i < rshader->noutput; i++) {
2500 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2501 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2502 exports_ps |= 1;
2503 }
2504 }
2505 num_cout = rshader->nr_ps_color_exports;
2506 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2507 if (!exports_ps) {
2508 /* always at least export 1 component per pixel */
2509 exports_ps = 2;
2510 }
2511
2512 shader->nr_ps_color_outputs = num_cout;
2513
2514 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2515 S_0286CC_PERSP_GRADIENT_ENA(1)|
2516 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2517 spi_input_z = 0;
2518 if (pos_index != -1) {
2519 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2520 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2521 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2522 S_0286CC_BARYC_SAMPLE_CNTL(1));
2523 spi_input_z |= 1;
2524 }
2525
2526 spi_ps_in_control_1 = 0;
2527 if (face_index != -1) {
2528 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2529 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2530 }
2531
2532 /* HW bug in original R600 */
2533 if (rctx->family == CHIP_R600)
2534 ufi = 1;
2535
2536 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2537 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2538 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2539 r600_pipe_state_add_reg_bo(rstate,
2540 R_028840_SQ_PGM_START_PS,
2541 0, shader->bo, RADEON_USAGE_READ);
2542 r600_pipe_state_add_reg(rstate,
2543 R_028850_SQ_PGM_RESOURCES_PS,
2544 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2545 S_028850_STACK_SIZE(rshader->bc.nstack) |
2546 S_028850_UNCACHED_FIRST_INST(ufi));
2547 r600_pipe_state_add_reg(rstate,
2548 R_028854_SQ_PGM_EXPORTS_PS,
2549 exports_ps);
2550 /* only set some bits here, the other bits are set in the dsa state */
2551 shader->db_shader_control = db_shader_control;
2552 shader->ps_depth_export = z_export | stencil_export;
2553
2554 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2555 if (rctx->rasterizer)
2556 shader->flatshade = rctx->rasterizer->flatshade;
2557 }
2558
2559 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2560 {
2561 struct r600_context *rctx = (struct r600_context *)ctx;
2562 struct r600_pipe_state *rstate = &shader->rstate;
2563 struct r600_shader *rshader = &shader->shader;
2564 unsigned spi_vs_out_id[10] = {};
2565 unsigned i, tmp, nparams = 0;
2566
2567 /* clear previous register */
2568 rstate->nregs = 0;
2569
2570 for (i = 0; i < rshader->noutput; i++) {
2571 if (rshader->output[i].spi_sid) {
2572 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2573 spi_vs_out_id[nparams / 4] |= tmp;
2574 nparams++;
2575 }
2576 }
2577
2578 for (i = 0; i < 10; i++) {
2579 r600_pipe_state_add_reg(rstate,
2580 R_028614_SPI_VS_OUT_ID_0 + i * 4,
2581 spi_vs_out_id[i]);
2582 }
2583
2584 /* Certain attributes (position, psize, etc.) don't count as params.
2585 * VS is required to export at least one param and r600_shader_from_tgsi()
2586 * takes care of adding a dummy export.
2587 */
2588 if (nparams < 1)
2589 nparams = 1;
2590
2591 r600_pipe_state_add_reg(rstate,
2592 R_0286C4_SPI_VS_OUT_CONFIG,
2593 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2594 r600_pipe_state_add_reg(rstate,
2595 R_028868_SQ_PGM_RESOURCES_VS,
2596 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2597 S_028868_STACK_SIZE(rshader->bc.nstack));
2598 r600_pipe_state_add_reg_bo(rstate,
2599 R_028858_SQ_PGM_START_VS,
2600 0, shader->bo, RADEON_USAGE_READ);
2601
2602 shader->pa_cl_vs_out_cntl =
2603 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2604 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2605 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2606 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2607 }
2608
2609 void r600_fetch_shader(struct pipe_context *ctx,
2610 struct r600_vertex_element *ve)
2611 {
2612 struct r600_pipe_state *rstate;
2613 struct r600_context *rctx = (struct r600_context *)ctx;
2614
2615 rstate = &ve->rstate;
2616 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2617 rstate->nregs = 0;
2618 r600_pipe_state_add_reg_bo(rstate, R_028894_SQ_PGM_START_FS,
2619 0,
2620 ve->fetch_shader, RADEON_USAGE_READ);
2621 }
2622
2623 void *r600_create_resolve_blend(struct r600_context *rctx)
2624 {
2625 struct pipe_blend_state blend;
2626 struct r600_pipe_state *rstate;
2627 unsigned i;
2628
2629 memset(&blend, 0, sizeof(blend));
2630 blend.independent_blend_enable = true;
2631 for (i = 0; i < 2; i++) {
2632 blend.rt[i].colormask = 0xf;
2633 blend.rt[i].blend_enable = 1;
2634 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2635 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2636 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2637 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2638 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2639 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2640 }
2641 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2642 return rstate;
2643 }
2644
2645 void *r700_create_resolve_blend(struct r600_context *rctx)
2646 {
2647 struct pipe_blend_state blend;
2648 struct r600_pipe_state *rstate;
2649
2650 memset(&blend, 0, sizeof(blend));
2651 blend.independent_blend_enable = true;
2652 blend.rt[0].colormask = 0xf;
2653 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2654 return rstate;
2655 }
2656
2657 void *r600_create_decompress_blend(struct r600_context *rctx)
2658 {
2659 struct pipe_blend_state blend;
2660 struct r600_pipe_state *rstate;
2661
2662 memset(&blend, 0, sizeof(blend));
2663 blend.independent_blend_enable = true;
2664 blend.rt[0].colormask = 0xf;
2665 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2666 return rstate;
2667 }
2668
2669 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2670 {
2671 struct pipe_depth_stencil_alpha_state dsa;
2672 boolean quirk = false;
2673
2674 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2675 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2676 quirk = true;
2677
2678 memset(&dsa, 0, sizeof(dsa));
2679
2680 if (quirk) {
2681 dsa.depth.enabled = 1;
2682 dsa.depth.func = PIPE_FUNC_LEQUAL;
2683 dsa.stencil[0].enabled = 1;
2684 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2685 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2686 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2687 dsa.stencil[0].writemask = 0xff;
2688 }
2689
2690 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2691 }
2692
2693 void r600_update_dual_export_state(struct r600_context * rctx)
2694 {
2695 unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
2696 !rctx->ps_shader->current->ps_depth_export;
2697 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2698 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2699
2700 if (db_shader_control != rctx->db_shader_control) {
2701 struct r600_pipe_state rstate;
2702
2703 rctx->db_shader_control = db_shader_control;
2704 rstate.nregs = 0;
2705 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2706 r600_context_pipe_state_set(rctx, &rstate);
2707 }
2708 }