2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
24 #include "r600_shader.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
33 static uint32_t r600_translate_blend_function(int blend_func
)
37 return V_028804_COMB_DST_PLUS_SRC
;
38 case PIPE_BLEND_SUBTRACT
:
39 return V_028804_COMB_SRC_MINUS_DST
;
40 case PIPE_BLEND_REVERSE_SUBTRACT
:
41 return V_028804_COMB_DST_MINUS_SRC
;
43 return V_028804_COMB_MIN_DST_SRC
;
45 return V_028804_COMB_MAX_DST_SRC
;
47 R600_ERR("Unknown blend function %d\n", blend_func
);
54 static uint32_t r600_translate_blend_factor(int blend_fact
)
57 case PIPE_BLENDFACTOR_ONE
:
58 return V_028804_BLEND_ONE
;
59 case PIPE_BLENDFACTOR_SRC_COLOR
:
60 return V_028804_BLEND_SRC_COLOR
;
61 case PIPE_BLENDFACTOR_SRC_ALPHA
:
62 return V_028804_BLEND_SRC_ALPHA
;
63 case PIPE_BLENDFACTOR_DST_ALPHA
:
64 return V_028804_BLEND_DST_ALPHA
;
65 case PIPE_BLENDFACTOR_DST_COLOR
:
66 return V_028804_BLEND_DST_COLOR
;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE
;
69 case PIPE_BLENDFACTOR_CONST_COLOR
:
70 return V_028804_BLEND_CONST_COLOR
;
71 case PIPE_BLENDFACTOR_CONST_ALPHA
:
72 return V_028804_BLEND_CONST_ALPHA
;
73 case PIPE_BLENDFACTOR_ZERO
:
74 return V_028804_BLEND_ZERO
;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR
;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA
;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA
;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR
;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR
;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA
;
87 case PIPE_BLENDFACTOR_SRC1_COLOR
:
88 return V_028804_BLEND_SRC1_COLOR
;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
90 return V_028804_BLEND_SRC1_ALPHA
;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
92 return V_028804_BLEND_INV_SRC1_COLOR
;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
94 return V_028804_BLEND_INV_SRC1_ALPHA
;
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
103 static unsigned r600_tex_dim(unsigned dim
, unsigned nr_samples
)
107 case PIPE_TEXTURE_1D
:
108 return V_038000_SQ_TEX_DIM_1D
;
109 case PIPE_TEXTURE_1D_ARRAY
:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY
;
111 case PIPE_TEXTURE_2D
:
112 case PIPE_TEXTURE_RECT
:
113 return nr_samples
> 1 ? V_038000_SQ_TEX_DIM_2D_MSAA
:
114 V_038000_SQ_TEX_DIM_2D
;
115 case PIPE_TEXTURE_2D_ARRAY
:
116 return nr_samples
> 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
117 V_038000_SQ_TEX_DIM_2D_ARRAY
;
118 case PIPE_TEXTURE_3D
:
119 return V_038000_SQ_TEX_DIM_3D
;
120 case PIPE_TEXTURE_CUBE
:
121 case PIPE_TEXTURE_CUBE_ARRAY
:
122 return V_038000_SQ_TEX_DIM_CUBEMAP
;
126 static uint32_t r600_translate_dbformat(enum pipe_format format
)
129 case PIPE_FORMAT_Z16_UNORM
:
130 return V_028010_DEPTH_16
;
131 case PIPE_FORMAT_Z24X8_UNORM
:
132 return V_028010_DEPTH_X8_24
;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
134 return V_028010_DEPTH_8_24
;
135 case PIPE_FORMAT_Z32_FLOAT
:
136 return V_028010_DEPTH_32_FLOAT
;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
138 return V_028010_DEPTH_X24_8_32_FLOAT
;
144 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
146 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
) != ~0U;
149 static bool r600_is_colorbuffer_format_supported(enum chip_class chip
, enum pipe_format format
)
151 return r600_translate_colorformat(chip
, format
) != ~0U &&
152 r600_translate_colorswap(format
) != ~0U;
155 static bool r600_is_zs_format_supported(enum pipe_format format
)
157 return r600_translate_dbformat(format
) != ~0U;
160 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
161 enum pipe_format format
,
162 enum pipe_texture_target target
,
163 unsigned sample_count
,
166 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
169 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
170 R600_ERR("r600: unsupported texture type %d\n", target
);
174 if (!util_format_is_supported(format
, usage
))
177 if (sample_count
> 1) {
178 if (!rscreen
->has_msaa
)
181 /* R11G11B10 is broken on R6xx. */
182 if (rscreen
->b
.chip_class
== R600
&&
183 format
== PIPE_FORMAT_R11G11B10_FLOAT
)
186 /* MSAA integer colorbuffers hang. */
187 if (util_format_is_pure_integer(format
) &&
188 !util_format_is_depth_or_stencil(format
))
191 switch (sample_count
) {
201 if (usage
& PIPE_BIND_SAMPLER_VIEW
) {
202 if (target
== PIPE_BUFFER
) {
203 if (r600_is_vertex_format_supported(format
))
204 retval
|= PIPE_BIND_SAMPLER_VIEW
;
206 if (r600_is_sampler_format_supported(screen
, format
))
207 retval
|= PIPE_BIND_SAMPLER_VIEW
;
211 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
212 PIPE_BIND_DISPLAY_TARGET
|
215 PIPE_BIND_BLENDABLE
)) &&
216 r600_is_colorbuffer_format_supported(rscreen
->b
.chip_class
, format
)) {
218 (PIPE_BIND_RENDER_TARGET
|
219 PIPE_BIND_DISPLAY_TARGET
|
222 if (!util_format_is_pure_integer(format
) &&
223 !util_format_is_depth_or_stencil(format
))
224 retval
|= usage
& PIPE_BIND_BLENDABLE
;
227 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
228 r600_is_zs_format_supported(format
)) {
229 retval
|= PIPE_BIND_DEPTH_STENCIL
;
232 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
233 r600_is_vertex_format_supported(format
)) {
234 retval
|= PIPE_BIND_VERTEX_BUFFER
;
237 if (usage
& PIPE_BIND_TRANSFER_READ
)
238 retval
|= PIPE_BIND_TRANSFER_READ
;
239 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
240 retval
|= PIPE_BIND_TRANSFER_WRITE
;
242 if ((usage
& PIPE_BIND_LINEAR
) &&
243 !util_format_is_compressed(format
) &&
244 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
245 retval
|= PIPE_BIND_LINEAR
;
247 return retval
== usage
;
250 static void r600_emit_polygon_offset(struct r600_context
*rctx
, struct r600_atom
*a
)
252 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
253 struct r600_poly_offset_state
*state
= (struct r600_poly_offset_state
*)a
;
254 float offset_units
= state
->offset_units
;
255 float offset_scale
= state
->offset_scale
;
257 switch (state
->zs_format
) {
258 case PIPE_FORMAT_Z24X8_UNORM
:
259 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
260 offset_units
*= 2.0f
;
262 case PIPE_FORMAT_Z16_UNORM
:
263 offset_units
*= 4.0f
;
268 radeon_set_context_reg_seq(cs
, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE
, 4);
269 radeon_emit(cs
, fui(offset_scale
));
270 radeon_emit(cs
, fui(offset_units
));
271 radeon_emit(cs
, fui(offset_scale
));
272 radeon_emit(cs
, fui(offset_units
));
275 static uint32_t r600_get_blend_control(const struct pipe_blend_state
*state
, unsigned i
)
277 int j
= state
->independent_blend_enable
? i
: 0;
279 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
280 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
281 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
283 unsigned eqA
= state
->rt
[j
].alpha_func
;
284 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
285 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
288 if (!state
->rt
[j
].blend_enable
)
291 bc
|= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
292 bc
|= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
293 bc
|= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
295 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
296 bc
|= S_028804_SEPARATE_ALPHA_BLEND(1);
297 bc
|= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
298 bc
|= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
299 bc
|= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
304 static void *r600_create_blend_state_mode(struct pipe_context
*ctx
,
305 const struct pipe_blend_state
*state
,
308 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
309 uint32_t color_control
= 0, target_mask
= 0;
310 struct r600_blend_state
*blend
= CALLOC_STRUCT(r600_blend_state
);
316 r600_init_command_buffer(&blend
->buffer
, 20);
317 r600_init_command_buffer(&blend
->buffer_no_blend
, 20);
319 /* R600 does not support per-MRT blends */
320 if (rctx
->b
.family
> CHIP_R600
)
321 color_control
|= S_028808_PER_MRT_BLEND(1);
323 if (state
->logicop_enable
) {
324 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
326 color_control
|= (0xcc << 16);
328 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
329 if (state
->independent_blend_enable
) {
330 for (int i
= 0; i
< 8; i
++) {
331 if (state
->rt
[i
].blend_enable
) {
332 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
334 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
337 for (int i
= 0; i
< 8; i
++) {
338 if (state
->rt
[0].blend_enable
) {
339 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
341 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
346 color_control
|= S_028808_SPECIAL_OP(mode
);
348 color_control
|= S_028808_SPECIAL_OP(V_028808_DISABLE
);
350 /* only MRT0 has dual src blend */
351 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
352 blend
->cb_target_mask
= target_mask
;
353 blend
->cb_color_control
= color_control
;
354 blend
->cb_color_control_no_blend
= color_control
& C_028808_TARGET_BLEND_ENABLE
;
355 blend
->alpha_to_one
= state
->alpha_to_one
;
357 r600_store_context_reg(&blend
->buffer
, R_028D44_DB_ALPHA_TO_MASK
,
358 S_028D44_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
359 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
360 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
361 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
362 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
364 /* Copy over the registers set so far into buffer_no_blend. */
365 memcpy(blend
->buffer_no_blend
.buf
, blend
->buffer
.buf
, blend
->buffer
.num_dw
* 4);
366 blend
->buffer_no_blend
.num_dw
= blend
->buffer
.num_dw
;
368 /* Only add blend registers if blending is enabled. */
369 if (!G_028808_TARGET_BLEND_ENABLE(color_control
)) {
373 /* The first R600 does not support per-MRT blends */
374 r600_store_context_reg(&blend
->buffer
, R_028804_CB_BLEND_CONTROL
,
375 r600_get_blend_control(state
, 0));
377 if (rctx
->b
.family
> CHIP_R600
) {
378 r600_store_context_reg_seq(&blend
->buffer
, R_028780_CB_BLEND0_CONTROL
, 8);
379 for (int i
= 0; i
< 8; i
++) {
380 r600_store_value(&blend
->buffer
, r600_get_blend_control(state
, i
));
386 static void *r600_create_blend_state(struct pipe_context
*ctx
,
387 const struct pipe_blend_state
*state
)
389 return r600_create_blend_state_mode(ctx
, state
, V_028808_SPECIAL_NORMAL
);
392 static void *r600_create_dsa_state(struct pipe_context
*ctx
,
393 const struct pipe_depth_stencil_alpha_state
*state
)
395 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
396 struct r600_dsa_state
*dsa
= CALLOC_STRUCT(r600_dsa_state
);
402 r600_init_command_buffer(&dsa
->buffer
, 3);
404 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
405 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
406 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
407 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
408 dsa
->zwritemask
= state
->depth
.writemask
;
410 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
411 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
412 S_028800_ZFUNC(state
->depth
.func
);
415 if (state
->stencil
[0].enabled
) {
416 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
417 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
418 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
419 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
420 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
422 if (state
->stencil
[1].enabled
) {
423 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
424 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
425 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
426 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
427 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
432 alpha_test_control
= 0;
434 if (state
->alpha
.enabled
) {
435 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
436 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
437 alpha_ref
= fui(state
->alpha
.ref_value
);
439 dsa
->sx_alpha_test_control
= alpha_test_control
& 0xff;
440 dsa
->alpha_ref
= alpha_ref
;
442 r600_store_context_reg(&dsa
->buffer
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
446 static void *r600_create_rs_state(struct pipe_context
*ctx
,
447 const struct pipe_rasterizer_state
*state
)
449 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
450 unsigned tmp
, sc_mode_cntl
, spi_interp
;
451 float psize_min
, psize_max
;
452 struct r600_rasterizer_state
*rs
= CALLOC_STRUCT(r600_rasterizer_state
);
458 r600_init_command_buffer(&rs
->buffer
, 30);
460 rs
->flatshade
= state
->flatshade
;
461 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
462 rs
->two_side
= state
->light_twoside
;
463 rs
->clip_plane_enable
= state
->clip_plane_enable
;
464 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
465 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
466 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
467 rs
->pa_cl_clip_cntl
=
468 S_028810_PS_UCP_MODE(3) |
469 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
470 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
471 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
472 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
473 if (rctx
->b
.chip_class
== R700
) {
474 rs
->pa_cl_clip_cntl
|=
475 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
);
477 rs
->multisample_enable
= state
->multisample
;
480 rs
->offset_units
= state
->offset_units
;
481 rs
->offset_scale
= state
->offset_scale
* 16.0f
;
482 rs
->offset_enable
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
484 if (state
->point_size_per_vertex
) {
485 psize_min
= util_get_min_point_size(state
);
488 /* Force the point size to be as if the vertex output was disabled. */
489 psize_min
= state
->point_size
;
490 psize_max
= state
->point_size
;
493 sc_mode_cntl
= S_028A4C_MSAA_ENABLE(state
->multisample
) |
494 S_028A4C_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
495 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
496 S_028A4C_PS_ITER_SAMPLE(state
->multisample
&& rctx
->ps_iter_samples
> 1);
497 if (rctx
->b
.family
== CHIP_RV770
) {
498 /* workaround possible rendering corruption on RV770 with hyperz together with sample shading */
499 sc_mode_cntl
|= S_028A4C_TILE_COVER_DISABLE(state
->multisample
&& rctx
->ps_iter_samples
> 1);
501 if (rctx
->b
.chip_class
>= R700
) {
502 sc_mode_cntl
|= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
503 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
504 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state
->scissor
);
506 sc_mode_cntl
|= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
507 rs
->scissor_enable
= state
->scissor
;
510 spi_interp
= S_0286D4_FLAT_SHADE_ENA(1);
511 if (state
->sprite_coord_enable
) {
512 spi_interp
|= S_0286D4_PNT_SPRITE_ENA(1) |
513 S_0286D4_PNT_SPRITE_OVRD_X(2) |
514 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
515 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
516 S_0286D4_PNT_SPRITE_OVRD_W(1);
517 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
518 spi_interp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
522 r600_store_context_reg_seq(&rs
->buffer
, R_028A00_PA_SU_POINT_SIZE
, 3);
523 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
524 tmp
= r600_pack_float_12p4(state
->point_size
/2);
525 r600_store_value(&rs
->buffer
, /* R_028A00_PA_SU_POINT_SIZE */
526 S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
527 r600_store_value(&rs
->buffer
, /* R_028A04_PA_SU_POINT_MINMAX */
528 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
529 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
530 r600_store_value(&rs
->buffer
, /* R_028A08_PA_SU_LINE_CNTL */
531 S_028A08_WIDTH(r600_pack_float_12p4(state
->line_width
/2)));
533 r600_store_context_reg(&rs
->buffer
, R_0286D4_SPI_INTERP_CONTROL_0
, spi_interp
);
534 r600_store_context_reg(&rs
->buffer
, R_028A4C_PA_SC_MODE_CNTL
, sc_mode_cntl
);
535 r600_store_context_reg(&rs
->buffer
, R_028C08_PA_SU_VTX_CNTL
,
536 S_028C08_PIX_CENTER_HALF(state
->half_pixel_center
) |
537 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
538 r600_store_context_reg(&rs
->buffer
, R_028DFC_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
540 rs
->pa_su_sc_mode_cntl
= S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
541 S_028814_CULL_FRONT(state
->cull_face
& PIPE_FACE_FRONT
? 1 : 0) |
542 S_028814_CULL_BACK(state
->cull_face
& PIPE_FACE_BACK
? 1 : 0) |
543 S_028814_FACE(!state
->front_ccw
) |
544 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
545 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
546 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
547 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
548 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
549 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
550 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
));
551 if (rctx
->b
.chip_class
== R700
) {
552 r600_store_context_reg(&rs
->buffer
, R_028814_PA_SU_SC_MODE_CNTL
, rs
->pa_su_sc_mode_cntl
);
554 if (rctx
->b
.chip_class
== R600
) {
555 r600_store_context_reg(&rs
->buffer
, R_028350_SX_MISC
,
556 S_028350_MULTIPASS(state
->rasterizer_discard
));
561 static void *r600_create_sampler_state(struct pipe_context
*ctx
,
562 const struct pipe_sampler_state
*state
)
564 struct r600_pipe_sampler_state
*ss
= CALLOC_STRUCT(r600_pipe_sampler_state
);
565 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 4 : 0;
571 ss
->seamless_cube_map
= state
->seamless_cube_map
;
572 ss
->border_color_use
= sampler_state_needs_border_color(state
);
574 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
575 ss
->tex_sampler_words
[0] =
576 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
577 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
578 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
579 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
580 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
581 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
582 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
583 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
584 S_03C000_BORDER_COLOR_TYPE(ss
->border_color_use
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0);
585 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
586 ss
->tex_sampler_words
[1] =
587 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 6)) |
588 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 6)) |
589 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 6));
590 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
591 ss
->tex_sampler_words
[2] = S_03C008_TYPE(1);
593 if (ss
->border_color_use
) {
594 memcpy(&ss
->border_color
, &state
->border_color
, sizeof(state
->border_color
));
599 static struct pipe_sampler_view
*
600 texture_buffer_sampler_view(struct r600_pipe_sampler_view
*view
,
601 unsigned width0
, unsigned height0
)
604 struct r600_texture
*tmp
= (struct r600_texture
*)view
->base
.texture
;
605 int stride
= util_format_get_blocksize(view
->base
.format
);
606 unsigned format
, num_format
, format_comp
, endian
;
607 uint64_t offset
= view
->base
.u
.buf
.first_element
* stride
;
608 unsigned size
= (view
->base
.u
.buf
.last_element
- view
->base
.u
.buf
.first_element
+ 1) * stride
;
610 r600_vertex_data_type(view
->base
.format
,
611 &format
, &num_format
, &format_comp
,
614 view
->tex_resource
= &tmp
->resource
;
615 view
->skip_mip_address_reloc
= true;
617 view
->tex_resource_words
[0] = offset
;
618 view
->tex_resource_words
[1] = size
- 1;
619 view
->tex_resource_words
[2] = S_038008_BASE_ADDRESS_HI(offset
>> 32UL) |
620 S_038008_STRIDE(stride
) |
621 S_038008_DATA_FORMAT(format
) |
622 S_038008_NUM_FORMAT_ALL(num_format
) |
623 S_038008_FORMAT_COMP_ALL(format_comp
) |
624 S_038008_ENDIAN_SWAP(endian
);
625 view
->tex_resource_words
[3] = 0;
627 * in theory dword 4 is for number of elements, for use with resinfo,
628 * but it seems to utterly fail to work, the amd gpu shader analyser
629 * uses a const buffer to store the element sizes for buffer txq
631 view
->tex_resource_words
[4] = 0;
632 view
->tex_resource_words
[5] = 0;
633 view
->tex_resource_words
[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER
);
637 struct pipe_sampler_view
*
638 r600_create_sampler_view_custom(struct pipe_context
*ctx
,
639 struct pipe_resource
*texture
,
640 const struct pipe_sampler_view
*state
,
641 unsigned width_first_level
, unsigned height_first_level
)
643 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
644 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
645 unsigned format
, endian
;
646 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
647 unsigned char swizzle
[4], array_mode
= 0;
648 unsigned width
, height
, depth
, offset_level
, last_level
;
653 /* initialize base object */
655 view
->base
.texture
= NULL
;
656 pipe_reference(NULL
, &texture
->reference
);
657 view
->base
.texture
= texture
;
658 view
->base
.reference
.count
= 1;
659 view
->base
.context
= ctx
;
661 if (texture
->target
== PIPE_BUFFER
)
662 return texture_buffer_sampler_view(view
, texture
->width0
, 1);
664 swizzle
[0] = state
->swizzle_r
;
665 swizzle
[1] = state
->swizzle_g
;
666 swizzle
[2] = state
->swizzle_b
;
667 swizzle
[3] = state
->swizzle_a
;
669 format
= r600_translate_texformat(ctx
->screen
, state
->format
,
671 &word4
, &yuv_format
);
672 assert(format
!= ~0);
678 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
&& !r600_can_read_depth(tmp
)) {
679 if (!r600_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
683 tmp
= tmp
->flushed_depth_texture
;
686 endian
= r600_colorformat_endian_swap(format
);
688 offset_level
= state
->u
.tex
.first_level
;
689 last_level
= state
->u
.tex
.last_level
- offset_level
;
690 width
= width_first_level
;
691 height
= height_first_level
;
692 depth
= u_minify(texture
->depth0
, offset_level
);
693 pitch
= tmp
->surface
.level
[offset_level
].nblk_x
* util_format_get_blockwidth(state
->format
);
695 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
697 depth
= texture
->array_size
;
698 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
699 depth
= texture
->array_size
;
700 } else if (texture
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
701 depth
= texture
->array_size
/ 6;
702 switch (tmp
->surface
.level
[offset_level
].mode
) {
703 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
704 array_mode
= V_038000_ARRAY_LINEAR_ALIGNED
;
706 case RADEON_SURF_MODE_1D
:
707 array_mode
= V_038000_ARRAY_1D_TILED_THIN1
;
709 case RADEON_SURF_MODE_2D
:
710 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
712 case RADEON_SURF_MODE_LINEAR
:
714 array_mode
= V_038000_ARRAY_LINEAR_GENERAL
;
718 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
719 state
->format
== PIPE_FORMAT_S8X24_UINT
||
720 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
721 state
->format
== PIPE_FORMAT_S8_UINT
)
722 view
->is_stencil_sampler
= true;
724 view
->tex_resource
= &tmp
->resource
;
725 view
->tex_resource_words
[0] = (S_038000_DIM(r600_tex_dim(texture
->target
, texture
->nr_samples
)) |
726 S_038000_TILE_MODE(array_mode
) |
727 S_038000_TILE_TYPE(tmp
->non_disp_tiling
) |
728 S_038000_PITCH((pitch
/ 8) - 1) |
729 S_038000_TEX_WIDTH(width
- 1));
730 view
->tex_resource_words
[1] = (S_038004_TEX_HEIGHT(height
- 1) |
731 S_038004_TEX_DEPTH(depth
- 1) |
732 S_038004_DATA_FORMAT(format
));
733 view
->tex_resource_words
[2] = tmp
->surface
.level
[offset_level
].offset
>> 8;
734 if (offset_level
>= tmp
->surface
.last_level
) {
735 view
->tex_resource_words
[3] = tmp
->surface
.level
[offset_level
].offset
>> 8;
737 view
->tex_resource_words
[3] = tmp
->surface
.level
[offset_level
+ 1].offset
>> 8;
739 view
->tex_resource_words
[4] = (word4
|
740 S_038010_REQUEST_SIZE(1) |
741 S_038010_ENDIAN_SWAP(endian
) |
742 S_038010_BASE_LEVEL(0));
743 view
->tex_resource_words
[5] = (S_038014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
744 S_038014_LAST_ARRAY(state
->u
.tex
.last_layer
));
745 if (texture
->nr_samples
> 1) {
746 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
747 view
->tex_resource_words
[5] |= S_038014_LAST_LEVEL(util_logbase2(texture
->nr_samples
));
749 view
->tex_resource_words
[5] |= S_038014_LAST_LEVEL(last_level
);
751 view
->tex_resource_words
[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE
) |
752 S_038018_MAX_ANISO(4 /* max 16 samples */));
756 static struct pipe_sampler_view
*
757 r600_create_sampler_view(struct pipe_context
*ctx
,
758 struct pipe_resource
*tex
,
759 const struct pipe_sampler_view
*state
)
761 return r600_create_sampler_view_custom(ctx
, tex
, state
,
762 u_minify(tex
->width0
, state
->u
.tex
.first_level
),
763 u_minify(tex
->height0
, state
->u
.tex
.first_level
));
766 static void r600_emit_clip_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
768 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
769 struct pipe_clip_state
*state
= &rctx
->clip_state
.state
;
771 radeon_set_context_reg_seq(cs
, R_028E20_PA_CL_UCP0_X
, 6*4);
772 radeon_emit_array(cs
, (unsigned*)state
, 6*4);
775 static void r600_set_polygon_stipple(struct pipe_context
*ctx
,
776 const struct pipe_poly_stipple
*state
)
780 static void r600_emit_scissor_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
782 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
783 struct r600_scissor_state
*rstate
= &rctx
->scissor
;
784 struct pipe_scissor_state
*state
;
785 bool do_disable_workaround
= false;
790 if (rctx
->b
.chip_class
== R600
&& !rctx
->scissor
.enable
) {
791 tl
= S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
792 br
= S_028244_BR_X(8192) | S_028244_BR_Y(8192);
793 do_disable_workaround
= true;
796 dirty_mask
= rstate
->dirty_mask
;
797 while (dirty_mask
!= 0)
799 i
= u_bit_scan(&dirty_mask
);
801 radeon_set_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
+ offset
, 2);
802 if (!do_disable_workaround
) {
803 state
= &rstate
->scissor
[i
];
804 tl
= S_028240_TL_X(state
->minx
) | S_028240_TL_Y(state
->miny
) |
805 S_028240_WINDOW_OFFSET_DISABLE(1);
806 br
= S_028244_BR_X(state
->maxx
) | S_028244_BR_Y(state
->maxy
);
811 rstate
->dirty_mask
= 0;
812 rstate
->atom
.num_dw
= 0;
815 static void r600_set_scissor_states(struct pipe_context
*ctx
,
817 unsigned num_scissors
,
818 const struct pipe_scissor_state
*state
)
820 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
821 struct r600_scissor_state
*rstate
= &rctx
->scissor
;
824 for (i
= start_slot
; i
< start_slot
+ num_scissors
; i
++)
825 rstate
->scissor
[i
] = state
[i
- start_slot
];
826 rstate
->dirty_mask
|= ((1 << num_scissors
) - 1) << start_slot
;
827 rstate
->atom
.num_dw
= util_bitcount(rstate
->dirty_mask
) * 4;
829 if (rctx
->b
.chip_class
== R600
&& !rstate
->enable
)
832 r600_mark_atom_dirty(rctx
, &rstate
->atom
);
835 static struct r600_resource
*r600_buffer_create_helper(struct r600_screen
*rscreen
,
836 unsigned size
, unsigned alignment
)
838 struct pipe_resource buffer
;
840 memset(&buffer
, 0, sizeof buffer
);
841 buffer
.target
= PIPE_BUFFER
;
842 buffer
.format
= PIPE_FORMAT_R8_UNORM
;
843 buffer
.bind
= PIPE_BIND_CUSTOM
;
844 buffer
.usage
= PIPE_USAGE_DEFAULT
;
846 buffer
.width0
= size
;
849 buffer
.array_size
= 1;
851 return (struct r600_resource
*)
852 r600_buffer_create(&rscreen
->b
.b
, &buffer
, alignment
);
855 static void r600_init_color_surface(struct r600_context
*rctx
,
856 struct r600_surface
*surf
,
857 bool force_cmask_fmask
)
859 struct r600_screen
*rscreen
= rctx
->screen
;
860 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
861 unsigned level
= surf
->base
.u
.tex
.level
;
862 unsigned pitch
, slice
;
865 unsigned format
, swap
, ntype
, endian
;
867 const struct util_format_description
*desc
;
869 bool blend_bypass
= 0, blend_clamp
= 1;
871 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
&& !r600_can_read_depth(rtex
)) {
872 r600_init_flushed_depth_texture(&rctx
->b
.b
, surf
->base
.texture
, NULL
);
873 rtex
= rtex
->flushed_depth_texture
;
877 offset
= rtex
->surface
.level
[level
].offset
;
878 if (rtex
->surface
.level
[level
].mode
== RADEON_SURF_MODE_LINEAR
) {
879 assert(surf
->base
.u
.tex
.first_layer
== surf
->base
.u
.tex
.last_layer
);
880 offset
+= rtex
->surface
.level
[level
].slice_size
*
881 surf
->base
.u
.tex
.first_layer
;
884 color_view
= S_028080_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
885 S_028080_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
887 pitch
= rtex
->surface
.level
[level
].nblk_x
/ 8 - 1;
888 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
893 switch (rtex
->surface
.level
[level
].mode
) {
894 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
895 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED
);
897 case RADEON_SURF_MODE_1D
:
898 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1
);
900 case RADEON_SURF_MODE_2D
:
901 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1
);
903 case RADEON_SURF_MODE_LINEAR
:
905 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL
);
909 desc
= util_format_description(surf
->base
.format
);
911 for (i
= 0; i
< 4; i
++) {
912 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
917 ntype
= V_0280A0_NUMBER_UNORM
;
918 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
919 ntype
= V_0280A0_NUMBER_SRGB
;
920 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
921 if (desc
->channel
[i
].normalized
)
922 ntype
= V_0280A0_NUMBER_SNORM
;
923 else if (desc
->channel
[i
].pure_integer
)
924 ntype
= V_0280A0_NUMBER_SINT
;
925 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
926 if (desc
->channel
[i
].normalized
)
927 ntype
= V_0280A0_NUMBER_UNORM
;
928 else if (desc
->channel
[i
].pure_integer
)
929 ntype
= V_0280A0_NUMBER_UINT
;
932 format
= r600_translate_colorformat(rctx
->b
.chip_class
, surf
->base
.format
);
933 assert(format
!= ~0);
935 swap
= r600_translate_colorswap(surf
->base
.format
);
938 endian
= r600_colorformat_endian_swap(format
);
940 /* set blend bypass according to docs if SINT/UINT or
941 8/24 COLOR variants */
942 if (ntype
== V_0280A0_NUMBER_UINT
|| ntype
== V_0280A0_NUMBER_SINT
||
943 format
== V_0280A0_COLOR_8_24
|| format
== V_0280A0_COLOR_24_8
||
944 format
== V_0280A0_COLOR_X24_8_32_FLOAT
) {
949 surf
->alphatest_bypass
= ntype
== V_0280A0_NUMBER_UINT
|| ntype
== V_0280A0_NUMBER_SINT
;
951 color_info
|= S_0280A0_FORMAT(format
) |
952 S_0280A0_COMP_SWAP(swap
) |
953 S_0280A0_BLEND_BYPASS(blend_bypass
) |
954 S_0280A0_BLEND_CLAMP(blend_clamp
) |
955 S_0280A0_NUMBER_TYPE(ntype
) |
956 S_0280A0_ENDIAN(endian
);
958 /* EXPORT_NORM is an optimzation that can be enabled for better
959 * performance in certain cases
961 if (rctx
->b
.chip_class
== R600
) {
962 /* EXPORT_NORM can be enabled if:
963 * - 11-bit or smaller UNORM/SNORM/SRGB
964 * - BLEND_CLAMP is enabled
965 * - BLEND_FLOAT32 is disabled
967 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
968 (desc
->channel
[i
].size
< 12 &&
969 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
970 ntype
!= V_0280A0_NUMBER_UINT
&&
971 ntype
!= V_0280A0_NUMBER_SINT
) &&
972 G_0280A0_BLEND_CLAMP(color_info
) &&
973 !G_0280A0_BLEND_FLOAT32(color_info
)) {
974 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
975 surf
->export_16bpc
= true;
978 /* EXPORT_NORM can be enabled if:
979 * - 11-bit or smaller UNORM/SNORM/SRGB
980 * - 16-bit or smaller FLOAT
982 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
983 ((desc
->channel
[i
].size
< 12 &&
984 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
985 ntype
!= V_0280A0_NUMBER_UINT
&& ntype
!= V_0280A0_NUMBER_SINT
) ||
986 (desc
->channel
[i
].size
< 17 &&
987 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
988 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
989 surf
->export_16bpc
= true;
993 /* These might not always be initialized to zero. */
994 surf
->cb_color_base
= offset
>> 8;
995 surf
->cb_color_size
= S_028060_PITCH_TILE_MAX(pitch
) |
996 S_028060_SLICE_TILE_MAX(slice
);
997 surf
->cb_color_fmask
= surf
->cb_color_base
;
998 surf
->cb_color_cmask
= surf
->cb_color_base
;
999 surf
->cb_color_mask
= 0;
1001 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
,
1002 &rtex
->resource
.b
.b
);
1003 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
,
1004 &rtex
->resource
.b
.b
);
1006 if (rtex
->cmask
.size
) {
1007 surf
->cb_color_cmask
= rtex
->cmask
.offset
>> 8;
1008 surf
->cb_color_mask
|= S_028100_CMASK_BLOCK_MAX(rtex
->cmask
.slice_tile_max
);
1010 if (rtex
->fmask
.size
) {
1011 color_info
|= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE
);
1012 surf
->cb_color_fmask
= rtex
->fmask
.offset
>> 8;
1013 surf
->cb_color_mask
|= S_028100_FMASK_TILE_MAX(rtex
->fmask
.slice_tile_max
);
1014 } else { /* cmask only */
1015 color_info
|= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE
);
1017 } else if (force_cmask_fmask
) {
1018 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1020 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1021 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1022 * because it's not an MSAA buffer.
1024 struct r600_cmask_info cmask
;
1025 struct r600_fmask_info fmask
;
1027 r600_texture_get_cmask_info(&rscreen
->b
, rtex
, &cmask
);
1028 r600_texture_get_fmask_info(&rscreen
->b
, rtex
, 8, &fmask
);
1031 if (!rctx
->dummy_cmask
||
1032 rctx
->dummy_cmask
->b
.b
.width0
< cmask
.size
||
1033 rctx
->dummy_cmask
->buf
->alignment
% cmask
.alignment
!= 0) {
1034 struct pipe_transfer
*transfer
;
1037 pipe_resource_reference((struct pipe_resource
**)&rctx
->dummy_cmask
, NULL
);
1038 rctx
->dummy_cmask
= r600_buffer_create_helper(rscreen
, cmask
.size
, cmask
.alignment
);
1040 /* Set the contents to 0xCC. */
1041 ptr
= pipe_buffer_map(&rctx
->b
.b
, &rctx
->dummy_cmask
->b
.b
, PIPE_TRANSFER_WRITE
, &transfer
);
1042 memset(ptr
, 0xCC, cmask
.size
);
1043 pipe_buffer_unmap(&rctx
->b
.b
, transfer
);
1045 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
,
1046 &rctx
->dummy_cmask
->b
.b
);
1049 if (!rctx
->dummy_fmask
||
1050 rctx
->dummy_fmask
->b
.b
.width0
< fmask
.size
||
1051 rctx
->dummy_fmask
->buf
->alignment
% fmask
.alignment
!= 0) {
1052 pipe_resource_reference((struct pipe_resource
**)&rctx
->dummy_fmask
, NULL
);
1053 rctx
->dummy_fmask
= r600_buffer_create_helper(rscreen
, fmask
.size
, fmask
.alignment
);
1056 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
,
1057 &rctx
->dummy_fmask
->b
.b
);
1059 /* Init the registers. */
1060 color_info
|= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE
);
1061 surf
->cb_color_cmask
= 0;
1062 surf
->cb_color_fmask
= 0;
1063 surf
->cb_color_mask
= S_028100_CMASK_BLOCK_MAX(cmask
.slice_tile_max
) |
1064 S_028100_FMASK_TILE_MAX(fmask
.slice_tile_max
);
1067 surf
->cb_color_info
= color_info
;
1068 surf
->cb_color_view
= color_view
;
1069 surf
->color_initialized
= true;
1072 static void r600_init_depth_surface(struct r600_context
*rctx
,
1073 struct r600_surface
*surf
)
1075 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1076 unsigned level
, pitch
, slice
, format
, offset
, array_mode
;
1078 level
= surf
->base
.u
.tex
.level
;
1079 offset
= rtex
->surface
.level
[level
].offset
;
1080 pitch
= rtex
->surface
.level
[level
].nblk_x
/ 8 - 1;
1081 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1085 switch (rtex
->surface
.level
[level
].mode
) {
1086 case RADEON_SURF_MODE_2D
:
1087 array_mode
= V_0280A0_ARRAY_2D_TILED_THIN1
;
1089 case RADEON_SURF_MODE_1D
:
1090 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1091 case RADEON_SURF_MODE_LINEAR
:
1093 array_mode
= V_0280A0_ARRAY_1D_TILED_THIN1
;
1097 format
= r600_translate_dbformat(surf
->base
.format
);
1098 assert(format
!= ~0);
1100 surf
->db_depth_info
= S_028010_ARRAY_MODE(array_mode
) | S_028010_FORMAT(format
);
1101 surf
->db_depth_base
= offset
>> 8;
1102 surf
->db_depth_view
= S_028004_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1103 S_028004_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1104 surf
->db_depth_size
= S_028000_PITCH_TILE_MAX(pitch
) | S_028000_SLICE_TILE_MAX(slice
);
1105 surf
->db_prefetch_limit
= (rtex
->surface
.level
[level
].nblk_y
/ 8) - 1;
1107 switch (surf
->base
.format
) {
1108 case PIPE_FORMAT_Z24X8_UNORM
:
1109 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1110 surf
->pa_su_poly_offset_db_fmt_cntl
=
1111 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1113 case PIPE_FORMAT_Z32_FLOAT
:
1114 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1115 surf
->pa_su_poly_offset_db_fmt_cntl
=
1116 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1117 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1119 case PIPE_FORMAT_Z16_UNORM
:
1120 surf
->pa_su_poly_offset_db_fmt_cntl
=
1121 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1126 /* use htile only for first level */
1127 if (rtex
->htile_buffer
&& !level
) {
1128 surf
->db_htile_data_base
= 0;
1129 surf
->db_htile_surface
= S_028D24_HTILE_WIDTH(1) |
1130 S_028D24_HTILE_HEIGHT(1) |
1131 S_028D24_FULL_CACHE(1);
1132 /* preload is not working properly on r6xx/r7xx */
1133 surf
->db_depth_info
|= S_028010_TILE_SURFACE_ENABLE(1);
1136 surf
->depth_initialized
= true;
1139 static void r600_set_framebuffer_state(struct pipe_context
*ctx
,
1140 const struct pipe_framebuffer_state
*state
)
1142 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1143 struct r600_surface
*surf
;
1144 struct r600_texture
*rtex
;
1147 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1148 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
1149 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_CB
|
1150 R600_CONTEXT_FLUSH_AND_INV_CB_META
;
1152 if (rctx
->framebuffer
.state
.zsbuf
) {
1153 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
1154 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_DB
;
1156 rtex
= (struct r600_texture
*)rctx
->framebuffer
.state
.zsbuf
->texture
;
1157 if (rctx
->b
.chip_class
>= R700
&& rtex
->htile_buffer
) {
1158 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_DB_META
;
1162 /* Set the new state. */
1163 util_copy_framebuffer_state(&rctx
->framebuffer
.state
, state
);
1165 rctx
->framebuffer
.export_16bpc
= state
->nr_cbufs
!= 0;
1166 rctx
->framebuffer
.cb0_is_integer
= state
->nr_cbufs
&& state
->cbufs
[0] &&
1167 util_format_is_pure_integer(state
->cbufs
[0]->format
);
1168 rctx
->framebuffer
.compressed_cb_mask
= 0;
1169 rctx
->framebuffer
.is_msaa_resolve
= state
->nr_cbufs
== 2 &&
1170 state
->cbufs
[0] && state
->cbufs
[1] &&
1171 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
1172 state
->cbufs
[1]->texture
->nr_samples
<= 1;
1173 rctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
1176 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
1177 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1178 bool force_cmask_fmask
= rctx
->b
.chip_class
== R600
&&
1179 rctx
->framebuffer
.is_msaa_resolve
&&
1182 surf
= (struct r600_surface
*)state
->cbufs
[i
];
1186 rtex
= (struct r600_texture
*)surf
->base
.texture
;
1187 r600_context_add_resource_size(ctx
, state
->cbufs
[i
]->texture
);
1189 if (!surf
->color_initialized
|| force_cmask_fmask
) {
1190 r600_init_color_surface(rctx
, surf
, force_cmask_fmask
);
1191 if (force_cmask_fmask
) {
1192 /* re-initialize later without compression */
1193 surf
->color_initialized
= false;
1197 if (!surf
->export_16bpc
) {
1198 rctx
->framebuffer
.export_16bpc
= false;
1201 if (rtex
->fmask
.size
&& rtex
->cmask
.size
) {
1202 rctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
1206 /* Update alpha-test state dependencies.
1207 * Alpha-test is done on the first colorbuffer only. */
1208 if (state
->nr_cbufs
) {
1209 bool alphatest_bypass
= false;
1211 surf
= (struct r600_surface
*)state
->cbufs
[0];
1213 alphatest_bypass
= surf
->alphatest_bypass
;
1216 if (rctx
->alphatest_state
.bypass
!= alphatest_bypass
) {
1217 rctx
->alphatest_state
.bypass
= alphatest_bypass
;
1218 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1224 surf
= (struct r600_surface
*)state
->zsbuf
;
1226 r600_context_add_resource_size(ctx
, state
->zsbuf
->texture
);
1228 if (!surf
->depth_initialized
) {
1229 r600_init_depth_surface(rctx
, surf
);
1232 if (state
->zsbuf
->format
!= rctx
->poly_offset_state
.zs_format
) {
1233 rctx
->poly_offset_state
.zs_format
= state
->zsbuf
->format
;
1234 r600_mark_atom_dirty(rctx
, &rctx
->poly_offset_state
.atom
);
1237 if (rctx
->db_state
.rsurf
!= surf
) {
1238 rctx
->db_state
.rsurf
= surf
;
1239 r600_mark_atom_dirty(rctx
, &rctx
->db_state
.atom
);
1240 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1242 } else if (rctx
->db_state
.rsurf
) {
1243 rctx
->db_state
.rsurf
= NULL
;
1244 r600_mark_atom_dirty(rctx
, &rctx
->db_state
.atom
);
1245 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1248 if (rctx
->cb_misc_state
.nr_cbufs
!= state
->nr_cbufs
) {
1249 rctx
->cb_misc_state
.nr_cbufs
= state
->nr_cbufs
;
1250 r600_mark_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1253 if (state
->nr_cbufs
== 0 && rctx
->alphatest_state
.bypass
) {
1254 rctx
->alphatest_state
.bypass
= false;
1255 r600_mark_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1258 /* Calculate the CS size. */
1259 rctx
->framebuffer
.atom
.num_dw
=
1260 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1262 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1263 rctx
->framebuffer
.atom
.num_dw
+= 15 * rctx
->framebuffer
.state
.nr_cbufs
;
1264 rctx
->framebuffer
.atom
.num_dw
+= 3 * (2 + rctx
->framebuffer
.state
.nr_cbufs
);
1266 if (rctx
->framebuffer
.state
.zsbuf
) {
1267 rctx
->framebuffer
.atom
.num_dw
+= 16;
1268 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1269 rctx
->framebuffer
.atom
.num_dw
+= 3;
1271 if (rctx
->b
.family
> CHIP_R600
&& rctx
->b
.family
< CHIP_RV770
) {
1272 rctx
->framebuffer
.atom
.num_dw
+= 2;
1275 r600_mark_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
1277 r600_set_sample_locations_constant_buffer(rctx
);
1280 static uint32_t sample_locs_2x
[] = {
1281 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1282 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1284 static unsigned max_dist_2x
= 4;
1286 static uint32_t sample_locs_4x
[] = {
1287 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1288 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1290 static unsigned max_dist_4x
= 6;
1291 static uint32_t sample_locs_8x
[] = {
1292 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1293 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1295 static unsigned max_dist_8x
= 7;
1297 static void r600_get_sample_position(struct pipe_context
*ctx
,
1298 unsigned sample_count
,
1299 unsigned sample_index
,
1306 switch (sample_count
) {
1309 out_value
[0] = out_value
[1] = 0.5;
1312 offset
= 4 * (sample_index
* 2);
1313 val
.idx
= (sample_locs_2x
[0] >> offset
) & 0xf;
1314 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1315 val
.idx
= (sample_locs_2x
[0] >> (offset
+ 4)) & 0xf;
1316 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1319 offset
= 4 * (sample_index
* 2);
1320 val
.idx
= (sample_locs_4x
[0] >> offset
) & 0xf;
1321 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1322 val
.idx
= (sample_locs_4x
[0] >> (offset
+ 4)) & 0xf;
1323 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1326 offset
= 4 * (sample_index
% 4 * 2);
1327 index
= (sample_index
/ 4);
1328 val
.idx
= (sample_locs_8x
[index
] >> offset
) & 0xf;
1329 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1330 val
.idx
= (sample_locs_8x
[index
] >> (offset
+ 4)) & 0xf;
1331 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1336 static void r600_emit_msaa_state(struct r600_context
*rctx
, int nr_samples
)
1338 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1339 unsigned max_dist
= 0;
1341 if (rctx
->b
.family
== CHIP_R600
) {
1342 switch (nr_samples
) {
1347 radeon_set_config_reg(cs
, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S
, sample_locs_2x
[0]);
1348 max_dist
= max_dist_2x
;
1351 radeon_set_config_reg(cs
, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S
, sample_locs_4x
[0]);
1352 max_dist
= max_dist_4x
;
1355 radeon_set_config_reg_seq(cs
, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0
, 2);
1356 radeon_emit(cs
, sample_locs_8x
[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1357 radeon_emit(cs
, sample_locs_8x
[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1358 max_dist
= max_dist_8x
;
1362 switch (nr_samples
) {
1364 radeon_set_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1365 radeon_emit(cs
, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1366 radeon_emit(cs
, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1370 radeon_set_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1371 radeon_emit(cs
, sample_locs_2x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1372 radeon_emit(cs
, sample_locs_2x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1373 max_dist
= max_dist_2x
;
1376 radeon_set_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1377 radeon_emit(cs
, sample_locs_4x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1378 radeon_emit(cs
, sample_locs_4x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1379 max_dist
= max_dist_4x
;
1382 radeon_set_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1383 radeon_emit(cs
, sample_locs_8x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1384 radeon_emit(cs
, sample_locs_8x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1385 max_dist
= max_dist_8x
;
1390 if (nr_samples
> 1) {
1391 radeon_set_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1392 radeon_emit(cs
, S_028C00_LAST_PIXEL(1) |
1393 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1394 radeon_emit(cs
, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples
)) |
1395 S_028C04_MAX_SAMPLE_DIST(max_dist
)); /* R_028C04_PA_SC_AA_CONFIG */
1397 radeon_set_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1398 radeon_emit(cs
, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1399 radeon_emit(cs
, 0); /* R_028C04_PA_SC_AA_CONFIG */
1403 static void r600_emit_framebuffer_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1405 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1406 struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
.state
;
1407 unsigned nr_cbufs
= state
->nr_cbufs
;
1408 struct r600_surface
**cb
= (struct r600_surface
**)&state
->cbufs
[0];
1409 unsigned i
, sbu
= 0;
1412 radeon_set_context_reg_seq(cs
, R_0280A0_CB_COLOR0_INFO
, 8);
1413 for (i
= 0; i
< nr_cbufs
; i
++) {
1414 radeon_emit(cs
, cb
[i
] ? cb
[i
]->cb_color_info
: 0);
1416 /* set CB_COLOR1_INFO for possible dual-src blending */
1417 if (i
== 1 && cb
[0]) {
1418 radeon_emit(cs
, cb
[0]->cb_color_info
);
1421 for (; i
< 8; i
++) {
1426 for (i
= 0; i
< nr_cbufs
; i
++) {
1433 radeon_set_context_reg(cs
, R_028040_CB_COLOR0_BASE
+ i
*4, cb
[i
]->cb_color_base
);
1435 reloc
= radeon_add_to_buffer_list(&rctx
->b
,
1437 (struct r600_resource
*)cb
[i
]->base
.texture
,
1438 RADEON_USAGE_READWRITE
,
1439 cb
[i
]->base
.texture
->nr_samples
> 1 ?
1440 RADEON_PRIO_COLOR_BUFFER_MSAA
:
1441 RADEON_PRIO_COLOR_BUFFER
);
1442 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1443 radeon_emit(cs
, reloc
);
1446 radeon_set_context_reg(cs
, R_0280E0_CB_COLOR0_FRAG
+ i
*4, cb
[i
]->cb_color_fmask
);
1448 reloc
= radeon_add_to_buffer_list(&rctx
->b
,
1450 cb
[i
]->cb_buffer_fmask
,
1451 RADEON_USAGE_READWRITE
,
1452 cb
[i
]->base
.texture
->nr_samples
> 1 ?
1453 RADEON_PRIO_COLOR_BUFFER_MSAA
:
1454 RADEON_PRIO_COLOR_BUFFER
);
1455 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1456 radeon_emit(cs
, reloc
);
1459 radeon_set_context_reg(cs
, R_0280C0_CB_COLOR0_TILE
+ i
*4, cb
[i
]->cb_color_cmask
);
1461 reloc
= radeon_add_to_buffer_list(&rctx
->b
,
1463 cb
[i
]->cb_buffer_cmask
,
1464 RADEON_USAGE_READWRITE
,
1465 cb
[i
]->base
.texture
->nr_samples
> 1 ?
1466 RADEON_PRIO_COLOR_BUFFER_MSAA
:
1467 RADEON_PRIO_COLOR_BUFFER
);
1468 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1469 radeon_emit(cs
, reloc
);
1472 radeon_set_context_reg_seq(cs
, R_028060_CB_COLOR0_SIZE
, nr_cbufs
);
1473 for (i
= 0; i
< nr_cbufs
; i
++) {
1474 radeon_emit(cs
, cb
[i
] ? cb
[i
]->cb_color_size
: 0);
1477 radeon_set_context_reg_seq(cs
, R_028080_CB_COLOR0_VIEW
, nr_cbufs
);
1478 for (i
= 0; i
< nr_cbufs
; i
++) {
1479 radeon_emit(cs
, cb
[i
] ? cb
[i
]->cb_color_view
: 0);
1482 radeon_set_context_reg_seq(cs
, R_028100_CB_COLOR0_MASK
, nr_cbufs
);
1483 for (i
= 0; i
< nr_cbufs
; i
++) {
1484 radeon_emit(cs
, cb
[i
] ? cb
[i
]->cb_color_mask
: 0);
1487 sbu
|= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs
);
1490 /* SURFACE_BASE_UPDATE */
1491 if (rctx
->b
.family
> CHIP_R600
&& rctx
->b
.family
< CHIP_RV770
&& sbu
) {
1492 radeon_emit(cs
, PKT3(PKT3_SURFACE_BASE_UPDATE
, 0, 0));
1493 radeon_emit(cs
, sbu
);
1499 struct r600_surface
*surf
= (struct r600_surface
*)state
->zsbuf
;
1500 unsigned reloc
= radeon_add_to_buffer_list(&rctx
->b
,
1502 (struct r600_resource
*)state
->zsbuf
->texture
,
1503 RADEON_USAGE_READWRITE
,
1504 surf
->base
.texture
->nr_samples
> 1 ?
1505 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
1506 RADEON_PRIO_DEPTH_BUFFER
);
1508 radeon_set_context_reg(cs
, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1509 surf
->pa_su_poly_offset_db_fmt_cntl
);
1511 radeon_set_context_reg_seq(cs
, R_028000_DB_DEPTH_SIZE
, 2);
1512 radeon_emit(cs
, surf
->db_depth_size
); /* R_028000_DB_DEPTH_SIZE */
1513 radeon_emit(cs
, surf
->db_depth_view
); /* R_028004_DB_DEPTH_VIEW */
1514 radeon_set_context_reg_seq(cs
, R_02800C_DB_DEPTH_BASE
, 2);
1515 radeon_emit(cs
, surf
->db_depth_base
); /* R_02800C_DB_DEPTH_BASE */
1516 radeon_emit(cs
, surf
->db_depth_info
); /* R_028010_DB_DEPTH_INFO */
1518 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1519 radeon_emit(cs
, reloc
);
1521 radeon_set_context_reg(cs
, R_028D34_DB_PREFETCH_LIMIT
, surf
->db_prefetch_limit
);
1523 sbu
|= SURFACE_BASE_UPDATE_DEPTH
;
1524 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1525 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1526 * Older kernels are out of luck. */
1527 radeon_set_context_reg(cs
, R_028010_DB_DEPTH_INFO
, S_028010_FORMAT(V_028010_DEPTH_INVALID
));
1530 /* SURFACE_BASE_UPDATE */
1531 if (rctx
->b
.family
> CHIP_R600
&& rctx
->b
.family
< CHIP_RV770
&& sbu
) {
1532 radeon_emit(cs
, PKT3(PKT3_SURFACE_BASE_UPDATE
, 0, 0));
1533 radeon_emit(cs
, sbu
);
1537 /* Framebuffer dimensions. */
1538 radeon_set_context_reg_seq(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, 2);
1539 radeon_emit(cs
, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1540 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1541 radeon_emit(cs
, S_028244_BR_X(state
->width
) |
1542 S_028244_BR_Y(state
->height
)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1544 if (rctx
->framebuffer
.is_msaa_resolve
) {
1545 radeon_set_context_reg(cs
, R_0287A0_CB_SHADER_CONTROL
, 1);
1547 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1548 * will assure that the alpha-test will work even if there is
1549 * no colorbuffer bound. */
1550 radeon_set_context_reg(cs
, R_0287A0_CB_SHADER_CONTROL
,
1551 (1ull << MAX2(nr_cbufs
, 1)) - 1);
1554 r600_emit_msaa_state(rctx
, rctx
->framebuffer
.nr_samples
);
1557 static void r600_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
1559 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1561 if (rctx
->ps_iter_samples
== min_samples
)
1564 rctx
->ps_iter_samples
= min_samples
;
1565 if (rctx
->framebuffer
.nr_samples
> 1) {
1566 r600_mark_atom_dirty(rctx
, &rctx
->rasterizer_state
.atom
);
1567 if (rctx
->b
.chip_class
== R600
)
1568 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
1572 static void r600_emit_cb_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1574 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1575 struct r600_cb_misc_state
*a
= (struct r600_cb_misc_state
*)atom
;
1577 if (G_028808_SPECIAL_OP(a
->cb_color_control
) == V_028808_SPECIAL_RESOLVE_BOX
) {
1578 radeon_set_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1579 if (rctx
->b
.chip_class
== R600
) {
1580 radeon_emit(cs
, 0xff); /* R_028238_CB_TARGET_MASK */
1581 radeon_emit(cs
, 0xff); /* R_02823C_CB_SHADER_MASK */
1583 radeon_emit(cs
, 0xf); /* R_028238_CB_TARGET_MASK */
1584 radeon_emit(cs
, 0xf); /* R_02823C_CB_SHADER_MASK */
1586 radeon_set_context_reg(cs
, R_028808_CB_COLOR_CONTROL
, a
->cb_color_control
);
1588 unsigned fb_colormask
= (1ULL << ((unsigned)a
->nr_cbufs
* 4)) - 1;
1589 unsigned ps_colormask
= (1ULL << ((unsigned)a
->nr_ps_color_outputs
* 4)) - 1;
1590 unsigned multiwrite
= a
->multiwrite
&& a
->nr_cbufs
> 1;
1592 radeon_set_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1593 radeon_emit(cs
, a
->blend_colormask
& fb_colormask
); /* R_028238_CB_TARGET_MASK */
1594 /* Always enable the first color output to make sure alpha-test works even without one. */
1595 radeon_emit(cs
, 0xf | (multiwrite
? fb_colormask
: ps_colormask
)); /* R_02823C_CB_SHADER_MASK */
1596 radeon_set_context_reg(cs
, R_028808_CB_COLOR_CONTROL
,
1597 a
->cb_color_control
|
1598 S_028808_MULTIWRITE_ENABLE(multiwrite
));
1602 static void r600_emit_db_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1604 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1605 struct r600_db_state
*a
= (struct r600_db_state
*)atom
;
1607 if (a
->rsurf
&& a
->rsurf
->db_htile_surface
) {
1608 struct r600_texture
*rtex
= (struct r600_texture
*)a
->rsurf
->base
.texture
;
1611 radeon_set_context_reg(cs
, R_02802C_DB_DEPTH_CLEAR
, fui(rtex
->depth_clear_value
));
1612 radeon_set_context_reg(cs
, R_028D24_DB_HTILE_SURFACE
, a
->rsurf
->db_htile_surface
);
1613 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, a
->rsurf
->db_htile_data_base
);
1614 reloc_idx
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rtex
->htile_buffer
,
1615 RADEON_USAGE_READWRITE
, RADEON_PRIO_HTILE
);
1616 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1617 cs
->buf
[cs
->cdw
++] = reloc_idx
;
1619 radeon_set_context_reg(cs
, R_028D24_DB_HTILE_SURFACE
, 0);
1623 static void r600_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1625 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1626 struct r600_db_misc_state
*a
= (struct r600_db_misc_state
*)atom
;
1627 unsigned db_render_control
= 0;
1628 unsigned db_render_override
=
1629 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE
) |
1630 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE
);
1632 if (rctx
->b
.chip_class
>= R700
) {
1633 switch (a
->ps_conservative_z
) {
1634 default: /* fall through */
1635 case TGSI_FS_DEPTH_LAYOUT_ANY
:
1636 db_render_control
|= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_ANY_Z
);
1638 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
1639 db_render_control
|= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_GREATER_THAN_Z
);
1641 case TGSI_FS_DEPTH_LAYOUT_LESS
:
1642 db_render_control
|= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_LESS_THAN_Z
);
1647 if (a
->occlusion_query_enabled
) {
1648 if (rctx
->b
.chip_class
>= R700
) {
1649 db_render_control
|= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1651 db_render_override
|= S_028D10_NOOP_CULL_DISABLE(1);
1653 if (rctx
->db_state
.rsurf
&& rctx
->db_state
.rsurf
->db_htile_surface
) {
1654 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1655 db_render_override
|= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF
);
1656 /* This is to fix a lockup when hyperz and alpha test are enabled at
1657 * the same time somehow GPU get confuse on which order to pick for
1660 if (rctx
->alphatest_state
.sx_alpha_test_control
) {
1661 db_render_override
|= S_028D10_FORCE_SHADER_Z_ORDER(1);
1664 db_render_override
|= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE
);
1666 if (rctx
->b
.chip_class
== R600
&& rctx
->framebuffer
.nr_samples
> 1 && rctx
->ps_iter_samples
> 0) {
1667 /* sample shading and hyperz causes lockups on R6xx chips */
1668 db_render_override
|= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE
);
1670 if (a
->flush_depthstencil_through_cb
) {
1671 assert(a
->copy_depth
|| a
->copy_stencil
);
1673 db_render_control
|= S_028D0C_DEPTH_COPY_ENABLE(a
->copy_depth
) |
1674 S_028D0C_STENCIL_COPY_ENABLE(a
->copy_stencil
) |
1675 S_028D0C_COPY_CENTROID(1) |
1676 S_028D0C_COPY_SAMPLE(a
->copy_sample
);
1678 if (rctx
->b
.chip_class
== R600
)
1679 db_render_override
|= S_028D10_NOOP_CULL_DISABLE(1);
1681 if (rctx
->b
.family
== CHIP_RV610
|| rctx
->b
.family
== CHIP_RV630
||
1682 rctx
->b
.family
== CHIP_RV620
|| rctx
->b
.family
== CHIP_RV635
)
1683 db_render_override
|= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE
);
1684 } else if (a
->flush_depth_inplace
|| a
->flush_stencil_inplace
) {
1685 db_render_control
|= S_028D0C_DEPTH_COMPRESS_DISABLE(a
->flush_depth_inplace
) |
1686 S_028D0C_STENCIL_COMPRESS_DISABLE(a
->flush_stencil_inplace
);
1687 db_render_override
|= S_028D10_NOOP_CULL_DISABLE(1);
1689 if (a
->htile_clear
) {
1690 db_render_control
|= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1693 /* RV770 workaround for a hang with 8x MSAA. */
1694 if (rctx
->b
.family
== CHIP_RV770
&& a
->log_samples
== 3) {
1695 db_render_override
|= S_028D10_MAX_TILES_IN_DTT(6);
1698 radeon_set_context_reg_seq(cs
, R_028D0C_DB_RENDER_CONTROL
, 2);
1699 radeon_emit(cs
, db_render_control
); /* R_028D0C_DB_RENDER_CONTROL */
1700 radeon_emit(cs
, db_render_override
); /* R_028D10_DB_RENDER_OVERRIDE */
1701 radeon_set_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
, a
->db_shader_control
);
1704 static void r600_emit_config_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1706 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1707 struct r600_config_state
*a
= (struct r600_config_state
*)atom
;
1709 radeon_set_config_reg(cs
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, a
->sq_gpr_resource_mgmt_1
);
1710 radeon_set_config_reg(cs
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, a
->sq_gpr_resource_mgmt_2
);
1713 static void r600_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1715 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1716 uint32_t dirty_mask
= rctx
->vertex_buffer_state
.dirty_mask
;
1718 while (dirty_mask
) {
1719 struct pipe_vertex_buffer
*vb
;
1720 struct r600_resource
*rbuffer
;
1722 unsigned buffer_index
= u_bit_scan(&dirty_mask
);
1724 vb
= &rctx
->vertex_buffer_state
.vb
[buffer_index
];
1725 rbuffer
= (struct r600_resource
*)vb
->buffer
;
1728 offset
= vb
->buffer_offset
;
1730 /* fetch resources start at index 320 (OFFSET_FS) */
1731 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1732 radeon_emit(cs
, (R600_FETCH_CONSTANTS_OFFSET_FS
+ buffer_index
) * 7);
1733 radeon_emit(cs
, offset
); /* RESOURCEi_WORD0 */
1734 radeon_emit(cs
, rbuffer
->b
.b
.width0
- offset
- 1); /* RESOURCEi_WORD1 */
1735 radeon_emit(cs
, /* RESOURCEi_WORD2 */
1736 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1737 S_038008_STRIDE(vb
->stride
));
1738 radeon_emit(cs
, 0); /* RESOURCEi_WORD3 */
1739 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
1740 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
1741 radeon_emit(cs
, 0xc0000000); /* RESOURCEi_WORD6 */
1743 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1744 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
1745 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
));
1749 static void r600_emit_constant_buffers(struct r600_context
*rctx
,
1750 struct r600_constbuf_state
*state
,
1751 unsigned buffer_id_base
,
1752 unsigned reg_alu_constbuf_size
,
1753 unsigned reg_alu_const_cache
)
1755 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1756 uint32_t dirty_mask
= state
->dirty_mask
;
1758 while (dirty_mask
) {
1759 struct pipe_constant_buffer
*cb
;
1760 struct r600_resource
*rbuffer
;
1762 unsigned buffer_index
= ffs(dirty_mask
) - 1;
1763 unsigned gs_ring_buffer
= (buffer_index
== R600_GS_RING_CONST_BUFFER
);
1764 cb
= &state
->cb
[buffer_index
];
1765 rbuffer
= (struct r600_resource
*)cb
->buffer
;
1768 offset
= cb
->buffer_offset
;
1770 if (!gs_ring_buffer
) {
1771 radeon_set_context_reg(cs
, reg_alu_constbuf_size
+ buffer_index
* 4,
1772 DIV_ROUND_UP(cb
->buffer_size
, 256));
1773 radeon_set_context_reg(cs
, reg_alu_const_cache
+ buffer_index
* 4, offset
>> 8);
1776 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1777 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
1778 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
));
1780 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1781 radeon_emit(cs
, (buffer_id_base
+ buffer_index
) * 7);
1782 radeon_emit(cs
, offset
); /* RESOURCEi_WORD0 */
1783 radeon_emit(cs
, rbuffer
->b
.b
.width0
- offset
- 1); /* RESOURCEi_WORD1 */
1784 radeon_emit(cs
, /* RESOURCEi_WORD2 */
1785 S_038008_ENDIAN_SWAP(gs_ring_buffer
? ENDIAN_NONE
: r600_endian_swap(32)) |
1786 S_038008_STRIDE(gs_ring_buffer
? 4 : 16));
1787 radeon_emit(cs
, 0); /* RESOURCEi_WORD3 */
1788 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
1789 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
1790 radeon_emit(cs
, 0xc0000000); /* RESOURCEi_WORD6 */
1792 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1793 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
1794 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
));
1796 dirty_mask
&= ~(1 << buffer_index
);
1798 state
->dirty_mask
= 0;
1801 static void r600_emit_vs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1803 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
],
1804 R600_FETCH_CONSTANTS_OFFSET_VS
,
1805 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
1806 R_028980_ALU_CONST_CACHE_VS_0
);
1809 static void r600_emit_gs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1811 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
],
1812 R600_FETCH_CONSTANTS_OFFSET_GS
,
1813 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
,
1814 R_0289C0_ALU_CONST_CACHE_GS_0
);
1817 static void r600_emit_ps_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1819 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
],
1820 R600_FETCH_CONSTANTS_OFFSET_PS
,
1821 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
1822 R_028940_ALU_CONST_CACHE_PS_0
);
1825 static void r600_emit_sampler_views(struct r600_context
*rctx
,
1826 struct r600_samplerview_state
*state
,
1827 unsigned resource_id_base
)
1829 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1830 uint32_t dirty_mask
= state
->dirty_mask
;
1832 while (dirty_mask
) {
1833 struct r600_pipe_sampler_view
*rview
;
1834 unsigned resource_index
= u_bit_scan(&dirty_mask
);
1837 rview
= state
->views
[resource_index
];
1840 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1841 radeon_emit(cs
, (resource_id_base
+ resource_index
) * 7);
1842 radeon_emit_array(cs
, rview
->tex_resource_words
, 7);
1844 reloc
= radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rview
->tex_resource
,
1846 r600_get_sampler_view_priority(rview
->tex_resource
));
1847 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1848 radeon_emit(cs
, reloc
);
1849 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1850 radeon_emit(cs
, reloc
);
1852 state
->dirty_mask
= 0;
1856 static void r600_emit_vs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
1858 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
, R600_FETCH_CONSTANTS_OFFSET_VS
+ R600_MAX_CONST_BUFFERS
);
1861 static void r600_emit_gs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
1863 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
, R600_FETCH_CONSTANTS_OFFSET_GS
+ R600_MAX_CONST_BUFFERS
);
1866 static void r600_emit_ps_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
1868 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
, R600_FETCH_CONSTANTS_OFFSET_PS
+ R600_MAX_CONST_BUFFERS
);
1871 static void r600_emit_sampler_states(struct r600_context
*rctx
,
1872 struct r600_textures_info
*texinfo
,
1873 unsigned resource_id_base
,
1874 unsigned border_color_reg
)
1876 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1877 uint32_t dirty_mask
= texinfo
->states
.dirty_mask
;
1879 while (dirty_mask
) {
1880 struct r600_pipe_sampler_state
*rstate
;
1881 struct r600_pipe_sampler_view
*rview
;
1882 unsigned i
= u_bit_scan(&dirty_mask
);
1884 rstate
= texinfo
->states
.states
[i
];
1886 rview
= texinfo
->views
.views
[i
];
1888 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1889 * filtering between layers.
1890 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1893 enum pipe_texture_target target
= rview
->base
.texture
->target
;
1894 if (target
== PIPE_TEXTURE_1D_ARRAY
||
1895 target
== PIPE_TEXTURE_2D_ARRAY
) {
1896 rstate
->tex_sampler_words
[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1897 texinfo
->is_array_sampler
[i
] = true;
1899 rstate
->tex_sampler_words
[0] &= C_03C000_TEX_ARRAY_OVERRIDE
;
1900 texinfo
->is_array_sampler
[i
] = false;
1904 radeon_emit(cs
, PKT3(PKT3_SET_SAMPLER
, 3, 0));
1905 radeon_emit(cs
, (resource_id_base
+ i
) * 3);
1906 radeon_emit_array(cs
, rstate
->tex_sampler_words
, 3);
1908 if (rstate
->border_color_use
) {
1911 offset
= border_color_reg
;
1913 radeon_set_config_reg_seq(cs
, offset
, 4);
1914 radeon_emit_array(cs
, rstate
->border_color
.ui
, 4);
1917 texinfo
->states
.dirty_mask
= 0;
1920 static void r600_emit_vs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
1922 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED
);
1925 static void r600_emit_gs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
1927 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED
);
1930 static void r600_emit_ps_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
1932 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED
);
1935 static void r600_emit_seamless_cube_map(struct r600_context
*rctx
, struct r600_atom
*atom
)
1937 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1940 tmp
= S_009508_DISABLE_CUBE_ANISO(1) |
1941 S_009508_SYNC_GRADIENT(1) |
1942 S_009508_SYNC_WALKER(1) |
1943 S_009508_SYNC_ALIGNER(1);
1944 if (!rctx
->seamless_cube_map
.enabled
) {
1945 tmp
|= S_009508_DISABLE_CUBE_WRAP(1);
1947 radeon_set_config_reg(cs
, R_009508_TA_CNTL_AUX
, tmp
);
1950 static void r600_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
1952 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
1953 uint8_t mask
= s
->sample_mask
;
1955 radeon_set_context_reg(rctx
->b
.gfx
.cs
, R_028C48_PA_SC_AA_MASK
,
1956 mask
| (mask
<< 8) | (mask
<< 16) | (mask
<< 24));
1959 static void r600_emit_vertex_fetch_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
1961 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1962 struct r600_cso_state
*state
= (struct r600_cso_state
*)a
;
1963 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
->cso
;
1965 radeon_set_context_reg(cs
, R_028894_SQ_PGM_START_FS
, shader
->offset
>> 8);
1966 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1967 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, shader
->buffer
,
1969 RADEON_PRIO_INTERNAL_SHADER
));
1972 static void r600_emit_shader_stages(struct r600_context
*rctx
, struct r600_atom
*a
)
1974 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
1975 struct r600_shader_stages_state
*state
= (struct r600_shader_stages_state
*)a
;
1977 uint32_t v2
= 0, primid
= 0;
1979 if (rctx
->vs_shader
->current
->shader
.vs_as_gs_a
) {
1980 v2
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
1984 if (state
->geom_enable
) {
1987 if (rctx
->gs_shader
->gs_max_out_vertices
<= 128)
1988 cut_val
= V_028A40_GS_CUT_128
;
1989 else if (rctx
->gs_shader
->gs_max_out_vertices
<= 256)
1990 cut_val
= V_028A40_GS_CUT_256
;
1991 else if (rctx
->gs_shader
->gs_max_out_vertices
<= 512)
1992 cut_val
= V_028A40_GS_CUT_512
;
1994 cut_val
= V_028A40_GS_CUT_1024
;
1996 v2
= S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
1997 S_028A40_CUT_MODE(cut_val
);
1999 if (rctx
->gs_shader
->current
->shader
.gs_prim_id_input
)
2003 radeon_set_context_reg(cs
, R_028A40_VGT_GS_MODE
, v2
);
2004 radeon_set_context_reg(cs
, R_028A84_VGT_PRIMITIVEID_EN
, primid
);
2007 static void r600_emit_gs_rings(struct r600_context
*rctx
, struct r600_atom
*a
)
2009 struct radeon_winsys_cs
*cs
= rctx
->b
.gfx
.cs
;
2010 struct r600_gs_rings_state
*state
= (struct r600_gs_rings_state
*)a
;
2011 struct r600_resource
*rbuffer
;
2013 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2014 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2015 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
2017 if (state
->enable
) {
2018 rbuffer
=(struct r600_resource
*)state
->esgs_ring
.buffer
;
2019 radeon_set_config_reg(cs
, R_008C40_SQ_ESGS_RING_BASE
, 0);
2020 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2021 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
2022 RADEON_USAGE_READWRITE
,
2023 RADEON_PRIO_RINGS_STREAMOUT
));
2024 radeon_set_config_reg(cs
, R_008C44_SQ_ESGS_RING_SIZE
,
2025 state
->esgs_ring
.buffer_size
>> 8);
2027 rbuffer
=(struct r600_resource
*)state
->gsvs_ring
.buffer
;
2028 radeon_set_config_reg(cs
, R_008C48_SQ_GSVS_RING_BASE
, 0);
2029 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2030 radeon_emit(cs
, radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.gfx
, rbuffer
,
2031 RADEON_USAGE_READWRITE
,
2032 RADEON_PRIO_RINGS_STREAMOUT
));
2033 radeon_set_config_reg(cs
, R_008C4C_SQ_GSVS_RING_SIZE
,
2034 state
->gsvs_ring
.buffer_size
>> 8);
2036 radeon_set_config_reg(cs
, R_008C44_SQ_ESGS_RING_SIZE
, 0);
2037 radeon_set_config_reg(cs
, R_008C4C_SQ_GSVS_RING_SIZE
, 0);
2040 radeon_set_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
2041 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2042 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
2045 /* Adjust GPR allocation on R6xx/R7xx */
2046 bool r600_adjust_gprs(struct r600_context
*rctx
)
2048 unsigned num_gprs
[R600_NUM_HW_STAGES
];
2049 unsigned new_gprs
[R600_NUM_HW_STAGES
];
2050 unsigned cur_gprs
[R600_NUM_HW_STAGES
];
2051 unsigned def_gprs
[R600_NUM_HW_STAGES
];
2052 unsigned def_num_clause_temp_gprs
= rctx
->r6xx_num_clause_temp_gprs
;
2056 bool need_recalc
= false, use_default
= true;
2058 /* hardware will reserve twice num_clause_temp_gprs */
2059 max_gprs
= def_num_clause_temp_gprs
* 2;
2060 for (i
= 0; i
< R600_NUM_HW_STAGES
; i
++) {
2061 def_gprs
[i
] = rctx
->default_gprs
[i
];
2062 max_gprs
+= def_gprs
[i
];
2065 cur_gprs
[R600_HW_STAGE_PS
] = G_008C04_NUM_PS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_1
);
2066 cur_gprs
[R600_HW_STAGE_VS
] = G_008C04_NUM_VS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_1
);
2067 cur_gprs
[R600_HW_STAGE_GS
] = G_008C08_NUM_GS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_2
);
2068 cur_gprs
[R600_HW_STAGE_ES
] = G_008C08_NUM_ES_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_2
);
2070 num_gprs
[R600_HW_STAGE_PS
] = rctx
->ps_shader
->current
->shader
.bc
.ngpr
;
2071 if (rctx
->gs_shader
) {
2072 num_gprs
[R600_HW_STAGE_ES
] = rctx
->vs_shader
->current
->shader
.bc
.ngpr
;
2073 num_gprs
[R600_HW_STAGE_GS
] = rctx
->gs_shader
->current
->shader
.bc
.ngpr
;
2074 num_gprs
[R600_HW_STAGE_VS
] = rctx
->gs_shader
->current
->gs_copy_shader
->shader
.bc
.ngpr
;
2076 num_gprs
[R600_HW_STAGE_ES
] = 0;
2077 num_gprs
[R600_HW_STAGE_GS
] = 0;
2078 num_gprs
[R600_HW_STAGE_VS
] = rctx
->vs_shader
->current
->shader
.bc
.ngpr
;
2081 for (i
= 0; i
< R600_NUM_HW_STAGES
; i
++) {
2082 new_gprs
[i
] = num_gprs
[i
];
2083 if (new_gprs
[i
] > cur_gprs
[i
])
2085 if (new_gprs
[i
] > def_gprs
[i
])
2086 use_default
= false;
2089 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2093 /* try to use switch back to default */
2095 /* always privilege vs stage so that at worst we have the
2096 * pixel stage producing wrong output (not the vertex
2098 new_gprs
[R600_HW_STAGE_PS
] = max_gprs
- def_num_clause_temp_gprs
* 2;
2099 for (i
= R600_HW_STAGE_VS
; i
< R600_NUM_HW_STAGES
; i
++)
2100 new_gprs
[R600_HW_STAGE_PS
] -= new_gprs
[i
];
2102 for (i
= 0; i
< R600_NUM_HW_STAGES
; i
++)
2103 new_gprs
[i
] = def_gprs
[i
];
2106 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2107 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2108 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2109 * it will lockup. So in this case just discard the draw command
2110 * and don't change the current gprs repartitions.
2112 for (i
= 0; i
< R600_NUM_HW_STAGES
; i
++) {
2113 if (num_gprs
[i
] > new_gprs
[i
]) {
2114 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2115 "for a combined maximum of %d\n",
2116 num_gprs
[R600_HW_STAGE_PS
], num_gprs
[R600_HW_STAGE_VS
], num_gprs
[R600_HW_STAGE_ES
], num_gprs
[R600_HW_STAGE_GS
], max_gprs
);
2121 /* in some case we endup recomputing the current value */
2122 tmp
= S_008C04_NUM_PS_GPRS(new_gprs
[R600_HW_STAGE_PS
]) |
2123 S_008C04_NUM_VS_GPRS(new_gprs
[R600_HW_STAGE_VS
]) |
2124 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs
);
2126 tmp2
= S_008C08_NUM_ES_GPRS(new_gprs
[R600_HW_STAGE_ES
]) |
2127 S_008C08_NUM_GS_GPRS(new_gprs
[R600_HW_STAGE_GS
]);
2128 if (rctx
->config_state
.sq_gpr_resource_mgmt_1
!= tmp
|| rctx
->config_state
.sq_gpr_resource_mgmt_2
!= tmp2
) {
2129 rctx
->config_state
.sq_gpr_resource_mgmt_1
= tmp
;
2130 rctx
->config_state
.sq_gpr_resource_mgmt_2
= tmp2
;
2131 r600_mark_atom_dirty(rctx
, &rctx
->config_state
.atom
);
2132 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
2137 void r600_init_atom_start_cs(struct r600_context
*rctx
)
2152 int num_ps_stack_entries
;
2153 int num_vs_stack_entries
;
2154 int num_gs_stack_entries
;
2155 int num_es_stack_entries
;
2156 enum radeon_family family
;
2157 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2160 r600_init_command_buffer(cb
, 256);
2162 /* R6xx requires this packet at the start of each command buffer */
2163 if (rctx
->b
.chip_class
== R600
) {
2164 r600_store_value(cb
, PKT3(PKT3_START_3D_CMDBUF
, 0, 0));
2165 r600_store_value(cb
, 0);
2167 /* All asics require this one */
2168 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2169 r600_store_value(cb
, 0x80000000);
2170 r600_store_value(cb
, 0x80000000);
2172 /* We're setting config registers here. */
2173 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2174 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2176 family
= rctx
->b
.family
;
2188 num_ps_threads
= 136;
2189 num_vs_threads
= 48;
2192 num_ps_stack_entries
= 128;
2193 num_vs_stack_entries
= 128;
2194 num_gs_stack_entries
= 0;
2195 num_es_stack_entries
= 0;
2204 num_ps_threads
= 144;
2205 num_vs_threads
= 40;
2208 num_ps_stack_entries
= 40;
2209 num_vs_stack_entries
= 40;
2210 num_gs_stack_entries
= 32;
2211 num_es_stack_entries
= 16;
2223 /* use limits 40 VS and at least 16 ES/GS */
2224 num_ps_threads
= 120;
2225 num_vs_threads
= 40;
2226 num_gs_threads
= 16;
2227 num_es_threads
= 16;
2228 num_ps_stack_entries
= 40;
2229 num_vs_stack_entries
= 40;
2230 num_gs_stack_entries
= 32;
2231 num_es_stack_entries
= 16;
2239 num_ps_threads
= 136;
2240 num_vs_threads
= 48;
2243 num_ps_stack_entries
= 40;
2244 num_vs_stack_entries
= 40;
2245 num_gs_stack_entries
= 32;
2246 num_es_stack_entries
= 16;
2254 num_ps_threads
= 180;
2255 num_vs_threads
= 60;
2258 num_ps_stack_entries
= 128;
2259 num_vs_stack_entries
= 128;
2260 num_gs_stack_entries
= 128;
2261 num_es_stack_entries
= 128;
2270 num_ps_threads
= 180;
2271 num_vs_threads
= 60;
2274 num_ps_stack_entries
= 128;
2275 num_vs_stack_entries
= 128;
2276 num_gs_stack_entries
= 0;
2277 num_es_stack_entries
= 0;
2285 num_ps_threads
= 136;
2286 num_vs_threads
= 48;
2289 num_ps_stack_entries
= 128;
2290 num_vs_stack_entries
= 128;
2291 num_gs_stack_entries
= 0;
2292 num_es_stack_entries
= 0;
2296 rctx
->default_gprs
[R600_HW_STAGE_PS
] = num_ps_gprs
;
2297 rctx
->default_gprs
[R600_HW_STAGE_VS
] = num_vs_gprs
;
2298 rctx
->default_gprs
[R600_HW_STAGE_GS
] = 0;
2299 rctx
->default_gprs
[R600_HW_STAGE_ES
] = 0;
2301 rctx
->r6xx_num_clause_temp_gprs
= num_temp_gprs
;
2313 tmp
|= S_008C00_VC_ENABLE(1);
2316 tmp
|= S_008C00_DX9_CONSTS(0);
2317 tmp
|= S_008C00_ALU_INST_PREFER_VECTOR(1);
2318 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2319 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2320 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2321 tmp
|= S_008C00_ES_PRIO(es_prio
);
2322 r600_store_config_reg(cb
, R_008C00_SQ_CONFIG
, tmp
);
2324 /* SQ_GPR_RESOURCE_MGMT_2 */
2325 tmp
= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
2326 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
2327 r600_store_config_reg_seq(cb
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, 4);
2328 r600_store_value(cb
, tmp
);
2330 /* SQ_THREAD_RESOURCE_MGMT */
2331 tmp
= S_008C0C_NUM_PS_THREADS(num_ps_threads
);
2332 tmp
|= S_008C0C_NUM_VS_THREADS(num_vs_threads
);
2333 tmp
|= S_008C0C_NUM_GS_THREADS(num_gs_threads
);
2334 tmp
|= S_008C0C_NUM_ES_THREADS(num_es_threads
);
2335 r600_store_value(cb
, tmp
); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2337 /* SQ_STACK_RESOURCE_MGMT_1 */
2338 tmp
= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
2339 tmp
|= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
2340 r600_store_value(cb
, tmp
); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2342 /* SQ_STACK_RESOURCE_MGMT_2 */
2343 tmp
= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
2344 tmp
|= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
2345 r600_store_value(cb
, tmp
); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2347 r600_store_config_reg(cb
, R_009714_VC_ENHANCE
, 0);
2349 if (rctx
->b
.chip_class
>= R700
) {
2350 r600_store_context_reg(cb
, R_028A50_VGT_ENHANCE
, 4);
2351 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0x00004000);
2352 r600_store_config_reg(cb
, R_009830_DB_DEBUG
, 0);
2353 r600_store_config_reg(cb
, R_009838_DB_WATERMARKS
, 0x00420204);
2354 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2356 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0);
2357 r600_store_config_reg(cb
, R_009830_DB_DEBUG
, 0x82000000);
2358 r600_store_config_reg(cb
, R_009838_DB_WATERMARKS
, 0x01020204);
2359 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 1);
2361 r600_store_context_reg_seq(cb
, R_0288A8_SQ_ESGS_RING_ITEMSIZE
, 9);
2362 r600_store_value(cb
, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2363 r600_store_value(cb
, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2364 r600_store_value(cb
, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2365 r600_store_value(cb
, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2366 r600_store_value(cb
, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2367 r600_store_value(cb
, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2368 r600_store_value(cb
, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2369 r600_store_value(cb
, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2370 r600_store_value(cb
, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2372 /* to avoid GPU doing any preloading of constant from random address */
2373 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
2374 for (i
= 0; i
< 16; i
++)
2375 r600_store_value(cb
, 0);
2377 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
2378 for (i
= 0; i
< 16; i
++)
2379 r600_store_value(cb
, 0);
2381 r600_store_context_reg_seq(cb
, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
, 16);
2382 for (i
= 0; i
< 16; i
++)
2383 r600_store_value(cb
, 0);
2385 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2386 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2387 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2388 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2389 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2390 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2391 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2392 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2393 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2394 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2395 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2396 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2397 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2398 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE, 0); */
2400 r600_store_context_reg(cb
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
2401 r600_store_context_reg(cb
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 0);
2402 r600_store_context_reg(cb
, R_028AA4_VGT_INSTANCE_STEP_RATE_1
, 0);
2404 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
2405 r600_store_value(cb
, 1); /* R_028AB4_VGT_REUSE_OFF */
2406 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2408 r600_store_context_reg(cb
, R_028B20_VGT_STRMOUT_BUFFER_EN
, 0);
2410 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2412 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
2414 r600_store_context_reg_seq(cb
, R_0286DC_SPI_FOG_CNTL
, 3);
2415 r600_store_value(cb
, 0); /* R_0286DC_SPI_FOG_CNTL */
2416 r600_store_value(cb
, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2417 r600_store_value(cb
, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2419 r600_store_context_reg_seq(cb
, R_028D28_DB_SRESULTS_COMPARE_STATE0
, 3);
2420 r600_store_value(cb
, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2421 r600_store_value(cb
, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2422 r600_store_value(cb
, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2424 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2425 r600_store_context_reg(cb
, R_028A48_PA_SC_MPASS_PS_CNTL
, 0);
2427 r600_store_context_reg_seq(cb
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 4);
2428 r600_store_value(cb
, fui(1.0)); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2429 r600_store_value(cb
, fui(1.0)); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2430 r600_store_value(cb
, fui(1.0)); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2431 r600_store_value(cb
, fui(1.0)); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2433 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2 * R600_MAX_VIEWPORTS
);
2434 for (tmp
= 0; tmp
< R600_MAX_VIEWPORTS
; tmp
++) {
2435 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2436 r600_store_value(cb
, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2439 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2440 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2442 if (rctx
->b
.chip_class
>= R700
) {
2443 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2446 r600_store_context_reg_seq(cb
, R_028C30_CB_CLRCMP_CONTROL
, 4);
2447 r600_store_value(cb
, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2448 r600_store_value(cb
, 0); /* R_028C34_CB_CLRCMP_SRC */
2449 r600_store_value(cb
, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2450 r600_store_value(cb
, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2452 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2453 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2454 r600_store_value(cb
, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2456 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2457 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2458 r600_store_value(cb
, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2460 r600_store_context_reg_seq(cb
, R_0288CC_SQ_PGM_CF_OFFSET_PS
, 5);
2461 r600_store_value(cb
, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2462 r600_store_value(cb
, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2463 r600_store_value(cb
, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2464 r600_store_value(cb
, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2465 r600_store_value(cb
, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2467 r600_store_context_reg(cb
, R_0288E0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
2469 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2470 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2471 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2473 r600_store_context_reg(cb
, R_0288A4_SQ_PGM_RESOURCES_FS
, 0);
2475 if (rctx
->b
.chip_class
== R700
)
2476 r600_store_context_reg(cb
, R_028350_SX_MISC
, 0);
2477 if (rctx
->b
.chip_class
== R700
&& rctx
->screen
->b
.has_streamout
)
2478 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
2480 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2481 if (rctx
->screen
->b
.has_streamout
) {
2482 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2485 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
, 0x1000FFF);
2486 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
+ (32 * 4), 0x1000FFF);
2487 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
+ (64 * 4), 0x1000FFF);
2490 void r600_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2492 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2493 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2494 struct r600_shader
*rshader
= &shader
->shader
;
2495 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
;
2496 int pos_index
= -1, face_index
= -1, fixed_pt_position_index
= -1;
2497 unsigned tmp
, sid
, ufi
= 0;
2498 int need_linear
= 0;
2499 unsigned z_export
= 0, stencil_export
= 0, mask_export
= 0;
2500 unsigned sprite_coord_enable
= rctx
->rasterizer
? rctx
->rasterizer
->sprite_coord_enable
: 0;
2503 r600_init_command_buffer(cb
, 64);
2508 r600_store_context_reg_seq(cb
, R_028644_SPI_PS_INPUT_CNTL_0
, rshader
->ninput
);
2509 for (i
= 0; i
< rshader
->ninput
; i
++) {
2510 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
2512 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
&& face_index
== -1)
2514 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_SAMPLEID
)
2515 fixed_pt_position_index
= i
;
2517 sid
= rshader
->input
[i
].spi_sid
;
2519 tmp
= S_028644_SEMANTIC(sid
);
2521 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
2522 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2523 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
2524 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
))
2525 tmp
|= S_028644_FLAT_SHADE(1);
2527 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
2528 sprite_coord_enable
& (1 << rshader
->input
[i
].sid
)) {
2529 tmp
|= S_028644_PT_SPRITE_TEX(1);
2532 if (rshader
->input
[i
].interpolate_location
== TGSI_INTERPOLATE_LOC_CENTROID
)
2533 tmp
|= S_028644_SEL_CENTROID(1);
2535 if (rshader
->input
[i
].interpolate_location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
2536 tmp
|= S_028644_SEL_SAMPLE(1);
2538 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
) {
2540 tmp
|= S_028644_SEL_LINEAR(1);
2543 r600_store_value(cb
, tmp
);
2546 db_shader_control
= 0;
2547 for (i
= 0; i
< rshader
->noutput
; i
++) {
2548 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2550 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2552 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
&&
2553 rctx
->framebuffer
.nr_samples
> 1 && rctx
->ps_iter_samples
> 0)
2556 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(z_export
);
2557 db_shader_control
|= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export
);
2558 db_shader_control
|= S_02880C_MASK_EXPORT_ENABLE(mask_export
);
2559 if (rshader
->uses_kill
)
2560 db_shader_control
|= S_02880C_KILL_ENABLE(1);
2563 for (i
= 0; i
< rshader
->noutput
; i
++) {
2564 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
2565 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
||
2566 rshader
->output
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
) {
2570 num_cout
= rshader
->nr_ps_color_exports
;
2571 exports_ps
|= S_028854_EXPORT_COLORS(num_cout
);
2573 /* always at least export 1 component per pixel */
2577 shader
->nr_ps_color_outputs
= num_cout
;
2579 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(rshader
->ninput
) |
2580 S_0286CC_PERSP_GRADIENT_ENA(1)|
2581 S_0286CC_LINEAR_GRADIENT_ENA(need_linear
);
2583 if (pos_index
!= -1) {
2584 spi_ps_in_control_0
|= (S_0286CC_POSITION_ENA(1) |
2585 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].interpolate_location
== TGSI_INTERPOLATE_LOC_CENTROID
) |
2586 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
) |
2587 S_0286CC_BARYC_SAMPLE_CNTL(1)) |
2588 S_0286CC_POSITION_SAMPLE(rshader
->input
[pos_index
].interpolate_location
== TGSI_INTERPOLATE_LOC_SAMPLE
);
2589 spi_input_z
|= S_0286D8_PROVIDE_Z_TO_SPI(1);
2592 spi_ps_in_control_1
= 0;
2593 if (face_index
!= -1) {
2594 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
2595 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
2597 if (fixed_pt_position_index
!= -1) {
2598 spi_ps_in_control_1
|= S_0286D0_FIXED_PT_POSITION_ENA(1) |
2599 S_0286D0_FIXED_PT_POSITION_ADDR(rshader
->input
[fixed_pt_position_index
].gpr
);
2602 /* HW bug in original R600 */
2603 if (rctx
->b
.family
== CHIP_R600
)
2606 r600_store_context_reg_seq(cb
, R_0286CC_SPI_PS_IN_CONTROL_0
, 2);
2607 r600_store_value(cb
, spi_ps_in_control_0
); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2608 r600_store_value(cb
, spi_ps_in_control_1
); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2610 r600_store_context_reg(cb
, R_0286D8_SPI_INPUT_Z
, spi_input_z
);
2612 r600_store_context_reg_seq(cb
, R_028850_SQ_PGM_RESOURCES_PS
, 2);
2613 r600_store_value(cb
, /* R_028850_SQ_PGM_RESOURCES_PS*/
2614 S_028850_NUM_GPRS(rshader
->bc
.ngpr
) |
2615 S_028850_STACK_SIZE(rshader
->bc
.nstack
) |
2616 S_028850_UNCACHED_FIRST_INST(ufi
));
2617 r600_store_value(cb
, exports_ps
); /* R_028854_SQ_PGM_EXPORTS_PS */
2619 r600_store_context_reg(cb
, R_028840_SQ_PGM_START_PS
, 0);
2620 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2622 /* only set some bits here, the other bits are set in the dsa state */
2623 shader
->db_shader_control
= db_shader_control
;
2624 shader
->ps_depth_export
= z_export
| stencil_export
| mask_export
;
2626 shader
->sprite_coord_enable
= sprite_coord_enable
;
2627 if (rctx
->rasterizer
)
2628 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
2631 void r600_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2633 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2634 struct r600_shader
*rshader
= &shader
->shader
;
2635 unsigned spi_vs_out_id
[10] = {};
2636 unsigned i
, tmp
, nparams
= 0;
2638 for (i
= 0; i
< rshader
->noutput
; i
++) {
2639 if (rshader
->output
[i
].spi_sid
) {
2640 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
2641 spi_vs_out_id
[nparams
/ 4] |= tmp
;
2646 r600_init_command_buffer(cb
, 32);
2648 r600_store_context_reg_seq(cb
, R_028614_SPI_VS_OUT_ID_0
, 10);
2649 for (i
= 0; i
< 10; i
++) {
2650 r600_store_value(cb
, spi_vs_out_id
[i
]);
2653 /* Certain attributes (position, psize, etc.) don't count as params.
2654 * VS is required to export at least one param and r600_shader_from_tgsi()
2655 * takes care of adding a dummy export.
2660 r600_store_context_reg(cb
, R_0286C4_SPI_VS_OUT_CONFIG
,
2661 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
2662 r600_store_context_reg(cb
, R_028868_SQ_PGM_RESOURCES_VS
,
2663 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
2664 S_028868_STACK_SIZE(rshader
->bc
.nstack
));
2665 if (rshader
->vs_position_window_space
) {
2666 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
,
2667 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
2669 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
,
2670 S_028818_VTX_W0_FMT(1) |
2671 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2672 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2673 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2676 r600_store_context_reg(cb
, R_028858_SQ_PGM_START_VS
, 0);
2677 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2679 shader
->pa_cl_vs_out_cntl
=
2680 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
2681 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
2682 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
2683 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
) |
2684 S_02881C_USE_VTX_EDGE_FLAG(rshader
->vs_out_edgeflag
) |
2685 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader
->vs_out_layer
) |
2686 S_02881C_USE_VTX_VIEWPORT_INDX(rshader
->vs_out_viewport
);
2689 #define RV610_GSVS_ALIGN 32
2690 #define R600_GSVS_ALIGN 16
2692 void r600_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2694 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2695 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2696 struct r600_shader
*rshader
= &shader
->shader
;
2697 struct r600_shader
*cp_shader
= &shader
->gs_copy_shader
->shader
;
2698 unsigned gsvs_itemsize
=
2699 (cp_shader
->ring_item_sizes
[0] * shader
->selector
->gs_max_out_vertices
) >> 2;
2701 /* some r600s needs gsvs itemsize aligned to cacheline size
2702 this was fixed in rs780 and above. */
2703 switch (rctx
->b
.family
) {
2705 gsvs_itemsize
= align(gsvs_itemsize
, RV610_GSVS_ALIGN
);
2712 gsvs_itemsize
= align(gsvs_itemsize
, R600_GSVS_ALIGN
);
2718 r600_init_command_buffer(cb
, 64);
2720 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2721 r600_store_context_reg(cb
, R_028AB8_VGT_VTX_CNT_EN
, 1);
2723 if (rctx
->b
.chip_class
>= R700
) {
2724 r600_store_context_reg(cb
, R_028B38_VGT_GS_MAX_VERT_OUT
,
2725 S_028B38_MAX_VERT_OUT(shader
->selector
->gs_max_out_vertices
));
2727 r600_store_context_reg(cb
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
,
2728 r600_conv_prim_to_gs_out(shader
->selector
->gs_output_prim
));
2730 r600_store_context_reg(cb
, R_0288C8_SQ_GS_VERT_ITEMSIZE
,
2731 cp_shader
->ring_item_sizes
[0] >> 2);
2733 r600_store_context_reg(cb
, R_0288A8_SQ_ESGS_RING_ITEMSIZE
,
2734 (rshader
->ring_item_sizes
[0]) >> 2);
2736 r600_store_context_reg(cb
, R_0288AC_SQ_GSVS_RING_ITEMSIZE
,
2739 /* FIXME calculate these values somehow ??? */
2740 r600_store_config_reg_seq(cb
, R_0088C8_VGT_GS_PER_ES
, 2);
2741 r600_store_value(cb
, 0x80); /* GS_PER_ES */
2742 r600_store_value(cb
, 0x100); /* ES_PER_GS */
2743 r600_store_config_reg_seq(cb
, R_0088E8_VGT_GS_PER_VS
, 1);
2744 r600_store_value(cb
, 0x2); /* GS_PER_VS */
2746 r600_store_context_reg(cb
, R_02887C_SQ_PGM_RESOURCES_GS
,
2747 S_02887C_NUM_GPRS(rshader
->bc
.ngpr
) |
2748 S_02887C_STACK_SIZE(rshader
->bc
.nstack
));
2749 r600_store_context_reg(cb
, R_02886C_SQ_PGM_START_GS
, 0);
2750 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2753 void r600_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2755 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2756 struct r600_shader
*rshader
= &shader
->shader
;
2758 r600_init_command_buffer(cb
, 32);
2760 r600_store_context_reg(cb
, R_028890_SQ_PGM_RESOURCES_ES
,
2761 S_028890_NUM_GPRS(rshader
->bc
.ngpr
) |
2762 S_028890_STACK_SIZE(rshader
->bc
.nstack
));
2763 r600_store_context_reg(cb
, R_028880_SQ_PGM_START_ES
, 0);
2764 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2768 void *r600_create_resolve_blend(struct r600_context
*rctx
)
2770 struct pipe_blend_state blend
;
2773 memset(&blend
, 0, sizeof(blend
));
2774 blend
.independent_blend_enable
= true;
2775 for (i
= 0; i
< 2; i
++) {
2776 blend
.rt
[i
].colormask
= 0xf;
2777 blend
.rt
[i
].blend_enable
= 1;
2778 blend
.rt
[i
].rgb_func
= PIPE_BLEND_ADD
;
2779 blend
.rt
[i
].alpha_func
= PIPE_BLEND_ADD
;
2780 blend
.rt
[i
].rgb_src_factor
= PIPE_BLENDFACTOR_ZERO
;
2781 blend
.rt
[i
].rgb_dst_factor
= PIPE_BLENDFACTOR_ZERO
;
2782 blend
.rt
[i
].alpha_src_factor
= PIPE_BLENDFACTOR_ZERO
;
2783 blend
.rt
[i
].alpha_dst_factor
= PIPE_BLENDFACTOR_ZERO
;
2785 return r600_create_blend_state_mode(&rctx
->b
.b
, &blend
, V_028808_SPECIAL_RESOLVE_BOX
);
2788 void *r700_create_resolve_blend(struct r600_context
*rctx
)
2790 struct pipe_blend_state blend
;
2792 memset(&blend
, 0, sizeof(blend
));
2793 blend
.independent_blend_enable
= true;
2794 blend
.rt
[0].colormask
= 0xf;
2795 return r600_create_blend_state_mode(&rctx
->b
.b
, &blend
, V_028808_SPECIAL_RESOLVE_BOX
);
2798 void *r600_create_decompress_blend(struct r600_context
*rctx
)
2800 struct pipe_blend_state blend
;
2802 memset(&blend
, 0, sizeof(blend
));
2803 blend
.independent_blend_enable
= true;
2804 blend
.rt
[0].colormask
= 0xf;
2805 return r600_create_blend_state_mode(&rctx
->b
.b
, &blend
, V_028808_SPECIAL_EXPAND_SAMPLES
);
2808 void *r600_create_db_flush_dsa(struct r600_context
*rctx
)
2810 struct pipe_depth_stencil_alpha_state dsa
;
2811 boolean quirk
= false;
2813 if (rctx
->b
.family
== CHIP_RV610
|| rctx
->b
.family
== CHIP_RV630
||
2814 rctx
->b
.family
== CHIP_RV620
|| rctx
->b
.family
== CHIP_RV635
)
2817 memset(&dsa
, 0, sizeof(dsa
));
2820 dsa
.depth
.enabled
= 1;
2821 dsa
.depth
.func
= PIPE_FUNC_LEQUAL
;
2822 dsa
.stencil
[0].enabled
= 1;
2823 dsa
.stencil
[0].func
= PIPE_FUNC_ALWAYS
;
2824 dsa
.stencil
[0].zpass_op
= PIPE_STENCIL_OP_KEEP
;
2825 dsa
.stencil
[0].zfail_op
= PIPE_STENCIL_OP_INCR
;
2826 dsa
.stencil
[0].writemask
= 0xff;
2829 return rctx
->b
.b
.create_depth_stencil_alpha_state(&rctx
->b
.b
, &dsa
);
2832 void r600_update_db_shader_control(struct r600_context
* rctx
)
2835 unsigned db_shader_control
;
2836 uint8_t ps_conservative_z
;
2838 if (!rctx
->ps_shader
) {
2842 dual_export
= rctx
->framebuffer
.export_16bpc
&&
2843 !rctx
->ps_shader
->current
->ps_depth_export
;
2845 db_shader_control
= rctx
->ps_shader
->current
->db_shader_control
|
2846 S_02880C_DUAL_EXPORT_ENABLE(dual_export
);
2848 ps_conservative_z
= rctx
->ps_shader
->current
->shader
.ps_conservative_z
;
2850 /* When alpha test is enabled we can't trust the hw to make the proper
2851 * decision on the order in which ztest should be run related to fragment
2854 * If alpha test is enabled perform z test after fragment. RE_Z (early
2855 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2857 if (rctx
->alphatest_state
.sx_alpha_test_control
) {
2858 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
2860 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2863 if (db_shader_control
!= rctx
->db_misc_state
.db_shader_control
||
2864 ps_conservative_z
!= rctx
->db_misc_state
.ps_conservative_z
) {
2865 rctx
->db_misc_state
.db_shader_control
= db_shader_control
;
2866 rctx
->db_misc_state
.ps_conservative_z
= ps_conservative_z
;
2867 r600_mark_atom_dirty(rctx
, &rctx
->db_misc_state
.atom
);
2871 static inline unsigned r600_array_mode(unsigned mode
)
2874 case RADEON_SURF_MODE_LINEAR_ALIGNED
: return V_0280A0_ARRAY_LINEAR_ALIGNED
;
2876 case RADEON_SURF_MODE_1D
: return V_0280A0_ARRAY_1D_TILED_THIN1
;
2878 case RADEON_SURF_MODE_2D
: return V_0280A0_ARRAY_2D_TILED_THIN1
;
2880 case RADEON_SURF_MODE_LINEAR
: return V_0280A0_ARRAY_LINEAR_GENERAL
;
2884 static boolean
r600_dma_copy_tile(struct r600_context
*rctx
,
2885 struct pipe_resource
*dst
,
2890 struct pipe_resource
*src
,
2895 unsigned copy_height
,
2899 struct radeon_winsys_cs
*cs
= rctx
->b
.dma
.cs
;
2900 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
2901 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
2902 unsigned array_mode
, lbpp
, pitch_tile_max
, slice_tile_max
, size
;
2903 unsigned ncopy
, height
, cheight
, detile
, i
, x
, y
, z
, src_mode
, dst_mode
;
2904 uint64_t base
, addr
;
2906 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
2907 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
2908 /* downcast linear aligned to linear to simplify test */
2909 src_mode
= src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: src_mode
;
2910 dst_mode
= dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: dst_mode
;
2911 assert(dst_mode
!= src_mode
);
2914 lbpp
= util_logbase2(bpp
);
2915 pitch_tile_max
= ((pitch
/ bpp
) / 8) - 1;
2917 if (dst_mode
== RADEON_SURF_MODE_LINEAR
) {
2919 array_mode
= r600_array_mode(src_mode
);
2920 slice_tile_max
= (rsrc
->surface
.level
[src_level
].nblk_x
* rsrc
->surface
.level
[src_level
].nblk_y
) / (8*8);
2921 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
2922 /* linear height must be the same as the slice tile max height, it's ok even
2923 * if the linear destination/source have smaller heigh as the size of the
2924 * dma packet will be using the copy_height which is always smaller or equal
2925 * to the linear height
2927 height
= rsrc
->surface
.level
[src_level
].npix_y
;
2932 base
= rsrc
->surface
.level
[src_level
].offset
;
2933 addr
= rdst
->surface
.level
[dst_level
].offset
;
2934 addr
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
2935 addr
+= dst_y
* pitch
+ dst_x
* bpp
;
2938 array_mode
= r600_array_mode(dst_mode
);
2939 slice_tile_max
= (rdst
->surface
.level
[dst_level
].nblk_x
* rdst
->surface
.level
[dst_level
].nblk_y
) / (8*8);
2940 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
2941 /* linear height must be the same as the slice tile max height, it's ok even
2942 * if the linear destination/source have smaller heigh as the size of the
2943 * dma packet will be using the copy_height which is always smaller or equal
2944 * to the linear height
2946 height
= rdst
->surface
.level
[dst_level
].npix_y
;
2951 base
= rdst
->surface
.level
[dst_level
].offset
;
2952 addr
= rsrc
->surface
.level
[src_level
].offset
;
2953 addr
+= rsrc
->surface
.level
[src_level
].slice_size
* src_z
;
2954 addr
+= src_y
* pitch
+ src_x
* bpp
;
2956 /* check that we are in dw/base alignment constraint */
2957 if (addr
% 4 || base
% 256) {
2961 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2962 * line in the blit. Compute max 8 line we can copy in the size limit
2964 cheight
= ((R600_DMA_COPY_MAX_SIZE_DW
* 4) / pitch
) & 0xfffffff8;
2965 ncopy
= (copy_height
/ cheight
) + !!(copy_height
% cheight
);
2966 r600_need_dma_space(&rctx
->b
, ncopy
* 7);
2968 for (i
= 0; i
< ncopy
; i
++) {
2969 cheight
= cheight
> copy_height
? copy_height
: cheight
;
2970 size
= (cheight
* pitch
) / 4;
2971 /* emit reloc before writing cs so that cs is always in consistent state */
2972 radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.dma
, &rsrc
->resource
, RADEON_USAGE_READ
,
2973 RADEON_PRIO_SDMA_TEXTURE
);
2974 radeon_add_to_buffer_list(&rctx
->b
, &rctx
->b
.dma
, &rdst
->resource
, RADEON_USAGE_WRITE
,
2975 RADEON_PRIO_SDMA_TEXTURE
);
2976 cs
->buf
[cs
->cdw
++] = DMA_PACKET(DMA_PACKET_COPY
, 1, 0, size
);
2977 cs
->buf
[cs
->cdw
++] = base
>> 8;
2978 cs
->buf
[cs
->cdw
++] = (detile
<< 31) | (array_mode
<< 27) |
2979 (lbpp
<< 24) | ((height
- 1) << 10) |
2981 cs
->buf
[cs
->cdw
++] = (slice_tile_max
<< 12) | (z
<< 0);
2982 cs
->buf
[cs
->cdw
++] = (x
<< 3) | (y
<< 17);
2983 cs
->buf
[cs
->cdw
++] = addr
& 0xfffffffc;
2984 cs
->buf
[cs
->cdw
++] = (addr
>> 32UL) & 0xff;
2985 copy_height
-= cheight
;
2986 addr
+= cheight
* pitch
;
2992 static void r600_dma_copy(struct pipe_context
*ctx
,
2993 struct pipe_resource
*dst
,
2995 unsigned dstx
, unsigned dsty
, unsigned dstz
,
2996 struct pipe_resource
*src
,
2998 const struct pipe_box
*src_box
)
3000 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3001 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
3002 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
3003 unsigned dst_pitch
, src_pitch
, bpp
, dst_mode
, src_mode
, copy_height
;
3004 unsigned src_w
, dst_w
;
3005 unsigned src_x
, src_y
;
3006 unsigned dst_x
= dstx
, dst_y
= dsty
, dst_z
= dstz
;
3008 if (rctx
->b
.dma
.cs
== NULL
) {
3012 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
3013 if (dst_x
% 4 || src_box
->x
% 4 || src_box
->width
% 4)
3016 r600_dma_copy_buffer(rctx
, dst
, src
, dst_x
, src_box
->x
, src_box
->width
);
3020 if (src
->format
!= dst
->format
|| src_box
->depth
> 1) {
3024 src_x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
3025 dst_x
= util_format_get_nblocksx(src
->format
, dst_x
);
3026 src_y
= util_format_get_nblocksy(src
->format
, src_box
->y
);
3027 dst_y
= util_format_get_nblocksy(src
->format
, dst_y
);
3029 bpp
= rdst
->surface
.bpe
;
3030 dst_pitch
= rdst
->surface
.level
[dst_level
].pitch_bytes
;
3031 src_pitch
= rsrc
->surface
.level
[src_level
].pitch_bytes
;
3032 src_w
= rsrc
->surface
.level
[src_level
].npix_x
;
3033 dst_w
= rdst
->surface
.level
[dst_level
].npix_x
;
3034 copy_height
= src_box
->height
/ rsrc
->surface
.blk_h
;
3036 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
3037 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
3038 /* downcast linear aligned to linear to simplify test */
3039 src_mode
= src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: src_mode
;
3040 dst_mode
= dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: dst_mode
;
3042 if (src_pitch
!= dst_pitch
|| src_box
->x
|| dst_x
|| src_w
!= dst_w
) {
3043 /* strict requirement on r6xx/r7xx */
3046 /* lot of constraint on alignment this should capture them all */
3047 if (src_pitch
% 8 || src_box
->y
% 8 || dst_y
% 8) {
3051 if (src_mode
== dst_mode
) {
3052 uint64_t dst_offset
, src_offset
, size
;
3054 /* simple dma blit would do NOTE code here assume :
3057 * dst_pitch == src_pitch
3059 src_offset
= rsrc
->surface
.level
[src_level
].offset
;
3060 src_offset
+= rsrc
->surface
.level
[src_level
].slice_size
* src_box
->z
;
3061 src_offset
+= src_y
* src_pitch
+ src_x
* bpp
;
3062 dst_offset
= rdst
->surface
.level
[dst_level
].offset
;
3063 dst_offset
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
3064 dst_offset
+= dst_y
* dst_pitch
+ dst_x
* bpp
;
3065 size
= src_box
->height
* src_pitch
;
3066 /* must be dw aligned */
3067 if (dst_offset
% 4 || src_offset
% 4 || size
% 4) {
3070 r600_dma_copy_buffer(rctx
, dst
, src
, dst_offset
, src_offset
, size
);
3072 if (!r600_dma_copy_tile(rctx
, dst
, dst_level
, dst_x
, dst_y
, dst_z
,
3073 src
, src_level
, src_x
, src_y
, src_box
->z
,
3074 copy_height
, dst_pitch
, bpp
)) {
3081 r600_resource_copy_region(ctx
, dst
, dst_level
, dstx
, dsty
, dstz
,
3082 src
, src_level
, src_box
);
3085 void r600_init_state_functions(struct r600_context
*rctx
)
3090 * To avoid GPU lockup registers must be emited in a specific order
3091 * (no kidding ...). The order below is important and have been
3092 * partialy infered from analyzing fglrx command stream.
3094 * Don't reorder atom without carefully checking the effect (GPU lockup
3095 * or piglit regression).
3099 r600_init_atom(rctx
, &rctx
->framebuffer
.atom
, id
++, r600_emit_framebuffer_state
, 0);
3102 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
].atom
, id
++, r600_emit_vs_constant_buffers
, 0);
3103 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
].atom
, id
++, r600_emit_gs_constant_buffers
, 0);
3104 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
].atom
, id
++, r600_emit_ps_constant_buffers
, 0);
3106 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3107 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
3109 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].states
.atom
, id
++, r600_emit_vs_sampler_states
, 0);
3110 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].states
.atom
, id
++, r600_emit_gs_sampler_states
, 0);
3111 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].states
.atom
, id
++, r600_emit_ps_sampler_states
, 0);
3113 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
.atom
, id
++, r600_emit_vs_sampler_views
, 0);
3114 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
.atom
, id
++, r600_emit_gs_sampler_views
, 0);
3115 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.atom
, id
++, r600_emit_ps_sampler_views
, 0);
3116 r600_init_atom(rctx
, &rctx
->vertex_buffer_state
.atom
, id
++, r600_emit_vertex_buffers
, 0);
3118 r600_init_atom(rctx
, &rctx
->vgt_state
.atom
, id
++, r600_emit_vgt_state
, 10);
3120 r600_init_atom(rctx
, &rctx
->seamless_cube_map
.atom
, id
++, r600_emit_seamless_cube_map
, 3);
3121 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, r600_emit_sample_mask
, 3);
3122 rctx
->sample_mask
.sample_mask
= ~0;
3124 r600_init_atom(rctx
, &rctx
->alphatest_state
.atom
, id
++, r600_emit_alphatest_state
, 6);
3125 r600_init_atom(rctx
, &rctx
->blend_color
.atom
, id
++, r600_emit_blend_color
, 6);
3126 r600_init_atom(rctx
, &rctx
->blend_state
.atom
, id
++, r600_emit_cso_state
, 0);
3127 r600_init_atom(rctx
, &rctx
->cb_misc_state
.atom
, id
++, r600_emit_cb_misc_state
, 7);
3128 r600_init_atom(rctx
, &rctx
->clip_misc_state
.atom
, id
++, r600_emit_clip_misc_state
, 6);
3129 r600_init_atom(rctx
, &rctx
->clip_state
.atom
, id
++, r600_emit_clip_state
, 26);
3130 r600_init_atom(rctx
, &rctx
->db_misc_state
.atom
, id
++, r600_emit_db_misc_state
, 7);
3131 r600_init_atom(rctx
, &rctx
->db_state
.atom
, id
++, r600_emit_db_state
, 11);
3132 r600_init_atom(rctx
, &rctx
->dsa_state
.atom
, id
++, r600_emit_cso_state
, 0);
3133 r600_init_atom(rctx
, &rctx
->poly_offset_state
.atom
, id
++, r600_emit_polygon_offset
, 6);
3134 r600_init_atom(rctx
, &rctx
->rasterizer_state
.atom
, id
++, r600_emit_cso_state
, 0);
3135 r600_init_atom(rctx
, &rctx
->scissor
.atom
, id
++, r600_emit_scissor_state
, 0);
3136 r600_init_atom(rctx
, &rctx
->viewport
.atom
, id
++, r600_emit_viewport_state
, 0);
3137 r600_init_atom(rctx
, &rctx
->config_state
.atom
, id
++, r600_emit_config_state
, 3);
3138 r600_init_atom(rctx
, &rctx
->stencil_ref
.atom
, id
++, r600_emit_stencil_ref
, 4);
3139 r600_init_atom(rctx
, &rctx
->vertex_fetch_shader
.atom
, id
++, r600_emit_vertex_fetch_shader
, 5);
3140 r600_add_atom(rctx
, &rctx
->b
.render_cond_atom
, id
++);
3141 r600_add_atom(rctx
, &rctx
->b
.streamout
.begin_atom
, id
++);
3142 r600_add_atom(rctx
, &rctx
->b
.streamout
.enable_atom
, id
++);
3143 for (i
= 0; i
< R600_NUM_HW_STAGES
; i
++)
3144 r600_init_atom(rctx
, &rctx
->hw_shader_stages
[i
].atom
, id
++, r600_emit_shader
, 0);
3145 r600_init_atom(rctx
, &rctx
->shader_stages
.atom
, id
++, r600_emit_shader_stages
, 0);
3146 r600_init_atom(rctx
, &rctx
->gs_rings
.atom
, id
++, r600_emit_gs_rings
, 0);
3148 rctx
->b
.b
.create_blend_state
= r600_create_blend_state
;
3149 rctx
->b
.b
.create_depth_stencil_alpha_state
= r600_create_dsa_state
;
3150 rctx
->b
.b
.create_rasterizer_state
= r600_create_rs_state
;
3151 rctx
->b
.b
.create_sampler_state
= r600_create_sampler_state
;
3152 rctx
->b
.b
.create_sampler_view
= r600_create_sampler_view
;
3153 rctx
->b
.b
.set_framebuffer_state
= r600_set_framebuffer_state
;
3154 rctx
->b
.b
.set_polygon_stipple
= r600_set_polygon_stipple
;
3155 rctx
->b
.b
.set_min_samples
= r600_set_min_samples
;
3156 rctx
->b
.b
.set_scissor_states
= r600_set_scissor_states
;
3157 rctx
->b
.b
.get_sample_position
= r600_get_sample_position
;
3158 rctx
->b
.dma_copy
= r600_dma_copy
;
3160 /* this function must be last */