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r600g: rework flusing and synchronization pattern v7
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static uint32_t r600_translate_colorswap(enum pipe_format format)
145 {
146 switch (format) {
147 /* 8-bit buffers. */
148 case PIPE_FORMAT_A8_UNORM:
149 case PIPE_FORMAT_A8_SNORM:
150 case PIPE_FORMAT_A8_UINT:
151 case PIPE_FORMAT_A8_SINT:
152 case PIPE_FORMAT_A16_UNORM:
153 case PIPE_FORMAT_A16_SNORM:
154 case PIPE_FORMAT_A16_UINT:
155 case PIPE_FORMAT_A16_SINT:
156 case PIPE_FORMAT_A16_FLOAT:
157 case PIPE_FORMAT_A32_UINT:
158 case PIPE_FORMAT_A32_SINT:
159 case PIPE_FORMAT_A32_FLOAT:
160 case PIPE_FORMAT_R4A4_UNORM:
161 return V_0280A0_SWAP_ALT_REV;
162 case PIPE_FORMAT_I8_UNORM:
163 case PIPE_FORMAT_I8_SNORM:
164 case PIPE_FORMAT_I8_UINT:
165 case PIPE_FORMAT_I8_SINT:
166 case PIPE_FORMAT_L8_UNORM:
167 case PIPE_FORMAT_L8_SNORM:
168 case PIPE_FORMAT_L8_UINT:
169 case PIPE_FORMAT_L8_SINT:
170 case PIPE_FORMAT_L8_SRGB:
171 case PIPE_FORMAT_L16_UNORM:
172 case PIPE_FORMAT_L16_SNORM:
173 case PIPE_FORMAT_L16_UINT:
174 case PIPE_FORMAT_L16_SINT:
175 case PIPE_FORMAT_L16_FLOAT:
176 case PIPE_FORMAT_L32_UINT:
177 case PIPE_FORMAT_L32_SINT:
178 case PIPE_FORMAT_L32_FLOAT:
179 case PIPE_FORMAT_I16_UNORM:
180 case PIPE_FORMAT_I16_SNORM:
181 case PIPE_FORMAT_I16_UINT:
182 case PIPE_FORMAT_I16_SINT:
183 case PIPE_FORMAT_I16_FLOAT:
184 case PIPE_FORMAT_I32_UINT:
185 case PIPE_FORMAT_I32_SINT:
186 case PIPE_FORMAT_I32_FLOAT:
187 case PIPE_FORMAT_R8_UNORM:
188 case PIPE_FORMAT_R8_SNORM:
189 case PIPE_FORMAT_R8_UINT:
190 case PIPE_FORMAT_R8_SINT:
191 return V_0280A0_SWAP_STD;
192
193 case PIPE_FORMAT_L4A4_UNORM:
194 case PIPE_FORMAT_A4R4_UNORM:
195 return V_0280A0_SWAP_ALT;
196
197 /* 16-bit buffers. */
198 case PIPE_FORMAT_B5G6R5_UNORM:
199 return V_0280A0_SWAP_STD_REV;
200
201 case PIPE_FORMAT_B5G5R5A1_UNORM:
202 case PIPE_FORMAT_B5G5R5X1_UNORM:
203 return V_0280A0_SWAP_ALT;
204
205 case PIPE_FORMAT_B4G4R4A4_UNORM:
206 case PIPE_FORMAT_B4G4R4X4_UNORM:
207 return V_0280A0_SWAP_ALT;
208
209 case PIPE_FORMAT_Z16_UNORM:
210 return V_0280A0_SWAP_STD;
211
212 case PIPE_FORMAT_L8A8_UNORM:
213 case PIPE_FORMAT_L8A8_SNORM:
214 case PIPE_FORMAT_L8A8_UINT:
215 case PIPE_FORMAT_L8A8_SINT:
216 case PIPE_FORMAT_L8A8_SRGB:
217 case PIPE_FORMAT_L16A16_UNORM:
218 case PIPE_FORMAT_L16A16_SNORM:
219 case PIPE_FORMAT_L16A16_UINT:
220 case PIPE_FORMAT_L16A16_SINT:
221 case PIPE_FORMAT_L16A16_FLOAT:
222 case PIPE_FORMAT_L32A32_UINT:
223 case PIPE_FORMAT_L32A32_SINT:
224 case PIPE_FORMAT_L32A32_FLOAT:
225 return V_0280A0_SWAP_ALT;
226 case PIPE_FORMAT_R8G8_UNORM:
227 case PIPE_FORMAT_R8G8_SNORM:
228 case PIPE_FORMAT_R8G8_UINT:
229 case PIPE_FORMAT_R8G8_SINT:
230 return V_0280A0_SWAP_STD;
231
232 case PIPE_FORMAT_R16_UNORM:
233 case PIPE_FORMAT_R16_SNORM:
234 case PIPE_FORMAT_R16_UINT:
235 case PIPE_FORMAT_R16_SINT:
236 case PIPE_FORMAT_R16_FLOAT:
237 return V_0280A0_SWAP_STD;
238
239 /* 32-bit buffers. */
240
241 case PIPE_FORMAT_A8B8G8R8_SRGB:
242 return V_0280A0_SWAP_STD_REV;
243 case PIPE_FORMAT_B8G8R8A8_SRGB:
244 return V_0280A0_SWAP_ALT;
245
246 case PIPE_FORMAT_B8G8R8A8_UNORM:
247 case PIPE_FORMAT_B8G8R8X8_UNORM:
248 return V_0280A0_SWAP_ALT;
249
250 case PIPE_FORMAT_A8R8G8B8_UNORM:
251 case PIPE_FORMAT_X8R8G8B8_UNORM:
252 return V_0280A0_SWAP_ALT_REV;
253 case PIPE_FORMAT_R8G8B8A8_SNORM:
254 case PIPE_FORMAT_R8G8B8A8_UNORM:
255 case PIPE_FORMAT_R8G8B8X8_UNORM:
256 case PIPE_FORMAT_R8G8B8A8_SINT:
257 case PIPE_FORMAT_R8G8B8A8_UINT:
258 return V_0280A0_SWAP_STD;
259
260 case PIPE_FORMAT_A8B8G8R8_UNORM:
261 case PIPE_FORMAT_X8B8G8R8_UNORM:
262 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
263 return V_0280A0_SWAP_STD_REV;
264
265 case PIPE_FORMAT_Z24X8_UNORM:
266 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
267 return V_0280A0_SWAP_STD;
268
269 case PIPE_FORMAT_X8Z24_UNORM:
270 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
271 return V_0280A0_SWAP_STD;
272
273 case PIPE_FORMAT_R10G10B10A2_UNORM:
274 case PIPE_FORMAT_R10G10B10X2_SNORM:
275 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
276 return V_0280A0_SWAP_STD;
277
278 case PIPE_FORMAT_B10G10R10A2_UNORM:
279 case PIPE_FORMAT_B10G10R10A2_UINT:
280 return V_0280A0_SWAP_ALT;
281
282 case PIPE_FORMAT_R11G11B10_FLOAT:
283 case PIPE_FORMAT_R16G16_UNORM:
284 case PIPE_FORMAT_R16G16_SNORM:
285 case PIPE_FORMAT_R16G16_FLOAT:
286 case PIPE_FORMAT_R16G16_UINT:
287 case PIPE_FORMAT_R16G16_SINT:
288 case PIPE_FORMAT_R32_UINT:
289 case PIPE_FORMAT_R32_SINT:
290 case PIPE_FORMAT_R32_FLOAT:
291 case PIPE_FORMAT_Z32_FLOAT:
292 return V_0280A0_SWAP_STD;
293
294 /* 64-bit buffers. */
295 case PIPE_FORMAT_R32G32_FLOAT:
296 case PIPE_FORMAT_R32G32_UINT:
297 case PIPE_FORMAT_R32G32_SINT:
298 case PIPE_FORMAT_R16G16B16A16_UNORM:
299 case PIPE_FORMAT_R16G16B16A16_SNORM:
300 case PIPE_FORMAT_R16G16B16A16_UINT:
301 case PIPE_FORMAT_R16G16B16A16_SINT:
302 case PIPE_FORMAT_R16G16B16A16_FLOAT:
303 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
304
305 /* 128-bit buffers. */
306 case PIPE_FORMAT_R32G32B32A32_FLOAT:
307 case PIPE_FORMAT_R32G32B32A32_SNORM:
308 case PIPE_FORMAT_R32G32B32A32_UNORM:
309 case PIPE_FORMAT_R32G32B32A32_SINT:
310 case PIPE_FORMAT_R32G32B32A32_UINT:
311 return V_0280A0_SWAP_STD;
312 default:
313 R600_ERR("unsupported colorswap format %d\n", format);
314 return ~0U;
315 }
316 return ~0U;
317 }
318
319 static uint32_t r600_translate_colorformat(enum pipe_format format)
320 {
321 switch (format) {
322 case PIPE_FORMAT_L4A4_UNORM:
323 case PIPE_FORMAT_R4A4_UNORM:
324 case PIPE_FORMAT_A4R4_UNORM:
325 return V_0280A0_COLOR_4_4;
326
327 /* 8-bit buffers. */
328 case PIPE_FORMAT_A8_UNORM:
329 case PIPE_FORMAT_A8_SNORM:
330 case PIPE_FORMAT_A8_UINT:
331 case PIPE_FORMAT_A8_SINT:
332 case PIPE_FORMAT_I8_UNORM:
333 case PIPE_FORMAT_I8_SNORM:
334 case PIPE_FORMAT_I8_UINT:
335 case PIPE_FORMAT_I8_SINT:
336 case PIPE_FORMAT_L8_UNORM:
337 case PIPE_FORMAT_L8_SNORM:
338 case PIPE_FORMAT_L8_UINT:
339 case PIPE_FORMAT_L8_SINT:
340 case PIPE_FORMAT_L8_SRGB:
341 case PIPE_FORMAT_R8_UNORM:
342 case PIPE_FORMAT_R8_SNORM:
343 case PIPE_FORMAT_R8_UINT:
344 case PIPE_FORMAT_R8_SINT:
345 return V_0280A0_COLOR_8;
346
347 /* 16-bit buffers. */
348 case PIPE_FORMAT_B5G6R5_UNORM:
349 return V_0280A0_COLOR_5_6_5;
350
351 case PIPE_FORMAT_B5G5R5A1_UNORM:
352 case PIPE_FORMAT_B5G5R5X1_UNORM:
353 return V_0280A0_COLOR_1_5_5_5;
354
355 case PIPE_FORMAT_B4G4R4A4_UNORM:
356 case PIPE_FORMAT_B4G4R4X4_UNORM:
357 return V_0280A0_COLOR_4_4_4_4;
358
359 case PIPE_FORMAT_Z16_UNORM:
360 return V_0280A0_COLOR_16;
361
362 case PIPE_FORMAT_L8A8_UNORM:
363 case PIPE_FORMAT_L8A8_SNORM:
364 case PIPE_FORMAT_L8A8_UINT:
365 case PIPE_FORMAT_L8A8_SINT:
366 case PIPE_FORMAT_L8A8_SRGB:
367 case PIPE_FORMAT_R8G8_UNORM:
368 case PIPE_FORMAT_R8G8_SNORM:
369 case PIPE_FORMAT_R8G8_UINT:
370 case PIPE_FORMAT_R8G8_SINT:
371 return V_0280A0_COLOR_8_8;
372
373 case PIPE_FORMAT_R16_UNORM:
374 case PIPE_FORMAT_R16_SNORM:
375 case PIPE_FORMAT_R16_UINT:
376 case PIPE_FORMAT_R16_SINT:
377 case PIPE_FORMAT_A16_UNORM:
378 case PIPE_FORMAT_A16_SNORM:
379 case PIPE_FORMAT_A16_UINT:
380 case PIPE_FORMAT_A16_SINT:
381 case PIPE_FORMAT_L16_UNORM:
382 case PIPE_FORMAT_L16_SNORM:
383 case PIPE_FORMAT_L16_UINT:
384 case PIPE_FORMAT_L16_SINT:
385 case PIPE_FORMAT_I16_UNORM:
386 case PIPE_FORMAT_I16_SNORM:
387 case PIPE_FORMAT_I16_UINT:
388 case PIPE_FORMAT_I16_SINT:
389 return V_0280A0_COLOR_16;
390
391 case PIPE_FORMAT_R16_FLOAT:
392 case PIPE_FORMAT_A16_FLOAT:
393 case PIPE_FORMAT_L16_FLOAT:
394 case PIPE_FORMAT_I16_FLOAT:
395 return V_0280A0_COLOR_16_FLOAT;
396
397 /* 32-bit buffers. */
398 case PIPE_FORMAT_A8B8G8R8_SRGB:
399 case PIPE_FORMAT_A8B8G8R8_UNORM:
400 case PIPE_FORMAT_A8R8G8B8_UNORM:
401 case PIPE_FORMAT_B8G8R8A8_SRGB:
402 case PIPE_FORMAT_B8G8R8A8_UNORM:
403 case PIPE_FORMAT_B8G8R8X8_UNORM:
404 case PIPE_FORMAT_R8G8B8A8_SNORM:
405 case PIPE_FORMAT_R8G8B8A8_UNORM:
406 case PIPE_FORMAT_R8G8B8X8_UNORM:
407 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
408 case PIPE_FORMAT_X8B8G8R8_UNORM:
409 case PIPE_FORMAT_X8R8G8B8_UNORM:
410 case PIPE_FORMAT_R8G8B8A8_SINT:
411 case PIPE_FORMAT_R8G8B8A8_UINT:
412 return V_0280A0_COLOR_8_8_8_8;
413
414 case PIPE_FORMAT_R10G10B10A2_UNORM:
415 case PIPE_FORMAT_R10G10B10X2_SNORM:
416 case PIPE_FORMAT_B10G10R10A2_UNORM:
417 case PIPE_FORMAT_B10G10R10A2_UINT:
418 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
419 return V_0280A0_COLOR_2_10_10_10;
420
421 case PIPE_FORMAT_Z24X8_UNORM:
422 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
423 return V_0280A0_COLOR_8_24;
424
425 case PIPE_FORMAT_X8Z24_UNORM:
426 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
427 return V_0280A0_COLOR_24_8;
428
429 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
430 return V_0280A0_COLOR_X24_8_32_FLOAT;
431
432 case PIPE_FORMAT_R32_UINT:
433 case PIPE_FORMAT_R32_SINT:
434 case PIPE_FORMAT_A32_UINT:
435 case PIPE_FORMAT_A32_SINT:
436 case PIPE_FORMAT_L32_UINT:
437 case PIPE_FORMAT_L32_SINT:
438 case PIPE_FORMAT_I32_UINT:
439 case PIPE_FORMAT_I32_SINT:
440 return V_0280A0_COLOR_32;
441
442 case PIPE_FORMAT_R32_FLOAT:
443 case PIPE_FORMAT_A32_FLOAT:
444 case PIPE_FORMAT_L32_FLOAT:
445 case PIPE_FORMAT_I32_FLOAT:
446 case PIPE_FORMAT_Z32_FLOAT:
447 return V_0280A0_COLOR_32_FLOAT;
448
449 case PIPE_FORMAT_R16G16_FLOAT:
450 case PIPE_FORMAT_L16A16_FLOAT:
451 return V_0280A0_COLOR_16_16_FLOAT;
452
453 case PIPE_FORMAT_R16G16_UNORM:
454 case PIPE_FORMAT_R16G16_SNORM:
455 case PIPE_FORMAT_R16G16_UINT:
456 case PIPE_FORMAT_R16G16_SINT:
457 case PIPE_FORMAT_L16A16_UNORM:
458 case PIPE_FORMAT_L16A16_SNORM:
459 case PIPE_FORMAT_L16A16_UINT:
460 case PIPE_FORMAT_L16A16_SINT:
461 return V_0280A0_COLOR_16_16;
462
463 case PIPE_FORMAT_R11G11B10_FLOAT:
464 return V_0280A0_COLOR_10_11_11_FLOAT;
465
466 /* 64-bit buffers. */
467 case PIPE_FORMAT_R16G16B16A16_UINT:
468 case PIPE_FORMAT_R16G16B16A16_SINT:
469 case PIPE_FORMAT_R16G16B16A16_UNORM:
470 case PIPE_FORMAT_R16G16B16A16_SNORM:
471 return V_0280A0_COLOR_16_16_16_16;
472
473 case PIPE_FORMAT_R16G16B16A16_FLOAT:
474 return V_0280A0_COLOR_16_16_16_16_FLOAT;
475
476 case PIPE_FORMAT_R32G32_FLOAT:
477 case PIPE_FORMAT_L32A32_FLOAT:
478 return V_0280A0_COLOR_32_32_FLOAT;
479
480 case PIPE_FORMAT_R32G32_SINT:
481 case PIPE_FORMAT_R32G32_UINT:
482 case PIPE_FORMAT_L32A32_UINT:
483 case PIPE_FORMAT_L32A32_SINT:
484 return V_0280A0_COLOR_32_32;
485
486 /* 128-bit buffers. */
487 case PIPE_FORMAT_R32G32B32A32_FLOAT:
488 return V_0280A0_COLOR_32_32_32_32_FLOAT;
489 case PIPE_FORMAT_R32G32B32A32_SNORM:
490 case PIPE_FORMAT_R32G32B32A32_UNORM:
491 case PIPE_FORMAT_R32G32B32A32_SINT:
492 case PIPE_FORMAT_R32G32B32A32_UINT:
493 return V_0280A0_COLOR_32_32_32_32;
494
495 /* YUV buffers. */
496 case PIPE_FORMAT_UYVY:
497 case PIPE_FORMAT_YUYV:
498 default:
499 return ~0U; /* Unsupported. */
500 }
501 }
502
503 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
504 {
505 if (R600_BIG_ENDIAN) {
506 switch(colorformat) {
507 case V_0280A0_COLOR_4_4:
508 return ENDIAN_NONE;
509
510 /* 8-bit buffers. */
511 case V_0280A0_COLOR_8:
512 return ENDIAN_NONE;
513
514 /* 16-bit buffers. */
515 case V_0280A0_COLOR_5_6_5:
516 case V_0280A0_COLOR_1_5_5_5:
517 case V_0280A0_COLOR_4_4_4_4:
518 case V_0280A0_COLOR_16:
519 case V_0280A0_COLOR_8_8:
520 return ENDIAN_8IN16;
521
522 /* 32-bit buffers. */
523 case V_0280A0_COLOR_8_8_8_8:
524 case V_0280A0_COLOR_2_10_10_10:
525 case V_0280A0_COLOR_8_24:
526 case V_0280A0_COLOR_24_8:
527 case V_0280A0_COLOR_32_FLOAT:
528 case V_0280A0_COLOR_16_16_FLOAT:
529 case V_0280A0_COLOR_16_16:
530 return ENDIAN_8IN32;
531
532 /* 64-bit buffers. */
533 case V_0280A0_COLOR_16_16_16_16:
534 case V_0280A0_COLOR_16_16_16_16_FLOAT:
535 return ENDIAN_8IN16;
536
537 case V_0280A0_COLOR_32_32_FLOAT:
538 case V_0280A0_COLOR_32_32:
539 case V_0280A0_COLOR_X24_8_32_FLOAT:
540 return ENDIAN_8IN32;
541
542 /* 128-bit buffers. */
543 case V_0280A0_COLOR_32_32_32_FLOAT:
544 case V_0280A0_COLOR_32_32_32_32_FLOAT:
545 case V_0280A0_COLOR_32_32_32_32:
546 return ENDIAN_8IN32;
547 default:
548 return ENDIAN_NONE; /* Unsupported. */
549 }
550 } else {
551 return ENDIAN_NONE;
552 }
553 }
554
555 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
556 {
557 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
558 }
559
560 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
561 {
562 return r600_translate_colorformat(format) != ~0U &&
563 r600_translate_colorswap(format) != ~0U;
564 }
565
566 static bool r600_is_zs_format_supported(enum pipe_format format)
567 {
568 return r600_translate_dbformat(format) != ~0U;
569 }
570
571 boolean r600_is_format_supported(struct pipe_screen *screen,
572 enum pipe_format format,
573 enum pipe_texture_target target,
574 unsigned sample_count,
575 unsigned usage)
576 {
577 struct r600_screen *rscreen = (struct r600_screen*)screen;
578 unsigned retval = 0;
579
580 if (target >= PIPE_MAX_TEXTURE_TYPES) {
581 R600_ERR("r600: unsupported texture type %d\n", target);
582 return FALSE;
583 }
584
585 if (!util_format_is_supported(format, usage))
586 return FALSE;
587
588 if (sample_count > 1) {
589 if (!rscreen->has_msaa)
590 return FALSE;
591
592 /* R11G11B10 is broken on R6xx. */
593 if (rscreen->chip_class == R600 &&
594 format == PIPE_FORMAT_R11G11B10_FLOAT)
595 return FALSE;
596
597 /* MSAA integer colorbuffers hang. */
598 if (util_format_is_pure_integer(format) &&
599 !util_format_is_depth_or_stencil(format))
600 return FALSE;
601
602 switch (sample_count) {
603 case 2:
604 case 4:
605 case 8:
606 break;
607 default:
608 return FALSE;
609 }
610 }
611
612 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
613 r600_is_sampler_format_supported(screen, format)) {
614 retval |= PIPE_BIND_SAMPLER_VIEW;
615 }
616
617 if ((usage & (PIPE_BIND_RENDER_TARGET |
618 PIPE_BIND_DISPLAY_TARGET |
619 PIPE_BIND_SCANOUT |
620 PIPE_BIND_SHARED)) &&
621 r600_is_colorbuffer_format_supported(format)) {
622 retval |= usage &
623 (PIPE_BIND_RENDER_TARGET |
624 PIPE_BIND_DISPLAY_TARGET |
625 PIPE_BIND_SCANOUT |
626 PIPE_BIND_SHARED);
627 }
628
629 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
630 r600_is_zs_format_supported(format)) {
631 retval |= PIPE_BIND_DEPTH_STENCIL;
632 }
633
634 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
635 r600_is_vertex_format_supported(format)) {
636 retval |= PIPE_BIND_VERTEX_BUFFER;
637 }
638
639 if (usage & PIPE_BIND_TRANSFER_READ)
640 retval |= PIPE_BIND_TRANSFER_READ;
641 if (usage & PIPE_BIND_TRANSFER_WRITE)
642 retval |= PIPE_BIND_TRANSFER_WRITE;
643
644 return retval == usage;
645 }
646
647 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
648 {
649 struct radeon_winsys_cs *cs = rctx->cs;
650 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
651 float offset_units = state->offset_units;
652 float offset_scale = state->offset_scale;
653
654 switch (state->zs_format) {
655 case PIPE_FORMAT_Z24X8_UNORM:
656 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
657 offset_units *= 2.0f;
658 break;
659 case PIPE_FORMAT_Z16_UNORM:
660 offset_units *= 4.0f;
661 break;
662 default:;
663 }
664
665 r600_write_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
666 r600_write_value(cs, fui(offset_scale));
667 r600_write_value(cs, fui(offset_units));
668 r600_write_value(cs, fui(offset_scale));
669 r600_write_value(cs, fui(offset_units));
670 }
671
672 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
673 {
674 int j = state->independent_blend_enable ? i : 0;
675
676 unsigned eqRGB = state->rt[j].rgb_func;
677 unsigned srcRGB = state->rt[j].rgb_src_factor;
678 unsigned dstRGB = state->rt[j].rgb_dst_factor;
679
680 unsigned eqA = state->rt[j].alpha_func;
681 unsigned srcA = state->rt[j].alpha_src_factor;
682 unsigned dstA = state->rt[j].alpha_dst_factor;
683 uint32_t bc = 0;
684
685 if (!state->rt[j].blend_enable)
686 return 0;
687
688 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
689 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
690 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
691
692 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
693 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
694 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
695 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
696 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
697 }
698 return bc;
699 }
700
701 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
702 const struct pipe_blend_state *state,
703 int mode)
704 {
705 struct r600_context *rctx = (struct r600_context *)ctx;
706 uint32_t color_control = 0, target_mask = 0;
707 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
708
709 if (!blend) {
710 return NULL;
711 }
712
713 r600_init_command_buffer(&blend->buffer, 20);
714 r600_init_command_buffer(&blend->buffer_no_blend, 20);
715
716 /* R600 does not support per-MRT blends */
717 if (rctx->family > CHIP_R600)
718 color_control |= S_028808_PER_MRT_BLEND(1);
719
720 if (state->logicop_enable) {
721 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
722 } else {
723 color_control |= (0xcc << 16);
724 }
725 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
726 if (state->independent_blend_enable) {
727 for (int i = 0; i < 8; i++) {
728 if (state->rt[i].blend_enable) {
729 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
730 }
731 target_mask |= (state->rt[i].colormask << (4 * i));
732 }
733 } else {
734 for (int i = 0; i < 8; i++) {
735 if (state->rt[0].blend_enable) {
736 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
737 }
738 target_mask |= (state->rt[0].colormask << (4 * i));
739 }
740 }
741
742 if (target_mask)
743 color_control |= S_028808_SPECIAL_OP(mode);
744 else
745 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
746
747 /* only MRT0 has dual src blend */
748 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
749 blend->cb_target_mask = target_mask;
750 blend->cb_color_control = color_control;
751 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
752 blend->alpha_to_one = state->alpha_to_one;
753
754 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
755 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
756 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
757 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
758 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
759 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
760
761 /* Copy over the registers set so far into buffer_no_blend. */
762 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
763 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
764
765 /* Only add blend registers if blending is enabled. */
766 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
767 return blend;
768 }
769
770 /* The first R600 does not support per-MRT blends */
771 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
772 r600_get_blend_control(state, 0));
773
774 if (rctx->family > CHIP_R600) {
775 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
776 for (int i = 0; i < 8; i++) {
777 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
778 }
779 }
780 return blend;
781 }
782
783 static void *r600_create_blend_state(struct pipe_context *ctx,
784 const struct pipe_blend_state *state)
785 {
786 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
787 }
788
789 static void *r600_create_dsa_state(struct pipe_context *ctx,
790 const struct pipe_depth_stencil_alpha_state *state)
791 {
792 unsigned db_depth_control, alpha_test_control, alpha_ref;
793 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
794
795 if (dsa == NULL) {
796 return NULL;
797 }
798
799 r600_init_command_buffer(&dsa->buffer, 3);
800
801 dsa->valuemask[0] = state->stencil[0].valuemask;
802 dsa->valuemask[1] = state->stencil[1].valuemask;
803 dsa->writemask[0] = state->stencil[0].writemask;
804 dsa->writemask[1] = state->stencil[1].writemask;
805
806 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
807 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
808 S_028800_ZFUNC(state->depth.func);
809
810 /* stencil */
811 if (state->stencil[0].enabled) {
812 db_depth_control |= S_028800_STENCIL_ENABLE(1);
813 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
814 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
815 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
816 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
817
818 if (state->stencil[1].enabled) {
819 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
820 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
821 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
822 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
823 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
824 }
825 }
826
827 /* alpha */
828 alpha_test_control = 0;
829 alpha_ref = 0;
830 if (state->alpha.enabled) {
831 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
832 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
833 alpha_ref = fui(state->alpha.ref_value);
834 }
835 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
836 dsa->alpha_ref = alpha_ref;
837
838 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
839 return dsa;
840 }
841
842 static void *r600_create_rs_state(struct pipe_context *ctx,
843 const struct pipe_rasterizer_state *state)
844 {
845 struct r600_context *rctx = (struct r600_context *)ctx;
846 unsigned tmp, sc_mode_cntl, spi_interp;
847 float psize_min, psize_max;
848 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
849
850 if (rs == NULL) {
851 return NULL;
852 }
853
854 r600_init_command_buffer(&rs->buffer, 30);
855
856 rs->flatshade = state->flatshade;
857 rs->sprite_coord_enable = state->sprite_coord_enable;
858 rs->two_side = state->light_twoside;
859 rs->clip_plane_enable = state->clip_plane_enable;
860 rs->pa_sc_line_stipple = state->line_stipple_enable ?
861 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
862 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
863 rs->pa_cl_clip_cntl =
864 S_028810_PS_UCP_MODE(3) |
865 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
866 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
867 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
868 rs->multisample_enable = state->multisample;
869
870 /* offset */
871 rs->offset_units = state->offset_units;
872 rs->offset_scale = state->offset_scale * 12.0f;
873 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
874
875 if (state->point_size_per_vertex) {
876 psize_min = util_get_min_point_size(state);
877 psize_max = 8192;
878 } else {
879 /* Force the point size to be as if the vertex output was disabled. */
880 psize_min = state->point_size;
881 psize_max = state->point_size;
882 }
883
884 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
885 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
886 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
887 if (rctx->chip_class >= R700) {
888 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
889 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
890 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
891 } else {
892 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
893 rs->scissor_enable = state->scissor;
894 }
895
896 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
897 if (state->sprite_coord_enable) {
898 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
899 S_0286D4_PNT_SPRITE_OVRD_X(2) |
900 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
901 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
902 S_0286D4_PNT_SPRITE_OVRD_W(1);
903 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
904 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
905 }
906 }
907
908 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
909 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
910 tmp = r600_pack_float_12p4(state->point_size/2);
911 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
912 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
913 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
914 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
915 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
916 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
917 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
918
919 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
920 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
921 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
922 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
923 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
924 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
925 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
926 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
927 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
928 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
929 S_028814_FACE(!state->front_ccw) |
930 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
931 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
932 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
933 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
934 state->fill_back != PIPE_POLYGON_MODE_FILL) |
935 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
936 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
937 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
938 return rs;
939 }
940
941 static void *r600_create_sampler_state(struct pipe_context *ctx,
942 const struct pipe_sampler_state *state)
943 {
944 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
945 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
946
947 if (ss == NULL) {
948 return NULL;
949 }
950
951 ss->seamless_cube_map = state->seamless_cube_map;
952 ss->border_color_use = sampler_state_needs_border_color(state);
953
954 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
955 ss->tex_sampler_words[0] =
956 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
957 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
958 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
959 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
960 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
961 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
962 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
963 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
964 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
965 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
966 ss->tex_sampler_words[1] =
967 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
968 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
969 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
970 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
971 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
972
973 if (ss->border_color_use) {
974 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
975 }
976 return ss;
977 }
978
979 struct pipe_sampler_view *
980 r600_create_sampler_view_custom(struct pipe_context *ctx,
981 struct pipe_resource *texture,
982 const struct pipe_sampler_view *state,
983 unsigned width_first_level, unsigned height_first_level)
984 {
985 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
986 struct r600_texture *tmp = (struct r600_texture*)texture;
987 unsigned format, endian;
988 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
989 unsigned char swizzle[4], array_mode = 0;
990 unsigned width, height, depth, offset_level, last_level;
991
992 if (view == NULL)
993 return NULL;
994
995 /* initialize base object */
996 view->base = *state;
997 view->base.texture = NULL;
998 pipe_reference(NULL, &texture->reference);
999 view->base.texture = texture;
1000 view->base.reference.count = 1;
1001 view->base.context = ctx;
1002
1003 swizzle[0] = state->swizzle_r;
1004 swizzle[1] = state->swizzle_g;
1005 swizzle[2] = state->swizzle_b;
1006 swizzle[3] = state->swizzle_a;
1007
1008 format = r600_translate_texformat(ctx->screen, state->format,
1009 swizzle,
1010 &word4, &yuv_format);
1011 assert(format != ~0);
1012 if (format == ~0) {
1013 FREE(view);
1014 return NULL;
1015 }
1016
1017 if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) {
1018 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1019 FREE(view);
1020 return NULL;
1021 }
1022 tmp = tmp->flushed_depth_texture;
1023 }
1024
1025 endian = r600_colorformat_endian_swap(format);
1026
1027 offset_level = state->u.tex.first_level;
1028 last_level = state->u.tex.last_level - offset_level;
1029 width = width_first_level;
1030 height = height_first_level;
1031 depth = tmp->surface.level[offset_level].npix_z;
1032 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1033
1034 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1035 height = 1;
1036 depth = texture->array_size;
1037 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1038 depth = texture->array_size;
1039 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
1040 depth = texture->array_size / 6;
1041 switch (tmp->surface.level[offset_level].mode) {
1042 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1043 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1044 break;
1045 case RADEON_SURF_MODE_1D:
1046 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1047 break;
1048 case RADEON_SURF_MODE_2D:
1049 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1050 break;
1051 case RADEON_SURF_MODE_LINEAR:
1052 default:
1053 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1054 break;
1055 }
1056
1057 view->tex_resource = &tmp->resource;
1058 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1059 S_038000_TILE_MODE(array_mode) |
1060 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
1061 S_038000_PITCH((pitch / 8) - 1) |
1062 S_038000_TEX_WIDTH(width - 1));
1063 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
1064 S_038004_TEX_DEPTH(depth - 1) |
1065 S_038004_DATA_FORMAT(format));
1066 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
1067 if (offset_level >= tmp->surface.last_level) {
1068 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
1069 } else {
1070 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1071 }
1072 view->tex_resource_words[4] = (word4 |
1073 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1074 S_038010_REQUEST_SIZE(1) |
1075 S_038010_ENDIAN_SWAP(endian) |
1076 S_038010_BASE_LEVEL(0));
1077 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1078 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1079 if (texture->nr_samples > 1) {
1080 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1081 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
1082 } else {
1083 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
1084 }
1085 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1086 S_038018_MAX_ANISO(4 /* max 16 samples */));
1087 return &view->base;
1088 }
1089
1090 static struct pipe_sampler_view *
1091 r600_create_sampler_view(struct pipe_context *ctx,
1092 struct pipe_resource *tex,
1093 const struct pipe_sampler_view *state)
1094 {
1095 struct r600_texture *rtex = (struct r600_texture*)tex;
1096
1097 return r600_create_sampler_view_custom(ctx, tex, state,
1098 rtex->surface.level[state->u.tex.first_level].npix_x,
1099 rtex->surface.level[state->u.tex.first_level].npix_y);
1100 }
1101
1102 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1103 {
1104 struct radeon_winsys_cs *cs = rctx->cs;
1105 struct pipe_clip_state *state = &rctx->clip_state.state;
1106
1107 r600_write_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
1108 r600_write_array(cs, 6*4, (unsigned*)state);
1109 }
1110
1111 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1112 const struct pipe_poly_stipple *state)
1113 {
1114 }
1115
1116 static void r600_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
1117 {
1118 struct radeon_winsys_cs *cs = rctx->cs;
1119 struct pipe_scissor_state *state = &rctx->scissor.scissor;
1120
1121 if (rctx->chip_class != R600 || rctx->scissor.enable) {
1122 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1123 r600_write_value(cs, S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) |
1124 S_028240_WINDOW_OFFSET_DISABLE(1));
1125 r600_write_value(cs, S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy));
1126 } else {
1127 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1128 r600_write_value(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1129 S_028240_WINDOW_OFFSET_DISABLE(1));
1130 r600_write_value(cs, S_028244_BR_X(8192) | S_028244_BR_Y(8192));
1131 }
1132 }
1133
1134 static void r600_set_scissor_state(struct pipe_context *ctx,
1135 const struct pipe_scissor_state *state)
1136 {
1137 struct r600_context *rctx = (struct r600_context *)ctx;
1138
1139 rctx->scissor.scissor = *state;
1140
1141 if (rctx->chip_class == R600 && !rctx->scissor.enable)
1142 return;
1143
1144 rctx->scissor.atom.dirty = true;
1145 }
1146
1147 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
1148 unsigned size, unsigned alignment)
1149 {
1150 struct pipe_resource buffer;
1151
1152 memset(&buffer, 0, sizeof buffer);
1153 buffer.target = PIPE_BUFFER;
1154 buffer.format = PIPE_FORMAT_R8_UNORM;
1155 buffer.bind = PIPE_BIND_CUSTOM;
1156 buffer.usage = PIPE_USAGE_STATIC;
1157 buffer.flags = 0;
1158 buffer.width0 = size;
1159 buffer.height0 = 1;
1160 buffer.depth0 = 1;
1161 buffer.array_size = 1;
1162
1163 return (struct r600_resource*)
1164 r600_buffer_create(&rscreen->screen, &buffer, alignment);
1165 }
1166
1167 static void r600_init_color_surface(struct r600_context *rctx,
1168 struct r600_surface *surf,
1169 bool force_cmask_fmask)
1170 {
1171 struct r600_screen *rscreen = rctx->screen;
1172 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1173 unsigned level = surf->base.u.tex.level;
1174 unsigned pitch, slice;
1175 unsigned color_info;
1176 unsigned format, swap, ntype, endian;
1177 unsigned offset;
1178 const struct util_format_description *desc;
1179 int i;
1180 bool blend_bypass = 0, blend_clamp = 1;
1181
1182 if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
1183 r600_init_flushed_depth_texture(&rctx->context, surf->base.texture, NULL);
1184 rtex = rtex->flushed_depth_texture;
1185 assert(rtex);
1186 }
1187
1188 offset = rtex->surface.level[level].offset;
1189 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1190 offset += rtex->surface.level[level].slice_size *
1191 surf->base.u.tex.first_layer;
1192 }
1193 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1194 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1195 if (slice) {
1196 slice = slice - 1;
1197 }
1198 color_info = 0;
1199 switch (rtex->surface.level[level].mode) {
1200 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1201 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1202 break;
1203 case RADEON_SURF_MODE_1D:
1204 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1205 break;
1206 case RADEON_SURF_MODE_2D:
1207 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1208 break;
1209 case RADEON_SURF_MODE_LINEAR:
1210 default:
1211 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1212 break;
1213 }
1214
1215 desc = util_format_description(surf->base.format);
1216
1217 for (i = 0; i < 4; i++) {
1218 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1219 break;
1220 }
1221 }
1222
1223 ntype = V_0280A0_NUMBER_UNORM;
1224 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1225 ntype = V_0280A0_NUMBER_SRGB;
1226 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1227 if (desc->channel[i].normalized)
1228 ntype = V_0280A0_NUMBER_SNORM;
1229 else if (desc->channel[i].pure_integer)
1230 ntype = V_0280A0_NUMBER_SINT;
1231 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1232 if (desc->channel[i].normalized)
1233 ntype = V_0280A0_NUMBER_UNORM;
1234 else if (desc->channel[i].pure_integer)
1235 ntype = V_0280A0_NUMBER_UINT;
1236 }
1237
1238 format = r600_translate_colorformat(surf->base.format);
1239 assert(format != ~0);
1240
1241 swap = r600_translate_colorswap(surf->base.format);
1242 assert(swap != ~0);
1243
1244 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1245 endian = ENDIAN_NONE;
1246 } else {
1247 endian = r600_colorformat_endian_swap(format);
1248 }
1249
1250 /* set blend bypass according to docs if SINT/UINT or
1251 8/24 COLOR variants */
1252 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1253 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1254 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1255 blend_clamp = 0;
1256 blend_bypass = 1;
1257 }
1258
1259 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
1260
1261 color_info |= S_0280A0_FORMAT(format) |
1262 S_0280A0_COMP_SWAP(swap) |
1263 S_0280A0_BLEND_BYPASS(blend_bypass) |
1264 S_0280A0_BLEND_CLAMP(blend_clamp) |
1265 S_0280A0_NUMBER_TYPE(ntype) |
1266 S_0280A0_ENDIAN(endian);
1267
1268 /* EXPORT_NORM is an optimzation that can be enabled for better
1269 * performance in certain cases
1270 */
1271 if (rctx->chip_class == R600) {
1272 /* EXPORT_NORM can be enabled if:
1273 * - 11-bit or smaller UNORM/SNORM/SRGB
1274 * - BLEND_CLAMP is enabled
1275 * - BLEND_FLOAT32 is disabled
1276 */
1277 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1278 (desc->channel[i].size < 12 &&
1279 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1280 ntype != V_0280A0_NUMBER_UINT &&
1281 ntype != V_0280A0_NUMBER_SINT) &&
1282 G_0280A0_BLEND_CLAMP(color_info) &&
1283 !G_0280A0_BLEND_FLOAT32(color_info)) {
1284 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1285 surf->export_16bpc = true;
1286 }
1287 } else {
1288 /* EXPORT_NORM can be enabled if:
1289 * - 11-bit or smaller UNORM/SNORM/SRGB
1290 * - 16-bit or smaller FLOAT
1291 */
1292 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1293 ((desc->channel[i].size < 12 &&
1294 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1295 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1296 (desc->channel[i].size < 17 &&
1297 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1298 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1299 surf->export_16bpc = true;
1300 }
1301 }
1302
1303 /* These might not always be initialized to zero. */
1304 surf->cb_color_base = offset >> 8;
1305 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
1306 S_028060_SLICE_TILE_MAX(slice);
1307 surf->cb_color_fmask = surf->cb_color_base;
1308 surf->cb_color_cmask = surf->cb_color_base;
1309 surf->cb_color_mask = 0;
1310
1311 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1312 &rtex->resource.b.b);
1313 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1314 &rtex->resource.b.b);
1315
1316 if (rtex->cmask_size) {
1317 surf->cb_color_cmask = rtex->cmask_offset >> 8;
1318 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask_slice_tile_max);
1319
1320 if (rtex->fmask_size) {
1321 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1322 surf->cb_color_fmask = rtex->fmask_offset >> 8;
1323 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(slice);
1324 } else { /* cmask only */
1325 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
1326 }
1327 } else if (force_cmask_fmask) {
1328 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1329 *
1330 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1331 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1332 * because it's not an MSAA buffer.
1333 */
1334 struct r600_cmask_info cmask;
1335 struct r600_fmask_info fmask;
1336
1337 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
1338 r600_texture_get_fmask_info(rscreen, rtex, 8, &fmask);
1339
1340 /* CMASK. */
1341 if (!rctx->dummy_cmask ||
1342 rctx->dummy_cmask->buf->size < cmask.size ||
1343 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1344 struct pipe_transfer *transfer;
1345 void *ptr;
1346
1347 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1348 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1349
1350 /* Set the contents to 0xCC. */
1351 ptr = pipe_buffer_map(&rctx->context, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1352 memset(ptr, 0xCC, cmask.size);
1353 pipe_buffer_unmap(&rctx->context, transfer);
1354 }
1355 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1356 &rctx->dummy_cmask->b.b);
1357
1358 /* FMASK. */
1359 if (!rctx->dummy_fmask ||
1360 rctx->dummy_fmask->buf->size < fmask.size ||
1361 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1362 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1363 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1364
1365 }
1366 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1367 &rctx->dummy_fmask->b.b);
1368
1369 /* Init the registers. */
1370 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1371 surf->cb_color_cmask = 0;
1372 surf->cb_color_fmask = 0;
1373 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1374 S_028100_FMASK_TILE_MAX(slice);
1375 }
1376
1377 surf->cb_color_info = color_info;
1378
1379 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1380 surf->cb_color_view = 0;
1381 } else {
1382 surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
1383 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
1384 }
1385
1386 surf->color_initialized = true;
1387 }
1388
1389 static void r600_init_depth_surface(struct r600_context *rctx,
1390 struct r600_surface *surf)
1391 {
1392 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1393 unsigned level, pitch, slice, format, offset, array_mode;
1394
1395 level = surf->base.u.tex.level;
1396 offset = rtex->surface.level[level].offset;
1397 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1398 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1399 if (slice) {
1400 slice = slice - 1;
1401 }
1402 switch (rtex->surface.level[level].mode) {
1403 case RADEON_SURF_MODE_2D:
1404 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1405 break;
1406 case RADEON_SURF_MODE_1D:
1407 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1408 case RADEON_SURF_MODE_LINEAR:
1409 default:
1410 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1411 break;
1412 }
1413
1414 format = r600_translate_dbformat(surf->base.format);
1415 assert(format != ~0);
1416
1417 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1418 surf->db_depth_base = offset >> 8;
1419 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1420 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1421 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1422 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1423
1424 switch (surf->base.format) {
1425 case PIPE_FORMAT_Z24X8_UNORM:
1426 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1427 surf->pa_su_poly_offset_db_fmt_cntl =
1428 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1429 break;
1430 case PIPE_FORMAT_Z32_FLOAT:
1431 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1432 surf->pa_su_poly_offset_db_fmt_cntl =
1433 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1434 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1435 break;
1436 case PIPE_FORMAT_Z16_UNORM:
1437 surf->pa_su_poly_offset_db_fmt_cntl =
1438 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1439 break;
1440 default:;
1441 }
1442
1443 surf->depth_initialized = true;
1444 }
1445
1446 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1447 const struct pipe_framebuffer_state *state)
1448 {
1449 struct r600_context *rctx = (struct r600_context *)ctx;
1450 struct r600_surface *surf;
1451 struct r600_texture *rtex;
1452 unsigned i;
1453
1454 if (rctx->framebuffer.state.nr_cbufs) {
1455 rctx->flags |= R600_CONTEXT_WAIT_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1456
1457 if (rctx->chip_class >= R700 &&
1458 rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
1459 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
1460 }
1461 }
1462 if (rctx->framebuffer.state.zsbuf) {
1463 rctx->flags |= R600_CONTEXT_WAIT_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1464 }
1465
1466 /* Set the new state. */
1467 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1468
1469 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1470 rctx->framebuffer.cb0_is_integer = state->nr_cbufs &&
1471 util_format_is_pure_integer(state->cbufs[0]->format);
1472 rctx->framebuffer.compressed_cb_mask = 0;
1473 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1474 state->cbufs[0]->texture->nr_samples > 1 &&
1475 state->cbufs[1]->texture->nr_samples <= 1;
1476
1477 if (state->nr_cbufs)
1478 rctx->framebuffer.nr_samples = state->cbufs[0]->texture->nr_samples;
1479 else if (state->zsbuf)
1480 rctx->framebuffer.nr_samples = state->zsbuf->texture->nr_samples;
1481 else
1482 rctx->framebuffer.nr_samples = 0;
1483
1484 /* Colorbuffers. */
1485 for (i = 0; i < state->nr_cbufs; i++) {
1486 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1487 bool force_cmask_fmask = rctx->chip_class == R600 &&
1488 rctx->framebuffer.is_msaa_resolve &&
1489 i == 1;
1490
1491 surf = (struct r600_surface*)state->cbufs[i];
1492 rtex = (struct r600_texture*)surf->base.texture;
1493
1494 if (!surf->color_initialized || force_cmask_fmask) {
1495 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1496 if (force_cmask_fmask) {
1497 /* re-initialize later without compression */
1498 surf->color_initialized = false;
1499 }
1500 }
1501
1502 if (!surf->export_16bpc) {
1503 rctx->framebuffer.export_16bpc = false;
1504 }
1505
1506 if (rtex->fmask_size && rtex->cmask_size) {
1507 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1508 }
1509 }
1510
1511 /* Update alpha-test state dependencies.
1512 * Alpha-test is done on the first colorbuffer only. */
1513 if (state->nr_cbufs) {
1514 surf = (struct r600_surface*)state->cbufs[0];
1515 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1516 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1517 rctx->alphatest_state.atom.dirty = true;
1518 }
1519 }
1520
1521 /* ZS buffer. */
1522 if (state->zsbuf) {
1523 surf = (struct r600_surface*)state->zsbuf;
1524
1525 if (!surf->depth_initialized) {
1526 r600_init_depth_surface(rctx, surf);
1527 }
1528
1529 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1530 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1531 rctx->poly_offset_state.atom.dirty = true;
1532 }
1533 }
1534
1535 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1536 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1537 rctx->cb_misc_state.atom.dirty = true;
1538 }
1539
1540 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1541 rctx->alphatest_state.bypass = false;
1542 rctx->alphatest_state.atom.dirty = true;
1543 }
1544
1545 r600_update_db_shader_control(rctx);
1546
1547 /* Calculate the CS size. */
1548 rctx->framebuffer.atom.num_dw =
1549 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1550
1551 if (rctx->framebuffer.state.nr_cbufs) {
1552 rctx->framebuffer.atom.num_dw += 6 * (2 + rctx->framebuffer.state.nr_cbufs);
1553 rctx->framebuffer.atom.num_dw += 6 * rctx->framebuffer.state.nr_cbufs; /* relocs */
1554
1555 }
1556 if (rctx->framebuffer.state.zsbuf) {
1557 rctx->framebuffer.atom.num_dw += 18;
1558 } else if (rctx->screen->info.drm_minor >= 18) {
1559 rctx->framebuffer.atom.num_dw += 3;
1560 }
1561 if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770) {
1562 rctx->framebuffer.atom.num_dw += 2;
1563 }
1564
1565 rctx->framebuffer.atom.dirty = true;
1566 }
1567
1568 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1569 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1570 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1571 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1572 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1573
1574 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1575 {
1576 static uint32_t sample_locs_2x[] = {
1577 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1578 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1579 };
1580 static unsigned max_dist_2x = 4;
1581 static uint32_t sample_locs_4x[] = {
1582 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1583 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1584 };
1585 static unsigned max_dist_4x = 6;
1586 static uint32_t sample_locs_8x[] = {
1587 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1588 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1589 };
1590 static unsigned max_dist_8x = 7;
1591
1592 struct radeon_winsys_cs *cs = rctx->cs;
1593 unsigned max_dist = 0;
1594
1595 if (rctx->family == CHIP_R600) {
1596 switch (nr_samples) {
1597 default:
1598 nr_samples = 0;
1599 break;
1600 case 2:
1601 r600_write_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1602 max_dist = max_dist_2x;
1603 break;
1604 case 4:
1605 r600_write_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1606 max_dist = max_dist_4x;
1607 break;
1608 case 8:
1609 r600_write_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1610 r600_write_value(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1611 r600_write_value(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1612 max_dist = max_dist_8x;
1613 break;
1614 }
1615 } else {
1616 switch (nr_samples) {
1617 default:
1618 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1619 r600_write_value(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1620 r600_write_value(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1621 nr_samples = 0;
1622 break;
1623 case 2:
1624 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1625 r600_write_value(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1626 r600_write_value(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1627 max_dist = max_dist_2x;
1628 break;
1629 case 4:
1630 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1631 r600_write_value(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1632 r600_write_value(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1633 max_dist = max_dist_4x;
1634 break;
1635 case 8:
1636 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1637 r600_write_value(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1638 r600_write_value(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1639 max_dist = max_dist_8x;
1640 break;
1641 }
1642 }
1643
1644 if (nr_samples > 1) {
1645 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1646 r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
1647 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1648 r600_write_value(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1649 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1650 } else {
1651 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1652 r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1653 r600_write_value(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1654 }
1655 }
1656
1657 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1658 {
1659 struct radeon_winsys_cs *cs = rctx->cs;
1660 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1661 unsigned nr_cbufs = state->nr_cbufs;
1662 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1663 unsigned i, sbu = 0;
1664
1665 /* Colorbuffers. */
1666 r600_write_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1667 for (i = 0; i < nr_cbufs; i++) {
1668 r600_write_value(cs, cb[i]->cb_color_info);
1669 }
1670 /* set CB_COLOR1_INFO for possible dual-src blending */
1671 if (i == 1) {
1672 r600_write_value(cs, cb[0]->cb_color_info);
1673 i++;
1674 }
1675 for (; i < 8; i++) {
1676 r600_write_value(cs, 0);
1677 }
1678
1679 if (nr_cbufs) {
1680 /* COLOR_BASE */
1681 r600_write_context_reg_seq(cs, R_028040_CB_COLOR0_BASE, nr_cbufs);
1682 for (i = 0; i < nr_cbufs; i++) {
1683 r600_write_value(cs, cb[i]->cb_color_base);
1684 }
1685
1686 /* relocations */
1687 for (i = 0; i < nr_cbufs; i++) {
1688 unsigned reloc = r600_context_bo_reloc(rctx,
1689 (struct r600_resource*)cb[i]->base.texture,
1690 RADEON_USAGE_READWRITE);
1691 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1692 r600_write_value(cs, reloc);
1693 }
1694
1695 r600_write_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1696 for (i = 0; i < nr_cbufs; i++) {
1697 r600_write_value(cs, cb[i]->cb_color_size);
1698 }
1699
1700 r600_write_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1701 for (i = 0; i < nr_cbufs; i++) {
1702 r600_write_value(cs, cb[i]->cb_color_view);
1703 }
1704
1705 r600_write_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1706 for (i = 0; i < nr_cbufs; i++) {
1707 r600_write_value(cs, cb[i]->cb_color_mask);
1708 }
1709
1710 /* FMASK. */
1711 r600_write_context_reg_seq(cs, R_0280E0_CB_COLOR0_FRAG, nr_cbufs);
1712 for (i = 0; i < nr_cbufs; i++) {
1713 r600_write_value(cs, cb[i]->cb_color_fmask);
1714 }
1715 /* relocations */
1716 for (i = 0; i < nr_cbufs; i++) {
1717 unsigned reloc = r600_context_bo_reloc(rctx,
1718 cb[i]->cb_buffer_fmask,
1719 RADEON_USAGE_READWRITE);
1720 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1721 r600_write_value(cs, reloc);
1722 }
1723
1724 /* CMASK. */
1725 r600_write_context_reg_seq(cs, R_0280C0_CB_COLOR0_TILE, nr_cbufs);
1726 for (i = 0; i < nr_cbufs; i++) {
1727 r600_write_value(cs, cb[i]->cb_color_cmask);
1728 }
1729 /* relocations */
1730 for (i = 0; i < nr_cbufs; i++) {
1731 unsigned reloc = r600_context_bo_reloc(rctx,
1732 cb[i]->cb_buffer_cmask,
1733 RADEON_USAGE_READWRITE);
1734 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1735 r600_write_value(cs, reloc);
1736 }
1737
1738 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1739 }
1740
1741 /* SURFACE_BASE_UPDATE */
1742 if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770 && sbu) {
1743 r600_write_value(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1744 r600_write_value(cs, sbu);
1745 sbu = 0;
1746 }
1747
1748 /* Zbuffer. */
1749 if (state->zsbuf) {
1750 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1751 unsigned reloc = r600_context_bo_reloc(rctx,
1752 (struct r600_resource*)state->zsbuf->texture,
1753 RADEON_USAGE_READWRITE);
1754
1755 r600_write_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1756 surf->pa_su_poly_offset_db_fmt_cntl);
1757
1758 r600_write_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1759 r600_write_value(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1760 r600_write_value(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1761 r600_write_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1762 r600_write_value(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1763 r600_write_value(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1764
1765 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1766 r600_write_value(cs, reloc);
1767
1768 r600_write_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1769
1770 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1771 } else if (rctx->screen->info.drm_minor >= 18) {
1772 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1773 * Older kernels are out of luck. */
1774 r600_write_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1775 }
1776
1777 /* SURFACE_BASE_UPDATE */
1778 if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770 && sbu) {
1779 r600_write_value(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1780 r600_write_value(cs, sbu);
1781 sbu = 0;
1782 }
1783
1784 /* Framebuffer dimensions. */
1785 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1786 r600_write_value(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1787 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1788 r600_write_value(cs, S_028244_BR_X(state->width) |
1789 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1790
1791 if (rctx->framebuffer.is_msaa_resolve) {
1792 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1793 } else {
1794 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1795 * will assure that the alpha-test will work even if there is
1796 * no colorbuffer bound. */
1797 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1798 (1ull << MAX2(nr_cbufs, 1)) - 1);
1799 }
1800
1801 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1802 }
1803
1804 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1805 {
1806 struct radeon_winsys_cs *cs = rctx->cs;
1807 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1808
1809 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1810 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1811 if (rctx->chip_class == R600) {
1812 r600_write_value(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1813 r600_write_value(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1814 } else {
1815 r600_write_value(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1816 r600_write_value(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1817 }
1818 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1819 } else {
1820 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1821 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1822 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1823
1824 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1825 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1826 /* Always enable the first color output to make sure alpha-test works even without one. */
1827 r600_write_value(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1828 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1829 a->cb_color_control |
1830 S_028808_MULTIWRITE_ENABLE(multiwrite));
1831 }
1832 }
1833
1834 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1835 {
1836 struct radeon_winsys_cs *cs = rctx->cs;
1837 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1838 unsigned db_render_control = 0;
1839 unsigned db_render_override =
1840 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
1841 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1842 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1843
1844 if (a->occlusion_query_enabled) {
1845 if (rctx->chip_class >= R700) {
1846 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1847 }
1848 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1849 }
1850 if (a->flush_depthstencil_through_cb) {
1851 assert(a->copy_depth || a->copy_stencil);
1852
1853 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1854 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1855 S_028D0C_COPY_CENTROID(1) |
1856 S_028D0C_COPY_SAMPLE(a->copy_sample);
1857 } else if (a->flush_depthstencil_in_place) {
1858 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(1) |
1859 S_028D0C_STENCIL_COMPRESS_DISABLE(1);
1860 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1861 }
1862
1863 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1864 r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1865 r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1866 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1867 }
1868
1869 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1870 {
1871 struct radeon_winsys_cs *cs = rctx->cs;
1872 struct r600_config_state *a = (struct r600_config_state*)atom;
1873
1874 r600_write_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1875 }
1876
1877 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1878 {
1879 struct radeon_winsys_cs *cs = rctx->cs;
1880 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1881
1882 while (dirty_mask) {
1883 struct pipe_vertex_buffer *vb;
1884 struct r600_resource *rbuffer;
1885 unsigned offset;
1886 unsigned buffer_index = u_bit_scan(&dirty_mask);
1887
1888 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1889 rbuffer = (struct r600_resource*)vb->buffer;
1890 assert(rbuffer);
1891
1892 offset = vb->buffer_offset;
1893
1894 /* fetch resources start at index 320 */
1895 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1896 r600_write_value(cs, (320 + buffer_index) * 7);
1897 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1898 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1899 r600_write_value(cs, /* RESOURCEi_WORD2 */
1900 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1901 S_038008_STRIDE(vb->stride));
1902 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1903 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1904 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1905 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1906
1907 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1908 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1909 }
1910 }
1911
1912 static void r600_emit_constant_buffers(struct r600_context *rctx,
1913 struct r600_constbuf_state *state,
1914 unsigned buffer_id_base,
1915 unsigned reg_alu_constbuf_size,
1916 unsigned reg_alu_const_cache)
1917 {
1918 struct radeon_winsys_cs *cs = rctx->cs;
1919 uint32_t dirty_mask = state->dirty_mask;
1920
1921 while (dirty_mask) {
1922 struct pipe_constant_buffer *cb;
1923 struct r600_resource *rbuffer;
1924 unsigned offset;
1925 unsigned buffer_index = ffs(dirty_mask) - 1;
1926
1927 cb = &state->cb[buffer_index];
1928 rbuffer = (struct r600_resource*)cb->buffer;
1929 assert(rbuffer);
1930
1931 offset = cb->buffer_offset;
1932
1933 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1934 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1935 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1936
1937 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1938 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1939
1940 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1941 r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
1942 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1943 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1944 r600_write_value(cs, /* RESOURCEi_WORD2 */
1945 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1946 S_038008_STRIDE(16));
1947 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1948 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1949 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1950 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1951
1952 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1953 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1954
1955 dirty_mask &= ~(1 << buffer_index);
1956 }
1957 state->dirty_mask = 0;
1958 }
1959
1960 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1961 {
1962 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 160,
1963 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1964 R_028980_ALU_CONST_CACHE_VS_0);
1965 }
1966
1967 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1968 {
1969 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
1970 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1971 R_0289C0_ALU_CONST_CACHE_GS_0);
1972 }
1973
1974 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1975 {
1976 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
1977 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1978 R_028940_ALU_CONST_CACHE_PS_0);
1979 }
1980
1981 static void r600_emit_sampler_views(struct r600_context *rctx,
1982 struct r600_samplerview_state *state,
1983 unsigned resource_id_base)
1984 {
1985 struct radeon_winsys_cs *cs = rctx->cs;
1986 uint32_t dirty_mask = state->dirty_mask;
1987
1988 while (dirty_mask) {
1989 struct r600_pipe_sampler_view *rview;
1990 unsigned resource_index = u_bit_scan(&dirty_mask);
1991 unsigned reloc;
1992
1993 rview = state->views[resource_index];
1994 assert(rview);
1995
1996 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1997 r600_write_value(cs, (resource_id_base + resource_index) * 7);
1998 r600_write_array(cs, 7, rview->tex_resource_words);
1999
2000 reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
2001 RADEON_USAGE_READ);
2002 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2003 r600_write_value(cs, reloc);
2004 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2005 r600_write_value(cs, reloc);
2006 }
2007 state->dirty_mask = 0;
2008 }
2009
2010 /* Resource IDs:
2011 * PS: 0 .. +160
2012 * VS: 160 .. +160
2013 * FS: 320 .. +16
2014 * GS: 336 .. +160
2015 */
2016
2017 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2018 {
2019 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 160 + R600_MAX_CONST_BUFFERS);
2020 }
2021
2022 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2023 {
2024 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
2025 }
2026
2027 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2028 {
2029 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
2030 }
2031
2032 static void r600_emit_sampler_states(struct r600_context *rctx,
2033 struct r600_textures_info *texinfo,
2034 unsigned resource_id_base,
2035 unsigned border_color_reg)
2036 {
2037 struct radeon_winsys_cs *cs = rctx->cs;
2038 uint32_t dirty_mask = texinfo->states.dirty_mask;
2039
2040 while (dirty_mask) {
2041 struct r600_pipe_sampler_state *rstate;
2042 struct r600_pipe_sampler_view *rview;
2043 unsigned i = u_bit_scan(&dirty_mask);
2044
2045 rstate = texinfo->states.states[i];
2046 assert(rstate);
2047 rview = texinfo->views.views[i];
2048
2049 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
2050 * filtering between layers.
2051 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
2052 */
2053 if (rview) {
2054 enum pipe_texture_target target = rview->base.texture->target;
2055 if (target == PIPE_TEXTURE_1D_ARRAY ||
2056 target == PIPE_TEXTURE_2D_ARRAY) {
2057 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
2058 texinfo->is_array_sampler[i] = true;
2059 } else {
2060 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
2061 texinfo->is_array_sampler[i] = false;
2062 }
2063 }
2064
2065 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2066 r600_write_value(cs, (resource_id_base + i) * 3);
2067 r600_write_array(cs, 3, rstate->tex_sampler_words);
2068
2069 if (rstate->border_color_use) {
2070 unsigned offset;
2071
2072 offset = border_color_reg;
2073 offset += i * 16;
2074 r600_write_config_reg_seq(cs, offset, 4);
2075 r600_write_array(cs, 4, rstate->border_color.ui);
2076 }
2077 }
2078 texinfo->states.dirty_mask = 0;
2079 }
2080
2081 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2082 {
2083 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
2084 }
2085
2086 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2087 {
2088 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
2089 }
2090
2091 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2092 {
2093 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
2094 }
2095
2096 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
2097 {
2098 struct radeon_winsys_cs *cs = rctx->cs;
2099 unsigned tmp;
2100
2101 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
2102 S_009508_SYNC_GRADIENT(1) |
2103 S_009508_SYNC_WALKER(1) |
2104 S_009508_SYNC_ALIGNER(1);
2105 if (!rctx->seamless_cube_map.enabled) {
2106 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
2107 }
2108 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
2109 }
2110
2111 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2112 {
2113 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2114 uint8_t mask = s->sample_mask;
2115
2116 r600_write_context_reg(rctx->cs, R_028C48_PA_SC_AA_MASK,
2117 mask | (mask << 8) | (mask << 16) | (mask << 24));
2118 }
2119
2120 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2121 {
2122 struct radeon_winsys_cs *cs = rctx->cs;
2123 struct r600_cso_state *state = (struct r600_cso_state*)a;
2124 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2125
2126 r600_write_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
2127 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2128 r600_write_value(cs, r600_context_bo_reloc(rctx, shader->buffer, RADEON_USAGE_READ));
2129 }
2130
2131 void r600_init_state_functions(struct r600_context *rctx)
2132 {
2133 unsigned id = 4;
2134
2135 /* !!!
2136 * To avoid GPU lockup registers must be emited in a specific order
2137 * (no kidding ...). The order below is important and have been
2138 * partialy infered from analyzing fglrx command stream.
2139 *
2140 * Don't reorder atom without carefully checking the effect (GPU lockup
2141 * or piglit regression).
2142 * !!!
2143 */
2144
2145 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
2146
2147 /* shader const */
2148 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
2149 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
2150 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
2151
2152 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2153 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
2154 */
2155 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
2156 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
2157 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
2158 /* resource */
2159 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
2160 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
2161 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
2162 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
2163
2164 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 6);
2165 r600_init_atom(rctx, &rctx->vgt2_state.atom, id++, r600_emit_vgt2_state, 3);
2166
2167 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
2168 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
2169 rctx->sample_mask.sample_mask = ~0;
2170
2171 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
2172 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
2173 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
2174 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
2175 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
2176 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
2177 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
2178 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
2179 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
2180 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
2181 r600_init_atom(rctx, &rctx->scissor.atom, id++, r600_emit_scissor_state, 4);
2182 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
2183 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
2184 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
2185 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
2186
2187 rctx->context.create_blend_state = r600_create_blend_state;
2188 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
2189 rctx->context.create_rasterizer_state = r600_create_rs_state;
2190 rctx->context.create_sampler_state = r600_create_sampler_state;
2191 rctx->context.create_sampler_view = r600_create_sampler_view;
2192 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
2193 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
2194 rctx->context.set_scissor_state = r600_set_scissor_state;
2195 }
2196
2197 /* Adjust GPR allocation on R6xx/R7xx */
2198 bool r600_adjust_gprs(struct r600_context *rctx)
2199 {
2200 unsigned num_ps_gprs = rctx->ps_shader->current->shader.bc.ngpr;
2201 unsigned num_vs_gprs = rctx->vs_shader->current->shader.bc.ngpr;
2202 unsigned new_num_ps_gprs = num_ps_gprs;
2203 unsigned new_num_vs_gprs = num_vs_gprs;
2204 unsigned cur_num_ps_gprs = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2205 unsigned cur_num_vs_gprs = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2206 unsigned def_num_ps_gprs = rctx->default_ps_gprs;
2207 unsigned def_num_vs_gprs = rctx->default_vs_gprs;
2208 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
2209 /* hardware will reserve twice num_clause_temp_gprs */
2210 unsigned max_gprs = def_num_ps_gprs + def_num_vs_gprs + def_num_clause_temp_gprs * 2;
2211 unsigned tmp;
2212
2213 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2214 if (new_num_ps_gprs > cur_num_ps_gprs || new_num_vs_gprs > cur_num_vs_gprs) {
2215 /* try to use switch back to default */
2216 if (new_num_ps_gprs > def_num_ps_gprs || new_num_vs_gprs > def_num_vs_gprs) {
2217 /* always privilege vs stage so that at worst we have the
2218 * pixel stage producing wrong output (not the vertex
2219 * stage) */
2220 new_num_ps_gprs = max_gprs - (new_num_vs_gprs + def_num_clause_temp_gprs * 2);
2221 new_num_vs_gprs = num_vs_gprs;
2222 } else {
2223 new_num_ps_gprs = def_num_ps_gprs;
2224 new_num_vs_gprs = def_num_vs_gprs;
2225 }
2226 } else {
2227 return true;
2228 }
2229
2230 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2231 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2232 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2233 * it will lockup. So in this case just discard the draw command
2234 * and don't change the current gprs repartitions.
2235 */
2236 if (num_ps_gprs > new_num_ps_gprs || num_vs_gprs > new_num_vs_gprs) {
2237 R600_ERR("ps & vs shader require too many register (%d + %d) "
2238 "for a combined maximum of %d\n",
2239 num_ps_gprs, num_vs_gprs, max_gprs);
2240 return false;
2241 }
2242
2243 /* in some case we endup recomputing the current value */
2244 tmp = S_008C04_NUM_PS_GPRS(new_num_ps_gprs) |
2245 S_008C04_NUM_VS_GPRS(new_num_vs_gprs) |
2246 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2247 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp) {
2248 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2249 rctx->config_state.atom.dirty = true;
2250 rctx->flags |= R600_CONTEXT_WAIT_IDLE;
2251 }
2252 return true;
2253 }
2254
2255 void r600_init_atom_start_cs(struct r600_context *rctx)
2256 {
2257 int ps_prio;
2258 int vs_prio;
2259 int gs_prio;
2260 int es_prio;
2261 int num_ps_gprs;
2262 int num_vs_gprs;
2263 int num_gs_gprs;
2264 int num_es_gprs;
2265 int num_temp_gprs;
2266 int num_ps_threads;
2267 int num_vs_threads;
2268 int num_gs_threads;
2269 int num_es_threads;
2270 int num_ps_stack_entries;
2271 int num_vs_stack_entries;
2272 int num_gs_stack_entries;
2273 int num_es_stack_entries;
2274 enum radeon_family family;
2275 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2276 uint32_t tmp;
2277
2278 r600_init_command_buffer(cb, 256);
2279
2280 /* R6xx requires this packet at the start of each command buffer */
2281 if (rctx->chip_class == R600) {
2282 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2283 r600_store_value(cb, 0);
2284 }
2285 /* All asics require this one */
2286 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2287 r600_store_value(cb, 0x80000000);
2288 r600_store_value(cb, 0x80000000);
2289
2290 /* We're setting config registers here. */
2291 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2292 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2293
2294 family = rctx->family;
2295 ps_prio = 0;
2296 vs_prio = 1;
2297 gs_prio = 2;
2298 es_prio = 3;
2299 switch (family) {
2300 case CHIP_R600:
2301 num_ps_gprs = 192;
2302 num_vs_gprs = 56;
2303 num_temp_gprs = 4;
2304 num_gs_gprs = 0;
2305 num_es_gprs = 0;
2306 num_ps_threads = 136;
2307 num_vs_threads = 48;
2308 num_gs_threads = 4;
2309 num_es_threads = 4;
2310 num_ps_stack_entries = 128;
2311 num_vs_stack_entries = 128;
2312 num_gs_stack_entries = 0;
2313 num_es_stack_entries = 0;
2314 break;
2315 case CHIP_RV630:
2316 case CHIP_RV635:
2317 num_ps_gprs = 84;
2318 num_vs_gprs = 36;
2319 num_temp_gprs = 4;
2320 num_gs_gprs = 0;
2321 num_es_gprs = 0;
2322 num_ps_threads = 144;
2323 num_vs_threads = 40;
2324 num_gs_threads = 4;
2325 num_es_threads = 4;
2326 num_ps_stack_entries = 40;
2327 num_vs_stack_entries = 40;
2328 num_gs_stack_entries = 32;
2329 num_es_stack_entries = 16;
2330 break;
2331 case CHIP_RV610:
2332 case CHIP_RV620:
2333 case CHIP_RS780:
2334 case CHIP_RS880:
2335 default:
2336 num_ps_gprs = 84;
2337 num_vs_gprs = 36;
2338 num_temp_gprs = 4;
2339 num_gs_gprs = 0;
2340 num_es_gprs = 0;
2341 num_ps_threads = 136;
2342 num_vs_threads = 48;
2343 num_gs_threads = 4;
2344 num_es_threads = 4;
2345 num_ps_stack_entries = 40;
2346 num_vs_stack_entries = 40;
2347 num_gs_stack_entries = 32;
2348 num_es_stack_entries = 16;
2349 break;
2350 case CHIP_RV670:
2351 num_ps_gprs = 144;
2352 num_vs_gprs = 40;
2353 num_temp_gprs = 4;
2354 num_gs_gprs = 0;
2355 num_es_gprs = 0;
2356 num_ps_threads = 136;
2357 num_vs_threads = 48;
2358 num_gs_threads = 4;
2359 num_es_threads = 4;
2360 num_ps_stack_entries = 40;
2361 num_vs_stack_entries = 40;
2362 num_gs_stack_entries = 32;
2363 num_es_stack_entries = 16;
2364 break;
2365 case CHIP_RV770:
2366 num_ps_gprs = 192;
2367 num_vs_gprs = 56;
2368 num_temp_gprs = 4;
2369 num_gs_gprs = 0;
2370 num_es_gprs = 0;
2371 num_ps_threads = 188;
2372 num_vs_threads = 60;
2373 num_gs_threads = 0;
2374 num_es_threads = 0;
2375 num_ps_stack_entries = 256;
2376 num_vs_stack_entries = 256;
2377 num_gs_stack_entries = 0;
2378 num_es_stack_entries = 0;
2379 break;
2380 case CHIP_RV730:
2381 case CHIP_RV740:
2382 num_ps_gprs = 84;
2383 num_vs_gprs = 36;
2384 num_temp_gprs = 4;
2385 num_gs_gprs = 0;
2386 num_es_gprs = 0;
2387 num_ps_threads = 188;
2388 num_vs_threads = 60;
2389 num_gs_threads = 0;
2390 num_es_threads = 0;
2391 num_ps_stack_entries = 128;
2392 num_vs_stack_entries = 128;
2393 num_gs_stack_entries = 0;
2394 num_es_stack_entries = 0;
2395 break;
2396 case CHIP_RV710:
2397 num_ps_gprs = 192;
2398 num_vs_gprs = 56;
2399 num_temp_gprs = 4;
2400 num_gs_gprs = 0;
2401 num_es_gprs = 0;
2402 num_ps_threads = 144;
2403 num_vs_threads = 48;
2404 num_gs_threads = 0;
2405 num_es_threads = 0;
2406 num_ps_stack_entries = 128;
2407 num_vs_stack_entries = 128;
2408 num_gs_stack_entries = 0;
2409 num_es_stack_entries = 0;
2410 break;
2411 }
2412
2413 rctx->default_ps_gprs = num_ps_gprs;
2414 rctx->default_vs_gprs = num_vs_gprs;
2415 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2416
2417 /* SQ_CONFIG */
2418 tmp = 0;
2419 switch (family) {
2420 case CHIP_RV610:
2421 case CHIP_RV620:
2422 case CHIP_RS780:
2423 case CHIP_RS880:
2424 case CHIP_RV710:
2425 break;
2426 default:
2427 tmp |= S_008C00_VC_ENABLE(1);
2428 break;
2429 }
2430 tmp |= S_008C00_DX9_CONSTS(0);
2431 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2432 tmp |= S_008C00_PS_PRIO(ps_prio);
2433 tmp |= S_008C00_VS_PRIO(vs_prio);
2434 tmp |= S_008C00_GS_PRIO(gs_prio);
2435 tmp |= S_008C00_ES_PRIO(es_prio);
2436 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2437
2438 /* SQ_GPR_RESOURCE_MGMT_2 */
2439 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2440 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2441 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2442 r600_store_value(cb, tmp);
2443
2444 /* SQ_THREAD_RESOURCE_MGMT */
2445 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2446 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2447 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2448 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2449 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2450
2451 /* SQ_STACK_RESOURCE_MGMT_1 */
2452 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2453 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2454 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2455
2456 /* SQ_STACK_RESOURCE_MGMT_2 */
2457 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2458 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2459 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2460
2461 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2462
2463 if (rctx->chip_class >= R700) {
2464 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2465 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2466 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2467 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2468 } else {
2469 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2470 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2471 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2472 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2473 }
2474 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2475 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2476 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2477 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2478 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2479 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2480 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2481 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2482 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2483 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2484
2485 /* to avoid GPU doing any preloading of constant from random address */
2486 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2487 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2488 r600_store_value(cb, 0);
2489 r600_store_value(cb, 0);
2490 r600_store_value(cb, 0);
2491 r600_store_value(cb, 0);
2492 r600_store_value(cb, 0);
2493 r600_store_value(cb, 0);
2494 r600_store_value(cb, 0);
2495 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2496 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2497 r600_store_value(cb, 0);
2498 r600_store_value(cb, 0);
2499 r600_store_value(cb, 0);
2500 r600_store_value(cb, 0);
2501 r600_store_value(cb, 0);
2502 r600_store_value(cb, 0);
2503 r600_store_value(cb, 0);
2504
2505 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2506 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2507 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2508 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2509 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2510 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2511 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2512 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2513 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2514 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2515 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2516 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2517 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2518 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2519
2520 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2521 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2522 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2523
2524 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2525 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2526 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2527 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2528
2529 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2530
2531 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2532
2533 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2534 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2535 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2536
2537 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2538 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2539 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2540 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2541
2542 r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2543 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2544 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2545
2546 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2547 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2548
2549 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2550 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2551 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2552 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2553 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2554
2555 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2556 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2557 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2558
2559 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2560
2561 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2562 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2563
2564 if (rctx->chip_class >= R700) {
2565 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2566 }
2567
2568 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2569 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2570 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2571 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2572 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2573
2574 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2575 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2576 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2577
2578 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2579 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2580 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2581
2582 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2583 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2584 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2585
2586 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2587
2588 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2589 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2590 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2591
2592 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2593 r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2594
2595 if (rctx->chip_class == R700 && rctx->screen->has_streamout)
2596 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2597 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2598 if (rctx->screen->has_streamout) {
2599 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2600 }
2601
2602 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2603 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2604 }
2605
2606 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2607 {
2608 struct r600_context *rctx = (struct r600_context *)ctx;
2609 struct r600_pipe_state *rstate = &shader->rstate;
2610 struct r600_shader *rshader = &shader->shader;
2611 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2612 int pos_index = -1, face_index = -1;
2613 unsigned tmp, sid, ufi = 0;
2614 int need_linear = 0;
2615 unsigned z_export = 0, stencil_export = 0;
2616 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2617
2618 rstate->nregs = 0;
2619
2620 for (i = 0; i < rshader->ninput; i++) {
2621 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2622 pos_index = i;
2623 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2624 face_index = i;
2625
2626 sid = rshader->input[i].spi_sid;
2627
2628 tmp = S_028644_SEMANTIC(sid);
2629
2630 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2631 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2632 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2633 rctx->rasterizer && rctx->rasterizer->flatshade))
2634 tmp |= S_028644_FLAT_SHADE(1);
2635
2636 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2637 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2638 tmp |= S_028644_PT_SPRITE_TEX(1);
2639 }
2640
2641 if (rshader->input[i].centroid)
2642 tmp |= S_028644_SEL_CENTROID(1);
2643
2644 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2645 need_linear = 1;
2646 tmp |= S_028644_SEL_LINEAR(1);
2647 }
2648
2649 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2650 tmp);
2651 }
2652
2653 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2654 for (i = 0; i < rshader->noutput; i++) {
2655 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2656 z_export = 1;
2657 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2658 stencil_export = 1;
2659 }
2660 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2661 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2662 if (rshader->uses_kill)
2663 db_shader_control |= S_02880C_KILL_ENABLE(1);
2664
2665 exports_ps = 0;
2666 for (i = 0; i < rshader->noutput; i++) {
2667 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2668 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2669 exports_ps |= 1;
2670 }
2671 }
2672 num_cout = rshader->nr_ps_color_exports;
2673 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2674 if (!exports_ps) {
2675 /* always at least export 1 component per pixel */
2676 exports_ps = 2;
2677 }
2678
2679 shader->nr_ps_color_outputs = num_cout;
2680
2681 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2682 S_0286CC_PERSP_GRADIENT_ENA(1)|
2683 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2684 spi_input_z = 0;
2685 if (pos_index != -1) {
2686 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2687 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2688 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2689 S_0286CC_BARYC_SAMPLE_CNTL(1));
2690 spi_input_z |= 1;
2691 }
2692
2693 spi_ps_in_control_1 = 0;
2694 if (face_index != -1) {
2695 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2696 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2697 }
2698
2699 /* HW bug in original R600 */
2700 if (rctx->family == CHIP_R600)
2701 ufi = 1;
2702
2703 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2704 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2705 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2706 r600_pipe_state_add_reg_bo(rstate,
2707 R_028840_SQ_PGM_START_PS,
2708 0, shader->bo, RADEON_USAGE_READ);
2709 r600_pipe_state_add_reg(rstate,
2710 R_028850_SQ_PGM_RESOURCES_PS,
2711 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2712 S_028850_STACK_SIZE(rshader->bc.nstack) |
2713 S_028850_UNCACHED_FIRST_INST(ufi));
2714 r600_pipe_state_add_reg(rstate,
2715 R_028854_SQ_PGM_EXPORTS_PS,
2716 exports_ps);
2717 /* only set some bits here, the other bits are set in the dsa state */
2718 shader->db_shader_control = db_shader_control;
2719 shader->ps_depth_export = z_export | stencil_export;
2720
2721 shader->sprite_coord_enable = sprite_coord_enable;
2722 if (rctx->rasterizer)
2723 shader->flatshade = rctx->rasterizer->flatshade;
2724 }
2725
2726 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2727 {
2728 struct r600_context *rctx = (struct r600_context *)ctx;
2729 struct r600_pipe_state *rstate = &shader->rstate;
2730 struct r600_shader *rshader = &shader->shader;
2731 unsigned spi_vs_out_id[10] = {};
2732 unsigned i, tmp, nparams = 0;
2733
2734 /* clear previous register */
2735 rstate->nregs = 0;
2736
2737 for (i = 0; i < rshader->noutput; i++) {
2738 if (rshader->output[i].spi_sid) {
2739 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2740 spi_vs_out_id[nparams / 4] |= tmp;
2741 nparams++;
2742 }
2743 }
2744
2745 for (i = 0; i < 10; i++) {
2746 r600_pipe_state_add_reg(rstate,
2747 R_028614_SPI_VS_OUT_ID_0 + i * 4,
2748 spi_vs_out_id[i]);
2749 }
2750
2751 /* Certain attributes (position, psize, etc.) don't count as params.
2752 * VS is required to export at least one param and r600_shader_from_tgsi()
2753 * takes care of adding a dummy export.
2754 */
2755 if (nparams < 1)
2756 nparams = 1;
2757
2758 r600_pipe_state_add_reg(rstate,
2759 R_0286C4_SPI_VS_OUT_CONFIG,
2760 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2761 r600_pipe_state_add_reg(rstate,
2762 R_028868_SQ_PGM_RESOURCES_VS,
2763 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2764 S_028868_STACK_SIZE(rshader->bc.nstack));
2765 r600_pipe_state_add_reg_bo(rstate,
2766 R_028858_SQ_PGM_START_VS,
2767 0, shader->bo, RADEON_USAGE_READ);
2768
2769 shader->pa_cl_vs_out_cntl =
2770 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2771 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2772 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2773 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2774 }
2775
2776 void *r600_create_resolve_blend(struct r600_context *rctx)
2777 {
2778 struct pipe_blend_state blend;
2779 unsigned i;
2780
2781 memset(&blend, 0, sizeof(blend));
2782 blend.independent_blend_enable = true;
2783 for (i = 0; i < 2; i++) {
2784 blend.rt[i].colormask = 0xf;
2785 blend.rt[i].blend_enable = 1;
2786 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2787 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2788 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2789 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2790 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2791 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2792 }
2793 return r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2794 }
2795
2796 void *r700_create_resolve_blend(struct r600_context *rctx)
2797 {
2798 struct pipe_blend_state blend;
2799
2800 memset(&blend, 0, sizeof(blend));
2801 blend.independent_blend_enable = true;
2802 blend.rt[0].colormask = 0xf;
2803 return r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2804 }
2805
2806 void *r600_create_decompress_blend(struct r600_context *rctx)
2807 {
2808 struct pipe_blend_state blend;
2809
2810 memset(&blend, 0, sizeof(blend));
2811 blend.independent_blend_enable = true;
2812 blend.rt[0].colormask = 0xf;
2813 return r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2814 }
2815
2816 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2817 {
2818 struct pipe_depth_stencil_alpha_state dsa;
2819 boolean quirk = false;
2820
2821 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2822 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2823 quirk = true;
2824
2825 memset(&dsa, 0, sizeof(dsa));
2826
2827 if (quirk) {
2828 dsa.depth.enabled = 1;
2829 dsa.depth.func = PIPE_FUNC_LEQUAL;
2830 dsa.stencil[0].enabled = 1;
2831 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2832 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2833 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2834 dsa.stencil[0].writemask = 0xff;
2835 }
2836
2837 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2838 }
2839
2840 void r600_update_db_shader_control(struct r600_context * rctx)
2841 {
2842 bool dual_export = rctx->framebuffer.export_16bpc &&
2843 !rctx->ps_shader->current->ps_depth_export;
2844
2845 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2846 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2847
2848 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
2849 rctx->db_misc_state.db_shader_control = db_shader_control;
2850 rctx->db_misc_state.atom.dirty = true;
2851 }
2852 }