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r600g: don't flush the gfx IB explicitly before doing DMA
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
145 {
146 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
147 }
148
149 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
150 {
151 return r600_translate_colorformat(chip, format) != ~0U &&
152 r600_translate_colorswap(format) != ~0U;
153 }
154
155 static bool r600_is_zs_format_supported(enum pipe_format format)
156 {
157 return r600_translate_dbformat(format) != ~0U;
158 }
159
160 boolean r600_is_format_supported(struct pipe_screen *screen,
161 enum pipe_format format,
162 enum pipe_texture_target target,
163 unsigned sample_count,
164 unsigned usage)
165 {
166 struct r600_screen *rscreen = (struct r600_screen*)screen;
167 unsigned retval = 0;
168
169 if (target >= PIPE_MAX_TEXTURE_TYPES) {
170 R600_ERR("r600: unsupported texture type %d\n", target);
171 return FALSE;
172 }
173
174 if (!util_format_is_supported(format, usage))
175 return FALSE;
176
177 if (sample_count > 1) {
178 if (!rscreen->has_msaa)
179 return FALSE;
180
181 /* R11G11B10 is broken on R6xx. */
182 if (rscreen->b.chip_class == R600 &&
183 format == PIPE_FORMAT_R11G11B10_FLOAT)
184 return FALSE;
185
186 /* MSAA integer colorbuffers hang. */
187 if (util_format_is_pure_integer(format) &&
188 !util_format_is_depth_or_stencil(format))
189 return FALSE;
190
191 switch (sample_count) {
192 case 2:
193 case 4:
194 case 8:
195 break;
196 default:
197 return FALSE;
198 }
199 }
200
201 if (usage & PIPE_BIND_SAMPLER_VIEW) {
202 if (target == PIPE_BUFFER) {
203 if (r600_is_vertex_format_supported(format))
204 retval |= PIPE_BIND_SAMPLER_VIEW;
205 } else {
206 if (r600_is_sampler_format_supported(screen, format))
207 retval |= PIPE_BIND_SAMPLER_VIEW;
208 }
209 }
210
211 if ((usage & (PIPE_BIND_RENDER_TARGET |
212 PIPE_BIND_DISPLAY_TARGET |
213 PIPE_BIND_SCANOUT |
214 PIPE_BIND_SHARED)) &&
215 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
216 retval |= usage &
217 (PIPE_BIND_RENDER_TARGET |
218 PIPE_BIND_DISPLAY_TARGET |
219 PIPE_BIND_SCANOUT |
220 PIPE_BIND_SHARED);
221 }
222
223 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
224 r600_is_zs_format_supported(format)) {
225 retval |= PIPE_BIND_DEPTH_STENCIL;
226 }
227
228 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
229 r600_is_vertex_format_supported(format)) {
230 retval |= PIPE_BIND_VERTEX_BUFFER;
231 }
232
233 if (usage & PIPE_BIND_TRANSFER_READ)
234 retval |= PIPE_BIND_TRANSFER_READ;
235 if (usage & PIPE_BIND_TRANSFER_WRITE)
236 retval |= PIPE_BIND_TRANSFER_WRITE;
237
238 return retval == usage;
239 }
240
241 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
242 {
243 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
244 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
245 float offset_units = state->offset_units;
246 float offset_scale = state->offset_scale;
247
248 switch (state->zs_format) {
249 case PIPE_FORMAT_Z24X8_UNORM:
250 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
251 offset_units *= 2.0f;
252 break;
253 case PIPE_FORMAT_Z16_UNORM:
254 offset_units *= 4.0f;
255 break;
256 default:;
257 }
258
259 r600_write_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
260 radeon_emit(cs, fui(offset_scale));
261 radeon_emit(cs, fui(offset_units));
262 radeon_emit(cs, fui(offset_scale));
263 radeon_emit(cs, fui(offset_units));
264 }
265
266 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
267 {
268 int j = state->independent_blend_enable ? i : 0;
269
270 unsigned eqRGB = state->rt[j].rgb_func;
271 unsigned srcRGB = state->rt[j].rgb_src_factor;
272 unsigned dstRGB = state->rt[j].rgb_dst_factor;
273
274 unsigned eqA = state->rt[j].alpha_func;
275 unsigned srcA = state->rt[j].alpha_src_factor;
276 unsigned dstA = state->rt[j].alpha_dst_factor;
277 uint32_t bc = 0;
278
279 if (!state->rt[j].blend_enable)
280 return 0;
281
282 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
283 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
284 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
285
286 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
287 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
288 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
289 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
290 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
291 }
292 return bc;
293 }
294
295 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
296 const struct pipe_blend_state *state,
297 int mode)
298 {
299 struct r600_context *rctx = (struct r600_context *)ctx;
300 uint32_t color_control = 0, target_mask = 0;
301 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
302
303 if (!blend) {
304 return NULL;
305 }
306
307 r600_init_command_buffer(&blend->buffer, 20);
308 r600_init_command_buffer(&blend->buffer_no_blend, 20);
309
310 /* R600 does not support per-MRT blends */
311 if (rctx->b.family > CHIP_R600)
312 color_control |= S_028808_PER_MRT_BLEND(1);
313
314 if (state->logicop_enable) {
315 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
316 } else {
317 color_control |= (0xcc << 16);
318 }
319 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
320 if (state->independent_blend_enable) {
321 for (int i = 0; i < 8; i++) {
322 if (state->rt[i].blend_enable) {
323 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
324 }
325 target_mask |= (state->rt[i].colormask << (4 * i));
326 }
327 } else {
328 for (int i = 0; i < 8; i++) {
329 if (state->rt[0].blend_enable) {
330 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
331 }
332 target_mask |= (state->rt[0].colormask << (4 * i));
333 }
334 }
335
336 if (target_mask)
337 color_control |= S_028808_SPECIAL_OP(mode);
338 else
339 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
340
341 /* only MRT0 has dual src blend */
342 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
343 blend->cb_target_mask = target_mask;
344 blend->cb_color_control = color_control;
345 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
346 blend->alpha_to_one = state->alpha_to_one;
347
348 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
349 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
350 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
351 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
352 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
353 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
354
355 /* Copy over the registers set so far into buffer_no_blend. */
356 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
357 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
358
359 /* Only add blend registers if blending is enabled. */
360 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
361 return blend;
362 }
363
364 /* The first R600 does not support per-MRT blends */
365 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
366 r600_get_blend_control(state, 0));
367
368 if (rctx->b.family > CHIP_R600) {
369 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
370 for (int i = 0; i < 8; i++) {
371 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
372 }
373 }
374 return blend;
375 }
376
377 static void *r600_create_blend_state(struct pipe_context *ctx,
378 const struct pipe_blend_state *state)
379 {
380 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
381 }
382
383 static void *r600_create_dsa_state(struct pipe_context *ctx,
384 const struct pipe_depth_stencil_alpha_state *state)
385 {
386 unsigned db_depth_control, alpha_test_control, alpha_ref;
387 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
388
389 if (dsa == NULL) {
390 return NULL;
391 }
392
393 r600_init_command_buffer(&dsa->buffer, 3);
394
395 dsa->valuemask[0] = state->stencil[0].valuemask;
396 dsa->valuemask[1] = state->stencil[1].valuemask;
397 dsa->writemask[0] = state->stencil[0].writemask;
398 dsa->writemask[1] = state->stencil[1].writemask;
399 dsa->zwritemask = state->depth.writemask;
400
401 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
402 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
403 S_028800_ZFUNC(state->depth.func);
404
405 /* stencil */
406 if (state->stencil[0].enabled) {
407 db_depth_control |= S_028800_STENCIL_ENABLE(1);
408 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
409 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
410 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
411 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
412
413 if (state->stencil[1].enabled) {
414 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
415 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
416 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
417 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
418 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
419 }
420 }
421
422 /* alpha */
423 alpha_test_control = 0;
424 alpha_ref = 0;
425 if (state->alpha.enabled) {
426 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
427 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
428 alpha_ref = fui(state->alpha.ref_value);
429 }
430 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
431 dsa->alpha_ref = alpha_ref;
432
433 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
434 return dsa;
435 }
436
437 static void *r600_create_rs_state(struct pipe_context *ctx,
438 const struct pipe_rasterizer_state *state)
439 {
440 struct r600_context *rctx = (struct r600_context *)ctx;
441 unsigned tmp, sc_mode_cntl, spi_interp;
442 float psize_min, psize_max;
443 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
444
445 if (rs == NULL) {
446 return NULL;
447 }
448
449 r600_init_command_buffer(&rs->buffer, 30);
450
451 rs->flatshade = state->flatshade;
452 rs->sprite_coord_enable = state->sprite_coord_enable;
453 rs->two_side = state->light_twoside;
454 rs->clip_plane_enable = state->clip_plane_enable;
455 rs->pa_sc_line_stipple = state->line_stipple_enable ?
456 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
457 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
458 rs->pa_cl_clip_cntl =
459 S_028810_PS_UCP_MODE(3) |
460 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
461 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
462 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
463 rs->multisample_enable = state->multisample;
464
465 /* offset */
466 rs->offset_units = state->offset_units;
467 rs->offset_scale = state->offset_scale * 12.0f;
468 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
469
470 if (state->point_size_per_vertex) {
471 psize_min = util_get_min_point_size(state);
472 psize_max = 8192;
473 } else {
474 /* Force the point size to be as if the vertex output was disabled. */
475 psize_min = state->point_size;
476 psize_max = state->point_size;
477 }
478
479 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
480 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
481 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
482 if (rctx->b.chip_class >= R700) {
483 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
484 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
485 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
486 } else {
487 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
488 rs->scissor_enable = state->scissor;
489 }
490
491 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
492 if (state->sprite_coord_enable) {
493 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
494 S_0286D4_PNT_SPRITE_OVRD_X(2) |
495 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
496 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
497 S_0286D4_PNT_SPRITE_OVRD_W(1);
498 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
499 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
500 }
501 }
502
503 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
504 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
505 tmp = r600_pack_float_12p4(state->point_size/2);
506 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
507 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
508 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
509 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
510 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
511 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
512 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
513
514 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
515 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
516 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
517 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
518 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
519 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
520 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
521 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
522 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
523 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
524 S_028814_FACE(!state->front_ccw) |
525 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
526 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
527 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
528 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
529 state->fill_back != PIPE_POLYGON_MODE_FILL) |
530 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
531 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
532 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
533 return rs;
534 }
535
536 static void *r600_create_sampler_state(struct pipe_context *ctx,
537 const struct pipe_sampler_state *state)
538 {
539 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
540 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
541
542 if (ss == NULL) {
543 return NULL;
544 }
545
546 ss->seamless_cube_map = state->seamless_cube_map;
547 ss->border_color_use = sampler_state_needs_border_color(state);
548
549 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
550 ss->tex_sampler_words[0] =
551 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
552 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
553 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
554 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
555 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
556 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
557 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
558 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
559 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
560 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
561 ss->tex_sampler_words[1] =
562 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
563 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
564 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
565 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
566 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
567
568 if (ss->border_color_use) {
569 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
570 }
571 return ss;
572 }
573
574 static struct pipe_sampler_view *
575 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
576 unsigned width0, unsigned height0)
577
578 {
579 struct pipe_context *ctx = view->base.context;
580 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
581 uint64_t va;
582 int stride = util_format_get_blocksize(view->base.format);
583 unsigned format, num_format, format_comp, endian;
584 unsigned offset = view->base.u.buf.first_element * stride;
585 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
586
587 r600_vertex_data_type(view->base.format,
588 &format, &num_format, &format_comp,
589 &endian);
590
591 va = r600_resource_va(ctx->screen, view->base.texture) + offset;
592 view->tex_resource = &tmp->resource;
593
594 view->skip_mip_address_reloc = true;
595 view->tex_resource_words[0] = va;
596 view->tex_resource_words[1] = size - 1;
597 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(va >> 32UL) |
598 S_038008_STRIDE(stride) |
599 S_038008_DATA_FORMAT(format) |
600 S_038008_NUM_FORMAT_ALL(num_format) |
601 S_038008_FORMAT_COMP_ALL(format_comp) |
602 S_038008_SRF_MODE_ALL(1) |
603 S_038008_ENDIAN_SWAP(endian);
604 view->tex_resource_words[3] = 0;
605 /*
606 * in theory dword 4 is for number of elements, for use with resinfo,
607 * but it seems to utterly fail to work, the amd gpu shader analyser
608 * uses a const buffer to store the element sizes for buffer txq
609 */
610 view->tex_resource_words[4] = 0;
611 view->tex_resource_words[5] = 0;
612 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
613 return &view->base;
614 }
615
616 struct pipe_sampler_view *
617 r600_create_sampler_view_custom(struct pipe_context *ctx,
618 struct pipe_resource *texture,
619 const struct pipe_sampler_view *state,
620 unsigned width_first_level, unsigned height_first_level)
621 {
622 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
623 struct r600_texture *tmp = (struct r600_texture*)texture;
624 unsigned format, endian;
625 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
626 unsigned char swizzle[4], array_mode = 0;
627 unsigned width, height, depth, offset_level, last_level;
628
629 if (view == NULL)
630 return NULL;
631
632 /* initialize base object */
633 view->base = *state;
634 view->base.texture = NULL;
635 pipe_reference(NULL, &texture->reference);
636 view->base.texture = texture;
637 view->base.reference.count = 1;
638 view->base.context = ctx;
639
640 if (texture->target == PIPE_BUFFER)
641 return texture_buffer_sampler_view(view, texture->width0, 1);
642
643 swizzle[0] = state->swizzle_r;
644 swizzle[1] = state->swizzle_g;
645 swizzle[2] = state->swizzle_b;
646 swizzle[3] = state->swizzle_a;
647
648 format = r600_translate_texformat(ctx->screen, state->format,
649 swizzle,
650 &word4, &yuv_format);
651 assert(format != ~0);
652 if (format == ~0) {
653 FREE(view);
654 return NULL;
655 }
656
657 if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) {
658 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
659 FREE(view);
660 return NULL;
661 }
662 tmp = tmp->flushed_depth_texture;
663 }
664
665 endian = r600_colorformat_endian_swap(format);
666
667 offset_level = state->u.tex.first_level;
668 last_level = state->u.tex.last_level - offset_level;
669 width = width_first_level;
670 height = height_first_level;
671 depth = u_minify(texture->depth0, offset_level);
672 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
673
674 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
675 height = 1;
676 depth = texture->array_size;
677 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
678 depth = texture->array_size;
679 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
680 depth = texture->array_size / 6;
681 switch (tmp->surface.level[offset_level].mode) {
682 case RADEON_SURF_MODE_LINEAR_ALIGNED:
683 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
684 break;
685 case RADEON_SURF_MODE_1D:
686 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
687 break;
688 case RADEON_SURF_MODE_2D:
689 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
690 break;
691 case RADEON_SURF_MODE_LINEAR:
692 default:
693 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
694 break;
695 }
696
697 view->tex_resource = &tmp->resource;
698 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
699 S_038000_TILE_MODE(array_mode) |
700 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
701 S_038000_PITCH((pitch / 8) - 1) |
702 S_038000_TEX_WIDTH(width - 1));
703 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
704 S_038004_TEX_DEPTH(depth - 1) |
705 S_038004_DATA_FORMAT(format));
706 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
707 if (offset_level >= tmp->surface.last_level) {
708 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
709 } else {
710 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
711 }
712 view->tex_resource_words[4] = (word4 |
713 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
714 S_038010_REQUEST_SIZE(1) |
715 S_038010_ENDIAN_SWAP(endian) |
716 S_038010_BASE_LEVEL(0));
717 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
718 S_038014_LAST_ARRAY(state->u.tex.last_layer));
719 if (texture->nr_samples > 1) {
720 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
721 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
722 } else {
723 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
724 }
725 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
726 S_038018_MAX_ANISO(4 /* max 16 samples */));
727 return &view->base;
728 }
729
730 static struct pipe_sampler_view *
731 r600_create_sampler_view(struct pipe_context *ctx,
732 struct pipe_resource *tex,
733 const struct pipe_sampler_view *state)
734 {
735 return r600_create_sampler_view_custom(ctx, tex, state,
736 u_minify(tex->width0, state->u.tex.first_level),
737 u_minify(tex->height0, state->u.tex.first_level));
738 }
739
740 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
741 {
742 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
743 struct pipe_clip_state *state = &rctx->clip_state.state;
744
745 r600_write_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
746 radeon_emit_array(cs, (unsigned*)state, 6*4);
747 }
748
749 static void r600_set_polygon_stipple(struct pipe_context *ctx,
750 const struct pipe_poly_stipple *state)
751 {
752 }
753
754 static void r600_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
755 {
756 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
757 struct r600_scissor_state *rstate = (struct r600_scissor_state *)atom;
758 struct pipe_scissor_state *state = &rstate->scissor;
759 unsigned offset = rstate->idx * 4 * 2;
760
761 if (rctx->b.chip_class != R600 || rctx->scissor[0].enable) {
762 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + offset, 2);
763 radeon_emit(cs, S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) |
764 S_028240_WINDOW_OFFSET_DISABLE(1));
765 radeon_emit(cs, S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy));
766 } else {
767 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
768 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
769 S_028240_WINDOW_OFFSET_DISABLE(1));
770 radeon_emit(cs, S_028244_BR_X(8192) | S_028244_BR_Y(8192));
771 }
772 }
773
774 static void r600_set_scissor_states(struct pipe_context *ctx,
775 unsigned start_slot,
776 unsigned num_scissors,
777 const struct pipe_scissor_state *state)
778 {
779 struct r600_context *rctx = (struct r600_context *)ctx;
780 int i;
781
782 for (i = start_slot ; i < start_slot + num_scissors; i++) {
783 rctx->scissor[i].scissor = state[i - start_slot];
784 }
785
786 if (rctx->b.chip_class == R600 && !rctx->scissor[0].enable)
787 return;
788
789 for (i = start_slot ; i < start_slot + num_scissors; i++) {
790 rctx->scissor[i].atom.dirty = true;
791 }
792 }
793
794 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
795 unsigned size, unsigned alignment)
796 {
797 struct pipe_resource buffer;
798
799 memset(&buffer, 0, sizeof buffer);
800 buffer.target = PIPE_BUFFER;
801 buffer.format = PIPE_FORMAT_R8_UNORM;
802 buffer.bind = PIPE_BIND_CUSTOM;
803 buffer.usage = PIPE_USAGE_DEFAULT;
804 buffer.flags = 0;
805 buffer.width0 = size;
806 buffer.height0 = 1;
807 buffer.depth0 = 1;
808 buffer.array_size = 1;
809
810 return (struct r600_resource*)
811 r600_buffer_create(&rscreen->b.b, &buffer, alignment);
812 }
813
814 static void r600_init_color_surface(struct r600_context *rctx,
815 struct r600_surface *surf,
816 bool force_cmask_fmask)
817 {
818 struct r600_screen *rscreen = rctx->screen;
819 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
820 unsigned level = surf->base.u.tex.level;
821 unsigned pitch, slice;
822 unsigned color_info;
823 unsigned color_view;
824 unsigned format, swap, ntype, endian;
825 unsigned offset;
826 const struct util_format_description *desc;
827 int i;
828 bool blend_bypass = 0, blend_clamp = 1;
829
830 if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
831 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
832 rtex = rtex->flushed_depth_texture;
833 assert(rtex);
834 }
835
836 offset = rtex->surface.level[level].offset;
837 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
838 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
839 offset += rtex->surface.level[level].slice_size *
840 surf->base.u.tex.first_layer;
841 color_view = 0;
842 } else
843 color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
844 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
845
846 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
847 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
848 if (slice) {
849 slice = slice - 1;
850 }
851 color_info = 0;
852 switch (rtex->surface.level[level].mode) {
853 case RADEON_SURF_MODE_LINEAR_ALIGNED:
854 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
855 break;
856 case RADEON_SURF_MODE_1D:
857 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
858 break;
859 case RADEON_SURF_MODE_2D:
860 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
861 break;
862 case RADEON_SURF_MODE_LINEAR:
863 default:
864 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
865 break;
866 }
867
868 desc = util_format_description(surf->base.format);
869
870 for (i = 0; i < 4; i++) {
871 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
872 break;
873 }
874 }
875
876 ntype = V_0280A0_NUMBER_UNORM;
877 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
878 ntype = V_0280A0_NUMBER_SRGB;
879 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
880 if (desc->channel[i].normalized)
881 ntype = V_0280A0_NUMBER_SNORM;
882 else if (desc->channel[i].pure_integer)
883 ntype = V_0280A0_NUMBER_SINT;
884 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
885 if (desc->channel[i].normalized)
886 ntype = V_0280A0_NUMBER_UNORM;
887 else if (desc->channel[i].pure_integer)
888 ntype = V_0280A0_NUMBER_UINT;
889 }
890
891 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
892 assert(format != ~0);
893
894 swap = r600_translate_colorswap(surf->base.format);
895 assert(swap != ~0);
896
897 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
898 endian = ENDIAN_NONE;
899 } else {
900 endian = r600_colorformat_endian_swap(format);
901 }
902
903 /* set blend bypass according to docs if SINT/UINT or
904 8/24 COLOR variants */
905 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
906 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
907 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
908 blend_clamp = 0;
909 blend_bypass = 1;
910 }
911
912 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
913
914 color_info |= S_0280A0_FORMAT(format) |
915 S_0280A0_COMP_SWAP(swap) |
916 S_0280A0_BLEND_BYPASS(blend_bypass) |
917 S_0280A0_BLEND_CLAMP(blend_clamp) |
918 S_0280A0_NUMBER_TYPE(ntype) |
919 S_0280A0_ENDIAN(endian);
920
921 /* EXPORT_NORM is an optimzation that can be enabled for better
922 * performance in certain cases
923 */
924 if (rctx->b.chip_class == R600) {
925 /* EXPORT_NORM can be enabled if:
926 * - 11-bit or smaller UNORM/SNORM/SRGB
927 * - BLEND_CLAMP is enabled
928 * - BLEND_FLOAT32 is disabled
929 */
930 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
931 (desc->channel[i].size < 12 &&
932 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
933 ntype != V_0280A0_NUMBER_UINT &&
934 ntype != V_0280A0_NUMBER_SINT) &&
935 G_0280A0_BLEND_CLAMP(color_info) &&
936 !G_0280A0_BLEND_FLOAT32(color_info)) {
937 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
938 surf->export_16bpc = true;
939 }
940 } else {
941 /* EXPORT_NORM can be enabled if:
942 * - 11-bit or smaller UNORM/SNORM/SRGB
943 * - 16-bit or smaller FLOAT
944 */
945 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
946 ((desc->channel[i].size < 12 &&
947 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
948 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
949 (desc->channel[i].size < 17 &&
950 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
951 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
952 surf->export_16bpc = true;
953 }
954 }
955
956 /* These might not always be initialized to zero. */
957 surf->cb_color_base = offset >> 8;
958 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
959 S_028060_SLICE_TILE_MAX(slice);
960 surf->cb_color_fmask = surf->cb_color_base;
961 surf->cb_color_cmask = surf->cb_color_base;
962 surf->cb_color_mask = 0;
963
964 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
965 &rtex->resource.b.b);
966 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
967 &rtex->resource.b.b);
968
969 if (rtex->cmask.size) {
970 surf->cb_color_cmask = rtex->cmask.offset >> 8;
971 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
972
973 if (rtex->fmask.size) {
974 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
975 surf->cb_color_fmask = rtex->fmask.offset >> 8;
976 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
977 } else { /* cmask only */
978 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
979 }
980 } else if (force_cmask_fmask) {
981 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
982 *
983 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
984 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
985 * because it's not an MSAA buffer.
986 */
987 struct r600_cmask_info cmask;
988 struct r600_fmask_info fmask;
989
990 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
991 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
992
993 /* CMASK. */
994 if (!rctx->dummy_cmask ||
995 rctx->dummy_cmask->buf->size < cmask.size ||
996 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
997 struct pipe_transfer *transfer;
998 void *ptr;
999
1000 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1001 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1002
1003 /* Set the contents to 0xCC. */
1004 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1005 memset(ptr, 0xCC, cmask.size);
1006 pipe_buffer_unmap(&rctx->b.b, transfer);
1007 }
1008 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1009 &rctx->dummy_cmask->b.b);
1010
1011 /* FMASK. */
1012 if (!rctx->dummy_fmask ||
1013 rctx->dummy_fmask->buf->size < fmask.size ||
1014 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1015 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1016 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1017
1018 }
1019 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1020 &rctx->dummy_fmask->b.b);
1021
1022 /* Init the registers. */
1023 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1024 surf->cb_color_cmask = 0;
1025 surf->cb_color_fmask = 0;
1026 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1027 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1028 }
1029
1030 surf->cb_color_info = color_info;
1031 surf->cb_color_view = color_view;
1032 surf->color_initialized = true;
1033 }
1034
1035 static void r600_init_depth_surface(struct r600_context *rctx,
1036 struct r600_surface *surf)
1037 {
1038 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1039 unsigned level, pitch, slice, format, offset, array_mode;
1040
1041 level = surf->base.u.tex.level;
1042 offset = rtex->surface.level[level].offset;
1043 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1044 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1045 if (slice) {
1046 slice = slice - 1;
1047 }
1048 switch (rtex->surface.level[level].mode) {
1049 case RADEON_SURF_MODE_2D:
1050 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1051 break;
1052 case RADEON_SURF_MODE_1D:
1053 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1054 case RADEON_SURF_MODE_LINEAR:
1055 default:
1056 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1057 break;
1058 }
1059
1060 format = r600_translate_dbformat(surf->base.format);
1061 assert(format != ~0);
1062
1063 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1064 surf->db_depth_base = offset >> 8;
1065 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1066 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1067 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1068 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1069
1070 switch (surf->base.format) {
1071 case PIPE_FORMAT_Z24X8_UNORM:
1072 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1073 surf->pa_su_poly_offset_db_fmt_cntl =
1074 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1075 break;
1076 case PIPE_FORMAT_Z32_FLOAT:
1077 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1078 surf->pa_su_poly_offset_db_fmt_cntl =
1079 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1080 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1081 break;
1082 case PIPE_FORMAT_Z16_UNORM:
1083 surf->pa_su_poly_offset_db_fmt_cntl =
1084 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1085 break;
1086 default:;
1087 }
1088
1089 /* use htile only for first level */
1090 if (rtex->htile_buffer && !level) {
1091 uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile_buffer->b.b);
1092 surf->db_htile_data_base = va >> 8;
1093 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1094 S_028D24_HTILE_HEIGHT(1) |
1095 S_028D24_FULL_CACHE(1) |
1096 S_028D24_LINEAR(1);
1097 /* preload is not working properly on r6xx/r7xx */
1098 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1099 }
1100
1101 surf->depth_initialized = true;
1102 }
1103
1104 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1105 const struct pipe_framebuffer_state *state)
1106 {
1107 struct r600_context *rctx = (struct r600_context *)ctx;
1108 struct r600_surface *surf;
1109 struct r600_texture *rtex;
1110 unsigned i;
1111
1112 if (rctx->framebuffer.state.nr_cbufs) {
1113 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1114 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1115 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1116 }
1117 if (rctx->framebuffer.state.zsbuf) {
1118 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1119 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1120
1121 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1122 if (rctx->b.chip_class >= R700 && rtex->htile_buffer) {
1123 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1124 }
1125 }
1126
1127 /* Set the new state. */
1128 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1129
1130 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1131 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1132 util_format_is_pure_integer(state->cbufs[0]->format);
1133 rctx->framebuffer.compressed_cb_mask = 0;
1134 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1135 state->cbufs[0] && state->cbufs[1] &&
1136 state->cbufs[0]->texture->nr_samples > 1 &&
1137 state->cbufs[1]->texture->nr_samples <= 1;
1138 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1139
1140 /* Colorbuffers. */
1141 for (i = 0; i < state->nr_cbufs; i++) {
1142 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1143 bool force_cmask_fmask = rctx->b.chip_class == R600 &&
1144 rctx->framebuffer.is_msaa_resolve &&
1145 i == 1;
1146
1147 surf = (struct r600_surface*)state->cbufs[i];
1148 if (!surf)
1149 continue;
1150
1151 rtex = (struct r600_texture*)surf->base.texture;
1152 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1153
1154 if (!surf->color_initialized || force_cmask_fmask) {
1155 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1156 if (force_cmask_fmask) {
1157 /* re-initialize later without compression */
1158 surf->color_initialized = false;
1159 }
1160 }
1161
1162 if (!surf->export_16bpc) {
1163 rctx->framebuffer.export_16bpc = false;
1164 }
1165
1166 if (rtex->fmask.size && rtex->cmask.size) {
1167 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1168 }
1169 }
1170
1171 /* Update alpha-test state dependencies.
1172 * Alpha-test is done on the first colorbuffer only. */
1173 if (state->nr_cbufs) {
1174 bool alphatest_bypass = false;
1175
1176 surf = (struct r600_surface*)state->cbufs[0];
1177 if (surf) {
1178 alphatest_bypass = surf->alphatest_bypass;
1179 }
1180
1181 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1182 rctx->alphatest_state.bypass = alphatest_bypass;
1183 rctx->alphatest_state.atom.dirty = true;
1184 }
1185 }
1186
1187 /* ZS buffer. */
1188 if (state->zsbuf) {
1189 surf = (struct r600_surface*)state->zsbuf;
1190
1191 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1192
1193 if (!surf->depth_initialized) {
1194 r600_init_depth_surface(rctx, surf);
1195 }
1196
1197 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1198 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1199 rctx->poly_offset_state.atom.dirty = true;
1200 }
1201
1202 if (rctx->db_state.rsurf != surf) {
1203 rctx->db_state.rsurf = surf;
1204 rctx->db_state.atom.dirty = true;
1205 rctx->db_misc_state.atom.dirty = true;
1206 }
1207 } else if (rctx->db_state.rsurf) {
1208 rctx->db_state.rsurf = NULL;
1209 rctx->db_state.atom.dirty = true;
1210 rctx->db_misc_state.atom.dirty = true;
1211 }
1212
1213 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1214 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1215 rctx->cb_misc_state.atom.dirty = true;
1216 }
1217
1218 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1219 rctx->alphatest_state.bypass = false;
1220 rctx->alphatest_state.atom.dirty = true;
1221 }
1222
1223 /* Calculate the CS size. */
1224 rctx->framebuffer.atom.num_dw =
1225 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1226
1227 if (rctx->framebuffer.state.nr_cbufs) {
1228 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
1229 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
1230 }
1231 if (rctx->framebuffer.state.zsbuf) {
1232 rctx->framebuffer.atom.num_dw += 16;
1233 } else if (rctx->screen->b.info.drm_minor >= 18) {
1234 rctx->framebuffer.atom.num_dw += 3;
1235 }
1236 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1237 rctx->framebuffer.atom.num_dw += 2;
1238 }
1239
1240 rctx->framebuffer.atom.dirty = true;
1241 }
1242
1243 static uint32_t sample_locs_2x[] = {
1244 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1245 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1246 };
1247 static unsigned max_dist_2x = 4;
1248
1249 static uint32_t sample_locs_4x[] = {
1250 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1251 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1252 };
1253 static unsigned max_dist_4x = 6;
1254 static uint32_t sample_locs_8x[] = {
1255 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1256 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1257 };
1258 static unsigned max_dist_8x = 7;
1259
1260 static void r600_get_sample_position(struct pipe_context *ctx,
1261 unsigned sample_count,
1262 unsigned sample_index,
1263 float *out_value)
1264 {
1265 int offset, index;
1266 struct {
1267 int idx:4;
1268 } val;
1269 switch (sample_count) {
1270 case 1:
1271 default:
1272 out_value[0] = out_value[1] = 0.5;
1273 break;
1274 case 2:
1275 offset = 4 * (sample_index * 2);
1276 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1277 out_value[0] = (float)(val.idx + 8) / 16.0f;
1278 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1279 out_value[1] = (float)(val.idx + 8) / 16.0f;
1280 break;
1281 case 4:
1282 offset = 4 * (sample_index * 2);
1283 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1284 out_value[0] = (float)(val.idx + 8) / 16.0f;
1285 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1286 out_value[1] = (float)(val.idx + 8) / 16.0f;
1287 break;
1288 case 8:
1289 offset = 4 * (sample_index % 4 * 2);
1290 index = (sample_index / 4);
1291 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1292 out_value[0] = (float)(val.idx + 8) / 16.0f;
1293 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1294 out_value[1] = (float)(val.idx + 8) / 16.0f;
1295 break;
1296 }
1297 }
1298
1299 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1300 {
1301 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1302 unsigned max_dist = 0;
1303
1304 if (rctx->b.family == CHIP_R600) {
1305 switch (nr_samples) {
1306 default:
1307 nr_samples = 0;
1308 break;
1309 case 2:
1310 r600_write_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1311 max_dist = max_dist_2x;
1312 break;
1313 case 4:
1314 r600_write_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1315 max_dist = max_dist_4x;
1316 break;
1317 case 8:
1318 r600_write_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1319 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1320 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1321 max_dist = max_dist_8x;
1322 break;
1323 }
1324 } else {
1325 switch (nr_samples) {
1326 default:
1327 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1328 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1329 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1330 nr_samples = 0;
1331 break;
1332 case 2:
1333 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1334 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1335 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1336 max_dist = max_dist_2x;
1337 break;
1338 case 4:
1339 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1340 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1341 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1342 max_dist = max_dist_4x;
1343 break;
1344 case 8:
1345 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1346 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1347 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1348 max_dist = max_dist_8x;
1349 break;
1350 }
1351 }
1352
1353 if (nr_samples > 1) {
1354 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1355 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1356 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1357 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1358 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1359 } else {
1360 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1361 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1362 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1363 }
1364 }
1365
1366 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1367 {
1368 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1369 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1370 unsigned nr_cbufs = state->nr_cbufs;
1371 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1372 unsigned i, sbu = 0;
1373
1374 /* Colorbuffers. */
1375 r600_write_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1376 for (i = 0; i < nr_cbufs; i++) {
1377 radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0);
1378 }
1379 /* set CB_COLOR1_INFO for possible dual-src blending */
1380 if (i == 1 && cb[0]) {
1381 radeon_emit(cs, cb[0]->cb_color_info);
1382 i++;
1383 }
1384 for (; i < 8; i++) {
1385 radeon_emit(cs, 0);
1386 }
1387
1388 if (nr_cbufs) {
1389 for (i = 0; i < nr_cbufs; i++) {
1390 unsigned reloc;
1391
1392 if (!cb[i])
1393 continue;
1394
1395 /* COLOR_BASE */
1396 r600_write_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1397
1398 reloc = r600_context_bo_reloc(&rctx->b,
1399 &rctx->b.rings.gfx,
1400 (struct r600_resource*)cb[i]->base.texture,
1401 RADEON_USAGE_READWRITE,
1402 cb[i]->base.texture->nr_samples > 1 ?
1403 RADEON_PRIO_COLOR_BUFFER_MSAA :
1404 RADEON_PRIO_COLOR_BUFFER);
1405 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1406 radeon_emit(cs, reloc);
1407
1408 /* FMASK */
1409 r600_write_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1410
1411 reloc = r600_context_bo_reloc(&rctx->b,
1412 &rctx->b.rings.gfx,
1413 cb[i]->cb_buffer_fmask,
1414 RADEON_USAGE_READWRITE,
1415 cb[i]->base.texture->nr_samples > 1 ?
1416 RADEON_PRIO_COLOR_BUFFER_MSAA :
1417 RADEON_PRIO_COLOR_BUFFER);
1418 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1419 radeon_emit(cs, reloc);
1420
1421 /* CMASK */
1422 r600_write_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1423
1424 reloc = r600_context_bo_reloc(&rctx->b,
1425 &rctx->b.rings.gfx,
1426 cb[i]->cb_buffer_cmask,
1427 RADEON_USAGE_READWRITE,
1428 cb[i]->base.texture->nr_samples > 1 ?
1429 RADEON_PRIO_COLOR_BUFFER_MSAA :
1430 RADEON_PRIO_COLOR_BUFFER);
1431 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1432 radeon_emit(cs, reloc);
1433 }
1434
1435 r600_write_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1436 for (i = 0; i < nr_cbufs; i++) {
1437 radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0);
1438 }
1439
1440 r600_write_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1441 for (i = 0; i < nr_cbufs; i++) {
1442 radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0);
1443 }
1444
1445 r600_write_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1446 for (i = 0; i < nr_cbufs; i++) {
1447 radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0);
1448 }
1449
1450 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1451 }
1452
1453 /* SURFACE_BASE_UPDATE */
1454 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1455 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1456 radeon_emit(cs, sbu);
1457 sbu = 0;
1458 }
1459
1460 /* Zbuffer. */
1461 if (state->zsbuf) {
1462 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1463 unsigned reloc = r600_context_bo_reloc(&rctx->b,
1464 &rctx->b.rings.gfx,
1465 (struct r600_resource*)state->zsbuf->texture,
1466 RADEON_USAGE_READWRITE,
1467 surf->base.texture->nr_samples > 1 ?
1468 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1469 RADEON_PRIO_DEPTH_BUFFER);
1470
1471 r600_write_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1472 surf->pa_su_poly_offset_db_fmt_cntl);
1473
1474 r600_write_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1475 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1476 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1477 r600_write_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1478 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1479 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1480
1481 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1482 radeon_emit(cs, reloc);
1483
1484 r600_write_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1485
1486 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1487 } else if (rctx->screen->b.info.drm_minor >= 18) {
1488 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1489 * Older kernels are out of luck. */
1490 r600_write_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1491 }
1492
1493 /* SURFACE_BASE_UPDATE */
1494 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1495 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1496 radeon_emit(cs, sbu);
1497 sbu = 0;
1498 }
1499
1500 /* Framebuffer dimensions. */
1501 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1502 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1503 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1504 radeon_emit(cs, S_028244_BR_X(state->width) |
1505 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1506
1507 if (rctx->framebuffer.is_msaa_resolve) {
1508 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1509 } else {
1510 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1511 * will assure that the alpha-test will work even if there is
1512 * no colorbuffer bound. */
1513 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1514 (1ull << MAX2(nr_cbufs, 1)) - 1);
1515 }
1516
1517 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1518 }
1519
1520 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1521 {
1522 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1523 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1524
1525 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1526 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1527 if (rctx->b.chip_class == R600) {
1528 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1529 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1530 } else {
1531 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1532 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1533 }
1534 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1535 } else {
1536 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1537 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1538 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1539
1540 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1541 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1542 /* Always enable the first color output to make sure alpha-test works even without one. */
1543 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1544 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1545 a->cb_color_control |
1546 S_028808_MULTIWRITE_ENABLE(multiwrite));
1547 }
1548 }
1549
1550 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1551 {
1552 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1553 struct r600_db_state *a = (struct r600_db_state*)atom;
1554
1555 if (a->rsurf && a->rsurf->db_htile_surface) {
1556 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1557 unsigned reloc_idx;
1558
1559 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1560 r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1561 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1562 reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer,
1563 RADEON_USAGE_READWRITE, RADEON_PRIO_DEPTH_META);
1564 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1565 cs->buf[cs->cdw++] = reloc_idx;
1566 } else {
1567 r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1568 }
1569 }
1570
1571 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1572 {
1573 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1574 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1575 unsigned db_render_control = 0;
1576 unsigned db_render_override =
1577 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1578 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1579
1580 if (a->occlusion_query_enabled) {
1581 if (rctx->b.chip_class >= R700) {
1582 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1583 }
1584 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1585 }
1586 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
1587 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1588 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1589 /* This is to fix a lockup when hyperz and alpha test are enabled at
1590 * the same time somehow GPU get confuse on which order to pick for
1591 * z test
1592 */
1593 if (rctx->alphatest_state.sx_alpha_test_control) {
1594 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
1595 }
1596 } else {
1597 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1598 }
1599 if (a->flush_depthstencil_through_cb) {
1600 assert(a->copy_depth || a->copy_stencil);
1601
1602 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1603 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1604 S_028D0C_COPY_CENTROID(1) |
1605 S_028D0C_COPY_SAMPLE(a->copy_sample);
1606 } else if (a->flush_depthstencil_in_place) {
1607 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(1) |
1608 S_028D0C_STENCIL_COMPRESS_DISABLE(1);
1609 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1610 }
1611 if (a->htile_clear) {
1612 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1613 }
1614
1615 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1616 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1617 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1618 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1619 }
1620
1621 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1622 {
1623 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1624 struct r600_config_state *a = (struct r600_config_state*)atom;
1625
1626 r600_write_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1627 r600_write_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
1628 }
1629
1630 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1631 {
1632 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1633 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1634
1635 while (dirty_mask) {
1636 struct pipe_vertex_buffer *vb;
1637 struct r600_resource *rbuffer;
1638 unsigned offset;
1639 unsigned buffer_index = u_bit_scan(&dirty_mask);
1640
1641 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1642 rbuffer = (struct r600_resource*)vb->buffer;
1643 assert(rbuffer);
1644
1645 offset = vb->buffer_offset;
1646
1647 /* fetch resources start at index 320 */
1648 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1649 radeon_emit(cs, (320 + buffer_index) * 7);
1650 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1651 radeon_emit(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1652 radeon_emit(cs, /* RESOURCEi_WORD2 */
1653 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1654 S_038008_STRIDE(vb->stride));
1655 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1656 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1657 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1658 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1659
1660 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1661 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1662 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1663 }
1664 }
1665
1666 static void r600_emit_constant_buffers(struct r600_context *rctx,
1667 struct r600_constbuf_state *state,
1668 unsigned buffer_id_base,
1669 unsigned reg_alu_constbuf_size,
1670 unsigned reg_alu_const_cache)
1671 {
1672 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1673 uint32_t dirty_mask = state->dirty_mask;
1674
1675 while (dirty_mask) {
1676 struct pipe_constant_buffer *cb;
1677 struct r600_resource *rbuffer;
1678 unsigned offset;
1679 unsigned buffer_index = ffs(dirty_mask) - 1;
1680 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1681 cb = &state->cb[buffer_index];
1682 rbuffer = (struct r600_resource*)cb->buffer;
1683 assert(rbuffer);
1684
1685 offset = cb->buffer_offset;
1686
1687 if (!gs_ring_buffer) {
1688 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1689 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1690 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1691 }
1692
1693 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1694 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1695 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1696
1697 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1698 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
1699 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1700 radeon_emit(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1701 radeon_emit(cs, /* RESOURCEi_WORD2 */
1702 S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1703 S_038008_STRIDE(gs_ring_buffer ? 4 : 16));
1704 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1705 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1706 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1707 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1708
1709 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1710 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1711 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1712
1713 dirty_mask &= ~(1 << buffer_index);
1714 }
1715 state->dirty_mask = 0;
1716 }
1717
1718 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1719 {
1720 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 160,
1721 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1722 R_028980_ALU_CONST_CACHE_VS_0);
1723 }
1724
1725 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1726 {
1727 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
1728 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1729 R_0289C0_ALU_CONST_CACHE_GS_0);
1730 }
1731
1732 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1733 {
1734 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
1735 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1736 R_028940_ALU_CONST_CACHE_PS_0);
1737 }
1738
1739 static void r600_emit_sampler_views(struct r600_context *rctx,
1740 struct r600_samplerview_state *state,
1741 unsigned resource_id_base)
1742 {
1743 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1744 uint32_t dirty_mask = state->dirty_mask;
1745
1746 while (dirty_mask) {
1747 struct r600_pipe_sampler_view *rview;
1748 unsigned resource_index = u_bit_scan(&dirty_mask);
1749 unsigned reloc;
1750
1751 rview = state->views[resource_index];
1752 assert(rview);
1753
1754 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1755 radeon_emit(cs, (resource_id_base + resource_index) * 7);
1756 radeon_emit_array(cs, rview->tex_resource_words, 7);
1757
1758 reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->tex_resource,
1759 RADEON_USAGE_READ,
1760 rview->tex_resource->b.b.nr_samples > 1 ?
1761 RADEON_PRIO_SHADER_TEXTURE_MSAA :
1762 RADEON_PRIO_SHADER_TEXTURE_RO);
1763 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1764 radeon_emit(cs, reloc);
1765 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1766 radeon_emit(cs, reloc);
1767 }
1768 state->dirty_mask = 0;
1769 }
1770
1771 /* Resource IDs:
1772 * PS: 0 .. +160
1773 * VS: 160 .. +160
1774 * FS: 320 .. +16
1775 * GS: 336 .. +160
1776 */
1777
1778 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1779 {
1780 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 160 + R600_MAX_CONST_BUFFERS);
1781 }
1782
1783 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1784 {
1785 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
1786 }
1787
1788 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1789 {
1790 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
1791 }
1792
1793 static void r600_emit_sampler_states(struct r600_context *rctx,
1794 struct r600_textures_info *texinfo,
1795 unsigned resource_id_base,
1796 unsigned border_color_reg)
1797 {
1798 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1799 uint32_t dirty_mask = texinfo->states.dirty_mask;
1800
1801 while (dirty_mask) {
1802 struct r600_pipe_sampler_state *rstate;
1803 struct r600_pipe_sampler_view *rview;
1804 unsigned i = u_bit_scan(&dirty_mask);
1805
1806 rstate = texinfo->states.states[i];
1807 assert(rstate);
1808 rview = texinfo->views.views[i];
1809
1810 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1811 * filtering between layers.
1812 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1813 */
1814 if (rview) {
1815 enum pipe_texture_target target = rview->base.texture->target;
1816 if (target == PIPE_TEXTURE_1D_ARRAY ||
1817 target == PIPE_TEXTURE_2D_ARRAY) {
1818 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1819 texinfo->is_array_sampler[i] = true;
1820 } else {
1821 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1822 texinfo->is_array_sampler[i] = false;
1823 }
1824 }
1825
1826 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1827 radeon_emit(cs, (resource_id_base + i) * 3);
1828 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
1829
1830 if (rstate->border_color_use) {
1831 unsigned offset;
1832
1833 offset = border_color_reg;
1834 offset += i * 16;
1835 r600_write_config_reg_seq(cs, offset, 4);
1836 radeon_emit_array(cs, rstate->border_color.ui, 4);
1837 }
1838 }
1839 texinfo->states.dirty_mask = 0;
1840 }
1841
1842 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1843 {
1844 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1845 }
1846
1847 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1848 {
1849 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1850 }
1851
1852 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1853 {
1854 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1855 }
1856
1857 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1858 {
1859 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1860 unsigned tmp;
1861
1862 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1863 S_009508_SYNC_GRADIENT(1) |
1864 S_009508_SYNC_WALKER(1) |
1865 S_009508_SYNC_ALIGNER(1);
1866 if (!rctx->seamless_cube_map.enabled) {
1867 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1868 }
1869 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1870 }
1871
1872 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1873 {
1874 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1875 uint8_t mask = s->sample_mask;
1876
1877 r600_write_context_reg(rctx->b.rings.gfx.cs, R_028C48_PA_SC_AA_MASK,
1878 mask | (mask << 8) | (mask << 16) | (mask << 24));
1879 }
1880
1881 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
1882 {
1883 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1884 struct r600_cso_state *state = (struct r600_cso_state*)a;
1885 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
1886
1887 r600_write_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
1888 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1889 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->buffer,
1890 RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA));
1891 }
1892
1893 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
1894 {
1895 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1896 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
1897
1898 uint32_t v2 = 0, primid = 0;
1899
1900 if (state->geom_enable) {
1901 uint32_t cut_val;
1902
1903 if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 128)
1904 cut_val = V_028A40_GS_CUT_128;
1905 else if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 256)
1906 cut_val = V_028A40_GS_CUT_256;
1907 else if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 512)
1908 cut_val = V_028A40_GS_CUT_512;
1909 else
1910 cut_val = V_028A40_GS_CUT_1024;
1911
1912 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1913 S_028A40_CUT_MODE(cut_val);
1914
1915 if (rctx->gs_shader->current->shader.gs_prim_id_input)
1916 primid = 1;
1917 }
1918
1919 r600_write_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
1920 r600_write_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
1921 }
1922
1923 static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
1924 {
1925 struct pipe_screen *screen = rctx->b.b.screen;
1926 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1927 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
1928 struct r600_resource *rbuffer;
1929
1930 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1931 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1932 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1933
1934 if (state->enable) {
1935 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
1936 r600_write_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
1937 (r600_resource_va(screen, &rbuffer->b.b)) >> 8);
1938 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1939 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1940 RADEON_USAGE_READWRITE,
1941 RADEON_PRIO_SHADER_RESOURCE_RW));
1942 r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
1943 state->esgs_ring.buffer_size >> 8);
1944
1945 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
1946 r600_write_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
1947 (r600_resource_va(screen, &rbuffer->b.b)) >> 8);
1948 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1949 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1950 RADEON_USAGE_READWRITE,
1951 RADEON_PRIO_SHADER_RESOURCE_RW));
1952 r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
1953 state->gsvs_ring.buffer_size >> 8);
1954 } else {
1955 r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
1956 r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
1957 }
1958
1959 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1960 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1961 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1962 }
1963
1964 /* Adjust GPR allocation on R6xx/R7xx */
1965 bool r600_adjust_gprs(struct r600_context *rctx)
1966 {
1967 unsigned num_ps_gprs = rctx->ps_shader->current->shader.bc.ngpr;
1968 unsigned num_vs_gprs, num_es_gprs, num_gs_gprs;
1969 unsigned new_num_ps_gprs = num_ps_gprs;
1970 unsigned new_num_vs_gprs, new_num_es_gprs, new_num_gs_gprs;
1971 unsigned cur_num_ps_gprs = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
1972 unsigned cur_num_vs_gprs = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
1973 unsigned cur_num_gs_gprs = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
1974 unsigned cur_num_es_gprs = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
1975 unsigned def_num_ps_gprs = rctx->default_ps_gprs;
1976 unsigned def_num_vs_gprs = rctx->default_vs_gprs;
1977 unsigned def_num_gs_gprs = 0;
1978 unsigned def_num_es_gprs = 0;
1979 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
1980 /* hardware will reserve twice num_clause_temp_gprs */
1981 unsigned max_gprs = def_num_gs_gprs + def_num_es_gprs + def_num_ps_gprs + def_num_vs_gprs + def_num_clause_temp_gprs * 2;
1982 unsigned tmp, tmp2;
1983
1984 if (rctx->gs_shader) {
1985 num_es_gprs = rctx->vs_shader->current->shader.bc.ngpr;
1986 num_gs_gprs = rctx->gs_shader->current->shader.bc.ngpr;
1987 num_vs_gprs = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
1988 } else {
1989 num_es_gprs = 0;
1990 num_gs_gprs = 0;
1991 num_vs_gprs = rctx->vs_shader->current->shader.bc.ngpr;
1992 }
1993 new_num_vs_gprs = num_vs_gprs;
1994 new_num_es_gprs = num_es_gprs;
1995 new_num_gs_gprs = num_gs_gprs;
1996
1997 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
1998 if (new_num_ps_gprs > cur_num_ps_gprs || new_num_vs_gprs > cur_num_vs_gprs ||
1999 new_num_es_gprs > cur_num_es_gprs || new_num_gs_gprs > cur_num_gs_gprs) {
2000 /* try to use switch back to default */
2001 if (new_num_ps_gprs > def_num_ps_gprs || new_num_vs_gprs > def_num_vs_gprs ||
2002 new_num_gs_gprs > def_num_gs_gprs || new_num_es_gprs > def_num_es_gprs) {
2003 /* always privilege vs stage so that at worst we have the
2004 * pixel stage producing wrong output (not the vertex
2005 * stage) */
2006 new_num_ps_gprs = max_gprs - ((new_num_vs_gprs - new_num_es_gprs - new_num_gs_gprs) + def_num_clause_temp_gprs * 2);
2007 new_num_vs_gprs = num_vs_gprs;
2008 new_num_gs_gprs = num_gs_gprs;
2009 new_num_es_gprs = num_es_gprs;
2010 } else {
2011 new_num_ps_gprs = def_num_ps_gprs;
2012 new_num_vs_gprs = def_num_vs_gprs;
2013 new_num_es_gprs = def_num_es_gprs;
2014 new_num_gs_gprs = def_num_gs_gprs;
2015 }
2016 } else {
2017 return true;
2018 }
2019
2020 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2021 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2022 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2023 * it will lockup. So in this case just discard the draw command
2024 * and don't change the current gprs repartitions.
2025 */
2026 if (num_ps_gprs > new_num_ps_gprs || num_vs_gprs > new_num_vs_gprs ||
2027 num_gs_gprs > new_num_gs_gprs || num_es_gprs > new_num_es_gprs) {
2028 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2029 "for a combined maximum of %d\n",
2030 num_ps_gprs, num_vs_gprs, num_es_gprs, num_gs_gprs, max_gprs);
2031 return false;
2032 }
2033
2034 /* in some case we endup recomputing the current value */
2035 tmp = S_008C04_NUM_PS_GPRS(new_num_ps_gprs) |
2036 S_008C04_NUM_VS_GPRS(new_num_vs_gprs) |
2037 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2038
2039 tmp2 = S_008C08_NUM_ES_GPRS(new_num_es_gprs) |
2040 S_008C08_NUM_GS_GPRS(new_num_gs_gprs);
2041 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2042 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2043 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2;
2044 rctx->config_state.atom.dirty = true;
2045 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2046 }
2047 return true;
2048 }
2049
2050 void r600_init_atom_start_cs(struct r600_context *rctx)
2051 {
2052 int ps_prio;
2053 int vs_prio;
2054 int gs_prio;
2055 int es_prio;
2056 int num_ps_gprs;
2057 int num_vs_gprs;
2058 int num_gs_gprs;
2059 int num_es_gprs;
2060 int num_temp_gprs;
2061 int num_ps_threads;
2062 int num_vs_threads;
2063 int num_gs_threads;
2064 int num_es_threads;
2065 int num_ps_stack_entries;
2066 int num_vs_stack_entries;
2067 int num_gs_stack_entries;
2068 int num_es_stack_entries;
2069 enum radeon_family family;
2070 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2071 uint32_t tmp;
2072
2073 r600_init_command_buffer(cb, 256);
2074
2075 /* R6xx requires this packet at the start of each command buffer */
2076 if (rctx->b.chip_class == R600) {
2077 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2078 r600_store_value(cb, 0);
2079 }
2080 /* All asics require this one */
2081 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2082 r600_store_value(cb, 0x80000000);
2083 r600_store_value(cb, 0x80000000);
2084
2085 /* We're setting config registers here. */
2086 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2087 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2088
2089 family = rctx->b.family;
2090 ps_prio = 0;
2091 vs_prio = 1;
2092 gs_prio = 2;
2093 es_prio = 3;
2094 switch (family) {
2095 case CHIP_R600:
2096 num_ps_gprs = 192;
2097 num_vs_gprs = 56;
2098 num_temp_gprs = 4;
2099 num_gs_gprs = 0;
2100 num_es_gprs = 0;
2101 num_ps_threads = 136;
2102 num_vs_threads = 48;
2103 num_gs_threads = 4;
2104 num_es_threads = 4;
2105 num_ps_stack_entries = 128;
2106 num_vs_stack_entries = 128;
2107 num_gs_stack_entries = 0;
2108 num_es_stack_entries = 0;
2109 break;
2110 case CHIP_RV630:
2111 case CHIP_RV635:
2112 num_ps_gprs = 84;
2113 num_vs_gprs = 36;
2114 num_temp_gprs = 4;
2115 num_gs_gprs = 0;
2116 num_es_gprs = 0;
2117 num_ps_threads = 144;
2118 num_vs_threads = 40;
2119 num_gs_threads = 4;
2120 num_es_threads = 4;
2121 num_ps_stack_entries = 40;
2122 num_vs_stack_entries = 40;
2123 num_gs_stack_entries = 32;
2124 num_es_stack_entries = 16;
2125 break;
2126 case CHIP_RV610:
2127 case CHIP_RV620:
2128 case CHIP_RS780:
2129 case CHIP_RS880:
2130 default:
2131 num_ps_gprs = 84;
2132 num_vs_gprs = 36;
2133 num_temp_gprs = 4;
2134 num_gs_gprs = 0;
2135 num_es_gprs = 0;
2136 num_ps_threads = 136;
2137 num_vs_threads = 48;
2138 num_gs_threads = 4;
2139 num_es_threads = 4;
2140 num_ps_stack_entries = 40;
2141 num_vs_stack_entries = 40;
2142 num_gs_stack_entries = 32;
2143 num_es_stack_entries = 16;
2144 break;
2145 case CHIP_RV670:
2146 num_ps_gprs = 144;
2147 num_vs_gprs = 40;
2148 num_temp_gprs = 4;
2149 num_gs_gprs = 0;
2150 num_es_gprs = 0;
2151 num_ps_threads = 136;
2152 num_vs_threads = 48;
2153 num_gs_threads = 4;
2154 num_es_threads = 4;
2155 num_ps_stack_entries = 40;
2156 num_vs_stack_entries = 40;
2157 num_gs_stack_entries = 32;
2158 num_es_stack_entries = 16;
2159 break;
2160 case CHIP_RV770:
2161 num_ps_gprs = 130;
2162 num_vs_gprs = 56;
2163 num_temp_gprs = 4;
2164 num_gs_gprs = 31;
2165 num_es_gprs = 31;
2166 num_ps_threads = 180;
2167 num_vs_threads = 60;
2168 num_gs_threads = 4;
2169 num_es_threads = 4;
2170 num_ps_stack_entries = 128;
2171 num_vs_stack_entries = 128;
2172 num_gs_stack_entries = 128;
2173 num_es_stack_entries = 128;
2174 break;
2175 case CHIP_RV730:
2176 case CHIP_RV740:
2177 num_ps_gprs = 84;
2178 num_vs_gprs = 36;
2179 num_temp_gprs = 4;
2180 num_gs_gprs = 0;
2181 num_es_gprs = 0;
2182 num_ps_threads = 180;
2183 num_vs_threads = 60;
2184 num_gs_threads = 4;
2185 num_es_threads = 4;
2186 num_ps_stack_entries = 128;
2187 num_vs_stack_entries = 128;
2188 num_gs_stack_entries = 0;
2189 num_es_stack_entries = 0;
2190 break;
2191 case CHIP_RV710:
2192 num_ps_gprs = 192;
2193 num_vs_gprs = 56;
2194 num_temp_gprs = 4;
2195 num_gs_gprs = 0;
2196 num_es_gprs = 0;
2197 num_ps_threads = 136;
2198 num_vs_threads = 48;
2199 num_gs_threads = 4;
2200 num_es_threads = 4;
2201 num_ps_stack_entries = 128;
2202 num_vs_stack_entries = 128;
2203 num_gs_stack_entries = 0;
2204 num_es_stack_entries = 0;
2205 break;
2206 }
2207
2208 rctx->default_ps_gprs = num_ps_gprs;
2209 rctx->default_vs_gprs = num_vs_gprs;
2210 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2211
2212 /* SQ_CONFIG */
2213 tmp = 0;
2214 switch (family) {
2215 case CHIP_RV610:
2216 case CHIP_RV620:
2217 case CHIP_RS780:
2218 case CHIP_RS880:
2219 case CHIP_RV710:
2220 break;
2221 default:
2222 tmp |= S_008C00_VC_ENABLE(1);
2223 break;
2224 }
2225 tmp |= S_008C00_DX9_CONSTS(0);
2226 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2227 tmp |= S_008C00_PS_PRIO(ps_prio);
2228 tmp |= S_008C00_VS_PRIO(vs_prio);
2229 tmp |= S_008C00_GS_PRIO(gs_prio);
2230 tmp |= S_008C00_ES_PRIO(es_prio);
2231 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2232
2233 /* SQ_GPR_RESOURCE_MGMT_2 */
2234 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2235 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2236 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2237 r600_store_value(cb, tmp);
2238
2239 /* SQ_THREAD_RESOURCE_MGMT */
2240 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2241 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2242 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2243 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2244 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2245
2246 /* SQ_STACK_RESOURCE_MGMT_1 */
2247 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2248 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2249 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2250
2251 /* SQ_STACK_RESOURCE_MGMT_2 */
2252 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2253 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2254 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2255
2256 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2257
2258 if (rctx->b.chip_class >= R700) {
2259 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2260 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2261 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2262 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2263 } else {
2264 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2265 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2266 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2267 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2268 }
2269 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2270 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2271 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2272 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2273 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2274 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2275 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2276 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2277 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2278 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2279
2280 /* to avoid GPU doing any preloading of constant from random address */
2281 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2282 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2283 r600_store_value(cb, 0);
2284 r600_store_value(cb, 0);
2285 r600_store_value(cb, 0);
2286 r600_store_value(cb, 0);
2287 r600_store_value(cb, 0);
2288 r600_store_value(cb, 0);
2289 r600_store_value(cb, 0);
2290 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2291 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2292 r600_store_value(cb, 0);
2293 r600_store_value(cb, 0);
2294 r600_store_value(cb, 0);
2295 r600_store_value(cb, 0);
2296 r600_store_value(cb, 0);
2297 r600_store_value(cb, 0);
2298 r600_store_value(cb, 0);
2299
2300 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2301 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2302 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2303 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2304 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2305 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2306 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2307 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2308 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2309 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2310 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2311 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2312 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2313 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2314
2315 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2316 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2317 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2318
2319 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2320 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2321 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2322
2323 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2324
2325 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2326
2327 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2328
2329 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2330 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2331 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2332 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2333
2334 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2335 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2336 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2337 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2338
2339 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2340 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2341
2342 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2343 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2344 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2345 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2346 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2347
2348 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * 16);
2349 for (tmp = 0; tmp < 16; tmp++) {
2350 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2351 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2352 }
2353
2354 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2355
2356 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2357 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2358
2359 if (rctx->b.chip_class >= R700) {
2360 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2361 }
2362
2363 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2364 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2365 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2366 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2367 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2368
2369 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2370 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2371 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2372
2373 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2374 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2375 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2376
2377 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5);
2378 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2379 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2380 r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2381 r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2382 r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2383
2384 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2385
2386 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2387 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2388 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2389
2390 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2391
2392 if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
2393 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2394 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2395 if (rctx->screen->b.has_streamout) {
2396 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2397 }
2398
2399 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2400 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2401 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF);
2402 }
2403
2404 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2405 {
2406 struct r600_context *rctx = (struct r600_context *)ctx;
2407 struct r600_command_buffer *cb = &shader->command_buffer;
2408 struct r600_shader *rshader = &shader->shader;
2409 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2410 int pos_index = -1, face_index = -1;
2411 unsigned tmp, sid, ufi = 0;
2412 int need_linear = 0;
2413 unsigned z_export = 0, stencil_export = 0;
2414 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2415
2416 if (!cb->buf) {
2417 r600_init_command_buffer(cb, 64);
2418 } else {
2419 cb->num_dw = 0;
2420 }
2421
2422 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2423 for (i = 0; i < rshader->ninput; i++) {
2424 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2425 pos_index = i;
2426 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2427 face_index = i;
2428
2429 sid = rshader->input[i].spi_sid;
2430
2431 tmp = S_028644_SEMANTIC(sid);
2432
2433 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2434 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2435 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2436 rctx->rasterizer && rctx->rasterizer->flatshade))
2437 tmp |= S_028644_FLAT_SHADE(1);
2438
2439 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2440 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2441 tmp |= S_028644_PT_SPRITE_TEX(1);
2442 }
2443
2444 if (rshader->input[i].centroid)
2445 tmp |= S_028644_SEL_CENTROID(1);
2446
2447 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2448 need_linear = 1;
2449 tmp |= S_028644_SEL_LINEAR(1);
2450 }
2451
2452 r600_store_value(cb, tmp);
2453 }
2454
2455 db_shader_control = 0;
2456 for (i = 0; i < rshader->noutput; i++) {
2457 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2458 z_export = 1;
2459 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2460 stencil_export = 1;
2461 }
2462 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2463 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2464 if (rshader->uses_kill)
2465 db_shader_control |= S_02880C_KILL_ENABLE(1);
2466
2467 exports_ps = 0;
2468 for (i = 0; i < rshader->noutput; i++) {
2469 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2470 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2471 exports_ps |= 1;
2472 }
2473 }
2474 num_cout = rshader->nr_ps_color_exports;
2475 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2476 if (!exports_ps) {
2477 /* always at least export 1 component per pixel */
2478 exports_ps = 2;
2479 }
2480
2481 shader->nr_ps_color_outputs = num_cout;
2482
2483 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2484 S_0286CC_PERSP_GRADIENT_ENA(1)|
2485 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2486 spi_input_z = 0;
2487 if (pos_index != -1) {
2488 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2489 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2490 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2491 S_0286CC_BARYC_SAMPLE_CNTL(1));
2492 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2493 }
2494
2495 spi_ps_in_control_1 = 0;
2496 if (face_index != -1) {
2497 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2498 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2499 }
2500
2501 /* HW bug in original R600 */
2502 if (rctx->b.family == CHIP_R600)
2503 ufi = 1;
2504
2505 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2506 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2507 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2508
2509 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2510
2511 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2512 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2513 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2514 S_028850_STACK_SIZE(rshader->bc.nstack) |
2515 S_028850_UNCACHED_FIRST_INST(ufi));
2516 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2517
2518 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2519 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2520
2521 /* only set some bits here, the other bits are set in the dsa state */
2522 shader->db_shader_control = db_shader_control;
2523 shader->ps_depth_export = z_export | stencil_export;
2524
2525 shader->sprite_coord_enable = sprite_coord_enable;
2526 if (rctx->rasterizer)
2527 shader->flatshade = rctx->rasterizer->flatshade;
2528 }
2529
2530 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2531 {
2532 struct r600_command_buffer *cb = &shader->command_buffer;
2533 struct r600_shader *rshader = &shader->shader;
2534 unsigned spi_vs_out_id[10] = {};
2535 unsigned i, tmp, nparams = 0;
2536
2537 for (i = 0; i < rshader->noutput; i++) {
2538 if (rshader->output[i].spi_sid) {
2539 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2540 spi_vs_out_id[nparams / 4] |= tmp;
2541 nparams++;
2542 }
2543 }
2544
2545 r600_init_command_buffer(cb, 32);
2546
2547 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2548 for (i = 0; i < 10; i++) {
2549 r600_store_value(cb, spi_vs_out_id[i]);
2550 }
2551
2552 /* Certain attributes (position, psize, etc.) don't count as params.
2553 * VS is required to export at least one param and r600_shader_from_tgsi()
2554 * takes care of adding a dummy export.
2555 */
2556 if (nparams < 1)
2557 nparams = 1;
2558
2559 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2560 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2561 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2562 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2563 S_028868_STACK_SIZE(rshader->bc.nstack));
2564 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2565 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2566
2567 shader->pa_cl_vs_out_cntl =
2568 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2569 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2570 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2571 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
2572 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2573 }
2574
2575 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
2576 {
2577 static const int prim_conv[] = {
2578 V_028A6C_OUTPRIM_TYPE_POINTLIST,
2579 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
2580 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
2581 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
2582 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
2583 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
2584 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
2585 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
2586 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
2587 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
2588 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
2589 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
2590 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
2591 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
2592 V_028A6C_OUTPRIM_TYPE_TRISTRIP
2593 };
2594 assert(mode < Elements(prim_conv));
2595
2596 return prim_conv[mode];
2597 }
2598
2599 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2600 {
2601 struct r600_context *rctx = (struct r600_context *)ctx;
2602 struct r600_command_buffer *cb = &shader->command_buffer;
2603 struct r600_shader *rshader = &shader->shader;
2604 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
2605 unsigned gsvs_itemsize =
2606 (cp_shader->ring_item_size * rshader->gs_max_out_vertices) >> 2;
2607
2608 r600_init_command_buffer(cb, 64);
2609
2610 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2611 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
2612
2613 if (rctx->b.chip_class >= R700) {
2614 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
2615 S_028B38_MAX_VERT_OUT(rshader->gs_max_out_vertices));
2616 }
2617 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
2618 r600_conv_prim_to_gs_out(rshader->gs_output_prim));
2619
2620 r600_store_context_reg_seq(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE, 4);
2621 r600_store_value(cb, cp_shader->ring_item_size >> 2);
2622 r600_store_value(cb, 0);
2623 r600_store_value(cb, 0);
2624 r600_store_value(cb, 0);
2625
2626 r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
2627 (rshader->ring_item_size) >> 2);
2628
2629 r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE,
2630 gsvs_itemsize);
2631
2632 /* FIXME calculate these values somehow ??? */
2633 r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2);
2634 r600_store_value(cb, 0x80); /* GS_PER_ES */
2635 r600_store_value(cb, 0x100); /* ES_PER_GS */
2636 r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1);
2637 r600_store_value(cb, 0x2); /* GS_PER_VS */
2638
2639 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS,
2640 S_02887C_NUM_GPRS(rshader->bc.ngpr) |
2641 S_02887C_STACK_SIZE(rshader->bc.nstack));
2642 r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS,
2643 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
2644 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2645 }
2646
2647 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2648 {
2649 struct r600_command_buffer *cb = &shader->command_buffer;
2650 struct r600_shader *rshader = &shader->shader;
2651
2652 r600_init_command_buffer(cb, 32);
2653
2654 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
2655 S_028890_NUM_GPRS(rshader->bc.ngpr) |
2656 S_028890_STACK_SIZE(rshader->bc.nstack));
2657 r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES,
2658 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
2659 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2660 }
2661
2662
2663 void *r600_create_resolve_blend(struct r600_context *rctx)
2664 {
2665 struct pipe_blend_state blend;
2666 unsigned i;
2667
2668 memset(&blend, 0, sizeof(blend));
2669 blend.independent_blend_enable = true;
2670 for (i = 0; i < 2; i++) {
2671 blend.rt[i].colormask = 0xf;
2672 blend.rt[i].blend_enable = 1;
2673 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2674 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2675 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2676 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2677 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2678 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2679 }
2680 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2681 }
2682
2683 void *r700_create_resolve_blend(struct r600_context *rctx)
2684 {
2685 struct pipe_blend_state blend;
2686
2687 memset(&blend, 0, sizeof(blend));
2688 blend.independent_blend_enable = true;
2689 blend.rt[0].colormask = 0xf;
2690 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2691 }
2692
2693 void *r600_create_decompress_blend(struct r600_context *rctx)
2694 {
2695 struct pipe_blend_state blend;
2696
2697 memset(&blend, 0, sizeof(blend));
2698 blend.independent_blend_enable = true;
2699 blend.rt[0].colormask = 0xf;
2700 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2701 }
2702
2703 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2704 {
2705 struct pipe_depth_stencil_alpha_state dsa;
2706 boolean quirk = false;
2707
2708 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2709 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2710 quirk = true;
2711
2712 memset(&dsa, 0, sizeof(dsa));
2713
2714 if (quirk) {
2715 dsa.depth.enabled = 1;
2716 dsa.depth.func = PIPE_FUNC_LEQUAL;
2717 dsa.stencil[0].enabled = 1;
2718 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2719 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2720 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2721 dsa.stencil[0].writemask = 0xff;
2722 }
2723
2724 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2725 }
2726
2727 void r600_update_db_shader_control(struct r600_context * rctx)
2728 {
2729 bool dual_export;
2730 unsigned db_shader_control;
2731
2732 if (!rctx->ps_shader) {
2733 return;
2734 }
2735
2736 dual_export = rctx->framebuffer.export_16bpc &&
2737 !rctx->ps_shader->current->ps_depth_export;
2738
2739 db_shader_control = rctx->ps_shader->current->db_shader_control |
2740 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2741
2742 /* When alpha test is enabled we can't trust the hw to make the proper
2743 * decision on the order in which ztest should be run related to fragment
2744 * shader execution.
2745 *
2746 * If alpha test is enabled perform z test after fragment. RE_Z (early
2747 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2748 */
2749 if (rctx->alphatest_state.sx_alpha_test_control) {
2750 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2751 } else {
2752 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2753 }
2754
2755 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
2756 rctx->db_misc_state.db_shader_control = db_shader_control;
2757 rctx->db_misc_state.atom.dirty = true;
2758 }
2759 }
2760
2761 static INLINE unsigned r600_array_mode(unsigned mode)
2762 {
2763 switch (mode) {
2764 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
2765 break;
2766 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
2767 break;
2768 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
2769 default:
2770 case RADEON_SURF_MODE_LINEAR: return V_0280A0_ARRAY_LINEAR_GENERAL;
2771 }
2772 }
2773
2774 static boolean r600_dma_copy_tile(struct r600_context *rctx,
2775 struct pipe_resource *dst,
2776 unsigned dst_level,
2777 unsigned dst_x,
2778 unsigned dst_y,
2779 unsigned dst_z,
2780 struct pipe_resource *src,
2781 unsigned src_level,
2782 unsigned src_x,
2783 unsigned src_y,
2784 unsigned src_z,
2785 unsigned copy_height,
2786 unsigned pitch,
2787 unsigned bpp)
2788 {
2789 struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs;
2790 struct r600_texture *rsrc = (struct r600_texture*)src;
2791 struct r600_texture *rdst = (struct r600_texture*)dst;
2792 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
2793 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
2794 uint64_t base, addr;
2795
2796 dst_mode = rdst->surface.level[dst_level].mode;
2797 src_mode = rsrc->surface.level[src_level].mode;
2798 /* downcast linear aligned to linear to simplify test */
2799 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
2800 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
2801 assert(dst_mode != src_mode);
2802
2803 y = 0;
2804 lbpp = util_logbase2(bpp);
2805 pitch_tile_max = ((pitch / bpp) >> 3) - 1;
2806
2807 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
2808 /* T2L */
2809 array_mode = r600_array_mode(src_mode);
2810 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) >> 6;
2811 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2812 /* linear height must be the same as the slice tile max height, it's ok even
2813 * if the linear destination/source have smaller heigh as the size of the
2814 * dma packet will be using the copy_height which is always smaller or equal
2815 * to the linear height
2816 */
2817 height = rsrc->surface.level[src_level].npix_y;
2818 detile = 1;
2819 x = src_x;
2820 y = src_y;
2821 z = src_z;
2822 base = rsrc->surface.level[src_level].offset;
2823 addr = rdst->surface.level[dst_level].offset;
2824 addr += rdst->surface.level[dst_level].slice_size * dst_z;
2825 addr += dst_y * pitch + dst_x * bpp;
2826 } else {
2827 /* L2T */
2828 array_mode = r600_array_mode(dst_mode);
2829 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) >> 6;
2830 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2831 /* linear height must be the same as the slice tile max height, it's ok even
2832 * if the linear destination/source have smaller heigh as the size of the
2833 * dma packet will be using the copy_height which is always smaller or equal
2834 * to the linear height
2835 */
2836 height = rdst->surface.level[dst_level].npix_y;
2837 detile = 0;
2838 x = dst_x;
2839 y = dst_y;
2840 z = dst_z;
2841 base = rdst->surface.level[dst_level].offset;
2842 addr = rsrc->surface.level[src_level].offset;
2843 addr += rsrc->surface.level[src_level].slice_size * src_z;
2844 addr += src_y * pitch + src_x * bpp;
2845 }
2846 /* check that we are in dw/base alignment constraint */
2847 if ((addr & 0x3) || (base & 0xff)) {
2848 return FALSE;
2849 }
2850
2851 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2852 * line in the blit. Compute max 8 line we can copy in the size limit
2853 */
2854 cheight = ((0x0000ffff << 2) / pitch) & 0xfffffff8;
2855 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
2856 r600_need_dma_space(&rctx->b, ncopy * 7);
2857
2858 for (i = 0; i < ncopy; i++) {
2859 cheight = cheight > copy_height ? copy_height : cheight;
2860 size = (cheight * pitch) >> 2;
2861 /* emit reloc before writting cs so that cs is always in consistent state */
2862 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rsrc->resource, RADEON_USAGE_READ,
2863 RADEON_PRIO_MIN);
2864 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rdst->resource, RADEON_USAGE_WRITE,
2865 RADEON_PRIO_MIN);
2866 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 1, 0, size);
2867 cs->buf[cs->cdw++] = base >> 8;
2868 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
2869 (lbpp << 24) | ((height - 1) << 10) |
2870 pitch_tile_max;
2871 cs->buf[cs->cdw++] = (slice_tile_max << 12) | (z << 0);
2872 cs->buf[cs->cdw++] = (x << 3) | (y << 17);
2873 cs->buf[cs->cdw++] = addr & 0xfffffffc;
2874 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
2875 copy_height -= cheight;
2876 addr += cheight * pitch;
2877 y += cheight;
2878 }
2879 return TRUE;
2880 }
2881
2882 static void r600_dma_blit(struct pipe_context *ctx,
2883 struct pipe_resource *dst,
2884 unsigned dst_level,
2885 unsigned dstx, unsigned dsty, unsigned dstz,
2886 struct pipe_resource *src,
2887 unsigned src_level,
2888 const struct pipe_box *src_box)
2889 {
2890 struct r600_context *rctx = (struct r600_context *)ctx;
2891 struct r600_texture *rsrc = (struct r600_texture*)src;
2892 struct r600_texture *rdst = (struct r600_texture*)dst;
2893 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
2894 unsigned src_w, dst_w;
2895 unsigned src_x, src_y;
2896 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
2897
2898 if (rctx->b.rings.dma.cs == NULL) {
2899 goto fallback;
2900 }
2901
2902 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
2903 if (dst_x % 4 || src_box->x % 4 || src_box->width % 4)
2904 goto fallback;
2905
2906 r600_dma_copy(rctx, dst, src, dst_x, src_box->x, src_box->width);
2907 return;
2908 }
2909
2910 if (src->format != dst->format || src_box->depth > 1) {
2911 goto fallback;
2912 }
2913
2914 src_x = util_format_get_nblocksx(src->format, src_box->x);
2915 dst_x = util_format_get_nblocksx(src->format, dst_x);
2916 src_y = util_format_get_nblocksy(src->format, src_box->y);
2917 dst_y = util_format_get_nblocksy(src->format, dst_y);
2918
2919 bpp = rdst->surface.bpe;
2920 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
2921 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
2922 src_w = rsrc->surface.level[src_level].npix_x;
2923 dst_w = rdst->surface.level[dst_level].npix_x;
2924 copy_height = src_box->height / rsrc->surface.blk_h;
2925
2926 dst_mode = rdst->surface.level[dst_level].mode;
2927 src_mode = rsrc->surface.level[src_level].mode;
2928 /* downcast linear aligned to linear to simplify test */
2929 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
2930 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
2931
2932 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
2933 /* strick requirement on r6xx/r7xx */
2934 goto fallback;
2935 }
2936 /* lot of constraint on alignment this should capture them all */
2937 if ((src_pitch & 0x7) || (src_box->y & 0x7) || (dst_y & 0x7)) {
2938 goto fallback;
2939 }
2940
2941 if (src_mode == dst_mode) {
2942 uint64_t dst_offset, src_offset, size;
2943
2944 /* simple dma blit would do NOTE code here assume :
2945 * src_box.x/y == 0
2946 * dst_x/y == 0
2947 * dst_pitch == src_pitch
2948 */
2949 src_offset= rsrc->surface.level[src_level].offset;
2950 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
2951 src_offset += src_y * src_pitch + src_x * bpp;
2952 dst_offset = rdst->surface.level[dst_level].offset;
2953 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
2954 dst_offset += dst_y * dst_pitch + dst_x * bpp;
2955 size = src_box->height * src_pitch;
2956 /* must be dw aligned */
2957 if ((dst_offset & 0x3) || (src_offset & 0x3) || (size & 0x3)) {
2958 goto fallback;
2959 }
2960 r600_dma_copy(rctx, dst, src, dst_offset, src_offset, size);
2961 } else {
2962 if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
2963 src, src_level, src_x, src_y, src_box->z,
2964 copy_height, dst_pitch, bpp)) {
2965 goto fallback;
2966 }
2967 }
2968 return;
2969
2970 fallback:
2971 ctx->resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
2972 src, src_level, src_box);
2973 }
2974
2975 void r600_init_state_functions(struct r600_context *rctx)
2976 {
2977 unsigned id = 4;
2978 int i;
2979
2980 /* !!!
2981 * To avoid GPU lockup registers must be emited in a specific order
2982 * (no kidding ...). The order below is important and have been
2983 * partialy infered from analyzing fglrx command stream.
2984 *
2985 * Don't reorder atom without carefully checking the effect (GPU lockup
2986 * or piglit regression).
2987 * !!!
2988 */
2989
2990 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
2991
2992 /* shader const */
2993 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
2994 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
2995 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
2996
2997 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2998 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
2999 */
3000 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
3001 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
3002 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
3003 /* resource */
3004 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
3005 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
3006 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
3007 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
3008
3009 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 7);
3010
3011 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3012 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3013 rctx->sample_mask.sample_mask = ~0;
3014
3015 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3016 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3017 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3018 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3019 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3020 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3021 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3022 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3023 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3024 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
3025 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3026 for (i = 0;i < 16; i++) {
3027 r600_init_atom(rctx, &rctx->scissor[i].atom, id++, r600_emit_scissor_state, 4);
3028 r600_init_atom(rctx, &rctx->viewport[i].atom, id++, r600_emit_viewport_state, 8);
3029 rctx->scissor[i].idx = i;
3030 rctx->viewport[i].idx = i;
3031 }
3032 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3033 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3034 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3035 rctx->atoms[id++] = &rctx->b.streamout.begin_atom;
3036 rctx->atoms[id++] = &rctx->b.streamout.enable_atom;
3037 r600_init_atom(rctx, &rctx->vertex_shader.atom, id++, r600_emit_shader, 23);
3038 r600_init_atom(rctx, &rctx->pixel_shader.atom, id++, r600_emit_shader, 0);
3039 r600_init_atom(rctx, &rctx->geometry_shader.atom, id++, r600_emit_shader, 0);
3040 r600_init_atom(rctx, &rctx->export_shader.atom, id++, r600_emit_shader, 0);
3041 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0);
3042 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0);
3043
3044 rctx->b.b.create_blend_state = r600_create_blend_state;
3045 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3046 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3047 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3048 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3049 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3050 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3051 rctx->b.b.set_scissor_states = r600_set_scissor_states;
3052 rctx->b.b.get_sample_position = r600_get_sample_position;
3053 rctx->b.dma_copy = r600_dma_blit;
3054 }
3055 /* this function must be last */