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r600g: initialize SQ_VTX_SEMANTIC_* in the start_cs command buffer
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600d.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31
32 static uint32_t r600_translate_blend_function(int blend_func)
33 {
34 switch (blend_func) {
35 case PIPE_BLEND_ADD:
36 return V_028804_COMB_DST_PLUS_SRC;
37 case PIPE_BLEND_SUBTRACT:
38 return V_028804_COMB_SRC_MINUS_DST;
39 case PIPE_BLEND_REVERSE_SUBTRACT:
40 return V_028804_COMB_DST_MINUS_SRC;
41 case PIPE_BLEND_MIN:
42 return V_028804_COMB_MIN_DST_SRC;
43 case PIPE_BLEND_MAX:
44 return V_028804_COMB_MAX_DST_SRC;
45 default:
46 R600_ERR("Unknown blend function %d\n", blend_func);
47 assert(0);
48 break;
49 }
50 return 0;
51 }
52
53 static uint32_t r600_translate_blend_factor(int blend_fact)
54 {
55 switch (blend_fact) {
56 case PIPE_BLENDFACTOR_ONE:
57 return V_028804_BLEND_ONE;
58 case PIPE_BLENDFACTOR_SRC_COLOR:
59 return V_028804_BLEND_SRC_COLOR;
60 case PIPE_BLENDFACTOR_SRC_ALPHA:
61 return V_028804_BLEND_SRC_ALPHA;
62 case PIPE_BLENDFACTOR_DST_ALPHA:
63 return V_028804_BLEND_DST_ALPHA;
64 case PIPE_BLENDFACTOR_DST_COLOR:
65 return V_028804_BLEND_DST_COLOR;
66 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
67 return V_028804_BLEND_SRC_ALPHA_SATURATE;
68 case PIPE_BLENDFACTOR_CONST_COLOR:
69 return V_028804_BLEND_CONST_COLOR;
70 case PIPE_BLENDFACTOR_CONST_ALPHA:
71 return V_028804_BLEND_CONST_ALPHA;
72 case PIPE_BLENDFACTOR_ZERO:
73 return V_028804_BLEND_ZERO;
74 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
75 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
76 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
77 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
78 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
79 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
80 case PIPE_BLENDFACTOR_INV_DST_COLOR:
81 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
82 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
83 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
84 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
85 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
86 case PIPE_BLENDFACTOR_SRC1_COLOR:
87 return V_028804_BLEND_SRC1_COLOR;
88 case PIPE_BLENDFACTOR_SRC1_ALPHA:
89 return V_028804_BLEND_SRC1_ALPHA;
90 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
91 return V_028804_BLEND_INV_SRC1_COLOR;
92 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
93 return V_028804_BLEND_INV_SRC1_ALPHA;
94 default:
95 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
96 assert(0);
97 break;
98 }
99 return 0;
100 }
101
102 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
103 {
104 switch (dim) {
105 default:
106 case PIPE_TEXTURE_1D:
107 return V_038000_SQ_TEX_DIM_1D;
108 case PIPE_TEXTURE_1D_ARRAY:
109 return V_038000_SQ_TEX_DIM_1D_ARRAY;
110 case PIPE_TEXTURE_2D:
111 case PIPE_TEXTURE_RECT:
112 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
113 V_038000_SQ_TEX_DIM_2D;
114 case PIPE_TEXTURE_2D_ARRAY:
115 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
116 V_038000_SQ_TEX_DIM_2D_ARRAY;
117 case PIPE_TEXTURE_3D:
118 return V_038000_SQ_TEX_DIM_3D;
119 case PIPE_TEXTURE_CUBE:
120 return V_038000_SQ_TEX_DIM_CUBEMAP;
121 }
122 }
123
124 static uint32_t r600_translate_dbformat(enum pipe_format format)
125 {
126 switch (format) {
127 case PIPE_FORMAT_Z16_UNORM:
128 return V_028010_DEPTH_16;
129 case PIPE_FORMAT_Z24X8_UNORM:
130 return V_028010_DEPTH_X8_24;
131 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
132 return V_028010_DEPTH_8_24;
133 case PIPE_FORMAT_Z32_FLOAT:
134 return V_028010_DEPTH_32_FLOAT;
135 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
136 return V_028010_DEPTH_X24_8_32_FLOAT;
137 default:
138 return ~0U;
139 }
140 }
141
142 static uint32_t r600_translate_colorswap(enum pipe_format format)
143 {
144 switch (format) {
145 /* 8-bit buffers. */
146 case PIPE_FORMAT_A8_UNORM:
147 case PIPE_FORMAT_A8_SNORM:
148 case PIPE_FORMAT_A8_UINT:
149 case PIPE_FORMAT_A8_SINT:
150 case PIPE_FORMAT_A16_UNORM:
151 case PIPE_FORMAT_A16_SNORM:
152 case PIPE_FORMAT_A16_UINT:
153 case PIPE_FORMAT_A16_SINT:
154 case PIPE_FORMAT_A16_FLOAT:
155 case PIPE_FORMAT_A32_UINT:
156 case PIPE_FORMAT_A32_SINT:
157 case PIPE_FORMAT_A32_FLOAT:
158 case PIPE_FORMAT_R4A4_UNORM:
159 return V_0280A0_SWAP_ALT_REV;
160 case PIPE_FORMAT_I8_UNORM:
161 case PIPE_FORMAT_I8_SNORM:
162 case PIPE_FORMAT_I8_UINT:
163 case PIPE_FORMAT_I8_SINT:
164 case PIPE_FORMAT_L8_UNORM:
165 case PIPE_FORMAT_L8_SNORM:
166 case PIPE_FORMAT_L8_UINT:
167 case PIPE_FORMAT_L8_SINT:
168 case PIPE_FORMAT_L8_SRGB:
169 case PIPE_FORMAT_L16_UNORM:
170 case PIPE_FORMAT_L16_SNORM:
171 case PIPE_FORMAT_L16_UINT:
172 case PIPE_FORMAT_L16_SINT:
173 case PIPE_FORMAT_L16_FLOAT:
174 case PIPE_FORMAT_L32_UINT:
175 case PIPE_FORMAT_L32_SINT:
176 case PIPE_FORMAT_L32_FLOAT:
177 case PIPE_FORMAT_I16_UNORM:
178 case PIPE_FORMAT_I16_SNORM:
179 case PIPE_FORMAT_I16_UINT:
180 case PIPE_FORMAT_I16_SINT:
181 case PIPE_FORMAT_I16_FLOAT:
182 case PIPE_FORMAT_I32_UINT:
183 case PIPE_FORMAT_I32_SINT:
184 case PIPE_FORMAT_I32_FLOAT:
185 case PIPE_FORMAT_R8_UNORM:
186 case PIPE_FORMAT_R8_SNORM:
187 case PIPE_FORMAT_R8_UINT:
188 case PIPE_FORMAT_R8_SINT:
189 return V_0280A0_SWAP_STD;
190
191 case PIPE_FORMAT_L4A4_UNORM:
192 case PIPE_FORMAT_A4R4_UNORM:
193 return V_0280A0_SWAP_ALT;
194
195 /* 16-bit buffers. */
196 case PIPE_FORMAT_B5G6R5_UNORM:
197 return V_0280A0_SWAP_STD_REV;
198
199 case PIPE_FORMAT_B5G5R5A1_UNORM:
200 case PIPE_FORMAT_B5G5R5X1_UNORM:
201 return V_0280A0_SWAP_ALT;
202
203 case PIPE_FORMAT_B4G4R4A4_UNORM:
204 case PIPE_FORMAT_B4G4R4X4_UNORM:
205 return V_0280A0_SWAP_ALT;
206
207 case PIPE_FORMAT_Z16_UNORM:
208 return V_0280A0_SWAP_STD;
209
210 case PIPE_FORMAT_L8A8_UNORM:
211 case PIPE_FORMAT_L8A8_SNORM:
212 case PIPE_FORMAT_L8A8_UINT:
213 case PIPE_FORMAT_L8A8_SINT:
214 case PIPE_FORMAT_L8A8_SRGB:
215 case PIPE_FORMAT_L16A16_UNORM:
216 case PIPE_FORMAT_L16A16_SNORM:
217 case PIPE_FORMAT_L16A16_UINT:
218 case PIPE_FORMAT_L16A16_SINT:
219 case PIPE_FORMAT_L16A16_FLOAT:
220 case PIPE_FORMAT_L32A32_UINT:
221 case PIPE_FORMAT_L32A32_SINT:
222 case PIPE_FORMAT_L32A32_FLOAT:
223 return V_0280A0_SWAP_ALT;
224 case PIPE_FORMAT_R8G8_UNORM:
225 case PIPE_FORMAT_R8G8_SNORM:
226 case PIPE_FORMAT_R8G8_UINT:
227 case PIPE_FORMAT_R8G8_SINT:
228 return V_0280A0_SWAP_STD;
229
230 case PIPE_FORMAT_R16_UNORM:
231 case PIPE_FORMAT_R16_SNORM:
232 case PIPE_FORMAT_R16_UINT:
233 case PIPE_FORMAT_R16_SINT:
234 case PIPE_FORMAT_R16_FLOAT:
235 return V_0280A0_SWAP_STD;
236
237 /* 32-bit buffers. */
238
239 case PIPE_FORMAT_A8B8G8R8_SRGB:
240 return V_0280A0_SWAP_STD_REV;
241 case PIPE_FORMAT_B8G8R8A8_SRGB:
242 return V_0280A0_SWAP_ALT;
243
244 case PIPE_FORMAT_B8G8R8A8_UNORM:
245 case PIPE_FORMAT_B8G8R8X8_UNORM:
246 return V_0280A0_SWAP_ALT;
247
248 case PIPE_FORMAT_A8R8G8B8_UNORM:
249 case PIPE_FORMAT_X8R8G8B8_UNORM:
250 return V_0280A0_SWAP_ALT_REV;
251 case PIPE_FORMAT_R8G8B8A8_SNORM:
252 case PIPE_FORMAT_R8G8B8A8_UNORM:
253 case PIPE_FORMAT_R8G8B8X8_UNORM:
254 case PIPE_FORMAT_R8G8B8A8_SINT:
255 case PIPE_FORMAT_R8G8B8A8_UINT:
256 return V_0280A0_SWAP_STD;
257
258 case PIPE_FORMAT_A8B8G8R8_UNORM:
259 case PIPE_FORMAT_X8B8G8R8_UNORM:
260 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
261 return V_0280A0_SWAP_STD_REV;
262
263 case PIPE_FORMAT_Z24X8_UNORM:
264 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
265 return V_0280A0_SWAP_STD;
266
267 case PIPE_FORMAT_X8Z24_UNORM:
268 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
269 return V_0280A0_SWAP_STD;
270
271 case PIPE_FORMAT_R10G10B10A2_UNORM:
272 case PIPE_FORMAT_R10G10B10X2_SNORM:
273 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
274 return V_0280A0_SWAP_STD;
275
276 case PIPE_FORMAT_B10G10R10A2_UNORM:
277 case PIPE_FORMAT_B10G10R10A2_UINT:
278 return V_0280A0_SWAP_ALT;
279
280 case PIPE_FORMAT_R11G11B10_FLOAT:
281 case PIPE_FORMAT_R16G16_UNORM:
282 case PIPE_FORMAT_R16G16_SNORM:
283 case PIPE_FORMAT_R16G16_FLOAT:
284 case PIPE_FORMAT_R16G16_UINT:
285 case PIPE_FORMAT_R16G16_SINT:
286 case PIPE_FORMAT_R32_UINT:
287 case PIPE_FORMAT_R32_SINT:
288 case PIPE_FORMAT_R32_FLOAT:
289 case PIPE_FORMAT_Z32_FLOAT:
290 return V_0280A0_SWAP_STD;
291
292 /* 64-bit buffers. */
293 case PIPE_FORMAT_R32G32_FLOAT:
294 case PIPE_FORMAT_R32G32_UINT:
295 case PIPE_FORMAT_R32G32_SINT:
296 case PIPE_FORMAT_R16G16B16A16_UNORM:
297 case PIPE_FORMAT_R16G16B16A16_SNORM:
298 case PIPE_FORMAT_R16G16B16A16_UINT:
299 case PIPE_FORMAT_R16G16B16A16_SINT:
300 case PIPE_FORMAT_R16G16B16A16_FLOAT:
301 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
302
303 /* 128-bit buffers. */
304 case PIPE_FORMAT_R32G32B32A32_FLOAT:
305 case PIPE_FORMAT_R32G32B32A32_SNORM:
306 case PIPE_FORMAT_R32G32B32A32_UNORM:
307 case PIPE_FORMAT_R32G32B32A32_SINT:
308 case PIPE_FORMAT_R32G32B32A32_UINT:
309 return V_0280A0_SWAP_STD;
310 default:
311 R600_ERR("unsupported colorswap format %d\n", format);
312 return ~0U;
313 }
314 return ~0U;
315 }
316
317 static uint32_t r600_translate_colorformat(enum pipe_format format)
318 {
319 switch (format) {
320 case PIPE_FORMAT_L4A4_UNORM:
321 case PIPE_FORMAT_R4A4_UNORM:
322 case PIPE_FORMAT_A4R4_UNORM:
323 return V_0280A0_COLOR_4_4;
324
325 /* 8-bit buffers. */
326 case PIPE_FORMAT_A8_UNORM:
327 case PIPE_FORMAT_A8_SNORM:
328 case PIPE_FORMAT_A8_UINT:
329 case PIPE_FORMAT_A8_SINT:
330 case PIPE_FORMAT_I8_UNORM:
331 case PIPE_FORMAT_I8_SNORM:
332 case PIPE_FORMAT_I8_UINT:
333 case PIPE_FORMAT_I8_SINT:
334 case PIPE_FORMAT_L8_UNORM:
335 case PIPE_FORMAT_L8_SNORM:
336 case PIPE_FORMAT_L8_UINT:
337 case PIPE_FORMAT_L8_SINT:
338 case PIPE_FORMAT_L8_SRGB:
339 case PIPE_FORMAT_R8_UNORM:
340 case PIPE_FORMAT_R8_SNORM:
341 case PIPE_FORMAT_R8_UINT:
342 case PIPE_FORMAT_R8_SINT:
343 return V_0280A0_COLOR_8;
344
345 /* 16-bit buffers. */
346 case PIPE_FORMAT_B5G6R5_UNORM:
347 return V_0280A0_COLOR_5_6_5;
348
349 case PIPE_FORMAT_B5G5R5A1_UNORM:
350 case PIPE_FORMAT_B5G5R5X1_UNORM:
351 return V_0280A0_COLOR_1_5_5_5;
352
353 case PIPE_FORMAT_B4G4R4A4_UNORM:
354 case PIPE_FORMAT_B4G4R4X4_UNORM:
355 return V_0280A0_COLOR_4_4_4_4;
356
357 case PIPE_FORMAT_Z16_UNORM:
358 return V_0280A0_COLOR_16;
359
360 case PIPE_FORMAT_L8A8_UNORM:
361 case PIPE_FORMAT_L8A8_SNORM:
362 case PIPE_FORMAT_L8A8_UINT:
363 case PIPE_FORMAT_L8A8_SINT:
364 case PIPE_FORMAT_L8A8_SRGB:
365 case PIPE_FORMAT_R8G8_UNORM:
366 case PIPE_FORMAT_R8G8_SNORM:
367 case PIPE_FORMAT_R8G8_UINT:
368 case PIPE_FORMAT_R8G8_SINT:
369 return V_0280A0_COLOR_8_8;
370
371 case PIPE_FORMAT_R16_UNORM:
372 case PIPE_FORMAT_R16_SNORM:
373 case PIPE_FORMAT_R16_UINT:
374 case PIPE_FORMAT_R16_SINT:
375 case PIPE_FORMAT_A16_UNORM:
376 case PIPE_FORMAT_A16_SNORM:
377 case PIPE_FORMAT_A16_UINT:
378 case PIPE_FORMAT_A16_SINT:
379 case PIPE_FORMAT_L16_UNORM:
380 case PIPE_FORMAT_L16_SNORM:
381 case PIPE_FORMAT_L16_UINT:
382 case PIPE_FORMAT_L16_SINT:
383 case PIPE_FORMAT_I16_UNORM:
384 case PIPE_FORMAT_I16_SNORM:
385 case PIPE_FORMAT_I16_UINT:
386 case PIPE_FORMAT_I16_SINT:
387 return V_0280A0_COLOR_16;
388
389 case PIPE_FORMAT_R16_FLOAT:
390 case PIPE_FORMAT_A16_FLOAT:
391 case PIPE_FORMAT_L16_FLOAT:
392 case PIPE_FORMAT_I16_FLOAT:
393 return V_0280A0_COLOR_16_FLOAT;
394
395 /* 32-bit buffers. */
396 case PIPE_FORMAT_A8B8G8R8_SRGB:
397 case PIPE_FORMAT_A8B8G8R8_UNORM:
398 case PIPE_FORMAT_A8R8G8B8_UNORM:
399 case PIPE_FORMAT_B8G8R8A8_SRGB:
400 case PIPE_FORMAT_B8G8R8A8_UNORM:
401 case PIPE_FORMAT_B8G8R8X8_UNORM:
402 case PIPE_FORMAT_R8G8B8A8_SNORM:
403 case PIPE_FORMAT_R8G8B8A8_UNORM:
404 case PIPE_FORMAT_R8G8B8X8_UNORM:
405 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
406 case PIPE_FORMAT_X8B8G8R8_UNORM:
407 case PIPE_FORMAT_X8R8G8B8_UNORM:
408 case PIPE_FORMAT_R8G8B8A8_SINT:
409 case PIPE_FORMAT_R8G8B8A8_UINT:
410 return V_0280A0_COLOR_8_8_8_8;
411
412 case PIPE_FORMAT_R10G10B10A2_UNORM:
413 case PIPE_FORMAT_R10G10B10X2_SNORM:
414 case PIPE_FORMAT_B10G10R10A2_UNORM:
415 case PIPE_FORMAT_B10G10R10A2_UINT:
416 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
417 return V_0280A0_COLOR_2_10_10_10;
418
419 case PIPE_FORMAT_Z24X8_UNORM:
420 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
421 return V_0280A0_COLOR_8_24;
422
423 case PIPE_FORMAT_X8Z24_UNORM:
424 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
425 return V_0280A0_COLOR_24_8;
426
427 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
428 return V_0280A0_COLOR_X24_8_32_FLOAT;
429
430 case PIPE_FORMAT_R32_UINT:
431 case PIPE_FORMAT_R32_SINT:
432 case PIPE_FORMAT_A32_UINT:
433 case PIPE_FORMAT_A32_SINT:
434 case PIPE_FORMAT_L32_UINT:
435 case PIPE_FORMAT_L32_SINT:
436 case PIPE_FORMAT_I32_UINT:
437 case PIPE_FORMAT_I32_SINT:
438 return V_0280A0_COLOR_32;
439
440 case PIPE_FORMAT_R32_FLOAT:
441 case PIPE_FORMAT_A32_FLOAT:
442 case PIPE_FORMAT_L32_FLOAT:
443 case PIPE_FORMAT_I32_FLOAT:
444 case PIPE_FORMAT_Z32_FLOAT:
445 return V_0280A0_COLOR_32_FLOAT;
446
447 case PIPE_FORMAT_R16G16_FLOAT:
448 case PIPE_FORMAT_L16A16_FLOAT:
449 return V_0280A0_COLOR_16_16_FLOAT;
450
451 case PIPE_FORMAT_R16G16_UNORM:
452 case PIPE_FORMAT_R16G16_SNORM:
453 case PIPE_FORMAT_R16G16_UINT:
454 case PIPE_FORMAT_R16G16_SINT:
455 case PIPE_FORMAT_L16A16_UNORM:
456 case PIPE_FORMAT_L16A16_SNORM:
457 case PIPE_FORMAT_L16A16_UINT:
458 case PIPE_FORMAT_L16A16_SINT:
459 return V_0280A0_COLOR_16_16;
460
461 case PIPE_FORMAT_R11G11B10_FLOAT:
462 return V_0280A0_COLOR_10_11_11_FLOAT;
463
464 /* 64-bit buffers. */
465 case PIPE_FORMAT_R16G16B16A16_UINT:
466 case PIPE_FORMAT_R16G16B16A16_SINT:
467 case PIPE_FORMAT_R16G16B16A16_UNORM:
468 case PIPE_FORMAT_R16G16B16A16_SNORM:
469 return V_0280A0_COLOR_16_16_16_16;
470
471 case PIPE_FORMAT_R16G16B16A16_FLOAT:
472 return V_0280A0_COLOR_16_16_16_16_FLOAT;
473
474 case PIPE_FORMAT_R32G32_FLOAT:
475 case PIPE_FORMAT_L32A32_FLOAT:
476 return V_0280A0_COLOR_32_32_FLOAT;
477
478 case PIPE_FORMAT_R32G32_SINT:
479 case PIPE_FORMAT_R32G32_UINT:
480 case PIPE_FORMAT_L32A32_UINT:
481 case PIPE_FORMAT_L32A32_SINT:
482 return V_0280A0_COLOR_32_32;
483
484 /* 128-bit buffers. */
485 case PIPE_FORMAT_R32G32B32A32_FLOAT:
486 return V_0280A0_COLOR_32_32_32_32_FLOAT;
487 case PIPE_FORMAT_R32G32B32A32_SNORM:
488 case PIPE_FORMAT_R32G32B32A32_UNORM:
489 case PIPE_FORMAT_R32G32B32A32_SINT:
490 case PIPE_FORMAT_R32G32B32A32_UINT:
491 return V_0280A0_COLOR_32_32_32_32;
492
493 /* YUV buffers. */
494 case PIPE_FORMAT_UYVY:
495 case PIPE_FORMAT_YUYV:
496 default:
497 return ~0U; /* Unsupported. */
498 }
499 }
500
501 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
502 {
503 if (R600_BIG_ENDIAN) {
504 switch(colorformat) {
505 case V_0280A0_COLOR_4_4:
506 return ENDIAN_NONE;
507
508 /* 8-bit buffers. */
509 case V_0280A0_COLOR_8:
510 return ENDIAN_NONE;
511
512 /* 16-bit buffers. */
513 case V_0280A0_COLOR_5_6_5:
514 case V_0280A0_COLOR_1_5_5_5:
515 case V_0280A0_COLOR_4_4_4_4:
516 case V_0280A0_COLOR_16:
517 case V_0280A0_COLOR_8_8:
518 return ENDIAN_8IN16;
519
520 /* 32-bit buffers. */
521 case V_0280A0_COLOR_8_8_8_8:
522 case V_0280A0_COLOR_2_10_10_10:
523 case V_0280A0_COLOR_8_24:
524 case V_0280A0_COLOR_24_8:
525 case V_0280A0_COLOR_32_FLOAT:
526 case V_0280A0_COLOR_16_16_FLOAT:
527 case V_0280A0_COLOR_16_16:
528 return ENDIAN_8IN32;
529
530 /* 64-bit buffers. */
531 case V_0280A0_COLOR_16_16_16_16:
532 case V_0280A0_COLOR_16_16_16_16_FLOAT:
533 return ENDIAN_8IN16;
534
535 case V_0280A0_COLOR_32_32_FLOAT:
536 case V_0280A0_COLOR_32_32:
537 case V_0280A0_COLOR_X24_8_32_FLOAT:
538 return ENDIAN_8IN32;
539
540 /* 128-bit buffers. */
541 case V_0280A0_COLOR_32_32_32_FLOAT:
542 case V_0280A0_COLOR_32_32_32_32_FLOAT:
543 case V_0280A0_COLOR_32_32_32_32:
544 return ENDIAN_8IN32;
545 default:
546 return ENDIAN_NONE; /* Unsupported. */
547 }
548 } else {
549 return ENDIAN_NONE;
550 }
551 }
552
553 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
554 {
555 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
556 }
557
558 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
559 {
560 return r600_translate_colorformat(format) != ~0U &&
561 r600_translate_colorswap(format) != ~0U;
562 }
563
564 static bool r600_is_zs_format_supported(enum pipe_format format)
565 {
566 return r600_translate_dbformat(format) != ~0U;
567 }
568
569 boolean r600_is_format_supported(struct pipe_screen *screen,
570 enum pipe_format format,
571 enum pipe_texture_target target,
572 unsigned sample_count,
573 unsigned usage)
574 {
575 struct r600_screen *rscreen = (struct r600_screen*)screen;
576 unsigned retval = 0;
577
578 if (target >= PIPE_MAX_TEXTURE_TYPES) {
579 R600_ERR("r600: unsupported texture type %d\n", target);
580 return FALSE;
581 }
582
583 if (!util_format_is_supported(format, usage))
584 return FALSE;
585
586 if (sample_count > 1) {
587 if (rscreen->info.drm_minor < 22)
588 return FALSE;
589
590 /* R11G11B10 is broken on R6xx. */
591 if (rscreen->chip_class == R600 &&
592 format == PIPE_FORMAT_R11G11B10_FLOAT)
593 return FALSE;
594
595 /* MSAA integer colorbuffers hang. */
596 if (util_format_is_pure_integer(format) &&
597 !util_format_is_depth_or_stencil(format))
598 return FALSE;
599
600 switch (sample_count) {
601 case 2:
602 case 4:
603 case 8:
604 break;
605 default:
606 return FALSE;
607 }
608 }
609
610 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
611 r600_is_sampler_format_supported(screen, format)) {
612 retval |= PIPE_BIND_SAMPLER_VIEW;
613 }
614
615 if ((usage & (PIPE_BIND_RENDER_TARGET |
616 PIPE_BIND_DISPLAY_TARGET |
617 PIPE_BIND_SCANOUT |
618 PIPE_BIND_SHARED)) &&
619 r600_is_colorbuffer_format_supported(format)) {
620 retval |= usage &
621 (PIPE_BIND_RENDER_TARGET |
622 PIPE_BIND_DISPLAY_TARGET |
623 PIPE_BIND_SCANOUT |
624 PIPE_BIND_SHARED);
625 }
626
627 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
628 r600_is_zs_format_supported(format)) {
629 retval |= PIPE_BIND_DEPTH_STENCIL;
630 }
631
632 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
633 r600_is_vertex_format_supported(format)) {
634 retval |= PIPE_BIND_VERTEX_BUFFER;
635 }
636
637 if (usage & PIPE_BIND_TRANSFER_READ)
638 retval |= PIPE_BIND_TRANSFER_READ;
639 if (usage & PIPE_BIND_TRANSFER_WRITE)
640 retval |= PIPE_BIND_TRANSFER_WRITE;
641
642 return retval == usage;
643 }
644
645 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
646 {
647 struct radeon_winsys_cs *cs = rctx->cs;
648 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
649 float offset_units = state->offset_units;
650 float offset_scale = state->offset_scale;
651
652 switch (state->zs_format) {
653 case PIPE_FORMAT_Z24X8_UNORM:
654 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
655 offset_units *= 2.0f;
656 break;
657 case PIPE_FORMAT_Z16_UNORM:
658 offset_units *= 4.0f;
659 break;
660 default:;
661 }
662
663 r600_write_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
664 r600_write_value(cs, fui(offset_scale));
665 r600_write_value(cs, fui(offset_units));
666 r600_write_value(cs, fui(offset_scale));
667 r600_write_value(cs, fui(offset_units));
668 }
669
670 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
671 {
672 int j = state->independent_blend_enable ? i : 0;
673
674 unsigned eqRGB = state->rt[j].rgb_func;
675 unsigned srcRGB = state->rt[j].rgb_src_factor;
676 unsigned dstRGB = state->rt[j].rgb_dst_factor;
677
678 unsigned eqA = state->rt[j].alpha_func;
679 unsigned srcA = state->rt[j].alpha_src_factor;
680 unsigned dstA = state->rt[j].alpha_dst_factor;
681 uint32_t bc = 0;
682
683 if (!state->rt[j].blend_enable)
684 return 0;
685
686 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
687 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
688 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
689
690 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
691 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
692 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
693 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
694 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
695 }
696 return bc;
697 }
698
699 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
700 const struct pipe_blend_state *state,
701 int mode)
702 {
703 struct r600_context *rctx = (struct r600_context *)ctx;
704 uint32_t color_control = 0, target_mask = 0;
705 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
706
707 if (!blend) {
708 return NULL;
709 }
710
711 r600_init_command_buffer(&blend->buffer, 20);
712 r600_init_command_buffer(&blend->buffer_no_blend, 20);
713
714 /* R600 does not support per-MRT blends */
715 if (rctx->family > CHIP_R600)
716 color_control |= S_028808_PER_MRT_BLEND(1);
717
718 if (state->logicop_enable) {
719 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
720 } else {
721 color_control |= (0xcc << 16);
722 }
723 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
724 if (state->independent_blend_enable) {
725 for (int i = 0; i < 8; i++) {
726 if (state->rt[i].blend_enable) {
727 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
728 }
729 target_mask |= (state->rt[i].colormask << (4 * i));
730 }
731 } else {
732 for (int i = 0; i < 8; i++) {
733 if (state->rt[0].blend_enable) {
734 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
735 }
736 target_mask |= (state->rt[0].colormask << (4 * i));
737 }
738 }
739
740 if (target_mask)
741 color_control |= S_028808_SPECIAL_OP(mode);
742 else
743 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
744
745 /* only MRT0 has dual src blend */
746 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
747 blend->cb_target_mask = target_mask;
748 blend->cb_color_control = color_control;
749 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
750 blend->alpha_to_one = state->alpha_to_one;
751
752 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
753 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
754 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
755 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
756 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
757 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
758
759 /* Copy over the registers set so far into buffer_no_blend. */
760 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
761 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
762
763 /* Only add blend registers if blending is enabled. */
764 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
765 return blend;
766 }
767
768 /* The first R600 does not support per-MRT blends */
769 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
770 r600_get_blend_control(state, 0));
771
772 if (rctx->family > CHIP_R600) {
773 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
774 for (int i = 0; i < 8; i++) {
775 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
776 }
777 }
778 return blend;
779 }
780
781 static void *r600_create_blend_state(struct pipe_context *ctx,
782 const struct pipe_blend_state *state)
783 {
784 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
785 }
786
787 static void *r600_create_dsa_state(struct pipe_context *ctx,
788 const struct pipe_depth_stencil_alpha_state *state)
789 {
790 struct r600_context *rctx = (struct r600_context *)ctx;
791 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
792 unsigned db_depth_control, alpha_test_control, alpha_ref;
793 struct r600_pipe_state *rstate;
794
795 if (dsa == NULL) {
796 return NULL;
797 }
798
799 dsa->valuemask[0] = state->stencil[0].valuemask;
800 dsa->valuemask[1] = state->stencil[1].valuemask;
801 dsa->writemask[0] = state->stencil[0].writemask;
802 dsa->writemask[1] = state->stencil[1].writemask;
803
804 rstate = &dsa->rstate;
805
806 rstate->id = R600_PIPE_STATE_DSA;
807 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
808 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
809 S_028800_ZFUNC(state->depth.func);
810
811 /* stencil */
812 if (state->stencil[0].enabled) {
813 db_depth_control |= S_028800_STENCIL_ENABLE(1);
814 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
815 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
816 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
817 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
818
819 if (state->stencil[1].enabled) {
820 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
821 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
822 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
823 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
824 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
825 }
826 }
827
828 /* alpha */
829 alpha_test_control = 0;
830 alpha_ref = 0;
831 if (state->alpha.enabled) {
832 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
833 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
834 alpha_ref = fui(state->alpha.ref_value);
835 }
836 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
837 dsa->alpha_ref = alpha_ref;
838
839 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
840 return rstate;
841 }
842
843 static void *r600_create_rs_state(struct pipe_context *ctx,
844 const struct pipe_rasterizer_state *state)
845 {
846 struct r600_context *rctx = (struct r600_context *)ctx;
847 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
848 struct r600_pipe_state *rstate;
849 unsigned tmp;
850 unsigned prov_vtx = 1, polygon_dual_mode;
851 unsigned sc_mode_cntl;
852 float psize_min, psize_max;
853
854 if (rs == NULL) {
855 return NULL;
856 }
857
858 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
859 state->fill_back != PIPE_POLYGON_MODE_FILL);
860
861 if (state->flatshade_first)
862 prov_vtx = 0;
863
864 rstate = &rs->rstate;
865 rs->flatshade = state->flatshade;
866 rs->sprite_coord_enable = state->sprite_coord_enable;
867 rs->two_side = state->light_twoside;
868 rs->clip_plane_enable = state->clip_plane_enable;
869 rs->pa_sc_line_stipple = state->line_stipple_enable ?
870 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
871 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
872 rs->pa_cl_clip_cntl =
873 S_028810_PS_UCP_MODE(3) |
874 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
875 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
876 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
877 rs->multisample_enable = state->multisample;
878
879 /* offset */
880 rs->offset_units = state->offset_units;
881 rs->offset_scale = state->offset_scale * 12.0f;
882 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
883
884 rstate->id = R600_PIPE_STATE_RASTERIZER;
885 tmp = S_0286D4_FLAT_SHADE_ENA(1);
886 if (state->sprite_coord_enable) {
887 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
888 S_0286D4_PNT_SPRITE_OVRD_X(2) |
889 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
890 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
891 S_0286D4_PNT_SPRITE_OVRD_W(1);
892 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
893 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
894 }
895 }
896 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
897
898 /* point size 12.4 fixed point */
899 tmp = r600_pack_float_12p4(state->point_size/2);
900 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
901
902 if (state->point_size_per_vertex) {
903 psize_min = util_get_min_point_size(state);
904 psize_max = 8192;
905 } else {
906 /* Force the point size to be as if the vertex output was disabled. */
907 psize_min = state->point_size;
908 psize_max = state->point_size;
909 }
910 /* Divide by two, because 0.5 = 1 pixel. */
911 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
912 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
913 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
914
915 tmp = r600_pack_float_12p4(state->line_width/2);
916 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
917
918 if (rctx->chip_class >= R700) {
919 sc_mode_cntl =
920 S_028A4C_MSAA_ENABLE(state->multisample) |
921 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
922 S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
923 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
924 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
925 } else {
926 sc_mode_cntl =
927 S_028A4C_MSAA_ENABLE(state->multisample) |
928 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
929 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
930 rs->scissor_enable = state->scissor;
931 }
932 sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
933
934 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
935
936 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
937 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
938 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
939
940 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
941 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
942 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
943 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
944 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
945 S_028814_FACE(!state->front_ccw) |
946 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
947 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
948 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
949 S_028814_POLY_MODE(polygon_dual_mode) |
950 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
951 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
952 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
953 return rstate;
954 }
955
956 static void *r600_create_sampler_state(struct pipe_context *ctx,
957 const struct pipe_sampler_state *state)
958 {
959 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
960 union util_color uc;
961 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
962
963 if (ss == NULL) {
964 return NULL;
965 }
966
967 ss->seamless_cube_map = state->seamless_cube_map;
968 ss->border_color_use = false;
969 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
970 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
971 ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
972 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
973 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
974 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
975 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
976 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
977 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
978 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
979 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
980 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
981 ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
982 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
983 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
984 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
985 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
986 if (uc.ui) {
987 ss->border_color_use = true;
988 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
989 ss->border_color[0] = fui(state->border_color.f[0]);
990 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
991 ss->border_color[1] = fui(state->border_color.f[1]);
992 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
993 ss->border_color[2] = fui(state->border_color.f[2]);
994 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
995 ss->border_color[3] = fui(state->border_color.f[3]);
996 }
997 return ss;
998 }
999
1000 struct pipe_sampler_view *
1001 r600_create_sampler_view_custom(struct pipe_context *ctx,
1002 struct pipe_resource *texture,
1003 const struct pipe_sampler_view *state,
1004 unsigned width_first_level, unsigned height_first_level)
1005 {
1006 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1007 struct r600_texture *tmp = (struct r600_texture*)texture;
1008 unsigned format, endian;
1009 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1010 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1011 unsigned width, height, depth, offset_level, last_level;
1012
1013 if (view == NULL)
1014 return NULL;
1015
1016 /* initialize base object */
1017 view->base = *state;
1018 view->base.texture = NULL;
1019 pipe_reference(NULL, &texture->reference);
1020 view->base.texture = texture;
1021 view->base.reference.count = 1;
1022 view->base.context = ctx;
1023
1024 swizzle[0] = state->swizzle_r;
1025 swizzle[1] = state->swizzle_g;
1026 swizzle[2] = state->swizzle_b;
1027 swizzle[3] = state->swizzle_a;
1028
1029 format = r600_translate_texformat(ctx->screen, state->format,
1030 swizzle,
1031 &word4, &yuv_format);
1032 assert(format != ~0);
1033 if (format == ~0) {
1034 FREE(view);
1035 return NULL;
1036 }
1037
1038 if (tmp->is_depth && !tmp->is_flushing_texture) {
1039 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1040 FREE(view);
1041 return NULL;
1042 }
1043 tmp = tmp->flushed_depth_texture;
1044 }
1045
1046 endian = r600_colorformat_endian_swap(format);
1047
1048 offset_level = state->u.tex.first_level;
1049 last_level = state->u.tex.last_level - offset_level;
1050 width = width_first_level;
1051 height = height_first_level;
1052 depth = tmp->surface.level[offset_level].npix_z;
1053 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1054 tile_type = tmp->tile_type;
1055
1056 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1057 height = 1;
1058 depth = texture->array_size;
1059 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1060 depth = texture->array_size;
1061 }
1062 switch (tmp->surface.level[offset_level].mode) {
1063 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1064 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1065 break;
1066 case RADEON_SURF_MODE_1D:
1067 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1068 break;
1069 case RADEON_SURF_MODE_2D:
1070 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1071 break;
1072 case RADEON_SURF_MODE_LINEAR:
1073 default:
1074 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1075 break;
1076 }
1077
1078 view->tex_resource = &tmp->resource;
1079 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1080 S_038000_TILE_MODE(array_mode) |
1081 S_038000_TILE_TYPE(tile_type) |
1082 S_038000_PITCH((pitch / 8) - 1) |
1083 S_038000_TEX_WIDTH(width - 1));
1084 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
1085 S_038004_TEX_DEPTH(depth - 1) |
1086 S_038004_DATA_FORMAT(format));
1087 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
1088 if (offset_level >= tmp->surface.last_level) {
1089 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
1090 } else {
1091 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1092 }
1093 view->tex_resource_words[4] = (word4 |
1094 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1095 S_038010_REQUEST_SIZE(1) |
1096 S_038010_ENDIAN_SWAP(endian) |
1097 S_038010_BASE_LEVEL(0));
1098 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1099 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1100 if (texture->nr_samples > 1) {
1101 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1102 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
1103 } else {
1104 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
1105 }
1106 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1107 S_038018_MAX_ANISO(4 /* max 16 samples */));
1108 return &view->base;
1109 }
1110
1111 static struct pipe_sampler_view *
1112 r600_create_sampler_view(struct pipe_context *ctx,
1113 struct pipe_resource *tex,
1114 const struct pipe_sampler_view *state)
1115 {
1116 struct r600_texture *rtex = (struct r600_texture*)tex;
1117
1118 return r600_create_sampler_view_custom(ctx, tex, state,
1119 rtex->surface.level[state->u.tex.first_level].npix_x,
1120 rtex->surface.level[state->u.tex.first_level].npix_y);
1121 }
1122
1123 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1124 {
1125 struct radeon_winsys_cs *cs = rctx->cs;
1126 struct pipe_clip_state *state = &rctx->clip_state.state;
1127
1128 r600_write_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
1129 r600_write_array(cs, 6*4, (unsigned*)state);
1130 }
1131
1132 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1133 const struct pipe_poly_stipple *state)
1134 {
1135 }
1136
1137 static void r600_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
1138 {
1139 struct radeon_winsys_cs *cs = rctx->cs;
1140 struct pipe_scissor_state *state = &rctx->scissor.scissor;
1141
1142 if (rctx->chip_class != R600 || rctx->scissor.enable) {
1143 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1144 r600_write_value(cs, S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) |
1145 S_028240_WINDOW_OFFSET_DISABLE(1));
1146 r600_write_value(cs, S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy));
1147 } else {
1148 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1149 r600_write_value(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1150 S_028240_WINDOW_OFFSET_DISABLE(1));
1151 r600_write_value(cs, S_028244_BR_X(8192) | S_028244_BR_Y(8192));
1152 }
1153 }
1154
1155 static void r600_set_scissor_state(struct pipe_context *ctx,
1156 const struct pipe_scissor_state *state)
1157 {
1158 struct r600_context *rctx = (struct r600_context *)ctx;
1159
1160 rctx->scissor.scissor = *state;
1161
1162 if (rctx->chip_class == R600 && !rctx->scissor.enable)
1163 return;
1164
1165 rctx->scissor.atom.dirty = true;
1166 }
1167
1168 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
1169 unsigned size, unsigned alignment)
1170 {
1171 struct pipe_resource buffer;
1172
1173 memset(&buffer, 0, sizeof buffer);
1174 buffer.target = PIPE_BUFFER;
1175 buffer.format = PIPE_FORMAT_R8_UNORM;
1176 buffer.bind = PIPE_BIND_CUSTOM;
1177 buffer.usage = PIPE_USAGE_STATIC;
1178 buffer.flags = 0;
1179 buffer.width0 = size;
1180 buffer.height0 = 1;
1181 buffer.depth0 = 1;
1182 buffer.array_size = 1;
1183
1184 return (struct r600_resource*)
1185 r600_buffer_create(&rscreen->screen, &buffer, alignment);
1186 }
1187
1188 static void r600_init_color_surface(struct r600_context *rctx,
1189 struct r600_surface *surf,
1190 bool force_cmask_fmask)
1191 {
1192 struct r600_screen *rscreen = rctx->screen;
1193 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1194 unsigned level = surf->base.u.tex.level;
1195 unsigned pitch, slice;
1196 unsigned color_info;
1197 unsigned format, swap, ntype, endian;
1198 unsigned offset;
1199 const struct util_format_description *desc;
1200 int i;
1201 bool blend_bypass = 0, blend_clamp = 1;
1202
1203 if (rtex->is_depth && !rtex->is_flushing_texture) {
1204 r600_init_flushed_depth_texture(&rctx->context, surf->base.texture, NULL);
1205 rtex = rtex->flushed_depth_texture;
1206 assert(rtex);
1207 }
1208
1209 offset = rtex->surface.level[level].offset;
1210 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1211 offset += rtex->surface.level[level].slice_size *
1212 surf->base.u.tex.first_layer;
1213 }
1214 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1215 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1216 if (slice) {
1217 slice = slice - 1;
1218 }
1219 color_info = 0;
1220 switch (rtex->surface.level[level].mode) {
1221 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1222 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1223 break;
1224 case RADEON_SURF_MODE_1D:
1225 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1226 break;
1227 case RADEON_SURF_MODE_2D:
1228 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1229 break;
1230 case RADEON_SURF_MODE_LINEAR:
1231 default:
1232 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1233 break;
1234 }
1235
1236 desc = util_format_description(surf->base.format);
1237
1238 for (i = 0; i < 4; i++) {
1239 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1240 break;
1241 }
1242 }
1243
1244 ntype = V_0280A0_NUMBER_UNORM;
1245 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1246 ntype = V_0280A0_NUMBER_SRGB;
1247 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1248 if (desc->channel[i].normalized)
1249 ntype = V_0280A0_NUMBER_SNORM;
1250 else if (desc->channel[i].pure_integer)
1251 ntype = V_0280A0_NUMBER_SINT;
1252 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1253 if (desc->channel[i].normalized)
1254 ntype = V_0280A0_NUMBER_UNORM;
1255 else if (desc->channel[i].pure_integer)
1256 ntype = V_0280A0_NUMBER_UINT;
1257 }
1258
1259 format = r600_translate_colorformat(surf->base.format);
1260 assert(format != ~0);
1261
1262 swap = r600_translate_colorswap(surf->base.format);
1263 assert(swap != ~0);
1264
1265 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1266 endian = ENDIAN_NONE;
1267 } else {
1268 endian = r600_colorformat_endian_swap(format);
1269 }
1270
1271 /* set blend bypass according to docs if SINT/UINT or
1272 8/24 COLOR variants */
1273 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1274 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1275 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1276 blend_clamp = 0;
1277 blend_bypass = 1;
1278 }
1279
1280 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
1281
1282 color_info |= S_0280A0_FORMAT(format) |
1283 S_0280A0_COMP_SWAP(swap) |
1284 S_0280A0_BLEND_BYPASS(blend_bypass) |
1285 S_0280A0_BLEND_CLAMP(blend_clamp) |
1286 S_0280A0_NUMBER_TYPE(ntype) |
1287 S_0280A0_ENDIAN(endian);
1288
1289 /* EXPORT_NORM is an optimzation that can be enabled for better
1290 * performance in certain cases
1291 */
1292 if (rctx->chip_class == R600) {
1293 /* EXPORT_NORM can be enabled if:
1294 * - 11-bit or smaller UNORM/SNORM/SRGB
1295 * - BLEND_CLAMP is enabled
1296 * - BLEND_FLOAT32 is disabled
1297 */
1298 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1299 (desc->channel[i].size < 12 &&
1300 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1301 ntype != V_0280A0_NUMBER_UINT &&
1302 ntype != V_0280A0_NUMBER_SINT) &&
1303 G_0280A0_BLEND_CLAMP(color_info) &&
1304 !G_0280A0_BLEND_FLOAT32(color_info)) {
1305 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1306 surf->export_16bpc = true;
1307 }
1308 } else {
1309 /* EXPORT_NORM can be enabled if:
1310 * - 11-bit or smaller UNORM/SNORM/SRGB
1311 * - 16-bit or smaller FLOAT
1312 */
1313 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1314 ((desc->channel[i].size < 12 &&
1315 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1316 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1317 (desc->channel[i].size < 17 &&
1318 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1319 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1320 surf->export_16bpc = true;
1321 }
1322 }
1323
1324 /* These might not always be initialized to zero. */
1325 surf->cb_color_base = offset >> 8;
1326 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
1327 S_028060_SLICE_TILE_MAX(slice);
1328 surf->cb_color_fmask = surf->cb_color_base;
1329 surf->cb_color_cmask = surf->cb_color_base;
1330 surf->cb_color_mask = 0;
1331
1332 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1333 &rtex->resource.b.b);
1334 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1335 &rtex->resource.b.b);
1336
1337 if (rtex->cmask_size) {
1338 surf->cb_color_cmask = rtex->cmask_offset >> 8;
1339 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask_slice_tile_max);
1340
1341 if (rtex->fmask_size) {
1342 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1343 surf->cb_color_fmask = rtex->fmask_offset >> 8;
1344 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(slice);
1345 } else { /* cmask only */
1346 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
1347 }
1348 } else if (force_cmask_fmask) {
1349 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1350 *
1351 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1352 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1353 * because it's not an MSAA buffer.
1354 */
1355 struct r600_cmask_info cmask;
1356 struct r600_fmask_info fmask;
1357
1358 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
1359 r600_texture_get_fmask_info(rscreen, rtex, 8, &fmask);
1360
1361 /* CMASK. */
1362 if (!rctx->dummy_cmask ||
1363 rctx->dummy_cmask->buf->size < cmask.size ||
1364 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1365 struct pipe_transfer *transfer;
1366 void *ptr;
1367
1368 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1369 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1370
1371 /* Set the contents to 0xCC. */
1372 ptr = pipe_buffer_map(&rctx->context, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1373 memset(ptr, 0xCC, cmask.size);
1374 pipe_buffer_unmap(&rctx->context, transfer);
1375 }
1376 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1377 &rctx->dummy_cmask->b.b);
1378
1379 /* FMASK. */
1380 if (!rctx->dummy_fmask ||
1381 rctx->dummy_fmask->buf->size < fmask.size ||
1382 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1383 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1384 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1385
1386 }
1387 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1388 &rctx->dummy_fmask->b.b);
1389
1390 /* Init the registers. */
1391 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1392 surf->cb_color_cmask = 0;
1393 surf->cb_color_fmask = 0;
1394 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1395 S_028100_FMASK_TILE_MAX(slice);
1396 }
1397
1398 surf->cb_color_info = color_info;
1399
1400 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1401 surf->cb_color_view = 0;
1402 } else {
1403 surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
1404 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
1405 }
1406
1407 surf->color_initialized = true;
1408 }
1409
1410 static void r600_init_depth_surface(struct r600_context *rctx,
1411 struct r600_surface *surf)
1412 {
1413 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1414 unsigned level, pitch, slice, format, offset, array_mode;
1415
1416 level = surf->base.u.tex.level;
1417 offset = rtex->surface.level[level].offset;
1418 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1419 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1420 if (slice) {
1421 slice = slice - 1;
1422 }
1423 switch (rtex->surface.level[level].mode) {
1424 case RADEON_SURF_MODE_2D:
1425 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1426 break;
1427 case RADEON_SURF_MODE_1D:
1428 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1429 case RADEON_SURF_MODE_LINEAR:
1430 default:
1431 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1432 break;
1433 }
1434
1435 format = r600_translate_dbformat(surf->base.format);
1436 assert(format != ~0);
1437
1438 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1439 surf->db_depth_base = offset >> 8;
1440 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1441 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1442 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1443 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1444
1445 switch (surf->base.format) {
1446 case PIPE_FORMAT_Z24X8_UNORM:
1447 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1448 surf->pa_su_poly_offset_db_fmt_cntl =
1449 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1450 break;
1451 case PIPE_FORMAT_Z32_FLOAT:
1452 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1453 surf->pa_su_poly_offset_db_fmt_cntl =
1454 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1455 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1456 break;
1457 case PIPE_FORMAT_Z16_UNORM:
1458 surf->pa_su_poly_offset_db_fmt_cntl =
1459 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1460 break;
1461 default:;
1462 }
1463
1464 surf->depth_initialized = true;
1465 }
1466
1467 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1468 const struct pipe_framebuffer_state *state)
1469 {
1470 struct r600_context *rctx = (struct r600_context *)ctx;
1471 struct r600_surface *surf;
1472 struct r600_texture *rtex;
1473 unsigned i;
1474
1475 if (rctx->framebuffer.state.nr_cbufs) {
1476 rctx->flags |= R600_CONTEXT_CB_FLUSH;
1477
1478 if (rctx->chip_class >= R700 &&
1479 rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
1480 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
1481 }
1482 }
1483 if (rctx->framebuffer.state.zsbuf) {
1484 rctx->flags |= R600_CONTEXT_DB_FLUSH;
1485 }
1486 /* R6xx errata */
1487 if (rctx->chip_class == R600) {
1488 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
1489 }
1490
1491 /* Set the new state. */
1492 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1493
1494 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1495 rctx->framebuffer.cb0_is_integer = state->nr_cbufs &&
1496 util_format_is_pure_integer(state->cbufs[0]->format);
1497 rctx->framebuffer.compressed_cb_mask = 0;
1498 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1499 state->cbufs[0]->texture->nr_samples > 1 &&
1500 state->cbufs[1]->texture->nr_samples <= 1;
1501
1502 if (state->nr_cbufs)
1503 rctx->framebuffer.nr_samples = state->cbufs[0]->texture->nr_samples;
1504 else if (state->zsbuf)
1505 rctx->framebuffer.nr_samples = state->zsbuf->texture->nr_samples;
1506 else
1507 rctx->framebuffer.nr_samples = 0;
1508
1509 /* Colorbuffers. */
1510 for (i = 0; i < state->nr_cbufs; i++) {
1511 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1512 bool force_cmask_fmask = rctx->chip_class == R600 &&
1513 rctx->framebuffer.is_msaa_resolve &&
1514 i == 1;
1515
1516 surf = (struct r600_surface*)state->cbufs[i];
1517 rtex = (struct r600_texture*)surf->base.texture;
1518
1519 if (!surf->color_initialized || force_cmask_fmask) {
1520 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1521 if (force_cmask_fmask) {
1522 /* re-initialize later without compression */
1523 surf->color_initialized = false;
1524 }
1525 }
1526
1527 if (!surf->export_16bpc) {
1528 rctx->framebuffer.export_16bpc = false;
1529 }
1530
1531 if (rtex->fmask_size && rtex->cmask_size) {
1532 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1533 }
1534 }
1535
1536 /* Update alpha-test state dependencies.
1537 * Alpha-test is done on the first colorbuffer only. */
1538 if (state->nr_cbufs) {
1539 surf = (struct r600_surface*)state->cbufs[0];
1540 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1541 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1542 rctx->alphatest_state.atom.dirty = true;
1543 }
1544 }
1545
1546 /* ZS buffer. */
1547 if (state->zsbuf) {
1548 surf = (struct r600_surface*)state->zsbuf;
1549
1550 if (!surf->depth_initialized) {
1551 r600_init_depth_surface(rctx, surf);
1552 }
1553
1554 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1555 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1556 rctx->poly_offset_state.atom.dirty = true;
1557 }
1558 }
1559
1560 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1561 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1562 rctx->cb_misc_state.atom.dirty = true;
1563 }
1564
1565 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1566 rctx->alphatest_state.bypass = false;
1567 rctx->alphatest_state.atom.dirty = true;
1568 }
1569
1570 /* Calculate the CS size. */
1571 rctx->framebuffer.atom.num_dw =
1572 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1573
1574 if (rctx->framebuffer.state.nr_cbufs) {
1575 rctx->framebuffer.atom.num_dw += 6 * (2 + rctx->framebuffer.state.nr_cbufs);
1576 rctx->framebuffer.atom.num_dw += 6 * rctx->framebuffer.state.nr_cbufs; /* relocs */
1577
1578 }
1579 if (rctx->framebuffer.state.zsbuf) {
1580 rctx->framebuffer.atom.num_dw += 16;
1581 } else if (rctx->screen->info.drm_minor >= 18) {
1582 rctx->framebuffer.atom.num_dw += 3;
1583 }
1584 if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770) {
1585 rctx->framebuffer.atom.num_dw += 2;
1586 }
1587
1588 rctx->framebuffer.atom.dirty = true;
1589 }
1590
1591 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1592 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1593 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1594 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1595 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1596
1597 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1598 {
1599 static uint32_t sample_locs_2x[] = {
1600 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1601 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1602 };
1603 static unsigned max_dist_2x = 4;
1604 static uint32_t sample_locs_4x[] = {
1605 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1606 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1607 };
1608 static unsigned max_dist_4x = 6;
1609 static uint32_t sample_locs_8x[] = {
1610 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1611 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1612 };
1613 static unsigned max_dist_8x = 8;
1614
1615 struct radeon_winsys_cs *cs = rctx->cs;
1616 unsigned max_dist = 0;
1617
1618 if (rctx->family == CHIP_R600) {
1619 switch (nr_samples) {
1620 default:
1621 nr_samples = 0;
1622 break;
1623 case 2:
1624 r600_write_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1625 max_dist = max_dist_2x;
1626 break;
1627 case 4:
1628 r600_write_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1629 max_dist = max_dist_4x;
1630 break;
1631 case 8:
1632 r600_write_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1633 r600_write_value(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1634 r600_write_value(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1635 max_dist = max_dist_8x;
1636 break;
1637 }
1638 } else {
1639 switch (nr_samples) {
1640 default:
1641 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1642 r600_write_value(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1643 r600_write_value(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1644 nr_samples = 0;
1645 break;
1646 case 2:
1647 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1648 r600_write_value(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1649 r600_write_value(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1650 max_dist = max_dist_2x;
1651 break;
1652 case 4:
1653 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1654 r600_write_value(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1655 r600_write_value(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1656 max_dist = max_dist_4x;
1657 break;
1658 case 8:
1659 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1660 r600_write_value(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1661 r600_write_value(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1662 max_dist = max_dist_8x;
1663 break;
1664 }
1665 }
1666
1667 if (nr_samples > 1) {
1668 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1669 r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
1670 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1671 r600_write_value(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1672 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1673 } else {
1674 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1675 r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1676 r600_write_value(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1677 }
1678 }
1679
1680 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1681 {
1682 struct radeon_winsys_cs *cs = rctx->cs;
1683 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1684 unsigned nr_cbufs = state->nr_cbufs;
1685 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1686 unsigned i, sbu = 0;
1687
1688 /* Colorbuffers. */
1689 r600_write_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1690 for (i = 0; i < nr_cbufs; i++) {
1691 r600_write_value(cs, cb[i]->cb_color_info);
1692 }
1693 /* set CB_COLOR1_INFO for possible dual-src blending */
1694 if (i == 1) {
1695 r600_write_value(cs, cb[0]->cb_color_info);
1696 i++;
1697 }
1698 for (; i < 8; i++) {
1699 r600_write_value(cs, 0);
1700 }
1701
1702 if (nr_cbufs) {
1703 /* COLOR_BASE */
1704 r600_write_context_reg_seq(cs, R_028040_CB_COLOR0_BASE, nr_cbufs);
1705 for (i = 0; i < nr_cbufs; i++) {
1706 r600_write_value(cs, cb[i]->cb_color_base);
1707 }
1708
1709 /* relocations */
1710 for (i = 0; i < nr_cbufs; i++) {
1711 unsigned reloc = r600_context_bo_reloc(rctx,
1712 (struct r600_resource*)cb[i]->base.texture,
1713 RADEON_USAGE_READWRITE);
1714 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1715 r600_write_value(cs, reloc);
1716 }
1717
1718 r600_write_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1719 for (i = 0; i < nr_cbufs; i++) {
1720 r600_write_value(cs, cb[i]->cb_color_size);
1721 }
1722
1723 r600_write_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1724 for (i = 0; i < nr_cbufs; i++) {
1725 r600_write_value(cs, cb[i]->cb_color_view);
1726 }
1727
1728 r600_write_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1729 for (i = 0; i < nr_cbufs; i++) {
1730 r600_write_value(cs, cb[i]->cb_color_mask);
1731 }
1732
1733 /* FMASK. */
1734 r600_write_context_reg_seq(cs, R_0280E0_CB_COLOR0_FRAG, nr_cbufs);
1735 for (i = 0; i < nr_cbufs; i++) {
1736 r600_write_value(cs, cb[i]->cb_color_fmask);
1737 }
1738 /* relocations */
1739 for (i = 0; i < nr_cbufs; i++) {
1740 unsigned reloc = r600_context_bo_reloc(rctx,
1741 cb[i]->cb_buffer_fmask,
1742 RADEON_USAGE_READWRITE);
1743 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1744 r600_write_value(cs, reloc);
1745 }
1746
1747 /* CMASK. */
1748 r600_write_context_reg_seq(cs, R_0280C0_CB_COLOR0_TILE, nr_cbufs);
1749 for (i = 0; i < nr_cbufs; i++) {
1750 r600_write_value(cs, cb[i]->cb_color_cmask);
1751 }
1752 /* relocations */
1753 for (i = 0; i < nr_cbufs; i++) {
1754 unsigned reloc = r600_context_bo_reloc(rctx,
1755 cb[i]->cb_buffer_cmask,
1756 RADEON_USAGE_READWRITE);
1757 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1758 r600_write_value(cs, reloc);
1759 }
1760
1761 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1762 }
1763
1764 /* Zbuffer. */
1765 if (state->zsbuf) {
1766 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1767 unsigned reloc = r600_context_bo_reloc(rctx,
1768 (struct r600_resource*)state->zsbuf->texture,
1769 RADEON_USAGE_READWRITE);
1770
1771 r600_write_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1772 surf->pa_su_poly_offset_db_fmt_cntl);
1773
1774 r600_write_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1775 r600_write_value(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1776 r600_write_value(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1777 r600_write_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1778 r600_write_value(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1779 r600_write_value(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1780
1781 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1782 r600_write_value(cs, reloc);
1783
1784 r600_write_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1785
1786 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1787 } else if (rctx->screen->info.drm_minor >= 18) {
1788 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1789 * Older kernels are out of luck. */
1790 r600_write_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1791 }
1792
1793 /* SURFACE_BASE_UPDATE */
1794 if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770 && sbu) {
1795 r600_write_value(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1796 r600_write_value(cs, sbu);
1797 }
1798
1799 /* Framebuffer dimensions. */
1800 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1801 r600_write_value(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1802 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1803 r600_write_value(cs, S_028244_BR_X(state->width) |
1804 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1805
1806 if (rctx->framebuffer.is_msaa_resolve) {
1807 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1808 } else {
1809 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1810 * will assure that the alpha-test will work even if there is
1811 * no colorbuffer bound. */
1812 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1813 (1ull << MAX2(nr_cbufs, 1)) - 1);
1814 }
1815
1816 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1817 }
1818
1819 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1820 {
1821 struct radeon_winsys_cs *cs = rctx->cs;
1822 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1823
1824 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1825 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1826 if (rctx->chip_class == R600) {
1827 r600_write_value(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1828 r600_write_value(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1829 } else {
1830 r600_write_value(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1831 r600_write_value(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1832 }
1833 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1834 } else {
1835 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1836 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1837 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1838
1839 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1840 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1841 /* Always enable the first color output to make sure alpha-test works even without one. */
1842 r600_write_value(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1843 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1844 a->cb_color_control |
1845 S_028808_MULTIWRITE_ENABLE(multiwrite));
1846 }
1847 }
1848
1849 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1850 {
1851 struct radeon_winsys_cs *cs = rctx->cs;
1852 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1853 unsigned db_render_control = 0;
1854 unsigned db_render_override =
1855 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
1856 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1857 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1858
1859 if (a->occlusion_query_enabled) {
1860 if (rctx->chip_class >= R700) {
1861 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1862 }
1863 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1864 }
1865 if (a->flush_depthstencil_through_cb) {
1866 assert(a->copy_depth || a->copy_stencil);
1867
1868 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1869 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1870 S_028D0C_COPY_CENTROID(1) |
1871 S_028D0C_COPY_SAMPLE(a->copy_sample);
1872 }
1873
1874 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1875 r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1876 r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1877 }
1878
1879 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1880 {
1881 struct radeon_winsys_cs *cs = rctx->cs;
1882 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1883
1884 while (dirty_mask) {
1885 struct pipe_vertex_buffer *vb;
1886 struct r600_resource *rbuffer;
1887 unsigned offset;
1888 unsigned buffer_index = u_bit_scan(&dirty_mask);
1889
1890 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1891 rbuffer = (struct r600_resource*)vb->buffer;
1892 assert(rbuffer);
1893
1894 offset = vb->buffer_offset;
1895
1896 /* fetch resources start at index 320 */
1897 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1898 r600_write_value(cs, (320 + buffer_index) * 7);
1899 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1900 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1901 r600_write_value(cs, /* RESOURCEi_WORD2 */
1902 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1903 S_038008_STRIDE(vb->stride));
1904 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1905 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1906 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1907 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1908
1909 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1910 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1911 }
1912 }
1913
1914 static void r600_emit_constant_buffers(struct r600_context *rctx,
1915 struct r600_constbuf_state *state,
1916 unsigned buffer_id_base,
1917 unsigned reg_alu_constbuf_size,
1918 unsigned reg_alu_const_cache)
1919 {
1920 struct radeon_winsys_cs *cs = rctx->cs;
1921 uint32_t dirty_mask = state->dirty_mask;
1922
1923 while (dirty_mask) {
1924 struct pipe_constant_buffer *cb;
1925 struct r600_resource *rbuffer;
1926 unsigned offset;
1927 unsigned buffer_index = ffs(dirty_mask) - 1;
1928
1929 cb = &state->cb[buffer_index];
1930 rbuffer = (struct r600_resource*)cb->buffer;
1931 assert(rbuffer);
1932
1933 offset = cb->buffer_offset;
1934
1935 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1936 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1937 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1938
1939 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1940 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1941
1942 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1943 r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
1944 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1945 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1946 r600_write_value(cs, /* RESOURCEi_WORD2 */
1947 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1948 S_038008_STRIDE(16));
1949 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1950 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1951 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1952 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1953
1954 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1955 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1956
1957 dirty_mask &= ~(1 << buffer_index);
1958 }
1959 state->dirty_mask = 0;
1960 }
1961
1962 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1963 {
1964 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 160,
1965 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1966 R_028980_ALU_CONST_CACHE_VS_0);
1967 }
1968
1969 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1970 {
1971 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
1972 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1973 R_0289C0_ALU_CONST_CACHE_GS_0);
1974 }
1975
1976 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1977 {
1978 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
1979 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1980 R_028940_ALU_CONST_CACHE_PS_0);
1981 }
1982
1983 static void r600_emit_sampler_views(struct r600_context *rctx,
1984 struct r600_samplerview_state *state,
1985 unsigned resource_id_base)
1986 {
1987 struct radeon_winsys_cs *cs = rctx->cs;
1988 uint32_t dirty_mask = state->dirty_mask;
1989
1990 while (dirty_mask) {
1991 struct r600_pipe_sampler_view *rview;
1992 unsigned resource_index = u_bit_scan(&dirty_mask);
1993 unsigned reloc;
1994
1995 rview = state->views[resource_index];
1996 assert(rview);
1997
1998 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1999 r600_write_value(cs, (resource_id_base + resource_index) * 7);
2000 r600_write_array(cs, 7, rview->tex_resource_words);
2001
2002 /* XXX The kernel needs two relocations. This is stupid. */
2003 reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
2004 RADEON_USAGE_READ);
2005 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2006 r600_write_value(cs, reloc);
2007 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2008 r600_write_value(cs, reloc);
2009 }
2010 state->dirty_mask = 0;
2011 }
2012
2013 /* Resource IDs:
2014 * PS: 0 .. +160
2015 * VS: 160 .. +160
2016 * FS: 320 .. +16
2017 * GS: 336 .. +160
2018 */
2019
2020 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2021 {
2022 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 160 + R600_MAX_CONST_BUFFERS);
2023 }
2024
2025 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2026 {
2027 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
2028 }
2029
2030 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2031 {
2032 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
2033 }
2034
2035 static void r600_emit_sampler_states(struct r600_context *rctx,
2036 struct r600_textures_info *texinfo,
2037 unsigned resource_id_base,
2038 unsigned border_color_reg)
2039 {
2040 struct radeon_winsys_cs *cs = rctx->cs;
2041 uint32_t dirty_mask = texinfo->states.dirty_mask;
2042
2043 while (dirty_mask) {
2044 struct r600_pipe_sampler_state *rstate;
2045 struct r600_pipe_sampler_view *rview;
2046 unsigned i = u_bit_scan(&dirty_mask);
2047
2048 rstate = texinfo->states.states[i];
2049 assert(rstate);
2050 rview = texinfo->views.views[i];
2051
2052 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
2053 * filtering between layers.
2054 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
2055 */
2056 if (rview) {
2057 enum pipe_texture_target target = rview->base.texture->target;
2058 if (target == PIPE_TEXTURE_1D_ARRAY ||
2059 target == PIPE_TEXTURE_2D_ARRAY) {
2060 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
2061 texinfo->is_array_sampler[i] = true;
2062 } else {
2063 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
2064 texinfo->is_array_sampler[i] = false;
2065 }
2066 }
2067
2068 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2069 r600_write_value(cs, (resource_id_base + i) * 3);
2070 r600_write_array(cs, 3, rstate->tex_sampler_words);
2071
2072 if (rstate->border_color_use) {
2073 unsigned offset;
2074
2075 offset = border_color_reg;
2076 offset += i * 16;
2077 r600_write_config_reg_seq(cs, offset, 4);
2078 r600_write_array(cs, 4, rstate->border_color);
2079 }
2080 }
2081 texinfo->states.dirty_mask = 0;
2082 }
2083
2084 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2085 {
2086 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
2087 }
2088
2089 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2090 {
2091 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
2092 }
2093
2094 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2095 {
2096 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
2097 }
2098
2099 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
2100 {
2101 struct radeon_winsys_cs *cs = rctx->cs;
2102 unsigned tmp;
2103
2104 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
2105 S_009508_SYNC_GRADIENT(1) |
2106 S_009508_SYNC_WALKER(1) |
2107 S_009508_SYNC_ALIGNER(1);
2108 if (!rctx->seamless_cube_map.enabled) {
2109 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
2110 }
2111 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
2112 }
2113
2114 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2115 {
2116 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2117 uint8_t mask = s->sample_mask;
2118
2119 r600_write_context_reg(rctx->cs, R_028C48_PA_SC_AA_MASK,
2120 mask | (mask << 8) | (mask << 16) | (mask << 24));
2121 }
2122
2123 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2124 {
2125 struct radeon_winsys_cs *cs = rctx->cs;
2126 struct r600_cso_state *state = (struct r600_cso_state*)a;
2127 struct r600_resource *shader = (struct r600_resource*)state->cso;
2128
2129 r600_write_context_reg(cs, R_028894_SQ_PGM_START_FS, 0);
2130 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2131 r600_write_value(cs, r600_context_bo_reloc(rctx, shader, RADEON_USAGE_READ));
2132 }
2133
2134 void r600_init_state_functions(struct r600_context *rctx)
2135 {
2136 unsigned id = 4;
2137
2138 /* !!!
2139 * To avoid GPU lockup registers must be emited in a specific order
2140 * (no kidding ...). The order below is important and have been
2141 * partialy infered from analyzing fglrx command stream.
2142 *
2143 * Don't reorder atom without carefully checking the effect (GPU lockup
2144 * or piglit regression).
2145 * !!!
2146 */
2147
2148 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
2149
2150 /* shader const */
2151 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
2152 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
2153 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
2154
2155 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2156 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
2157 */
2158 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
2159 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
2160 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
2161 /* resource */
2162 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
2163 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
2164 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
2165 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
2166
2167 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 6);
2168 r600_init_atom(rctx, &rctx->vgt2_state.atom, id++, r600_emit_vgt2_state, 3);
2169
2170 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
2171 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
2172 rctx->sample_mask.sample_mask = ~0;
2173
2174 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
2175 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
2176 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
2177 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
2178 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
2179 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
2180 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 4);
2181 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
2182 r600_init_atom(rctx, &rctx->scissor.atom, id++, r600_emit_scissor_state, 4);
2183 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
2184 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
2185 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
2186
2187 rctx->context.create_blend_state = r600_create_blend_state;
2188 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
2189 rctx->context.create_rasterizer_state = r600_create_rs_state;
2190 rctx->context.create_sampler_state = r600_create_sampler_state;
2191 rctx->context.create_sampler_view = r600_create_sampler_view;
2192 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
2193 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
2194 rctx->context.set_scissor_state = r600_set_scissor_state;
2195 }
2196
2197 /* Adjust GPR allocation on R6xx/R7xx */
2198 void r600_adjust_gprs(struct r600_context *rctx)
2199 {
2200 struct r600_pipe_state rstate;
2201 unsigned num_ps_gprs = rctx->default_ps_gprs;
2202 unsigned num_vs_gprs = rctx->default_vs_gprs;
2203 unsigned tmp;
2204 int diff;
2205
2206 if (rctx->ps_shader->current->shader.bc.ngpr > rctx->default_ps_gprs) {
2207 diff = rctx->ps_shader->current->shader.bc.ngpr - rctx->default_ps_gprs;
2208 num_vs_gprs -= diff;
2209 num_ps_gprs += diff;
2210 }
2211
2212 if (rctx->vs_shader->current->shader.bc.ngpr > rctx->default_vs_gprs)
2213 {
2214 diff = rctx->vs_shader->current->shader.bc.ngpr - rctx->default_vs_gprs;
2215 num_ps_gprs -= diff;
2216 num_vs_gprs += diff;
2217 }
2218
2219 tmp = 0;
2220 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2221 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2222 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
2223 rstate.nregs = 0;
2224 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp);
2225
2226 r600_context_pipe_state_set(rctx, &rstate);
2227 }
2228
2229 void r600_init_atom_start_cs(struct r600_context *rctx)
2230 {
2231 int ps_prio;
2232 int vs_prio;
2233 int gs_prio;
2234 int es_prio;
2235 int num_ps_gprs;
2236 int num_vs_gprs;
2237 int num_gs_gprs;
2238 int num_es_gprs;
2239 int num_temp_gprs;
2240 int num_ps_threads;
2241 int num_vs_threads;
2242 int num_gs_threads;
2243 int num_es_threads;
2244 int num_ps_stack_entries;
2245 int num_vs_stack_entries;
2246 int num_gs_stack_entries;
2247 int num_es_stack_entries;
2248 enum radeon_family family;
2249 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2250 uint32_t tmp;
2251
2252 r600_init_command_buffer(cb, 256);
2253
2254 /* R6xx requires this packet at the start of each command buffer */
2255 if (rctx->chip_class == R600) {
2256 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2257 r600_store_value(cb, 0);
2258 }
2259 /* All asics require this one */
2260 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2261 r600_store_value(cb, 0x80000000);
2262 r600_store_value(cb, 0x80000000);
2263
2264 family = rctx->family;
2265 ps_prio = 0;
2266 vs_prio = 1;
2267 gs_prio = 2;
2268 es_prio = 3;
2269 switch (family) {
2270 case CHIP_R600:
2271 num_ps_gprs = 192;
2272 num_vs_gprs = 56;
2273 num_temp_gprs = 4;
2274 num_gs_gprs = 0;
2275 num_es_gprs = 0;
2276 num_ps_threads = 136;
2277 num_vs_threads = 48;
2278 num_gs_threads = 4;
2279 num_es_threads = 4;
2280 num_ps_stack_entries = 128;
2281 num_vs_stack_entries = 128;
2282 num_gs_stack_entries = 0;
2283 num_es_stack_entries = 0;
2284 break;
2285 case CHIP_RV630:
2286 case CHIP_RV635:
2287 num_ps_gprs = 84;
2288 num_vs_gprs = 36;
2289 num_temp_gprs = 4;
2290 num_gs_gprs = 0;
2291 num_es_gprs = 0;
2292 num_ps_threads = 144;
2293 num_vs_threads = 40;
2294 num_gs_threads = 4;
2295 num_es_threads = 4;
2296 num_ps_stack_entries = 40;
2297 num_vs_stack_entries = 40;
2298 num_gs_stack_entries = 32;
2299 num_es_stack_entries = 16;
2300 break;
2301 case CHIP_RV610:
2302 case CHIP_RV620:
2303 case CHIP_RS780:
2304 case CHIP_RS880:
2305 default:
2306 num_ps_gprs = 84;
2307 num_vs_gprs = 36;
2308 num_temp_gprs = 4;
2309 num_gs_gprs = 0;
2310 num_es_gprs = 0;
2311 num_ps_threads = 136;
2312 num_vs_threads = 48;
2313 num_gs_threads = 4;
2314 num_es_threads = 4;
2315 num_ps_stack_entries = 40;
2316 num_vs_stack_entries = 40;
2317 num_gs_stack_entries = 32;
2318 num_es_stack_entries = 16;
2319 break;
2320 case CHIP_RV670:
2321 num_ps_gprs = 144;
2322 num_vs_gprs = 40;
2323 num_temp_gprs = 4;
2324 num_gs_gprs = 0;
2325 num_es_gprs = 0;
2326 num_ps_threads = 136;
2327 num_vs_threads = 48;
2328 num_gs_threads = 4;
2329 num_es_threads = 4;
2330 num_ps_stack_entries = 40;
2331 num_vs_stack_entries = 40;
2332 num_gs_stack_entries = 32;
2333 num_es_stack_entries = 16;
2334 break;
2335 case CHIP_RV770:
2336 num_ps_gprs = 192;
2337 num_vs_gprs = 56;
2338 num_temp_gprs = 4;
2339 num_gs_gprs = 0;
2340 num_es_gprs = 0;
2341 num_ps_threads = 188;
2342 num_vs_threads = 60;
2343 num_gs_threads = 0;
2344 num_es_threads = 0;
2345 num_ps_stack_entries = 256;
2346 num_vs_stack_entries = 256;
2347 num_gs_stack_entries = 0;
2348 num_es_stack_entries = 0;
2349 break;
2350 case CHIP_RV730:
2351 case CHIP_RV740:
2352 num_ps_gprs = 84;
2353 num_vs_gprs = 36;
2354 num_temp_gprs = 4;
2355 num_gs_gprs = 0;
2356 num_es_gprs = 0;
2357 num_ps_threads = 188;
2358 num_vs_threads = 60;
2359 num_gs_threads = 0;
2360 num_es_threads = 0;
2361 num_ps_stack_entries = 128;
2362 num_vs_stack_entries = 128;
2363 num_gs_stack_entries = 0;
2364 num_es_stack_entries = 0;
2365 break;
2366 case CHIP_RV710:
2367 num_ps_gprs = 192;
2368 num_vs_gprs = 56;
2369 num_temp_gprs = 4;
2370 num_gs_gprs = 0;
2371 num_es_gprs = 0;
2372 num_ps_threads = 144;
2373 num_vs_threads = 48;
2374 num_gs_threads = 0;
2375 num_es_threads = 0;
2376 num_ps_stack_entries = 128;
2377 num_vs_stack_entries = 128;
2378 num_gs_stack_entries = 0;
2379 num_es_stack_entries = 0;
2380 break;
2381 }
2382
2383 rctx->default_ps_gprs = num_ps_gprs;
2384 rctx->default_vs_gprs = num_vs_gprs;
2385 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2386
2387 /* SQ_CONFIG */
2388 tmp = 0;
2389 switch (family) {
2390 case CHIP_RV610:
2391 case CHIP_RV620:
2392 case CHIP_RS780:
2393 case CHIP_RS880:
2394 case CHIP_RV710:
2395 break;
2396 default:
2397 tmp |= S_008C00_VC_ENABLE(1);
2398 break;
2399 }
2400 tmp |= S_008C00_DX9_CONSTS(0);
2401 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2402 tmp |= S_008C00_PS_PRIO(ps_prio);
2403 tmp |= S_008C00_VS_PRIO(vs_prio);
2404 tmp |= S_008C00_GS_PRIO(gs_prio);
2405 tmp |= S_008C00_ES_PRIO(es_prio);
2406 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2407
2408 /* SQ_GPR_RESOURCE_MGMT_2 */
2409 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2410 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2411 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2412 r600_store_value(cb, tmp);
2413
2414 /* SQ_THREAD_RESOURCE_MGMT */
2415 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2416 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2417 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2418 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2419 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2420
2421 /* SQ_STACK_RESOURCE_MGMT_1 */
2422 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2423 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2424 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2425
2426 /* SQ_STACK_RESOURCE_MGMT_2 */
2427 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2428 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2429 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2430
2431 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2432
2433 if (rctx->chip_class >= R700) {
2434 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2435 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2436 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2437 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2438 } else {
2439 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2440 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2441 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2442 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2443 }
2444 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2445 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2446 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2447 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2448 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2449 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2450 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2451 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2452 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2453 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2454
2455 /* to avoid GPU doing any preloading of constant from random address */
2456 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2457 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2458 r600_store_value(cb, 0);
2459 r600_store_value(cb, 0);
2460 r600_store_value(cb, 0);
2461 r600_store_value(cb, 0);
2462 r600_store_value(cb, 0);
2463 r600_store_value(cb, 0);
2464 r600_store_value(cb, 0);
2465 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2466 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2467 r600_store_value(cb, 0);
2468 r600_store_value(cb, 0);
2469 r600_store_value(cb, 0);
2470 r600_store_value(cb, 0);
2471 r600_store_value(cb, 0);
2472 r600_store_value(cb, 0);
2473 r600_store_value(cb, 0);
2474
2475 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2476 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2477 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2478 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2479 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2480 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2481 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2482 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2483 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2484 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2485 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2486 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2487 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2488 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2489
2490 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2491 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2492 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2493
2494 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2495 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2496 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2497 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2498
2499 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2500
2501 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2502
2503 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2504 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2505 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2506
2507 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2508 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2509 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2510 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2511
2512 r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2513 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2514 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2515
2516 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2517 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2518
2519 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2520 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2521 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2522 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2523 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2524
2525 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2526 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2527 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2528
2529 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2530
2531 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2532 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2533
2534 if (rctx->chip_class >= R700) {
2535 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2536 }
2537
2538 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2539 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2540 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2541 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2542 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2543
2544 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2545 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2546 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2547
2548 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2549 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2550 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2551
2552 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2553 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2554 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2555
2556 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2557 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2558 r600_store_value(cb, 0);
2559 r600_store_value(cb, 0);
2560 r600_store_value(cb, 0);
2561 r600_store_value(cb, 0);
2562 r600_store_value(cb, 0);
2563 r600_store_value(cb, 0);
2564 r600_store_value(cb, 0);
2565 r600_store_value(cb, 0);
2566 r600_store_value(cb, 0);
2567 r600_store_value(cb, 0);
2568 r600_store_value(cb, 0);
2569 r600_store_value(cb, 0);
2570 r600_store_value(cb, 0);
2571 r600_store_value(cb, 0);
2572 r600_store_value(cb, 0);
2573 r600_store_value(cb, 0);
2574 r600_store_value(cb, 0);
2575 r600_store_value(cb, 0);
2576 r600_store_value(cb, 0);
2577 r600_store_value(cb, 0);
2578 r600_store_value(cb, 0);
2579 r600_store_value(cb, 0);
2580 r600_store_value(cb, 0);
2581 r600_store_value(cb, 0);
2582 r600_store_value(cb, 0);
2583 r600_store_value(cb, 0);
2584 r600_store_value(cb, 0);
2585 r600_store_value(cb, 0);
2586 r600_store_value(cb, 0);
2587 r600_store_value(cb, 0);
2588 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2589 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2590 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2591
2592 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2593 r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2594
2595 if (rctx->chip_class == R700 && rctx->screen->has_streamout)
2596 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2597 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2598 if (rctx->screen->has_streamout) {
2599 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2600 }
2601
2602 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2603 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2604 }
2605
2606 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2607 {
2608 struct r600_context *rctx = (struct r600_context *)ctx;
2609 struct r600_pipe_state *rstate = &shader->rstate;
2610 struct r600_shader *rshader = &shader->shader;
2611 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2612 int pos_index = -1, face_index = -1;
2613 unsigned tmp, sid, ufi = 0;
2614 int need_linear = 0;
2615 unsigned z_export = 0, stencil_export = 0;
2616
2617 rstate->nregs = 0;
2618
2619 for (i = 0; i < rshader->ninput; i++) {
2620 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2621 pos_index = i;
2622 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2623 face_index = i;
2624
2625 sid = rshader->input[i].spi_sid;
2626
2627 tmp = S_028644_SEMANTIC(sid);
2628
2629 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2630 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2631 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2632 rctx->rasterizer && rctx->rasterizer->flatshade))
2633 tmp |= S_028644_FLAT_SHADE(1);
2634
2635 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2636 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2637 tmp |= S_028644_PT_SPRITE_TEX(1);
2638 }
2639
2640 if (rshader->input[i].centroid)
2641 tmp |= S_028644_SEL_CENTROID(1);
2642
2643 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2644 need_linear = 1;
2645 tmp |= S_028644_SEL_LINEAR(1);
2646 }
2647
2648 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2649 tmp);
2650 }
2651
2652 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2653 for (i = 0; i < rshader->noutput; i++) {
2654 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2655 z_export = 1;
2656 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2657 stencil_export = 1;
2658 }
2659 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2660 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2661 if (rshader->uses_kill)
2662 db_shader_control |= S_02880C_KILL_ENABLE(1);
2663
2664 exports_ps = 0;
2665 for (i = 0; i < rshader->noutput; i++) {
2666 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2667 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2668 exports_ps |= 1;
2669 }
2670 }
2671 num_cout = rshader->nr_ps_color_exports;
2672 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2673 if (!exports_ps) {
2674 /* always at least export 1 component per pixel */
2675 exports_ps = 2;
2676 }
2677
2678 shader->nr_ps_color_outputs = num_cout;
2679
2680 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2681 S_0286CC_PERSP_GRADIENT_ENA(1)|
2682 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2683 spi_input_z = 0;
2684 if (pos_index != -1) {
2685 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2686 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2687 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2688 S_0286CC_BARYC_SAMPLE_CNTL(1));
2689 spi_input_z |= 1;
2690 }
2691
2692 spi_ps_in_control_1 = 0;
2693 if (face_index != -1) {
2694 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2695 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2696 }
2697
2698 /* HW bug in original R600 */
2699 if (rctx->family == CHIP_R600)
2700 ufi = 1;
2701
2702 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2703 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2704 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2705 r600_pipe_state_add_reg_bo(rstate,
2706 R_028840_SQ_PGM_START_PS,
2707 0, shader->bo, RADEON_USAGE_READ);
2708 r600_pipe_state_add_reg(rstate,
2709 R_028850_SQ_PGM_RESOURCES_PS,
2710 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2711 S_028850_STACK_SIZE(rshader->bc.nstack) |
2712 S_028850_UNCACHED_FIRST_INST(ufi));
2713 r600_pipe_state_add_reg(rstate,
2714 R_028854_SQ_PGM_EXPORTS_PS,
2715 exports_ps);
2716 /* only set some bits here, the other bits are set in the dsa state */
2717 shader->db_shader_control = db_shader_control;
2718 shader->ps_depth_export = z_export | stencil_export;
2719
2720 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2721 if (rctx->rasterizer)
2722 shader->flatshade = rctx->rasterizer->flatshade;
2723 }
2724
2725 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2726 {
2727 struct r600_context *rctx = (struct r600_context *)ctx;
2728 struct r600_pipe_state *rstate = &shader->rstate;
2729 struct r600_shader *rshader = &shader->shader;
2730 unsigned spi_vs_out_id[10] = {};
2731 unsigned i, tmp, nparams = 0;
2732
2733 /* clear previous register */
2734 rstate->nregs = 0;
2735
2736 for (i = 0; i < rshader->noutput; i++) {
2737 if (rshader->output[i].spi_sid) {
2738 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2739 spi_vs_out_id[nparams / 4] |= tmp;
2740 nparams++;
2741 }
2742 }
2743
2744 for (i = 0; i < 10; i++) {
2745 r600_pipe_state_add_reg(rstate,
2746 R_028614_SPI_VS_OUT_ID_0 + i * 4,
2747 spi_vs_out_id[i]);
2748 }
2749
2750 /* Certain attributes (position, psize, etc.) don't count as params.
2751 * VS is required to export at least one param and r600_shader_from_tgsi()
2752 * takes care of adding a dummy export.
2753 */
2754 if (nparams < 1)
2755 nparams = 1;
2756
2757 r600_pipe_state_add_reg(rstate,
2758 R_0286C4_SPI_VS_OUT_CONFIG,
2759 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2760 r600_pipe_state_add_reg(rstate,
2761 R_028868_SQ_PGM_RESOURCES_VS,
2762 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2763 S_028868_STACK_SIZE(rshader->bc.nstack));
2764 r600_pipe_state_add_reg_bo(rstate,
2765 R_028858_SQ_PGM_START_VS,
2766 0, shader->bo, RADEON_USAGE_READ);
2767
2768 shader->pa_cl_vs_out_cntl =
2769 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2770 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2771 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2772 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2773 }
2774
2775 void *r600_create_resolve_blend(struct r600_context *rctx)
2776 {
2777 struct pipe_blend_state blend;
2778 unsigned i;
2779
2780 memset(&blend, 0, sizeof(blend));
2781 blend.independent_blend_enable = true;
2782 for (i = 0; i < 2; i++) {
2783 blend.rt[i].colormask = 0xf;
2784 blend.rt[i].blend_enable = 1;
2785 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2786 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2787 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2788 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2789 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2790 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2791 }
2792 return r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2793 }
2794
2795 void *r700_create_resolve_blend(struct r600_context *rctx)
2796 {
2797 struct pipe_blend_state blend;
2798
2799 memset(&blend, 0, sizeof(blend));
2800 blend.independent_blend_enable = true;
2801 blend.rt[0].colormask = 0xf;
2802 return r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2803 }
2804
2805 void *r600_create_decompress_blend(struct r600_context *rctx)
2806 {
2807 struct pipe_blend_state blend;
2808
2809 memset(&blend, 0, sizeof(blend));
2810 blend.independent_blend_enable = true;
2811 blend.rt[0].colormask = 0xf;
2812 return r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2813 }
2814
2815 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2816 {
2817 struct pipe_depth_stencil_alpha_state dsa;
2818 boolean quirk = false;
2819
2820 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2821 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2822 quirk = true;
2823
2824 memset(&dsa, 0, sizeof(dsa));
2825
2826 if (quirk) {
2827 dsa.depth.enabled = 1;
2828 dsa.depth.func = PIPE_FUNC_LEQUAL;
2829 dsa.stencil[0].enabled = 1;
2830 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2831 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2832 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2833 dsa.stencil[0].writemask = 0xff;
2834 }
2835
2836 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2837 }
2838
2839 void r600_update_dual_export_state(struct r600_context * rctx)
2840 {
2841 bool dual_export = rctx->framebuffer.export_16bpc &&
2842 !rctx->ps_shader->current->ps_depth_export;
2843
2844 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2845 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2846
2847 if (db_shader_control != rctx->db_shader_control) {
2848 struct r600_pipe_state rstate;
2849
2850 rctx->db_shader_control = db_shader_control;
2851 rstate.nregs = 0;
2852 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2853 r600_context_pipe_state_set(rctx, &rstate);
2854 }
2855 }