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r600g: don't run with scissors.
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_double_list.h>
36 #include <util/u_pack_color.h>
37 #include <util/u_memory.h>
38 #include <util/u_inlines.h>
39 #include <util/u_upload_mgr.h>
40 #include <util/u_index_modify.h>
41 #include <pipebuffer/pb_buffer.h>
42 #include "r600.h"
43 #include "r600d.h"
44 #include "r600_resource.h"
45 #include "r600_shader.h"
46 #include "r600_pipe.h"
47 #include "r600_state_inlines.h"
48
49 static void r600_draw_common(struct r600_drawl *draw)
50 {
51 struct r600_pipe_context *rctx = (struct r600_pipe_context *)draw->ctx;
52 struct r600_pipe_state *rstate;
53 struct r600_resource *rbuffer;
54 unsigned i, j, offset, prim;
55 u32 vgt_dma_index_type, vgt_draw_initiator, mask;
56 struct pipe_vertex_buffer *vertex_buffer;
57 struct r600_draw rdraw;
58 struct r600_pipe_state vgt;
59
60 switch (draw->index_size) {
61 case 2:
62 vgt_draw_initiator = 0;
63 vgt_dma_index_type = 0;
64 break;
65 case 4:
66 vgt_draw_initiator = 0;
67 vgt_dma_index_type = 1;
68 break;
69 case 0:
70 vgt_draw_initiator = 2;
71 vgt_dma_index_type = 0;
72 break;
73 default:
74 R600_ERR("unsupported index size %d\n", draw->index_size);
75 return;
76 }
77 if (r600_conv_pipe_prim(draw->mode, &prim))
78 return;
79
80
81 /* rebuild vertex shader if input format changed */
82 if (r600_pipe_shader_update(&rctx->context, rctx->vs_shader))
83 return;
84 if (r600_pipe_shader_update(&rctx->context, rctx->ps_shader))
85 return;
86
87 for (i = 0 ; i < rctx->vertex_elements->count; i++) {
88 uint32_t word2, format;
89
90 rstate = &rctx->vs_resource[i];
91 rstate->id = R600_PIPE_STATE_RESOURCE;
92 rstate->nregs = 0;
93
94 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
95 vertex_buffer = &rctx->vertex_buffer[j];
96 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
97 offset = rctx->vertex_elements->elements[i].src_offset +
98 vertex_buffer->buffer_offset +
99 r600_bo_offset(rbuffer->bo);
100
101 format = r600_translate_vertex_data_type(rctx->vertex_elements->elements[i].src_format);
102
103 word2 = format | S_038008_STRIDE(vertex_buffer->stride);
104
105 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
106 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
107 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2, word2, 0xFFFFFFFF, NULL);
108 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3, 0x00000000, 0xFFFFFFFF, NULL);
109 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
110 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
111 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6, 0xC0000000, 0xFFFFFFFF, NULL);
112 r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, i);
113 }
114
115 mask = 0;
116 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
117 mask |= (0xF << (i * 4));
118 }
119
120 vgt.id = R600_PIPE_STATE_VGT;
121 vgt.nregs = 0;
122 r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
123 r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw->index_bias, 0xFFFFFFFF, NULL);
124 r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw->max_index, 0xFFFFFFFF, NULL);
125 r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw->min_index, 0xFFFFFFFF, NULL);
126 r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
127 r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
128 r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
129 /* build late state */
130 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
131 float offset_units = rctx->rasterizer->offset_units;
132 unsigned offset_db_fmt_cntl = 0, depth;
133
134 switch (rctx->framebuffer.zsbuf->texture->format) {
135 case PIPE_FORMAT_Z24X8_UNORM:
136 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
137 depth = -24;
138 offset_units *= 2.0f;
139 break;
140 case PIPE_FORMAT_Z32_FLOAT:
141 depth = -23;
142 offset_units *= 1.0f;
143 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
144 break;
145 case PIPE_FORMAT_Z16_UNORM:
146 depth = -16;
147 offset_units *= 4.0f;
148 break;
149 default:
150 return;
151 }
152 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
153 r600_pipe_state_add_reg(&vgt,
154 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
155 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
156 r600_pipe_state_add_reg(&vgt,
157 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
158 fui(offset_units), 0xFFFFFFFF, NULL);
159 r600_pipe_state_add_reg(&vgt,
160 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
161 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
162 r600_pipe_state_add_reg(&vgt,
163 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
164 fui(offset_units), 0xFFFFFFFF, NULL);
165 r600_pipe_state_add_reg(&vgt,
166 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
167 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
168 }
169 r600_context_pipe_state_set(&rctx->ctx, &vgt);
170
171 rdraw.vgt_num_indices = draw->count;
172 rdraw.vgt_num_instances = 1;
173 rdraw.vgt_index_type = vgt_dma_index_type;
174 rdraw.vgt_draw_initiator = vgt_draw_initiator;
175 rdraw.indices = NULL;
176 if (draw->index_buffer) {
177 rbuffer = (struct r600_resource*)draw->index_buffer;
178 rdraw.indices = rbuffer->bo;
179 rdraw.indices_bo_offset = draw->index_buffer_offset;
180 }
181 r600_context_draw(&rctx->ctx, &rdraw);
182 }
183
184 void r600_translate_index_buffer(struct r600_pipe_context *r600,
185 struct pipe_resource **index_buffer,
186 unsigned *index_size,
187 unsigned *start, unsigned count)
188 {
189 switch (*index_size) {
190 case 1:
191 util_shorten_ubyte_elts(&r600->context, index_buffer, 0, *start, count);
192 *index_size = 2;
193 *start = 0;
194 break;
195
196 case 2:
197 if (*start % 2 != 0) {
198 util_rebuild_ushort_elts(&r600->context, index_buffer, 0, *start, count);
199 *start = 0;
200 }
201 break;
202
203 case 4:
204 break;
205 }
206 }
207
208 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
209 {
210 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
211 struct r600_drawl draw;
212
213 if (rctx->any_user_vbs) {
214 r600_upload_user_buffers(rctx);
215 rctx->any_user_vbs = FALSE;
216 }
217
218 memset(&draw, 0, sizeof(struct r600_drawl));
219 draw.ctx = ctx;
220 draw.mode = info->mode;
221 draw.start = info->start;
222 draw.count = info->count;
223 if (info->indexed && rctx->index_buffer.buffer) {
224 draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
225 draw.min_index = info->min_index;
226 draw.max_index = info->max_index;
227 draw.index_bias = info->index_bias;
228
229 r600_translate_index_buffer(rctx, &rctx->index_buffer.buffer,
230 &rctx->index_buffer.index_size,
231 &draw.start,
232 info->count);
233
234 draw.index_size = rctx->index_buffer.index_size;
235 pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
236 draw.index_buffer_offset = draw.start * draw.index_size;
237 draw.start = 0;
238 r600_upload_index_buffer(rctx, &draw);
239 } else {
240 draw.index_size = 0;
241 draw.index_buffer = NULL;
242 draw.min_index = info->min_index;
243 draw.max_index = info->max_index;
244 draw.index_bias = info->start;
245 }
246 r600_draw_common(&draw);
247
248 pipe_resource_reference(&draw.index_buffer, NULL);
249 }
250
251 static void r600_set_blend_color(struct pipe_context *ctx,
252 const struct pipe_blend_color *state)
253 {
254 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
255 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
256
257 if (rstate == NULL)
258 return;
259
260 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
261 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
262 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
263 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
264 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
265 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
266 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
267 r600_context_pipe_state_set(&rctx->ctx, rstate);
268 }
269
270 static void *r600_create_blend_state(struct pipe_context *ctx,
271 const struct pipe_blend_state *state)
272 {
273 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
274 struct r600_pipe_state *rstate;
275 u32 color_control, target_mask;
276
277 if (blend == NULL) {
278 return NULL;
279 }
280 rstate = &blend->rstate;
281
282 rstate->id = R600_PIPE_STATE_BLEND;
283
284 target_mask = 0;
285 color_control = S_028808_PER_MRT_BLEND(1);
286 if (state->logicop_enable) {
287 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
288 } else {
289 color_control |= (0xcc << 16);
290 }
291 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
292 if (state->independent_blend_enable) {
293 for (int i = 0; i < 8; i++) {
294 if (state->rt[i].blend_enable) {
295 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
296 }
297 target_mask |= (state->rt[i].colormask << (4 * i));
298 }
299 } else {
300 for (int i = 0; i < 8; i++) {
301 if (state->rt[0].blend_enable) {
302 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
303 }
304 target_mask |= (state->rt[0].colormask << (4 * i));
305 }
306 }
307 blend->cb_target_mask = target_mask;
308 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
309 color_control, 0xFFFFFFFF, NULL);
310
311 for (int i = 0; i < 8; i++) {
312 unsigned eqRGB = state->rt[i].rgb_func;
313 unsigned srcRGB = state->rt[i].rgb_src_factor;
314 unsigned dstRGB = state->rt[i].rgb_dst_factor;
315
316 unsigned eqA = state->rt[i].alpha_func;
317 unsigned srcA = state->rt[i].alpha_src_factor;
318 unsigned dstA = state->rt[i].alpha_dst_factor;
319 uint32_t bc = 0;
320
321 if (!state->rt[i].blend_enable)
322 continue;
323
324 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
325 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
326 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
327
328 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
329 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
330 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
331 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
332 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
333 }
334
335 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
336 if (i == 0) {
337 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
338 }
339 }
340 return rstate;
341 }
342
343 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
344 {
345 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
346 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
347 struct r600_pipe_state *rstate;
348
349 if (state == NULL)
350 return;
351 rstate = &blend->rstate;
352 rctx->states[rstate->id] = rstate;
353 rctx->cb_target_mask = blend->cb_target_mask;
354 r600_context_pipe_state_set(&rctx->ctx, rstate);
355 }
356
357 static void *r600_create_dsa_state(struct pipe_context *ctx,
358 const struct pipe_depth_stencil_alpha_state *state)
359 {
360 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
361 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
362 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
363
364 if (rstate == NULL) {
365 return NULL;
366 }
367
368 rstate->id = R600_PIPE_STATE_DSA;
369 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
370 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
371 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
372 * be set if shader use texkill instruction
373 */
374 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
375 stencil_ref_mask = 0;
376 stencil_ref_mask_bf = 0;
377 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
378 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
379 S_028800_ZFUNC(state->depth.func);
380
381 /* stencil */
382 if (state->stencil[0].enabled) {
383 db_depth_control |= S_028800_STENCIL_ENABLE(1);
384 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
385 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
386 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
387 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
388
389
390 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
391 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
392 if (state->stencil[1].enabled) {
393 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
394 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
395 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
396 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
397 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
398 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
399 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
400 }
401 }
402
403 /* alpha */
404 alpha_test_control = 0;
405 alpha_ref = 0;
406 if (state->alpha.enabled) {
407 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
408 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
409 alpha_ref = fui(state->alpha.ref_value);
410 }
411
412 /* misc */
413 db_render_control = 0;
414 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
415 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
416 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
417 /* TODO db_render_override depends on query */
418 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
419 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
420 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
421 r600_pipe_state_add_reg(rstate,
422 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
423 0xFFFFFFFF & C_028430_STENCILREF, NULL);
424 r600_pipe_state_add_reg(rstate,
425 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
426 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
427 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
428 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
429 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
430 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
431 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
432 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
433 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
434 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
435 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
436 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
437 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
438
439 return rstate;
440 }
441
442 static void *r600_create_rs_state(struct pipe_context *ctx,
443 const struct pipe_rasterizer_state *state)
444 {
445 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
446 struct r600_pipe_state *rstate;
447 unsigned tmp;
448 unsigned prov_vtx = 1, polygon_dual_mode;
449
450 if (rs == NULL) {
451 return NULL;
452 }
453
454 rstate = &rs->rstate;
455 rs->flatshade = state->flatshade;
456 rs->sprite_coord_enable = state->sprite_coord_enable;
457
458 /* offset */
459 rs->offset_units = state->offset_units;
460 rs->offset_scale = state->offset_scale * 12.0f;
461
462 rstate->id = R600_PIPE_STATE_RASTERIZER;
463 if (state->flatshade_first)
464 prov_vtx = 0;
465 tmp = 0x00000001;
466 if (state->sprite_coord_enable) {
467 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
468 S_0286D4_PNT_SPRITE_OVRD_X(2) |
469 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
470 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
471 S_0286D4_PNT_SPRITE_OVRD_W(1);
472 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
473 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
474 }
475 }
476 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
477
478 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
479 state->fill_back != PIPE_POLYGON_MODE_FILL);
480 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
481 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
482 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
483 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
484 S_028814_FACE(!state->front_ccw) |
485 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
486 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
487 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
488 S_028814_POLY_MODE(polygon_dual_mode) |
489 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
490 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
491 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
492 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
493 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
494 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
495 /* point size 12.4 fixed point */
496 tmp = (unsigned)(state->point_size * 8.0);
497 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
498 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
499 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, 0x00000008, 0xFFFFFFFF, NULL);
500 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
501 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
502 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
503 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
504 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
505 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
506 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
507 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
508 return rstate;
509 }
510
511 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
512 {
513 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
514 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
515
516 if (state == NULL)
517 return;
518
519 rctx->flatshade = rs->flatshade;
520 rctx->sprite_coord_enable = rs->sprite_coord_enable;
521 rctx->rasterizer = rs;
522
523 rctx->states[rs->rstate.id] = &rs->rstate;
524 r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
525 }
526
527 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
528 {
529 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
530 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
531
532 if (rctx->rasterizer == rs) {
533 rctx->rasterizer = NULL;
534 }
535 if (rctx->states[rs->rstate.id] == &rs->rstate) {
536 rctx->states[rs->rstate.id] = NULL;
537 }
538 free(rs);
539 }
540
541 static void *r600_create_sampler_state(struct pipe_context *ctx,
542 const struct pipe_sampler_state *state)
543 {
544 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
545 union util_color uc;
546
547 if (rstate == NULL) {
548 return NULL;
549 }
550
551 rstate->id = R600_PIPE_STATE_SAMPLER;
552 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
553 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
554 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
555 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
556 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
557 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
558 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
559 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
560 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
561 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
562 /* FIXME LOD it depends on texture base level ... */
563 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
564 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
565 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
566 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
567 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
568 if (uc.ui) {
569 r600_pipe_state_add_reg(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
570 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
571 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
572 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
573 }
574 return rstate;
575 }
576
577 static void *r600_create_vertex_elements(struct pipe_context *ctx,
578 unsigned count,
579 const struct pipe_vertex_element *elements)
580 {
581 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
582
583 assert(count < 32);
584 v->count = count;
585 v->refcount = 1;
586 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
587 return v;
588 }
589
590 static void r600_sampler_view_destroy(struct pipe_context *ctx,
591 struct pipe_sampler_view *state)
592 {
593 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
594
595 pipe_resource_reference(&state->texture, NULL);
596 FREE(resource);
597 }
598
599 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
600 struct pipe_resource *texture,
601 const struct pipe_sampler_view *state)
602 {
603 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
604 struct r600_pipe_state *rstate;
605 const struct util_format_description *desc;
606 struct r600_resource_texture *tmp;
607 struct r600_resource *rbuffer;
608 unsigned format;
609 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
610 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
611 struct r600_bo *bo[2];
612
613 if (resource == NULL)
614 return NULL;
615 rstate = &resource->state;
616
617 /* initialize base object */
618 resource->base = *state;
619 resource->base.texture = NULL;
620 pipe_reference(NULL, &texture->reference);
621 resource->base.texture = texture;
622 resource->base.reference.count = 1;
623 resource->base.context = ctx;
624
625 swizzle[0] = state->swizzle_r;
626 swizzle[1] = state->swizzle_g;
627 swizzle[2] = state->swizzle_b;
628 swizzle[3] = state->swizzle_a;
629 format = r600_translate_texformat(state->format,
630 swizzle,
631 &word4, &yuv_format);
632 if (format == ~0) {
633 format = 0;
634 }
635 desc = util_format_description(state->format);
636 if (desc == NULL) {
637 R600_ERR("unknow format %d\n", state->format);
638 }
639 tmp = (struct r600_resource_texture*)texture;
640 rbuffer = &tmp->resource;
641 bo[0] = rbuffer->bo;
642 bo[1] = rbuffer->bo;
643 /* FIXME depth texture decompression */
644 if (tmp->depth) {
645 r600_texture_depth_flush(ctx, texture);
646 tmp = (struct r600_resource_texture*)texture;
647 rbuffer = &tmp->flushed_depth_texture->resource;
648 bo[0] = rbuffer->bo;
649 bo[1] = rbuffer->bo;
650 }
651 pitch = align(tmp->pitch[0] / tmp->bpt, 8);
652
653 /* FIXME properly handle first level != 0 */
654 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
655 S_038000_DIM(r600_tex_dim(texture->target)) |
656 S_038000_TILE_MODE(array_mode) |
657 S_038000_TILE_TYPE(tile_type) |
658 S_038000_PITCH((pitch / 8) - 1) |
659 S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
660 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
661 S_038004_TEX_HEIGHT(texture->height0 - 1) |
662 S_038004_TEX_DEPTH(texture->depth0 - 1) |
663 S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
664 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
665 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
666 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
667 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
668 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
669 word4 | S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
670 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
671 S_038010_REQUEST_SIZE(1) |
672 S_038010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
673 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
674 S_038014_LAST_LEVEL(state->last_level) |
675 S_038014_BASE_ARRAY(0) |
676 S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL);
677 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
678 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
679
680 return &resource->base;
681 }
682
683 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
684 struct pipe_sampler_view **views)
685 {
686 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
687 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
688
689 for (int i = 0; i < count; i++) {
690 if (resource[i]) {
691 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i + PIPE_MAX_ATTRIBS);
692 }
693 }
694 }
695
696 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
697 struct pipe_sampler_view **views)
698 {
699 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
700 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
701
702 for (int i = 0; i < count; i++) {
703 if (resource[i]) {
704 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
705 }
706 }
707 }
708
709 static void r600_bind_state(struct pipe_context *ctx, void *state)
710 {
711 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
712 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
713
714 if (state == NULL)
715 return;
716 rctx->states[rstate->id] = rstate;
717 r600_context_pipe_state_set(&rctx->ctx, rstate);
718 }
719
720 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
721 {
722 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
723 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
724
725 for (int i = 0; i < count; i++) {
726 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
727 }
728 }
729
730 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
731 {
732 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
733 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
734
735 for (int i = 0; i < count; i++) {
736 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
737 }
738 }
739
740 static void r600_delete_state(struct pipe_context *ctx, void *state)
741 {
742 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
743 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
744
745 if (rctx->states[rstate->id] == rstate) {
746 rctx->states[rstate->id] = NULL;
747 }
748 for (int i = 0; i < rstate->nregs; i++) {
749 r600_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
750 }
751 free(rstate);
752 }
753
754 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
755 {
756 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
757
758 if (v == NULL)
759 return;
760 if (--v->refcount)
761 return;
762 free(v);
763 }
764
765 static void r600_set_clip_state(struct pipe_context *ctx,
766 const struct pipe_clip_state *state)
767 {
768 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
769 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
770
771 if (rstate == NULL)
772 return;
773
774 rctx->clip = *state;
775 rstate->id = R600_PIPE_STATE_CLIP;
776 for (int i = 0; i < state->nr; i++) {
777 r600_pipe_state_add_reg(rstate,
778 R_028E20_PA_CL_UCP0_X + i * 4,
779 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
780 r600_pipe_state_add_reg(rstate,
781 R_028E24_PA_CL_UCP0_Y + i * 4,
782 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
783 r600_pipe_state_add_reg(rstate,
784 R_028E28_PA_CL_UCP0_Z + i * 4,
785 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
786 r600_pipe_state_add_reg(rstate,
787 R_028E2C_PA_CL_UCP0_W + i * 4,
788 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
789 }
790 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
791 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
792 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
793 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
794
795 free(rctx->states[R600_PIPE_STATE_CLIP]);
796 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
797 r600_context_pipe_state_set(&rctx->ctx, rstate);
798 }
799
800 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
801 {
802 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
803 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
804
805 r600_delete_vertex_element(ctx, rctx->vertex_elements);
806 rctx->vertex_elements = v;
807 if (v) {
808 v->refcount++;
809 // rctx->vs_rebuild = TRUE;
810 }
811 }
812
813 static void r600_set_polygon_stipple(struct pipe_context *ctx,
814 const struct pipe_poly_stipple *state)
815 {
816 }
817
818 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
819 {
820 }
821
822 static void r600_set_scissor_state(struct pipe_context *ctx,
823 const struct pipe_scissor_state *state)
824 {
825 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
826 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
827 u32 tl, br;
828
829 if (rstate == NULL)
830 return;
831
832 rstate->id = R600_PIPE_STATE_SCISSOR;
833 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
834 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
835 r600_pipe_state_add_reg(rstate,
836 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
837 0xFFFFFFFF, NULL);
838 r600_pipe_state_add_reg(rstate,
839 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
840 0xFFFFFFFF, NULL);
841 r600_pipe_state_add_reg(rstate,
842 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
843 0xFFFFFFFF, NULL);
844 r600_pipe_state_add_reg(rstate,
845 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
846 0xFFFFFFFF, NULL);
847 r600_pipe_state_add_reg(rstate,
848 R_028210_PA_SC_CLIPRECT_0_TL, tl,
849 0xFFFFFFFF, NULL);
850 r600_pipe_state_add_reg(rstate,
851 R_028214_PA_SC_CLIPRECT_0_BR, br,
852 0xFFFFFFFF, NULL);
853 r600_pipe_state_add_reg(rstate,
854 R_028218_PA_SC_CLIPRECT_1_TL, tl,
855 0xFFFFFFFF, NULL);
856 r600_pipe_state_add_reg(rstate,
857 R_02821C_PA_SC_CLIPRECT_1_BR, br,
858 0xFFFFFFFF, NULL);
859 r600_pipe_state_add_reg(rstate,
860 R_028220_PA_SC_CLIPRECT_2_TL, tl,
861 0xFFFFFFFF, NULL);
862 r600_pipe_state_add_reg(rstate,
863 R_028224_PA_SC_CLIPRECT_2_BR, br,
864 0xFFFFFFFF, NULL);
865 r600_pipe_state_add_reg(rstate,
866 R_028228_PA_SC_CLIPRECT_3_TL, tl,
867 0xFFFFFFFF, NULL);
868 r600_pipe_state_add_reg(rstate,
869 R_02822C_PA_SC_CLIPRECT_3_BR, br,
870 0xFFFFFFFF, NULL);
871 r600_pipe_state_add_reg(rstate,
872 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
873 0xFFFFFFFF, NULL);
874 r600_pipe_state_add_reg(rstate,
875 R_02820C_PA_SC_CLIPRECT_RULE, 0x0000FFFF,
876 0xFFFFFFFF, NULL);
877 if (rctx->family >= CHIP_RV770) {
878 r600_pipe_state_add_reg(rstate,
879 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
880 0xFFFFFFFF, NULL);
881 }
882
883 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
884 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
885 r600_context_pipe_state_set(&rctx->ctx, rstate);
886 }
887
888 static void r600_set_stencil_ref(struct pipe_context *ctx,
889 const struct pipe_stencil_ref *state)
890 {
891 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
892 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
893 u32 tmp;
894
895 if (rstate == NULL)
896 return;
897
898 rctx->stencil_ref = *state;
899 rstate->id = R600_PIPE_STATE_STENCIL_REF;
900 tmp = S_028430_STENCILREF(state->ref_value[0]);
901 r600_pipe_state_add_reg(rstate,
902 R_028430_DB_STENCILREFMASK, tmp,
903 ~C_028430_STENCILREF, NULL);
904 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
905 r600_pipe_state_add_reg(rstate,
906 R_028434_DB_STENCILREFMASK_BF, tmp,
907 ~C_028434_STENCILREF_BF, NULL);
908
909 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
910 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
911 r600_context_pipe_state_set(&rctx->ctx, rstate);
912 }
913
914 static void r600_set_viewport_state(struct pipe_context *ctx,
915 const struct pipe_viewport_state *state)
916 {
917 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
918 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
919
920 if (rstate == NULL)
921 return;
922
923 rctx->viewport = *state;
924 rstate->id = R600_PIPE_STATE_VIEWPORT;
925 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
926 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
927 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
928 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
929 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
930 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
931 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
932 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
933 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
934
935 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
936 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
937 r600_context_pipe_state_set(&rctx->ctx, rstate);
938 }
939
940 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
941 const struct pipe_framebuffer_state *state, int cb)
942 {
943 struct r600_resource_texture *rtex;
944 struct r600_resource *rbuffer;
945 unsigned level = state->cbufs[cb]->level;
946 unsigned pitch, slice;
947 unsigned color_info;
948 unsigned format, swap, ntype;
949 const struct util_format_description *desc;
950 struct r600_bo *bo[3];
951
952 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
953 rbuffer = &rtex->resource;
954 bo[0] = rbuffer->bo;
955 bo[1] = rbuffer->bo;
956 bo[2] = rbuffer->bo;
957
958 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
959 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
960 ntype = 0;
961 desc = util_format_description(rtex->resource.base.b.format);
962 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
963 ntype = V_0280A0_NUMBER_SRGB;
964
965 format = r600_translate_colorformat(rtex->resource.base.b.format);
966 swap = r600_translate_colorswap(rtex->resource.base.b.format);
967 color_info = S_0280A0_FORMAT(format) |
968 S_0280A0_COMP_SWAP(swap) |
969 S_0280A0_BLEND_CLAMP(1) |
970 S_0280A0_NUMBER_TYPE(ntype);
971 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
972 color_info |= S_0280A0_SOURCE_FORMAT(1);
973
974 r600_pipe_state_add_reg(rstate,
975 R_028040_CB_COLOR0_BASE + cb * 4,
976 (state->cbufs[cb]->offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
977 r600_pipe_state_add_reg(rstate,
978 R_0280A0_CB_COLOR0_INFO + cb * 4,
979 color_info, 0xFFFFFFFF, bo[0]);
980 r600_pipe_state_add_reg(rstate,
981 R_028060_CB_COLOR0_SIZE + cb * 4,
982 S_028060_PITCH_TILE_MAX(pitch) |
983 S_028060_SLICE_TILE_MAX(slice),
984 0xFFFFFFFF, NULL);
985 r600_pipe_state_add_reg(rstate,
986 R_028080_CB_COLOR0_VIEW + cb * 4,
987 0x00000000, 0xFFFFFFFF, NULL);
988 r600_pipe_state_add_reg(rstate,
989 R_0280E0_CB_COLOR0_FRAG + cb * 4,
990 r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]);
991 r600_pipe_state_add_reg(rstate,
992 R_0280C0_CB_COLOR0_TILE + cb * 4,
993 r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]);
994 r600_pipe_state_add_reg(rstate,
995 R_028100_CB_COLOR0_MASK + cb * 4,
996 0x00000000, 0xFFFFFFFF, NULL);
997 }
998
999 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1000 const struct pipe_framebuffer_state *state)
1001 {
1002 struct r600_resource_texture *rtex;
1003 struct r600_resource *rbuffer;
1004 unsigned level;
1005 unsigned pitch, slice, format;
1006
1007 if (state->zsbuf == NULL)
1008 return;
1009
1010 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1011 rtex->tiled = 1;
1012 rtex->array_mode = 2;
1013 rtex->tile_type = 1;
1014 rtex->depth = 1;
1015 rbuffer = &rtex->resource;
1016
1017 level = state->zsbuf->level;
1018 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
1019 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
1020 format = r600_translate_dbformat(state->zsbuf->texture->format);
1021
1022 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
1023 (state->zsbuf->offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
1024 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1025 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1026 0xFFFFFFFF, NULL);
1027 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
1028 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
1029 S_028010_ARRAY_MODE(rtex->array_mode) | S_028010_FORMAT(format),
1030 0xFFFFFFFF, rbuffer->bo);
1031 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1032 (state->zsbuf->height / 8) - 1, 0xFFFFFFFF, NULL);
1033 }
1034
1035 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1036 const struct pipe_framebuffer_state *state)
1037 {
1038 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1039 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1040 u32 shader_mask, tl, br, shader_control, target_mask;
1041
1042 if (rstate == NULL)
1043 return;
1044
1045 /* unreference old buffer and reference new one */
1046 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1047 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
1048 pipe_surface_reference(&rctx->framebuffer.cbufs[i], NULL);
1049 }
1050 for (int i = 0; i < state->nr_cbufs; i++) {
1051 pipe_surface_reference(&rctx->framebuffer.cbufs[i], state->cbufs[i]);
1052 }
1053 pipe_surface_reference(&rctx->framebuffer.zsbuf, state->zsbuf);
1054 rctx->framebuffer = *state;
1055 rctx->pframebuffer = &rctx->framebuffer;
1056
1057 /* build states */
1058 for (int i = 0; i < state->nr_cbufs; i++) {
1059 r600_cb(rctx, rstate, state, i);
1060 }
1061 if (state->zsbuf) {
1062 r600_db(rctx, rstate, state);
1063 }
1064
1065 target_mask = 0x00000000;
1066 target_mask = 0xFFFFFFFF;
1067 shader_mask = 0;
1068 shader_control = 0;
1069 for (int i = 0; i < state->nr_cbufs; i++) {
1070 target_mask ^= 0xf << (i * 4);
1071 shader_mask |= 0xf << (i * 4);
1072 shader_control |= 1 << i;
1073 }
1074 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1075 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1076
1077 r600_pipe_state_add_reg(rstate,
1078 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1079 0xFFFFFFFF, NULL);
1080 r600_pipe_state_add_reg(rstate,
1081 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1082 0xFFFFFFFF, NULL);
1083 r600_pipe_state_add_reg(rstate,
1084 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1085 0xFFFFFFFF, NULL);
1086 r600_pipe_state_add_reg(rstate,
1087 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1088 0xFFFFFFFF, NULL);
1089 r600_pipe_state_add_reg(rstate,
1090 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1091 0xFFFFFFFF, NULL);
1092 r600_pipe_state_add_reg(rstate,
1093 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1094 0xFFFFFFFF, NULL);
1095 r600_pipe_state_add_reg(rstate,
1096 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1097 0xFFFFFFFF, NULL);
1098 r600_pipe_state_add_reg(rstate,
1099 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1100 0xFFFFFFFF, NULL);
1101 r600_pipe_state_add_reg(rstate,
1102 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1103 0xFFFFFFFF, NULL);
1104 r600_pipe_state_add_reg(rstate,
1105 R_028214_PA_SC_CLIPRECT_0_BR, br,
1106 0xFFFFFFFF, NULL);
1107 r600_pipe_state_add_reg(rstate,
1108 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1109 0xFFFFFFFF, NULL);
1110 r600_pipe_state_add_reg(rstate,
1111 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1112 0xFFFFFFFF, NULL);
1113 r600_pipe_state_add_reg(rstate,
1114 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1115 0xFFFFFFFF, NULL);
1116 r600_pipe_state_add_reg(rstate,
1117 R_028224_PA_SC_CLIPRECT_2_BR, br,
1118 0xFFFFFFFF, NULL);
1119 r600_pipe_state_add_reg(rstate,
1120 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1121 0xFFFFFFFF, NULL);
1122 r600_pipe_state_add_reg(rstate,
1123 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1124 0xFFFFFFFF, NULL);
1125 r600_pipe_state_add_reg(rstate,
1126 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1127 0xFFFFFFFF, NULL);
1128 r600_pipe_state_add_reg(rstate,
1129 R_02820C_PA_SC_CLIPRECT_RULE, 0x0000FFFF,
1130 0xFFFFFFFF, NULL);
1131 if (rctx->family >= CHIP_RV770) {
1132 r600_pipe_state_add_reg(rstate,
1133 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1134 0xFFFFFFFF, NULL);
1135 }
1136
1137 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1138 shader_control, 0xFFFFFFFF, NULL);
1139 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1140 0x00000000, target_mask, NULL);
1141 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1142 shader_mask, 0xFFFFFFFF, NULL);
1143 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1144 0x00000000, 0xFFFFFFFF, NULL);
1145 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1146 0x00000000, 0xFFFFFFFF, NULL);
1147 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1148 0x00000000, 0xFFFFFFFF, NULL);
1149 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1150 0x01000000, 0xFFFFFFFF, NULL);
1151 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1152 0x00000000, 0xFFFFFFFF, NULL);
1153 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1154 0x000000FF, 0xFFFFFFFF, NULL);
1155 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1156 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1157 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1158 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1159
1160 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1161 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1162 r600_context_pipe_state_set(&rctx->ctx, rstate);
1163 }
1164
1165 static void r600_set_index_buffer(struct pipe_context *ctx,
1166 const struct pipe_index_buffer *ib)
1167 {
1168 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1169
1170 if (ib) {
1171 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
1172 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
1173 } else {
1174 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
1175 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
1176 }
1177
1178 /* TODO make this more like a state */
1179 }
1180
1181 static void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
1182 const struct pipe_vertex_buffer *buffers)
1183 {
1184 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1185
1186 for (int i = 0; i < rctx->nvertex_buffer; i++) {
1187 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
1188 }
1189 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
1190 for (int i = 0; i < count; i++) {
1191 rctx->vertex_buffer[i].buffer = NULL;
1192 if (r600_buffer_is_user_buffer(buffers[i].buffer))
1193 rctx->any_user_vbs = TRUE;
1194 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
1195 }
1196 rctx->nvertex_buffer = count;
1197 }
1198
1199 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
1200 struct pipe_resource *buffer)
1201 {
1202 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1203 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
1204
1205 switch (shader) {
1206 case PIPE_SHADER_VERTEX:
1207 rctx->vs_const_buffer.nregs = 0;
1208 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1209 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1210 ALIGN_DIVUP(buffer->width0 >> 4, 16),
1211 0xFFFFFFFF, NULL);
1212 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1213 R_028980_ALU_CONST_CACHE_VS_0,
1214 r600_bo_offset(rbuffer->bo) >> 8, 0xFFFFFFFF, rbuffer->bo);
1215 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
1216 break;
1217 case PIPE_SHADER_FRAGMENT:
1218 rctx->ps_const_buffer.nregs = 0;
1219 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1220 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1221 ALIGN_DIVUP(buffer->width0 >> 4, 16),
1222 0xFFFFFFFF, NULL);
1223 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1224 R_028940_ALU_CONST_CACHE_PS_0,
1225 r600_bo_offset(rbuffer->bo) >> 8, 0xFFFFFFFF, rbuffer->bo);
1226 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
1227 break;
1228 default:
1229 R600_ERR("unsupported %d\n", shader);
1230 return;
1231 }
1232 }
1233
1234 static void *r600_create_shader_state(struct pipe_context *ctx,
1235 const struct pipe_shader_state *state)
1236 {
1237 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
1238 int r;
1239
1240 r = r600_pipe_shader_create(ctx, shader, state->tokens);
1241 if (r) {
1242 return NULL;
1243 }
1244 return shader;
1245 }
1246
1247 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
1248 {
1249 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1250
1251 /* TODO delete old shader */
1252 rctx->ps_shader = (struct r600_pipe_shader *)state;
1253 }
1254
1255 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
1256 {
1257 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1258
1259 /* TODO delete old shader */
1260 rctx->vs_shader = (struct r600_pipe_shader *)state;
1261 }
1262
1263 static void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
1264 {
1265 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1266 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1267
1268 if (rctx->ps_shader == shader) {
1269 rctx->ps_shader = NULL;
1270 }
1271 /* TODO proper delete */
1272 free(shader);
1273 }
1274
1275 static void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
1276 {
1277 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1278 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1279
1280 if (rctx->vs_shader == shader) {
1281 rctx->vs_shader = NULL;
1282 }
1283 /* TODO proper delete */
1284 free(shader);
1285 }
1286
1287 void r600_init_state_functions(struct r600_pipe_context *rctx)
1288 {
1289 rctx->context.create_blend_state = r600_create_blend_state;
1290 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1291 rctx->context.create_fs_state = r600_create_shader_state;
1292 rctx->context.create_rasterizer_state = r600_create_rs_state;
1293 rctx->context.create_sampler_state = r600_create_sampler_state;
1294 rctx->context.create_sampler_view = r600_create_sampler_view;
1295 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1296 rctx->context.create_vs_state = r600_create_shader_state;
1297 rctx->context.bind_blend_state = r600_bind_blend_state;
1298 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
1299 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
1300 rctx->context.bind_fs_state = r600_bind_ps_shader;
1301 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1302 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1303 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
1304 rctx->context.bind_vs_state = r600_bind_vs_shader;
1305 rctx->context.delete_blend_state = r600_delete_state;
1306 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1307 rctx->context.delete_fs_state = r600_delete_ps_shader;
1308 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1309 rctx->context.delete_sampler_state = r600_delete_state;
1310 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1311 rctx->context.delete_vs_state = r600_delete_vs_shader;
1312 rctx->context.set_blend_color = r600_set_blend_color;
1313 rctx->context.set_clip_state = r600_set_clip_state;
1314 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1315 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
1316 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1317 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1318 rctx->context.set_sample_mask = r600_set_sample_mask;
1319 rctx->context.set_scissor_state = r600_set_scissor_state;
1320 rctx->context.set_stencil_ref = r600_set_stencil_ref;
1321 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1322 rctx->context.set_index_buffer = r600_set_index_buffer;
1323 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
1324 rctx->context.set_viewport_state = r600_set_viewport_state;
1325 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1326 }
1327
1328 void r600_init_config(struct r600_pipe_context *rctx)
1329 {
1330 int ps_prio;
1331 int vs_prio;
1332 int gs_prio;
1333 int es_prio;
1334 int num_ps_gprs;
1335 int num_vs_gprs;
1336 int num_gs_gprs;
1337 int num_es_gprs;
1338 int num_temp_gprs;
1339 int num_ps_threads;
1340 int num_vs_threads;
1341 int num_gs_threads;
1342 int num_es_threads;
1343 int num_ps_stack_entries;
1344 int num_vs_stack_entries;
1345 int num_gs_stack_entries;
1346 int num_es_stack_entries;
1347 enum radeon_family family;
1348 struct r600_pipe_state *rstate = &rctx->config;
1349 u32 tmp;
1350
1351 family = r600_get_family(rctx->radeon);
1352 ps_prio = 0;
1353 vs_prio = 1;
1354 gs_prio = 2;
1355 es_prio = 3;
1356 switch (family) {
1357 case CHIP_R600:
1358 num_ps_gprs = 192;
1359 num_vs_gprs = 56;
1360 num_temp_gprs = 4;
1361 num_gs_gprs = 0;
1362 num_es_gprs = 0;
1363 num_ps_threads = 136;
1364 num_vs_threads = 48;
1365 num_gs_threads = 4;
1366 num_es_threads = 4;
1367 num_ps_stack_entries = 128;
1368 num_vs_stack_entries = 128;
1369 num_gs_stack_entries = 0;
1370 num_es_stack_entries = 0;
1371 break;
1372 case CHIP_RV630:
1373 case CHIP_RV635:
1374 num_ps_gprs = 84;
1375 num_vs_gprs = 36;
1376 num_temp_gprs = 4;
1377 num_gs_gprs = 0;
1378 num_es_gprs = 0;
1379 num_ps_threads = 144;
1380 num_vs_threads = 40;
1381 num_gs_threads = 4;
1382 num_es_threads = 4;
1383 num_ps_stack_entries = 40;
1384 num_vs_stack_entries = 40;
1385 num_gs_stack_entries = 32;
1386 num_es_stack_entries = 16;
1387 break;
1388 case CHIP_RV610:
1389 case CHIP_RV620:
1390 case CHIP_RS780:
1391 case CHIP_RS880:
1392 default:
1393 num_ps_gprs = 84;
1394 num_vs_gprs = 36;
1395 num_temp_gprs = 4;
1396 num_gs_gprs = 0;
1397 num_es_gprs = 0;
1398 num_ps_threads = 136;
1399 num_vs_threads = 48;
1400 num_gs_threads = 4;
1401 num_es_threads = 4;
1402 num_ps_stack_entries = 40;
1403 num_vs_stack_entries = 40;
1404 num_gs_stack_entries = 32;
1405 num_es_stack_entries = 16;
1406 break;
1407 case CHIP_RV670:
1408 num_ps_gprs = 144;
1409 num_vs_gprs = 40;
1410 num_temp_gprs = 4;
1411 num_gs_gprs = 0;
1412 num_es_gprs = 0;
1413 num_ps_threads = 136;
1414 num_vs_threads = 48;
1415 num_gs_threads = 4;
1416 num_es_threads = 4;
1417 num_ps_stack_entries = 40;
1418 num_vs_stack_entries = 40;
1419 num_gs_stack_entries = 32;
1420 num_es_stack_entries = 16;
1421 break;
1422 case CHIP_RV770:
1423 num_ps_gprs = 192;
1424 num_vs_gprs = 56;
1425 num_temp_gprs = 4;
1426 num_gs_gprs = 0;
1427 num_es_gprs = 0;
1428 num_ps_threads = 188;
1429 num_vs_threads = 60;
1430 num_gs_threads = 0;
1431 num_es_threads = 0;
1432 num_ps_stack_entries = 256;
1433 num_vs_stack_entries = 256;
1434 num_gs_stack_entries = 0;
1435 num_es_stack_entries = 0;
1436 break;
1437 case CHIP_RV730:
1438 case CHIP_RV740:
1439 num_ps_gprs = 84;
1440 num_vs_gprs = 36;
1441 num_temp_gprs = 4;
1442 num_gs_gprs = 0;
1443 num_es_gprs = 0;
1444 num_ps_threads = 188;
1445 num_vs_threads = 60;
1446 num_gs_threads = 0;
1447 num_es_threads = 0;
1448 num_ps_stack_entries = 128;
1449 num_vs_stack_entries = 128;
1450 num_gs_stack_entries = 0;
1451 num_es_stack_entries = 0;
1452 break;
1453 case CHIP_RV710:
1454 num_ps_gprs = 192;
1455 num_vs_gprs = 56;
1456 num_temp_gprs = 4;
1457 num_gs_gprs = 0;
1458 num_es_gprs = 0;
1459 num_ps_threads = 144;
1460 num_vs_threads = 48;
1461 num_gs_threads = 0;
1462 num_es_threads = 0;
1463 num_ps_stack_entries = 128;
1464 num_vs_stack_entries = 128;
1465 num_gs_stack_entries = 0;
1466 num_es_stack_entries = 0;
1467 break;
1468 }
1469
1470 rstate->id = R600_PIPE_STATE_CONFIG;
1471
1472 /* SQ_CONFIG */
1473 tmp = 0;
1474 switch (family) {
1475 case CHIP_RV610:
1476 case CHIP_RV620:
1477 case CHIP_RS780:
1478 case CHIP_RS880:
1479 case CHIP_RV710:
1480 break;
1481 default:
1482 tmp |= S_008C00_VC_ENABLE(1);
1483 break;
1484 }
1485 tmp |= S_008C00_DX9_CONSTS(0);
1486 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1487 tmp |= S_008C00_PS_PRIO(ps_prio);
1488 tmp |= S_008C00_VS_PRIO(vs_prio);
1489 tmp |= S_008C00_GS_PRIO(gs_prio);
1490 tmp |= S_008C00_ES_PRIO(es_prio);
1491 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1492
1493 /* SQ_GPR_RESOURCE_MGMT_1 */
1494 tmp = 0;
1495 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1496 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1497 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1498 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1499
1500 /* SQ_GPR_RESOURCE_MGMT_2 */
1501 tmp = 0;
1502 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1503 tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
1504 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1505
1506 /* SQ_THREAD_RESOURCE_MGMT */
1507 tmp = 0;
1508 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1509 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1510 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1511 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1512 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1513
1514 /* SQ_STACK_RESOURCE_MGMT_1 */
1515 tmp = 0;
1516 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1517 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1518 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1519
1520 /* SQ_STACK_RESOURCE_MGMT_2 */
1521 tmp = 0;
1522 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1523 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1524 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1525
1526 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1527 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1528
1529 if (family >= CHIP_RV770) {
1530 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1531 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
1532 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1533 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1534 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1535 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514000, 0xFFFFFFFF, NULL);
1536 } else {
1537 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1538 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
1539 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1540 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1541 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1542 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004010, 0xFFFFFFFF, NULL);
1543 }
1544 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1545 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1546 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1547 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1548 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1549 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1550 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1551 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1552 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1553 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1554 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1555 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1556 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1557 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
1558 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
1559 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1560 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1561 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1562 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1563 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1564 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1565 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
1566 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1567 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1568 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1569 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
1570
1571 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1572 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
1573 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
1574 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
1575 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
1576 r600_context_pipe_state_set(&rctx->ctx, rstate);
1577 }
1578
1579 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
1580 {
1581 struct pipe_depth_stencil_alpha_state dsa;
1582 struct r600_pipe_state *rstate;
1583 boolean quirk = false;
1584
1585 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
1586 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
1587 quirk = true;
1588
1589 memset(&dsa, 0, sizeof(dsa));
1590
1591 if (quirk) {
1592 dsa.depth.enabled = 1;
1593 dsa.depth.func = PIPE_FUNC_LEQUAL;
1594 dsa.stencil[0].enabled = 1;
1595 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
1596 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
1597 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
1598 dsa.stencil[0].writemask = 0xff;
1599 }
1600
1601 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1602 r600_pipe_state_add_reg(rstate,
1603 R_02880C_DB_SHADER_CONTROL,
1604 0x0,
1605 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1606 r600_pipe_state_add_reg(rstate,
1607 R_028D0C_DB_RENDER_CONTROL,
1608 S_028D0C_DEPTH_COPY_ENABLE(1) |
1609 S_028D0C_STENCIL_COPY_ENABLE(1) |
1610 S_028D0C_COPY_CENTROID(1),
1611 S_028D0C_DEPTH_COPY_ENABLE(1) |
1612 S_028D0C_STENCIL_COPY_ENABLE(1) |
1613 S_028D0C_COPY_CENTROID(1), NULL);
1614 return rstate;
1615 }