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r600g: add support for red-alpha render targets
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static uint32_t r600_translate_colorswap(enum pipe_format format)
145 {
146 switch (format) {
147 /* 8-bit buffers. */
148 case PIPE_FORMAT_A8_UNORM:
149 case PIPE_FORMAT_A8_SNORM:
150 case PIPE_FORMAT_A8_UINT:
151 case PIPE_FORMAT_A8_SINT:
152 case PIPE_FORMAT_A16_UNORM:
153 case PIPE_FORMAT_A16_SNORM:
154 case PIPE_FORMAT_A16_UINT:
155 case PIPE_FORMAT_A16_SINT:
156 case PIPE_FORMAT_A16_FLOAT:
157 case PIPE_FORMAT_A32_UINT:
158 case PIPE_FORMAT_A32_SINT:
159 case PIPE_FORMAT_A32_FLOAT:
160 case PIPE_FORMAT_R4A4_UNORM:
161 return V_0280A0_SWAP_ALT_REV;
162 case PIPE_FORMAT_I8_UNORM:
163 case PIPE_FORMAT_I8_SNORM:
164 case PIPE_FORMAT_I8_UINT:
165 case PIPE_FORMAT_I8_SINT:
166 case PIPE_FORMAT_L8_UNORM:
167 case PIPE_FORMAT_L8_SNORM:
168 case PIPE_FORMAT_L8_UINT:
169 case PIPE_FORMAT_L8_SINT:
170 case PIPE_FORMAT_L8_SRGB:
171 case PIPE_FORMAT_L16_UNORM:
172 case PIPE_FORMAT_L16_SNORM:
173 case PIPE_FORMAT_L16_UINT:
174 case PIPE_FORMAT_L16_SINT:
175 case PIPE_FORMAT_L16_FLOAT:
176 case PIPE_FORMAT_L32_UINT:
177 case PIPE_FORMAT_L32_SINT:
178 case PIPE_FORMAT_L32_FLOAT:
179 case PIPE_FORMAT_I16_UNORM:
180 case PIPE_FORMAT_I16_SNORM:
181 case PIPE_FORMAT_I16_UINT:
182 case PIPE_FORMAT_I16_SINT:
183 case PIPE_FORMAT_I16_FLOAT:
184 case PIPE_FORMAT_I32_UINT:
185 case PIPE_FORMAT_I32_SINT:
186 case PIPE_FORMAT_I32_FLOAT:
187 case PIPE_FORMAT_R8_UNORM:
188 case PIPE_FORMAT_R8_SNORM:
189 case PIPE_FORMAT_R8_UINT:
190 case PIPE_FORMAT_R8_SINT:
191 return V_0280A0_SWAP_STD;
192
193 case PIPE_FORMAT_L4A4_UNORM:
194 case PIPE_FORMAT_A4R4_UNORM:
195 return V_0280A0_SWAP_ALT;
196
197 /* 16-bit buffers. */
198 case PIPE_FORMAT_B5G6R5_UNORM:
199 return V_0280A0_SWAP_STD_REV;
200
201 case PIPE_FORMAT_B5G5R5A1_UNORM:
202 case PIPE_FORMAT_B5G5R5X1_UNORM:
203 return V_0280A0_SWAP_ALT;
204
205 case PIPE_FORMAT_B4G4R4A4_UNORM:
206 case PIPE_FORMAT_B4G4R4X4_UNORM:
207 return V_0280A0_SWAP_ALT;
208
209 case PIPE_FORMAT_Z16_UNORM:
210 return V_0280A0_SWAP_STD;
211
212 case PIPE_FORMAT_L8A8_UNORM:
213 case PIPE_FORMAT_L8A8_SNORM:
214 case PIPE_FORMAT_L8A8_UINT:
215 case PIPE_FORMAT_L8A8_SINT:
216 case PIPE_FORMAT_L8A8_SRGB:
217 case PIPE_FORMAT_L16A16_UNORM:
218 case PIPE_FORMAT_L16A16_SNORM:
219 case PIPE_FORMAT_L16A16_UINT:
220 case PIPE_FORMAT_L16A16_SINT:
221 case PIPE_FORMAT_L16A16_FLOAT:
222 case PIPE_FORMAT_L32A32_UINT:
223 case PIPE_FORMAT_L32A32_SINT:
224 case PIPE_FORMAT_L32A32_FLOAT:
225 case PIPE_FORMAT_R8A8_UNORM:
226 case PIPE_FORMAT_R8A8_SNORM:
227 case PIPE_FORMAT_R8A8_UINT:
228 case PIPE_FORMAT_R8A8_SINT:
229 case PIPE_FORMAT_R16A16_UNORM:
230 case PIPE_FORMAT_R16A16_SNORM:
231 case PIPE_FORMAT_R16A16_UINT:
232 case PIPE_FORMAT_R16A16_SINT:
233 case PIPE_FORMAT_R16A16_FLOAT:
234 case PIPE_FORMAT_R32A32_UINT:
235 case PIPE_FORMAT_R32A32_SINT:
236 case PIPE_FORMAT_R32A32_FLOAT:
237 return V_0280A0_SWAP_ALT;
238 case PIPE_FORMAT_R8G8_UNORM:
239 case PIPE_FORMAT_R8G8_SNORM:
240 case PIPE_FORMAT_R8G8_UINT:
241 case PIPE_FORMAT_R8G8_SINT:
242 return V_0280A0_SWAP_STD;
243
244 case PIPE_FORMAT_R16_UNORM:
245 case PIPE_FORMAT_R16_SNORM:
246 case PIPE_FORMAT_R16_UINT:
247 case PIPE_FORMAT_R16_SINT:
248 case PIPE_FORMAT_R16_FLOAT:
249 return V_0280A0_SWAP_STD;
250
251 /* 32-bit buffers. */
252
253 case PIPE_FORMAT_A8B8G8R8_SRGB:
254 return V_0280A0_SWAP_STD_REV;
255 case PIPE_FORMAT_B8G8R8A8_SRGB:
256 return V_0280A0_SWAP_ALT;
257
258 case PIPE_FORMAT_B8G8R8A8_UNORM:
259 case PIPE_FORMAT_B8G8R8X8_UNORM:
260 return V_0280A0_SWAP_ALT;
261
262 case PIPE_FORMAT_A8R8G8B8_UNORM:
263 case PIPE_FORMAT_X8R8G8B8_UNORM:
264 return V_0280A0_SWAP_ALT_REV;
265 case PIPE_FORMAT_R8G8B8A8_SNORM:
266 case PIPE_FORMAT_R8G8B8A8_UNORM:
267 case PIPE_FORMAT_R8G8B8X8_UNORM:
268 case PIPE_FORMAT_R8G8B8X8_SNORM:
269 case PIPE_FORMAT_R8G8B8X8_SRGB:
270 case PIPE_FORMAT_R8G8B8X8_UINT:
271 case PIPE_FORMAT_R8G8B8X8_SINT:
272 case PIPE_FORMAT_R8G8B8A8_SINT:
273 case PIPE_FORMAT_R8G8B8A8_UINT:
274 return V_0280A0_SWAP_STD;
275
276 case PIPE_FORMAT_A8B8G8R8_UNORM:
277 case PIPE_FORMAT_X8B8G8R8_UNORM:
278 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
279 return V_0280A0_SWAP_STD_REV;
280
281 case PIPE_FORMAT_Z24X8_UNORM:
282 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
283 return V_0280A0_SWAP_STD;
284
285 case PIPE_FORMAT_R10G10B10A2_UNORM:
286 case PIPE_FORMAT_R10G10B10X2_SNORM:
287 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
288 return V_0280A0_SWAP_STD;
289
290 case PIPE_FORMAT_B10G10R10A2_UNORM:
291 case PIPE_FORMAT_B10G10R10A2_UINT:
292 case PIPE_FORMAT_B10G10R10X2_UNORM:
293 return V_0280A0_SWAP_ALT;
294
295 case PIPE_FORMAT_R11G11B10_FLOAT:
296 case PIPE_FORMAT_R16G16_UNORM:
297 case PIPE_FORMAT_R16G16_SNORM:
298 case PIPE_FORMAT_R16G16_FLOAT:
299 case PIPE_FORMAT_R16G16_UINT:
300 case PIPE_FORMAT_R16G16_SINT:
301 case PIPE_FORMAT_R32_UINT:
302 case PIPE_FORMAT_R32_SINT:
303 case PIPE_FORMAT_R32_FLOAT:
304 case PIPE_FORMAT_Z32_FLOAT:
305 return V_0280A0_SWAP_STD;
306
307 /* 64-bit buffers. */
308 case PIPE_FORMAT_R32G32_FLOAT:
309 case PIPE_FORMAT_R32G32_UINT:
310 case PIPE_FORMAT_R32G32_SINT:
311 case PIPE_FORMAT_R16G16B16A16_UNORM:
312 case PIPE_FORMAT_R16G16B16A16_SNORM:
313 case PIPE_FORMAT_R16G16B16A16_UINT:
314 case PIPE_FORMAT_R16G16B16A16_SINT:
315 case PIPE_FORMAT_R16G16B16A16_FLOAT:
316 case PIPE_FORMAT_R16G16B16X16_UNORM:
317 case PIPE_FORMAT_R16G16B16X16_SNORM:
318 case PIPE_FORMAT_R16G16B16X16_FLOAT:
319 case PIPE_FORMAT_R16G16B16X16_UINT:
320 case PIPE_FORMAT_R16G16B16X16_SINT:
321 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
322
323 /* 128-bit buffers. */
324 case PIPE_FORMAT_R32G32B32A32_FLOAT:
325 case PIPE_FORMAT_R32G32B32A32_SNORM:
326 case PIPE_FORMAT_R32G32B32A32_UNORM:
327 case PIPE_FORMAT_R32G32B32A32_SINT:
328 case PIPE_FORMAT_R32G32B32A32_UINT:
329 case PIPE_FORMAT_R32G32B32X32_FLOAT:
330 case PIPE_FORMAT_R32G32B32X32_UINT:
331 case PIPE_FORMAT_R32G32B32X32_SINT:
332 return V_0280A0_SWAP_STD;
333 default:
334 R600_ERR("unsupported colorswap format %d\n", format);
335 return ~0U;
336 }
337 return ~0U;
338 }
339
340 static uint32_t r600_translate_colorformat(enum pipe_format format)
341 {
342 switch (format) {
343 case PIPE_FORMAT_L4A4_UNORM:
344 case PIPE_FORMAT_R4A4_UNORM:
345 case PIPE_FORMAT_A4R4_UNORM:
346 return V_0280A0_COLOR_4_4;
347
348 /* 8-bit buffers. */
349 case PIPE_FORMAT_A8_UNORM:
350 case PIPE_FORMAT_A8_SNORM:
351 case PIPE_FORMAT_A8_UINT:
352 case PIPE_FORMAT_A8_SINT:
353 case PIPE_FORMAT_I8_UNORM:
354 case PIPE_FORMAT_I8_SNORM:
355 case PIPE_FORMAT_I8_UINT:
356 case PIPE_FORMAT_I8_SINT:
357 case PIPE_FORMAT_L8_UNORM:
358 case PIPE_FORMAT_L8_SNORM:
359 case PIPE_FORMAT_L8_UINT:
360 case PIPE_FORMAT_L8_SINT:
361 case PIPE_FORMAT_L8_SRGB:
362 case PIPE_FORMAT_R8_UNORM:
363 case PIPE_FORMAT_R8_SNORM:
364 case PIPE_FORMAT_R8_UINT:
365 case PIPE_FORMAT_R8_SINT:
366 return V_0280A0_COLOR_8;
367
368 /* 16-bit buffers. */
369 case PIPE_FORMAT_B5G6R5_UNORM:
370 return V_0280A0_COLOR_5_6_5;
371
372 case PIPE_FORMAT_B5G5R5A1_UNORM:
373 case PIPE_FORMAT_B5G5R5X1_UNORM:
374 return V_0280A0_COLOR_1_5_5_5;
375
376 case PIPE_FORMAT_B4G4R4A4_UNORM:
377 case PIPE_FORMAT_B4G4R4X4_UNORM:
378 return V_0280A0_COLOR_4_4_4_4;
379
380 case PIPE_FORMAT_Z16_UNORM:
381 return V_0280A0_COLOR_16;
382
383 case PIPE_FORMAT_L8A8_UNORM:
384 case PIPE_FORMAT_L8A8_SNORM:
385 case PIPE_FORMAT_L8A8_UINT:
386 case PIPE_FORMAT_L8A8_SINT:
387 case PIPE_FORMAT_L8A8_SRGB:
388 case PIPE_FORMAT_R8G8_UNORM:
389 case PIPE_FORMAT_R8G8_SNORM:
390 case PIPE_FORMAT_R8G8_UINT:
391 case PIPE_FORMAT_R8G8_SINT:
392 case PIPE_FORMAT_R8A8_UNORM:
393 case PIPE_FORMAT_R8A8_SNORM:
394 case PIPE_FORMAT_R8A8_UINT:
395 case PIPE_FORMAT_R8A8_SINT:
396 return V_0280A0_COLOR_8_8;
397
398 case PIPE_FORMAT_R16_UNORM:
399 case PIPE_FORMAT_R16_SNORM:
400 case PIPE_FORMAT_R16_UINT:
401 case PIPE_FORMAT_R16_SINT:
402 case PIPE_FORMAT_A16_UNORM:
403 case PIPE_FORMAT_A16_SNORM:
404 case PIPE_FORMAT_A16_UINT:
405 case PIPE_FORMAT_A16_SINT:
406 case PIPE_FORMAT_L16_UNORM:
407 case PIPE_FORMAT_L16_SNORM:
408 case PIPE_FORMAT_L16_UINT:
409 case PIPE_FORMAT_L16_SINT:
410 case PIPE_FORMAT_I16_UNORM:
411 case PIPE_FORMAT_I16_SNORM:
412 case PIPE_FORMAT_I16_UINT:
413 case PIPE_FORMAT_I16_SINT:
414 return V_0280A0_COLOR_16;
415
416 case PIPE_FORMAT_R16_FLOAT:
417 case PIPE_FORMAT_A16_FLOAT:
418 case PIPE_FORMAT_L16_FLOAT:
419 case PIPE_FORMAT_I16_FLOAT:
420 return V_0280A0_COLOR_16_FLOAT;
421
422 /* 32-bit buffers. */
423 case PIPE_FORMAT_A8B8G8R8_SRGB:
424 case PIPE_FORMAT_A8B8G8R8_UNORM:
425 case PIPE_FORMAT_A8R8G8B8_UNORM:
426 case PIPE_FORMAT_B8G8R8A8_SRGB:
427 case PIPE_FORMAT_B8G8R8A8_UNORM:
428 case PIPE_FORMAT_B8G8R8X8_UNORM:
429 case PIPE_FORMAT_R8G8B8A8_SNORM:
430 case PIPE_FORMAT_R8G8B8A8_UNORM:
431 case PIPE_FORMAT_R8G8B8X8_UNORM:
432 case PIPE_FORMAT_R8G8B8X8_SNORM:
433 case PIPE_FORMAT_R8G8B8X8_SRGB:
434 case PIPE_FORMAT_R8G8B8X8_UINT:
435 case PIPE_FORMAT_R8G8B8X8_SINT:
436 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
437 case PIPE_FORMAT_X8B8G8R8_UNORM:
438 case PIPE_FORMAT_X8R8G8B8_UNORM:
439 case PIPE_FORMAT_R8G8B8A8_SINT:
440 case PIPE_FORMAT_R8G8B8A8_UINT:
441 return V_0280A0_COLOR_8_8_8_8;
442
443 case PIPE_FORMAT_R10G10B10A2_UNORM:
444 case PIPE_FORMAT_R10G10B10X2_SNORM:
445 case PIPE_FORMAT_B10G10R10A2_UNORM:
446 case PIPE_FORMAT_B10G10R10A2_UINT:
447 case PIPE_FORMAT_B10G10R10X2_UNORM:
448 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
449 return V_0280A0_COLOR_2_10_10_10;
450
451 case PIPE_FORMAT_Z24X8_UNORM:
452 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
453 return V_0280A0_COLOR_8_24;
454
455 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
456 return V_0280A0_COLOR_X24_8_32_FLOAT;
457
458 case PIPE_FORMAT_R32_UINT:
459 case PIPE_FORMAT_R32_SINT:
460 case PIPE_FORMAT_A32_UINT:
461 case PIPE_FORMAT_A32_SINT:
462 case PIPE_FORMAT_L32_UINT:
463 case PIPE_FORMAT_L32_SINT:
464 case PIPE_FORMAT_I32_UINT:
465 case PIPE_FORMAT_I32_SINT:
466 return V_0280A0_COLOR_32;
467
468 case PIPE_FORMAT_R32_FLOAT:
469 case PIPE_FORMAT_A32_FLOAT:
470 case PIPE_FORMAT_L32_FLOAT:
471 case PIPE_FORMAT_I32_FLOAT:
472 case PIPE_FORMAT_Z32_FLOAT:
473 return V_0280A0_COLOR_32_FLOAT;
474
475 case PIPE_FORMAT_R16G16_FLOAT:
476 case PIPE_FORMAT_L16A16_FLOAT:
477 case PIPE_FORMAT_R16A16_FLOAT:
478 return V_0280A0_COLOR_16_16_FLOAT;
479
480 case PIPE_FORMAT_R16G16_UNORM:
481 case PIPE_FORMAT_R16G16_SNORM:
482 case PIPE_FORMAT_R16G16_UINT:
483 case PIPE_FORMAT_R16G16_SINT:
484 case PIPE_FORMAT_L16A16_UNORM:
485 case PIPE_FORMAT_L16A16_SNORM:
486 case PIPE_FORMAT_L16A16_UINT:
487 case PIPE_FORMAT_L16A16_SINT:
488 case PIPE_FORMAT_R16A16_UNORM:
489 case PIPE_FORMAT_R16A16_SNORM:
490 case PIPE_FORMAT_R16A16_UINT:
491 case PIPE_FORMAT_R16A16_SINT:
492 return V_0280A0_COLOR_16_16;
493
494 case PIPE_FORMAT_R11G11B10_FLOAT:
495 return V_0280A0_COLOR_10_11_11_FLOAT;
496
497 /* 64-bit buffers. */
498 case PIPE_FORMAT_R16G16B16A16_UINT:
499 case PIPE_FORMAT_R16G16B16A16_SINT:
500 case PIPE_FORMAT_R16G16B16A16_UNORM:
501 case PIPE_FORMAT_R16G16B16A16_SNORM:
502 case PIPE_FORMAT_R16G16B16X16_UNORM:
503 case PIPE_FORMAT_R16G16B16X16_SNORM:
504 case PIPE_FORMAT_R16G16B16X16_UINT:
505 case PIPE_FORMAT_R16G16B16X16_SINT:
506 return V_0280A0_COLOR_16_16_16_16;
507
508 case PIPE_FORMAT_R16G16B16A16_FLOAT:
509 case PIPE_FORMAT_R16G16B16X16_FLOAT:
510 return V_0280A0_COLOR_16_16_16_16_FLOAT;
511
512 case PIPE_FORMAT_R32G32_FLOAT:
513 case PIPE_FORMAT_L32A32_FLOAT:
514 case PIPE_FORMAT_R32A32_FLOAT:
515 return V_0280A0_COLOR_32_32_FLOAT;
516
517 case PIPE_FORMAT_R32G32_SINT:
518 case PIPE_FORMAT_R32G32_UINT:
519 case PIPE_FORMAT_L32A32_UINT:
520 case PIPE_FORMAT_L32A32_SINT:
521 return V_0280A0_COLOR_32_32;
522
523 /* 128-bit buffers. */
524 case PIPE_FORMAT_R32G32B32A32_FLOAT:
525 case PIPE_FORMAT_R32G32B32X32_FLOAT:
526 return V_0280A0_COLOR_32_32_32_32_FLOAT;
527 case PIPE_FORMAT_R32G32B32A32_SNORM:
528 case PIPE_FORMAT_R32G32B32A32_UNORM:
529 case PIPE_FORMAT_R32G32B32A32_SINT:
530 case PIPE_FORMAT_R32G32B32A32_UINT:
531 case PIPE_FORMAT_R32G32B32X32_UINT:
532 case PIPE_FORMAT_R32G32B32X32_SINT:
533 return V_0280A0_COLOR_32_32_32_32;
534
535 /* YUV buffers. */
536 case PIPE_FORMAT_UYVY:
537 case PIPE_FORMAT_YUYV:
538 default:
539 return ~0U; /* Unsupported. */
540 }
541 }
542
543 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
544 {
545 if (R600_BIG_ENDIAN) {
546 switch(colorformat) {
547 case V_0280A0_COLOR_4_4:
548 return ENDIAN_NONE;
549
550 /* 8-bit buffers. */
551 case V_0280A0_COLOR_8:
552 return ENDIAN_NONE;
553
554 /* 16-bit buffers. */
555 case V_0280A0_COLOR_5_6_5:
556 case V_0280A0_COLOR_1_5_5_5:
557 case V_0280A0_COLOR_4_4_4_4:
558 case V_0280A0_COLOR_16:
559 case V_0280A0_COLOR_8_8:
560 return ENDIAN_8IN16;
561
562 /* 32-bit buffers. */
563 case V_0280A0_COLOR_8_8_8_8:
564 case V_0280A0_COLOR_2_10_10_10:
565 case V_0280A0_COLOR_8_24:
566 case V_0280A0_COLOR_24_8:
567 case V_0280A0_COLOR_32_FLOAT:
568 case V_0280A0_COLOR_16_16_FLOAT:
569 case V_0280A0_COLOR_16_16:
570 return ENDIAN_8IN32;
571
572 /* 64-bit buffers. */
573 case V_0280A0_COLOR_16_16_16_16:
574 case V_0280A0_COLOR_16_16_16_16_FLOAT:
575 return ENDIAN_8IN16;
576
577 case V_0280A0_COLOR_32_32_FLOAT:
578 case V_0280A0_COLOR_32_32:
579 case V_0280A0_COLOR_X24_8_32_FLOAT:
580 return ENDIAN_8IN32;
581
582 /* 128-bit buffers. */
583 case V_0280A0_COLOR_32_32_32_FLOAT:
584 case V_0280A0_COLOR_32_32_32_32_FLOAT:
585 case V_0280A0_COLOR_32_32_32_32:
586 return ENDIAN_8IN32;
587 default:
588 return ENDIAN_NONE; /* Unsupported. */
589 }
590 } else {
591 return ENDIAN_NONE;
592 }
593 }
594
595 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
596 {
597 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
598 }
599
600 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
601 {
602 return r600_translate_colorformat(format) != ~0U &&
603 r600_translate_colorswap(format) != ~0U;
604 }
605
606 static bool r600_is_zs_format_supported(enum pipe_format format)
607 {
608 return r600_translate_dbformat(format) != ~0U;
609 }
610
611 boolean r600_is_format_supported(struct pipe_screen *screen,
612 enum pipe_format format,
613 enum pipe_texture_target target,
614 unsigned sample_count,
615 unsigned usage)
616 {
617 struct r600_screen *rscreen = (struct r600_screen*)screen;
618 unsigned retval = 0;
619
620 if (target >= PIPE_MAX_TEXTURE_TYPES) {
621 R600_ERR("r600: unsupported texture type %d\n", target);
622 return FALSE;
623 }
624
625 if (!util_format_is_supported(format, usage))
626 return FALSE;
627
628 if (sample_count > 1) {
629 if (!rscreen->has_msaa)
630 return FALSE;
631
632 /* R11G11B10 is broken on R6xx. */
633 if (rscreen->chip_class == R600 &&
634 format == PIPE_FORMAT_R11G11B10_FLOAT)
635 return FALSE;
636
637 /* MSAA integer colorbuffers hang. */
638 if (util_format_is_pure_integer(format) &&
639 !util_format_is_depth_or_stencil(format))
640 return FALSE;
641
642 switch (sample_count) {
643 case 2:
644 case 4:
645 case 8:
646 break;
647 default:
648 return FALSE;
649 }
650 }
651
652 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
653 r600_is_sampler_format_supported(screen, format)) {
654 retval |= PIPE_BIND_SAMPLER_VIEW;
655 }
656
657 if ((usage & (PIPE_BIND_RENDER_TARGET |
658 PIPE_BIND_DISPLAY_TARGET |
659 PIPE_BIND_SCANOUT |
660 PIPE_BIND_SHARED)) &&
661 r600_is_colorbuffer_format_supported(format)) {
662 retval |= usage &
663 (PIPE_BIND_RENDER_TARGET |
664 PIPE_BIND_DISPLAY_TARGET |
665 PIPE_BIND_SCANOUT |
666 PIPE_BIND_SHARED);
667 }
668
669 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
670 r600_is_zs_format_supported(format)) {
671 retval |= PIPE_BIND_DEPTH_STENCIL;
672 }
673
674 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
675 r600_is_vertex_format_supported(format)) {
676 retval |= PIPE_BIND_VERTEX_BUFFER;
677 }
678
679 if (usage & PIPE_BIND_TRANSFER_READ)
680 retval |= PIPE_BIND_TRANSFER_READ;
681 if (usage & PIPE_BIND_TRANSFER_WRITE)
682 retval |= PIPE_BIND_TRANSFER_WRITE;
683
684 return retval == usage;
685 }
686
687 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
688 {
689 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
690 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
691 float offset_units = state->offset_units;
692 float offset_scale = state->offset_scale;
693
694 switch (state->zs_format) {
695 case PIPE_FORMAT_Z24X8_UNORM:
696 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
697 offset_units *= 2.0f;
698 break;
699 case PIPE_FORMAT_Z16_UNORM:
700 offset_units *= 4.0f;
701 break;
702 default:;
703 }
704
705 r600_write_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
706 r600_write_value(cs, fui(offset_scale));
707 r600_write_value(cs, fui(offset_units));
708 r600_write_value(cs, fui(offset_scale));
709 r600_write_value(cs, fui(offset_units));
710 }
711
712 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
713 {
714 int j = state->independent_blend_enable ? i : 0;
715
716 unsigned eqRGB = state->rt[j].rgb_func;
717 unsigned srcRGB = state->rt[j].rgb_src_factor;
718 unsigned dstRGB = state->rt[j].rgb_dst_factor;
719
720 unsigned eqA = state->rt[j].alpha_func;
721 unsigned srcA = state->rt[j].alpha_src_factor;
722 unsigned dstA = state->rt[j].alpha_dst_factor;
723 uint32_t bc = 0;
724
725 if (!state->rt[j].blend_enable)
726 return 0;
727
728 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
729 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
730 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
731
732 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
733 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
734 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
735 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
736 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
737 }
738 return bc;
739 }
740
741 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
742 const struct pipe_blend_state *state,
743 int mode)
744 {
745 struct r600_context *rctx = (struct r600_context *)ctx;
746 uint32_t color_control = 0, target_mask = 0;
747 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
748
749 if (!blend) {
750 return NULL;
751 }
752
753 r600_init_command_buffer(&blend->buffer, 20);
754 r600_init_command_buffer(&blend->buffer_no_blend, 20);
755
756 /* R600 does not support per-MRT blends */
757 if (rctx->family > CHIP_R600)
758 color_control |= S_028808_PER_MRT_BLEND(1);
759
760 if (state->logicop_enable) {
761 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
762 } else {
763 color_control |= (0xcc << 16);
764 }
765 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
766 if (state->independent_blend_enable) {
767 for (int i = 0; i < 8; i++) {
768 if (state->rt[i].blend_enable) {
769 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
770 }
771 target_mask |= (state->rt[i].colormask << (4 * i));
772 }
773 } else {
774 for (int i = 0; i < 8; i++) {
775 if (state->rt[0].blend_enable) {
776 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
777 }
778 target_mask |= (state->rt[0].colormask << (4 * i));
779 }
780 }
781
782 if (target_mask)
783 color_control |= S_028808_SPECIAL_OP(mode);
784 else
785 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
786
787 /* only MRT0 has dual src blend */
788 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
789 blend->cb_target_mask = target_mask;
790 blend->cb_color_control = color_control;
791 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
792 blend->alpha_to_one = state->alpha_to_one;
793
794 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
795 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
796 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
797 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
798 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
799 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
800
801 /* Copy over the registers set so far into buffer_no_blend. */
802 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
803 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
804
805 /* Only add blend registers if blending is enabled. */
806 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
807 return blend;
808 }
809
810 /* The first R600 does not support per-MRT blends */
811 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
812 r600_get_blend_control(state, 0));
813
814 if (rctx->family > CHIP_R600) {
815 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
816 for (int i = 0; i < 8; i++) {
817 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
818 }
819 }
820 return blend;
821 }
822
823 static void *r600_create_blend_state(struct pipe_context *ctx,
824 const struct pipe_blend_state *state)
825 {
826 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
827 }
828
829 static void *r600_create_dsa_state(struct pipe_context *ctx,
830 const struct pipe_depth_stencil_alpha_state *state)
831 {
832 unsigned db_depth_control, alpha_test_control, alpha_ref;
833 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
834
835 if (dsa == NULL) {
836 return NULL;
837 }
838
839 r600_init_command_buffer(&dsa->buffer, 3);
840
841 dsa->valuemask[0] = state->stencil[0].valuemask;
842 dsa->valuemask[1] = state->stencil[1].valuemask;
843 dsa->writemask[0] = state->stencil[0].writemask;
844 dsa->writemask[1] = state->stencil[1].writemask;
845
846 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
847 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
848 S_028800_ZFUNC(state->depth.func);
849
850 /* stencil */
851 if (state->stencil[0].enabled) {
852 db_depth_control |= S_028800_STENCIL_ENABLE(1);
853 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
854 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
855 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
856 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
857
858 if (state->stencil[1].enabled) {
859 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
860 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
861 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
862 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
863 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
864 }
865 }
866
867 /* alpha */
868 alpha_test_control = 0;
869 alpha_ref = 0;
870 if (state->alpha.enabled) {
871 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
872 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
873 alpha_ref = fui(state->alpha.ref_value);
874 }
875 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
876 dsa->alpha_ref = alpha_ref;
877
878 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
879 return dsa;
880 }
881
882 static void *r600_create_rs_state(struct pipe_context *ctx,
883 const struct pipe_rasterizer_state *state)
884 {
885 struct r600_context *rctx = (struct r600_context *)ctx;
886 unsigned tmp, sc_mode_cntl, spi_interp;
887 float psize_min, psize_max;
888 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
889
890 if (rs == NULL) {
891 return NULL;
892 }
893
894 r600_init_command_buffer(&rs->buffer, 30);
895
896 rs->flatshade = state->flatshade;
897 rs->sprite_coord_enable = state->sprite_coord_enable;
898 rs->two_side = state->light_twoside;
899 rs->clip_plane_enable = state->clip_plane_enable;
900 rs->pa_sc_line_stipple = state->line_stipple_enable ?
901 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
902 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
903 rs->pa_cl_clip_cntl =
904 S_028810_PS_UCP_MODE(3) |
905 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
906 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
907 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
908 rs->multisample_enable = state->multisample;
909
910 /* offset */
911 rs->offset_units = state->offset_units;
912 rs->offset_scale = state->offset_scale * 12.0f;
913 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
914
915 if (state->point_size_per_vertex) {
916 psize_min = util_get_min_point_size(state);
917 psize_max = 8192;
918 } else {
919 /* Force the point size to be as if the vertex output was disabled. */
920 psize_min = state->point_size;
921 psize_max = state->point_size;
922 }
923
924 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
925 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
926 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
927 if (rctx->chip_class >= R700) {
928 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
929 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
930 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
931 } else {
932 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
933 rs->scissor_enable = state->scissor;
934 }
935
936 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
937 if (state->sprite_coord_enable) {
938 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
939 S_0286D4_PNT_SPRITE_OVRD_X(2) |
940 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
941 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
942 S_0286D4_PNT_SPRITE_OVRD_W(1);
943 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
944 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
945 }
946 }
947
948 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
949 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
950 tmp = r600_pack_float_12p4(state->point_size/2);
951 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
952 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
953 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
954 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
955 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
956 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
957 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
958
959 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
960 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
961 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
962 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
963 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
964 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
965 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
966 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
967 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
968 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
969 S_028814_FACE(!state->front_ccw) |
970 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
971 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
972 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
973 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
974 state->fill_back != PIPE_POLYGON_MODE_FILL) |
975 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
976 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
977 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
978 return rs;
979 }
980
981 static void *r600_create_sampler_state(struct pipe_context *ctx,
982 const struct pipe_sampler_state *state)
983 {
984 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
985 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
986
987 if (ss == NULL) {
988 return NULL;
989 }
990
991 ss->seamless_cube_map = state->seamless_cube_map;
992 ss->border_color_use = sampler_state_needs_border_color(state);
993
994 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
995 ss->tex_sampler_words[0] =
996 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
997 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
998 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
999 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
1000 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
1001 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1002 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
1003 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1004 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
1005 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
1006 ss->tex_sampler_words[1] =
1007 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1008 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1009 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
1010 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
1011 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
1012
1013 if (ss->border_color_use) {
1014 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
1015 }
1016 return ss;
1017 }
1018
1019 static struct pipe_sampler_view *
1020 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
1021 unsigned width0, unsigned height0)
1022
1023 {
1024 struct pipe_context *ctx = view->base.context;
1025 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
1026 uint64_t va;
1027 int stride = util_format_get_blocksize(view->base.format);
1028 unsigned format, num_format, format_comp, endian;
1029
1030 r600_vertex_data_type(view->base.format,
1031 &format, &num_format, &format_comp,
1032 &endian);
1033
1034 va = r600_resource_va(ctx->screen, view->base.texture);
1035 view->tex_resource = &tmp->resource;
1036
1037 view->skip_mip_address_reloc = true;
1038 view->tex_resource_words[0] = va;
1039 view->tex_resource_words[1] = width0 - 1;
1040 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(va >> 32UL) |
1041 S_038008_STRIDE(stride) |
1042 S_038008_DATA_FORMAT(format) |
1043 S_038008_NUM_FORMAT_ALL(num_format) |
1044 S_038008_FORMAT_COMP_ALL(format_comp) |
1045 S_038008_SRF_MODE_ALL(1) |
1046 S_038008_ENDIAN_SWAP(endian);
1047 view->tex_resource_words[3] = 0;
1048 /*
1049 * in theory dword 4 is for number of elements, for use with resinfo,
1050 * but it seems to utterly fail to work, the amd gpu shader analyser
1051 * uses a const buffer to store the element sizes for buffer txq
1052 */
1053 view->tex_resource_words[4] = 0;
1054 view->tex_resource_words[5] = 0;
1055 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
1056 return &view->base;
1057 }
1058
1059 struct pipe_sampler_view *
1060 r600_create_sampler_view_custom(struct pipe_context *ctx,
1061 struct pipe_resource *texture,
1062 const struct pipe_sampler_view *state,
1063 unsigned width_first_level, unsigned height_first_level)
1064 {
1065 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1066 struct r600_texture *tmp = (struct r600_texture*)texture;
1067 unsigned format, endian;
1068 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1069 unsigned char swizzle[4], array_mode = 0;
1070 unsigned width, height, depth, offset_level, last_level;
1071
1072 if (view == NULL)
1073 return NULL;
1074
1075 /* initialize base object */
1076 view->base = *state;
1077 view->base.texture = NULL;
1078 pipe_reference(NULL, &texture->reference);
1079 view->base.texture = texture;
1080 view->base.reference.count = 1;
1081 view->base.context = ctx;
1082
1083 if (texture->target == PIPE_BUFFER)
1084 return texture_buffer_sampler_view(view, texture->width0, 1);
1085
1086 swizzle[0] = state->swizzle_r;
1087 swizzle[1] = state->swizzle_g;
1088 swizzle[2] = state->swizzle_b;
1089 swizzle[3] = state->swizzle_a;
1090
1091 format = r600_translate_texformat(ctx->screen, state->format,
1092 swizzle,
1093 &word4, &yuv_format);
1094 assert(format != ~0);
1095 if (format == ~0) {
1096 FREE(view);
1097 return NULL;
1098 }
1099
1100 if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) {
1101 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1102 FREE(view);
1103 return NULL;
1104 }
1105 tmp = tmp->flushed_depth_texture;
1106 }
1107
1108 endian = r600_colorformat_endian_swap(format);
1109
1110 offset_level = state->u.tex.first_level;
1111 last_level = state->u.tex.last_level - offset_level;
1112 width = width_first_level;
1113 height = height_first_level;
1114 depth = u_minify(texture->depth0, offset_level);
1115 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1116
1117 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1118 height = 1;
1119 depth = texture->array_size;
1120 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1121 depth = texture->array_size;
1122 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
1123 depth = texture->array_size / 6;
1124 switch (tmp->surface.level[offset_level].mode) {
1125 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1126 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1127 break;
1128 case RADEON_SURF_MODE_1D:
1129 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1130 break;
1131 case RADEON_SURF_MODE_2D:
1132 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1133 break;
1134 case RADEON_SURF_MODE_LINEAR:
1135 default:
1136 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1137 break;
1138 }
1139
1140 view->tex_resource = &tmp->resource;
1141 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1142 S_038000_TILE_MODE(array_mode) |
1143 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
1144 S_038000_PITCH((pitch / 8) - 1) |
1145 S_038000_TEX_WIDTH(width - 1));
1146 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
1147 S_038004_TEX_DEPTH(depth - 1) |
1148 S_038004_DATA_FORMAT(format));
1149 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
1150 if (offset_level >= tmp->surface.last_level) {
1151 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
1152 } else {
1153 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1154 }
1155 view->tex_resource_words[4] = (word4 |
1156 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1157 S_038010_REQUEST_SIZE(1) |
1158 S_038010_ENDIAN_SWAP(endian) |
1159 S_038010_BASE_LEVEL(0));
1160 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1161 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1162 if (texture->nr_samples > 1) {
1163 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1164 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
1165 } else {
1166 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
1167 }
1168 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1169 S_038018_MAX_ANISO(4 /* max 16 samples */));
1170 return &view->base;
1171 }
1172
1173 static struct pipe_sampler_view *
1174 r600_create_sampler_view(struct pipe_context *ctx,
1175 struct pipe_resource *tex,
1176 const struct pipe_sampler_view *state)
1177 {
1178 return r600_create_sampler_view_custom(ctx, tex, state,
1179 u_minify(tex->width0, state->u.tex.first_level),
1180 u_minify(tex->height0, state->u.tex.first_level));
1181 }
1182
1183 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1184 {
1185 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1186 struct pipe_clip_state *state = &rctx->clip_state.state;
1187
1188 r600_write_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
1189 r600_write_array(cs, 6*4, (unsigned*)state);
1190 }
1191
1192 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1193 const struct pipe_poly_stipple *state)
1194 {
1195 }
1196
1197 static void r600_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
1198 {
1199 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1200 struct pipe_scissor_state *state = &rctx->scissor.scissor;
1201
1202 if (rctx->chip_class != R600 || rctx->scissor.enable) {
1203 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1204 r600_write_value(cs, S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) |
1205 S_028240_WINDOW_OFFSET_DISABLE(1));
1206 r600_write_value(cs, S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy));
1207 } else {
1208 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1209 r600_write_value(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1210 S_028240_WINDOW_OFFSET_DISABLE(1));
1211 r600_write_value(cs, S_028244_BR_X(8192) | S_028244_BR_Y(8192));
1212 }
1213 }
1214
1215 static void r600_set_scissor_state(struct pipe_context *ctx,
1216 const struct pipe_scissor_state *state)
1217 {
1218 struct r600_context *rctx = (struct r600_context *)ctx;
1219
1220 rctx->scissor.scissor = *state;
1221
1222 if (rctx->chip_class == R600 && !rctx->scissor.enable)
1223 return;
1224
1225 rctx->scissor.atom.dirty = true;
1226 }
1227
1228 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
1229 unsigned size, unsigned alignment)
1230 {
1231 struct pipe_resource buffer;
1232
1233 memset(&buffer, 0, sizeof buffer);
1234 buffer.target = PIPE_BUFFER;
1235 buffer.format = PIPE_FORMAT_R8_UNORM;
1236 buffer.bind = PIPE_BIND_CUSTOM;
1237 buffer.usage = PIPE_USAGE_STATIC;
1238 buffer.flags = 0;
1239 buffer.width0 = size;
1240 buffer.height0 = 1;
1241 buffer.depth0 = 1;
1242 buffer.array_size = 1;
1243
1244 return (struct r600_resource*)
1245 r600_buffer_create(&rscreen->screen, &buffer, alignment);
1246 }
1247
1248 static void r600_init_color_surface(struct r600_context *rctx,
1249 struct r600_surface *surf,
1250 bool force_cmask_fmask)
1251 {
1252 struct r600_screen *rscreen = rctx->screen;
1253 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1254 unsigned level = surf->base.u.tex.level;
1255 unsigned pitch, slice;
1256 unsigned color_info;
1257 unsigned format, swap, ntype, endian;
1258 unsigned offset;
1259 const struct util_format_description *desc;
1260 int i;
1261 bool blend_bypass = 0, blend_clamp = 1;
1262
1263 if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
1264 r600_init_flushed_depth_texture(&rctx->context, surf->base.texture, NULL);
1265 rtex = rtex->flushed_depth_texture;
1266 assert(rtex);
1267 }
1268
1269 offset = rtex->surface.level[level].offset;
1270 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1271 offset += rtex->surface.level[level].slice_size *
1272 surf->base.u.tex.first_layer;
1273 }
1274 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1275 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1276 if (slice) {
1277 slice = slice - 1;
1278 }
1279 color_info = 0;
1280 switch (rtex->surface.level[level].mode) {
1281 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1282 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1283 break;
1284 case RADEON_SURF_MODE_1D:
1285 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1286 break;
1287 case RADEON_SURF_MODE_2D:
1288 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1289 break;
1290 case RADEON_SURF_MODE_LINEAR:
1291 default:
1292 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1293 break;
1294 }
1295
1296 desc = util_format_description(surf->base.format);
1297
1298 for (i = 0; i < 4; i++) {
1299 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1300 break;
1301 }
1302 }
1303
1304 ntype = V_0280A0_NUMBER_UNORM;
1305 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1306 ntype = V_0280A0_NUMBER_SRGB;
1307 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1308 if (desc->channel[i].normalized)
1309 ntype = V_0280A0_NUMBER_SNORM;
1310 else if (desc->channel[i].pure_integer)
1311 ntype = V_0280A0_NUMBER_SINT;
1312 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1313 if (desc->channel[i].normalized)
1314 ntype = V_0280A0_NUMBER_UNORM;
1315 else if (desc->channel[i].pure_integer)
1316 ntype = V_0280A0_NUMBER_UINT;
1317 }
1318
1319 format = r600_translate_colorformat(surf->base.format);
1320 assert(format != ~0);
1321
1322 swap = r600_translate_colorswap(surf->base.format);
1323 assert(swap != ~0);
1324
1325 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1326 endian = ENDIAN_NONE;
1327 } else {
1328 endian = r600_colorformat_endian_swap(format);
1329 }
1330
1331 /* set blend bypass according to docs if SINT/UINT or
1332 8/24 COLOR variants */
1333 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1334 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1335 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1336 blend_clamp = 0;
1337 blend_bypass = 1;
1338 }
1339
1340 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
1341
1342 color_info |= S_0280A0_FORMAT(format) |
1343 S_0280A0_COMP_SWAP(swap) |
1344 S_0280A0_BLEND_BYPASS(blend_bypass) |
1345 S_0280A0_BLEND_CLAMP(blend_clamp) |
1346 S_0280A0_NUMBER_TYPE(ntype) |
1347 S_0280A0_ENDIAN(endian);
1348
1349 /* EXPORT_NORM is an optimzation that can be enabled for better
1350 * performance in certain cases
1351 */
1352 if (rctx->chip_class == R600) {
1353 /* EXPORT_NORM can be enabled if:
1354 * - 11-bit or smaller UNORM/SNORM/SRGB
1355 * - BLEND_CLAMP is enabled
1356 * - BLEND_FLOAT32 is disabled
1357 */
1358 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1359 (desc->channel[i].size < 12 &&
1360 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1361 ntype != V_0280A0_NUMBER_UINT &&
1362 ntype != V_0280A0_NUMBER_SINT) &&
1363 G_0280A0_BLEND_CLAMP(color_info) &&
1364 !G_0280A0_BLEND_FLOAT32(color_info)) {
1365 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1366 surf->export_16bpc = true;
1367 }
1368 } else {
1369 /* EXPORT_NORM can be enabled if:
1370 * - 11-bit or smaller UNORM/SNORM/SRGB
1371 * - 16-bit or smaller FLOAT
1372 */
1373 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1374 ((desc->channel[i].size < 12 &&
1375 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1376 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1377 (desc->channel[i].size < 17 &&
1378 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1379 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1380 surf->export_16bpc = true;
1381 }
1382 }
1383
1384 /* These might not always be initialized to zero. */
1385 surf->cb_color_base = offset >> 8;
1386 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
1387 S_028060_SLICE_TILE_MAX(slice);
1388 surf->cb_color_fmask = surf->cb_color_base;
1389 surf->cb_color_cmask = surf->cb_color_base;
1390 surf->cb_color_mask = 0;
1391
1392 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1393 &rtex->resource.b.b);
1394 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1395 &rtex->resource.b.b);
1396
1397 if (rtex->cmask_size) {
1398 surf->cb_color_cmask = rtex->cmask_offset >> 8;
1399 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask_slice_tile_max);
1400
1401 if (rtex->fmask_size) {
1402 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1403 surf->cb_color_fmask = rtex->fmask_offset >> 8;
1404 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(slice);
1405 } else { /* cmask only */
1406 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
1407 }
1408 } else if (force_cmask_fmask) {
1409 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1410 *
1411 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1412 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1413 * because it's not an MSAA buffer.
1414 */
1415 struct r600_cmask_info cmask;
1416 struct r600_fmask_info fmask;
1417
1418 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
1419 r600_texture_get_fmask_info(rscreen, rtex, 8, &fmask);
1420
1421 /* CMASK. */
1422 if (!rctx->dummy_cmask ||
1423 rctx->dummy_cmask->buf->size < cmask.size ||
1424 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1425 struct pipe_transfer *transfer;
1426 void *ptr;
1427
1428 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1429 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1430
1431 /* Set the contents to 0xCC. */
1432 ptr = pipe_buffer_map(&rctx->context, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1433 memset(ptr, 0xCC, cmask.size);
1434 pipe_buffer_unmap(&rctx->context, transfer);
1435 }
1436 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1437 &rctx->dummy_cmask->b.b);
1438
1439 /* FMASK. */
1440 if (!rctx->dummy_fmask ||
1441 rctx->dummy_fmask->buf->size < fmask.size ||
1442 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1443 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1444 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1445
1446 }
1447 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1448 &rctx->dummy_fmask->b.b);
1449
1450 /* Init the registers. */
1451 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1452 surf->cb_color_cmask = 0;
1453 surf->cb_color_fmask = 0;
1454 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1455 S_028100_FMASK_TILE_MAX(slice);
1456 }
1457
1458 surf->cb_color_info = color_info;
1459
1460 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1461 surf->cb_color_view = 0;
1462 } else {
1463 surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
1464 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
1465 }
1466
1467 surf->color_initialized = true;
1468 }
1469
1470 static void r600_init_depth_surface(struct r600_context *rctx,
1471 struct r600_surface *surf)
1472 {
1473 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1474 unsigned level, pitch, slice, format, offset, array_mode;
1475
1476 level = surf->base.u.tex.level;
1477 offset = rtex->surface.level[level].offset;
1478 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1479 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1480 if (slice) {
1481 slice = slice - 1;
1482 }
1483 switch (rtex->surface.level[level].mode) {
1484 case RADEON_SURF_MODE_2D:
1485 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1486 break;
1487 case RADEON_SURF_MODE_1D:
1488 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1489 case RADEON_SURF_MODE_LINEAR:
1490 default:
1491 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1492 break;
1493 }
1494
1495 format = r600_translate_dbformat(surf->base.format);
1496 assert(format != ~0);
1497
1498 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1499 surf->db_depth_base = offset >> 8;
1500 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1501 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1502 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1503 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1504
1505 switch (surf->base.format) {
1506 case PIPE_FORMAT_Z24X8_UNORM:
1507 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1508 surf->pa_su_poly_offset_db_fmt_cntl =
1509 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1510 break;
1511 case PIPE_FORMAT_Z32_FLOAT:
1512 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1513 surf->pa_su_poly_offset_db_fmt_cntl =
1514 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1515 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1516 break;
1517 case PIPE_FORMAT_Z16_UNORM:
1518 surf->pa_su_poly_offset_db_fmt_cntl =
1519 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1520 break;
1521 default:;
1522 }
1523
1524 surf->htile_enabled = 0;
1525 /* use htile only for first level */
1526 if (rtex->htile && !level) {
1527 uint64_t va = r600_resource_va(&rctx->screen->screen, &rtex->htile->b.b);
1528 surf->htile_enabled = 1;
1529 surf->db_htile_data_base = va >> 8;
1530 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1531 S_028D24_HTILE_HEIGHT(1) |
1532 S_028D24_LINEAR(1);
1533 /* preload is not working properly on r6xx/r7xx */
1534 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1535 }
1536
1537 surf->depth_initialized = true;
1538 }
1539
1540 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1541 const struct pipe_framebuffer_state *state)
1542 {
1543 struct r600_context *rctx = (struct r600_context *)ctx;
1544 struct r600_surface *surf;
1545 struct r600_texture *rtex;
1546 unsigned i;
1547
1548 if (rctx->framebuffer.state.nr_cbufs) {
1549 rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1550
1551 if (rctx->chip_class >= R700 &&
1552 rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
1553 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
1554 }
1555 }
1556 if (rctx->framebuffer.state.zsbuf) {
1557 rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1558 }
1559
1560 /* Set the new state. */
1561 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1562
1563 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1564 rctx->framebuffer.cb0_is_integer = state->nr_cbufs &&
1565 util_format_is_pure_integer(state->cbufs[0]->format);
1566 rctx->framebuffer.compressed_cb_mask = 0;
1567 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1568 state->cbufs[0]->texture->nr_samples > 1 &&
1569 state->cbufs[1]->texture->nr_samples <= 1;
1570
1571 if (state->nr_cbufs)
1572 rctx->framebuffer.nr_samples = state->cbufs[0]->texture->nr_samples;
1573 else if (state->zsbuf)
1574 rctx->framebuffer.nr_samples = state->zsbuf->texture->nr_samples;
1575 else
1576 rctx->framebuffer.nr_samples = 0;
1577
1578 /* Colorbuffers. */
1579 for (i = 0; i < state->nr_cbufs; i++) {
1580 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1581 bool force_cmask_fmask = rctx->chip_class == R600 &&
1582 rctx->framebuffer.is_msaa_resolve &&
1583 i == 1;
1584
1585 surf = (struct r600_surface*)state->cbufs[i];
1586 rtex = (struct r600_texture*)surf->base.texture;
1587 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1588
1589 if (!surf->color_initialized || force_cmask_fmask) {
1590 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1591 if (force_cmask_fmask) {
1592 /* re-initialize later without compression */
1593 surf->color_initialized = false;
1594 }
1595 }
1596
1597 if (!surf->export_16bpc) {
1598 rctx->framebuffer.export_16bpc = false;
1599 }
1600
1601 if (rtex->fmask_size && rtex->cmask_size) {
1602 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1603 }
1604 }
1605
1606 /* Update alpha-test state dependencies.
1607 * Alpha-test is done on the first colorbuffer only. */
1608 if (state->nr_cbufs) {
1609 surf = (struct r600_surface*)state->cbufs[0];
1610 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1611 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1612 rctx->alphatest_state.atom.dirty = true;
1613 }
1614 }
1615
1616 /* ZS buffer. */
1617 if (state->zsbuf) {
1618 surf = (struct r600_surface*)state->zsbuf;
1619
1620 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1621
1622 if (!surf->depth_initialized) {
1623 r600_init_depth_surface(rctx, surf);
1624 }
1625
1626 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1627 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1628 rctx->poly_offset_state.atom.dirty = true;
1629 }
1630
1631 if (rctx->db_state.rsurf != surf) {
1632 rctx->db_state.rsurf = surf;
1633 rctx->db_state.atom.dirty = true;
1634 rctx->db_misc_state.atom.dirty = true;
1635 }
1636 } else if (rctx->db_state.rsurf) {
1637 rctx->db_state.rsurf = NULL;
1638 rctx->db_state.atom.dirty = true;
1639 rctx->db_misc_state.atom.dirty = true;
1640 }
1641
1642 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1643 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1644 rctx->cb_misc_state.atom.dirty = true;
1645 }
1646
1647 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1648 rctx->alphatest_state.bypass = false;
1649 rctx->alphatest_state.atom.dirty = true;
1650 }
1651
1652 r600_update_db_shader_control(rctx);
1653
1654 /* Calculate the CS size. */
1655 rctx->framebuffer.atom.num_dw =
1656 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1657
1658 if (rctx->framebuffer.state.nr_cbufs) {
1659 rctx->framebuffer.atom.num_dw += 6 * (2 + rctx->framebuffer.state.nr_cbufs);
1660 rctx->framebuffer.atom.num_dw += 6 * rctx->framebuffer.state.nr_cbufs; /* relocs */
1661
1662 }
1663 if (rctx->framebuffer.state.zsbuf) {
1664 rctx->framebuffer.atom.num_dw += 18;
1665 } else if (rctx->screen->info.drm_minor >= 18) {
1666 rctx->framebuffer.atom.num_dw += 3;
1667 }
1668 if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770) {
1669 rctx->framebuffer.atom.num_dw += 2;
1670 }
1671
1672 rctx->framebuffer.atom.dirty = true;
1673 }
1674
1675 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1676 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1677 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1678 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1679 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1680
1681 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1682 {
1683 static uint32_t sample_locs_2x[] = {
1684 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1685 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1686 };
1687 static unsigned max_dist_2x = 4;
1688 static uint32_t sample_locs_4x[] = {
1689 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1690 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1691 };
1692 static unsigned max_dist_4x = 6;
1693 static uint32_t sample_locs_8x[] = {
1694 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1695 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1696 };
1697 static unsigned max_dist_8x = 7;
1698
1699 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1700 unsigned max_dist = 0;
1701
1702 if (rctx->family == CHIP_R600) {
1703 switch (nr_samples) {
1704 default:
1705 nr_samples = 0;
1706 break;
1707 case 2:
1708 r600_write_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1709 max_dist = max_dist_2x;
1710 break;
1711 case 4:
1712 r600_write_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1713 max_dist = max_dist_4x;
1714 break;
1715 case 8:
1716 r600_write_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1717 r600_write_value(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1718 r600_write_value(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1719 max_dist = max_dist_8x;
1720 break;
1721 }
1722 } else {
1723 switch (nr_samples) {
1724 default:
1725 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1726 r600_write_value(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1727 r600_write_value(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1728 nr_samples = 0;
1729 break;
1730 case 2:
1731 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1732 r600_write_value(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1733 r600_write_value(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1734 max_dist = max_dist_2x;
1735 break;
1736 case 4:
1737 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1738 r600_write_value(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1739 r600_write_value(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1740 max_dist = max_dist_4x;
1741 break;
1742 case 8:
1743 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1744 r600_write_value(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1745 r600_write_value(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1746 max_dist = max_dist_8x;
1747 break;
1748 }
1749 }
1750
1751 if (nr_samples > 1) {
1752 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1753 r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
1754 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1755 r600_write_value(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1756 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1757 } else {
1758 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1759 r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1760 r600_write_value(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1761 }
1762 }
1763
1764 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1765 {
1766 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1767 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1768 unsigned nr_cbufs = state->nr_cbufs;
1769 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1770 unsigned i, sbu = 0;
1771
1772 /* Colorbuffers. */
1773 r600_write_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1774 for (i = 0; i < nr_cbufs; i++) {
1775 r600_write_value(cs, cb[i]->cb_color_info);
1776 }
1777 /* set CB_COLOR1_INFO for possible dual-src blending */
1778 if (i == 1) {
1779 r600_write_value(cs, cb[0]->cb_color_info);
1780 i++;
1781 }
1782 for (; i < 8; i++) {
1783 r600_write_value(cs, 0);
1784 }
1785
1786 if (nr_cbufs) {
1787 /* COLOR_BASE */
1788 r600_write_context_reg_seq(cs, R_028040_CB_COLOR0_BASE, nr_cbufs);
1789 for (i = 0; i < nr_cbufs; i++) {
1790 r600_write_value(cs, cb[i]->cb_color_base);
1791 }
1792
1793 /* relocations */
1794 for (i = 0; i < nr_cbufs; i++) {
1795 unsigned reloc = r600_context_bo_reloc(rctx,
1796 &rctx->rings.gfx,
1797 (struct r600_resource*)cb[i]->base.texture,
1798 RADEON_USAGE_READWRITE);
1799 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1800 r600_write_value(cs, reloc);
1801 }
1802
1803 r600_write_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1804 for (i = 0; i < nr_cbufs; i++) {
1805 r600_write_value(cs, cb[i]->cb_color_size);
1806 }
1807
1808 r600_write_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1809 for (i = 0; i < nr_cbufs; i++) {
1810 r600_write_value(cs, cb[i]->cb_color_view);
1811 }
1812
1813 r600_write_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1814 for (i = 0; i < nr_cbufs; i++) {
1815 r600_write_value(cs, cb[i]->cb_color_mask);
1816 }
1817
1818 /* FMASK. */
1819 r600_write_context_reg_seq(cs, R_0280E0_CB_COLOR0_FRAG, nr_cbufs);
1820 for (i = 0; i < nr_cbufs; i++) {
1821 r600_write_value(cs, cb[i]->cb_color_fmask);
1822 }
1823 /* relocations */
1824 for (i = 0; i < nr_cbufs; i++) {
1825 unsigned reloc = r600_context_bo_reloc(rctx,
1826 &rctx->rings.gfx,
1827 cb[i]->cb_buffer_fmask,
1828 RADEON_USAGE_READWRITE);
1829 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1830 r600_write_value(cs, reloc);
1831 }
1832
1833 /* CMASK. */
1834 r600_write_context_reg_seq(cs, R_0280C0_CB_COLOR0_TILE, nr_cbufs);
1835 for (i = 0; i < nr_cbufs; i++) {
1836 r600_write_value(cs, cb[i]->cb_color_cmask);
1837 }
1838 /* relocations */
1839 for (i = 0; i < nr_cbufs; i++) {
1840 unsigned reloc = r600_context_bo_reloc(rctx,
1841 &rctx->rings.gfx,
1842 cb[i]->cb_buffer_cmask,
1843 RADEON_USAGE_READWRITE);
1844 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1845 r600_write_value(cs, reloc);
1846 }
1847
1848 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1849 }
1850
1851 /* SURFACE_BASE_UPDATE */
1852 if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770 && sbu) {
1853 r600_write_value(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1854 r600_write_value(cs, sbu);
1855 sbu = 0;
1856 }
1857
1858 /* Zbuffer. */
1859 if (state->zsbuf) {
1860 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1861 unsigned reloc = r600_context_bo_reloc(rctx,
1862 &rctx->rings.gfx,
1863 (struct r600_resource*)state->zsbuf->texture,
1864 RADEON_USAGE_READWRITE);
1865
1866 r600_write_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1867 surf->pa_su_poly_offset_db_fmt_cntl);
1868
1869 r600_write_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1870 r600_write_value(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1871 r600_write_value(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1872 r600_write_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1873 r600_write_value(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1874 r600_write_value(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1875
1876 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1877 r600_write_value(cs, reloc);
1878
1879 r600_write_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1880
1881 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1882 } else if (rctx->screen->info.drm_minor >= 18) {
1883 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1884 * Older kernels are out of luck. */
1885 r600_write_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1886 }
1887
1888 /* SURFACE_BASE_UPDATE */
1889 if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770 && sbu) {
1890 r600_write_value(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1891 r600_write_value(cs, sbu);
1892 sbu = 0;
1893 }
1894
1895 /* Framebuffer dimensions. */
1896 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1897 r600_write_value(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1898 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1899 r600_write_value(cs, S_028244_BR_X(state->width) |
1900 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1901
1902 if (rctx->framebuffer.is_msaa_resolve) {
1903 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1904 } else {
1905 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1906 * will assure that the alpha-test will work even if there is
1907 * no colorbuffer bound. */
1908 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1909 (1ull << MAX2(nr_cbufs, 1)) - 1);
1910 }
1911
1912 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1913 }
1914
1915 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1916 {
1917 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1918 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1919
1920 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1921 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1922 if (rctx->chip_class == R600) {
1923 r600_write_value(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1924 r600_write_value(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1925 } else {
1926 r600_write_value(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1927 r600_write_value(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1928 }
1929 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1930 } else {
1931 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1932 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1933 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1934
1935 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1936 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1937 /* Always enable the first color output to make sure alpha-test works even without one. */
1938 r600_write_value(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1939 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1940 a->cb_color_control |
1941 S_028808_MULTIWRITE_ENABLE(multiwrite));
1942 }
1943 }
1944
1945 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1946 {
1947 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1948 struct r600_db_state *a = (struct r600_db_state*)atom;
1949
1950 if (a->rsurf && a->rsurf->htile_enabled) {
1951 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1952 unsigned reloc_idx;
1953
1954 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear));
1955 r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1956 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1957 reloc_idx = r600_context_bo_reloc(rctx, &rctx->rings.gfx, rtex->htile, RADEON_USAGE_READWRITE);
1958 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1959 cs->buf[cs->cdw++] = reloc_idx;
1960 } else {
1961 r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1962 }
1963 }
1964
1965 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1966 {
1967 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1968 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1969 unsigned db_render_control = 0;
1970 unsigned db_render_override =
1971 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1972 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1973
1974 if (a->occlusion_query_enabled) {
1975 if (rctx->chip_class >= R700) {
1976 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1977 }
1978 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1979 }
1980 if (rctx->db_state.rsurf && rctx->db_state.rsurf->htile_enabled) {
1981 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1982 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1983 /* This is to fix a lockup when hyperz and alpha test are enabled at
1984 * the same time somehow GPU get confuse on which order to pick for
1985 * z test
1986 */
1987 if (rctx->alphatest_state.sx_alpha_test_control) {
1988 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
1989 }
1990 } else {
1991 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1992 }
1993 if (a->flush_depthstencil_through_cb) {
1994 assert(a->copy_depth || a->copy_stencil);
1995
1996 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1997 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1998 S_028D0C_COPY_CENTROID(1) |
1999 S_028D0C_COPY_SAMPLE(a->copy_sample);
2000 } else if (a->flush_depthstencil_in_place) {
2001 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(1) |
2002 S_028D0C_STENCIL_COMPRESS_DISABLE(1);
2003 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
2004 }
2005 if (a->htile_clear) {
2006 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
2007 }
2008
2009 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
2010 r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
2011 r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
2012 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
2013 }
2014
2015 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
2016 {
2017 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2018 struct r600_config_state *a = (struct r600_config_state*)atom;
2019
2020 r600_write_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
2021 }
2022
2023 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
2024 {
2025 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2026 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
2027
2028 while (dirty_mask) {
2029 struct pipe_vertex_buffer *vb;
2030 struct r600_resource *rbuffer;
2031 unsigned offset;
2032 unsigned buffer_index = u_bit_scan(&dirty_mask);
2033
2034 vb = &rctx->vertex_buffer_state.vb[buffer_index];
2035 rbuffer = (struct r600_resource*)vb->buffer;
2036 assert(rbuffer);
2037
2038 offset = vb->buffer_offset;
2039
2040 /* fetch resources start at index 320 */
2041 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
2042 r600_write_value(cs, (320 + buffer_index) * 7);
2043 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
2044 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
2045 r600_write_value(cs, /* RESOURCEi_WORD2 */
2046 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
2047 S_038008_STRIDE(vb->stride));
2048 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
2049 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
2050 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
2051 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
2052
2053 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2054 r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, rbuffer, RADEON_USAGE_READ));
2055 }
2056 }
2057
2058 static void r600_emit_constant_buffers(struct r600_context *rctx,
2059 struct r600_constbuf_state *state,
2060 unsigned buffer_id_base,
2061 unsigned reg_alu_constbuf_size,
2062 unsigned reg_alu_const_cache)
2063 {
2064 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2065 uint32_t dirty_mask = state->dirty_mask;
2066
2067 while (dirty_mask) {
2068 struct pipe_constant_buffer *cb;
2069 struct r600_resource *rbuffer;
2070 unsigned offset;
2071 unsigned buffer_index = ffs(dirty_mask) - 1;
2072
2073 cb = &state->cb[buffer_index];
2074 rbuffer = (struct r600_resource*)cb->buffer;
2075 assert(rbuffer);
2076
2077 offset = cb->buffer_offset;
2078
2079 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
2080 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
2081 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
2082
2083 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2084 r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, rbuffer, RADEON_USAGE_READ));
2085
2086 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
2087 r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
2088 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
2089 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
2090 r600_write_value(cs, /* RESOURCEi_WORD2 */
2091 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
2092 S_038008_STRIDE(16));
2093 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
2094 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
2095 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
2096 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
2097
2098 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2099 r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, rbuffer, RADEON_USAGE_READ));
2100
2101 dirty_mask &= ~(1 << buffer_index);
2102 }
2103 state->dirty_mask = 0;
2104 }
2105
2106 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2107 {
2108 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 160,
2109 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2110 R_028980_ALU_CONST_CACHE_VS_0);
2111 }
2112
2113 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2114 {
2115 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
2116 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2117 R_0289C0_ALU_CONST_CACHE_GS_0);
2118 }
2119
2120 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2121 {
2122 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
2123 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2124 R_028940_ALU_CONST_CACHE_PS_0);
2125 }
2126
2127 static void r600_emit_sampler_views(struct r600_context *rctx,
2128 struct r600_samplerview_state *state,
2129 unsigned resource_id_base)
2130 {
2131 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2132 uint32_t dirty_mask = state->dirty_mask;
2133
2134 while (dirty_mask) {
2135 struct r600_pipe_sampler_view *rview;
2136 unsigned resource_index = u_bit_scan(&dirty_mask);
2137 unsigned reloc;
2138
2139 rview = state->views[resource_index];
2140 assert(rview);
2141
2142 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
2143 r600_write_value(cs, (resource_id_base + resource_index) * 7);
2144 r600_write_array(cs, 7, rview->tex_resource_words);
2145
2146 reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, rview->tex_resource,
2147 RADEON_USAGE_READ);
2148 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2149 r600_write_value(cs, reloc);
2150 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2151 r600_write_value(cs, reloc);
2152 }
2153 state->dirty_mask = 0;
2154 }
2155
2156 /* Resource IDs:
2157 * PS: 0 .. +160
2158 * VS: 160 .. +160
2159 * FS: 320 .. +16
2160 * GS: 336 .. +160
2161 */
2162
2163 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2164 {
2165 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 160 + R600_MAX_CONST_BUFFERS);
2166 }
2167
2168 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2169 {
2170 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
2171 }
2172
2173 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2174 {
2175 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
2176 }
2177
2178 static void r600_emit_sampler_states(struct r600_context *rctx,
2179 struct r600_textures_info *texinfo,
2180 unsigned resource_id_base,
2181 unsigned border_color_reg)
2182 {
2183 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2184 uint32_t dirty_mask = texinfo->states.dirty_mask;
2185
2186 while (dirty_mask) {
2187 struct r600_pipe_sampler_state *rstate;
2188 struct r600_pipe_sampler_view *rview;
2189 unsigned i = u_bit_scan(&dirty_mask);
2190
2191 rstate = texinfo->states.states[i];
2192 assert(rstate);
2193 rview = texinfo->views.views[i];
2194
2195 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
2196 * filtering between layers.
2197 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
2198 */
2199 if (rview) {
2200 enum pipe_texture_target target = rview->base.texture->target;
2201 if (target == PIPE_TEXTURE_1D_ARRAY ||
2202 target == PIPE_TEXTURE_2D_ARRAY) {
2203 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
2204 texinfo->is_array_sampler[i] = true;
2205 } else {
2206 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
2207 texinfo->is_array_sampler[i] = false;
2208 }
2209 }
2210
2211 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2212 r600_write_value(cs, (resource_id_base + i) * 3);
2213 r600_write_array(cs, 3, rstate->tex_sampler_words);
2214
2215 if (rstate->border_color_use) {
2216 unsigned offset;
2217
2218 offset = border_color_reg;
2219 offset += i * 16;
2220 r600_write_config_reg_seq(cs, offset, 4);
2221 r600_write_array(cs, 4, rstate->border_color.ui);
2222 }
2223 }
2224 texinfo->states.dirty_mask = 0;
2225 }
2226
2227 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2228 {
2229 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
2230 }
2231
2232 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2233 {
2234 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
2235 }
2236
2237 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2238 {
2239 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
2240 }
2241
2242 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
2243 {
2244 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2245 unsigned tmp;
2246
2247 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
2248 S_009508_SYNC_GRADIENT(1) |
2249 S_009508_SYNC_WALKER(1) |
2250 S_009508_SYNC_ALIGNER(1);
2251 if (!rctx->seamless_cube_map.enabled) {
2252 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
2253 }
2254 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
2255 }
2256
2257 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2258 {
2259 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2260 uint8_t mask = s->sample_mask;
2261
2262 r600_write_context_reg(rctx->rings.gfx.cs, R_028C48_PA_SC_AA_MASK,
2263 mask | (mask << 8) | (mask << 16) | (mask << 24));
2264 }
2265
2266 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2267 {
2268 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2269 struct r600_cso_state *state = (struct r600_cso_state*)a;
2270 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2271
2272 r600_write_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
2273 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2274 r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, shader->buffer, RADEON_USAGE_READ));
2275 }
2276
2277 void r600_init_state_functions(struct r600_context *rctx)
2278 {
2279 unsigned id = 4;
2280
2281 /* !!!
2282 * To avoid GPU lockup registers must be emited in a specific order
2283 * (no kidding ...). The order below is important and have been
2284 * partialy infered from analyzing fglrx command stream.
2285 *
2286 * Don't reorder atom without carefully checking the effect (GPU lockup
2287 * or piglit regression).
2288 * !!!
2289 */
2290
2291 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
2292
2293 /* shader const */
2294 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
2295 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
2296 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
2297
2298 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2299 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
2300 */
2301 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
2302 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
2303 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
2304 /* resource */
2305 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
2306 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
2307 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
2308 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
2309
2310 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 6);
2311 r600_init_atom(rctx, &rctx->vgt2_state.atom, id++, r600_emit_vgt2_state, 3);
2312
2313 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
2314 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
2315 rctx->sample_mask.sample_mask = ~0;
2316
2317 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
2318 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
2319 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
2320 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
2321 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
2322 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
2323 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
2324 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
2325 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
2326 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
2327 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
2328 r600_init_atom(rctx, &rctx->scissor.atom, id++, r600_emit_scissor_state, 4);
2329 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
2330 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
2331 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
2332 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
2333
2334 rctx->context.create_blend_state = r600_create_blend_state;
2335 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
2336 rctx->context.create_rasterizer_state = r600_create_rs_state;
2337 rctx->context.create_sampler_state = r600_create_sampler_state;
2338 rctx->context.create_sampler_view = r600_create_sampler_view;
2339 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
2340 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
2341 rctx->context.set_scissor_state = r600_set_scissor_state;
2342 }
2343
2344 /* Adjust GPR allocation on R6xx/R7xx */
2345 bool r600_adjust_gprs(struct r600_context *rctx)
2346 {
2347 unsigned num_ps_gprs = rctx->ps_shader->current->shader.bc.ngpr;
2348 unsigned num_vs_gprs = rctx->vs_shader->current->shader.bc.ngpr;
2349 unsigned new_num_ps_gprs = num_ps_gprs;
2350 unsigned new_num_vs_gprs = num_vs_gprs;
2351 unsigned cur_num_ps_gprs = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2352 unsigned cur_num_vs_gprs = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2353 unsigned def_num_ps_gprs = rctx->default_ps_gprs;
2354 unsigned def_num_vs_gprs = rctx->default_vs_gprs;
2355 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
2356 /* hardware will reserve twice num_clause_temp_gprs */
2357 unsigned max_gprs = def_num_ps_gprs + def_num_vs_gprs + def_num_clause_temp_gprs * 2;
2358 unsigned tmp;
2359
2360 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2361 if (new_num_ps_gprs > cur_num_ps_gprs || new_num_vs_gprs > cur_num_vs_gprs) {
2362 /* try to use switch back to default */
2363 if (new_num_ps_gprs > def_num_ps_gprs || new_num_vs_gprs > def_num_vs_gprs) {
2364 /* always privilege vs stage so that at worst we have the
2365 * pixel stage producing wrong output (not the vertex
2366 * stage) */
2367 new_num_ps_gprs = max_gprs - (new_num_vs_gprs + def_num_clause_temp_gprs * 2);
2368 new_num_vs_gprs = num_vs_gprs;
2369 } else {
2370 new_num_ps_gprs = def_num_ps_gprs;
2371 new_num_vs_gprs = def_num_vs_gprs;
2372 }
2373 } else {
2374 return true;
2375 }
2376
2377 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2378 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2379 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2380 * it will lockup. So in this case just discard the draw command
2381 * and don't change the current gprs repartitions.
2382 */
2383 if (num_ps_gprs > new_num_ps_gprs || num_vs_gprs > new_num_vs_gprs) {
2384 R600_ERR("ps & vs shader require too many register (%d + %d) "
2385 "for a combined maximum of %d\n",
2386 num_ps_gprs, num_vs_gprs, max_gprs);
2387 return false;
2388 }
2389
2390 /* in some case we endup recomputing the current value */
2391 tmp = S_008C04_NUM_PS_GPRS(new_num_ps_gprs) |
2392 S_008C04_NUM_VS_GPRS(new_num_vs_gprs) |
2393 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2394 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp) {
2395 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2396 rctx->config_state.atom.dirty = true;
2397 rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
2398 }
2399 return true;
2400 }
2401
2402 void r600_init_atom_start_cs(struct r600_context *rctx)
2403 {
2404 int ps_prio;
2405 int vs_prio;
2406 int gs_prio;
2407 int es_prio;
2408 int num_ps_gprs;
2409 int num_vs_gprs;
2410 int num_gs_gprs;
2411 int num_es_gprs;
2412 int num_temp_gprs;
2413 int num_ps_threads;
2414 int num_vs_threads;
2415 int num_gs_threads;
2416 int num_es_threads;
2417 int num_ps_stack_entries;
2418 int num_vs_stack_entries;
2419 int num_gs_stack_entries;
2420 int num_es_stack_entries;
2421 enum radeon_family family;
2422 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2423 uint32_t tmp;
2424
2425 r600_init_command_buffer(cb, 256);
2426
2427 /* R6xx requires this packet at the start of each command buffer */
2428 if (rctx->chip_class == R600) {
2429 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2430 r600_store_value(cb, 0);
2431 }
2432 /* All asics require this one */
2433 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2434 r600_store_value(cb, 0x80000000);
2435 r600_store_value(cb, 0x80000000);
2436
2437 /* We're setting config registers here. */
2438 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2439 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2440
2441 family = rctx->family;
2442 ps_prio = 0;
2443 vs_prio = 1;
2444 gs_prio = 2;
2445 es_prio = 3;
2446 switch (family) {
2447 case CHIP_R600:
2448 num_ps_gprs = 192;
2449 num_vs_gprs = 56;
2450 num_temp_gprs = 4;
2451 num_gs_gprs = 0;
2452 num_es_gprs = 0;
2453 num_ps_threads = 136;
2454 num_vs_threads = 48;
2455 num_gs_threads = 4;
2456 num_es_threads = 4;
2457 num_ps_stack_entries = 128;
2458 num_vs_stack_entries = 128;
2459 num_gs_stack_entries = 0;
2460 num_es_stack_entries = 0;
2461 break;
2462 case CHIP_RV630:
2463 case CHIP_RV635:
2464 num_ps_gprs = 84;
2465 num_vs_gprs = 36;
2466 num_temp_gprs = 4;
2467 num_gs_gprs = 0;
2468 num_es_gprs = 0;
2469 num_ps_threads = 144;
2470 num_vs_threads = 40;
2471 num_gs_threads = 4;
2472 num_es_threads = 4;
2473 num_ps_stack_entries = 40;
2474 num_vs_stack_entries = 40;
2475 num_gs_stack_entries = 32;
2476 num_es_stack_entries = 16;
2477 break;
2478 case CHIP_RV610:
2479 case CHIP_RV620:
2480 case CHIP_RS780:
2481 case CHIP_RS880:
2482 default:
2483 num_ps_gprs = 84;
2484 num_vs_gprs = 36;
2485 num_temp_gprs = 4;
2486 num_gs_gprs = 0;
2487 num_es_gprs = 0;
2488 num_ps_threads = 136;
2489 num_vs_threads = 48;
2490 num_gs_threads = 4;
2491 num_es_threads = 4;
2492 num_ps_stack_entries = 40;
2493 num_vs_stack_entries = 40;
2494 num_gs_stack_entries = 32;
2495 num_es_stack_entries = 16;
2496 break;
2497 case CHIP_RV670:
2498 num_ps_gprs = 144;
2499 num_vs_gprs = 40;
2500 num_temp_gprs = 4;
2501 num_gs_gprs = 0;
2502 num_es_gprs = 0;
2503 num_ps_threads = 136;
2504 num_vs_threads = 48;
2505 num_gs_threads = 4;
2506 num_es_threads = 4;
2507 num_ps_stack_entries = 40;
2508 num_vs_stack_entries = 40;
2509 num_gs_stack_entries = 32;
2510 num_es_stack_entries = 16;
2511 break;
2512 case CHIP_RV770:
2513 num_ps_gprs = 192;
2514 num_vs_gprs = 56;
2515 num_temp_gprs = 4;
2516 num_gs_gprs = 0;
2517 num_es_gprs = 0;
2518 num_ps_threads = 188;
2519 num_vs_threads = 60;
2520 num_gs_threads = 0;
2521 num_es_threads = 0;
2522 num_ps_stack_entries = 256;
2523 num_vs_stack_entries = 256;
2524 num_gs_stack_entries = 0;
2525 num_es_stack_entries = 0;
2526 break;
2527 case CHIP_RV730:
2528 case CHIP_RV740:
2529 num_ps_gprs = 84;
2530 num_vs_gprs = 36;
2531 num_temp_gprs = 4;
2532 num_gs_gprs = 0;
2533 num_es_gprs = 0;
2534 num_ps_threads = 188;
2535 num_vs_threads = 60;
2536 num_gs_threads = 0;
2537 num_es_threads = 0;
2538 num_ps_stack_entries = 128;
2539 num_vs_stack_entries = 128;
2540 num_gs_stack_entries = 0;
2541 num_es_stack_entries = 0;
2542 break;
2543 case CHIP_RV710:
2544 num_ps_gprs = 192;
2545 num_vs_gprs = 56;
2546 num_temp_gprs = 4;
2547 num_gs_gprs = 0;
2548 num_es_gprs = 0;
2549 num_ps_threads = 144;
2550 num_vs_threads = 48;
2551 num_gs_threads = 0;
2552 num_es_threads = 0;
2553 num_ps_stack_entries = 128;
2554 num_vs_stack_entries = 128;
2555 num_gs_stack_entries = 0;
2556 num_es_stack_entries = 0;
2557 break;
2558 }
2559
2560 rctx->default_ps_gprs = num_ps_gprs;
2561 rctx->default_vs_gprs = num_vs_gprs;
2562 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2563
2564 /* SQ_CONFIG */
2565 tmp = 0;
2566 switch (family) {
2567 case CHIP_RV610:
2568 case CHIP_RV620:
2569 case CHIP_RS780:
2570 case CHIP_RS880:
2571 case CHIP_RV710:
2572 break;
2573 default:
2574 tmp |= S_008C00_VC_ENABLE(1);
2575 break;
2576 }
2577 tmp |= S_008C00_DX9_CONSTS(0);
2578 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2579 tmp |= S_008C00_PS_PRIO(ps_prio);
2580 tmp |= S_008C00_VS_PRIO(vs_prio);
2581 tmp |= S_008C00_GS_PRIO(gs_prio);
2582 tmp |= S_008C00_ES_PRIO(es_prio);
2583 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2584
2585 /* SQ_GPR_RESOURCE_MGMT_2 */
2586 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2587 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2588 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2589 r600_store_value(cb, tmp);
2590
2591 /* SQ_THREAD_RESOURCE_MGMT */
2592 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2593 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2594 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2595 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2596 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2597
2598 /* SQ_STACK_RESOURCE_MGMT_1 */
2599 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2600 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2601 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2602
2603 /* SQ_STACK_RESOURCE_MGMT_2 */
2604 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2605 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2606 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2607
2608 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2609
2610 if (rctx->chip_class >= R700) {
2611 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2612 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2613 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2614 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2615 } else {
2616 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2617 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2618 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2619 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2620 }
2621 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2622 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2623 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2624 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2625 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2626 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2627 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2628 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2629 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2630 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2631
2632 /* to avoid GPU doing any preloading of constant from random address */
2633 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2634 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2635 r600_store_value(cb, 0);
2636 r600_store_value(cb, 0);
2637 r600_store_value(cb, 0);
2638 r600_store_value(cb, 0);
2639 r600_store_value(cb, 0);
2640 r600_store_value(cb, 0);
2641 r600_store_value(cb, 0);
2642 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2643 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2644 r600_store_value(cb, 0);
2645 r600_store_value(cb, 0);
2646 r600_store_value(cb, 0);
2647 r600_store_value(cb, 0);
2648 r600_store_value(cb, 0);
2649 r600_store_value(cb, 0);
2650 r600_store_value(cb, 0);
2651
2652 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2653 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2654 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2655 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2656 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2657 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2658 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2659 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2660 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2661 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2662 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2663 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2664 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2665 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2666
2667 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2668 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2669 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2670
2671 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2672 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2673 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2674 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2675
2676 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2677
2678 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2679
2680 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2681
2682 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2683 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2684 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2685 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2686
2687 r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2688 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2689 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2690
2691 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2692 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2693
2694 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2695 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2696 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2697 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2698 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2699
2700 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2701 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2702 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2703
2704 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2705
2706 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2707 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2708
2709 if (rctx->chip_class >= R700) {
2710 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2711 }
2712
2713 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2714 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2715 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2716 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2717 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2718
2719 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2720 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2721 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2722
2723 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2724 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2725 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2726
2727 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2728 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2729 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2730
2731 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2732
2733 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2734 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2735 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2736
2737 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2738 r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2739
2740 if (rctx->chip_class == R700 && rctx->screen->has_streamout)
2741 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2742 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2743 if (rctx->screen->has_streamout) {
2744 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2745 }
2746
2747 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2748 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2749 }
2750
2751 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2752 {
2753 struct r600_context *rctx = (struct r600_context *)ctx;
2754 struct r600_pipe_state *rstate = &shader->rstate;
2755 struct r600_shader *rshader = &shader->shader;
2756 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2757 int pos_index = -1, face_index = -1;
2758 unsigned tmp, sid, ufi = 0;
2759 int need_linear = 0;
2760 unsigned z_export = 0, stencil_export = 0;
2761 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2762
2763 rstate->nregs = 0;
2764
2765 for (i = 0; i < rshader->ninput; i++) {
2766 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2767 pos_index = i;
2768 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2769 face_index = i;
2770
2771 sid = rshader->input[i].spi_sid;
2772
2773 tmp = S_028644_SEMANTIC(sid);
2774
2775 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2776 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2777 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2778 rctx->rasterizer && rctx->rasterizer->flatshade))
2779 tmp |= S_028644_FLAT_SHADE(1);
2780
2781 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2782 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2783 tmp |= S_028644_PT_SPRITE_TEX(1);
2784 }
2785
2786 if (rshader->input[i].centroid)
2787 tmp |= S_028644_SEL_CENTROID(1);
2788
2789 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2790 need_linear = 1;
2791 tmp |= S_028644_SEL_LINEAR(1);
2792 }
2793
2794 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2795 tmp);
2796 }
2797
2798 db_shader_control = 0;
2799 for (i = 0; i < rshader->noutput; i++) {
2800 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2801 z_export = 1;
2802 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2803 stencil_export = 1;
2804 }
2805 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2806 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2807 if (rshader->uses_kill)
2808 db_shader_control |= S_02880C_KILL_ENABLE(1);
2809
2810 exports_ps = 0;
2811 for (i = 0; i < rshader->noutput; i++) {
2812 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2813 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2814 exports_ps |= 1;
2815 }
2816 }
2817 num_cout = rshader->nr_ps_color_exports;
2818 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2819 if (!exports_ps) {
2820 /* always at least export 1 component per pixel */
2821 exports_ps = 2;
2822 }
2823
2824 shader->nr_ps_color_outputs = num_cout;
2825
2826 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2827 S_0286CC_PERSP_GRADIENT_ENA(1)|
2828 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2829 spi_input_z = 0;
2830 if (pos_index != -1) {
2831 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2832 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2833 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2834 S_0286CC_BARYC_SAMPLE_CNTL(1));
2835 spi_input_z |= 1;
2836 }
2837
2838 spi_ps_in_control_1 = 0;
2839 if (face_index != -1) {
2840 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2841 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2842 }
2843
2844 /* HW bug in original R600 */
2845 if (rctx->family == CHIP_R600)
2846 ufi = 1;
2847
2848 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2849 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2850 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2851 r600_pipe_state_add_reg_bo(rstate,
2852 R_028840_SQ_PGM_START_PS,
2853 0, shader->bo, RADEON_USAGE_READ);
2854 r600_pipe_state_add_reg(rstate,
2855 R_028850_SQ_PGM_RESOURCES_PS,
2856 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2857 S_028850_STACK_SIZE(rshader->bc.nstack) |
2858 S_028850_UNCACHED_FIRST_INST(ufi));
2859 r600_pipe_state_add_reg(rstate,
2860 R_028854_SQ_PGM_EXPORTS_PS,
2861 exports_ps);
2862 /* only set some bits here, the other bits are set in the dsa state */
2863 shader->db_shader_control = db_shader_control;
2864 shader->ps_depth_export = z_export | stencil_export;
2865
2866 shader->sprite_coord_enable = sprite_coord_enable;
2867 if (rctx->rasterizer)
2868 shader->flatshade = rctx->rasterizer->flatshade;
2869 }
2870
2871 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2872 {
2873 struct r600_context *rctx = (struct r600_context *)ctx;
2874 struct r600_pipe_state *rstate = &shader->rstate;
2875 struct r600_shader *rshader = &shader->shader;
2876 unsigned spi_vs_out_id[10] = {};
2877 unsigned i, tmp, nparams = 0;
2878
2879 /* clear previous register */
2880 rstate->nregs = 0;
2881
2882 for (i = 0; i < rshader->noutput; i++) {
2883 if (rshader->output[i].spi_sid) {
2884 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2885 spi_vs_out_id[nparams / 4] |= tmp;
2886 nparams++;
2887 }
2888 }
2889
2890 for (i = 0; i < 10; i++) {
2891 r600_pipe_state_add_reg(rstate,
2892 R_028614_SPI_VS_OUT_ID_0 + i * 4,
2893 spi_vs_out_id[i]);
2894 }
2895
2896 /* Certain attributes (position, psize, etc.) don't count as params.
2897 * VS is required to export at least one param and r600_shader_from_tgsi()
2898 * takes care of adding a dummy export.
2899 */
2900 if (nparams < 1)
2901 nparams = 1;
2902
2903 r600_pipe_state_add_reg(rstate,
2904 R_0286C4_SPI_VS_OUT_CONFIG,
2905 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2906 r600_pipe_state_add_reg(rstate,
2907 R_028868_SQ_PGM_RESOURCES_VS,
2908 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2909 S_028868_STACK_SIZE(rshader->bc.nstack));
2910 r600_pipe_state_add_reg_bo(rstate,
2911 R_028858_SQ_PGM_START_VS,
2912 0, shader->bo, RADEON_USAGE_READ);
2913
2914 shader->pa_cl_vs_out_cntl =
2915 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2916 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2917 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2918 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2919 }
2920
2921 void *r600_create_resolve_blend(struct r600_context *rctx)
2922 {
2923 struct pipe_blend_state blend;
2924 unsigned i;
2925
2926 memset(&blend, 0, sizeof(blend));
2927 blend.independent_blend_enable = true;
2928 for (i = 0; i < 2; i++) {
2929 blend.rt[i].colormask = 0xf;
2930 blend.rt[i].blend_enable = 1;
2931 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2932 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2933 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2934 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2935 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2936 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2937 }
2938 return r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2939 }
2940
2941 void *r700_create_resolve_blend(struct r600_context *rctx)
2942 {
2943 struct pipe_blend_state blend;
2944
2945 memset(&blend, 0, sizeof(blend));
2946 blend.independent_blend_enable = true;
2947 blend.rt[0].colormask = 0xf;
2948 return r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2949 }
2950
2951 void *r600_create_decompress_blend(struct r600_context *rctx)
2952 {
2953 struct pipe_blend_state blend;
2954
2955 memset(&blend, 0, sizeof(blend));
2956 blend.independent_blend_enable = true;
2957 blend.rt[0].colormask = 0xf;
2958 return r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2959 }
2960
2961 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2962 {
2963 struct pipe_depth_stencil_alpha_state dsa;
2964 boolean quirk = false;
2965
2966 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2967 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2968 quirk = true;
2969
2970 memset(&dsa, 0, sizeof(dsa));
2971
2972 if (quirk) {
2973 dsa.depth.enabled = 1;
2974 dsa.depth.func = PIPE_FUNC_LEQUAL;
2975 dsa.stencil[0].enabled = 1;
2976 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2977 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2978 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2979 dsa.stencil[0].writemask = 0xff;
2980 }
2981
2982 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2983 }
2984
2985 void r600_update_db_shader_control(struct r600_context * rctx)
2986 {
2987 bool dual_export = rctx->framebuffer.export_16bpc &&
2988 !rctx->ps_shader->current->ps_depth_export;
2989
2990 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2991 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2992
2993 /* When alpha test is enabled we can't trust the hw to make the proper
2994 * decision on the order in which ztest should be run related to fragment
2995 * shader execution.
2996 *
2997 * If alpha test is enabled perform z test after fragment. RE_Z (early
2998 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2999 */
3000 if (rctx->alphatest_state.sx_alpha_test_control) {
3001 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3002 } else {
3003 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3004 }
3005
3006 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3007 rctx->db_misc_state.db_shader_control = db_shader_control;
3008 rctx->db_misc_state.atom.dirty = true;
3009 }
3010 }
3011
3012 static INLINE unsigned r600_array_mode(unsigned mode)
3013 {
3014 switch (mode) {
3015 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
3016 break;
3017 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
3018 break;
3019 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
3020 default:
3021 case RADEON_SURF_MODE_LINEAR: return V_0280A0_ARRAY_LINEAR_GENERAL;
3022 }
3023 }
3024
3025 static boolean r600_dma_copy_tile(struct r600_context *rctx,
3026 struct pipe_resource *dst,
3027 unsigned dst_level,
3028 unsigned dst_x,
3029 unsigned dst_y,
3030 unsigned dst_z,
3031 struct pipe_resource *src,
3032 unsigned src_level,
3033 unsigned src_x,
3034 unsigned src_y,
3035 unsigned src_z,
3036 unsigned copy_height,
3037 unsigned pitch,
3038 unsigned bpp)
3039 {
3040 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
3041 struct r600_texture *rsrc = (struct r600_texture*)src;
3042 struct r600_texture *rdst = (struct r600_texture*)dst;
3043 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3044 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3045 uint64_t base, addr;
3046
3047 /* make sure that the dma ring is only one active */
3048 rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
3049
3050 dst_mode = rdst->surface.level[dst_level].mode;
3051 src_mode = rsrc->surface.level[src_level].mode;
3052 /* downcast linear aligned to linear to simplify test */
3053 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3054 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3055 assert(dst_mode != src_mode);
3056
3057 y = 0;
3058 lbpp = util_logbase2(bpp);
3059 pitch_tile_max = ((pitch / bpp) >> 3) - 1;
3060
3061 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
3062 /* T2L */
3063 array_mode = r600_array_mode(src_mode);
3064 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) >> 6;
3065 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3066 /* linear height must be the same as the slice tile max height, it's ok even
3067 * if the linear destination/source have smaller heigh as the size of the
3068 * dma packet will be using the copy_height which is always smaller or equal
3069 * to the linear height
3070 */
3071 height = rsrc->surface.level[src_level].npix_y;
3072 detile = 1;
3073 x = src_x;
3074 y = src_y;
3075 z = src_z;
3076 base = rsrc->surface.level[src_level].offset;
3077 addr = rdst->surface.level[dst_level].offset;
3078 addr += rdst->surface.level[dst_level].slice_size * dst_z;
3079 addr += dst_y * pitch + dst_x * bpp;
3080 } else {
3081 /* L2T */
3082 array_mode = r600_array_mode(dst_mode);
3083 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) >> 6;
3084 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3085 /* linear height must be the same as the slice tile max height, it's ok even
3086 * if the linear destination/source have smaller heigh as the size of the
3087 * dma packet will be using the copy_height which is always smaller or equal
3088 * to the linear height
3089 */
3090 height = rdst->surface.level[dst_level].npix_y;
3091 detile = 0;
3092 x = dst_x;
3093 y = dst_y;
3094 z = dst_z;
3095 base = rdst->surface.level[dst_level].offset;
3096 addr = rsrc->surface.level[src_level].offset;
3097 addr += rsrc->surface.level[src_level].slice_size * src_z;
3098 addr += src_y * pitch + src_x * bpp;
3099 }
3100 /* check that we are in dw/base alignment constraint */
3101 if ((addr & 0x3) || (base & 0xff)) {
3102 return FALSE;
3103 }
3104
3105 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
3106 * line in the blit. Compute max 8 line we can copy in the size limit
3107 */
3108 cheight = ((0x0000ffff << 2) / pitch) & 0xfffffff8;
3109 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
3110 r600_need_dma_space(rctx, ncopy * 7);
3111
3112 for (i = 0; i < ncopy; i++) {
3113 cheight = cheight > copy_height ? copy_height : cheight;
3114 size = (cheight * pitch) >> 2;
3115 /* emit reloc before writting cs so that cs is always in consistent state */
3116 r600_context_bo_reloc(rctx, &rctx->rings.dma, &rsrc->resource, RADEON_USAGE_READ);
3117 r600_context_bo_reloc(rctx, &rctx->rings.dma, &rdst->resource, RADEON_USAGE_WRITE);
3118 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 1, 0, size);
3119 cs->buf[cs->cdw++] = base >> 8;
3120 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
3121 (lbpp << 24) | ((height - 1) << 10) |
3122 pitch_tile_max;
3123 cs->buf[cs->cdw++] = (slice_tile_max << 12) | (z << 0);
3124 cs->buf[cs->cdw++] = (x << 3) | (y << 17);
3125 cs->buf[cs->cdw++] = addr & 0xfffffffc;
3126 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
3127 copy_height -= cheight;
3128 addr += cheight * pitch;
3129 y += cheight;
3130 }
3131 return TRUE;
3132 }
3133
3134 boolean r600_dma_blit(struct pipe_context *ctx,
3135 struct pipe_resource *dst,
3136 unsigned dst_level,
3137 unsigned dst_x, unsigned dst_y, unsigned dst_z,
3138 struct pipe_resource *src,
3139 unsigned src_level,
3140 const struct pipe_box *src_box)
3141 {
3142 struct r600_context *rctx = (struct r600_context *)ctx;
3143 struct r600_texture *rsrc = (struct r600_texture*)src;
3144 struct r600_texture *rdst = (struct r600_texture*)dst;
3145 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3146 unsigned src_w, dst_w;
3147
3148 if (rctx->rings.dma.cs == NULL) {
3149 return FALSE;
3150 }
3151 if (src->format != dst->format) {
3152 return FALSE;
3153 }
3154
3155 bpp = rdst->surface.bpe;
3156 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
3157 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
3158 src_w = rsrc->surface.level[src_level].npix_x;
3159 dst_w = rdst->surface.level[dst_level].npix_x;
3160 copy_height = src_box->height / rsrc->surface.blk_h;
3161
3162 dst_mode = rdst->surface.level[dst_level].mode;
3163 src_mode = rsrc->surface.level[src_level].mode;
3164 /* downcast linear aligned to linear to simplify test */
3165 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3166 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3167
3168 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3169 /* strick requirement on r6xx/r7xx */
3170 return FALSE;
3171 }
3172 /* lot of constraint on alignment this should capture them all */
3173 if ((src_pitch & 0x7) || (src_box->y & 0x7) || (dst_y & 0x7)) {
3174 return FALSE;
3175 }
3176
3177 if (src_mode == dst_mode) {
3178 uint64_t dst_offset, src_offset, size;
3179
3180 /* simple dma blit would do NOTE code here assume :
3181 * src_box.x/y == 0
3182 * dst_x/y == 0
3183 * dst_pitch == src_pitch
3184 */
3185 src_offset= rsrc->surface.level[src_level].offset;
3186 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3187 src_offset += src_box->y * src_pitch + src_box->x * bpp;
3188 dst_offset = rdst->surface.level[dst_level].offset;
3189 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3190 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3191 size = src_box->height * src_pitch;
3192 /* must be dw aligned */
3193 if ((dst_offset & 0x3) || (src_offset & 0x3) || (size & 0x3)) {
3194 return FALSE;
3195 }
3196 r600_dma_copy(rctx, dst, src, dst_offset, src_offset, size);
3197 } else {
3198 return r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3199 src, src_level, src_box->x, src_box->y, src_box->z,
3200 copy_height, dst_pitch, bpp);
3201 }
3202 return TRUE;
3203 }