projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: switch btw flat/linear interpolation
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include <stdio.h>
27 #include "util/u_inlines.h"
28 #include "util/u_format.h"
29 #include "util/u_memory.h"
30 #include "r600_screen.h"
31 #include "r600_context.h"
32 #include "r600_resource.h"
33 #include "r600d.h"
34
35 static void *r600_create_blend_state(struct pipe_context *ctx,
36 const struct pipe_blend_state *state)
37 {
38 struct r600_context *rctx = r600_context(ctx);
39
40 return r600_context_state(rctx, pipe_blend_type, state);
41 }
42
43 static void *r600_create_dsa_state(struct pipe_context *ctx,
44 const struct pipe_depth_stencil_alpha_state *state)
45 {
46 struct r600_context *rctx = r600_context(ctx);
47
48 return r600_context_state(rctx, pipe_dsa_type, state);
49 }
50
51 static void *r600_create_rs_state(struct pipe_context *ctx,
52 const struct pipe_rasterizer_state *state)
53 {
54 struct r600_context *rctx = r600_context(ctx);
55
56 return r600_context_state(rctx, pipe_rasterizer_type, state);
57 }
58
59 static void *r600_create_sampler_state(struct pipe_context *ctx,
60 const struct pipe_sampler_state *state)
61 {
62 struct r600_context *rctx = r600_context(ctx);
63
64 return r600_context_state(rctx, pipe_sampler_type, state);
65 }
66
67 static void r600_sampler_view_destroy(struct pipe_context *ctx,
68 struct pipe_sampler_view *state)
69 {
70 struct r600_context_state *rstate = (struct r600_context_state *)state;
71
72 r600_context_state_decref(rstate);
73 }
74
75 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
76 struct pipe_resource *texture,
77 const struct pipe_sampler_view *state)
78 {
79 struct r600_context *rctx = r600_context(ctx);
80 struct r600_context_state *rstate;
81
82 rstate = r600_context_state(rctx, pipe_sampler_type, state);
83 pipe_reference(NULL, &texture->reference);
84 rstate->state.sampler_view.texture = texture;
85 rstate->state.sampler_view.reference.count = 1;
86 return &rstate->state.sampler_view;
87 }
88
89 static void *r600_create_shader_state(struct pipe_context *ctx,
90 const struct pipe_shader_state *state)
91 {
92 struct r600_context *rctx = r600_context(ctx);
93
94 return r600_context_state(rctx, pipe_shader_type, state);
95 }
96
97 static void *r600_create_vertex_elements(struct pipe_context *ctx,
98 unsigned count,
99 const struct pipe_vertex_element *elements)
100 {
101 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
102
103 assert(count < 32);
104 v->count = count;
105 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
106 v->refcount = 1;
107 return v;
108 }
109
110 static void r600_bind_state(struct pipe_context *ctx, void *state)
111 {
112 struct r600_context *rctx = r600_context(ctx);
113 struct r600_context_state *rstate = (struct r600_context_state *)state;
114
115 if (state == NULL)
116 return;
117 switch (rstate->type) {
118 case pipe_rasterizer_type:
119 rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
120 rctx->rasterizer = r600_context_state_incref(rstate);
121 break;
122 case pipe_poly_stipple_type:
123 rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple);
124 rctx->poly_stipple = r600_context_state_incref(rstate);
125 break;
126 case pipe_scissor_type:
127 rctx->scissor = r600_context_state_decref(rctx->scissor);
128 rctx->scissor = r600_context_state_incref(rstate);
129 break;
130 case pipe_clip_type:
131 rctx->clip = r600_context_state_decref(rctx->clip);
132 rctx->clip = r600_context_state_incref(rstate);
133 break;
134 case pipe_depth_type:
135 rctx->depth = r600_context_state_decref(rctx->depth);
136 rctx->depth = r600_context_state_incref(rstate);
137 break;
138 case pipe_stencil_type:
139 rctx->stencil = r600_context_state_decref(rctx->stencil);
140 rctx->stencil = r600_context_state_incref(rstate);
141 break;
142 case pipe_alpha_type:
143 rctx->alpha = r600_context_state_decref(rctx->alpha);
144 rctx->alpha = r600_context_state_incref(rstate);
145 break;
146 case pipe_dsa_type:
147 rctx->dsa = r600_context_state_decref(rctx->dsa);
148 rctx->dsa = r600_context_state_incref(rstate);
149 break;
150 case pipe_blend_type:
151 rctx->blend = r600_context_state_decref(rctx->blend);
152 rctx->blend = r600_context_state_incref(rstate);
153 break;
154 case pipe_framebuffer_type:
155 rctx->framebuffer = r600_context_state_decref(rctx->framebuffer);
156 rctx->framebuffer = r600_context_state_incref(rstate);
157 break;
158 case pipe_stencil_ref_type:
159 rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref);
160 rctx->stencil_ref = r600_context_state_incref(rstate);
161 break;
162 case pipe_viewport_type:
163 rctx->viewport = r600_context_state_decref(rctx->viewport);
164 rctx->viewport = r600_context_state_incref(rstate);
165 break;
166 case pipe_shader_type:
167 case pipe_sampler_type:
168 case pipe_sampler_view_type:
169 default:
170 R600_ERR("invalid type %d\n", rstate->type);
171 return;
172 }
173 }
174
175 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
176 {
177 struct r600_context *rctx = r600_context(ctx);
178 struct r600_context_state *rstate = (struct r600_context_state *)state;
179
180 rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
181 rctx->ps_shader = r600_context_state_incref(rstate);
182 }
183
184 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
185 {
186 struct r600_context *rctx = r600_context(ctx);
187 struct r600_context_state *rstate = (struct r600_context_state *)state;
188
189 rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
190 rctx->vs_shader = r600_context_state_incref(rstate);
191 }
192
193 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
194 {
195 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
196
197 if (v == NULL)
198 return;
199 if (--v->refcount)
200 return;
201 free(v);
202 }
203
204 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
205 {
206 struct r600_context *rctx = r600_context(ctx);
207 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
208
209 r600_delete_vertex_element(ctx, rctx->vertex_elements);
210 rctx->vertex_elements = v;
211 if (v) {
212 v->refcount++;
213 }
214 }
215
216 static void r600_bind_ps_sampler(struct pipe_context *ctx,
217 unsigned count, void **states)
218 {
219 struct r600_context *rctx = r600_context(ctx);
220 struct r600_context_state *rstate;
221 unsigned i;
222
223 for (i = 0; i < rctx->ps_nsampler; i++) {
224 rctx->ps_sampler[i] = r600_context_state_decref(rctx->ps_sampler[i]);
225 }
226 for (i = 0; i < count; i++) {
227 rstate = (struct r600_context_state *)states[i];
228 rctx->ps_sampler[i] = r600_context_state_incref(rstate);
229 }
230 rctx->ps_nsampler = count;
231 }
232
233 static void r600_bind_vs_sampler(struct pipe_context *ctx,
234 unsigned count, void **states)
235 {
236 struct r600_context *rctx = r600_context(ctx);
237 struct r600_context_state *rstate;
238 unsigned i;
239
240 for (i = 0; i < rctx->vs_nsampler; i++) {
241 rctx->vs_sampler[i] = r600_context_state_decref(rctx->vs_sampler[i]);
242 }
243 for (i = 0; i < count; i++) {
244 rstate = (struct r600_context_state *)states[i];
245 rctx->vs_sampler[i] = r600_context_state_incref(rstate);
246 }
247 rctx->vs_nsampler = count;
248 }
249
250 static void r600_delete_state(struct pipe_context *ctx, void *state)
251 {
252 struct r600_context_state *rstate = (struct r600_context_state *)state;
253
254 r600_context_state_decref(rstate);
255 }
256
257 static void r600_set_blend_color(struct pipe_context *ctx,
258 const struct pipe_blend_color *color)
259 {
260 }
261
262 static void r600_set_clip_state(struct pipe_context *ctx,
263 const struct pipe_clip_state *state)
264 {
265 }
266
267 static void r600_set_constant_buffer(struct pipe_context *ctx,
268 uint shader, uint index,
269 struct pipe_resource *buffer)
270 {
271 struct r600_screen *rscreen = r600_screen(ctx->screen);
272 struct r600_context *rctx = r600_context(ctx);
273 unsigned nconstant = 0, i, type, id;
274 struct radeon_state *rstate;
275 struct pipe_transfer *transfer;
276 u32 *ptr;
277
278 switch (shader) {
279 case PIPE_SHADER_VERTEX:
280 id = R600_VS_CONSTANT;
281 type = R600_VS_CONSTANT_TYPE;
282 break;
283 case PIPE_SHADER_FRAGMENT:
284 id = R600_PS_CONSTANT;
285 type = R600_PS_CONSTANT_TYPE;
286 break;
287 default:
288 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, shader);
289 return;
290 }
291 if (buffer && buffer->width0 > 0) {
292 nconstant = buffer->width0 / 16;
293 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
294 if (ptr == NULL)
295 return;
296 for (i = 0; i < nconstant; i++) {
297 rstate = radeon_state(rscreen->rw, type, id + i);
298 if (rstate == NULL)
299 return;
300 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
301 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
302 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
303 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
304 if (radeon_state_pm4(rstate))
305 return;
306 if (radeon_draw_set_new(rctx->draw, rstate))
307 return;
308 }
309 pipe_buffer_unmap(ctx, buffer, transfer);
310 }
311 }
312
313 static void r600_set_ps_sampler_view(struct pipe_context *ctx,
314 unsigned count,
315 struct pipe_sampler_view **views)
316 {
317 struct r600_context *rctx = r600_context(ctx);
318 struct r600_context_state *rstate;
319 unsigned i;
320
321 for (i = 0; i < rctx->ps_nsampler_view; i++) {
322 rctx->ps_sampler_view[i] = r600_context_state_decref(rctx->ps_sampler_view[i]);
323 }
324 for (i = 0; i < count; i++) {
325 rstate = (struct r600_context_state *)views[i];
326 rctx->ps_sampler_view[i] = r600_context_state_incref(rstate);
327 }
328 rctx->ps_nsampler_view = count;
329 }
330
331 static void r600_set_vs_sampler_view(struct pipe_context *ctx,
332 unsigned count,
333 struct pipe_sampler_view **views)
334 {
335 struct r600_context *rctx = r600_context(ctx);
336 struct r600_context_state *rstate;
337 unsigned i;
338
339 for (i = 0; i < rctx->vs_nsampler_view; i++) {
340 rctx->vs_sampler_view[i] = r600_context_state_decref(rctx->vs_sampler_view[i]);
341 }
342 for (i = 0; i < count; i++) {
343 rstate = (struct r600_context_state *)views[i];
344 rctx->vs_sampler_view[i] = r600_context_state_incref(rstate);
345 }
346 rctx->vs_nsampler_view = count;
347 }
348
349 static void r600_set_framebuffer_state(struct pipe_context *ctx,
350 const struct pipe_framebuffer_state *state)
351 {
352 struct r600_context *rctx = r600_context(ctx);
353 struct r600_context_state *rstate;
354
355 rstate = r600_context_state(rctx, pipe_framebuffer_type, state);
356 r600_bind_state(ctx, rstate);
357 }
358
359 static void r600_set_polygon_stipple(struct pipe_context *ctx,
360 const struct pipe_poly_stipple *state)
361 {
362 }
363
364 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
365 {
366 }
367
368 static void r600_set_scissor_state(struct pipe_context *ctx,
369 const struct pipe_scissor_state *state)
370 {
371 struct r600_context *rctx = r600_context(ctx);
372 struct r600_context_state *rstate;
373
374 rstate = r600_context_state(rctx, pipe_scissor_type, state);
375 r600_bind_state(ctx, rstate);
376 }
377
378 static void r600_set_stencil_ref(struct pipe_context *ctx,
379 const struct pipe_stencil_ref *state)
380 {
381 struct r600_context *rctx = r600_context(ctx);
382 struct r600_context_state *rstate;
383
384 rstate = r600_context_state(rctx, pipe_stencil_ref_type, state);
385 r600_bind_state(ctx, rstate);
386 }
387
388 static void r600_set_vertex_buffers(struct pipe_context *ctx,
389 unsigned count,
390 const struct pipe_vertex_buffer *buffers)
391 {
392 struct r600_context *rctx = r600_context(ctx);
393 unsigned i;
394
395 for (i = 0; i < rctx->nvertex_buffer; i++) {
396 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
397 }
398 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
399 for (i = 0; i < count; i++) {
400 rctx->vertex_buffer[i].buffer = NULL;
401 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
402 }
403 rctx->nvertex_buffer = count;
404 }
405
406 static void r600_set_viewport_state(struct pipe_context *ctx,
407 const struct pipe_viewport_state *state)
408 {
409 struct r600_context *rctx = r600_context(ctx);
410 struct r600_context_state *rstate;
411
412 rstate = r600_context_state(rctx, pipe_viewport_type, state);
413 r600_bind_state(ctx, rstate);
414 }
415
416 void r600_init_state_functions(struct r600_context *rctx)
417 {
418 rctx->context.create_blend_state = r600_create_blend_state;
419 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
420 rctx->context.create_fs_state = r600_create_shader_state;
421 rctx->context.create_rasterizer_state = r600_create_rs_state;
422 rctx->context.create_sampler_state = r600_create_sampler_state;
423 rctx->context.create_sampler_view = r600_create_sampler_view;
424 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
425 rctx->context.create_vs_state = r600_create_shader_state;
426 rctx->context.bind_blend_state = r600_bind_state;
427 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
428 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
429 rctx->context.bind_fs_state = r600_bind_ps_shader;
430 rctx->context.bind_rasterizer_state = r600_bind_state;
431 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
432 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
433 rctx->context.bind_vs_state = r600_bind_vs_shader;
434 rctx->context.delete_blend_state = r600_delete_state;
435 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
436 rctx->context.delete_fs_state = r600_delete_state;
437 rctx->context.delete_rasterizer_state = r600_delete_state;
438 rctx->context.delete_sampler_state = r600_delete_state;
439 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
440 rctx->context.delete_vs_state = r600_delete_state;
441 rctx->context.set_blend_color = r600_set_blend_color;
442 rctx->context.set_clip_state = r600_set_clip_state;
443 rctx->context.set_constant_buffer = r600_set_constant_buffer;
444 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
445 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
446 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
447 rctx->context.set_sample_mask = r600_set_sample_mask;
448 rctx->context.set_scissor_state = r600_set_scissor_state;
449 rctx->context.set_stencil_ref = r600_set_stencil_ref;
450 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
451 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
452 rctx->context.set_viewport_state = r600_set_viewport_state;
453 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
454 }
455
456 struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate)
457 {
458 if (rstate == NULL)
459 return NULL;
460 rstate->refcount++;
461 return rstate;
462 }
463
464 struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate)
465 {
466 unsigned i;
467
468 if (rstate == NULL)
469 return NULL;
470 if (--rstate->refcount)
471 return NULL;
472 switch (rstate->type) {
473 case pipe_sampler_view_type:
474 pipe_resource_reference(&rstate->state.sampler_view.texture, NULL);
475 break;
476 case pipe_framebuffer_type:
477 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
478 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], NULL);
479 }
480 pipe_surface_reference(&rstate->state.framebuffer.zsbuf, NULL);
481 break;
482 case pipe_viewport_type:
483 case pipe_depth_type:
484 case pipe_rasterizer_type:
485 case pipe_poly_stipple_type:
486 case pipe_scissor_type:
487 case pipe_clip_type:
488 case pipe_stencil_type:
489 case pipe_alpha_type:
490 case pipe_dsa_type:
491 case pipe_blend_type:
492 case pipe_stencil_ref_type:
493 case pipe_shader_type:
494 case pipe_sampler_type:
495 break;
496 default:
497 R600_ERR("invalid type %d\n", rstate->type);
498 return NULL;
499 }
500 radeon_state_decref(rstate->rstate);
501 FREE(rstate);
502 return NULL;
503 }
504
505 struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state)
506 {
507 struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state);
508 const union pipe_states *states = state;
509 unsigned i;
510 int r;
511
512 if (rstate == NULL)
513 return NULL;
514 rstate->type = type;
515 rstate->refcount = 1;
516
517 switch (rstate->type) {
518 case pipe_sampler_view_type:
519 rstate->state.sampler_view = (*states).sampler_view;
520 rstate->state.sampler_view.texture = NULL;
521 break;
522 case pipe_framebuffer_type:
523 rstate->state.framebuffer = (*states).framebuffer;
524 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
525 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i],
526 (*states).framebuffer.cbufs[i]);
527 }
528 pipe_surface_reference(&rstate->state.framebuffer.zsbuf,
529 (*states).framebuffer.zsbuf);
530 break;
531 case pipe_viewport_type:
532 rstate->state.viewport = (*states).viewport;
533 break;
534 case pipe_depth_type:
535 rstate->state.depth = (*states).depth;
536 break;
537 case pipe_rasterizer_type:
538 rstate->state.rasterizer = (*states).rasterizer;
539 break;
540 case pipe_poly_stipple_type:
541 rstate->state.poly_stipple = (*states).poly_stipple;
542 break;
543 case pipe_scissor_type:
544 rstate->state.scissor = (*states).scissor;
545 break;
546 case pipe_clip_type:
547 rstate->state.clip = (*states).clip;
548 break;
549 case pipe_stencil_type:
550 rstate->state.stencil = (*states).stencil;
551 break;
552 case pipe_alpha_type:
553 rstate->state.alpha = (*states).alpha;
554 break;
555 case pipe_dsa_type:
556 rstate->state.dsa = (*states).dsa;
557 break;
558 case pipe_blend_type:
559 rstate->state.blend = (*states).blend;
560 break;
561 case pipe_stencil_ref_type:
562 rstate->state.stencil_ref = (*states).stencil_ref;
563 break;
564 case pipe_shader_type:
565 rstate->state.shader = (*states).shader;
566 r = r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens);
567 if (r) {
568 r600_context_state_decref(rstate);
569 return NULL;
570 }
571 break;
572 case pipe_sampler_type:
573 rstate->state.sampler = (*states).sampler;
574 break;
575 default:
576 R600_ERR("invalid type %d\n", rstate->type);
577 FREE(rstate);
578 return NULL;
579 }
580 return rstate;
581 }
582
583 static struct radeon_state *r600_blend(struct r600_context *rctx)
584 {
585 struct r600_screen *rscreen = rctx->screen;
586 struct radeon_state *rstate;
587
588 rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
589 if (rstate == NULL)
590 return NULL;
591 rstate->states[R600_BLEND__CB_BLEND_RED] = 0x00000000;
592 rstate->states[R600_BLEND__CB_BLEND_GREEN] = 0x00000000;
593 rstate->states[R600_BLEND__CB_BLEND_BLUE] = 0x00000000;
594 rstate->states[R600_BLEND__CB_BLEND_ALPHA] = 0x00000000;
595 rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00010001;
596 rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
597 rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
598 rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
599 rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
600 rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
601 rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
602 rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
603 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
604 if (radeon_state_pm4(rstate)) {
605 radeon_state_decref(rstate);
606 return NULL;
607 }
608 return rstate;
609 }
610
611 static struct radeon_state *r600_cb0(struct r600_context *rctx)
612 {
613 struct r600_screen *rscreen = rctx->screen;
614 struct r600_resource_texture *rtex;
615 struct r600_resource *rbuffer;
616 struct radeon_state *rstate;
617 const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
618 unsigned level = state->cbufs[0]->level;
619 unsigned pitch, slice;
620
621 rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, R600_CB0);
622 if (rstate == NULL)
623 return NULL;
624 rtex = (struct r600_resource_texture*)state->cbufs[0]->texture;
625 rbuffer = &rtex->resource;
626 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
627 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
628 rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
629 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
630 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
631 rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
632 rstate->nbo = 3;
633 pitch = rtex->pitch[level] / 8 - 1;
634 slice = rtex->pitch[level] * state->cbufs[0]->height / 64 - 1;
635 rstate->states[R600_CB0__CB_COLOR0_BASE] = 0x00000000;
636 rstate->states[R600_CB0__CB_COLOR0_INFO] = 0x08110068;
637 rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
638 S_028060_SLICE_TILE_MAX(slice);
639 rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
640 rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
641 rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
642 rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
643 if (radeon_state_pm4(rstate)) {
644 radeon_state_decref(rstate);
645 return NULL;
646 }
647 return rstate;
648 }
649
650 static struct radeon_state *r600_db(struct r600_context *rctx)
651 {
652 struct r600_screen *rscreen = rctx->screen;
653 struct r600_resource_texture *rtex;
654 struct r600_resource *rbuffer;
655 struct radeon_state *rstate;
656 const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
657 unsigned level = state->cbufs[0]->level;
658 unsigned pitch, slice;
659
660 if (state->zsbuf == NULL)
661 return NULL;
662
663 rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
664 if (rstate == NULL)
665 return NULL;
666
667 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
668 rbuffer = &rtex->resource;
669 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
670 rstate->nbo = 1;
671 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
672 level = state->zsbuf->level;
673 pitch = rtex->pitch[level] / 8 - 1;
674 slice = rtex->pitch[level] * state->zsbuf->height / 64 - 1;
675 rstate->states[R600_DB__DB_DEPTH_BASE] = 0x00000000;
676 rstate->states[R600_DB__DB_DEPTH_INFO] = 0x00010006;
677 rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
678 rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
679 rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
680 S_028000_SLICE_TILE_MAX(slice);
681 if (radeon_state_pm4(rstate)) {
682 radeon_state_decref(rstate);
683 return NULL;
684 }
685 return rstate;
686 }
687
688 static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
689 {
690 const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
691 struct r600_screen *rscreen = rctx->screen;
692 struct radeon_state *rstate;
693
694 rctx->flat_shade = state->flatshade;
695 rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
696 if (rstate == NULL)
697 return NULL;
698 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
699 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0x00000000;
700 rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080000;
701 rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] = 0x00000000;
702 rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
703 rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = 0x00080008;
704 rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x00000000;
705 rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
706 rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
707 rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
708 rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
709 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
710 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
711 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
712 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
713 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = 0x00000000;
714 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
715 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = 0x00000000;
716 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = 0x00000000;
717 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = 0x00000000;
718 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = 0x00000000;
719 if (radeon_state_pm4(rstate)) {
720 radeon_state_decref(rstate);
721 return NULL;
722 }
723 return rstate;
724 }
725
726 static struct radeon_state *r600_scissor(struct r600_context *rctx)
727 {
728 const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
729 struct r600_screen *rscreen = rctx->screen;
730 struct radeon_state *rstate;
731 u32 tl, br;
732
733 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
734 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
735 rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
736 if (rstate == NULL)
737 return NULL;
738 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
739 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
740 rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
741 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
742 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
743 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
744 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
745 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
746 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
747 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
748 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
749 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
750 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
751 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
752 rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
753 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
754 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
755 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
756 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
757 if (radeon_state_pm4(rstate)) {
758 radeon_state_decref(rstate);
759 return NULL;
760 }
761 return rstate;
762 }
763
764 static struct radeon_state *r600_viewport(struct r600_context *rctx)
765 {
766 const struct pipe_viewport_state *state = &rctx->viewport->state.viewport;
767 struct r600_screen *rscreen = rctx->screen;
768 struct radeon_state *rstate;
769
770 rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
771 if (rstate == NULL)
772 return NULL;
773 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
774 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
775 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
776 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
777 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
778 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
779 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
780 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
781 rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
782 if (radeon_state_pm4(rstate)) {
783 radeon_state_decref(rstate);
784 return NULL;
785 }
786 return rstate;
787 }
788
789 static struct radeon_state *r600_dsa(struct r600_context *rctx)
790 {
791 const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
792 struct r600_screen *rscreen = rctx->screen;
793 struct radeon_state *rstate;
794 unsigned db_depth_control;
795
796 rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
797 if (rstate == NULL)
798 return NULL;
799 db_depth_control = 0x00700700 | S_028800_Z_ENABLE(state->depth.enabled) | S_028800_Z_WRITE_ENABLE(state->depth.writemask) | S_028800_ZFUNC(state->depth.func);
800
801 rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
802 rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
803 rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = 0x00000000;
804 rstate->states[R600_DSA__DB_STENCILREFMASK] = 0xFFFFFF00;
805 rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = 0xFFFFFF00;
806 rstate->states[R600_DSA__SX_ALPHA_REF] = 0x00000000;
807 rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
808 rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
809 rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
810 rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
811 rstate->states[R600_DSA__DB_SHADER_CONTROL] = 0x00000210;
812 rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060;
813 rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
814 rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
815 rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
816 rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
817 if (radeon_state_pm4(rstate)) {
818 radeon_state_decref(rstate);
819 return NULL;
820 }
821 return rstate;
822 }
823
824 static inline unsigned r600_tex_wrap(unsigned wrap)
825 {
826 switch (wrap) {
827 default:
828 case PIPE_TEX_WRAP_REPEAT:
829 return V_03C000_SQ_TEX_WRAP;
830 case PIPE_TEX_WRAP_CLAMP:
831 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
832 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
833 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
834 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
835 return V_03C000_SQ_TEX_CLAMP_BORDER;
836 case PIPE_TEX_WRAP_MIRROR_REPEAT:
837 return V_03C000_SQ_TEX_MIRROR;
838 case PIPE_TEX_WRAP_MIRROR_CLAMP:
839 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
840 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
841 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
842 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
843 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
844 }
845 }
846
847 static inline unsigned r600_tex_filter(unsigned filter)
848 {
849 switch (filter) {
850 default:
851 case PIPE_TEX_FILTER_NEAREST:
852 return V_03C000_SQ_TEX_XY_FILTER_POINT;
853 case PIPE_TEX_FILTER_LINEAR:
854 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
855 }
856 }
857
858 static inline unsigned r600_tex_mipfilter(unsigned filter)
859 {
860 switch (filter) {
861 case PIPE_TEX_MIPFILTER_NEAREST:
862 return V_03C000_SQ_TEX_Z_FILTER_POINT;
863 case PIPE_TEX_MIPFILTER_LINEAR:
864 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
865 default:
866 case PIPE_TEX_MIPFILTER_NONE:
867 return V_03C000_SQ_TEX_Z_FILTER_NONE;
868 }
869 }
870
871 static inline unsigned r600_tex_compare(unsigned compare)
872 {
873 switch (compare) {
874 default:
875 case PIPE_FUNC_NEVER:
876 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
877 case PIPE_FUNC_LESS:
878 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
879 case PIPE_FUNC_EQUAL:
880 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
881 case PIPE_FUNC_LEQUAL:
882 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
883 case PIPE_FUNC_GREATER:
884 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
885 case PIPE_FUNC_NOTEQUAL:
886 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
887 case PIPE_FUNC_GEQUAL:
888 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
889 case PIPE_FUNC_ALWAYS:
890 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
891 }
892 }
893
894 static struct radeon_state *r600_sampler(struct r600_context *rctx,
895 const struct pipe_sampler_state *state,
896 unsigned id)
897 {
898 struct r600_screen *rscreen = rctx->screen;
899 struct radeon_state *rstate;
900
901 rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, id);
902 if (rstate == NULL)
903 return NULL;
904 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
905 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
906 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
907 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
908 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
909 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
910 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
911 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func));
912 /* FIXME LOD it depends on texture base level ... */
913 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
914 S_03C004_MIN_LOD(0) |
915 S_03C004_MAX_LOD(0) |
916 S_03C004_LOD_BIAS(0);
917 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
918 if (radeon_state_pm4(rstate)) {
919 radeon_state_decref(rstate);
920 return NULL;
921 }
922 return rstate;
923 }
924
925 static inline unsigned r600_tex_swizzle(unsigned swizzle)
926 {
927 switch (swizzle) {
928 case PIPE_SWIZZLE_RED:
929 return V_038010_SQ_SEL_X;
930 case PIPE_SWIZZLE_GREEN:
931 return V_038010_SQ_SEL_Y;
932 case PIPE_SWIZZLE_BLUE:
933 return V_038010_SQ_SEL_Z;
934 case PIPE_SWIZZLE_ALPHA:
935 return V_038010_SQ_SEL_W;
936 case PIPE_SWIZZLE_ZERO:
937 return V_038010_SQ_SEL_0;
938 default:
939 case PIPE_SWIZZLE_ONE:
940 return V_038010_SQ_SEL_1;
941 }
942 }
943
944 static inline unsigned r600_format_type(unsigned format_type)
945 {
946 switch (format_type) {
947 default:
948 case UTIL_FORMAT_TYPE_UNSIGNED:
949 return V_038010_SQ_FORMAT_COMP_UNSIGNED;
950 case UTIL_FORMAT_TYPE_SIGNED:
951 return V_038010_SQ_FORMAT_COMP_SIGNED;
952 case UTIL_FORMAT_TYPE_FIXED:
953 return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED;
954 }
955 }
956
957 static inline unsigned r600_tex_dim(unsigned dim)
958 {
959 switch (dim) {
960 default:
961 case PIPE_TEXTURE_1D:
962 return V_038000_SQ_TEX_DIM_1D;
963 case PIPE_TEXTURE_2D:
964 return V_038000_SQ_TEX_DIM_2D;
965 case PIPE_TEXTURE_3D:
966 return V_038000_SQ_TEX_DIM_3D;
967 case PIPE_TEXTURE_CUBE:
968 return V_038000_SQ_TEX_DIM_CUBEMAP;
969 }
970 }
971
972 static struct radeon_state *r600_resource(struct r600_context *rctx,
973 const struct pipe_sampler_view *view,
974 unsigned id)
975 {
976 struct r600_screen *rscreen = rctx->screen;
977 const struct util_format_description *desc;
978 struct r600_resource_texture *tmp;
979 struct r600_resource *rbuffer;
980 struct radeon_state *rstate;
981 unsigned format;
982
983 if (r600_conv_pipe_format(view->texture->format, &format))
984 return NULL;
985 desc = util_format_description(view->texture->format);
986 assert(desc == NULL);
987 rstate = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, id);
988 if (rstate == NULL) {
989 return NULL;
990 }
991 tmp = (struct r600_resource_texture*)view->texture;
992 rbuffer = &tmp->resource;
993 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
994 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
995 rstate->nbo = 2;
996 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
997 rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
998 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
999 rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
1000
1001 /* FIXME properly handle first level != 0 */
1002 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
1003 S_038000_DIM(r600_tex_dim(view->texture->target)) |
1004 S_038000_PITCH((tmp->pitch[0] / 8) - 1) |
1005 S_038000_TEX_WIDTH(view->texture->width0 - 1);
1006 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
1007 S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
1008 S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
1009 S_038004_DATA_FORMAT(format);
1010 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = 0;
1011 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
1012 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
1013 S_038010_FORMAT_COMP_X(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
1014 S_038010_FORMAT_COMP_Y(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
1015 S_038010_FORMAT_COMP_Z(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
1016 S_038010_FORMAT_COMP_W(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
1017 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
1018 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
1019 S_038010_REQUEST_SIZE(1) |
1020 S_038010_DST_SEL_X(r600_tex_swizzle(view->swizzle_r)) |
1021 S_038010_DST_SEL_Y(r600_tex_swizzle(view->swizzle_g)) |
1022 S_038010_DST_SEL_Z(r600_tex_swizzle(view->swizzle_b)) |
1023 S_038010_DST_SEL_W(r600_tex_swizzle(view->swizzle_a)) |
1024 S_038010_BASE_LEVEL(view->first_level);
1025 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
1026 S_038014_LAST_LEVEL(view->last_level) |
1027 S_038014_BASE_ARRAY(0) |
1028 S_038014_LAST_ARRAY(0);
1029 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
1030 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
1031 if (radeon_state_pm4(rstate)) {
1032 radeon_state_decref(rstate);
1033 return NULL;
1034 }
1035 return rstate;
1036 }
1037
1038 int r600_context_hw_states(struct r600_context *rctx)
1039 {
1040 unsigned i;
1041 int r;
1042
1043 /* free previous TODO determine what need to be updated, what
1044 * doesn't
1045 */
1046 //radeon_state_decref(rctx->hw_states.config);
1047 //radeon_state_decref(rctx->hw_states.cb_cntl);
1048 radeon_state_decref(rctx->hw_states.db);
1049 radeon_state_decref(rctx->hw_states.rasterizer);
1050 radeon_state_decref(rctx->hw_states.scissor);
1051 radeon_state_decref(rctx->hw_states.dsa);
1052 radeon_state_decref(rctx->hw_states.blend);
1053 radeon_state_decref(rctx->hw_states.viewport);
1054 radeon_state_decref(rctx->hw_states.cb0);
1055 for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
1056 radeon_state_decref(rctx->hw_states.ps_resource[i]);
1057 rctx->hw_states.ps_resource[i] = NULL;
1058 }
1059 rctx->hw_states.ps_nresource = 0;
1060 for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
1061 radeon_state_decref(rctx->hw_states.ps_sampler[i]);
1062 rctx->hw_states.ps_sampler[i] = NULL;
1063 }
1064 rctx->hw_states.ps_nsampler = 0;
1065
1066 /* build new states */
1067 rctx->hw_states.rasterizer = r600_rasterizer(rctx);
1068 rctx->hw_states.scissor = r600_scissor(rctx);
1069 rctx->hw_states.dsa = r600_dsa(rctx);
1070 rctx->hw_states.blend = r600_blend(rctx);
1071 rctx->hw_states.viewport = r600_viewport(rctx);
1072 rctx->hw_states.cb0 = r600_cb0(rctx);
1073 rctx->hw_states.db = r600_db(rctx);
1074 for (i = 0; i < rctx->ps_nsampler; i++) {
1075 if (rctx->ps_sampler[i]) {
1076 rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
1077 &rctx->ps_sampler[i]->state.sampler,
1078 R600_PS_SAMPLER + i);
1079 }
1080 }
1081 rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
1082 for (i = 0; i < rctx->ps_nsampler_view; i++) {
1083 if (rctx->ps_sampler_view[i]) {
1084 rctx->hw_states.ps_resource[i] = r600_resource(rctx,
1085 &rctx->ps_sampler_view[i]->state.sampler_view,
1086 R600_PS_RESOURCE + i);
1087 }
1088 }
1089 rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
1090
1091 /* bind states */
1092 r = radeon_draw_set(rctx->draw, rctx->hw_states.db);
1093 if (r)
1094 return r;
1095 r = radeon_draw_set(rctx->draw, rctx->hw_states.rasterizer);
1096 if (r)
1097 return r;
1098 r = radeon_draw_set(rctx->draw, rctx->hw_states.scissor);
1099 if (r)
1100 return r;
1101 r = radeon_draw_set(rctx->draw, rctx->hw_states.dsa);
1102 if (r)
1103 return r;
1104 r = radeon_draw_set(rctx->draw, rctx->hw_states.blend);
1105 if (r)
1106 return r;
1107 r = radeon_draw_set(rctx->draw, rctx->hw_states.viewport);
1108 if (r)
1109 return r;
1110 r = radeon_draw_set(rctx->draw, rctx->hw_states.cb0);
1111 if (r)
1112 return r;
1113 r = radeon_draw_set(rctx->draw, rctx->hw_states.config);
1114 if (r)
1115 return r;
1116 r = radeon_draw_set(rctx->draw, rctx->hw_states.cb_cntl);
1117 if (r)
1118 return r;
1119 for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
1120 if (rctx->hw_states.ps_resource[i]) {
1121 r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_resource[i]);
1122 if (r)
1123 return r;
1124 }
1125 }
1126 for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
1127 if (rctx->hw_states.ps_sampler[i]) {
1128 r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_sampler[i]);
1129 if (r)
1130 return r;
1131 }
1132 }
1133 return 0;
1134 }