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r600g: fix incorrect state naming in pipe_sampler vs pipe_sampler_view
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include <stdio.h>
27 #include <errno.h>
28 #include "util/u_inlines.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "r600_screen.h"
32 #include "r600_context.h"
33 #include "r600_resource.h"
34 #include "r600d.h"
35 #include "r600_state_inlines.h"
36
37 static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state);
38 static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state);
39 static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_clip_state *state);
40 static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_sampler_state *state, unsigned id);
41 static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate, const struct pipe_sampler_view *view, unsigned id);
42 static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate,
43 const struct pipe_framebuffer_state *state, int cb);
44 static void r600_db(struct r600_context *rctx, struct radeon_state *rstate,
45 const struct pipe_framebuffer_state *state);
46
47
48 static void *r600_create_blend_state(struct pipe_context *ctx,
49 const struct pipe_blend_state *state)
50 {
51 struct r600_context *rctx = r600_context(ctx);
52
53 return r600_context_state(rctx, pipe_blend_type, state);
54 }
55
56 static void *r600_create_dsa_state(struct pipe_context *ctx,
57 const struct pipe_depth_stencil_alpha_state *state)
58 {
59 struct r600_context *rctx = r600_context(ctx);
60
61 return r600_context_state(rctx, pipe_dsa_type, state);
62 }
63
64 static void *r600_create_rs_state(struct pipe_context *ctx,
65 const struct pipe_rasterizer_state *state)
66 {
67 struct r600_context *rctx = r600_context(ctx);
68
69 return r600_context_state(rctx, pipe_rasterizer_type, state);
70 }
71
72 static void *r600_create_sampler_state(struct pipe_context *ctx,
73 const struct pipe_sampler_state *state)
74 {
75 struct r600_context *rctx = r600_context(ctx);
76
77 return r600_context_state(rctx, pipe_sampler_type, state);
78 }
79
80 static void r600_sampler_view_destroy(struct pipe_context *ctx,
81 struct pipe_sampler_view *state)
82 {
83 struct r600_context_state *rstate = (struct r600_context_state *)state;
84
85 r600_context_state_decref(rstate);
86 }
87
88 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
89 struct pipe_resource *texture,
90 const struct pipe_sampler_view *state)
91 {
92 struct r600_context *rctx = r600_context(ctx);
93 struct r600_context_state *rstate;
94
95 rstate = r600_context_state(rctx, pipe_sampler_view_type, state);
96 pipe_reference(NULL, &texture->reference);
97 rstate->state.sampler_view.texture = texture;
98 rstate->state.sampler_view.reference.count = 1;
99 rstate->state.sampler_view.context = ctx;
100 r600_resource(ctx, &rstate->rstate[0], &rstate->state.sampler_view, 0);
101 return &rstate->state.sampler_view;
102 }
103
104 static void *r600_create_shader_state(struct pipe_context *ctx,
105 const struct pipe_shader_state *state)
106 {
107 struct r600_context *rctx = r600_context(ctx);
108
109 return r600_context_state(rctx, pipe_shader_type, state);
110 }
111
112 static void *r600_create_vertex_elements(struct pipe_context *ctx,
113 unsigned count,
114 const struct pipe_vertex_element *elements)
115 {
116 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
117
118 assert(count < 32);
119 v->count = count;
120 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
121 v->refcount = 1;
122 return v;
123 }
124
125 static void r600_bind_state(struct pipe_context *ctx, void *state)
126 {
127 struct r600_context *rctx = r600_context(ctx);
128 struct r600_context_state *rstate = (struct r600_context_state *)state;
129
130 if (state == NULL)
131 return;
132 switch (rstate->type) {
133 case pipe_rasterizer_type:
134 rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
135 rctx->rasterizer = r600_context_state_incref(rstate);
136 break;
137 case pipe_poly_stipple_type:
138 rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple);
139 rctx->poly_stipple = r600_context_state_incref(rstate);
140 break;
141 case pipe_scissor_type:
142 rctx->scissor = r600_context_state_decref(rctx->scissor);
143 rctx->scissor = r600_context_state_incref(rstate);
144 break;
145 case pipe_clip_type:
146 rctx->clip = r600_context_state_decref(rctx->clip);
147 rctx->clip = r600_context_state_incref(rstate);
148 break;
149 case pipe_depth_type:
150 rctx->depth = r600_context_state_decref(rctx->depth);
151 rctx->depth = r600_context_state_incref(rstate);
152 break;
153 case pipe_stencil_type:
154 rctx->stencil = r600_context_state_decref(rctx->stencil);
155 rctx->stencil = r600_context_state_incref(rstate);
156 break;
157 case pipe_alpha_type:
158 rctx->alpha = r600_context_state_decref(rctx->alpha);
159 rctx->alpha = r600_context_state_incref(rstate);
160 break;
161 case pipe_dsa_type:
162 rctx->dsa = r600_context_state_decref(rctx->dsa);
163 rctx->dsa = r600_context_state_incref(rstate);
164 break;
165 case pipe_blend_type:
166 rctx->blend = r600_context_state_decref(rctx->blend);
167 rctx->blend = r600_context_state_incref(rstate);
168 break;
169 case pipe_framebuffer_type:
170 rctx->framebuffer = r600_context_state_decref(rctx->framebuffer);
171 rctx->framebuffer = r600_context_state_incref(rstate);
172 break;
173 case pipe_stencil_ref_type:
174 rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref);
175 rctx->stencil_ref = r600_context_state_incref(rstate);
176 break;
177 case pipe_viewport_type:
178 rctx->viewport = r600_context_state_decref(rctx->viewport);
179 rctx->viewport = r600_context_state_incref(rstate);
180 break;
181 case pipe_shader_type:
182 case pipe_sampler_type:
183 case pipe_sampler_view_type:
184 default:
185 R600_ERR("invalid type %d\n", rstate->type);
186 return;
187 }
188 }
189
190 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
191 {
192 struct r600_context *rctx = r600_context(ctx);
193 struct r600_context_state *rstate = (struct r600_context_state *)state;
194
195 rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
196 rctx->ps_shader = r600_context_state_incref(rstate);
197 }
198
199 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
200 {
201 struct r600_context *rctx = r600_context(ctx);
202 struct r600_context_state *rstate = (struct r600_context_state *)state;
203
204 rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
205 rctx->vs_shader = r600_context_state_incref(rstate);
206 }
207
208 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
209 {
210 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
211
212 if (v == NULL)
213 return;
214 if (--v->refcount)
215 return;
216 free(v);
217 }
218
219 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
220 {
221 struct r600_context *rctx = r600_context(ctx);
222 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
223
224 r600_delete_vertex_element(ctx, rctx->vertex_elements);
225 rctx->vertex_elements = v;
226 if (v) {
227 v->refcount++;
228 }
229 }
230
231 static void r600_bind_ps_sampler(struct pipe_context *ctx,
232 unsigned count, void **states)
233 {
234 struct r600_context *rctx = r600_context(ctx);
235 struct r600_context_state *rstate;
236 unsigned i;
237
238 for (i = 0; i < rctx->ps_nsampler; i++) {
239 rctx->ps_sampler[i] = r600_context_state_decref(rctx->ps_sampler[i]);
240 }
241 for (i = 0; i < count; i++) {
242 rstate = (struct r600_context_state *)states[i];
243 rctx->ps_sampler[i] = r600_context_state_incref(rstate);
244 if (rstate) {
245 radeon_state_convert(&rstate->rstate[0], R600_STATE_SAMPLER, i, R600_SHADER_PS);
246 }
247 }
248 rctx->ps_nsampler = count;
249 }
250
251 static void r600_bind_vs_sampler(struct pipe_context *ctx,
252 unsigned count, void **states)
253 {
254 struct r600_context *rctx = r600_context(ctx);
255 struct r600_context_state *rstate;
256 unsigned i;
257
258 for (i = 0; i < rctx->vs_nsampler; i++) {
259 rctx->vs_sampler[i] = r600_context_state_decref(rctx->vs_sampler[i]);
260 }
261 for (i = 0; i < count; i++) {
262 rstate = (struct r600_context_state *)states[i];
263 rctx->vs_sampler[i] = r600_context_state_incref(rstate);
264 if (rstate) {
265 radeon_state_convert(&rstate->rstate[0], R600_STATE_SAMPLER, i, R600_SHADER_VS);
266 }
267 }
268 rctx->vs_nsampler = count;
269 }
270
271 static void r600_delete_state(struct pipe_context *ctx, void *state)
272 {
273 struct r600_context_state *rstate = (struct r600_context_state *)state;
274
275 r600_context_state_decref(rstate);
276 }
277
278 static void r600_set_blend_color(struct pipe_context *ctx,
279 const struct pipe_blend_color *color)
280 {
281 struct r600_context *rctx = r600_context(ctx);
282
283 rctx->blend_color = *color;
284 }
285
286 static void r600_set_clip_state(struct pipe_context *ctx,
287 const struct pipe_clip_state *state)
288 {
289 struct r600_context *rctx = r600_context(ctx);
290 struct r600_context_state *rstate;
291
292 rstate = r600_context_state(rctx, pipe_clip_type, state);
293 r600_bind_state(ctx, rstate);
294 /* refcount is taken care of this */
295 r600_delete_state(ctx, rstate);
296 }
297
298 static void r600_set_constant_buffer(struct pipe_context *ctx,
299 uint shader, uint index,
300 struct pipe_resource *buffer)
301 {
302 struct r600_screen *rscreen = r600_screen(ctx->screen);
303 struct r600_context *rctx = r600_context(ctx);
304 unsigned nconstant = 0, i, type, shader_class;
305 struct radeon_state *rstate, *rstates;
306 struct pipe_transfer *transfer;
307 u32 *ptr;
308
309 type = R600_STATE_CONSTANT;
310
311 switch (shader) {
312 case PIPE_SHADER_VERTEX:
313 shader_class = R600_SHADER_VS;
314 rstates = rctx->vs_constant;
315 break;
316 case PIPE_SHADER_FRAGMENT:
317 shader_class = R600_SHADER_PS;
318 rstates = rctx->ps_constant;
319 break;
320 default:
321 R600_ERR("unsupported %d\n", shader);
322 return;
323 }
324 if (buffer && buffer->width0 > 0) {
325 nconstant = buffer->width0 / 16;
326 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
327 if (ptr == NULL)
328 return;
329 for (i = 0; i < nconstant; i++) {
330 rstate = &rstates[i];
331 radeon_state_init(rstate, rscreen->rw, type, i, shader_class);
332 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
333 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
334 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
335 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
336 if (radeon_state_pm4(rstate))
337 return;
338 radeon_draw_bind(&rctx->draw, rstate);
339 }
340 pipe_buffer_unmap(ctx, buffer, transfer);
341 }
342 }
343
344 static void r600_set_ps_sampler_view(struct pipe_context *ctx,
345 unsigned count,
346 struct pipe_sampler_view **views)
347 {
348 struct r600_context *rctx = r600_context(ctx);
349 struct r600_context_state *rstate;
350 unsigned i;
351
352 for (i = 0; i < rctx->ps_nsampler_view; i++) {
353 rctx->ps_sampler_view[i] = r600_context_state_decref(rctx->ps_sampler_view[i]);
354 }
355 for (i = 0; i < count; i++) {
356 rstate = (struct r600_context_state *)views[i];
357 rctx->ps_sampler_view[i] = r600_context_state_incref(rstate);
358 if (rstate) {
359 radeon_state_convert(&rstate->rstate[0], R600_STATE_RESOURCE, i, R600_SHADER_PS);
360 }
361 }
362 rctx->ps_nsampler_view = count;
363 }
364
365 static void r600_set_vs_sampler_view(struct pipe_context *ctx,
366 unsigned count,
367 struct pipe_sampler_view **views)
368 {
369 struct r600_context *rctx = r600_context(ctx);
370 struct r600_context_state *rstate;
371 unsigned i;
372
373 for (i = 0; i < rctx->vs_nsampler_view; i++) {
374 rctx->vs_sampler_view[i] = r600_context_state_decref(rctx->vs_sampler_view[i]);
375 }
376 for (i = 0; i < count; i++) {
377 rstate = (struct r600_context_state *)views[i];
378 rctx->vs_sampler_view[i] = r600_context_state_incref(rstate);
379 if (rstate) {
380 radeon_state_convert(&rstate->rstate[0], R600_STATE_RESOURCE, i, R600_SHADER_VS);
381 }
382 }
383 rctx->vs_nsampler_view = count;
384 }
385
386 static void r600_set_framebuffer_state(struct pipe_context *ctx,
387 const struct pipe_framebuffer_state *state)
388 {
389 struct r600_context *rctx = r600_context(ctx);
390 struct r600_context_state *rstate;
391
392 rstate = r600_context_state(rctx, pipe_framebuffer_type, state);
393 r600_bind_state(ctx, rstate);
394 for (int i = 0; i < state->nr_cbufs; i++) {
395 r600_cb(rctx, &rstate->rstate[i+1], state, i);
396 }
397 if (state->zsbuf) {
398 r600_db(rctx, &rstate->rstate[0], state);
399 }
400 }
401
402 static void r600_set_polygon_stipple(struct pipe_context *ctx,
403 const struct pipe_poly_stipple *state)
404 {
405 }
406
407 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
408 {
409 }
410
411 static void r600_set_scissor_state(struct pipe_context *ctx,
412 const struct pipe_scissor_state *state)
413 {
414 struct r600_context *rctx = r600_context(ctx);
415 struct r600_context_state *rstate;
416
417 rstate = r600_context_state(rctx, pipe_scissor_type, state);
418 r600_bind_state(ctx, rstate);
419 /* refcount is taken care of this */
420 r600_delete_state(ctx, rstate);
421 }
422
423 static void r600_set_stencil_ref(struct pipe_context *ctx,
424 const struct pipe_stencil_ref *state)
425 {
426 struct r600_context *rctx = r600_context(ctx);
427 struct r600_context_state *rstate;
428
429 rstate = r600_context_state(rctx, pipe_stencil_ref_type, state);
430 r600_bind_state(ctx, rstate);
431 /* refcount is taken care of this */
432 r600_delete_state(ctx, rstate);
433 }
434
435 static void r600_set_vertex_buffers(struct pipe_context *ctx,
436 unsigned count,
437 const struct pipe_vertex_buffer *buffers)
438 {
439 struct r600_context *rctx = r600_context(ctx);
440 unsigned i;
441
442 for (i = 0; i < rctx->nvertex_buffer; i++) {
443 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
444 }
445 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
446 for (i = 0; i < count; i++) {
447 rctx->vertex_buffer[i].buffer = NULL;
448 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
449 }
450 rctx->nvertex_buffer = count;
451 }
452
453 static void r600_set_index_buffer(struct pipe_context *ctx,
454 const struct pipe_index_buffer *ib)
455 {
456 struct r600_context *rctx = r600_context(ctx);
457
458 if (ib) {
459 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
460 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
461 } else {
462 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
463 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
464 }
465
466 /* TODO make this more like a state */
467 }
468
469 static void r600_set_viewport_state(struct pipe_context *ctx,
470 const struct pipe_viewport_state *state)
471 {
472 struct r600_context *rctx = r600_context(ctx);
473 struct r600_context_state *rstate;
474
475 rstate = r600_context_state(rctx, pipe_viewport_type, state);
476 r600_bind_state(ctx, rstate);
477 r600_delete_state(ctx, rstate);
478 }
479
480 void r600_init_state_functions(struct r600_context *rctx)
481 {
482 rctx->context.create_blend_state = r600_create_blend_state;
483 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
484 rctx->context.create_fs_state = r600_create_shader_state;
485 rctx->context.create_rasterizer_state = r600_create_rs_state;
486 rctx->context.create_sampler_state = r600_create_sampler_state;
487 rctx->context.create_sampler_view = r600_create_sampler_view;
488 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
489 rctx->context.create_vs_state = r600_create_shader_state;
490 rctx->context.bind_blend_state = r600_bind_state;
491 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
492 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
493 rctx->context.bind_fs_state = r600_bind_ps_shader;
494 rctx->context.bind_rasterizer_state = r600_bind_state;
495 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
496 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
497 rctx->context.bind_vs_state = r600_bind_vs_shader;
498 rctx->context.delete_blend_state = r600_delete_state;
499 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
500 rctx->context.delete_fs_state = r600_delete_state;
501 rctx->context.delete_rasterizer_state = r600_delete_state;
502 rctx->context.delete_sampler_state = r600_delete_state;
503 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
504 rctx->context.delete_vs_state = r600_delete_state;
505 rctx->context.set_blend_color = r600_set_blend_color;
506 rctx->context.set_clip_state = r600_set_clip_state;
507 rctx->context.set_constant_buffer = r600_set_constant_buffer;
508 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
509 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
510 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
511 rctx->context.set_sample_mask = r600_set_sample_mask;
512 rctx->context.set_scissor_state = r600_set_scissor_state;
513 rctx->context.set_stencil_ref = r600_set_stencil_ref;
514 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
515 rctx->context.set_index_buffer = r600_set_index_buffer;
516 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
517 rctx->context.set_viewport_state = r600_set_viewport_state;
518 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
519 }
520
521 struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate)
522 {
523 if (rstate == NULL)
524 return NULL;
525 rstate->refcount++;
526 return rstate;
527 }
528
529 struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate)
530 {
531 unsigned i;
532
533 if (rstate == NULL)
534 return NULL;
535 if (--rstate->refcount)
536 return NULL;
537 switch (rstate->type) {
538 case pipe_sampler_view_type:
539 pipe_resource_reference(&rstate->state.sampler_view.texture, NULL);
540 break;
541 case pipe_framebuffer_type:
542 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
543 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], NULL);
544 }
545 pipe_surface_reference(&rstate->state.framebuffer.zsbuf, NULL);
546 break;
547 case pipe_viewport_type:
548 case pipe_depth_type:
549 case pipe_rasterizer_type:
550 case pipe_poly_stipple_type:
551 case pipe_scissor_type:
552 case pipe_clip_type:
553 case pipe_stencil_type:
554 case pipe_alpha_type:
555 case pipe_dsa_type:
556 case pipe_blend_type:
557 case pipe_stencil_ref_type:
558 case pipe_shader_type:
559 case pipe_sampler_type:
560 break;
561 default:
562 R600_ERR("invalid type %d\n", rstate->type);
563 return NULL;
564 }
565 radeon_state_fini(&rstate->rstate[0]);
566 FREE(rstate);
567 return NULL;
568 }
569
570 struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state)
571 {
572 struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state);
573 const union pipe_states *states = state;
574 unsigned i;
575 int r;
576
577 if (rstate == NULL)
578 return NULL;
579 rstate->type = type;
580 rstate->refcount = 1;
581
582 switch (rstate->type) {
583 case pipe_sampler_view_type:
584 rstate->state.sampler_view = (*states).sampler_view;
585 rstate->state.sampler_view.texture = NULL;
586 break;
587 case pipe_framebuffer_type:
588 rstate->state.framebuffer = (*states).framebuffer;
589 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
590 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i],
591 (*states).framebuffer.cbufs[i]);
592 }
593 pipe_surface_reference(&rstate->state.framebuffer.zsbuf,
594 (*states).framebuffer.zsbuf);
595 break;
596 case pipe_viewport_type:
597 rstate->state.viewport = (*states).viewport;
598 r600_viewport(rctx, &rstate->rstate[0], &rstate->state.viewport);
599 break;
600 case pipe_depth_type:
601 rstate->state.depth = (*states).depth;
602 break;
603 case pipe_rasterizer_type:
604 rstate->state.rasterizer = (*states).rasterizer;
605 break;
606 case pipe_poly_stipple_type:
607 rstate->state.poly_stipple = (*states).poly_stipple;
608 break;
609 case pipe_scissor_type:
610 rstate->state.scissor = (*states).scissor;
611 break;
612 case pipe_clip_type:
613 rstate->state.clip = (*states).clip;
614 r600_ucp(rctx, &rstate->rstate[0], &rstate->state.clip);
615 break;
616 case pipe_stencil_type:
617 rstate->state.stencil = (*states).stencil;
618 break;
619 case pipe_alpha_type:
620 rstate->state.alpha = (*states).alpha;
621 break;
622 case pipe_dsa_type:
623 rstate->state.dsa = (*states).dsa;
624 break;
625 case pipe_blend_type:
626 rstate->state.blend = (*states).blend;
627 r600_blend(rctx, &rstate->rstate[0], &rstate->state.blend);
628 break;
629 case pipe_stencil_ref_type:
630 rstate->state.stencil_ref = (*states).stencil_ref;
631 break;
632 case pipe_shader_type:
633 rstate->state.shader = (*states).shader;
634 r = r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens);
635 if (r) {
636 r600_context_state_decref(rstate);
637 return NULL;
638 }
639 break;
640 case pipe_sampler_type:
641 rstate->state.sampler = (*states).sampler;
642 r600_sampler(rctx, &rstate->rstate[0], &rstate->state.sampler, 0);
643 break;
644 default:
645 R600_ERR("invalid type %d\n", rstate->type);
646 FREE(rstate);
647 return NULL;
648 }
649 return rstate;
650 }
651
652 static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state)
653 {
654 struct r600_screen *rscreen = rctx->screen;
655 int i;
656
657 radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
658 rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
659 rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
660 rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
661 rstate->states[R600_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
662 rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
663 rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
664 rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
665 rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
666 rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
667 rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
668 rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
669 rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
670 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
671
672 for (i = 0; i < 8; i++) {
673 unsigned eqRGB = state->rt[i].rgb_func;
674 unsigned srcRGB = state->rt[i].rgb_src_factor;
675 unsigned dstRGB = state->rt[i].rgb_dst_factor;
676
677 unsigned eqA = state->rt[i].alpha_func;
678 unsigned srcA = state->rt[i].alpha_src_factor;
679 unsigned dstA = state->rt[i].alpha_dst_factor;
680 uint32_t bc = 0;
681
682 if (!state->rt[i].blend_enable)
683 continue;
684
685 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
686 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
687 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
688
689 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
690 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
691 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
692 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
693 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
694 }
695
696 rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc;
697 if (i == 0)
698 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
699 }
700
701 radeon_state_pm4(rstate);
702 }
703
704 static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate,
705 const struct pipe_clip_state *state)
706 {
707 struct r600_screen *rscreen = rctx->screen;
708
709 radeon_state_init(rstate, rscreen->rw, R600_STATE_UCP, 0, 0);
710
711 for (int i = 0; i < state->nr; i++) {
712 rstate->states[i * 4 + 0] = fui(state->ucp[i][0]);
713 rstate->states[i * 4 + 1] = fui(state->ucp[i][1]);
714 rstate->states[i * 4 + 2] = fui(state->ucp[i][2]);
715 rstate->states[i * 4 + 3] = fui(state->ucp[i][3]);
716 }
717 radeon_state_pm4(rstate);
718 }
719
720 static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate,
721 const struct pipe_framebuffer_state *state, int cb)
722 {
723 struct r600_screen *rscreen = rctx->screen;
724 struct r600_resource_texture *rtex;
725 struct r600_resource *rbuffer;
726 unsigned level = state->cbufs[cb]->level;
727 unsigned pitch, slice;
728 unsigned color_info;
729 unsigned format, swap, ntype;
730 const struct util_format_description *desc;
731
732 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
733 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
734 rbuffer = &rtex->resource;
735 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
736 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
737 rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
738 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
739 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
740 rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
741 rstate->nbo = 3;
742 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
743 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
744
745 ntype = 0;
746 desc = util_format_description(rtex->resource.base.b.format);
747 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
748 ntype = V_0280A0_NUMBER_SRGB;
749
750 format = r600_translate_colorformat(rtex->resource.base.b.format);
751 swap = r600_translate_colorswap(rtex->resource.base.b.format);
752
753 color_info = S_0280A0_FORMAT(format) |
754 S_0280A0_COMP_SWAP(swap) |
755 S_0280A0_BLEND_CLAMP(1) |
756 S_0280A0_SOURCE_FORMAT(1) |
757 S_0280A0_NUMBER_TYPE(ntype);
758
759 rstate->states[R600_CB0__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
760 rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
761 rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
762 S_028060_SLICE_TILE_MAX(slice);
763 rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
764 rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
765 rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
766 rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
767 radeon_state_pm4(rstate);
768 }
769
770 static void r600_db(struct r600_context *rctx, struct radeon_state *rstate,
771 const struct pipe_framebuffer_state *state)
772 {
773 struct r600_screen *rscreen = rctx->screen;
774 struct r600_resource_texture *rtex;
775 struct r600_resource *rbuffer;
776 unsigned level;
777 unsigned pitch, slice, format;
778
779 radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
780 if (state->zsbuf == NULL)
781 return;
782
783 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
784 rtex->tilled = 1;
785 rtex->array_mode = 2;
786 rtex->tile_type = 1;
787 rtex->depth = 1;
788 rbuffer = &rtex->resource;
789
790 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
791 rstate->nbo = 1;
792 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
793 level = state->zsbuf->level;
794 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
795 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
796 format = r600_translate_dbformat(state->zsbuf->texture->format);
797 rstate->states[R600_DB__DB_DEPTH_BASE] = state->zsbuf->offset >> 8;
798 rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtex->array_mode) |
799 S_028010_FORMAT(format);
800 rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
801 rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
802 rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
803 S_028000_SLICE_TILE_MAX(slice);
804 radeon_state_pm4(rstate);
805 }
806
807 static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rstate)
808 {
809 const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
810 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
811 const struct pipe_clip_state *clip = NULL;
812 struct r600_screen *rscreen = rctx->screen;
813 float offset_units = 0, offset_scale = 0;
814 char depth = 0;
815 unsigned offset_db_fmt_cntl = 0;
816 unsigned tmp;
817 unsigned prov_vtx = 1;
818
819 if (rctx->clip)
820 clip = &rctx->clip->state.clip;
821 if (fb->zsbuf) {
822 offset_units = state->offset_units;
823 offset_scale = state->offset_scale * 12.0f;
824 switch (fb->zsbuf->texture->format) {
825 case PIPE_FORMAT_Z24X8_UNORM:
826 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
827 depth = -24;
828 offset_units *= 2.0f;
829 break;
830 case PIPE_FORMAT_Z32_FLOAT:
831 depth = -23;
832 offset_units *= 1.0f;
833 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
834 break;
835 case PIPE_FORMAT_Z16_UNORM:
836 depth = -16;
837 offset_units *= 4.0f;
838 break;
839 default:
840 R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
841 return;
842 }
843 }
844 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
845
846 if (state->flatshade_first)
847 prov_vtx = 0;
848
849 rctx->flat_shade = state->flatshade;
850 radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
851 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
852 if (state->sprite_coord_enable) {
853 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
854 S_0286D4_PNT_SPRITE_ENA(1) |
855 S_0286D4_PNT_SPRITE_OVRD_X(2) |
856 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
857 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
858 S_0286D4_PNT_SPRITE_OVRD_W(1);
859 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
860 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
861 S_0286D4_PNT_SPRITE_TOP_1(1);
862 }
863 }
864 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
865 if (clip) {
866 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1);
867 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp);
868 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp);
869 }
870 rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] =
871 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
872 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
873 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
874 S_028814_FACE(!state->front_ccw) |
875 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
876 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
877 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
878 rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] =
879 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
880 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
881 rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
882 /* point size 12.4 fixed point */
883 tmp = (unsigned)(state->point_size * 8.0);
884 rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
885 rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
886 rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
887 rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
888 rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
889 rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
890 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
891 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
892 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
893 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
894 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
895 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
896 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
897 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
898 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
899 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
900 radeon_state_pm4(rstate);
901 }
902
903 static void r600_scissor(struct r600_context *rctx, struct radeon_state *rstate)
904 {
905 const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
906 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
907 struct r600_screen *rscreen = rctx->screen;
908 unsigned minx, maxx, miny, maxy;
909 u32 tl, br;
910
911 if (state == NULL) {
912 minx = 0;
913 miny = 0;
914 maxx = fb->cbufs[0]->width;
915 maxy = fb->cbufs[0]->height;
916 } else {
917 minx = state->minx;
918 miny = state->miny;
919 maxx = state->maxx;
920 maxy = state->maxy;
921 }
922 tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
923 br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
924 radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
925 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
926 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
927 rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
928 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
929 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
930 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
931 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
932 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
933 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
934 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
935 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
936 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
937 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
938 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
939 rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
940 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
941 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
942 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
943 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
944 radeon_state_pm4(rstate);
945 }
946
947 static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state)
948 {
949 struct r600_screen *rscreen = rctx->screen;
950
951 radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
952 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
953 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
954 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
955 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
956 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
957 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
958 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
959 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
960 rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
961 radeon_state_pm4(rstate);
962 }
963
964 static void r600_dsa(struct r600_context *rctx, struct radeon_state *rstate)
965 {
966 const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
967 const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
968 struct r600_screen *rscreen = rctx->screen;
969 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
970 unsigned stencil_ref_mask, stencil_ref_mask_bf;
971 struct r600_shader *rshader;
972 int i;
973
974 if (rctx->ps_shader == NULL) {
975 return;
976 }
977 radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
978
979 db_shader_control = 0x210;
980 rshader = &rctx->ps_shader->shader;
981 if (rshader->uses_kill)
982 db_shader_control |= (1 << 6);
983 for (i = 0; i < rshader->noutput; i++) {
984 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
985 db_shader_control |= 1;
986 }
987 stencil_ref_mask = 0;
988 stencil_ref_mask_bf = 0;
989 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
990 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
991 S_028800_ZFUNC(state->depth.func);
992 /* set stencil enable */
993
994 if (state->stencil[0].enabled) {
995 db_depth_control |= S_028800_STENCIL_ENABLE(1);
996 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
997 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
998 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
999 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
1000
1001 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
1002 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
1003 stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]);
1004 if (state->stencil[1].enabled) {
1005 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1006 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
1007 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
1008 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
1009 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
1010 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
1011 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
1012 stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]);
1013 }
1014 }
1015
1016 alpha_test_control = 0;
1017 alpha_ref = 0;
1018 if (state->alpha.enabled) {
1019 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
1020 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
1021 alpha_ref = fui(state->alpha.ref_value);
1022 }
1023
1024 rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
1025 rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
1026 rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
1027 rstate->states[R600_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
1028 rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
1029 rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref;
1030 rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
1031 rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
1032 rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
1033 rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
1034 rstate->states[R600_DSA__DB_SHADER_CONTROL] = db_shader_control;
1035 rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060;
1036 rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
1037 rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
1038 rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
1039 rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
1040 radeon_state_pm4(rstate);
1041 }
1042
1043 static inline unsigned r600_tex_wrap(unsigned wrap)
1044 {
1045 switch (wrap) {
1046 default:
1047 case PIPE_TEX_WRAP_REPEAT:
1048 return V_03C000_SQ_TEX_WRAP;
1049 case PIPE_TEX_WRAP_CLAMP:
1050 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1051 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1052 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1053 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1054 return V_03C000_SQ_TEX_CLAMP_BORDER;
1055 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1056 return V_03C000_SQ_TEX_MIRROR;
1057 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1058 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1059 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1060 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1061 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1062 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1063 }
1064 }
1065
1066 static inline unsigned r600_tex_filter(unsigned filter)
1067 {
1068 switch (filter) {
1069 default:
1070 case PIPE_TEX_FILTER_NEAREST:
1071 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1072 case PIPE_TEX_FILTER_LINEAR:
1073 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1074 }
1075 }
1076
1077 static inline unsigned r600_tex_mipfilter(unsigned filter)
1078 {
1079 switch (filter) {
1080 case PIPE_TEX_MIPFILTER_NEAREST:
1081 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1082 case PIPE_TEX_MIPFILTER_LINEAR:
1083 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1084 default:
1085 case PIPE_TEX_MIPFILTER_NONE:
1086 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1087 }
1088 }
1089
1090 static inline unsigned r600_tex_compare(unsigned compare)
1091 {
1092 switch (compare) {
1093 default:
1094 case PIPE_FUNC_NEVER:
1095 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1096 case PIPE_FUNC_LESS:
1097 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1098 case PIPE_FUNC_EQUAL:
1099 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1100 case PIPE_FUNC_LEQUAL:
1101 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1102 case PIPE_FUNC_GREATER:
1103 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1104 case PIPE_FUNC_NOTEQUAL:
1105 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1106 case PIPE_FUNC_GEQUAL:
1107 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1108 case PIPE_FUNC_ALWAYS:
1109 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1110 }
1111 }
1112
1113 static INLINE u32 S_FIXED(float value, u32 frac_bits)
1114 {
1115 return value * (1 << frac_bits);
1116 }
1117
1118 static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate,
1119 const struct pipe_sampler_state *state, unsigned id)
1120 {
1121 struct r600_screen *rscreen = rctx->screen;
1122
1123 radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS);
1124 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
1125 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1126 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1127 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1128 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
1129 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
1130 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1131 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func));
1132 /* FIXME LOD it depends on texture base level ... */
1133 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
1134 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1135 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1136 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
1137 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
1138 radeon_state_pm4(rstate);
1139 }
1140
1141 static inline unsigned r600_tex_swizzle(unsigned swizzle)
1142 {
1143 switch (swizzle) {
1144 case PIPE_SWIZZLE_RED:
1145 return V_038010_SQ_SEL_X;
1146 case PIPE_SWIZZLE_GREEN:
1147 return V_038010_SQ_SEL_Y;
1148 case PIPE_SWIZZLE_BLUE:
1149 return V_038010_SQ_SEL_Z;
1150 case PIPE_SWIZZLE_ALPHA:
1151 return V_038010_SQ_SEL_W;
1152 case PIPE_SWIZZLE_ZERO:
1153 return V_038010_SQ_SEL_0;
1154 default:
1155 case PIPE_SWIZZLE_ONE:
1156 return V_038010_SQ_SEL_1;
1157 }
1158 }
1159
1160 static inline unsigned r600_format_type(unsigned format_type)
1161 {
1162 switch (format_type) {
1163 default:
1164 case UTIL_FORMAT_TYPE_UNSIGNED:
1165 return V_038010_SQ_FORMAT_COMP_UNSIGNED;
1166 case UTIL_FORMAT_TYPE_SIGNED:
1167 return V_038010_SQ_FORMAT_COMP_SIGNED;
1168 case UTIL_FORMAT_TYPE_FIXED:
1169 return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED;
1170 }
1171 }
1172
1173 static inline unsigned r600_tex_dim(unsigned dim)
1174 {
1175 switch (dim) {
1176 default:
1177 case PIPE_TEXTURE_1D:
1178 return V_038000_SQ_TEX_DIM_1D;
1179 case PIPE_TEXTURE_2D:
1180 case PIPE_TEXTURE_RECT:
1181 return V_038000_SQ_TEX_DIM_2D;
1182 case PIPE_TEXTURE_3D:
1183 return V_038000_SQ_TEX_DIM_3D;
1184 case PIPE_TEXTURE_CUBE:
1185 return V_038000_SQ_TEX_DIM_CUBEMAP;
1186 }
1187 }
1188
1189 static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate,
1190 const struct pipe_sampler_view *view, unsigned id)
1191 {
1192 struct r600_context *rctx = r600_context(ctx);
1193 struct r600_screen *rscreen = rctx->screen;
1194 const struct util_format_description *desc;
1195 struct r600_resource_texture *tmp;
1196 struct r600_resource *rbuffer;
1197 unsigned format;
1198 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1199 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1200 int r;
1201
1202 rstate->cpm4 = 0;
1203 swizzle[0] = view->swizzle_r;
1204 swizzle[1] = view->swizzle_g;
1205 swizzle[2] = view->swizzle_b;
1206 swizzle[3] = view->swizzle_a;
1207 format = r600_translate_texformat(view->texture->format,
1208 swizzle,
1209 &word4, &yuv_format);
1210 if (format == ~0) {
1211 return;
1212 }
1213 desc = util_format_description(view->texture->format);
1214 if (desc == NULL) {
1215 R600_ERR("unknow format %d\n", view->texture->format);
1216 return;
1217 }
1218 radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
1219 tmp = (struct r600_resource_texture*)view->texture;
1220 rbuffer = &tmp->resource;
1221 if (tmp->depth) {
1222 r = r600_texture_from_depth(ctx, tmp, view->first_level);
1223 if (r) {
1224 return;
1225 }
1226 rstate->bo[0] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
1227 rstate->bo[1] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
1228 } else {
1229 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1230 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1231 }
1232 rstate->nbo = 2;
1233 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
1234 rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
1235 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
1236 rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
1237
1238 pitch = (tmp->pitch[0] / tmp->bpt);
1239 pitch = (pitch + 0x7) & ~0x7;
1240
1241 /* FIXME properly handle first level != 0 */
1242 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
1243 S_038000_DIM(r600_tex_dim(view->texture->target)) |
1244 S_038000_TILE_MODE(array_mode) |
1245 S_038000_TILE_TYPE(tile_type) |
1246 S_038000_PITCH((pitch / 8) - 1) |
1247 S_038000_TEX_WIDTH(view->texture->width0 - 1);
1248 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
1249 S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
1250 S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
1251 S_038004_DATA_FORMAT(format);
1252 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
1253 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
1254 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
1255 word4 |
1256 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
1257 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
1258 S_038010_REQUEST_SIZE(1) |
1259 S_038010_BASE_LEVEL(view->first_level);
1260 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
1261 S_038014_LAST_LEVEL(view->last_level) |
1262 S_038014_BASE_ARRAY(0) |
1263 S_038014_LAST_ARRAY(0);
1264 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
1265 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
1266 radeon_state_pm4(rstate);
1267 }
1268
1269 static void r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
1270 {
1271 struct r600_screen *rscreen = rctx->screen;
1272 const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
1273 int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
1274 uint32_t color_control, target_mask, shader_mask;
1275 int i;
1276
1277 target_mask = 0;
1278 shader_mask = 0;
1279 color_control = S_028808_PER_MRT_BLEND(1);
1280
1281 for (i = 0; i < nr_cbufs; i++) {
1282 shader_mask |= 0xf << (i * 4);
1283 }
1284
1285 if (pbs->logicop_enable) {
1286 color_control |= (pbs->logicop_func) << 16;
1287 } else {
1288 color_control |= (0xcc << 16);
1289 }
1290
1291 if (pbs->independent_blend_enable) {
1292 for (i = 0; i < nr_cbufs; i++) {
1293 if (pbs->rt[i].blend_enable) {
1294 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
1295 }
1296 target_mask |= (pbs->rt[i].colormask << (4 * i));
1297 }
1298 } else {
1299 for (i = 0; i < nr_cbufs; i++) {
1300 if (pbs->rt[0].blend_enable) {
1301 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
1302 }
1303 target_mask |= (pbs->rt[0].colormask << (4 * i));
1304 }
1305 }
1306 radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
1307 rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
1308 rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
1309 rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
1310 rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
1311 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
1312 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
1313 rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
1314 rstate->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
1315 rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
1316 rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
1317 rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
1318 radeon_state_pm4(rstate);
1319 }
1320
1321 int r600_context_hw_states(struct pipe_context *ctx)
1322 {
1323 struct r600_context *rctx = r600_context(ctx);
1324 unsigned i;
1325
1326 /* build new states */
1327 r600_rasterizer(rctx, &rctx->hw_states.rasterizer);
1328 r600_scissor(rctx, &rctx->hw_states.scissor);
1329 r600_dsa(rctx, &rctx->hw_states.dsa);
1330 r600_cb_cntl(rctx, &rctx->hw_states.cb_cntl);
1331
1332 /* bind states */
1333 radeon_draw_bind(&rctx->draw, &rctx->hw_states.rasterizer);
1334 radeon_draw_bind(&rctx->draw, &rctx->hw_states.scissor);
1335 radeon_draw_bind(&rctx->draw, &rctx->hw_states.dsa);
1336 radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_cntl);
1337
1338 radeon_draw_bind(&rctx->draw, &rctx->config);
1339
1340 if (rctx->viewport) {
1341 radeon_draw_bind(&rctx->draw, &rctx->viewport->rstate[0]);
1342 }
1343 if (rctx->blend) {
1344 radeon_draw_bind(&rctx->draw, &rctx->blend->rstate[0]);
1345 }
1346 if (rctx->clip) {
1347 radeon_draw_bind(&rctx->draw, &rctx->clip->rstate[0]);
1348 }
1349 for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++) {
1350 radeon_draw_bind(&rctx->draw, &rctx->framebuffer->rstate[i+1]);
1351 }
1352 if (rctx->framebuffer->state.framebuffer.zsbuf) {
1353 radeon_draw_bind(&rctx->draw, &rctx->framebuffer->rstate[0]);
1354 }
1355 for (i = 0; i < rctx->ps_nsampler; i++) {
1356 if (rctx->ps_sampler[i]) {
1357 radeon_draw_bind(&rctx->draw, &rctx->ps_sampler[i]->rstate[0]);
1358 }
1359 }
1360 for (i = 0; i < rctx->ps_nsampler_view; i++) {
1361 if (rctx->ps_sampler_view[i]) {
1362 radeon_draw_bind(&rctx->draw, &rctx->ps_sampler_view[i]->rstate[0]);
1363 }
1364 }
1365 return 0;
1366 }