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Revert "r600g: don't advertise integer textures without GLSL 1.3"
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include "pipe/p_defines.h"
30 #include "pipe/p_state.h"
31 #include "pipe/p_context.h"
32 #include "tgsi/tgsi_scan.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_util.h"
35 #include "util/u_double_list.h"
36 #include "util/u_pack_color.h"
37 #include "util/u_memory.h"
38 #include "util/u_inlines.h"
39 #include "util/u_framebuffer.h"
40 #include "util/u_transfer.h"
41 #include "pipebuffer/pb_buffer.h"
42 #include "r600.h"
43 #include "r600d.h"
44 #include "r600_resource.h"
45 #include "r600_shader.h"
46 #include "r600_pipe.h"
47 #include "r600_formats.h"
48
49 static uint32_t r600_translate_blend_function(int blend_func)
50 {
51 switch (blend_func) {
52 case PIPE_BLEND_ADD:
53 return V_028804_COMB_DST_PLUS_SRC;
54 case PIPE_BLEND_SUBTRACT:
55 return V_028804_COMB_SRC_MINUS_DST;
56 case PIPE_BLEND_REVERSE_SUBTRACT:
57 return V_028804_COMB_DST_MINUS_SRC;
58 case PIPE_BLEND_MIN:
59 return V_028804_COMB_MIN_DST_SRC;
60 case PIPE_BLEND_MAX:
61 return V_028804_COMB_MAX_DST_SRC;
62 default:
63 R600_ERR("Unknown blend function %d\n", blend_func);
64 assert(0);
65 break;
66 }
67 return 0;
68 }
69
70 static uint32_t r600_translate_blend_factor(int blend_fact)
71 {
72 switch (blend_fact) {
73 case PIPE_BLENDFACTOR_ONE:
74 return V_028804_BLEND_ONE;
75 case PIPE_BLENDFACTOR_SRC_COLOR:
76 return V_028804_BLEND_SRC_COLOR;
77 case PIPE_BLENDFACTOR_SRC_ALPHA:
78 return V_028804_BLEND_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_DST_ALPHA:
80 return V_028804_BLEND_DST_ALPHA;
81 case PIPE_BLENDFACTOR_DST_COLOR:
82 return V_028804_BLEND_DST_COLOR;
83 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
84 return V_028804_BLEND_SRC_ALPHA_SATURATE;
85 case PIPE_BLENDFACTOR_CONST_COLOR:
86 return V_028804_BLEND_CONST_COLOR;
87 case PIPE_BLENDFACTOR_CONST_ALPHA:
88 return V_028804_BLEND_CONST_ALPHA;
89 case PIPE_BLENDFACTOR_ZERO:
90 return V_028804_BLEND_ZERO;
91 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
92 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
94 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
95 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
96 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
97 case PIPE_BLENDFACTOR_INV_DST_COLOR:
98 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
99 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
100 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
101 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
102 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
103 case PIPE_BLENDFACTOR_SRC1_COLOR:
104 return V_028804_BLEND_SRC1_COLOR;
105 case PIPE_BLENDFACTOR_SRC1_ALPHA:
106 return V_028804_BLEND_SRC1_ALPHA;
107 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
108 return V_028804_BLEND_INV_SRC1_COLOR;
109 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
110 return V_028804_BLEND_INV_SRC1_ALPHA;
111 default:
112 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
113 assert(0);
114 break;
115 }
116 return 0;
117 }
118
119 static uint32_t r600_translate_stencil_op(int s_op)
120 {
121 switch (s_op) {
122 case PIPE_STENCIL_OP_KEEP:
123 return V_028800_STENCIL_KEEP;
124 case PIPE_STENCIL_OP_ZERO:
125 return V_028800_STENCIL_ZERO;
126 case PIPE_STENCIL_OP_REPLACE:
127 return V_028800_STENCIL_REPLACE;
128 case PIPE_STENCIL_OP_INCR:
129 return V_028800_STENCIL_INCR;
130 case PIPE_STENCIL_OP_DECR:
131 return V_028800_STENCIL_DECR;
132 case PIPE_STENCIL_OP_INCR_WRAP:
133 return V_028800_STENCIL_INCR_WRAP;
134 case PIPE_STENCIL_OP_DECR_WRAP:
135 return V_028800_STENCIL_DECR_WRAP;
136 case PIPE_STENCIL_OP_INVERT:
137 return V_028800_STENCIL_INVERT;
138 default:
139 R600_ERR("Unknown stencil op %d", s_op);
140 assert(0);
141 break;
142 }
143 return 0;
144 }
145
146 static uint32_t r600_translate_fill(uint32_t func)
147 {
148 switch(func) {
149 case PIPE_POLYGON_MODE_FILL:
150 return 2;
151 case PIPE_POLYGON_MODE_LINE:
152 return 1;
153 case PIPE_POLYGON_MODE_POINT:
154 return 0;
155 default:
156 assert(0);
157 return 0;
158 }
159 }
160
161 /* translates straight */
162 static uint32_t r600_translate_ds_func(int func)
163 {
164 return func;
165 }
166
167 static unsigned r600_tex_wrap(unsigned wrap)
168 {
169 switch (wrap) {
170 default:
171 case PIPE_TEX_WRAP_REPEAT:
172 return V_03C000_SQ_TEX_WRAP;
173 case PIPE_TEX_WRAP_CLAMP:
174 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
175 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
176 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
177 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
178 return V_03C000_SQ_TEX_CLAMP_BORDER;
179 case PIPE_TEX_WRAP_MIRROR_REPEAT:
180 return V_03C000_SQ_TEX_MIRROR;
181 case PIPE_TEX_WRAP_MIRROR_CLAMP:
182 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
183 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
184 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
185 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
186 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
187 }
188 }
189
190 static unsigned r600_tex_filter(unsigned filter)
191 {
192 switch (filter) {
193 default:
194 case PIPE_TEX_FILTER_NEAREST:
195 return V_03C000_SQ_TEX_XY_FILTER_POINT;
196 case PIPE_TEX_FILTER_LINEAR:
197 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
198 }
199 }
200
201 static unsigned r600_tex_mipfilter(unsigned filter)
202 {
203 switch (filter) {
204 case PIPE_TEX_MIPFILTER_NEAREST:
205 return V_03C000_SQ_TEX_Z_FILTER_POINT;
206 case PIPE_TEX_MIPFILTER_LINEAR:
207 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
208 default:
209 case PIPE_TEX_MIPFILTER_NONE:
210 return V_03C000_SQ_TEX_Z_FILTER_NONE;
211 }
212 }
213
214 static unsigned r600_tex_compare(unsigned compare)
215 {
216 switch (compare) {
217 default:
218 case PIPE_FUNC_NEVER:
219 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
220 case PIPE_FUNC_LESS:
221 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
222 case PIPE_FUNC_EQUAL:
223 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
224 case PIPE_FUNC_LEQUAL:
225 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
226 case PIPE_FUNC_GREATER:
227 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
228 case PIPE_FUNC_NOTEQUAL:
229 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
230 case PIPE_FUNC_GEQUAL:
231 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
232 case PIPE_FUNC_ALWAYS:
233 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
234 }
235 }
236
237 static unsigned r600_tex_dim(unsigned dim)
238 {
239 switch (dim) {
240 default:
241 case PIPE_TEXTURE_1D:
242 return V_038000_SQ_TEX_DIM_1D;
243 case PIPE_TEXTURE_1D_ARRAY:
244 return V_038000_SQ_TEX_DIM_1D_ARRAY;
245 case PIPE_TEXTURE_2D:
246 case PIPE_TEXTURE_RECT:
247 return V_038000_SQ_TEX_DIM_2D;
248 case PIPE_TEXTURE_2D_ARRAY:
249 return V_038000_SQ_TEX_DIM_2D_ARRAY;
250 case PIPE_TEXTURE_3D:
251 return V_038000_SQ_TEX_DIM_3D;
252 case PIPE_TEXTURE_CUBE:
253 return V_038000_SQ_TEX_DIM_CUBEMAP;
254 }
255 }
256
257 static uint32_t r600_translate_dbformat(enum pipe_format format)
258 {
259 switch (format) {
260 case PIPE_FORMAT_Z16_UNORM:
261 return V_028010_DEPTH_16;
262 case PIPE_FORMAT_Z24X8_UNORM:
263 return V_028010_DEPTH_X8_24;
264 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
265 return V_028010_DEPTH_8_24;
266 case PIPE_FORMAT_Z32_FLOAT:
267 return V_028010_DEPTH_32_FLOAT;
268 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
269 return V_028010_DEPTH_X24_8_32_FLOAT;
270 default:
271 return ~0U;
272 }
273 }
274
275 static uint32_t r600_translate_colorswap(enum pipe_format format)
276 {
277 switch (format) {
278 /* 8-bit buffers. */
279 case PIPE_FORMAT_A8_UNORM:
280 case PIPE_FORMAT_A8_UINT:
281 case PIPE_FORMAT_A8_SINT:
282 case PIPE_FORMAT_R4A4_UNORM:
283 return V_0280A0_SWAP_ALT_REV;
284 case PIPE_FORMAT_I8_UNORM:
285 case PIPE_FORMAT_L8_UNORM:
286 case PIPE_FORMAT_I8_UINT:
287 case PIPE_FORMAT_I8_SINT:
288 case PIPE_FORMAT_L8_UINT:
289 case PIPE_FORMAT_L8_SINT:
290 case PIPE_FORMAT_L8_SRGB:
291 case PIPE_FORMAT_R8_UNORM:
292 case PIPE_FORMAT_R8_SNORM:
293 case PIPE_FORMAT_R8_UINT:
294 case PIPE_FORMAT_R8_SINT:
295 return V_0280A0_SWAP_STD;
296
297 case PIPE_FORMAT_L4A4_UNORM:
298 case PIPE_FORMAT_A4R4_UNORM:
299 return V_0280A0_SWAP_ALT;
300
301 /* 16-bit buffers. */
302 case PIPE_FORMAT_B5G6R5_UNORM:
303 return V_0280A0_SWAP_STD_REV;
304
305 case PIPE_FORMAT_B5G5R5A1_UNORM:
306 case PIPE_FORMAT_B5G5R5X1_UNORM:
307 return V_0280A0_SWAP_ALT;
308
309 case PIPE_FORMAT_B4G4R4A4_UNORM:
310 case PIPE_FORMAT_B4G4R4X4_UNORM:
311 return V_0280A0_SWAP_ALT;
312
313 case PIPE_FORMAT_Z16_UNORM:
314 return V_0280A0_SWAP_STD;
315
316 case PIPE_FORMAT_L8A8_UNORM:
317 case PIPE_FORMAT_L8A8_UINT:
318 case PIPE_FORMAT_L8A8_SINT:
319 case PIPE_FORMAT_L8A8_SRGB:
320 return V_0280A0_SWAP_ALT;
321 case PIPE_FORMAT_R8G8_UNORM:
322 case PIPE_FORMAT_R8G8_UINT:
323 case PIPE_FORMAT_R8G8_SINT:
324 return V_0280A0_SWAP_STD;
325
326 case PIPE_FORMAT_R16_UNORM:
327 case PIPE_FORMAT_R16_UINT:
328 case PIPE_FORMAT_R16_SINT:
329 case PIPE_FORMAT_R16_FLOAT:
330 return V_0280A0_SWAP_STD;
331
332 /* 32-bit buffers. */
333
334 case PIPE_FORMAT_A8B8G8R8_SRGB:
335 return V_0280A0_SWAP_STD_REV;
336 case PIPE_FORMAT_B8G8R8A8_SRGB:
337 return V_0280A0_SWAP_ALT;
338
339 case PIPE_FORMAT_B8G8R8A8_UNORM:
340 case PIPE_FORMAT_B8G8R8X8_UNORM:
341 return V_0280A0_SWAP_ALT;
342
343 case PIPE_FORMAT_A8R8G8B8_UNORM:
344 case PIPE_FORMAT_X8R8G8B8_UNORM:
345 return V_0280A0_SWAP_ALT_REV;
346 case PIPE_FORMAT_R8G8B8A8_SNORM:
347 case PIPE_FORMAT_R8G8B8A8_UNORM:
348 case PIPE_FORMAT_R8G8B8X8_UNORM:
349 case PIPE_FORMAT_R8G8B8A8_SSCALED:
350 case PIPE_FORMAT_R8G8B8A8_USCALED:
351 case PIPE_FORMAT_R8G8B8A8_SINT:
352 case PIPE_FORMAT_R8G8B8A8_UINT:
353 return V_0280A0_SWAP_STD;
354
355 case PIPE_FORMAT_A8B8G8R8_UNORM:
356 case PIPE_FORMAT_X8B8G8R8_UNORM:
357 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
358 return V_0280A0_SWAP_STD_REV;
359
360 case PIPE_FORMAT_Z24X8_UNORM:
361 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
362 return V_0280A0_SWAP_STD;
363
364 case PIPE_FORMAT_X8Z24_UNORM:
365 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
366 return V_0280A0_SWAP_STD;
367
368 case PIPE_FORMAT_R10G10B10A2_UNORM:
369 case PIPE_FORMAT_R10G10B10X2_SNORM:
370 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
371 return V_0280A0_SWAP_STD;
372
373 case PIPE_FORMAT_B10G10R10A2_UNORM:
374 case PIPE_FORMAT_B10G10R10A2_UINT:
375 return V_0280A0_SWAP_ALT;
376
377 case PIPE_FORMAT_R11G11B10_FLOAT:
378 case PIPE_FORMAT_R16G16_UNORM:
379 case PIPE_FORMAT_R16G16_FLOAT:
380 case PIPE_FORMAT_R16G16_UINT:
381 case PIPE_FORMAT_R16G16_SINT:
382 case PIPE_FORMAT_R32_UINT:
383 case PIPE_FORMAT_R32_SINT:
384 case PIPE_FORMAT_R32_FLOAT:
385 case PIPE_FORMAT_Z32_FLOAT:
386 return V_0280A0_SWAP_STD;
387
388 /* 64-bit buffers. */
389 case PIPE_FORMAT_R32G32_FLOAT:
390 case PIPE_FORMAT_R32G32_UINT:
391 case PIPE_FORMAT_R32G32_SINT:
392 case PIPE_FORMAT_R16G16B16A16_UNORM:
393 case PIPE_FORMAT_R16G16B16A16_SNORM:
394 case PIPE_FORMAT_R16G16B16A16_USCALED:
395 case PIPE_FORMAT_R16G16B16A16_SSCALED:
396 case PIPE_FORMAT_R16G16B16A16_UINT:
397 case PIPE_FORMAT_R16G16B16A16_SINT:
398 case PIPE_FORMAT_R16G16B16A16_FLOAT:
399 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
400
401 /* 128-bit buffers. */
402 case PIPE_FORMAT_R32G32B32A32_FLOAT:
403 case PIPE_FORMAT_R32G32B32A32_SNORM:
404 case PIPE_FORMAT_R32G32B32A32_UNORM:
405 case PIPE_FORMAT_R32G32B32A32_USCALED:
406 case PIPE_FORMAT_R32G32B32A32_SSCALED:
407 case PIPE_FORMAT_R32G32B32A32_SINT:
408 case PIPE_FORMAT_R32G32B32A32_UINT:
409 return V_0280A0_SWAP_STD;
410 default:
411 R600_ERR("unsupported colorswap format %d\n", format);
412 return ~0U;
413 }
414 return ~0U;
415 }
416
417 static uint32_t r600_translate_colorformat(enum pipe_format format)
418 {
419 switch (format) {
420 case PIPE_FORMAT_L4A4_UNORM:
421 case PIPE_FORMAT_R4A4_UNORM:
422 case PIPE_FORMAT_A4R4_UNORM:
423 return V_0280A0_COLOR_4_4;
424
425 /* 8-bit buffers. */
426 case PIPE_FORMAT_A8_UNORM:
427 case PIPE_FORMAT_A8_UINT:
428 case PIPE_FORMAT_A8_SINT:
429 case PIPE_FORMAT_I8_UNORM:
430 case PIPE_FORMAT_I8_UINT:
431 case PIPE_FORMAT_I8_SINT:
432 case PIPE_FORMAT_L8_UNORM:
433 case PIPE_FORMAT_L8_UINT:
434 case PIPE_FORMAT_L8_SINT:
435 case PIPE_FORMAT_L8_SRGB:
436 case PIPE_FORMAT_R8_UNORM:
437 case PIPE_FORMAT_R8_SNORM:
438 case PIPE_FORMAT_R8_UINT:
439 case PIPE_FORMAT_R8_SINT:
440 return V_0280A0_COLOR_8;
441
442 /* 16-bit buffers. */
443 case PIPE_FORMAT_B5G6R5_UNORM:
444 return V_0280A0_COLOR_5_6_5;
445
446 case PIPE_FORMAT_B5G5R5A1_UNORM:
447 case PIPE_FORMAT_B5G5R5X1_UNORM:
448 return V_0280A0_COLOR_1_5_5_5;
449
450 case PIPE_FORMAT_B4G4R4A4_UNORM:
451 case PIPE_FORMAT_B4G4R4X4_UNORM:
452 return V_0280A0_COLOR_4_4_4_4;
453
454 case PIPE_FORMAT_Z16_UNORM:
455 return V_0280A0_COLOR_16;
456
457 case PIPE_FORMAT_L8A8_UNORM:
458 case PIPE_FORMAT_L8A8_UINT:
459 case PIPE_FORMAT_L8A8_SINT:
460 case PIPE_FORMAT_L8A8_SRGB:
461 case PIPE_FORMAT_R8G8_UNORM:
462 case PIPE_FORMAT_R8G8_UINT:
463 case PIPE_FORMAT_R8G8_SINT:
464 return V_0280A0_COLOR_8_8;
465
466 case PIPE_FORMAT_R16_UNORM:
467 case PIPE_FORMAT_R16_UINT:
468 case PIPE_FORMAT_R16_SINT:
469 return V_0280A0_COLOR_16;
470
471 case PIPE_FORMAT_R16_FLOAT:
472 return V_0280A0_COLOR_16_FLOAT;
473
474 /* 32-bit buffers. */
475 case PIPE_FORMAT_A8B8G8R8_SRGB:
476 case PIPE_FORMAT_A8B8G8R8_UNORM:
477 case PIPE_FORMAT_A8R8G8B8_UNORM:
478 case PIPE_FORMAT_B8G8R8A8_SRGB:
479 case PIPE_FORMAT_B8G8R8A8_UNORM:
480 case PIPE_FORMAT_B8G8R8X8_UNORM:
481 case PIPE_FORMAT_R8G8B8A8_SNORM:
482 case PIPE_FORMAT_R8G8B8A8_UNORM:
483 case PIPE_FORMAT_R8G8B8A8_SSCALED:
484 case PIPE_FORMAT_R8G8B8A8_USCALED:
485 case PIPE_FORMAT_R8G8B8X8_UNORM:
486 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
487 case PIPE_FORMAT_X8B8G8R8_UNORM:
488 case PIPE_FORMAT_X8R8G8B8_UNORM:
489 case PIPE_FORMAT_R8G8B8_UNORM:
490 case PIPE_FORMAT_R8G8B8A8_SINT:
491 case PIPE_FORMAT_R8G8B8A8_UINT:
492 return V_0280A0_COLOR_8_8_8_8;
493
494 case PIPE_FORMAT_R10G10B10A2_UNORM:
495 case PIPE_FORMAT_R10G10B10X2_SNORM:
496 case PIPE_FORMAT_B10G10R10A2_UNORM:
497 case PIPE_FORMAT_B10G10R10A2_UINT:
498 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
499 return V_0280A0_COLOR_2_10_10_10;
500
501 case PIPE_FORMAT_Z24X8_UNORM:
502 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
503 return V_0280A0_COLOR_8_24;
504
505 case PIPE_FORMAT_X8Z24_UNORM:
506 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
507 return V_0280A0_COLOR_24_8;
508
509 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
510 return V_0280A0_COLOR_X24_8_32_FLOAT;
511
512 case PIPE_FORMAT_R32_UINT:
513 case PIPE_FORMAT_R32_SINT:
514 return V_0280A0_COLOR_32;
515
516 case PIPE_FORMAT_R32_FLOAT:
517 case PIPE_FORMAT_Z32_FLOAT:
518 return V_0280A0_COLOR_32_FLOAT;
519
520 case PIPE_FORMAT_R16G16_FLOAT:
521 return V_0280A0_COLOR_16_16_FLOAT;
522
523 case PIPE_FORMAT_R16G16_SSCALED:
524 case PIPE_FORMAT_R16G16_UNORM:
525 case PIPE_FORMAT_R16G16_UINT:
526 case PIPE_FORMAT_R16G16_SINT:
527 return V_0280A0_COLOR_16_16;
528
529 case PIPE_FORMAT_R11G11B10_FLOAT:
530 return V_0280A0_COLOR_10_11_11_FLOAT;
531
532 /* 64-bit buffers. */
533 case PIPE_FORMAT_R16G16B16_USCALED:
534 case PIPE_FORMAT_R16G16B16A16_USCALED:
535 case PIPE_FORMAT_R16G16B16_SSCALED:
536 case PIPE_FORMAT_R16G16B16A16_UINT:
537 case PIPE_FORMAT_R16G16B16A16_SINT:
538 case PIPE_FORMAT_R16G16B16A16_SSCALED:
539 case PIPE_FORMAT_R16G16B16A16_UNORM:
540 case PIPE_FORMAT_R16G16B16A16_SNORM:
541 return V_0280A0_COLOR_16_16_16_16;
542
543 case PIPE_FORMAT_R16G16B16_FLOAT:
544 case PIPE_FORMAT_R16G16B16A16_FLOAT:
545 return V_0280A0_COLOR_16_16_16_16_FLOAT;
546
547 case PIPE_FORMAT_R32G32_FLOAT:
548 return V_0280A0_COLOR_32_32_FLOAT;
549
550 case PIPE_FORMAT_R32G32_USCALED:
551 case PIPE_FORMAT_R32G32_SSCALED:
552 case PIPE_FORMAT_R32G32_SINT:
553 case PIPE_FORMAT_R32G32_UINT:
554 return V_0280A0_COLOR_32_32;
555
556 /* 96-bit buffers. */
557 case PIPE_FORMAT_R32G32B32_FLOAT:
558 return V_0280A0_COLOR_32_32_32_FLOAT;
559
560 /* 128-bit buffers. */
561 case PIPE_FORMAT_R32G32B32A32_FLOAT:
562 return V_0280A0_COLOR_32_32_32_32_FLOAT;
563 case PIPE_FORMAT_R32G32B32A32_SNORM:
564 case PIPE_FORMAT_R32G32B32A32_UNORM:
565 case PIPE_FORMAT_R32G32B32A32_SSCALED:
566 case PIPE_FORMAT_R32G32B32A32_USCALED:
567 case PIPE_FORMAT_R32G32B32A32_SINT:
568 case PIPE_FORMAT_R32G32B32A32_UINT:
569 return V_0280A0_COLOR_32_32_32_32;
570
571 /* YUV buffers. */
572 case PIPE_FORMAT_UYVY:
573 case PIPE_FORMAT_YUYV:
574 default:
575 return ~0U; /* Unsupported. */
576 }
577 }
578
579 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
580 {
581 if (R600_BIG_ENDIAN) {
582 switch(colorformat) {
583 case V_0280A0_COLOR_4_4:
584 return ENDIAN_NONE;
585
586 /* 8-bit buffers. */
587 case V_0280A0_COLOR_8:
588 return ENDIAN_NONE;
589
590 /* 16-bit buffers. */
591 case V_0280A0_COLOR_5_6_5:
592 case V_0280A0_COLOR_1_5_5_5:
593 case V_0280A0_COLOR_4_4_4_4:
594 case V_0280A0_COLOR_16:
595 case V_0280A0_COLOR_8_8:
596 return ENDIAN_8IN16;
597
598 /* 32-bit buffers. */
599 case V_0280A0_COLOR_8_8_8_8:
600 case V_0280A0_COLOR_2_10_10_10:
601 case V_0280A0_COLOR_8_24:
602 case V_0280A0_COLOR_24_8:
603 case V_0280A0_COLOR_32_FLOAT:
604 case V_0280A0_COLOR_16_16_FLOAT:
605 case V_0280A0_COLOR_16_16:
606 return ENDIAN_8IN32;
607
608 /* 64-bit buffers. */
609 case V_0280A0_COLOR_16_16_16_16:
610 case V_0280A0_COLOR_16_16_16_16_FLOAT:
611 return ENDIAN_8IN16;
612
613 case V_0280A0_COLOR_32_32_FLOAT:
614 case V_0280A0_COLOR_32_32:
615 case V_0280A0_COLOR_X24_8_32_FLOAT:
616 return ENDIAN_8IN32;
617
618 /* 128-bit buffers. */
619 case V_0280A0_COLOR_32_32_32_FLOAT:
620 case V_0280A0_COLOR_32_32_32_32_FLOAT:
621 case V_0280A0_COLOR_32_32_32_32:
622 return ENDIAN_8IN32;
623 default:
624 return ENDIAN_NONE; /* Unsupported. */
625 }
626 } else {
627 return ENDIAN_NONE;
628 }
629 }
630
631 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
632 {
633 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
634 }
635
636 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
637 {
638 return r600_translate_colorformat(format) != ~0U &&
639 r600_translate_colorswap(format) != ~0U;
640 }
641
642 static bool r600_is_zs_format_supported(enum pipe_format format)
643 {
644 return r600_translate_dbformat(format) != ~0U;
645 }
646
647 boolean r600_is_format_supported(struct pipe_screen *screen,
648 enum pipe_format format,
649 enum pipe_texture_target target,
650 unsigned sample_count,
651 unsigned usage)
652 {
653 unsigned retval = 0;
654
655 if (target >= PIPE_MAX_TEXTURE_TYPES) {
656 R600_ERR("r600: unsupported texture type %d\n", target);
657 return FALSE;
658 }
659
660 if (!util_format_is_supported(format, usage))
661 return FALSE;
662
663 /* Multisample */
664 if (sample_count > 1)
665 return FALSE;
666
667 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
668 r600_is_sampler_format_supported(screen, format)) {
669 retval |= PIPE_BIND_SAMPLER_VIEW;
670 }
671
672 if ((usage & (PIPE_BIND_RENDER_TARGET |
673 PIPE_BIND_DISPLAY_TARGET |
674 PIPE_BIND_SCANOUT |
675 PIPE_BIND_SHARED)) &&
676 r600_is_colorbuffer_format_supported(format)) {
677 retval |= usage &
678 (PIPE_BIND_RENDER_TARGET |
679 PIPE_BIND_DISPLAY_TARGET |
680 PIPE_BIND_SCANOUT |
681 PIPE_BIND_SHARED);
682 }
683
684 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
685 r600_is_zs_format_supported(format)) {
686 retval |= PIPE_BIND_DEPTH_STENCIL;
687 }
688
689 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
690 r600_is_vertex_format_supported(format)) {
691 retval |= PIPE_BIND_VERTEX_BUFFER;
692 }
693
694 if (usage & PIPE_BIND_TRANSFER_READ)
695 retval |= PIPE_BIND_TRANSFER_READ;
696 if (usage & PIPE_BIND_TRANSFER_WRITE)
697 retval |= PIPE_BIND_TRANSFER_WRITE;
698
699 return retval == usage;
700 }
701
702 void r600_polygon_offset_update(struct r600_context *rctx)
703 {
704 struct r600_pipe_state state;
705
706 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
707 state.nregs = 0;
708 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
709 float offset_units = rctx->rasterizer->offset_units;
710 unsigned offset_db_fmt_cntl = 0, depth;
711
712 switch (rctx->framebuffer.zsbuf->texture->format) {
713 case PIPE_FORMAT_Z24X8_UNORM:
714 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
715 depth = -24;
716 offset_units *= 2.0f;
717 break;
718 case PIPE_FORMAT_Z32_FLOAT:
719 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
720 depth = -23;
721 offset_units *= 1.0f;
722 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
723 break;
724 case PIPE_FORMAT_Z16_UNORM:
725 depth = -16;
726 offset_units *= 4.0f;
727 break;
728 default:
729 return;
730 }
731 /* FIXME some of those reg can be computed with cso */
732 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
733 r600_pipe_state_add_reg(&state,
734 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
735 fui(rctx->rasterizer->offset_scale), NULL, 0);
736 r600_pipe_state_add_reg(&state,
737 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
738 fui(offset_units), NULL, 0);
739 r600_pipe_state_add_reg(&state,
740 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
741 fui(rctx->rasterizer->offset_scale), NULL, 0);
742 r600_pipe_state_add_reg(&state,
743 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
744 fui(offset_units), NULL, 0);
745 r600_pipe_state_add_reg(&state,
746 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
747 offset_db_fmt_cntl, NULL, 0);
748 r600_context_pipe_state_set(rctx, &state);
749 }
750 }
751
752 static void r600_set_blend_color(struct pipe_context *ctx,
753 const struct pipe_blend_color *state)
754 {
755 struct r600_context *rctx = (struct r600_context *)ctx;
756 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
757
758 if (rstate == NULL)
759 return;
760
761 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
762 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), NULL, 0);
763 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), NULL, 0);
764 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), NULL, 0);
765 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), NULL, 0);
766 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
767 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
768 r600_context_pipe_state_set(rctx, rstate);
769 }
770
771 static void *r600_create_blend_state(struct pipe_context *ctx,
772 const struct pipe_blend_state *state)
773 {
774 struct r600_context *rctx = (struct r600_context *)ctx;
775 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
776 struct r600_pipe_state *rstate;
777 uint32_t color_control = 0, target_mask;
778
779 if (blend == NULL) {
780 return NULL;
781 }
782 rstate = &blend->rstate;
783
784 rstate->id = R600_PIPE_STATE_BLEND;
785
786 target_mask = 0;
787
788 /* R600 does not support per-MRT blends */
789 if (rctx->family > CHIP_R600)
790 color_control |= S_028808_PER_MRT_BLEND(1);
791 if (state->logicop_enable) {
792 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
793 } else {
794 color_control |= (0xcc << 16);
795 }
796 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
797 if (state->independent_blend_enable) {
798 for (int i = 0; i < 8; i++) {
799 if (state->rt[i].blend_enable) {
800 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
801 }
802 target_mask |= (state->rt[i].colormask << (4 * i));
803 }
804 } else {
805 for (int i = 0; i < 8; i++) {
806 if (state->rt[0].blend_enable) {
807 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
808 }
809 target_mask |= (state->rt[0].colormask << (4 * i));
810 }
811 }
812 blend->cb_target_mask = target_mask;
813 blend->cb_color_control = color_control;
814
815 for (int i = 0; i < 8; i++) {
816 /* state->rt entries > 0 only written if independent blending */
817 const int j = state->independent_blend_enable ? i : 0;
818
819 unsigned eqRGB = state->rt[j].rgb_func;
820 unsigned srcRGB = state->rt[j].rgb_src_factor;
821 unsigned dstRGB = state->rt[j].rgb_dst_factor;
822
823 unsigned eqA = state->rt[j].alpha_func;
824 unsigned srcA = state->rt[j].alpha_src_factor;
825 unsigned dstA = state->rt[j].alpha_dst_factor;
826 uint32_t bc = 0;
827
828 if (!state->rt[j].blend_enable)
829 continue;
830
831 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
832 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
833 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
834
835 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
836 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
837 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
838 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
839 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
840 }
841
842 /* R600 does not support per-MRT blends */
843 if (rctx->family > CHIP_R600)
844 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, NULL, 0);
845 if (i == 0)
846 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, NULL, 0);
847 }
848 return rstate;
849 }
850
851 static void *r600_create_dsa_state(struct pipe_context *ctx,
852 const struct pipe_depth_stencil_alpha_state *state)
853 {
854 struct r600_context *rctx = (struct r600_context *)ctx;
855 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
856 unsigned db_depth_control, alpha_test_control, alpha_ref;
857 unsigned db_render_override, db_render_control;
858 struct r600_pipe_state *rstate;
859
860 if (dsa == NULL) {
861 return NULL;
862 }
863
864 dsa->valuemask[0] = state->stencil[0].valuemask;
865 dsa->valuemask[1] = state->stencil[1].valuemask;
866 dsa->writemask[0] = state->stencil[0].writemask;
867 dsa->writemask[1] = state->stencil[1].writemask;
868
869 rstate = &dsa->rstate;
870
871 rstate->id = R600_PIPE_STATE_DSA;
872 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
873 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
874 S_028800_ZFUNC(state->depth.func);
875
876 /* stencil */
877 if (state->stencil[0].enabled) {
878 db_depth_control |= S_028800_STENCIL_ENABLE(1);
879 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
880 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
881 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
882 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
883
884 if (state->stencil[1].enabled) {
885 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
886 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
887 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
888 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
889 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
890 }
891 }
892
893 /* alpha */
894 alpha_test_control = 0;
895 alpha_ref = 0;
896 if (state->alpha.enabled) {
897 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
898 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
899 alpha_ref = fui(state->alpha.ref_value);
900 }
901 dsa->alpha_ref = alpha_ref;
902
903 /* misc */
904 db_render_control = 0;
905 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
906 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
907 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
908 /* TODO db_render_override depends on query */
909 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, NULL, 0);
910 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, NULL, 0);
911 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0);
912 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, NULL, 0);
913 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, NULL, 0);
914 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, NULL, 0);
915 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0);
916 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, NULL, 0);
917 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, NULL, 0);
918 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, NULL, 0);
919 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, NULL, 0);
920 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, NULL, 0);
921
922 dsa->db_render_override = db_render_override;
923 dsa->db_render_control = db_render_control;
924
925 return rstate;
926 }
927
928 static void *r600_create_rs_state(struct pipe_context *ctx,
929 const struct pipe_rasterizer_state *state)
930 {
931 struct r600_context *rctx = (struct r600_context *)ctx;
932 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
933 struct r600_pipe_state *rstate;
934 unsigned tmp;
935 unsigned prov_vtx = 1, polygon_dual_mode;
936 unsigned clip_rule;
937 unsigned sc_mode_cntl;
938 float psize_min, psize_max;
939
940 if (rs == NULL) {
941 return NULL;
942 }
943
944 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
945 state->fill_back != PIPE_POLYGON_MODE_FILL);
946
947 if (state->flatshade_first)
948 prov_vtx = 0;
949
950 rstate = &rs->rstate;
951 rs->flatshade = state->flatshade;
952 rs->sprite_coord_enable = state->sprite_coord_enable;
953 rs->two_side = state->light_twoside;
954 rs->clip_plane_enable = state->clip_plane_enable;
955 rs->pa_sc_line_stipple = state->line_stipple_enable ?
956 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
957 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
958 rs->pa_su_sc_mode_cntl =
959 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
960 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
961 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
962 S_028814_FACE(!state->front_ccw) |
963 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
964 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
965 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
966 S_028814_POLY_MODE(polygon_dual_mode) |
967 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
968 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
969 rs->pa_cl_clip_cntl =
970 S_028810_PS_UCP_MODE(3) |
971 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
972 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
973 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
974
975 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
976 /* offset */
977 rs->offset_units = state->offset_units;
978 rs->offset_scale = state->offset_scale * 12.0f;
979
980 rstate->id = R600_PIPE_STATE_RASTERIZER;
981 tmp = S_0286D4_FLAT_SHADE_ENA(1);
982 if (state->sprite_coord_enable) {
983 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
984 S_0286D4_PNT_SPRITE_OVRD_X(2) |
985 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
986 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
987 S_0286D4_PNT_SPRITE_OVRD_W(1);
988 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
989 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
990 }
991 }
992 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0);
993
994 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, NULL, 0);
995 /* point size 12.4 fixed point */
996 tmp = (unsigned)(state->point_size * 8.0);
997 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0);
998
999 if (state->point_size_per_vertex) {
1000 psize_min = util_get_min_point_size(state);
1001 psize_max = 8192;
1002 } else {
1003 /* Force the point size to be as if the vertex output was disabled. */
1004 psize_min = state->point_size;
1005 psize_max = state->point_size;
1006 }
1007 /* Divide by two, because 0.5 = 1 pixel. */
1008 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
1009 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
1010 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
1011 NULL, 0);
1012
1013 tmp = (unsigned)state->line_width * 8;
1014 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0);
1015
1016 if (rctx->chip_class >= R700)
1017 sc_mode_cntl = 0x514002;
1018 else
1019 sc_mode_cntl = 0x4102;
1020 sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
1021
1022 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl,
1023 NULL, 0);
1024 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, NULL, 0);
1025 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, NULL, 0);
1026
1027 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
1028 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
1029 NULL, 0);
1030
1031 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, NULL, 0);
1032 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, NULL, 0);
1033 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, NULL, 0);
1034 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, NULL, 0);
1035 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
1036 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, NULL, 0);
1037 return rstate;
1038 }
1039
1040 static void *r600_create_sampler_state(struct pipe_context *ctx,
1041 const struct pipe_sampler_state *state)
1042 {
1043 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
1044 struct r600_pipe_state *rstate;
1045 union util_color uc;
1046 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
1047
1048 if (ss == NULL) {
1049 return NULL;
1050 }
1051
1052 ss->seamless_cube_map = state->seamless_cube_map;
1053 rstate = &ss->rstate;
1054 rstate->id = R600_PIPE_STATE_SAMPLER;
1055 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1056 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
1057 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1058 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1059 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1060 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
1061 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
1062 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1063 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
1064 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1065 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
1066 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
1067 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1068 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1069 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), NULL, 0);
1070 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), NULL, 0);
1071 if (uc.ui) {
1072 r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
1073 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
1074 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
1075 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
1076 }
1077 return rstate;
1078 }
1079
1080 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
1081 struct pipe_resource *texture,
1082 const struct pipe_sampler_view *state)
1083 {
1084 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
1085 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1086 struct r600_pipe_resource_state *rstate;
1087 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1088 unsigned format, endian;
1089 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1090 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1091 unsigned width, height, depth, offset_level, last_level;
1092
1093 if (view == NULL)
1094 return NULL;
1095 rstate = &view->state;
1096
1097 /* initialize base object */
1098 view->base = *state;
1099 view->base.texture = NULL;
1100 pipe_reference(NULL, &texture->reference);
1101 view->base.texture = texture;
1102 view->base.reference.count = 1;
1103 view->base.context = ctx;
1104
1105 swizzle[0] = state->swizzle_r;
1106 swizzle[1] = state->swizzle_g;
1107 swizzle[2] = state->swizzle_b;
1108 swizzle[3] = state->swizzle_a;
1109
1110 format = r600_translate_texformat(ctx->screen, state->format,
1111 swizzle,
1112 &word4, &yuv_format);
1113 if (format == ~0) {
1114 format = 0;
1115 }
1116
1117 if (tmp->depth && !tmp->is_flushing_texture) {
1118 r600_texture_depth_flush(ctx, texture, TRUE);
1119 tmp = tmp->flushed_depth_texture;
1120 }
1121
1122 endian = r600_colorformat_endian_swap(format);
1123
1124 offset_level = state->u.tex.first_level;
1125 last_level = state->u.tex.last_level - offset_level;
1126 if (!rscreen->use_surface) {
1127 width = u_minify(texture->width0, offset_level);
1128 height = u_minify(texture->height0, offset_level);
1129 depth = u_minify(texture->depth0, offset_level);
1130
1131 pitch = align(tmp->pitch_in_blocks[offset_level] *
1132 util_format_get_blockwidth(state->format), 8);
1133 array_mode = tmp->array_mode[offset_level];
1134 tile_type = tmp->tile_type;
1135
1136 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1137 height = 1;
1138 depth = texture->array_size;
1139 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1140 depth = texture->array_size;
1141 }
1142
1143 rstate->bo[0] = &tmp->resource;
1144 rstate->bo[1] = &tmp->resource;
1145 rstate->bo_usage[0] = RADEON_USAGE_READ;
1146 rstate->bo_usage[1] = RADEON_USAGE_READ;
1147
1148 rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1149 S_038000_TILE_MODE(array_mode) |
1150 S_038000_TILE_TYPE(tile_type) |
1151 S_038000_PITCH((pitch / 8) - 1) |
1152 S_038000_TEX_WIDTH(width - 1));
1153 rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
1154 S_038004_TEX_DEPTH(depth - 1) |
1155 S_038004_DATA_FORMAT(format));
1156 rstate->val[2] = tmp->offset[offset_level] >> 8;
1157 rstate->val[3] = tmp->offset[offset_level+1] >> 8;
1158 rstate->val[4] = (word4 |
1159 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1160 S_038010_REQUEST_SIZE(1) |
1161 S_038010_ENDIAN_SWAP(endian) |
1162 S_038010_BASE_LEVEL(0));
1163 rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
1164 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1165 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1166 rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1167 S_038018_MAX_ANISO(4 /* max 16 samples */));
1168 } else {
1169 width = tmp->surface.level[offset_level].npix_x;
1170 height = tmp->surface.level[offset_level].npix_y;
1171 depth = tmp->surface.level[offset_level].npix_z;
1172 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1173 tile_type = tmp->tile_type;
1174
1175 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1176 height = 1;
1177 depth = texture->array_size;
1178 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1179 depth = texture->array_size;
1180 }
1181 switch (tmp->surface.level[offset_level].mode) {
1182 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1183 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1184 break;
1185 case RADEON_SURF_MODE_1D:
1186 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1187 break;
1188 case RADEON_SURF_MODE_2D:
1189 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1190 break;
1191 case RADEON_SURF_MODE_LINEAR:
1192 default:
1193 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1194 break;
1195 }
1196
1197 rstate->bo[0] = &tmp->resource;
1198 rstate->bo[1] = &tmp->resource;
1199 rstate->bo_usage[0] = RADEON_USAGE_READ;
1200 rstate->bo_usage[1] = RADEON_USAGE_READ;
1201
1202 rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1203 S_038000_TILE_MODE(array_mode) |
1204 S_038000_TILE_TYPE(tile_type) |
1205 S_038000_PITCH((pitch / 8) - 1) |
1206 S_038000_TEX_WIDTH(width - 1));
1207 rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
1208 S_038004_TEX_DEPTH(depth - 1) |
1209 S_038004_DATA_FORMAT(format));
1210 rstate->val[2] = tmp->surface.level[offset_level].offset >> 8;
1211 if (offset_level >= tmp->surface.last_level) {
1212 rstate->val[3] = tmp->surface.level[offset_level].offset >> 8;
1213 } else {
1214 rstate->val[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1215 }
1216 rstate->val[4] = (word4 |
1217 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1218 S_038010_REQUEST_SIZE(1) |
1219 S_038010_ENDIAN_SWAP(endian) |
1220 S_038010_BASE_LEVEL(0));
1221 rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
1222 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1223 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1224 rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1225 S_038018_MAX_ANISO(4 /* max 16 samples */));
1226 }
1227 return &view->base;
1228 }
1229
1230 static void r600_set_sampler_views(struct r600_context *rctx,
1231 struct r600_textures_info *dst,
1232 unsigned count,
1233 struct pipe_sampler_view **views,
1234 void (*set_resource)(struct r600_context*, struct r600_pipe_resource_state*, unsigned))
1235 {
1236 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
1237 unsigned i;
1238
1239 if (count)
1240 r600_inval_texture_cache(rctx);
1241
1242 for (i = 0; i < count; i++) {
1243 if (rviews[i]) {
1244 if (((struct r600_resource_texture *)rviews[i]->base.texture)->depth)
1245 rctx->have_depth_texture = true;
1246
1247 /* Changing from array to non-arrays textures and vice versa requires updating TEX_ARRAY_OVERRIDE. */
1248 if ((rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1249 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i])
1250 dst->samplers_dirty = true;
1251
1252 set_resource(rctx, &rviews[i]->state, i + R600_MAX_CONST_BUFFERS);
1253 } else {
1254 set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS);
1255 }
1256
1257 pipe_sampler_view_reference(
1258 (struct pipe_sampler_view **)&dst->views[i],
1259 views[i]);
1260 }
1261
1262 for (i = count; i < dst->n_views; i++) {
1263 if (dst->views[i]) {
1264 set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS);
1265 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], NULL);
1266 }
1267 }
1268
1269 dst->n_views = count;
1270 }
1271
1272 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1273 struct pipe_sampler_view **views)
1274 {
1275 struct r600_context *rctx = (struct r600_context *)ctx;
1276 r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views,
1277 r600_context_pipe_state_set_vs_resource);
1278 }
1279
1280 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1281 struct pipe_sampler_view **views)
1282 {
1283 struct r600_context *rctx = (struct r600_context *)ctx;
1284 r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views,
1285 r600_context_pipe_state_set_ps_resource);
1286 }
1287
1288 static void r600_set_seamless_cubemap(struct r600_context *rctx, boolean enable)
1289 {
1290 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1291 if (rstate == NULL)
1292 return;
1293
1294 rstate->id = R600_PIPE_STATE_SEAMLESS_CUBEMAP;
1295 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1296 (enable ? 0 : S_009508_DISABLE_CUBE_WRAP(1)) |
1297 S_009508_DISABLE_CUBE_ANISO(1) |
1298 S_009508_SYNC_GRADIENT(1) |
1299 S_009508_SYNC_WALKER(1) |
1300 S_009508_SYNC_ALIGNER(1),
1301 NULL, 0);
1302
1303 free(rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP]);
1304 rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP] = rstate;
1305 r600_context_pipe_state_set(rctx, rstate);
1306 }
1307
1308 static void r600_bind_samplers(struct r600_context *rctx,
1309 struct r600_textures_info *dst,
1310 unsigned count, void **states)
1311 {
1312 memcpy(dst->samplers, states, sizeof(void*) * count);
1313 dst->n_samplers = count;
1314 dst->samplers_dirty = true;
1315 }
1316
1317 static void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states)
1318 {
1319 struct r600_context *rctx = (struct r600_context *)ctx;
1320 r600_bind_samplers(rctx, &rctx->vs_samplers, count, states);
1321 }
1322
1323 static void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states)
1324 {
1325 struct r600_context *rctx = (struct r600_context *)ctx;
1326 r600_bind_samplers(rctx, &rctx->ps_samplers, count, states);
1327 }
1328
1329 static void r600_update_samplers(struct r600_context *rctx,
1330 struct r600_textures_info *tex,
1331 void (*set_sampler)(struct r600_context*, struct r600_pipe_state*, unsigned))
1332 {
1333 unsigned i;
1334
1335 if (tex->samplers_dirty) {
1336 int seamless = -1;
1337 for (i = 0; i < tex->n_samplers; i++) {
1338 if (!tex->samplers[i])
1339 continue;
1340
1341 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1342 * filtering between layers.
1343 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. */
1344 if (tex->views[i]) {
1345 if (tex->views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1346 tex->views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
1347 tex->samplers[i]->rstate.regs[0].value |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1348 tex->is_array_sampler[i] = true;
1349 } else {
1350 tex->samplers[i]->rstate.regs[0].value &= C_03C000_TEX_ARRAY_OVERRIDE;
1351 tex->is_array_sampler[i] = false;
1352 }
1353 }
1354
1355 set_sampler(rctx, &tex->samplers[i]->rstate, i);
1356
1357 if (tex->samplers[i])
1358 seamless = tex->samplers[i]->seamless_cube_map;
1359 }
1360
1361 if (seamless != -1)
1362 r600_set_seamless_cubemap(rctx, seamless);
1363
1364 tex->samplers_dirty = false;
1365 }
1366 }
1367
1368 void r600_update_sampler_states(struct r600_context *rctx)
1369 {
1370 r600_update_samplers(rctx, &rctx->vs_samplers,
1371 r600_context_pipe_state_set_vs_sampler);
1372 r600_update_samplers(rctx, &rctx->ps_samplers,
1373 r600_context_pipe_state_set_ps_sampler);
1374 }
1375
1376 static void r600_set_clip_state(struct pipe_context *ctx,
1377 const struct pipe_clip_state *state)
1378 {
1379 struct r600_context *rctx = (struct r600_context *)ctx;
1380 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1381 struct pipe_resource * cbuf;
1382
1383 if (rstate == NULL)
1384 return;
1385
1386 rctx->clip = *state;
1387 rstate->id = R600_PIPE_STATE_CLIP;
1388 for (int i = 0; i < 6; i++) {
1389 r600_pipe_state_add_reg(rstate,
1390 R_028E20_PA_CL_UCP0_X + i * 16,
1391 fui(state->ucp[i][0]), NULL, 0);
1392 r600_pipe_state_add_reg(rstate,
1393 R_028E24_PA_CL_UCP0_Y + i * 16,
1394 fui(state->ucp[i][1]) , NULL, 0);
1395 r600_pipe_state_add_reg(rstate,
1396 R_028E28_PA_CL_UCP0_Z + i * 16,
1397 fui(state->ucp[i][2]), NULL, 0);
1398 r600_pipe_state_add_reg(rstate,
1399 R_028E2C_PA_CL_UCP0_W + i * 16,
1400 fui(state->ucp[i][3]), NULL, 0);
1401 }
1402
1403 free(rctx->states[R600_PIPE_STATE_CLIP]);
1404 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1405 r600_context_pipe_state_set(rctx, rstate);
1406
1407 cbuf = pipe_user_buffer_create(ctx->screen,
1408 state->ucp,
1409 4*4*8, /* 8*4 floats */
1410 PIPE_BIND_CONSTANT_BUFFER);
1411 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, cbuf);
1412 pipe_resource_reference(&cbuf, NULL);
1413 }
1414
1415 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1416 const struct pipe_poly_stipple *state)
1417 {
1418 }
1419
1420 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1421 {
1422 }
1423
1424 static void r600_set_scissor_state(struct pipe_context *ctx,
1425 const struct pipe_scissor_state *state)
1426 {
1427 struct r600_context *rctx = (struct r600_context *)ctx;
1428 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1429 uint32_t tl, br;
1430
1431 if (rstate == NULL)
1432 return;
1433
1434 rstate->id = R600_PIPE_STATE_SCISSOR;
1435 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1436 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1437 r600_pipe_state_add_reg(rstate,
1438 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1439 NULL, 0);
1440 r600_pipe_state_add_reg(rstate,
1441 R_028214_PA_SC_CLIPRECT_0_BR, br,
1442 NULL, 0);
1443 r600_pipe_state_add_reg(rstate,
1444 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1445 NULL, 0);
1446 r600_pipe_state_add_reg(rstate,
1447 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1448 NULL, 0);
1449 r600_pipe_state_add_reg(rstate,
1450 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1451 NULL, 0);
1452 r600_pipe_state_add_reg(rstate,
1453 R_028224_PA_SC_CLIPRECT_2_BR, br,
1454 NULL, 0);
1455 r600_pipe_state_add_reg(rstate,
1456 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1457 NULL, 0);
1458 r600_pipe_state_add_reg(rstate,
1459 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1460 NULL, 0);
1461
1462 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1463 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1464 r600_context_pipe_state_set(rctx, rstate);
1465 }
1466
1467 static void r600_set_viewport_state(struct pipe_context *ctx,
1468 const struct pipe_viewport_state *state)
1469 {
1470 struct r600_context *rctx = (struct r600_context *)ctx;
1471 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1472
1473 if (rstate == NULL)
1474 return;
1475
1476 rctx->viewport = *state;
1477 rstate->id = R600_PIPE_STATE_VIEWPORT;
1478 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, NULL, 0);
1479 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, NULL, 0);
1480 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0);
1481 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0);
1482 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0);
1483 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0);
1484 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0);
1485 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0);
1486 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, NULL, 0);
1487
1488 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1489 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1490 r600_context_pipe_state_set(rctx, rstate);
1491 }
1492
1493 static void r600_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1494 const struct pipe_framebuffer_state *state, int cb)
1495 {
1496 struct r600_screen *rscreen = rctx->screen;
1497 struct r600_resource_texture *rtex;
1498 struct r600_surface *surf;
1499 unsigned level = state->cbufs[cb]->u.tex.level;
1500 unsigned pitch, slice;
1501 unsigned color_info;
1502 unsigned format, swap, ntype, endian;
1503 unsigned offset;
1504 const struct util_format_description *desc;
1505 int i;
1506 unsigned blend_bypass = 0, blend_clamp = 1;
1507
1508 surf = (struct r600_surface *)state->cbufs[cb];
1509 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1510
1511 if (rtex->depth)
1512 rctx->have_depth_fb = TRUE;
1513
1514 if (rtex->depth && !rtex->is_flushing_texture) {
1515 rtex = rtex->flushed_depth_texture;
1516 }
1517
1518 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1519 if (!rscreen->use_surface) {
1520 offset = r600_texture_get_offset(rtex,
1521 level, state->cbufs[cb]->u.tex.first_layer);
1522 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1523 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1524 if (slice) {
1525 slice = slice - 1;
1526 }
1527 color_info = S_0280A0_ARRAY_MODE(rtex->array_mode[level]);
1528 } else {
1529 offset = rtex->surface.level[level].offset;
1530 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1531 offset += rtex->surface.level[level].slice_size *
1532 state->cbufs[cb]->u.tex.first_layer;
1533 }
1534 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1535 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1536 if (slice) {
1537 slice = slice - 1;
1538 }
1539 color_info = 0;
1540 switch (rtex->surface.level[level].mode) {
1541 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1542 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1543 break;
1544 case RADEON_SURF_MODE_1D:
1545 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1546 break;
1547 case RADEON_SURF_MODE_2D:
1548 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1549 break;
1550 case RADEON_SURF_MODE_LINEAR:
1551 default:
1552 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1553 break;
1554 }
1555 }
1556 desc = util_format_description(surf->base.format);
1557
1558 for (i = 0; i < 4; i++) {
1559 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1560 break;
1561 }
1562 }
1563
1564 ntype = V_0280A0_NUMBER_UNORM;
1565 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1566 ntype = V_0280A0_NUMBER_SRGB;
1567 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1568 if (desc->channel[i].normalized)
1569 ntype = V_0280A0_NUMBER_SNORM;
1570 else if (desc->channel[i].pure_integer)
1571 ntype = V_0280A0_NUMBER_SINT;
1572 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1573 if (desc->channel[i].normalized)
1574 ntype = V_0280A0_NUMBER_UNORM;
1575 else if (desc->channel[i].pure_integer)
1576 ntype = V_0280A0_NUMBER_UINT;
1577 }
1578
1579 format = r600_translate_colorformat(surf->base.format);
1580 swap = r600_translate_colorswap(surf->base.format);
1581 if(rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
1582 endian = ENDIAN_NONE;
1583 } else {
1584 endian = r600_colorformat_endian_swap(format);
1585 }
1586
1587 /* set blend bypass according to docs if SINT/UINT or
1588 8/24 COLOR variants */
1589 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1590 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1591 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1592 blend_clamp = 0;
1593 blend_bypass = 1;
1594 }
1595
1596 color_info |= S_0280A0_FORMAT(format) |
1597 S_0280A0_COMP_SWAP(swap) |
1598 S_0280A0_BLEND_BYPASS(blend_bypass) |
1599 S_0280A0_BLEND_CLAMP(blend_clamp) |
1600 S_0280A0_NUMBER_TYPE(ntype) |
1601 S_0280A0_ENDIAN(endian);
1602
1603 /* EXPORT_NORM is an optimzation that can be enabled for better
1604 * performance in certain cases
1605 */
1606 if (rctx->chip_class == R600) {
1607 /* EXPORT_NORM can be enabled if:
1608 * - 11-bit or smaller UNORM/SNORM/SRGB
1609 * - BLEND_CLAMP is enabled
1610 * - BLEND_FLOAT32 is disabled
1611 */
1612 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1613 (desc->channel[i].size < 12 &&
1614 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1615 ntype != V_0280A0_NUMBER_UINT &&
1616 ntype != V_0280A0_NUMBER_SINT) &&
1617 G_0280A0_BLEND_CLAMP(color_info) &&
1618 !G_0280A0_BLEND_FLOAT32(color_info))
1619 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1620 } else {
1621 /* EXPORT_NORM can be enabled if:
1622 * - 11-bit or smaller UNORM/SNORM/SRGB
1623 * - 16-bit or smaller FLOAT
1624 */
1625 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1626 ((desc->channel[i].size < 12 &&
1627 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1628 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1629 (desc->channel[i].size < 17 &&
1630 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT)))
1631 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1632 }
1633
1634 r600_pipe_state_add_reg(rstate,
1635 R_028040_CB_COLOR0_BASE + cb * 4,
1636 offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE);
1637 r600_pipe_state_add_reg(rstate,
1638 R_0280A0_CB_COLOR0_INFO + cb * 4,
1639 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1640 r600_pipe_state_add_reg(rstate,
1641 R_028060_CB_COLOR0_SIZE + cb * 4,
1642 S_028060_PITCH_TILE_MAX(pitch) |
1643 S_028060_SLICE_TILE_MAX(slice),
1644 NULL, 0);
1645 if (!rscreen->use_surface) {
1646 r600_pipe_state_add_reg(rstate,
1647 R_028080_CB_COLOR0_VIEW + cb * 4,
1648 0x00000000, NULL, 0);
1649 } else {
1650 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1651 r600_pipe_state_add_reg(rstate,
1652 R_028080_CB_COLOR0_VIEW + cb * 4,
1653 0x00000000, NULL, 0);
1654 } else {
1655 r600_pipe_state_add_reg(rstate,
1656 R_028080_CB_COLOR0_VIEW + cb * 4,
1657 S_028080_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1658 S_028080_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer),
1659 NULL, 0);
1660 }
1661 }
1662 r600_pipe_state_add_reg(rstate,
1663 R_0280E0_CB_COLOR0_FRAG + cb * 4,
1664 0, &rtex->resource, RADEON_USAGE_READWRITE);
1665 r600_pipe_state_add_reg(rstate,
1666 R_0280C0_CB_COLOR0_TILE + cb * 4,
1667 0, &rtex->resource, RADEON_USAGE_READWRITE);
1668 r600_pipe_state_add_reg(rstate,
1669 R_028100_CB_COLOR0_MASK + cb * 4,
1670 0x00000000, NULL, 0);
1671 }
1672
1673 static void r600_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1674 const struct pipe_framebuffer_state *state)
1675 {
1676 struct r600_screen *rscreen = rctx->screen;
1677 struct r600_resource_texture *rtex;
1678 struct r600_surface *surf;
1679 unsigned level, pitch, slice, format, offset, array_mode;
1680
1681 if (state->zsbuf == NULL)
1682 return;
1683
1684 level = state->zsbuf->u.tex.level;
1685
1686 surf = (struct r600_surface *)state->zsbuf;
1687 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1688
1689 if (!rscreen->use_surface) {
1690 /* XXX remove this once tiling is properly supported */
1691 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1692 V_0280A0_ARRAY_1D_TILED_THIN1;
1693
1694 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1695 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
1696 level, state->zsbuf->u.tex.first_layer);
1697 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1698 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1699 if (slice) {
1700 slice = slice - 1;
1701 }
1702 } else {
1703 offset = rtex->surface.level[level].offset;
1704 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1705 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1706 if (slice) {
1707 slice = slice - 1;
1708 }
1709 switch (rtex->surface.level[level].mode) {
1710 case RADEON_SURF_MODE_2D:
1711 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1712 break;
1713 case RADEON_SURF_MODE_1D:
1714 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1715 case RADEON_SURF_MODE_LINEAR:
1716 default:
1717 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1718 break;
1719 }
1720 }
1721
1722 format = r600_translate_dbformat(state->zsbuf->texture->format);
1723
1724 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
1725 offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE);
1726 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1727 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1728 NULL, 0);
1729 if (!rscreen->use_surface) {
1730 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, NULL, 0);
1731 } else {
1732 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW,
1733 S_028004_SLICE_START(state->zsbuf->u.tex.first_layer) |
1734 S_028004_SLICE_MAX(state->zsbuf->u.tex.last_layer),
1735 NULL, 0);
1736 }
1737 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
1738 S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format),
1739 &rtex->resource, RADEON_USAGE_READWRITE);
1740 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1741 (surf->aligned_height / 8) - 1, NULL, 0);
1742 }
1743
1744 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1745 const struct pipe_framebuffer_state *state)
1746 {
1747 struct r600_context *rctx = (struct r600_context *)ctx;
1748 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1749 uint32_t shader_mask, tl, br, shader_control;
1750
1751 if (rstate == NULL)
1752 return;
1753
1754 r600_flush_framebuffer(rctx, false);
1755
1756 /* unreference old buffer and reference new one */
1757 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1758
1759 util_copy_framebuffer_state(&rctx->framebuffer, state);
1760
1761 /* build states */
1762 rctx->have_depth_fb = 0;
1763 for (int i = 0; i < state->nr_cbufs; i++) {
1764 r600_cb(rctx, rstate, state, i);
1765 }
1766 if (state->zsbuf) {
1767 r600_db(rctx, rstate, state);
1768 }
1769
1770 shader_mask = 0;
1771 shader_control = 0;
1772 for (int i = 0; i < state->nr_cbufs; i++) {
1773 shader_mask |= 0xf << (i * 4);
1774 shader_control |= 1 << i;
1775 }
1776 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1777 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1778
1779 r600_pipe_state_add_reg(rstate,
1780 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1781 NULL, 0);
1782 r600_pipe_state_add_reg(rstate,
1783 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1784 NULL, 0);
1785 r600_pipe_state_add_reg(rstate,
1786 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1787 NULL, 0);
1788 r600_pipe_state_add_reg(rstate,
1789 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1790 NULL, 0);
1791 r600_pipe_state_add_reg(rstate,
1792 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1793 NULL, 0);
1794 r600_pipe_state_add_reg(rstate,
1795 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1796 NULL, 0);
1797 r600_pipe_state_add_reg(rstate,
1798 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1799 NULL, 0);
1800 r600_pipe_state_add_reg(rstate,
1801 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1802 NULL, 0);
1803 r600_pipe_state_add_reg(rstate,
1804 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1805 NULL, 0);
1806 if (rctx->chip_class >= R700) {
1807 r600_pipe_state_add_reg(rstate,
1808 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1809 NULL, 0);
1810 }
1811
1812 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1813 shader_control, NULL, 0);
1814 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1815 shader_mask, NULL, 0);
1816 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1817 0x00000000, NULL, 0);
1818 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1819 0x00000000, NULL, 0);
1820 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1821 0x00000000, NULL, 0);
1822 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1823 0x01000000, NULL, 0);
1824 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1825 0x00000000, NULL, 0);
1826 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1827 0x000000FF, NULL, 0);
1828 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1829 0xFFFFFFFF, NULL, 0);
1830 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1831 0xFFFFFFFF, NULL, 0);
1832
1833 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1834 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1835 r600_context_pipe_state_set(rctx, rstate);
1836
1837 if (state->zsbuf) {
1838 r600_polygon_offset_update(rctx);
1839 }
1840 }
1841
1842 void r600_init_state_functions(struct r600_context *rctx)
1843 {
1844 rctx->context.create_blend_state = r600_create_blend_state;
1845 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1846 rctx->context.create_fs_state = r600_create_shader_state;
1847 rctx->context.create_rasterizer_state = r600_create_rs_state;
1848 rctx->context.create_sampler_state = r600_create_sampler_state;
1849 rctx->context.create_sampler_view = r600_create_sampler_view;
1850 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1851 rctx->context.create_vs_state = r600_create_shader_state;
1852 rctx->context.bind_blend_state = r600_bind_blend_state;
1853 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1854 rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
1855 rctx->context.bind_fs_state = r600_bind_ps_shader;
1856 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1857 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1858 rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
1859 rctx->context.bind_vs_state = r600_bind_vs_shader;
1860 rctx->context.delete_blend_state = r600_delete_state;
1861 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1862 rctx->context.delete_fs_state = r600_delete_ps_shader;
1863 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1864 rctx->context.delete_sampler_state = r600_delete_state;
1865 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1866 rctx->context.delete_vs_state = r600_delete_vs_shader;
1867 rctx->context.set_blend_color = r600_set_blend_color;
1868 rctx->context.set_clip_state = r600_set_clip_state;
1869 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1870 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1871 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1872 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1873 rctx->context.set_sample_mask = r600_set_sample_mask;
1874 rctx->context.set_scissor_state = r600_set_scissor_state;
1875 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1876 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1877 rctx->context.set_index_buffer = r600_set_index_buffer;
1878 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1879 rctx->context.set_viewport_state = r600_set_viewport_state;
1880 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1881 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1882 rctx->context.texture_barrier = r600_texture_barrier;
1883 rctx->context.create_stream_output_target = r600_create_so_target;
1884 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1885 rctx->context.set_stream_output_targets = r600_set_so_targets;
1886 }
1887
1888 void r600_adjust_gprs(struct r600_context *rctx)
1889 {
1890 struct r600_pipe_state rstate;
1891 unsigned num_ps_gprs = rctx->default_ps_gprs;
1892 unsigned num_vs_gprs = rctx->default_vs_gprs;
1893 unsigned tmp;
1894 int diff;
1895
1896 if (rctx->chip_class >= EVERGREEN)
1897 return;
1898
1899 if (!rctx->ps_shader || !rctx->vs_shader)
1900 return;
1901
1902 if (rctx->ps_shader->shader.bc.ngpr > rctx->default_ps_gprs)
1903 {
1904 diff = rctx->ps_shader->shader.bc.ngpr - rctx->default_ps_gprs;
1905 num_vs_gprs -= diff;
1906 num_ps_gprs += diff;
1907 }
1908
1909 if (rctx->vs_shader->shader.bc.ngpr > rctx->default_vs_gprs)
1910 {
1911 diff = rctx->vs_shader->shader.bc.ngpr - rctx->default_vs_gprs;
1912 num_ps_gprs -= diff;
1913 num_vs_gprs += diff;
1914 }
1915
1916 tmp = 0;
1917 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1918 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1919 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
1920 rstate.nregs = 0;
1921 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, NULL, 0);
1922
1923 r600_context_pipe_state_set(rctx, &rstate);
1924 }
1925
1926 void r600_init_config(struct r600_context *rctx)
1927 {
1928 int ps_prio;
1929 int vs_prio;
1930 int gs_prio;
1931 int es_prio;
1932 int num_ps_gprs;
1933 int num_vs_gprs;
1934 int num_gs_gprs;
1935 int num_es_gprs;
1936 int num_temp_gprs;
1937 int num_ps_threads;
1938 int num_vs_threads;
1939 int num_gs_threads;
1940 int num_es_threads;
1941 int num_ps_stack_entries;
1942 int num_vs_stack_entries;
1943 int num_gs_stack_entries;
1944 int num_es_stack_entries;
1945 enum radeon_family family;
1946 struct r600_pipe_state *rstate = &rctx->config;
1947 uint32_t tmp;
1948
1949 family = rctx->family;
1950 ps_prio = 0;
1951 vs_prio = 1;
1952 gs_prio = 2;
1953 es_prio = 3;
1954 switch (family) {
1955 case CHIP_R600:
1956 num_ps_gprs = 192;
1957 num_vs_gprs = 56;
1958 num_temp_gprs = 4;
1959 num_gs_gprs = 0;
1960 num_es_gprs = 0;
1961 num_ps_threads = 136;
1962 num_vs_threads = 48;
1963 num_gs_threads = 4;
1964 num_es_threads = 4;
1965 num_ps_stack_entries = 128;
1966 num_vs_stack_entries = 128;
1967 num_gs_stack_entries = 0;
1968 num_es_stack_entries = 0;
1969 break;
1970 case CHIP_RV630:
1971 case CHIP_RV635:
1972 num_ps_gprs = 84;
1973 num_vs_gprs = 36;
1974 num_temp_gprs = 4;
1975 num_gs_gprs = 0;
1976 num_es_gprs = 0;
1977 num_ps_threads = 144;
1978 num_vs_threads = 40;
1979 num_gs_threads = 4;
1980 num_es_threads = 4;
1981 num_ps_stack_entries = 40;
1982 num_vs_stack_entries = 40;
1983 num_gs_stack_entries = 32;
1984 num_es_stack_entries = 16;
1985 break;
1986 case CHIP_RV610:
1987 case CHIP_RV620:
1988 case CHIP_RS780:
1989 case CHIP_RS880:
1990 default:
1991 num_ps_gprs = 84;
1992 num_vs_gprs = 36;
1993 num_temp_gprs = 4;
1994 num_gs_gprs = 0;
1995 num_es_gprs = 0;
1996 num_ps_threads = 136;
1997 num_vs_threads = 48;
1998 num_gs_threads = 4;
1999 num_es_threads = 4;
2000 num_ps_stack_entries = 40;
2001 num_vs_stack_entries = 40;
2002 num_gs_stack_entries = 32;
2003 num_es_stack_entries = 16;
2004 break;
2005 case CHIP_RV670:
2006 num_ps_gprs = 144;
2007 num_vs_gprs = 40;
2008 num_temp_gprs = 4;
2009 num_gs_gprs = 0;
2010 num_es_gprs = 0;
2011 num_ps_threads = 136;
2012 num_vs_threads = 48;
2013 num_gs_threads = 4;
2014 num_es_threads = 4;
2015 num_ps_stack_entries = 40;
2016 num_vs_stack_entries = 40;
2017 num_gs_stack_entries = 32;
2018 num_es_stack_entries = 16;
2019 break;
2020 case CHIP_RV770:
2021 num_ps_gprs = 192;
2022 num_vs_gprs = 56;
2023 num_temp_gprs = 4;
2024 num_gs_gprs = 0;
2025 num_es_gprs = 0;
2026 num_ps_threads = 188;
2027 num_vs_threads = 60;
2028 num_gs_threads = 0;
2029 num_es_threads = 0;
2030 num_ps_stack_entries = 256;
2031 num_vs_stack_entries = 256;
2032 num_gs_stack_entries = 0;
2033 num_es_stack_entries = 0;
2034 break;
2035 case CHIP_RV730:
2036 case CHIP_RV740:
2037 num_ps_gprs = 84;
2038 num_vs_gprs = 36;
2039 num_temp_gprs = 4;
2040 num_gs_gprs = 0;
2041 num_es_gprs = 0;
2042 num_ps_threads = 188;
2043 num_vs_threads = 60;
2044 num_gs_threads = 0;
2045 num_es_threads = 0;
2046 num_ps_stack_entries = 128;
2047 num_vs_stack_entries = 128;
2048 num_gs_stack_entries = 0;
2049 num_es_stack_entries = 0;
2050 break;
2051 case CHIP_RV710:
2052 num_ps_gprs = 192;
2053 num_vs_gprs = 56;
2054 num_temp_gprs = 4;
2055 num_gs_gprs = 0;
2056 num_es_gprs = 0;
2057 num_ps_threads = 144;
2058 num_vs_threads = 48;
2059 num_gs_threads = 0;
2060 num_es_threads = 0;
2061 num_ps_stack_entries = 128;
2062 num_vs_stack_entries = 128;
2063 num_gs_stack_entries = 0;
2064 num_es_stack_entries = 0;
2065 break;
2066 }
2067
2068 rctx->default_ps_gprs = num_ps_gprs;
2069 rctx->default_vs_gprs = num_vs_gprs;
2070
2071 rstate->id = R600_PIPE_STATE_CONFIG;
2072
2073 /* SQ_CONFIG */
2074 tmp = 0;
2075 switch (family) {
2076 case CHIP_RV610:
2077 case CHIP_RV620:
2078 case CHIP_RS780:
2079 case CHIP_RS880:
2080 case CHIP_RV710:
2081 break;
2082 default:
2083 tmp |= S_008C00_VC_ENABLE(1);
2084 break;
2085 }
2086 tmp |= S_008C00_DX9_CONSTS(0);
2087 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2088 tmp |= S_008C00_PS_PRIO(ps_prio);
2089 tmp |= S_008C00_VS_PRIO(vs_prio);
2090 tmp |= S_008C00_GS_PRIO(gs_prio);
2091 tmp |= S_008C00_ES_PRIO(es_prio);
2092 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, NULL, 0);
2093
2094 /* SQ_GPR_RESOURCE_MGMT_1 */
2095 tmp = 0;
2096 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2097 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2098 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2099 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2100 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, NULL, 0);
2101
2102 /* SQ_GPR_RESOURCE_MGMT_2 */
2103 tmp = 0;
2104 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
2105 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2106 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, NULL, 0);
2107
2108 /* SQ_THREAD_RESOURCE_MGMT */
2109 tmp = 0;
2110 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
2111 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2112 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2113 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2114 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, NULL, 0);
2115
2116 /* SQ_STACK_RESOURCE_MGMT_1 */
2117 tmp = 0;
2118 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2119 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2120 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, NULL, 0);
2121
2122 /* SQ_STACK_RESOURCE_MGMT_2 */
2123 tmp = 0;
2124 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2125 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2126 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, NULL, 0);
2127
2128 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, NULL, 0);
2129 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, NULL, 0);
2130
2131 if (rctx->chip_class >= R700) {
2132 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, NULL, 0);
2133 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, NULL, 0);
2134 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, NULL, 0);
2135 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, NULL, 0);
2136 } else {
2137 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, NULL, 0);
2138 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, NULL, 0);
2139 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, NULL, 0);
2140 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, NULL, 0);
2141 }
2142 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, NULL, 0);
2143 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, NULL, 0);
2144 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, NULL, 0);
2145 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, NULL, 0);
2146 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, NULL, 0);
2147 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, NULL, 0);
2148 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, NULL, 0);
2149 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, NULL, 0);
2150 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, NULL, 0);
2151 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, NULL, 0);
2152 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, NULL, 0);
2153 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, NULL, 0);
2154 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, NULL, 0);
2155 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, NULL, 0);
2156 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, NULL, 0);
2157 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, NULL, 0);
2158 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, NULL, 0);
2159 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, NULL, 0);
2160 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, NULL, 0);
2161 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, NULL, 0);
2162 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, NULL, 0);
2163 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, NULL, 0);
2164 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, NULL, 0);
2165 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, NULL, 0);
2166 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, NULL, 0);
2167 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, NULL, 0);
2168
2169 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, NULL, 0);
2170 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, NULL, 0);
2171 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, NULL, 0);
2172 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, NULL, 0);
2173 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, NULL, 0);
2174 r600_context_pipe_state_set(rctx, rstate);
2175
2176 r600_set_seamless_cubemap(rctx, FALSE);
2177 }
2178
2179 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2180 {
2181 struct r600_context *rctx = (struct r600_context *)ctx;
2182 struct r600_pipe_state *rstate = &shader->rstate;
2183 struct r600_shader *rshader = &shader->shader;
2184 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2185 int pos_index = -1, face_index = -1;
2186 unsigned tmp, sid, ufi = 0;
2187 int need_linear = 0;
2188
2189 rstate->nregs = 0;
2190
2191 for (i = 0; i < rshader->ninput; i++) {
2192 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2193 pos_index = i;
2194 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2195 face_index = i;
2196
2197 sid = rshader->input[i].spi_sid;
2198
2199 tmp = S_028644_SEMANTIC(sid);
2200
2201 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2202 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2203 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2204 rctx->rasterizer && rctx->rasterizer->flatshade))
2205 tmp |= S_028644_FLAT_SHADE(1);
2206
2207 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2208 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2209 tmp |= S_028644_PT_SPRITE_TEX(1);
2210 }
2211
2212 if (rshader->input[i].centroid)
2213 tmp |= S_028644_SEL_CENTROID(1);
2214
2215 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2216 need_linear = 1;
2217 tmp |= S_028644_SEL_LINEAR(1);
2218 }
2219
2220 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2221 tmp, NULL, 0);
2222 }
2223
2224 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2225 for (i = 0; i < rshader->noutput; i++) {
2226 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2227 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2228 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2229 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1);
2230 }
2231 if (rshader->uses_kill)
2232 db_shader_control |= S_02880C_KILL_ENABLE(1);
2233
2234 exports_ps = 0;
2235 num_cout = 0;
2236 for (i = 0; i < rshader->noutput; i++) {
2237 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2238 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2239 exports_ps |= 1;
2240 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2241 num_cout++;
2242 }
2243 }
2244 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2245 if (!exports_ps) {
2246 /* always at least export 1 component per pixel */
2247 exports_ps = 2;
2248 }
2249
2250 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2251 S_0286CC_PERSP_GRADIENT_ENA(1)|
2252 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2253 spi_input_z = 0;
2254 if (pos_index != -1) {
2255 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2256 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2257 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2258 S_0286CC_BARYC_SAMPLE_CNTL(1));
2259 spi_input_z |= 1;
2260 }
2261
2262 spi_ps_in_control_1 = 0;
2263 if (face_index != -1) {
2264 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2265 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2266 }
2267
2268 /* HW bug in original R600 */
2269 if (rctx->family == CHIP_R600)
2270 ufi = 1;
2271
2272 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, NULL, 0);
2273 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, NULL, 0);
2274 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, NULL, 0);
2275 r600_pipe_state_add_reg(rstate,
2276 R_028840_SQ_PGM_START_PS,
2277 0, shader->bo, RADEON_USAGE_READ);
2278 r600_pipe_state_add_reg(rstate,
2279 R_028850_SQ_PGM_RESOURCES_PS,
2280 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2281 S_028850_STACK_SIZE(rshader->bc.nstack) |
2282 S_028850_UNCACHED_FIRST_INST(ufi),
2283 NULL, 0);
2284 r600_pipe_state_add_reg(rstate,
2285 R_028854_SQ_PGM_EXPORTS_PS,
2286 exports_ps, NULL, 0);
2287 r600_pipe_state_add_reg(rstate,
2288 R_0288CC_SQ_PGM_CF_OFFSET_PS,
2289 0x00000000, NULL, 0);
2290 /* only set some bits here, the other bits are set in the dsa state */
2291 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2292 db_shader_control,
2293 NULL, 0);
2294
2295 r600_pipe_state_add_reg(rstate,
2296 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
2297 NULL, 0);
2298
2299 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2300 if (rctx->rasterizer)
2301 shader->flatshade = rctx->rasterizer->flatshade;
2302 }
2303
2304 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2305 {
2306 struct r600_context *rctx = (struct r600_context *)ctx;
2307 struct r600_pipe_state *rstate = &shader->rstate;
2308 struct r600_shader *rshader = &shader->shader;
2309 unsigned spi_vs_out_id[10] = {};
2310 unsigned i, tmp, nparams = 0;
2311
2312 /* clear previous register */
2313 rstate->nregs = 0;
2314
2315 for (i = 0; i < rshader->noutput; i++) {
2316 if (rshader->output[i].spi_sid) {
2317 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2318 spi_vs_out_id[nparams / 4] |= tmp;
2319 nparams++;
2320 }
2321 }
2322
2323 for (i = 0; i < 10; i++) {
2324 r600_pipe_state_add_reg(rstate,
2325 R_028614_SPI_VS_OUT_ID_0 + i * 4,
2326 spi_vs_out_id[i], NULL, 0);
2327 }
2328
2329 /* Certain attributes (position, psize, etc.) don't count as params.
2330 * VS is required to export at least one param and r600_shader_from_tgsi()
2331 * takes care of adding a dummy export.
2332 */
2333 if (nparams < 1)
2334 nparams = 1;
2335
2336 r600_pipe_state_add_reg(rstate,
2337 R_0286C4_SPI_VS_OUT_CONFIG,
2338 S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2339 NULL, 0);
2340 r600_pipe_state_add_reg(rstate,
2341 R_028868_SQ_PGM_RESOURCES_VS,
2342 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2343 S_028868_STACK_SIZE(rshader->bc.nstack),
2344 NULL, 0);
2345 r600_pipe_state_add_reg(rstate,
2346 R_0288D0_SQ_PGM_CF_OFFSET_VS,
2347 0x00000000, NULL, 0);
2348 r600_pipe_state_add_reg(rstate,
2349 R_028858_SQ_PGM_START_VS,
2350 0, shader->bo, RADEON_USAGE_READ);
2351
2352 r600_pipe_state_add_reg(rstate,
2353 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2354 NULL, 0);
2355
2356 shader->pa_cl_vs_out_cntl =
2357 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2358 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2359 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2360 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2361 }
2362
2363 void r600_fetch_shader(struct pipe_context *ctx,
2364 struct r600_vertex_element *ve)
2365 {
2366 struct r600_pipe_state *rstate;
2367 struct r600_context *rctx = (struct r600_context *)ctx;
2368
2369 rstate = &ve->rstate;
2370 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2371 rstate->nregs = 0;
2372 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
2373 0x00000000, NULL, 0);
2374 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
2375 0x00000000, NULL, 0);
2376 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
2377 0,
2378 ve->fetch_shader, RADEON_USAGE_READ);
2379 }
2380
2381 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2382 {
2383 struct pipe_depth_stencil_alpha_state dsa;
2384 struct r600_pipe_state *rstate;
2385 struct r600_pipe_dsa *dsa_state;
2386 unsigned db_render_control;
2387 boolean quirk = false;
2388
2389 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2390 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2391 quirk = true;
2392
2393 memset(&dsa, 0, sizeof(dsa));
2394
2395 if (quirk) {
2396 dsa.depth.enabled = 1;
2397 dsa.depth.func = PIPE_FUNC_LEQUAL;
2398 dsa.stencil[0].enabled = 1;
2399 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2400 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2401 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2402 dsa.stencil[0].writemask = 0xff;
2403 }
2404
2405 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2406 dsa_state = (struct r600_pipe_dsa*)rstate;
2407
2408 db_render_control =
2409 S_028D0C_DEPTH_COPY_ENABLE(1) |
2410 S_028D0C_STENCIL_COPY_ENABLE(1) |
2411 S_028D0C_COPY_CENTROID(1);
2412
2413 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, NULL, 0);
2414
2415 dsa_state->db_render_control = db_render_control;
2416
2417 return rstate;
2418 }
2419
2420 void r600_pipe_init_buffer_resource(struct r600_context *rctx,
2421 struct r600_pipe_resource_state *rstate)
2422 {
2423 rstate->id = R600_PIPE_STATE_RESOURCE;
2424
2425 rstate->bo[0] = NULL;
2426 rstate->val[0] = 0;
2427 rstate->val[1] = 0;
2428 rstate->val[2] = 0;
2429 rstate->val[3] = 0;
2430 rstate->val[4] = 0;
2431 rstate->val[5] = 0;
2432 rstate->val[6] = 0xc0000000;
2433 }
2434
2435 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
2436 struct r600_resource *rbuffer,
2437 unsigned offset, unsigned stride,
2438 enum radeon_bo_usage usage)
2439 {
2440 rstate->val[0] = offset;
2441 rstate->bo[0] = rbuffer;
2442 rstate->bo_usage[0] = usage;
2443 rstate->val[1] = rbuffer->buf->size - offset - 1;
2444 rstate->val[2] = S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
2445 S_038008_STRIDE(stride);
2446 }