projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: clean up aniso state translation
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
145 {
146 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
147 }
148
149 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
150 {
151 return r600_translate_colorformat(chip, format) != ~0U &&
152 r600_translate_colorswap(format) != ~0U;
153 }
154
155 static bool r600_is_zs_format_supported(enum pipe_format format)
156 {
157 return r600_translate_dbformat(format) != ~0U;
158 }
159
160 boolean r600_is_format_supported(struct pipe_screen *screen,
161 enum pipe_format format,
162 enum pipe_texture_target target,
163 unsigned sample_count,
164 unsigned usage)
165 {
166 struct r600_screen *rscreen = (struct r600_screen*)screen;
167 unsigned retval = 0;
168
169 if (target >= PIPE_MAX_TEXTURE_TYPES) {
170 R600_ERR("r600: unsupported texture type %d\n", target);
171 return FALSE;
172 }
173
174 if (!util_format_is_supported(format, usage))
175 return FALSE;
176
177 if (sample_count > 1) {
178 if (!rscreen->has_msaa)
179 return FALSE;
180
181 /* R11G11B10 is broken on R6xx. */
182 if (rscreen->b.chip_class == R600 &&
183 format == PIPE_FORMAT_R11G11B10_FLOAT)
184 return FALSE;
185
186 /* MSAA integer colorbuffers hang. */
187 if (util_format_is_pure_integer(format) &&
188 !util_format_is_depth_or_stencil(format))
189 return FALSE;
190
191 switch (sample_count) {
192 case 2:
193 case 4:
194 case 8:
195 break;
196 default:
197 return FALSE;
198 }
199 }
200
201 if (usage & PIPE_BIND_SAMPLER_VIEW) {
202 if (target == PIPE_BUFFER) {
203 if (r600_is_vertex_format_supported(format))
204 retval |= PIPE_BIND_SAMPLER_VIEW;
205 } else {
206 if (r600_is_sampler_format_supported(screen, format))
207 retval |= PIPE_BIND_SAMPLER_VIEW;
208 }
209 }
210
211 if ((usage & (PIPE_BIND_RENDER_TARGET |
212 PIPE_BIND_DISPLAY_TARGET |
213 PIPE_BIND_SCANOUT |
214 PIPE_BIND_SHARED |
215 PIPE_BIND_BLENDABLE)) &&
216 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
217 retval |= usage &
218 (PIPE_BIND_RENDER_TARGET |
219 PIPE_BIND_DISPLAY_TARGET |
220 PIPE_BIND_SCANOUT |
221 PIPE_BIND_SHARED);
222 if (!util_format_is_pure_integer(format) &&
223 !util_format_is_depth_or_stencil(format))
224 retval |= usage & PIPE_BIND_BLENDABLE;
225 }
226
227 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
228 r600_is_zs_format_supported(format)) {
229 retval |= PIPE_BIND_DEPTH_STENCIL;
230 }
231
232 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
233 r600_is_vertex_format_supported(format)) {
234 retval |= PIPE_BIND_VERTEX_BUFFER;
235 }
236
237 if (usage & PIPE_BIND_TRANSFER_READ)
238 retval |= PIPE_BIND_TRANSFER_READ;
239 if (usage & PIPE_BIND_TRANSFER_WRITE)
240 retval |= PIPE_BIND_TRANSFER_WRITE;
241
242 if ((usage & PIPE_BIND_LINEAR) &&
243 !util_format_is_compressed(format) &&
244 !(usage & PIPE_BIND_DEPTH_STENCIL))
245 retval |= PIPE_BIND_LINEAR;
246
247 return retval == usage;
248 }
249
250 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
251 {
252 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
253 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
254 float offset_units = state->offset_units;
255 float offset_scale = state->offset_scale;
256
257 switch (state->zs_format) {
258 case PIPE_FORMAT_Z24X8_UNORM:
259 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
260 offset_units *= 2.0f;
261 break;
262 case PIPE_FORMAT_Z16_UNORM:
263 offset_units *= 4.0f;
264 break;
265 default:;
266 }
267
268 radeon_set_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
269 radeon_emit(cs, fui(offset_scale));
270 radeon_emit(cs, fui(offset_units));
271 radeon_emit(cs, fui(offset_scale));
272 radeon_emit(cs, fui(offset_units));
273 }
274
275 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
276 {
277 int j = state->independent_blend_enable ? i : 0;
278
279 unsigned eqRGB = state->rt[j].rgb_func;
280 unsigned srcRGB = state->rt[j].rgb_src_factor;
281 unsigned dstRGB = state->rt[j].rgb_dst_factor;
282
283 unsigned eqA = state->rt[j].alpha_func;
284 unsigned srcA = state->rt[j].alpha_src_factor;
285 unsigned dstA = state->rt[j].alpha_dst_factor;
286 uint32_t bc = 0;
287
288 if (!state->rt[j].blend_enable)
289 return 0;
290
291 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
292 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
293 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
294
295 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
296 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
297 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
298 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
299 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
300 }
301 return bc;
302 }
303
304 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
305 const struct pipe_blend_state *state,
306 int mode)
307 {
308 struct r600_context *rctx = (struct r600_context *)ctx;
309 uint32_t color_control = 0, target_mask = 0;
310 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
311
312 if (!blend) {
313 return NULL;
314 }
315
316 r600_init_command_buffer(&blend->buffer, 20);
317 r600_init_command_buffer(&blend->buffer_no_blend, 20);
318
319 /* R600 does not support per-MRT blends */
320 if (rctx->b.family > CHIP_R600)
321 color_control |= S_028808_PER_MRT_BLEND(1);
322
323 if (state->logicop_enable) {
324 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
325 } else {
326 color_control |= (0xcc << 16);
327 }
328 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
329 if (state->independent_blend_enable) {
330 for (int i = 0; i < 8; i++) {
331 if (state->rt[i].blend_enable) {
332 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
333 }
334 target_mask |= (state->rt[i].colormask << (4 * i));
335 }
336 } else {
337 for (int i = 0; i < 8; i++) {
338 if (state->rt[0].blend_enable) {
339 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
340 }
341 target_mask |= (state->rt[0].colormask << (4 * i));
342 }
343 }
344
345 if (target_mask)
346 color_control |= S_028808_SPECIAL_OP(mode);
347 else
348 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
349
350 /* only MRT0 has dual src blend */
351 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
352 blend->cb_target_mask = target_mask;
353 blend->cb_color_control = color_control;
354 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
355 blend->alpha_to_one = state->alpha_to_one;
356
357 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
358 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
359 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
360 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
361 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
362 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
363
364 /* Copy over the registers set so far into buffer_no_blend. */
365 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
366 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
367
368 /* Only add blend registers if blending is enabled. */
369 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
370 return blend;
371 }
372
373 /* The first R600 does not support per-MRT blends */
374 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
375 r600_get_blend_control(state, 0));
376
377 if (rctx->b.family > CHIP_R600) {
378 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
379 for (int i = 0; i < 8; i++) {
380 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
381 }
382 }
383 return blend;
384 }
385
386 static void *r600_create_blend_state(struct pipe_context *ctx,
387 const struct pipe_blend_state *state)
388 {
389 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
390 }
391
392 static void *r600_create_dsa_state(struct pipe_context *ctx,
393 const struct pipe_depth_stencil_alpha_state *state)
394 {
395 unsigned db_depth_control, alpha_test_control, alpha_ref;
396 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
397
398 if (!dsa) {
399 return NULL;
400 }
401
402 r600_init_command_buffer(&dsa->buffer, 3);
403
404 dsa->valuemask[0] = state->stencil[0].valuemask;
405 dsa->valuemask[1] = state->stencil[1].valuemask;
406 dsa->writemask[0] = state->stencil[0].writemask;
407 dsa->writemask[1] = state->stencil[1].writemask;
408 dsa->zwritemask = state->depth.writemask;
409
410 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
411 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
412 S_028800_ZFUNC(state->depth.func);
413
414 /* stencil */
415 if (state->stencil[0].enabled) {
416 db_depth_control |= S_028800_STENCIL_ENABLE(1);
417 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
418 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
419 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
420 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
421
422 if (state->stencil[1].enabled) {
423 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
424 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
425 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
426 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
427 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
428 }
429 }
430
431 /* alpha */
432 alpha_test_control = 0;
433 alpha_ref = 0;
434 if (state->alpha.enabled) {
435 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
436 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
437 alpha_ref = fui(state->alpha.ref_value);
438 }
439 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
440 dsa->alpha_ref = alpha_ref;
441
442 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
443 return dsa;
444 }
445
446 static void *r600_create_rs_state(struct pipe_context *ctx,
447 const struct pipe_rasterizer_state *state)
448 {
449 struct r600_context *rctx = (struct r600_context *)ctx;
450 unsigned tmp, sc_mode_cntl, spi_interp;
451 float psize_min, psize_max;
452 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
453
454 if (!rs) {
455 return NULL;
456 }
457
458 r600_init_command_buffer(&rs->buffer, 30);
459
460 rs->flatshade = state->flatshade;
461 rs->sprite_coord_enable = state->sprite_coord_enable;
462 rs->two_side = state->light_twoside;
463 rs->clip_plane_enable = state->clip_plane_enable;
464 rs->pa_sc_line_stipple = state->line_stipple_enable ?
465 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
466 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
467 rs->pa_cl_clip_cntl =
468 S_028810_PS_UCP_MODE(3) |
469 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
470 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
471 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
472 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
473 if (rctx->b.chip_class == R700) {
474 rs->pa_cl_clip_cntl |=
475 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
476 }
477 rs->multisample_enable = state->multisample;
478
479 /* offset */
480 rs->offset_units = state->offset_units;
481 rs->offset_scale = state->offset_scale * 16.0f;
482 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
483
484 if (state->point_size_per_vertex) {
485 psize_min = util_get_min_point_size(state);
486 psize_max = 8192;
487 } else {
488 /* Force the point size to be as if the vertex output was disabled. */
489 psize_min = state->point_size;
490 psize_max = state->point_size;
491 }
492
493 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
494 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
495 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
496 S_028A4C_PS_ITER_SAMPLE(state->multisample && rctx->ps_iter_samples > 1);
497 if (rctx->b.family == CHIP_RV770) {
498 /* workaround possible rendering corruption on RV770 with hyperz together with sample shading */
499 sc_mode_cntl |= S_028A4C_TILE_COVER_DISABLE(state->multisample && rctx->ps_iter_samples > 1);
500 }
501 if (rctx->b.chip_class >= R700) {
502 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
503 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
504 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
505 } else {
506 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
507 rs->scissor_enable = state->scissor;
508 }
509
510 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
511 if (state->sprite_coord_enable) {
512 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
513 S_0286D4_PNT_SPRITE_OVRD_X(2) |
514 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
515 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
516 S_0286D4_PNT_SPRITE_OVRD_W(1);
517 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
518 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
519 }
520 }
521
522 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
523 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
524 tmp = r600_pack_float_12p4(state->point_size/2);
525 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
526 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
527 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
528 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
529 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
530 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
531 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
532
533 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
534 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
535 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
536 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
537 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
538 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
539
540 rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
541 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
542 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
543 S_028814_FACE(!state->front_ccw) |
544 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
545 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
546 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
547 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
548 state->fill_back != PIPE_POLYGON_MODE_FILL) |
549 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
550 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
551 if (rctx->b.chip_class == R700) {
552 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl);
553 }
554 if (rctx->b.chip_class == R600) {
555 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC,
556 S_028350_MULTIPASS(state->rasterizer_discard));
557 }
558 return rs;
559 }
560
561 static unsigned r600_tex_filter(unsigned filter, unsigned max_aniso)
562 {
563 if (filter == PIPE_TEX_FILTER_LINEAR)
564 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_BILINEAR
565 : V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
566 else
567 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_POINT
568 : V_03C000_SQ_TEX_XY_FILTER_POINT;
569 }
570
571 static void *r600_create_sampler_state(struct pipe_context *ctx,
572 const struct pipe_sampler_state *state)
573 {
574 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
575
576 if (!ss) {
577 return NULL;
578 }
579
580 ss->seamless_cube_map = state->seamless_cube_map;
581 ss->border_color_use = sampler_state_needs_border_color(state);
582
583 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
584 ss->tex_sampler_words[0] =
585 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
586 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
587 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
588 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter, state->max_anisotropy)) |
589 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter, state->max_anisotropy)) |
590 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
591 S_03C000_MAX_ANISO_RATIO(r600_tex_aniso_filter(state->max_anisotropy)) |
592 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
593 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
594 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
595 ss->tex_sampler_words[1] =
596 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
597 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
598 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
599 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
600 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
601
602 if (ss->border_color_use) {
603 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
604 }
605 return ss;
606 }
607
608 static struct pipe_sampler_view *
609 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
610 unsigned width0, unsigned height0)
611
612 {
613 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
614 int stride = util_format_get_blocksize(view->base.format);
615 unsigned format, num_format, format_comp, endian;
616 uint64_t offset = view->base.u.buf.first_element * stride;
617 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
618
619 r600_vertex_data_type(view->base.format,
620 &format, &num_format, &format_comp,
621 &endian);
622
623 view->tex_resource = &tmp->resource;
624 view->skip_mip_address_reloc = true;
625
626 view->tex_resource_words[0] = offset;
627 view->tex_resource_words[1] = size - 1;
628 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(offset >> 32UL) |
629 S_038008_STRIDE(stride) |
630 S_038008_DATA_FORMAT(format) |
631 S_038008_NUM_FORMAT_ALL(num_format) |
632 S_038008_FORMAT_COMP_ALL(format_comp) |
633 S_038008_ENDIAN_SWAP(endian);
634 view->tex_resource_words[3] = 0;
635 /*
636 * in theory dword 4 is for number of elements, for use with resinfo,
637 * but it seems to utterly fail to work, the amd gpu shader analyser
638 * uses a const buffer to store the element sizes for buffer txq
639 */
640 view->tex_resource_words[4] = 0;
641 view->tex_resource_words[5] = 0;
642 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
643 return &view->base;
644 }
645
646 struct pipe_sampler_view *
647 r600_create_sampler_view_custom(struct pipe_context *ctx,
648 struct pipe_resource *texture,
649 const struct pipe_sampler_view *state,
650 unsigned width_first_level, unsigned height_first_level)
651 {
652 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
653 struct r600_texture *tmp = (struct r600_texture*)texture;
654 unsigned format, endian;
655 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
656 unsigned char swizzle[4], array_mode = 0;
657 unsigned width, height, depth, offset_level, last_level;
658
659 if (!view)
660 return NULL;
661
662 /* initialize base object */
663 view->base = *state;
664 view->base.texture = NULL;
665 pipe_reference(NULL, &texture->reference);
666 view->base.texture = texture;
667 view->base.reference.count = 1;
668 view->base.context = ctx;
669
670 if (texture->target == PIPE_BUFFER)
671 return texture_buffer_sampler_view(view, texture->width0, 1);
672
673 swizzle[0] = state->swizzle_r;
674 swizzle[1] = state->swizzle_g;
675 swizzle[2] = state->swizzle_b;
676 swizzle[3] = state->swizzle_a;
677
678 format = r600_translate_texformat(ctx->screen, state->format,
679 swizzle,
680 &word4, &yuv_format);
681 assert(format != ~0);
682 if (format == ~0) {
683 FREE(view);
684 return NULL;
685 }
686
687 if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) {
688 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
689 FREE(view);
690 return NULL;
691 }
692 tmp = tmp->flushed_depth_texture;
693 }
694
695 endian = r600_colorformat_endian_swap(format);
696
697 offset_level = state->u.tex.first_level;
698 last_level = state->u.tex.last_level - offset_level;
699 width = width_first_level;
700 height = height_first_level;
701 depth = u_minify(texture->depth0, offset_level);
702 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
703
704 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
705 height = 1;
706 depth = texture->array_size;
707 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
708 depth = texture->array_size;
709 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
710 depth = texture->array_size / 6;
711 switch (tmp->surface.level[offset_level].mode) {
712 case RADEON_SURF_MODE_LINEAR_ALIGNED:
713 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
714 break;
715 case RADEON_SURF_MODE_1D:
716 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
717 break;
718 case RADEON_SURF_MODE_2D:
719 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
720 break;
721 case RADEON_SURF_MODE_LINEAR:
722 default:
723 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
724 break;
725 }
726
727 if (state->format == PIPE_FORMAT_X24S8_UINT ||
728 state->format == PIPE_FORMAT_S8X24_UINT ||
729 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
730 state->format == PIPE_FORMAT_S8_UINT)
731 view->is_stencil_sampler = true;
732
733 view->tex_resource = &tmp->resource;
734 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
735 S_038000_TILE_MODE(array_mode) |
736 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
737 S_038000_PITCH((pitch / 8) - 1) |
738 S_038000_TEX_WIDTH(width - 1));
739 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
740 S_038004_TEX_DEPTH(depth - 1) |
741 S_038004_DATA_FORMAT(format));
742 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
743 if (offset_level >= tmp->surface.last_level) {
744 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
745 } else {
746 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
747 }
748 view->tex_resource_words[4] = (word4 |
749 S_038010_REQUEST_SIZE(1) |
750 S_038010_ENDIAN_SWAP(endian) |
751 S_038010_BASE_LEVEL(0));
752 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
753 S_038014_LAST_ARRAY(state->u.tex.last_layer));
754 if (texture->nr_samples > 1) {
755 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
756 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
757 } else {
758 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
759 }
760 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
761 S_038018_MAX_ANISO(4 /* max 16 samples */));
762 return &view->base;
763 }
764
765 static struct pipe_sampler_view *
766 r600_create_sampler_view(struct pipe_context *ctx,
767 struct pipe_resource *tex,
768 const struct pipe_sampler_view *state)
769 {
770 return r600_create_sampler_view_custom(ctx, tex, state,
771 u_minify(tex->width0, state->u.tex.first_level),
772 u_minify(tex->height0, state->u.tex.first_level));
773 }
774
775 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
776 {
777 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
778 struct pipe_clip_state *state = &rctx->clip_state.state;
779
780 radeon_set_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
781 radeon_emit_array(cs, (unsigned*)state, 6*4);
782 }
783
784 static void r600_set_polygon_stipple(struct pipe_context *ctx,
785 const struct pipe_poly_stipple *state)
786 {
787 }
788
789 static void r600_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
790 {
791 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
792 struct r600_scissor_state *rstate = &rctx->scissor;
793 struct pipe_scissor_state *state;
794 bool do_disable_workaround = false;
795 uint32_t dirty_mask;
796 unsigned i, offset;
797 uint32_t tl, br;
798
799 if (rctx->b.chip_class == R600 && !rctx->scissor.enable) {
800 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
801 br = S_028244_BR_X(8192) | S_028244_BR_Y(8192);
802 do_disable_workaround = true;
803 }
804
805 dirty_mask = rstate->dirty_mask;
806 while (dirty_mask != 0)
807 {
808 i = u_bit_scan(&dirty_mask);
809 offset = i * 4 * 2;
810 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + offset, 2);
811 if (!do_disable_workaround) {
812 state = &rstate->scissor[i];
813 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) |
814 S_028240_WINDOW_OFFSET_DISABLE(1);
815 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
816 }
817 radeon_emit(cs, tl);
818 radeon_emit(cs, br);
819 }
820 rstate->dirty_mask = 0;
821 rstate->atom.num_dw = 0;
822 }
823
824 static void r600_set_scissor_states(struct pipe_context *ctx,
825 unsigned start_slot,
826 unsigned num_scissors,
827 const struct pipe_scissor_state *state)
828 {
829 struct r600_context *rctx = (struct r600_context *)ctx;
830 struct r600_scissor_state *rstate = &rctx->scissor;
831 int i;
832
833 for (i = start_slot ; i < start_slot + num_scissors; i++)
834 rstate->scissor[i] = state[i - start_slot];
835 rstate->dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
836 rstate->atom.num_dw = util_bitcount(rstate->dirty_mask) * 4;
837
838 if (rctx->b.chip_class == R600 && !rstate->enable)
839 return;
840
841 r600_mark_atom_dirty(rctx, &rstate->atom);
842 }
843
844 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
845 unsigned size, unsigned alignment)
846 {
847 struct pipe_resource buffer;
848
849 memset(&buffer, 0, sizeof buffer);
850 buffer.target = PIPE_BUFFER;
851 buffer.format = PIPE_FORMAT_R8_UNORM;
852 buffer.bind = PIPE_BIND_CUSTOM;
853 buffer.usage = PIPE_USAGE_DEFAULT;
854 buffer.flags = 0;
855 buffer.width0 = size;
856 buffer.height0 = 1;
857 buffer.depth0 = 1;
858 buffer.array_size = 1;
859
860 return (struct r600_resource*)
861 r600_buffer_create(&rscreen->b.b, &buffer, alignment);
862 }
863
864 static void r600_init_color_surface(struct r600_context *rctx,
865 struct r600_surface *surf,
866 bool force_cmask_fmask)
867 {
868 struct r600_screen *rscreen = rctx->screen;
869 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
870 unsigned level = surf->base.u.tex.level;
871 unsigned pitch, slice;
872 unsigned color_info;
873 unsigned color_view;
874 unsigned format, swap, ntype, endian;
875 unsigned offset;
876 const struct util_format_description *desc;
877 int i;
878 bool blend_bypass = 0, blend_clamp = 1;
879
880 if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
881 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
882 rtex = rtex->flushed_depth_texture;
883 assert(rtex);
884 }
885
886 offset = rtex->surface.level[level].offset;
887 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
888 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
889 offset += rtex->surface.level[level].slice_size *
890 surf->base.u.tex.first_layer;
891 color_view = 0;
892 } else
893 color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
894 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
895
896 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
897 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
898 if (slice) {
899 slice = slice - 1;
900 }
901 color_info = 0;
902 switch (rtex->surface.level[level].mode) {
903 case RADEON_SURF_MODE_LINEAR_ALIGNED:
904 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
905 break;
906 case RADEON_SURF_MODE_1D:
907 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
908 break;
909 case RADEON_SURF_MODE_2D:
910 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
911 break;
912 case RADEON_SURF_MODE_LINEAR:
913 default:
914 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
915 break;
916 }
917
918 desc = util_format_description(surf->base.format);
919
920 for (i = 0; i < 4; i++) {
921 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
922 break;
923 }
924 }
925
926 ntype = V_0280A0_NUMBER_UNORM;
927 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
928 ntype = V_0280A0_NUMBER_SRGB;
929 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
930 if (desc->channel[i].normalized)
931 ntype = V_0280A0_NUMBER_SNORM;
932 else if (desc->channel[i].pure_integer)
933 ntype = V_0280A0_NUMBER_SINT;
934 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
935 if (desc->channel[i].normalized)
936 ntype = V_0280A0_NUMBER_UNORM;
937 else if (desc->channel[i].pure_integer)
938 ntype = V_0280A0_NUMBER_UINT;
939 }
940
941 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
942 assert(format != ~0);
943
944 swap = r600_translate_colorswap(surf->base.format);
945 assert(swap != ~0);
946
947 endian = r600_colorformat_endian_swap(format);
948
949 /* set blend bypass according to docs if SINT/UINT or
950 8/24 COLOR variants */
951 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
952 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
953 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
954 blend_clamp = 0;
955 blend_bypass = 1;
956 }
957
958 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
959
960 color_info |= S_0280A0_FORMAT(format) |
961 S_0280A0_COMP_SWAP(swap) |
962 S_0280A0_BLEND_BYPASS(blend_bypass) |
963 S_0280A0_BLEND_CLAMP(blend_clamp) |
964 S_0280A0_NUMBER_TYPE(ntype) |
965 S_0280A0_ENDIAN(endian);
966
967 /* EXPORT_NORM is an optimzation that can be enabled for better
968 * performance in certain cases
969 */
970 if (rctx->b.chip_class == R600) {
971 /* EXPORT_NORM can be enabled if:
972 * - 11-bit or smaller UNORM/SNORM/SRGB
973 * - BLEND_CLAMP is enabled
974 * - BLEND_FLOAT32 is disabled
975 */
976 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
977 (desc->channel[i].size < 12 &&
978 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
979 ntype != V_0280A0_NUMBER_UINT &&
980 ntype != V_0280A0_NUMBER_SINT) &&
981 G_0280A0_BLEND_CLAMP(color_info) &&
982 !G_0280A0_BLEND_FLOAT32(color_info)) {
983 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
984 surf->export_16bpc = true;
985 }
986 } else {
987 /* EXPORT_NORM can be enabled if:
988 * - 11-bit or smaller UNORM/SNORM/SRGB
989 * - 16-bit or smaller FLOAT
990 */
991 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
992 ((desc->channel[i].size < 12 &&
993 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
994 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
995 (desc->channel[i].size < 17 &&
996 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
997 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
998 surf->export_16bpc = true;
999 }
1000 }
1001
1002 /* These might not always be initialized to zero. */
1003 surf->cb_color_base = offset >> 8;
1004 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
1005 S_028060_SLICE_TILE_MAX(slice);
1006 surf->cb_color_fmask = surf->cb_color_base;
1007 surf->cb_color_cmask = surf->cb_color_base;
1008 surf->cb_color_mask = 0;
1009
1010 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1011 &rtex->resource.b.b);
1012 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1013 &rtex->resource.b.b);
1014
1015 if (rtex->cmask.size) {
1016 surf->cb_color_cmask = rtex->cmask.offset >> 8;
1017 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
1018
1019 if (rtex->fmask.size) {
1020 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1021 surf->cb_color_fmask = rtex->fmask.offset >> 8;
1022 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
1023 } else { /* cmask only */
1024 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
1025 }
1026 } else if (force_cmask_fmask) {
1027 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1028 *
1029 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1030 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1031 * because it's not an MSAA buffer.
1032 */
1033 struct r600_cmask_info cmask;
1034 struct r600_fmask_info fmask;
1035
1036 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
1037 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
1038
1039 /* CMASK. */
1040 if (!rctx->dummy_cmask ||
1041 rctx->dummy_cmask->b.b.width0 < cmask.size ||
1042 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1043 struct pipe_transfer *transfer;
1044 void *ptr;
1045
1046 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1047 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1048
1049 /* Set the contents to 0xCC. */
1050 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1051 memset(ptr, 0xCC, cmask.size);
1052 pipe_buffer_unmap(&rctx->b.b, transfer);
1053 }
1054 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1055 &rctx->dummy_cmask->b.b);
1056
1057 /* FMASK. */
1058 if (!rctx->dummy_fmask ||
1059 rctx->dummy_fmask->b.b.width0 < fmask.size ||
1060 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1061 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1062 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1063
1064 }
1065 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1066 &rctx->dummy_fmask->b.b);
1067
1068 /* Init the registers. */
1069 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1070 surf->cb_color_cmask = 0;
1071 surf->cb_color_fmask = 0;
1072 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1073 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1074 }
1075
1076 surf->cb_color_info = color_info;
1077 surf->cb_color_view = color_view;
1078 surf->color_initialized = true;
1079 }
1080
1081 static void r600_init_depth_surface(struct r600_context *rctx,
1082 struct r600_surface *surf)
1083 {
1084 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1085 unsigned level, pitch, slice, format, offset, array_mode;
1086
1087 level = surf->base.u.tex.level;
1088 offset = rtex->surface.level[level].offset;
1089 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1090 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1091 if (slice) {
1092 slice = slice - 1;
1093 }
1094 switch (rtex->surface.level[level].mode) {
1095 case RADEON_SURF_MODE_2D:
1096 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1097 break;
1098 case RADEON_SURF_MODE_1D:
1099 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1100 case RADEON_SURF_MODE_LINEAR:
1101 default:
1102 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1103 break;
1104 }
1105
1106 format = r600_translate_dbformat(surf->base.format);
1107 assert(format != ~0);
1108
1109 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1110 surf->db_depth_base = offset >> 8;
1111 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1112 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1113 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1114 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1115
1116 switch (surf->base.format) {
1117 case PIPE_FORMAT_Z24X8_UNORM:
1118 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1119 surf->pa_su_poly_offset_db_fmt_cntl =
1120 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1121 break;
1122 case PIPE_FORMAT_Z32_FLOAT:
1123 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1124 surf->pa_su_poly_offset_db_fmt_cntl =
1125 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1126 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1127 break;
1128 case PIPE_FORMAT_Z16_UNORM:
1129 surf->pa_su_poly_offset_db_fmt_cntl =
1130 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1131 break;
1132 default:;
1133 }
1134
1135 /* use htile only for first level */
1136 if (rtex->htile_buffer && !level) {
1137 surf->db_htile_data_base = 0;
1138 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1139 S_028D24_HTILE_HEIGHT(1) |
1140 S_028D24_FULL_CACHE(1);
1141 /* preload is not working properly on r6xx/r7xx */
1142 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1143 }
1144
1145 surf->depth_initialized = true;
1146 }
1147
1148 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1149 const struct pipe_framebuffer_state *state)
1150 {
1151 struct r600_context *rctx = (struct r600_context *)ctx;
1152 struct r600_surface *surf;
1153 struct r600_texture *rtex;
1154 unsigned i;
1155
1156 if (rctx->framebuffer.state.nr_cbufs) {
1157 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1158 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1159 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1160 }
1161 if (rctx->framebuffer.state.zsbuf) {
1162 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1163 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1164
1165 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1166 if (rctx->b.chip_class >= R700 && rtex->htile_buffer) {
1167 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1168 }
1169 }
1170
1171 /* Set the new state. */
1172 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1173
1174 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1175 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1176 util_format_is_pure_integer(state->cbufs[0]->format);
1177 rctx->framebuffer.compressed_cb_mask = 0;
1178 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1179 state->cbufs[0] && state->cbufs[1] &&
1180 state->cbufs[0]->texture->nr_samples > 1 &&
1181 state->cbufs[1]->texture->nr_samples <= 1;
1182 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1183
1184 /* Colorbuffers. */
1185 for (i = 0; i < state->nr_cbufs; i++) {
1186 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1187 bool force_cmask_fmask = rctx->b.chip_class == R600 &&
1188 rctx->framebuffer.is_msaa_resolve &&
1189 i == 1;
1190
1191 surf = (struct r600_surface*)state->cbufs[i];
1192 if (!surf)
1193 continue;
1194
1195 rtex = (struct r600_texture*)surf->base.texture;
1196 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1197
1198 if (!surf->color_initialized || force_cmask_fmask) {
1199 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1200 if (force_cmask_fmask) {
1201 /* re-initialize later without compression */
1202 surf->color_initialized = false;
1203 }
1204 }
1205
1206 if (!surf->export_16bpc) {
1207 rctx->framebuffer.export_16bpc = false;
1208 }
1209
1210 if (rtex->fmask.size && rtex->cmask.size) {
1211 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1212 }
1213 }
1214
1215 /* Update alpha-test state dependencies.
1216 * Alpha-test is done on the first colorbuffer only. */
1217 if (state->nr_cbufs) {
1218 bool alphatest_bypass = false;
1219
1220 surf = (struct r600_surface*)state->cbufs[0];
1221 if (surf) {
1222 alphatest_bypass = surf->alphatest_bypass;
1223 }
1224
1225 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1226 rctx->alphatest_state.bypass = alphatest_bypass;
1227 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1228 }
1229 }
1230
1231 /* ZS buffer. */
1232 if (state->zsbuf) {
1233 surf = (struct r600_surface*)state->zsbuf;
1234
1235 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1236
1237 if (!surf->depth_initialized) {
1238 r600_init_depth_surface(rctx, surf);
1239 }
1240
1241 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1242 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1243 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1244 }
1245
1246 if (rctx->db_state.rsurf != surf) {
1247 rctx->db_state.rsurf = surf;
1248 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1249 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1250 }
1251 } else if (rctx->db_state.rsurf) {
1252 rctx->db_state.rsurf = NULL;
1253 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1254 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1255 }
1256
1257 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1258 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1259 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1260 }
1261
1262 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1263 rctx->alphatest_state.bypass = false;
1264 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1265 }
1266
1267 /* Calculate the CS size. */
1268 rctx->framebuffer.atom.num_dw =
1269 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1270
1271 if (rctx->framebuffer.state.nr_cbufs) {
1272 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
1273 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
1274 }
1275 if (rctx->framebuffer.state.zsbuf) {
1276 rctx->framebuffer.atom.num_dw += 16;
1277 } else if (rctx->screen->b.info.drm_minor >= 18) {
1278 rctx->framebuffer.atom.num_dw += 3;
1279 }
1280 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1281 rctx->framebuffer.atom.num_dw += 2;
1282 }
1283
1284 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1285
1286 r600_set_sample_locations_constant_buffer(rctx);
1287 }
1288
1289 static uint32_t sample_locs_2x[] = {
1290 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1291 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1292 };
1293 static unsigned max_dist_2x = 4;
1294
1295 static uint32_t sample_locs_4x[] = {
1296 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1297 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1298 };
1299 static unsigned max_dist_4x = 6;
1300 static uint32_t sample_locs_8x[] = {
1301 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1302 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1303 };
1304 static unsigned max_dist_8x = 7;
1305
1306 static void r600_get_sample_position(struct pipe_context *ctx,
1307 unsigned sample_count,
1308 unsigned sample_index,
1309 float *out_value)
1310 {
1311 int offset, index;
1312 struct {
1313 int idx:4;
1314 } val;
1315 switch (sample_count) {
1316 case 1:
1317 default:
1318 out_value[0] = out_value[1] = 0.5;
1319 break;
1320 case 2:
1321 offset = 4 * (sample_index * 2);
1322 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1323 out_value[0] = (float)(val.idx + 8) / 16.0f;
1324 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1325 out_value[1] = (float)(val.idx + 8) / 16.0f;
1326 break;
1327 case 4:
1328 offset = 4 * (sample_index * 2);
1329 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1330 out_value[0] = (float)(val.idx + 8) / 16.0f;
1331 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1332 out_value[1] = (float)(val.idx + 8) / 16.0f;
1333 break;
1334 case 8:
1335 offset = 4 * (sample_index % 4 * 2);
1336 index = (sample_index / 4);
1337 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1338 out_value[0] = (float)(val.idx + 8) / 16.0f;
1339 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1340 out_value[1] = (float)(val.idx + 8) / 16.0f;
1341 break;
1342 }
1343 }
1344
1345 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1346 {
1347 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1348 unsigned max_dist = 0;
1349
1350 if (rctx->b.family == CHIP_R600) {
1351 switch (nr_samples) {
1352 default:
1353 nr_samples = 0;
1354 break;
1355 case 2:
1356 radeon_set_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1357 max_dist = max_dist_2x;
1358 break;
1359 case 4:
1360 radeon_set_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1361 max_dist = max_dist_4x;
1362 break;
1363 case 8:
1364 radeon_set_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1365 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1366 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1367 max_dist = max_dist_8x;
1368 break;
1369 }
1370 } else {
1371 switch (nr_samples) {
1372 default:
1373 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1374 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1375 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1376 nr_samples = 0;
1377 break;
1378 case 2:
1379 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1380 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1381 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1382 max_dist = max_dist_2x;
1383 break;
1384 case 4:
1385 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1386 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1387 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1388 max_dist = max_dist_4x;
1389 break;
1390 case 8:
1391 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1392 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1393 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1394 max_dist = max_dist_8x;
1395 break;
1396 }
1397 }
1398
1399 if (nr_samples > 1) {
1400 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1401 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1402 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1403 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1404 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1405 } else {
1406 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1407 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1408 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1409 }
1410 }
1411
1412 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1413 {
1414 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1415 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1416 unsigned nr_cbufs = state->nr_cbufs;
1417 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1418 unsigned i, sbu = 0;
1419
1420 /* Colorbuffers. */
1421 radeon_set_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1422 for (i = 0; i < nr_cbufs; i++) {
1423 radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0);
1424 }
1425 /* set CB_COLOR1_INFO for possible dual-src blending */
1426 if (i == 1 && cb[0]) {
1427 radeon_emit(cs, cb[0]->cb_color_info);
1428 i++;
1429 }
1430 for (; i < 8; i++) {
1431 radeon_emit(cs, 0);
1432 }
1433
1434 if (nr_cbufs) {
1435 for (i = 0; i < nr_cbufs; i++) {
1436 unsigned reloc;
1437
1438 if (!cb[i])
1439 continue;
1440
1441 /* COLOR_BASE */
1442 radeon_set_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1443
1444 reloc = radeon_add_to_buffer_list(&rctx->b,
1445 &rctx->b.gfx,
1446 (struct r600_resource*)cb[i]->base.texture,
1447 RADEON_USAGE_READWRITE,
1448 cb[i]->base.texture->nr_samples > 1 ?
1449 RADEON_PRIO_COLOR_BUFFER_MSAA :
1450 RADEON_PRIO_COLOR_BUFFER);
1451 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1452 radeon_emit(cs, reloc);
1453
1454 /* FMASK */
1455 radeon_set_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1456
1457 reloc = radeon_add_to_buffer_list(&rctx->b,
1458 &rctx->b.gfx,
1459 cb[i]->cb_buffer_fmask,
1460 RADEON_USAGE_READWRITE,
1461 cb[i]->base.texture->nr_samples > 1 ?
1462 RADEON_PRIO_COLOR_BUFFER_MSAA :
1463 RADEON_PRIO_COLOR_BUFFER);
1464 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1465 radeon_emit(cs, reloc);
1466
1467 /* CMASK */
1468 radeon_set_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1469
1470 reloc = radeon_add_to_buffer_list(&rctx->b,
1471 &rctx->b.gfx,
1472 cb[i]->cb_buffer_cmask,
1473 RADEON_USAGE_READWRITE,
1474 cb[i]->base.texture->nr_samples > 1 ?
1475 RADEON_PRIO_COLOR_BUFFER_MSAA :
1476 RADEON_PRIO_COLOR_BUFFER);
1477 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1478 radeon_emit(cs, reloc);
1479 }
1480
1481 radeon_set_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1482 for (i = 0; i < nr_cbufs; i++) {
1483 radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0);
1484 }
1485
1486 radeon_set_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1487 for (i = 0; i < nr_cbufs; i++) {
1488 radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0);
1489 }
1490
1491 radeon_set_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1492 for (i = 0; i < nr_cbufs; i++) {
1493 radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0);
1494 }
1495
1496 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1497 }
1498
1499 /* SURFACE_BASE_UPDATE */
1500 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1501 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1502 radeon_emit(cs, sbu);
1503 sbu = 0;
1504 }
1505
1506 /* Zbuffer. */
1507 if (state->zsbuf) {
1508 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1509 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1510 &rctx->b.gfx,
1511 (struct r600_resource*)state->zsbuf->texture,
1512 RADEON_USAGE_READWRITE,
1513 surf->base.texture->nr_samples > 1 ?
1514 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1515 RADEON_PRIO_DEPTH_BUFFER);
1516
1517 radeon_set_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1518 surf->pa_su_poly_offset_db_fmt_cntl);
1519
1520 radeon_set_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1521 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1522 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1523 radeon_set_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1524 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1525 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1526
1527 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1528 radeon_emit(cs, reloc);
1529
1530 radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1531
1532 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1533 } else if (rctx->screen->b.info.drm_minor >= 18) {
1534 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1535 * Older kernels are out of luck. */
1536 radeon_set_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1537 }
1538
1539 /* SURFACE_BASE_UPDATE */
1540 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1541 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1542 radeon_emit(cs, sbu);
1543 sbu = 0;
1544 }
1545
1546 /* Framebuffer dimensions. */
1547 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1548 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1549 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1550 radeon_emit(cs, S_028244_BR_X(state->width) |
1551 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1552
1553 if (rctx->framebuffer.is_msaa_resolve) {
1554 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1555 } else {
1556 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1557 * will assure that the alpha-test will work even if there is
1558 * no colorbuffer bound. */
1559 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1560 (1ull << MAX2(nr_cbufs, 1)) - 1);
1561 }
1562
1563 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1564 }
1565
1566 static void r600_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1567 {
1568 struct r600_context *rctx = (struct r600_context *)ctx;
1569
1570 if (rctx->ps_iter_samples == min_samples)
1571 return;
1572
1573 rctx->ps_iter_samples = min_samples;
1574 if (rctx->framebuffer.nr_samples > 1) {
1575 r600_mark_atom_dirty(rctx, &rctx->rasterizer_state.atom);
1576 if (rctx->b.chip_class == R600)
1577 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1578 }
1579 }
1580
1581 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1582 {
1583 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1584 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1585
1586 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1587 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1588 if (rctx->b.chip_class == R600) {
1589 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1590 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1591 } else {
1592 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1593 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1594 }
1595 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1596 } else {
1597 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1598 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1599 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1600
1601 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1602 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1603 /* Always enable the first color output to make sure alpha-test works even without one. */
1604 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1605 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1606 a->cb_color_control |
1607 S_028808_MULTIWRITE_ENABLE(multiwrite));
1608 }
1609 }
1610
1611 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1612 {
1613 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1614 struct r600_db_state *a = (struct r600_db_state*)atom;
1615
1616 if (a->rsurf && a->rsurf->db_htile_surface) {
1617 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1618 unsigned reloc_idx;
1619
1620 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1621 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1622 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1623 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
1624 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1625 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1626 cs->buf[cs->cdw++] = reloc_idx;
1627 } else {
1628 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1629 }
1630 }
1631
1632 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1633 {
1634 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1635 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1636 unsigned db_render_control = 0;
1637 unsigned db_render_override =
1638 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1639 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1640
1641 if (rctx->b.chip_class >= R700) {
1642 switch (a->ps_conservative_z) {
1643 default: /* fall through */
1644 case TGSI_FS_DEPTH_LAYOUT_ANY:
1645 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_ANY_Z);
1646 break;
1647 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1648 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_GREATER_THAN_Z);
1649 break;
1650 case TGSI_FS_DEPTH_LAYOUT_LESS:
1651 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_LESS_THAN_Z);
1652 break;
1653 }
1654 }
1655
1656 if (rctx->b.num_occlusion_queries > 0 &&
1657 !a->occlusion_queries_disabled) {
1658 if (rctx->b.chip_class >= R700) {
1659 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1660 }
1661 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1662 } else {
1663 db_render_control |= S_028D0C_ZPASS_INCREMENT_DISABLE(1);
1664 }
1665
1666 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
1667 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1668 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1669 /* This is to fix a lockup when hyperz and alpha test are enabled at
1670 * the same time somehow GPU get confuse on which order to pick for
1671 * z test
1672 */
1673 if (rctx->alphatest_state.sx_alpha_test_control) {
1674 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
1675 }
1676 } else {
1677 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1678 }
1679 if (rctx->b.chip_class == R600 && rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) {
1680 /* sample shading and hyperz causes lockups on R6xx chips */
1681 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1682 }
1683 if (a->flush_depthstencil_through_cb) {
1684 assert(a->copy_depth || a->copy_stencil);
1685
1686 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1687 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1688 S_028D0C_COPY_CENTROID(1) |
1689 S_028D0C_COPY_SAMPLE(a->copy_sample);
1690
1691 if (rctx->b.chip_class == R600)
1692 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1693
1694 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
1695 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
1696 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1697 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1698 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1699 S_028D0C_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1700 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1701 }
1702 if (a->htile_clear) {
1703 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1704 }
1705
1706 /* RV770 workaround for a hang with 8x MSAA. */
1707 if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) {
1708 db_render_override |= S_028D10_MAX_TILES_IN_DTT(6);
1709 }
1710
1711 radeon_set_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1712 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1713 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1714 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1715 }
1716
1717 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1718 {
1719 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1720 struct r600_config_state *a = (struct r600_config_state*)atom;
1721
1722 radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1723 radeon_set_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
1724 }
1725
1726 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1727 {
1728 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1729 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1730
1731 while (dirty_mask) {
1732 struct pipe_vertex_buffer *vb;
1733 struct r600_resource *rbuffer;
1734 unsigned offset;
1735 unsigned buffer_index = u_bit_scan(&dirty_mask);
1736
1737 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1738 rbuffer = (struct r600_resource*)vb->buffer;
1739 assert(rbuffer);
1740
1741 offset = vb->buffer_offset;
1742
1743 /* fetch resources start at index 320 (OFFSET_FS) */
1744 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1745 radeon_emit(cs, (R600_FETCH_CONSTANTS_OFFSET_FS + buffer_index) * 7);
1746 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1747 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1748 radeon_emit(cs, /* RESOURCEi_WORD2 */
1749 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1750 S_038008_STRIDE(vb->stride));
1751 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1752 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1753 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1754 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1755
1756 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1757 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1758 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1759 }
1760 }
1761
1762 static void r600_emit_constant_buffers(struct r600_context *rctx,
1763 struct r600_constbuf_state *state,
1764 unsigned buffer_id_base,
1765 unsigned reg_alu_constbuf_size,
1766 unsigned reg_alu_const_cache)
1767 {
1768 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1769 uint32_t dirty_mask = state->dirty_mask;
1770
1771 while (dirty_mask) {
1772 struct pipe_constant_buffer *cb;
1773 struct r600_resource *rbuffer;
1774 unsigned offset;
1775 unsigned buffer_index = ffs(dirty_mask) - 1;
1776 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1777 cb = &state->cb[buffer_index];
1778 rbuffer = (struct r600_resource*)cb->buffer;
1779 assert(rbuffer);
1780
1781 offset = cb->buffer_offset;
1782
1783 if (!gs_ring_buffer) {
1784 radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1785 DIV_ROUND_UP(cb->buffer_size, 256));
1786 radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1787 }
1788
1789 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1790 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1791 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1792
1793 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1794 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
1795 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1796 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1797 radeon_emit(cs, /* RESOURCEi_WORD2 */
1798 S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1799 S_038008_STRIDE(gs_ring_buffer ? 4 : 16));
1800 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1801 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1802 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1803 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1804
1805 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1806 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1807 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1808
1809 dirty_mask &= ~(1 << buffer_index);
1810 }
1811 state->dirty_mask = 0;
1812 }
1813
1814 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1815 {
1816 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1817 R600_FETCH_CONSTANTS_OFFSET_VS,
1818 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1819 R_028980_ALU_CONST_CACHE_VS_0);
1820 }
1821
1822 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1823 {
1824 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1825 R600_FETCH_CONSTANTS_OFFSET_GS,
1826 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1827 R_0289C0_ALU_CONST_CACHE_GS_0);
1828 }
1829
1830 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1831 {
1832 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1833 R600_FETCH_CONSTANTS_OFFSET_PS,
1834 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1835 R_028940_ALU_CONST_CACHE_PS_0);
1836 }
1837
1838 static void r600_emit_sampler_views(struct r600_context *rctx,
1839 struct r600_samplerview_state *state,
1840 unsigned resource_id_base)
1841 {
1842 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1843 uint32_t dirty_mask = state->dirty_mask;
1844
1845 while (dirty_mask) {
1846 struct r600_pipe_sampler_view *rview;
1847 unsigned resource_index = u_bit_scan(&dirty_mask);
1848 unsigned reloc;
1849
1850 rview = state->views[resource_index];
1851 assert(rview);
1852
1853 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1854 radeon_emit(cs, (resource_id_base + resource_index) * 7);
1855 radeon_emit_array(cs, rview->tex_resource_words, 7);
1856
1857 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
1858 RADEON_USAGE_READ,
1859 r600_get_sampler_view_priority(rview->tex_resource));
1860 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1861 radeon_emit(cs, reloc);
1862 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1863 radeon_emit(cs, reloc);
1864 }
1865 state->dirty_mask = 0;
1866 }
1867
1868
1869 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1870 {
1871 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, R600_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS);
1872 }
1873
1874 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1875 {
1876 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, R600_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS);
1877 }
1878
1879 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1880 {
1881 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS);
1882 }
1883
1884 static void r600_emit_sampler_states(struct r600_context *rctx,
1885 struct r600_textures_info *texinfo,
1886 unsigned resource_id_base,
1887 unsigned border_color_reg)
1888 {
1889 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1890 uint32_t dirty_mask = texinfo->states.dirty_mask;
1891
1892 while (dirty_mask) {
1893 struct r600_pipe_sampler_state *rstate;
1894 struct r600_pipe_sampler_view *rview;
1895 unsigned i = u_bit_scan(&dirty_mask);
1896
1897 rstate = texinfo->states.states[i];
1898 assert(rstate);
1899 rview = texinfo->views.views[i];
1900
1901 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1902 * filtering between layers.
1903 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1904 */
1905 if (rview) {
1906 enum pipe_texture_target target = rview->base.texture->target;
1907 if (target == PIPE_TEXTURE_1D_ARRAY ||
1908 target == PIPE_TEXTURE_2D_ARRAY) {
1909 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1910 texinfo->is_array_sampler[i] = true;
1911 } else {
1912 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1913 texinfo->is_array_sampler[i] = false;
1914 }
1915 }
1916
1917 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1918 radeon_emit(cs, (resource_id_base + i) * 3);
1919 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
1920
1921 if (rstate->border_color_use) {
1922 unsigned offset;
1923
1924 offset = border_color_reg;
1925 offset += i * 16;
1926 radeon_set_config_reg_seq(cs, offset, 4);
1927 radeon_emit_array(cs, rstate->border_color.ui, 4);
1928 }
1929 }
1930 texinfo->states.dirty_mask = 0;
1931 }
1932
1933 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1934 {
1935 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1936 }
1937
1938 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1939 {
1940 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1941 }
1942
1943 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1944 {
1945 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1946 }
1947
1948 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1949 {
1950 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1951 unsigned tmp;
1952
1953 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1954 S_009508_SYNC_GRADIENT(1) |
1955 S_009508_SYNC_WALKER(1) |
1956 S_009508_SYNC_ALIGNER(1);
1957 if (!rctx->seamless_cube_map.enabled) {
1958 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1959 }
1960 radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1961 }
1962
1963 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1964 {
1965 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1966 uint8_t mask = s->sample_mask;
1967
1968 radeon_set_context_reg(rctx->b.gfx.cs, R_028C48_PA_SC_AA_MASK,
1969 mask | (mask << 8) | (mask << 16) | (mask << 24));
1970 }
1971
1972 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
1973 {
1974 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1975 struct r600_cso_state *state = (struct r600_cso_state*)a;
1976 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
1977
1978 radeon_set_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
1979 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1980 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
1981 RADEON_USAGE_READ,
1982 RADEON_PRIO_INTERNAL_SHADER));
1983 }
1984
1985 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
1986 {
1987 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1988 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
1989
1990 uint32_t v2 = 0, primid = 0;
1991
1992 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
1993 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1994 primid = 1;
1995 }
1996
1997 if (state->geom_enable) {
1998 uint32_t cut_val;
1999
2000 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2001 cut_val = V_028A40_GS_CUT_128;
2002 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2003 cut_val = V_028A40_GS_CUT_256;
2004 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2005 cut_val = V_028A40_GS_CUT_512;
2006 else
2007 cut_val = V_028A40_GS_CUT_1024;
2008
2009 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2010 S_028A40_CUT_MODE(cut_val);
2011
2012 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2013 primid = 1;
2014 }
2015
2016 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2017 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2018 }
2019
2020 static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2021 {
2022 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2023 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2024 struct r600_resource *rbuffer;
2025
2026 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2027 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2028 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2029
2030 if (state->enable) {
2031 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2032 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
2033 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2034 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2035 RADEON_USAGE_READWRITE,
2036 RADEON_PRIO_RINGS_STREAMOUT));
2037 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2038 state->esgs_ring.buffer_size >> 8);
2039
2040 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2041 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
2042 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2043 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2044 RADEON_USAGE_READWRITE,
2045 RADEON_PRIO_RINGS_STREAMOUT));
2046 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2047 state->gsvs_ring.buffer_size >> 8);
2048 } else {
2049 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2050 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2051 }
2052
2053 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2054 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2055 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2056 }
2057
2058 /* Adjust GPR allocation on R6xx/R7xx */
2059 bool r600_adjust_gprs(struct r600_context *rctx)
2060 {
2061 unsigned num_gprs[R600_NUM_HW_STAGES];
2062 unsigned new_gprs[R600_NUM_HW_STAGES];
2063 unsigned cur_gprs[R600_NUM_HW_STAGES];
2064 unsigned def_gprs[R600_NUM_HW_STAGES];
2065 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
2066 unsigned max_gprs;
2067 unsigned tmp, tmp2;
2068 unsigned i;
2069 bool need_recalc = false, use_default = true;
2070
2071 /* hardware will reserve twice num_clause_temp_gprs */
2072 max_gprs = def_num_clause_temp_gprs * 2;
2073 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2074 def_gprs[i] = rctx->default_gprs[i];
2075 max_gprs += def_gprs[i];
2076 }
2077
2078 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2079 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2080 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2081 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2082
2083 num_gprs[R600_HW_STAGE_PS] = rctx->ps_shader->current->shader.bc.ngpr;
2084 if (rctx->gs_shader) {
2085 num_gprs[R600_HW_STAGE_ES] = rctx->vs_shader->current->shader.bc.ngpr;
2086 num_gprs[R600_HW_STAGE_GS] = rctx->gs_shader->current->shader.bc.ngpr;
2087 num_gprs[R600_HW_STAGE_VS] = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
2088 } else {
2089 num_gprs[R600_HW_STAGE_ES] = 0;
2090 num_gprs[R600_HW_STAGE_GS] = 0;
2091 num_gprs[R600_HW_STAGE_VS] = rctx->vs_shader->current->shader.bc.ngpr;
2092 }
2093
2094 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2095 new_gprs[i] = num_gprs[i];
2096 if (new_gprs[i] > cur_gprs[i])
2097 need_recalc = true;
2098 if (new_gprs[i] > def_gprs[i])
2099 use_default = false;
2100 }
2101
2102 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2103 if (!need_recalc)
2104 return true;
2105
2106 /* try to use switch back to default */
2107 if (!use_default) {
2108 /* always privilege vs stage so that at worst we have the
2109 * pixel stage producing wrong output (not the vertex
2110 * stage) */
2111 new_gprs[R600_HW_STAGE_PS] = max_gprs - def_num_clause_temp_gprs * 2;
2112 for (i = R600_HW_STAGE_VS; i < R600_NUM_HW_STAGES; i++)
2113 new_gprs[R600_HW_STAGE_PS] -= new_gprs[i];
2114 } else {
2115 for (i = 0; i < R600_NUM_HW_STAGES; i++)
2116 new_gprs[i] = def_gprs[i];
2117 }
2118
2119 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2120 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2121 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2122 * it will lockup. So in this case just discard the draw command
2123 * and don't change the current gprs repartitions.
2124 */
2125 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2126 if (num_gprs[i] > new_gprs[i]) {
2127 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2128 "for a combined maximum of %d\n",
2129 num_gprs[R600_HW_STAGE_PS], num_gprs[R600_HW_STAGE_VS], num_gprs[R600_HW_STAGE_ES], num_gprs[R600_HW_STAGE_GS], max_gprs);
2130 return false;
2131 }
2132 }
2133
2134 /* in some case we endup recomputing the current value */
2135 tmp = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
2136 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
2137 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2138
2139 tmp2 = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
2140 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
2141 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2142 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2143 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2;
2144 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
2145 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2146 }
2147 return true;
2148 }
2149
2150 void r600_init_atom_start_cs(struct r600_context *rctx)
2151 {
2152 int ps_prio;
2153 int vs_prio;
2154 int gs_prio;
2155 int es_prio;
2156 int num_ps_gprs;
2157 int num_vs_gprs;
2158 int num_gs_gprs;
2159 int num_es_gprs;
2160 int num_temp_gprs;
2161 int num_ps_threads;
2162 int num_vs_threads;
2163 int num_gs_threads;
2164 int num_es_threads;
2165 int num_ps_stack_entries;
2166 int num_vs_stack_entries;
2167 int num_gs_stack_entries;
2168 int num_es_stack_entries;
2169 enum radeon_family family;
2170 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2171 uint32_t tmp, i;
2172
2173 r600_init_command_buffer(cb, 256);
2174
2175 /* R6xx requires this packet at the start of each command buffer */
2176 if (rctx->b.chip_class == R600) {
2177 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2178 r600_store_value(cb, 0);
2179 }
2180 /* All asics require this one */
2181 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2182 r600_store_value(cb, 0x80000000);
2183 r600_store_value(cb, 0x80000000);
2184
2185 /* We're setting config registers here. */
2186 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2187 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2188
2189 /* This enables pipeline stat & streamout queries.
2190 * They are only disabled by blits.
2191 */
2192 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2193 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2194
2195 family = rctx->b.family;
2196 ps_prio = 0;
2197 vs_prio = 1;
2198 gs_prio = 2;
2199 es_prio = 3;
2200 switch (family) {
2201 case CHIP_R600:
2202 num_ps_gprs = 192;
2203 num_vs_gprs = 56;
2204 num_temp_gprs = 4;
2205 num_gs_gprs = 0;
2206 num_es_gprs = 0;
2207 num_ps_threads = 136;
2208 num_vs_threads = 48;
2209 num_gs_threads = 4;
2210 num_es_threads = 4;
2211 num_ps_stack_entries = 128;
2212 num_vs_stack_entries = 128;
2213 num_gs_stack_entries = 0;
2214 num_es_stack_entries = 0;
2215 break;
2216 case CHIP_RV630:
2217 case CHIP_RV635:
2218 num_ps_gprs = 84;
2219 num_vs_gprs = 36;
2220 num_temp_gprs = 4;
2221 num_gs_gprs = 0;
2222 num_es_gprs = 0;
2223 num_ps_threads = 144;
2224 num_vs_threads = 40;
2225 num_gs_threads = 4;
2226 num_es_threads = 4;
2227 num_ps_stack_entries = 40;
2228 num_vs_stack_entries = 40;
2229 num_gs_stack_entries = 32;
2230 num_es_stack_entries = 16;
2231 break;
2232 case CHIP_RV610:
2233 case CHIP_RV620:
2234 case CHIP_RS780:
2235 case CHIP_RS880:
2236 default:
2237 num_ps_gprs = 84;
2238 num_vs_gprs = 36;
2239 num_temp_gprs = 4;
2240 num_gs_gprs = 0;
2241 num_es_gprs = 0;
2242 /* use limits 40 VS and at least 16 ES/GS */
2243 num_ps_threads = 120;
2244 num_vs_threads = 40;
2245 num_gs_threads = 16;
2246 num_es_threads = 16;
2247 num_ps_stack_entries = 40;
2248 num_vs_stack_entries = 40;
2249 num_gs_stack_entries = 32;
2250 num_es_stack_entries = 16;
2251 break;
2252 case CHIP_RV670:
2253 num_ps_gprs = 144;
2254 num_vs_gprs = 40;
2255 num_temp_gprs = 4;
2256 num_gs_gprs = 0;
2257 num_es_gprs = 0;
2258 num_ps_threads = 136;
2259 num_vs_threads = 48;
2260 num_gs_threads = 4;
2261 num_es_threads = 4;
2262 num_ps_stack_entries = 40;
2263 num_vs_stack_entries = 40;
2264 num_gs_stack_entries = 32;
2265 num_es_stack_entries = 16;
2266 break;
2267 case CHIP_RV770:
2268 num_ps_gprs = 130;
2269 num_vs_gprs = 56;
2270 num_temp_gprs = 4;
2271 num_gs_gprs = 31;
2272 num_es_gprs = 31;
2273 num_ps_threads = 180;
2274 num_vs_threads = 60;
2275 num_gs_threads = 4;
2276 num_es_threads = 4;
2277 num_ps_stack_entries = 128;
2278 num_vs_stack_entries = 128;
2279 num_gs_stack_entries = 128;
2280 num_es_stack_entries = 128;
2281 break;
2282 case CHIP_RV730:
2283 case CHIP_RV740:
2284 num_ps_gprs = 84;
2285 num_vs_gprs = 36;
2286 num_temp_gprs = 4;
2287 num_gs_gprs = 0;
2288 num_es_gprs = 0;
2289 num_ps_threads = 180;
2290 num_vs_threads = 60;
2291 num_gs_threads = 4;
2292 num_es_threads = 4;
2293 num_ps_stack_entries = 128;
2294 num_vs_stack_entries = 128;
2295 num_gs_stack_entries = 0;
2296 num_es_stack_entries = 0;
2297 break;
2298 case CHIP_RV710:
2299 num_ps_gprs = 192;
2300 num_vs_gprs = 56;
2301 num_temp_gprs = 4;
2302 num_gs_gprs = 0;
2303 num_es_gprs = 0;
2304 num_ps_threads = 136;
2305 num_vs_threads = 48;
2306 num_gs_threads = 4;
2307 num_es_threads = 4;
2308 num_ps_stack_entries = 128;
2309 num_vs_stack_entries = 128;
2310 num_gs_stack_entries = 0;
2311 num_es_stack_entries = 0;
2312 break;
2313 }
2314
2315 rctx->default_gprs[R600_HW_STAGE_PS] = num_ps_gprs;
2316 rctx->default_gprs[R600_HW_STAGE_VS] = num_vs_gprs;
2317 rctx->default_gprs[R600_HW_STAGE_GS] = 0;
2318 rctx->default_gprs[R600_HW_STAGE_ES] = 0;
2319
2320 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2321
2322 /* SQ_CONFIG */
2323 tmp = 0;
2324 switch (family) {
2325 case CHIP_RV610:
2326 case CHIP_RV620:
2327 case CHIP_RS780:
2328 case CHIP_RS880:
2329 case CHIP_RV710:
2330 break;
2331 default:
2332 tmp |= S_008C00_VC_ENABLE(1);
2333 break;
2334 }
2335 tmp |= S_008C00_DX9_CONSTS(0);
2336 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2337 tmp |= S_008C00_PS_PRIO(ps_prio);
2338 tmp |= S_008C00_VS_PRIO(vs_prio);
2339 tmp |= S_008C00_GS_PRIO(gs_prio);
2340 tmp |= S_008C00_ES_PRIO(es_prio);
2341 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2342
2343 /* SQ_GPR_RESOURCE_MGMT_2 */
2344 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2345 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2346 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2347 r600_store_value(cb, tmp);
2348
2349 /* SQ_THREAD_RESOURCE_MGMT */
2350 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2351 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2352 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2353 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2354 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2355
2356 /* SQ_STACK_RESOURCE_MGMT_1 */
2357 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2358 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2359 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2360
2361 /* SQ_STACK_RESOURCE_MGMT_2 */
2362 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2363 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2364 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2365
2366 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2367
2368 if (rctx->b.chip_class >= R700) {
2369 r600_store_context_reg(cb, R_028A50_VGT_ENHANCE, 4);
2370 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2371 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2372 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2373 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2374 } else {
2375 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2376 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2377 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2378 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2379 }
2380 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2381 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2382 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2383 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2384 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2385 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2386 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2387 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2388 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2389 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2390
2391 /* to avoid GPU doing any preloading of constant from random address */
2392 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2393 for (i = 0; i < 16; i++)
2394 r600_store_value(cb, 0);
2395
2396 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2397 for (i = 0; i < 16; i++)
2398 r600_store_value(cb, 0);
2399
2400 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2401 for (i = 0; i < 16; i++)
2402 r600_store_value(cb, 0);
2403
2404 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2405 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2406 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2407 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2408 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2409 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2410 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2411 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2412 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2413 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2414 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2415 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2416 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2417 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2418
2419 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2420 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2421 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2422
2423 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2424 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2425 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2426
2427 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2428
2429 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2430
2431 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2432
2433 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2434 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2435 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2436 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2437
2438 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2439 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2440 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2441 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2442
2443 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2444 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2445
2446 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2447 r600_store_value(cb, fui(1.0)); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2448 r600_store_value(cb, fui(1.0)); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2449 r600_store_value(cb, fui(1.0)); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2450 r600_store_value(cb, fui(1.0)); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2451
2452 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2453 for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2454 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2455 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2456 }
2457
2458 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2459 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2460
2461 if (rctx->b.chip_class >= R700) {
2462 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2463 }
2464
2465 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2466 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2467 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2468 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2469 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2470
2471 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2472 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2473 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2474
2475 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2476 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2477 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2478
2479 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5);
2480 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2481 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2482 r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2483 r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2484 r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2485
2486 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2487
2488 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2489 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2490 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2491
2492 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2493
2494 if (rctx->b.chip_class == R700)
2495 r600_store_context_reg(cb, R_028350_SX_MISC, 0);
2496 if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
2497 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2498
2499 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2500 if (rctx->screen->b.has_streamout) {
2501 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2502 }
2503
2504 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2505 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2506 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF);
2507 }
2508
2509 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2510 {
2511 struct r600_context *rctx = (struct r600_context *)ctx;
2512 struct r600_command_buffer *cb = &shader->command_buffer;
2513 struct r600_shader *rshader = &shader->shader;
2514 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2515 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2516 unsigned tmp, sid, ufi = 0;
2517 int need_linear = 0;
2518 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2519 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2520
2521 if (!cb->buf) {
2522 r600_init_command_buffer(cb, 64);
2523 } else {
2524 cb->num_dw = 0;
2525 }
2526
2527 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2528 for (i = 0; i < rshader->ninput; i++) {
2529 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2530 pos_index = i;
2531 if (rshader->input[i].name == TGSI_SEMANTIC_FACE && face_index == -1)
2532 face_index = i;
2533 if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID)
2534 fixed_pt_position_index = i;
2535
2536 sid = rshader->input[i].spi_sid;
2537
2538 tmp = S_028644_SEMANTIC(sid);
2539
2540 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2541 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2542 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2543 rctx->rasterizer && rctx->rasterizer->flatshade))
2544 tmp |= S_028644_FLAT_SHADE(1);
2545
2546 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2547 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2548 tmp |= S_028644_PT_SPRITE_TEX(1);
2549 }
2550
2551 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID)
2552 tmp |= S_028644_SEL_CENTROID(1);
2553
2554 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE)
2555 tmp |= S_028644_SEL_SAMPLE(1);
2556
2557 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2558 need_linear = 1;
2559 tmp |= S_028644_SEL_LINEAR(1);
2560 }
2561
2562 r600_store_value(cb, tmp);
2563 }
2564
2565 db_shader_control = 0;
2566 for (i = 0; i < rshader->noutput; i++) {
2567 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2568 z_export = 1;
2569 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2570 stencil_export = 1;
2571 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
2572 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
2573 mask_export = 1;
2574 }
2575 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2576 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2577 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
2578 if (rshader->uses_kill)
2579 db_shader_control |= S_02880C_KILL_ENABLE(1);
2580
2581 exports_ps = 0;
2582 for (i = 0; i < rshader->noutput; i++) {
2583 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2584 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
2585 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2586 exports_ps |= 1;
2587 }
2588 }
2589 num_cout = rshader->nr_ps_color_exports;
2590 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2591 if (!exports_ps) {
2592 /* always at least export 1 component per pixel */
2593 exports_ps = 2;
2594 }
2595
2596 shader->nr_ps_color_outputs = num_cout;
2597
2598 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2599 S_0286CC_PERSP_GRADIENT_ENA(1)|
2600 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2601 spi_input_z = 0;
2602 if (pos_index != -1) {
2603 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2604 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
2605 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2606 S_0286CC_BARYC_SAMPLE_CNTL(1)) |
2607 S_0286CC_POSITION_SAMPLE(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE);
2608 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2609 }
2610
2611 spi_ps_in_control_1 = 0;
2612 if (face_index != -1) {
2613 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2614 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2615 }
2616 if (fixed_pt_position_index != -1) {
2617 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
2618 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
2619 }
2620
2621 /* HW bug in original R600 */
2622 if (rctx->b.family == CHIP_R600)
2623 ufi = 1;
2624
2625 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2626 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2627 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2628
2629 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2630
2631 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2632 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2633 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2634 S_028850_STACK_SIZE(rshader->bc.nstack) |
2635 S_028850_UNCACHED_FIRST_INST(ufi));
2636 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2637
2638 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2639 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2640
2641 /* only set some bits here, the other bits are set in the dsa state */
2642 shader->db_shader_control = db_shader_control;
2643 shader->ps_depth_export = z_export | stencil_export | mask_export;
2644
2645 shader->sprite_coord_enable = sprite_coord_enable;
2646 if (rctx->rasterizer)
2647 shader->flatshade = rctx->rasterizer->flatshade;
2648 }
2649
2650 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2651 {
2652 struct r600_command_buffer *cb = &shader->command_buffer;
2653 struct r600_shader *rshader = &shader->shader;
2654 unsigned spi_vs_out_id[10] = {};
2655 unsigned i, tmp, nparams = 0;
2656
2657 for (i = 0; i < rshader->noutput; i++) {
2658 if (rshader->output[i].spi_sid) {
2659 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2660 spi_vs_out_id[nparams / 4] |= tmp;
2661 nparams++;
2662 }
2663 }
2664
2665 r600_init_command_buffer(cb, 32);
2666
2667 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2668 for (i = 0; i < 10; i++) {
2669 r600_store_value(cb, spi_vs_out_id[i]);
2670 }
2671
2672 /* Certain attributes (position, psize, etc.) don't count as params.
2673 * VS is required to export at least one param and r600_shader_from_tgsi()
2674 * takes care of adding a dummy export.
2675 */
2676 if (nparams < 1)
2677 nparams = 1;
2678
2679 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2680 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2681 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2682 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2683 S_028868_STACK_SIZE(rshader->bc.nstack));
2684 if (rshader->vs_position_window_space) {
2685 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2686 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
2687 } else {
2688 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2689 S_028818_VTX_W0_FMT(1) |
2690 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2691 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2692 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2693
2694 }
2695 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2696 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2697
2698 shader->pa_cl_vs_out_cntl =
2699 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2700 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2701 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2702 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
2703 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
2704 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) |
2705 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport);
2706 }
2707
2708 #define RV610_GSVS_ALIGN 32
2709 #define R600_GSVS_ALIGN 16
2710
2711 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2712 {
2713 struct r600_context *rctx = (struct r600_context *)ctx;
2714 struct r600_command_buffer *cb = &shader->command_buffer;
2715 struct r600_shader *rshader = &shader->shader;
2716 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
2717 unsigned gsvs_itemsize =
2718 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2;
2719
2720 /* some r600s needs gsvs itemsize aligned to cacheline size
2721 this was fixed in rs780 and above. */
2722 switch (rctx->b.family) {
2723 case CHIP_RV610:
2724 gsvs_itemsize = align(gsvs_itemsize, RV610_GSVS_ALIGN);
2725 break;
2726 case CHIP_R600:
2727 case CHIP_RV630:
2728 case CHIP_RV670:
2729 case CHIP_RV620:
2730 case CHIP_RV635:
2731 gsvs_itemsize = align(gsvs_itemsize, R600_GSVS_ALIGN);
2732 break;
2733 default:
2734 break;
2735 }
2736
2737 r600_init_command_buffer(cb, 64);
2738
2739 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2740 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
2741
2742 if (rctx->b.chip_class >= R700) {
2743 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
2744 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
2745 }
2746 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
2747 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
2748
2749 r600_store_context_reg(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE,
2750 cp_shader->ring_item_sizes[0] >> 2);
2751
2752 r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
2753 (rshader->ring_item_sizes[0]) >> 2);
2754
2755 r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE,
2756 gsvs_itemsize);
2757
2758 /* FIXME calculate these values somehow ??? */
2759 r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2);
2760 r600_store_value(cb, 0x80); /* GS_PER_ES */
2761 r600_store_value(cb, 0x100); /* ES_PER_GS */
2762 r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1);
2763 r600_store_value(cb, 0x2); /* GS_PER_VS */
2764
2765 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS,
2766 S_02887C_NUM_GPRS(rshader->bc.ngpr) |
2767 S_02887C_STACK_SIZE(rshader->bc.nstack));
2768 r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, 0);
2769 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2770 }
2771
2772 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2773 {
2774 struct r600_command_buffer *cb = &shader->command_buffer;
2775 struct r600_shader *rshader = &shader->shader;
2776
2777 r600_init_command_buffer(cb, 32);
2778
2779 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
2780 S_028890_NUM_GPRS(rshader->bc.ngpr) |
2781 S_028890_STACK_SIZE(rshader->bc.nstack));
2782 r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, 0);
2783 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2784 }
2785
2786
2787 void *r600_create_resolve_blend(struct r600_context *rctx)
2788 {
2789 struct pipe_blend_state blend;
2790 unsigned i;
2791
2792 memset(&blend, 0, sizeof(blend));
2793 blend.independent_blend_enable = true;
2794 for (i = 0; i < 2; i++) {
2795 blend.rt[i].colormask = 0xf;
2796 blend.rt[i].blend_enable = 1;
2797 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2798 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2799 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2800 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2801 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2802 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2803 }
2804 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2805 }
2806
2807 void *r700_create_resolve_blend(struct r600_context *rctx)
2808 {
2809 struct pipe_blend_state blend;
2810
2811 memset(&blend, 0, sizeof(blend));
2812 blend.independent_blend_enable = true;
2813 blend.rt[0].colormask = 0xf;
2814 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2815 }
2816
2817 void *r600_create_decompress_blend(struct r600_context *rctx)
2818 {
2819 struct pipe_blend_state blend;
2820
2821 memset(&blend, 0, sizeof(blend));
2822 blend.independent_blend_enable = true;
2823 blend.rt[0].colormask = 0xf;
2824 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2825 }
2826
2827 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2828 {
2829 struct pipe_depth_stencil_alpha_state dsa;
2830 boolean quirk = false;
2831
2832 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2833 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2834 quirk = true;
2835
2836 memset(&dsa, 0, sizeof(dsa));
2837
2838 if (quirk) {
2839 dsa.depth.enabled = 1;
2840 dsa.depth.func = PIPE_FUNC_LEQUAL;
2841 dsa.stencil[0].enabled = 1;
2842 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2843 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2844 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2845 dsa.stencil[0].writemask = 0xff;
2846 }
2847
2848 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2849 }
2850
2851 void r600_update_db_shader_control(struct r600_context * rctx)
2852 {
2853 bool dual_export;
2854 unsigned db_shader_control;
2855 uint8_t ps_conservative_z;
2856
2857 if (!rctx->ps_shader) {
2858 return;
2859 }
2860
2861 dual_export = rctx->framebuffer.export_16bpc &&
2862 !rctx->ps_shader->current->ps_depth_export;
2863
2864 db_shader_control = rctx->ps_shader->current->db_shader_control |
2865 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2866
2867 ps_conservative_z = rctx->ps_shader->current->shader.ps_conservative_z;
2868
2869 /* When alpha test is enabled we can't trust the hw to make the proper
2870 * decision on the order in which ztest should be run related to fragment
2871 * shader execution.
2872 *
2873 * If alpha test is enabled perform z test after fragment. RE_Z (early
2874 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2875 */
2876 if (rctx->alphatest_state.sx_alpha_test_control) {
2877 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2878 } else {
2879 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2880 }
2881
2882 if (db_shader_control != rctx->db_misc_state.db_shader_control ||
2883 ps_conservative_z != rctx->db_misc_state.ps_conservative_z) {
2884 rctx->db_misc_state.db_shader_control = db_shader_control;
2885 rctx->db_misc_state.ps_conservative_z = ps_conservative_z;
2886 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
2887 }
2888 }
2889
2890 static inline unsigned r600_array_mode(unsigned mode)
2891 {
2892 switch (mode) {
2893 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
2894 break;
2895 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
2896 break;
2897 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
2898 default:
2899 case RADEON_SURF_MODE_LINEAR: return V_0280A0_ARRAY_LINEAR_GENERAL;
2900 }
2901 }
2902
2903 static boolean r600_dma_copy_tile(struct r600_context *rctx,
2904 struct pipe_resource *dst,
2905 unsigned dst_level,
2906 unsigned dst_x,
2907 unsigned dst_y,
2908 unsigned dst_z,
2909 struct pipe_resource *src,
2910 unsigned src_level,
2911 unsigned src_x,
2912 unsigned src_y,
2913 unsigned src_z,
2914 unsigned copy_height,
2915 unsigned pitch,
2916 unsigned bpp)
2917 {
2918 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
2919 struct r600_texture *rsrc = (struct r600_texture*)src;
2920 struct r600_texture *rdst = (struct r600_texture*)dst;
2921 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
2922 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
2923 uint64_t base, addr;
2924
2925 dst_mode = rdst->surface.level[dst_level].mode;
2926 src_mode = rsrc->surface.level[src_level].mode;
2927 /* downcast linear aligned to linear to simplify test */
2928 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
2929 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
2930 assert(dst_mode != src_mode);
2931
2932 y = 0;
2933 lbpp = util_logbase2(bpp);
2934 pitch_tile_max = ((pitch / bpp) / 8) - 1;
2935
2936 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
2937 /* T2L */
2938 array_mode = r600_array_mode(src_mode);
2939 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
2940 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2941 /* linear height must be the same as the slice tile max height, it's ok even
2942 * if the linear destination/source have smaller heigh as the size of the
2943 * dma packet will be using the copy_height which is always smaller or equal
2944 * to the linear height
2945 */
2946 height = rsrc->surface.level[src_level].npix_y;
2947 detile = 1;
2948 x = src_x;
2949 y = src_y;
2950 z = src_z;
2951 base = rsrc->surface.level[src_level].offset;
2952 addr = rdst->surface.level[dst_level].offset;
2953 addr += rdst->surface.level[dst_level].slice_size * dst_z;
2954 addr += dst_y * pitch + dst_x * bpp;
2955 } else {
2956 /* L2T */
2957 array_mode = r600_array_mode(dst_mode);
2958 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
2959 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2960 /* linear height must be the same as the slice tile max height, it's ok even
2961 * if the linear destination/source have smaller heigh as the size of the
2962 * dma packet will be using the copy_height which is always smaller or equal
2963 * to the linear height
2964 */
2965 height = rdst->surface.level[dst_level].npix_y;
2966 detile = 0;
2967 x = dst_x;
2968 y = dst_y;
2969 z = dst_z;
2970 base = rdst->surface.level[dst_level].offset;
2971 addr = rsrc->surface.level[src_level].offset;
2972 addr += rsrc->surface.level[src_level].slice_size * src_z;
2973 addr += src_y * pitch + src_x * bpp;
2974 }
2975 /* check that we are in dw/base alignment constraint */
2976 if (addr % 4 || base % 256) {
2977 return FALSE;
2978 }
2979
2980 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2981 * line in the blit. Compute max 8 line we can copy in the size limit
2982 */
2983 cheight = ((R600_DMA_COPY_MAX_SIZE_DW * 4) / pitch) & 0xfffffff8;
2984 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
2985 r600_need_dma_space(&rctx->b, ncopy * 7);
2986
2987 for (i = 0; i < ncopy; i++) {
2988 cheight = cheight > copy_height ? copy_height : cheight;
2989 size = (cheight * pitch) / 4;
2990 /* emit reloc before writing cs so that cs is always in consistent state */
2991 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, RADEON_USAGE_READ,
2992 RADEON_PRIO_SDMA_TEXTURE);
2993 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE,
2994 RADEON_PRIO_SDMA_TEXTURE);
2995 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 1, 0, size);
2996 cs->buf[cs->cdw++] = base >> 8;
2997 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
2998 (lbpp << 24) | ((height - 1) << 10) |
2999 pitch_tile_max;
3000 cs->buf[cs->cdw++] = (slice_tile_max << 12) | (z << 0);
3001 cs->buf[cs->cdw++] = (x << 3) | (y << 17);
3002 cs->buf[cs->cdw++] = addr & 0xfffffffc;
3003 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
3004 copy_height -= cheight;
3005 addr += cheight * pitch;
3006 y += cheight;
3007 }
3008 return TRUE;
3009 }
3010
3011 static void r600_dma_copy(struct pipe_context *ctx,
3012 struct pipe_resource *dst,
3013 unsigned dst_level,
3014 unsigned dstx, unsigned dsty, unsigned dstz,
3015 struct pipe_resource *src,
3016 unsigned src_level,
3017 const struct pipe_box *src_box)
3018 {
3019 struct r600_context *rctx = (struct r600_context *)ctx;
3020 struct r600_texture *rsrc = (struct r600_texture*)src;
3021 struct r600_texture *rdst = (struct r600_texture*)dst;
3022 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3023 unsigned src_w, dst_w;
3024 unsigned src_x, src_y;
3025 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3026
3027 if (rctx->b.dma.cs == NULL) {
3028 goto fallback;
3029 }
3030
3031 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3032 if (dst_x % 4 || src_box->x % 4 || src_box->width % 4)
3033 goto fallback;
3034
3035 r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3036 return;
3037 }
3038
3039 if (src->format != dst->format || src_box->depth > 1) {
3040 goto fallback;
3041 }
3042
3043 src_x = util_format_get_nblocksx(src->format, src_box->x);
3044 dst_x = util_format_get_nblocksx(src->format, dst_x);
3045 src_y = util_format_get_nblocksy(src->format, src_box->y);
3046 dst_y = util_format_get_nblocksy(src->format, dst_y);
3047
3048 bpp = rdst->surface.bpe;
3049 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
3050 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
3051 src_w = rsrc->surface.level[src_level].npix_x;
3052 dst_w = rdst->surface.level[dst_level].npix_x;
3053 copy_height = src_box->height / rsrc->surface.blk_h;
3054
3055 dst_mode = rdst->surface.level[dst_level].mode;
3056 src_mode = rsrc->surface.level[src_level].mode;
3057 /* downcast linear aligned to linear to simplify test */
3058 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3059 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3060
3061 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3062 /* strict requirement on r6xx/r7xx */
3063 goto fallback;
3064 }
3065 /* lot of constraint on alignment this should capture them all */
3066 if (src_pitch % 8 || src_box->y % 8 || dst_y % 8) {
3067 goto fallback;
3068 }
3069
3070 if (src_mode == dst_mode) {
3071 uint64_t dst_offset, src_offset, size;
3072
3073 /* simple dma blit would do NOTE code here assume :
3074 * src_box.x/y == 0
3075 * dst_x/y == 0
3076 * dst_pitch == src_pitch
3077 */
3078 src_offset= rsrc->surface.level[src_level].offset;
3079 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3080 src_offset += src_y * src_pitch + src_x * bpp;
3081 dst_offset = rdst->surface.level[dst_level].offset;
3082 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3083 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3084 size = src_box->height * src_pitch;
3085 /* must be dw aligned */
3086 if (dst_offset % 4 || src_offset % 4 || size % 4) {
3087 goto fallback;
3088 }
3089 r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size);
3090 } else {
3091 if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3092 src, src_level, src_x, src_y, src_box->z,
3093 copy_height, dst_pitch, bpp)) {
3094 goto fallback;
3095 }
3096 }
3097 return;
3098
3099 fallback:
3100 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3101 src, src_level, src_box);
3102 }
3103
3104 void r600_init_state_functions(struct r600_context *rctx)
3105 {
3106 unsigned id = 1;
3107 unsigned i;
3108 /* !!!
3109 * To avoid GPU lockup registers must be emited in a specific order
3110 * (no kidding ...). The order below is important and have been
3111 * partialy infered from analyzing fglrx command stream.
3112 *
3113 * Don't reorder atom without carefully checking the effect (GPU lockup
3114 * or piglit regression).
3115 * !!!
3116 */
3117
3118 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
3119
3120 /* shader const */
3121 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
3122 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
3123 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
3124
3125 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3126 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
3127 */
3128 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
3129 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
3130 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
3131 /* resource */
3132 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
3133 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
3134 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
3135 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
3136
3137 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3138
3139 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3140 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3141 rctx->sample_mask.sample_mask = ~0;
3142
3143 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3144 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3145 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3146 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3147 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3148 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3149 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3150 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3151 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3152 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
3153 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3154 r600_init_atom(rctx, &rctx->scissor.atom, id++, r600_emit_scissor_state, 0);
3155 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 0);
3156 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3157 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3158 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3159 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3160 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3161 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3162 for (i = 0; i < R600_NUM_HW_STAGES; i++)
3163 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3164 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0);
3165 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0);
3166
3167 rctx->b.b.create_blend_state = r600_create_blend_state;
3168 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3169 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3170 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3171 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3172 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3173 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3174 rctx->b.b.set_min_samples = r600_set_min_samples;
3175 rctx->b.b.set_scissor_states = r600_set_scissor_states;
3176 rctx->b.b.get_sample_position = r600_get_sample_position;
3177 rctx->b.dma_copy = r600_dma_copy;
3178 }
3179 /* this function must be last */