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r600g: add user clip plane support.
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include <stdio.h>
27 #include <errno.h>
28 #include "util/u_inlines.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "r600_screen.h"
32 #include "r600_context.h"
33 #include "r600_resource.h"
34 #include "r600d.h"
35 #include "r600_state_inlines.h"
36
37 static void *r600_create_blend_state(struct pipe_context *ctx,
38 const struct pipe_blend_state *state)
39 {
40 struct r600_context *rctx = r600_context(ctx);
41
42 return r600_context_state(rctx, pipe_blend_type, state);
43 }
44
45 static void *r600_create_dsa_state(struct pipe_context *ctx,
46 const struct pipe_depth_stencil_alpha_state *state)
47 {
48 struct r600_context *rctx = r600_context(ctx);
49
50 return r600_context_state(rctx, pipe_dsa_type, state);
51 }
52
53 static void *r600_create_rs_state(struct pipe_context *ctx,
54 const struct pipe_rasterizer_state *state)
55 {
56 struct r600_context *rctx = r600_context(ctx);
57
58 return r600_context_state(rctx, pipe_rasterizer_type, state);
59 }
60
61 static void *r600_create_sampler_state(struct pipe_context *ctx,
62 const struct pipe_sampler_state *state)
63 {
64 struct r600_context *rctx = r600_context(ctx);
65
66 return r600_context_state(rctx, pipe_sampler_type, state);
67 }
68
69 static void r600_sampler_view_destroy(struct pipe_context *ctx,
70 struct pipe_sampler_view *state)
71 {
72 struct r600_context_state *rstate = (struct r600_context_state *)state;
73
74 r600_context_state_decref(rstate);
75 }
76
77 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
78 struct pipe_resource *texture,
79 const struct pipe_sampler_view *state)
80 {
81 struct r600_context *rctx = r600_context(ctx);
82 struct r600_context_state *rstate;
83
84 rstate = r600_context_state(rctx, pipe_sampler_type, state);
85 pipe_reference(NULL, &texture->reference);
86 rstate->state.sampler_view.texture = texture;
87 rstate->state.sampler_view.reference.count = 1;
88 rstate->state.sampler_view.context = ctx;
89 return &rstate->state.sampler_view;
90 }
91
92 static void *r600_create_shader_state(struct pipe_context *ctx,
93 const struct pipe_shader_state *state)
94 {
95 struct r600_context *rctx = r600_context(ctx);
96
97 return r600_context_state(rctx, pipe_shader_type, state);
98 }
99
100 static void *r600_create_vertex_elements(struct pipe_context *ctx,
101 unsigned count,
102 const struct pipe_vertex_element *elements)
103 {
104 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
105
106 assert(count < 32);
107 v->count = count;
108 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
109 v->refcount = 1;
110 return v;
111 }
112
113 static void r600_bind_state(struct pipe_context *ctx, void *state)
114 {
115 struct r600_context *rctx = r600_context(ctx);
116 struct r600_context_state *rstate = (struct r600_context_state *)state;
117
118 if (state == NULL)
119 return;
120 switch (rstate->type) {
121 case pipe_rasterizer_type:
122 rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
123 rctx->rasterizer = r600_context_state_incref(rstate);
124 break;
125 case pipe_poly_stipple_type:
126 rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple);
127 rctx->poly_stipple = r600_context_state_incref(rstate);
128 break;
129 case pipe_scissor_type:
130 rctx->scissor = r600_context_state_decref(rctx->scissor);
131 rctx->scissor = r600_context_state_incref(rstate);
132 break;
133 case pipe_clip_type:
134 rctx->clip = r600_context_state_decref(rctx->clip);
135 rctx->clip = r600_context_state_incref(rstate);
136 break;
137 case pipe_depth_type:
138 rctx->depth = r600_context_state_decref(rctx->depth);
139 rctx->depth = r600_context_state_incref(rstate);
140 break;
141 case pipe_stencil_type:
142 rctx->stencil = r600_context_state_decref(rctx->stencil);
143 rctx->stencil = r600_context_state_incref(rstate);
144 break;
145 case pipe_alpha_type:
146 rctx->alpha = r600_context_state_decref(rctx->alpha);
147 rctx->alpha = r600_context_state_incref(rstate);
148 break;
149 case pipe_dsa_type:
150 rctx->dsa = r600_context_state_decref(rctx->dsa);
151 rctx->dsa = r600_context_state_incref(rstate);
152 break;
153 case pipe_blend_type:
154 rctx->blend = r600_context_state_decref(rctx->blend);
155 rctx->blend = r600_context_state_incref(rstate);
156 break;
157 case pipe_framebuffer_type:
158 rctx->framebuffer = r600_context_state_decref(rctx->framebuffer);
159 rctx->framebuffer = r600_context_state_incref(rstate);
160 break;
161 case pipe_stencil_ref_type:
162 rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref);
163 rctx->stencil_ref = r600_context_state_incref(rstate);
164 break;
165 case pipe_viewport_type:
166 rctx->viewport = r600_context_state_decref(rctx->viewport);
167 rctx->viewport = r600_context_state_incref(rstate);
168 break;
169 case pipe_shader_type:
170 case pipe_sampler_type:
171 case pipe_sampler_view_type:
172 default:
173 R600_ERR("invalid type %d\n", rstate->type);
174 return;
175 }
176 }
177
178 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
179 {
180 struct r600_context *rctx = r600_context(ctx);
181 struct r600_context_state *rstate = (struct r600_context_state *)state;
182
183 rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
184 rctx->ps_shader = r600_context_state_incref(rstate);
185 }
186
187 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
188 {
189 struct r600_context *rctx = r600_context(ctx);
190 struct r600_context_state *rstate = (struct r600_context_state *)state;
191
192 rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
193 rctx->vs_shader = r600_context_state_incref(rstate);
194 }
195
196 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
197 {
198 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
199
200 if (v == NULL)
201 return;
202 if (--v->refcount)
203 return;
204 free(v);
205 }
206
207 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
208 {
209 struct r600_context *rctx = r600_context(ctx);
210 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
211
212 r600_delete_vertex_element(ctx, rctx->vertex_elements);
213 rctx->vertex_elements = v;
214 if (v) {
215 v->refcount++;
216 }
217 }
218
219 static void r600_bind_ps_sampler(struct pipe_context *ctx,
220 unsigned count, void **states)
221 {
222 struct r600_context *rctx = r600_context(ctx);
223 struct r600_context_state *rstate;
224 unsigned i;
225
226 for (i = 0; i < rctx->ps_nsampler; i++) {
227 rctx->ps_sampler[i] = r600_context_state_decref(rctx->ps_sampler[i]);
228 }
229 for (i = 0; i < count; i++) {
230 rstate = (struct r600_context_state *)states[i];
231 rctx->ps_sampler[i] = r600_context_state_incref(rstate);
232 }
233 rctx->ps_nsampler = count;
234 }
235
236 static void r600_bind_vs_sampler(struct pipe_context *ctx,
237 unsigned count, void **states)
238 {
239 struct r600_context *rctx = r600_context(ctx);
240 struct r600_context_state *rstate;
241 unsigned i;
242
243 for (i = 0; i < rctx->vs_nsampler; i++) {
244 rctx->vs_sampler[i] = r600_context_state_decref(rctx->vs_sampler[i]);
245 }
246 for (i = 0; i < count; i++) {
247 rstate = (struct r600_context_state *)states[i];
248 rctx->vs_sampler[i] = r600_context_state_incref(rstate);
249 }
250 rctx->vs_nsampler = count;
251 }
252
253 static void r600_delete_state(struct pipe_context *ctx, void *state)
254 {
255 struct r600_context_state *rstate = (struct r600_context_state *)state;
256
257 r600_context_state_decref(rstate);
258 }
259
260 static void r600_set_blend_color(struct pipe_context *ctx,
261 const struct pipe_blend_color *color)
262 {
263 struct r600_context *rctx = r600_context(ctx);
264
265 rctx->blend_color = *color;
266 }
267
268 static void r600_set_clip_state(struct pipe_context *ctx,
269 const struct pipe_clip_state *state)
270 {
271 struct r600_screen *rscreen = r600_screen(ctx->screen);
272 struct r600_context *rctx = r600_context(ctx);
273 struct r600_context_state *rstate;
274
275 rstate = r600_context_state(rctx, pipe_clip_type, state);
276 r600_bind_state(ctx, rstate);
277 /* refcount is taken care of this */
278 r600_delete_state(ctx, rstate);
279 }
280
281 static void r600_set_constant_buffer(struct pipe_context *ctx,
282 uint shader, uint index,
283 struct pipe_resource *buffer)
284 {
285 struct r600_screen *rscreen = r600_screen(ctx->screen);
286 struct r600_context *rctx = r600_context(ctx);
287 unsigned nconstant = 0, i, type, id;
288 struct radeon_state *rstate;
289 struct pipe_transfer *transfer;
290 u32 *ptr;
291
292 switch (shader) {
293 case PIPE_SHADER_VERTEX:
294 id = R600_VS_CONSTANT;
295 type = R600_VS_CONSTANT_TYPE;
296 break;
297 case PIPE_SHADER_FRAGMENT:
298 id = R600_PS_CONSTANT;
299 type = R600_PS_CONSTANT_TYPE;
300 break;
301 default:
302 R600_ERR("unsupported %d\n", shader);
303 return;
304 }
305 if (buffer && buffer->width0 > 0) {
306 nconstant = buffer->width0 / 16;
307 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
308 if (ptr == NULL)
309 return;
310 for (i = 0; i < nconstant; i++) {
311 rstate = radeon_state(rscreen->rw, type, id + i);
312 if (rstate == NULL)
313 return;
314 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
315 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
316 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
317 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
318 if (radeon_state_pm4(rstate))
319 return;
320 if (radeon_draw_set_new(rctx->draw, rstate))
321 return;
322 }
323 pipe_buffer_unmap(ctx, buffer, transfer);
324 }
325 }
326
327 static void r600_set_ps_sampler_view(struct pipe_context *ctx,
328 unsigned count,
329 struct pipe_sampler_view **views)
330 {
331 struct r600_context *rctx = r600_context(ctx);
332 struct r600_context_state *rstate;
333 unsigned i;
334
335 for (i = 0; i < rctx->ps_nsampler_view; i++) {
336 rctx->ps_sampler_view[i] = r600_context_state_decref(rctx->ps_sampler_view[i]);
337 }
338 for (i = 0; i < count; i++) {
339 rstate = (struct r600_context_state *)views[i];
340 rctx->ps_sampler_view[i] = r600_context_state_incref(rstate);
341 }
342 rctx->ps_nsampler_view = count;
343 }
344
345 static void r600_set_vs_sampler_view(struct pipe_context *ctx,
346 unsigned count,
347 struct pipe_sampler_view **views)
348 {
349 struct r600_context *rctx = r600_context(ctx);
350 struct r600_context_state *rstate;
351 unsigned i;
352
353 for (i = 0; i < rctx->vs_nsampler_view; i++) {
354 rctx->vs_sampler_view[i] = r600_context_state_decref(rctx->vs_sampler_view[i]);
355 }
356 for (i = 0; i < count; i++) {
357 rstate = (struct r600_context_state *)views[i];
358 rctx->vs_sampler_view[i] = r600_context_state_incref(rstate);
359 }
360 rctx->vs_nsampler_view = count;
361 }
362
363 static void r600_set_framebuffer_state(struct pipe_context *ctx,
364 const struct pipe_framebuffer_state *state)
365 {
366 struct r600_context *rctx = r600_context(ctx);
367 struct r600_context_state *rstate;
368
369 rstate = r600_context_state(rctx, pipe_framebuffer_type, state);
370 r600_bind_state(ctx, rstate);
371 }
372
373 static void r600_set_polygon_stipple(struct pipe_context *ctx,
374 const struct pipe_poly_stipple *state)
375 {
376 }
377
378 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
379 {
380 }
381
382 static void r600_set_scissor_state(struct pipe_context *ctx,
383 const struct pipe_scissor_state *state)
384 {
385 struct r600_context *rctx = r600_context(ctx);
386 struct r600_context_state *rstate;
387
388 rstate = r600_context_state(rctx, pipe_scissor_type, state);
389 r600_bind_state(ctx, rstate);
390 /* refcount is taken care of this */
391 r600_delete_state(ctx, rstate);
392 }
393
394 static void r600_set_stencil_ref(struct pipe_context *ctx,
395 const struct pipe_stencil_ref *state)
396 {
397 struct r600_context *rctx = r600_context(ctx);
398 struct r600_context_state *rstate;
399
400 rstate = r600_context_state(rctx, pipe_stencil_ref_type, state);
401 r600_bind_state(ctx, rstate);
402 /* refcount is taken care of this */
403 r600_delete_state(ctx, rstate);
404 }
405
406 static void r600_set_vertex_buffers(struct pipe_context *ctx,
407 unsigned count,
408 const struct pipe_vertex_buffer *buffers)
409 {
410 struct r600_context *rctx = r600_context(ctx);
411 unsigned i;
412
413 for (i = 0; i < rctx->nvertex_buffer; i++) {
414 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
415 }
416 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
417 for (i = 0; i < count; i++) {
418 rctx->vertex_buffer[i].buffer = NULL;
419 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
420 }
421 rctx->nvertex_buffer = count;
422 }
423
424 static void r600_set_index_buffer(struct pipe_context *ctx,
425 const struct pipe_index_buffer *ib)
426 {
427 struct r600_context *rctx = r600_context(ctx);
428
429 if (ib) {
430 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
431 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
432 } else {
433 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
434 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
435 }
436
437 /* TODO make this more like a state */
438 }
439
440 static void r600_set_viewport_state(struct pipe_context *ctx,
441 const struct pipe_viewport_state *state)
442 {
443 struct r600_context *rctx = r600_context(ctx);
444 struct r600_context_state *rstate;
445
446 rstate = r600_context_state(rctx, pipe_viewport_type, state);
447 r600_bind_state(ctx, rstate);
448 r600_delete_state(ctx, rstate);
449 }
450
451 void r600_init_state_functions(struct r600_context *rctx)
452 {
453 rctx->context.create_blend_state = r600_create_blend_state;
454 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
455 rctx->context.create_fs_state = r600_create_shader_state;
456 rctx->context.create_rasterizer_state = r600_create_rs_state;
457 rctx->context.create_sampler_state = r600_create_sampler_state;
458 rctx->context.create_sampler_view = r600_create_sampler_view;
459 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
460 rctx->context.create_vs_state = r600_create_shader_state;
461 rctx->context.bind_blend_state = r600_bind_state;
462 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
463 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
464 rctx->context.bind_fs_state = r600_bind_ps_shader;
465 rctx->context.bind_rasterizer_state = r600_bind_state;
466 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
467 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
468 rctx->context.bind_vs_state = r600_bind_vs_shader;
469 rctx->context.delete_blend_state = r600_delete_state;
470 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
471 rctx->context.delete_fs_state = r600_delete_state;
472 rctx->context.delete_rasterizer_state = r600_delete_state;
473 rctx->context.delete_sampler_state = r600_delete_state;
474 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
475 rctx->context.delete_vs_state = r600_delete_state;
476 rctx->context.set_blend_color = r600_set_blend_color;
477 rctx->context.set_clip_state = r600_set_clip_state;
478 rctx->context.set_constant_buffer = r600_set_constant_buffer;
479 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
480 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
481 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
482 rctx->context.set_sample_mask = r600_set_sample_mask;
483 rctx->context.set_scissor_state = r600_set_scissor_state;
484 rctx->context.set_stencil_ref = r600_set_stencil_ref;
485 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
486 rctx->context.set_index_buffer = r600_set_index_buffer;
487 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
488 rctx->context.set_viewport_state = r600_set_viewport_state;
489 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
490 }
491
492 struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate)
493 {
494 if (rstate == NULL)
495 return NULL;
496 rstate->refcount++;
497 return rstate;
498 }
499
500 struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate)
501 {
502 unsigned i;
503
504 if (rstate == NULL)
505 return NULL;
506 if (--rstate->refcount)
507 return NULL;
508 switch (rstate->type) {
509 case pipe_sampler_view_type:
510 pipe_resource_reference(&rstate->state.sampler_view.texture, NULL);
511 break;
512 case pipe_framebuffer_type:
513 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
514 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], NULL);
515 }
516 pipe_surface_reference(&rstate->state.framebuffer.zsbuf, NULL);
517 break;
518 case pipe_viewport_type:
519 case pipe_depth_type:
520 case pipe_rasterizer_type:
521 case pipe_poly_stipple_type:
522 case pipe_scissor_type:
523 case pipe_clip_type:
524 case pipe_stencil_type:
525 case pipe_alpha_type:
526 case pipe_dsa_type:
527 case pipe_blend_type:
528 case pipe_stencil_ref_type:
529 case pipe_shader_type:
530 case pipe_sampler_type:
531 break;
532 default:
533 R600_ERR("invalid type %d\n", rstate->type);
534 return NULL;
535 }
536 radeon_state_decref(rstate->rstate);
537 FREE(rstate);
538 return NULL;
539 }
540
541 struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state)
542 {
543 struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state);
544 const union pipe_states *states = state;
545 unsigned i;
546 int r;
547
548 if (rstate == NULL)
549 return NULL;
550 rstate->type = type;
551 rstate->refcount = 1;
552
553 switch (rstate->type) {
554 case pipe_sampler_view_type:
555 rstate->state.sampler_view = (*states).sampler_view;
556 rstate->state.sampler_view.texture = NULL;
557 break;
558 case pipe_framebuffer_type:
559 rstate->state.framebuffer = (*states).framebuffer;
560 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
561 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i],
562 (*states).framebuffer.cbufs[i]);
563 }
564 pipe_surface_reference(&rstate->state.framebuffer.zsbuf,
565 (*states).framebuffer.zsbuf);
566 break;
567 case pipe_viewport_type:
568 rstate->state.viewport = (*states).viewport;
569 break;
570 case pipe_depth_type:
571 rstate->state.depth = (*states).depth;
572 break;
573 case pipe_rasterizer_type:
574 rstate->state.rasterizer = (*states).rasterizer;
575 break;
576 case pipe_poly_stipple_type:
577 rstate->state.poly_stipple = (*states).poly_stipple;
578 break;
579 case pipe_scissor_type:
580 rstate->state.scissor = (*states).scissor;
581 break;
582 case pipe_clip_type:
583 rstate->state.clip = (*states).clip;
584 break;
585 case pipe_stencil_type:
586 rstate->state.stencil = (*states).stencil;
587 break;
588 case pipe_alpha_type:
589 rstate->state.alpha = (*states).alpha;
590 break;
591 case pipe_dsa_type:
592 rstate->state.dsa = (*states).dsa;
593 break;
594 case pipe_blend_type:
595 rstate->state.blend = (*states).blend;
596 break;
597 case pipe_stencil_ref_type:
598 rstate->state.stencil_ref = (*states).stencil_ref;
599 break;
600 case pipe_shader_type:
601 rstate->state.shader = (*states).shader;
602 r = r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens);
603 if (r) {
604 r600_context_state_decref(rstate);
605 return NULL;
606 }
607 break;
608 case pipe_sampler_type:
609 rstate->state.sampler = (*states).sampler;
610 break;
611 default:
612 R600_ERR("invalid type %d\n", rstate->type);
613 FREE(rstate);
614 return NULL;
615 }
616 return rstate;
617 }
618
619 static struct radeon_state *r600_blend(struct r600_context *rctx)
620 {
621 struct r600_screen *rscreen = rctx->screen;
622 struct radeon_state *rstate;
623 const struct pipe_blend_state *state = &rctx->blend->state.blend;
624 int i;
625
626 rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
627 if (rstate == NULL)
628 return NULL;
629 rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
630 rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
631 rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
632 rstate->states[R600_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
633 rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
634 rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
635 rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
636 rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
637 rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
638 rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
639 rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
640 rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
641 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
642
643 for (i = 0; i < 8; i++) {
644 unsigned eqRGB = state->rt[i].rgb_func;
645 unsigned srcRGB = state->rt[i].rgb_src_factor;
646 unsigned dstRGB = state->rt[i].rgb_dst_factor;
647
648 unsigned eqA = state->rt[i].alpha_func;
649 unsigned srcA = state->rt[i].alpha_src_factor;
650 unsigned dstA = state->rt[i].alpha_dst_factor;
651 uint32_t bc = 0;
652
653 if (!state->rt[i].blend_enable)
654 continue;
655
656 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
657 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
658 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
659
660 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
661 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
662 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
663 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
664 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
665 }
666
667 rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc;
668 if (i == 0)
669 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
670 }
671
672 if (radeon_state_pm4(rstate)) {
673 radeon_state_decref(rstate);
674 return NULL;
675 }
676 return rstate;
677 }
678
679 static struct radeon_state *r600_ucp(struct r600_context *rctx, int clip)
680 {
681 struct r600_screen *rscreen = rctx->screen;
682 struct radeon_state *rstate;
683 const struct pipe_clip_state *state = &rctx->clip->state.clip;
684
685 rstate = radeon_state(rscreen->rw, R600_CLIP_TYPE, R600_CLIP + clip);
686 if (rstate == NULL)
687 return NULL;
688
689 rstate->states[R600_CLIP__PA_CL_UCP_X_0] = fui(state->ucp[clip][0]);
690 rstate->states[R600_CLIP__PA_CL_UCP_Y_0] = fui(state->ucp[clip][1]);
691 rstate->states[R600_CLIP__PA_CL_UCP_Z_0] = fui(state->ucp[clip][2]);
692 rstate->states[R600_CLIP__PA_CL_UCP_W_0] = fui(state->ucp[clip][3]);
693
694 if (radeon_state_pm4(rstate)) {
695 radeon_state_decref(rstate);
696 return NULL;
697 }
698 return rstate;
699
700 }
701
702 static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
703 {
704 struct r600_screen *rscreen = rctx->screen;
705 struct r600_resource_texture *rtex;
706 struct r600_resource *rbuffer;
707 struct radeon_state *rstate;
708 const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
709 unsigned level = state->cbufs[cb]->level;
710 unsigned pitch, slice;
711 unsigned color_info;
712 unsigned format, swap, ntype;
713 const struct util_format_description *desc;
714
715 rstate = radeon_state(rscreen->rw, R600_CB0_TYPE + cb, R600_CB0 + cb);
716 if (rstate == NULL)
717 return NULL;
718 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
719 rbuffer = &rtex->resource;
720 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
721 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
722 rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
723 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
724 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
725 rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
726 rstate->nbo = 3;
727 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
728 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
729
730 ntype = 0;
731 desc = util_format_description(rtex->resource.base.b.format);
732 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
733 ntype = V_0280A0_NUMBER_SRGB;
734
735 format = r600_translate_colorformat(rtex->resource.base.b.format);
736 swap = r600_translate_colorswap(rtex->resource.base.b.format);
737
738 color_info = S_0280A0_FORMAT(format) |
739 S_0280A0_COMP_SWAP(swap) |
740 S_0280A0_BLEND_CLAMP(1) |
741 S_0280A0_SOURCE_FORMAT(1) |
742 S_0280A0_NUMBER_TYPE(ntype);
743
744 rstate->states[R600_CB0__CB_COLOR0_BASE] = 0x00000000;
745 rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
746 rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
747 S_028060_SLICE_TILE_MAX(slice);
748 rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
749 rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
750 rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
751 rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
752 if (radeon_state_pm4(rstate)) {
753 radeon_state_decref(rstate);
754 return NULL;
755 }
756 return rstate;
757 }
758
759 static struct radeon_state *r600_db(struct r600_context *rctx)
760 {
761 struct r600_screen *rscreen = rctx->screen;
762 struct r600_resource_texture *rtex;
763 struct r600_resource *rbuffer;
764 struct radeon_state *rstate;
765 const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
766 unsigned level;
767 unsigned pitch, slice, format;
768
769 if (state->zsbuf == NULL)
770 return NULL;
771
772 rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
773 if (rstate == NULL)
774 return NULL;
775
776 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
777 rbuffer = &rtex->resource;
778 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
779 rstate->nbo = 1;
780 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
781 level = state->zsbuf->level;
782 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
783 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
784 format = r600_translate_dbformat(state->zsbuf->texture->format);
785 rstate->states[R600_DB__DB_DEPTH_BASE] = 0x00000000;
786 rstate->states[R600_DB__DB_DEPTH_INFO] = 0x00010000 |
787 S_028010_FORMAT(format);
788 rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
789 rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
790 rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
791 S_028000_SLICE_TILE_MAX(slice);
792 if (radeon_state_pm4(rstate)) {
793 radeon_state_decref(rstate);
794 return NULL;
795 }
796 return rstate;
797 }
798
799 static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
800 {
801 const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
802 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
803 const struct pipe_clip_state *clip = NULL;
804 struct r600_screen *rscreen = rctx->screen;
805 struct radeon_state *rstate;
806 float offset_units = 0, offset_scale = 0;
807 char depth = 0;
808 unsigned offset_db_fmt_cntl = 0;
809 unsigned tmp;
810 unsigned prov_vtx = 1;
811
812 if (rctx->clip)
813 clip = &rctx->clip->state.clip;
814 if (fb->zsbuf) {
815 offset_units = state->offset_units;
816 offset_scale = state->offset_scale * 12.0f;
817 switch (fb->zsbuf->texture->format) {
818 case PIPE_FORMAT_Z24X8_UNORM:
819 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
820 depth = -24;
821 offset_units *= 2.0f;
822 break;
823 case PIPE_FORMAT_Z32_FLOAT:
824 depth = -23;
825 offset_units *= 1.0f;
826 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
827 break;
828 case PIPE_FORMAT_Z16_UNORM:
829 depth = -16;
830 offset_units *= 4.0f;
831 break;
832 default:
833 R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
834 return NULL;
835 }
836 }
837 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
838
839 if (state->flatshade_first)
840 prov_vtx = 0;
841
842 rctx->flat_shade = state->flatshade;
843 rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
844 if (rstate == NULL)
845 return NULL;
846 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
847 if (state->sprite_coord_enable) {
848 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
849 S_0286D4_PNT_SPRITE_ENA(1) |
850 S_0286D4_PNT_SPRITE_OVRD_X(2) |
851 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
852 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
853 S_0286D4_PNT_SPRITE_OVRD_W(1);
854 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
855 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
856 S_0286D4_PNT_SPRITE_TOP_1(1);
857 }
858 }
859 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
860 if (clip && clip->nr) {
861 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1);
862 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_CLIP_DISABLE(clip->depth_clamp);
863 }
864 rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] =
865 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
866 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
867 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
868 S_028814_FACE(!state->front_ccw) |
869 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
870 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
871 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
872 rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] =
873 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
874 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
875 rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
876 /* point size 12.4 fixed point */
877 tmp = (unsigned)(state->point_size * 8.0 / 2.0);
878 rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
879 rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
880 rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
881 rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
882 rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
883 rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
884 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
885 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
886 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
887 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
888 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
889 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
890 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
891 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
892 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
893 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
894 if (radeon_state_pm4(rstate)) {
895 radeon_state_decref(rstate);
896 return NULL;
897 }
898 return rstate;
899 }
900
901 static struct radeon_state *r600_scissor(struct r600_context *rctx)
902 {
903 const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
904 const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
905 struct r600_screen *rscreen = rctx->screen;
906 struct radeon_state *rstate;
907 unsigned minx, maxx, miny, maxy;
908 u32 tl, br;
909
910 if (state == NULL) {
911 minx = 0;
912 miny = 0;
913 maxx = fb->cbufs[0]->width;
914 maxy = fb->cbufs[0]->height;
915 } else {
916 minx = state->minx;
917 miny = state->miny;
918 maxx = state->maxx;
919 maxy = state->maxy;
920 }
921 tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
922 br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
923 rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
924 if (rstate == NULL)
925 return NULL;
926 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
927 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
928 rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
929 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
930 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
931 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
932 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
933 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
934 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
935 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
936 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
937 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
938 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
939 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
940 rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
941 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
942 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
943 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
944 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
945 if (radeon_state_pm4(rstate)) {
946 radeon_state_decref(rstate);
947 return NULL;
948 }
949 return rstate;
950 }
951
952 static struct radeon_state *r600_viewport(struct r600_context *rctx)
953 {
954 const struct pipe_viewport_state *state = &rctx->viewport->state.viewport;
955 struct r600_screen *rscreen = rctx->screen;
956 struct radeon_state *rstate;
957
958 rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
959 if (rstate == NULL)
960 return NULL;
961 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
962 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
963 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
964 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
965 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
966 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
967 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
968 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
969 rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
970 if (radeon_state_pm4(rstate)) {
971 radeon_state_decref(rstate);
972 return NULL;
973 }
974 return rstate;
975 }
976
977 static struct radeon_state *r600_dsa(struct r600_context *rctx)
978 {
979 const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
980 const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
981 struct r600_screen *rscreen = rctx->screen;
982 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
983 unsigned stencil_ref_mask, stencil_ref_mask_bf;
984 struct r600_shader *rshader = &rctx->ps_shader->shader;
985 struct radeon_state *rstate;
986 int i;
987
988 rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
989 if (rstate == NULL)
990 return NULL;
991
992 db_shader_control = 0x210;
993 for (i = 0; i < rshader->noutput; i++) {
994 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
995 db_shader_control |= 1;
996 }
997 stencil_ref_mask = 0;
998 stencil_ref_mask_bf = 0;
999 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1000 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1001 S_028800_ZFUNC(state->depth.func);
1002 /* set stencil enable */
1003
1004 if (state->stencil[0].enabled) {
1005 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1006 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
1007 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
1008 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
1009 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
1010
1011 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
1012 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
1013 stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]);
1014 if (state->stencil[1].enabled) {
1015 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1016 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
1017 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
1018 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
1019 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
1020 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
1021 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
1022 stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]);
1023 }
1024 }
1025
1026 alpha_test_control = 0;
1027 alpha_ref = 0;
1028 if (state->alpha.enabled) {
1029 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
1030 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
1031 alpha_ref = fui(state->alpha.ref_value);
1032 }
1033
1034 rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
1035 rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
1036 rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
1037 rstate->states[R600_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
1038 rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
1039 rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref;
1040 rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
1041 rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
1042 rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
1043 rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
1044 rstate->states[R600_DSA__DB_SHADER_CONTROL] = db_shader_control;
1045 rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060;
1046 rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
1047 rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
1048 rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
1049 rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
1050 if (radeon_state_pm4(rstate)) {
1051 radeon_state_decref(rstate);
1052 return NULL;
1053 }
1054 return rstate;
1055 }
1056
1057 static inline unsigned r600_tex_wrap(unsigned wrap)
1058 {
1059 switch (wrap) {
1060 default:
1061 case PIPE_TEX_WRAP_REPEAT:
1062 return V_03C000_SQ_TEX_WRAP;
1063 case PIPE_TEX_WRAP_CLAMP:
1064 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1065 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1066 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1067 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1068 return V_03C000_SQ_TEX_CLAMP_BORDER;
1069 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1070 return V_03C000_SQ_TEX_MIRROR;
1071 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1072 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1073 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1074 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1075 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1076 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1077 }
1078 }
1079
1080 static inline unsigned r600_tex_filter(unsigned filter)
1081 {
1082 switch (filter) {
1083 default:
1084 case PIPE_TEX_FILTER_NEAREST:
1085 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1086 case PIPE_TEX_FILTER_LINEAR:
1087 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1088 }
1089 }
1090
1091 static inline unsigned r600_tex_mipfilter(unsigned filter)
1092 {
1093 switch (filter) {
1094 case PIPE_TEX_MIPFILTER_NEAREST:
1095 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1096 case PIPE_TEX_MIPFILTER_LINEAR:
1097 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1098 default:
1099 case PIPE_TEX_MIPFILTER_NONE:
1100 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1101 }
1102 }
1103
1104 static inline unsigned r600_tex_compare(unsigned compare)
1105 {
1106 switch (compare) {
1107 default:
1108 case PIPE_FUNC_NEVER:
1109 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1110 case PIPE_FUNC_LESS:
1111 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1112 case PIPE_FUNC_EQUAL:
1113 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1114 case PIPE_FUNC_LEQUAL:
1115 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1116 case PIPE_FUNC_GREATER:
1117 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1118 case PIPE_FUNC_NOTEQUAL:
1119 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1120 case PIPE_FUNC_GEQUAL:
1121 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1122 case PIPE_FUNC_ALWAYS:
1123 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1124 }
1125 }
1126
1127 static INLINE u32 S_FIXED(float value, u32 frac_bits)
1128 {
1129 return value * (1 << frac_bits);
1130 }
1131
1132 static struct radeon_state *r600_sampler(struct r600_context *rctx,
1133 const struct pipe_sampler_state *state,
1134 unsigned id)
1135 {
1136 struct r600_screen *rscreen = rctx->screen;
1137 struct radeon_state *rstate;
1138
1139 rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, id);
1140 if (rstate == NULL)
1141 return NULL;
1142 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
1143 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1144 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1145 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1146 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
1147 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
1148 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1149 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func));
1150 /* FIXME LOD it depends on texture base level ... */
1151 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
1152 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1153 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1154 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
1155 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
1156 if (radeon_state_pm4(rstate)) {
1157 radeon_state_decref(rstate);
1158 return NULL;
1159 }
1160 return rstate;
1161 }
1162
1163 static inline unsigned r600_tex_swizzle(unsigned swizzle)
1164 {
1165 switch (swizzle) {
1166 case PIPE_SWIZZLE_RED:
1167 return V_038010_SQ_SEL_X;
1168 case PIPE_SWIZZLE_GREEN:
1169 return V_038010_SQ_SEL_Y;
1170 case PIPE_SWIZZLE_BLUE:
1171 return V_038010_SQ_SEL_Z;
1172 case PIPE_SWIZZLE_ALPHA:
1173 return V_038010_SQ_SEL_W;
1174 case PIPE_SWIZZLE_ZERO:
1175 return V_038010_SQ_SEL_0;
1176 default:
1177 case PIPE_SWIZZLE_ONE:
1178 return V_038010_SQ_SEL_1;
1179 }
1180 }
1181
1182 static inline unsigned r600_format_type(unsigned format_type)
1183 {
1184 switch (format_type) {
1185 default:
1186 case UTIL_FORMAT_TYPE_UNSIGNED:
1187 return V_038010_SQ_FORMAT_COMP_UNSIGNED;
1188 case UTIL_FORMAT_TYPE_SIGNED:
1189 return V_038010_SQ_FORMAT_COMP_SIGNED;
1190 case UTIL_FORMAT_TYPE_FIXED:
1191 return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED;
1192 }
1193 }
1194
1195 static inline unsigned r600_tex_dim(unsigned dim)
1196 {
1197 switch (dim) {
1198 default:
1199 case PIPE_TEXTURE_1D:
1200 return V_038000_SQ_TEX_DIM_1D;
1201 case PIPE_TEXTURE_2D:
1202 return V_038000_SQ_TEX_DIM_2D;
1203 case PIPE_TEXTURE_3D:
1204 return V_038000_SQ_TEX_DIM_3D;
1205 case PIPE_TEXTURE_CUBE:
1206 return V_038000_SQ_TEX_DIM_CUBEMAP;
1207 }
1208 }
1209
1210 static struct radeon_state *r600_resource(struct r600_context *rctx,
1211 const struct pipe_sampler_view *view,
1212 unsigned id)
1213 {
1214 struct r600_screen *rscreen = rctx->screen;
1215 const struct util_format_description *desc;
1216 struct r600_resource_texture *tmp;
1217 struct r600_resource *rbuffer;
1218 struct radeon_state *rstate;
1219 unsigned format;
1220 uint32_t word4 = 0, yuv_format = 0;
1221 unsigned char swizzle[4];
1222
1223 swizzle[0] = view->swizzle_r;
1224 swizzle[1] = view->swizzle_g;
1225 swizzle[2] = view->swizzle_b;
1226 swizzle[3] = view->swizzle_a;
1227 format = r600_translate_texformat(view->texture->format,
1228 swizzle,
1229 &word4, &yuv_format);
1230 if (format == ~0)
1231 return NULL;
1232 desc = util_format_description(view->texture->format);
1233 if (desc == NULL) {
1234 R600_ERR("unknow format %d\n", view->texture->format);
1235 return NULL;
1236 }
1237 rstate = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, id);
1238 if (rstate == NULL) {
1239 return NULL;
1240 }
1241 tmp = (struct r600_resource_texture*)view->texture;
1242 rbuffer = &tmp->resource;
1243 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1244 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1245 rstate->nbo = 2;
1246 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
1247 rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
1248 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
1249 rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
1250
1251 /* FIXME properly handle first level != 0 */
1252 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
1253 S_038000_DIM(r600_tex_dim(view->texture->target)) |
1254 S_038000_PITCH(((tmp->pitch[0] / tmp->bpt) / 8) - 1) |
1255 S_038000_TEX_WIDTH(view->texture->width0 - 1);
1256 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
1257 S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
1258 S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
1259 S_038004_DATA_FORMAT(format);
1260 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = 0;
1261 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
1262 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
1263 word4 |
1264 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
1265 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
1266 S_038010_REQUEST_SIZE(1) |
1267 S_038010_BASE_LEVEL(view->first_level);
1268 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
1269 S_038014_LAST_LEVEL(view->last_level) |
1270 S_038014_BASE_ARRAY(0) |
1271 S_038014_LAST_ARRAY(0);
1272 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
1273 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
1274 if (radeon_state_pm4(rstate)) {
1275 radeon_state_decref(rstate);
1276 return NULL;
1277 }
1278 return rstate;
1279 }
1280
1281 static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
1282 {
1283 struct r600_screen *rscreen = rctx->screen;
1284 struct radeon_state *rstate;
1285 const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
1286 int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
1287 uint32_t color_control, target_mask, shader_mask;
1288 int i;
1289
1290 target_mask = 0;
1291 shader_mask = 0;
1292 color_control = S_028808_PER_MRT_BLEND(1);
1293
1294 for (i = 0; i < nr_cbufs; i++) {
1295 shader_mask |= 0xf << (i * 4);
1296 }
1297
1298 if (pbs->logicop_enable) {
1299 color_control |= (pbs->logicop_func) << 16;
1300 } else {
1301 color_control |= (0xcc << 16);
1302 }
1303
1304 if (pbs->independent_blend_enable) {
1305 for (i = 0; i < nr_cbufs; i++) {
1306 if (pbs->rt[i].blend_enable) {
1307 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
1308 }
1309 target_mask |= (pbs->rt[i].colormask << (4 * i));
1310 }
1311 } else {
1312 for (i = 0; i < nr_cbufs; i++) {
1313 if (pbs->rt[0].blend_enable) {
1314 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
1315 }
1316 target_mask |= (pbs->rt[0].colormask << (4 * i));
1317 }
1318 }
1319 rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
1320 rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
1321 rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
1322 rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
1323 rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
1324 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
1325 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
1326 rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
1327 rstate->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
1328 rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
1329 rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
1330 rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
1331 if (radeon_state_pm4(rstate)) {
1332 radeon_state_decref(rstate);
1333 return NULL;
1334 }
1335 return rstate;
1336 }
1337
1338 int r600_context_hw_states(struct r600_context *rctx)
1339 {
1340 unsigned i;
1341 int r;
1342 int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
1343 int ucp_nclip = 0;
1344
1345 if (rctx->clip)
1346 ucp_nclip = rctx->clip->state.clip.nr;
1347
1348 /* free previous TODO determine what need to be updated, what
1349 * doesn't
1350 */
1351 //radeon_state_decref(rctx->hw_states.config);
1352 rctx->hw_states.cb_cntl = radeon_state_decref(rctx->hw_states.cb_cntl);
1353 rctx->hw_states.db = radeon_state_decref(rctx->hw_states.db);
1354 rctx->hw_states.rasterizer = radeon_state_decref(rctx->hw_states.rasterizer);
1355 rctx->hw_states.scissor = radeon_state_decref(rctx->hw_states.scissor);
1356 rctx->hw_states.dsa = radeon_state_decref(rctx->hw_states.dsa);
1357 rctx->hw_states.blend = radeon_state_decref(rctx->hw_states.blend);
1358 rctx->hw_states.viewport = radeon_state_decref(rctx->hw_states.viewport);
1359 for (i = 0; i < 8; i++) {
1360 rctx->hw_states.cb[i] = radeon_state_decref(rctx->hw_states.cb[i]);
1361 }
1362 for (i = 0; i < 6; i++) {
1363 rctx->hw_states.ucp[i] = radeon_state_decref(rctx->hw_states.ucp[i]);
1364 }
1365 for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
1366 radeon_state_decref(rctx->hw_states.ps_resource[i]);
1367 rctx->hw_states.ps_resource[i] = NULL;
1368 }
1369 rctx->hw_states.ps_nresource = 0;
1370 for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
1371 radeon_state_decref(rctx->hw_states.ps_sampler[i]);
1372 rctx->hw_states.ps_sampler[i] = NULL;
1373 }
1374 rctx->hw_states.ps_nsampler = 0;
1375
1376 /* build new states */
1377 rctx->hw_states.rasterizer = r600_rasterizer(rctx);
1378 rctx->hw_states.scissor = r600_scissor(rctx);
1379 rctx->hw_states.dsa = r600_dsa(rctx);
1380 rctx->hw_states.blend = r600_blend(rctx);
1381 rctx->hw_states.viewport = r600_viewport(rctx);
1382 for (i = 0; i < nr_cbufs; i++) {
1383 rctx->hw_states.cb[i] = r600_cb(rctx, i);
1384 }
1385 for (i = 0; i < ucp_nclip; i++) {
1386 rctx->hw_states.ucp[i] = r600_ucp(rctx, i);
1387 }
1388 rctx->hw_states.db = r600_db(rctx);
1389 rctx->hw_states.cb_cntl = r600_cb_cntl(rctx);
1390
1391 for (i = 0; i < rctx->ps_nsampler; i++) {
1392 if (rctx->ps_sampler[i]) {
1393 rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
1394 &rctx->ps_sampler[i]->state.sampler,
1395 R600_PS_SAMPLER + i);
1396 }
1397 }
1398 rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
1399 for (i = 0; i < rctx->ps_nsampler_view; i++) {
1400 if (rctx->ps_sampler_view[i]) {
1401 rctx->hw_states.ps_resource[i] = r600_resource(rctx,
1402 &rctx->ps_sampler_view[i]->state.sampler_view,
1403 R600_PS_RESOURCE + i);
1404 }
1405 }
1406 rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
1407
1408 /* bind states */
1409 for (i = 0; i < ucp_nclip; i++) {
1410 r = radeon_draw_set(rctx->draw, rctx->hw_states.ucp[i]);
1411 if (r)
1412 return r;
1413 }
1414 r = radeon_draw_set(rctx->draw, rctx->hw_states.db);
1415 if (r)
1416 return r;
1417 r = radeon_draw_set(rctx->draw, rctx->hw_states.rasterizer);
1418 if (r)
1419 return r;
1420 r = radeon_draw_set(rctx->draw, rctx->hw_states.scissor);
1421 if (r)
1422 return r;
1423 r = radeon_draw_set(rctx->draw, rctx->hw_states.dsa);
1424 if (r)
1425 return r;
1426 r = radeon_draw_set(rctx->draw, rctx->hw_states.blend);
1427 if (r)
1428 return r;
1429 r = radeon_draw_set(rctx->draw, rctx->hw_states.viewport);
1430 if (r)
1431 return r;
1432 for (i = 0; i < nr_cbufs; i++) {
1433 r = radeon_draw_set(rctx->draw, rctx->hw_states.cb[i]);
1434 if (r)
1435 return r;
1436 }
1437 r = radeon_draw_set(rctx->draw, rctx->hw_states.config);
1438 if (r)
1439 return r;
1440 r = radeon_draw_set(rctx->draw, rctx->hw_states.cb_cntl);
1441 if (r)
1442 return r;
1443 for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
1444 if (rctx->hw_states.ps_resource[i]) {
1445 r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_resource[i]);
1446 if (r)
1447 return r;
1448 }
1449 }
1450 for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
1451 if (rctx->hw_states.ps_sampler[i]) {
1452 r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_sampler[i]);
1453 if (r)
1454 return r;
1455 }
1456 }
1457 return 0;
1458 }