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r600g: initial alpha test state
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #include <stdio.h>
27 #include <errno.h>
28 #include "util/u_inlines.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "r600_screen.h"
32 #include "r600_context.h"
33 #include "r600_resource.h"
34 #include "r600d.h"
35 #include "r600_reg.h"
36 #include "r600_state_inlines.h"
37
38 static void *r600_create_blend_state(struct pipe_context *ctx,
39 const struct pipe_blend_state *state)
40 {
41 struct r600_context *rctx = r600_context(ctx);
42
43 return r600_context_state(rctx, pipe_blend_type, state);
44 }
45
46 static void *r600_create_dsa_state(struct pipe_context *ctx,
47 const struct pipe_depth_stencil_alpha_state *state)
48 {
49 struct r600_context *rctx = r600_context(ctx);
50
51 return r600_context_state(rctx, pipe_dsa_type, state);
52 }
53
54 static void *r600_create_rs_state(struct pipe_context *ctx,
55 const struct pipe_rasterizer_state *state)
56 {
57 struct r600_context *rctx = r600_context(ctx);
58
59 return r600_context_state(rctx, pipe_rasterizer_type, state);
60 }
61
62 static void *r600_create_sampler_state(struct pipe_context *ctx,
63 const struct pipe_sampler_state *state)
64 {
65 struct r600_context *rctx = r600_context(ctx);
66
67 return r600_context_state(rctx, pipe_sampler_type, state);
68 }
69
70 static void r600_sampler_view_destroy(struct pipe_context *ctx,
71 struct pipe_sampler_view *state)
72 {
73 struct r600_context_state *rstate = (struct r600_context_state *)state;
74
75 r600_context_state_decref(rstate);
76 }
77
78 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
79 struct pipe_resource *texture,
80 const struct pipe_sampler_view *state)
81 {
82 struct r600_context *rctx = r600_context(ctx);
83 struct r600_context_state *rstate;
84
85 rstate = r600_context_state(rctx, pipe_sampler_type, state);
86 pipe_reference(NULL, &texture->reference);
87 rstate->state.sampler_view.texture = texture;
88 rstate->state.sampler_view.reference.count = 1;
89 rstate->state.sampler_view.context = ctx;
90 return &rstate->state.sampler_view;
91 }
92
93 static void *r600_create_shader_state(struct pipe_context *ctx,
94 const struct pipe_shader_state *state)
95 {
96 struct r600_context *rctx = r600_context(ctx);
97
98 return r600_context_state(rctx, pipe_shader_type, state);
99 }
100
101 static void *r600_create_vertex_elements(struct pipe_context *ctx,
102 unsigned count,
103 const struct pipe_vertex_element *elements)
104 {
105 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
106
107 assert(count < 32);
108 v->count = count;
109 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
110 v->refcount = 1;
111 return v;
112 }
113
114 static void r600_bind_state(struct pipe_context *ctx, void *state)
115 {
116 struct r600_context *rctx = r600_context(ctx);
117 struct r600_context_state *rstate = (struct r600_context_state *)state;
118
119 if (state == NULL)
120 return;
121 switch (rstate->type) {
122 case pipe_rasterizer_type:
123 rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
124 rctx->rasterizer = r600_context_state_incref(rstate);
125 break;
126 case pipe_poly_stipple_type:
127 rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple);
128 rctx->poly_stipple = r600_context_state_incref(rstate);
129 break;
130 case pipe_scissor_type:
131 rctx->scissor = r600_context_state_decref(rctx->scissor);
132 rctx->scissor = r600_context_state_incref(rstate);
133 break;
134 case pipe_clip_type:
135 rctx->clip = r600_context_state_decref(rctx->clip);
136 rctx->clip = r600_context_state_incref(rstate);
137 break;
138 case pipe_depth_type:
139 rctx->depth = r600_context_state_decref(rctx->depth);
140 rctx->depth = r600_context_state_incref(rstate);
141 break;
142 case pipe_stencil_type:
143 rctx->stencil = r600_context_state_decref(rctx->stencil);
144 rctx->stencil = r600_context_state_incref(rstate);
145 break;
146 case pipe_alpha_type:
147 rctx->alpha = r600_context_state_decref(rctx->alpha);
148 rctx->alpha = r600_context_state_incref(rstate);
149 break;
150 case pipe_dsa_type:
151 rctx->dsa = r600_context_state_decref(rctx->dsa);
152 rctx->dsa = r600_context_state_incref(rstate);
153 break;
154 case pipe_blend_type:
155 rctx->blend = r600_context_state_decref(rctx->blend);
156 rctx->blend = r600_context_state_incref(rstate);
157 break;
158 case pipe_framebuffer_type:
159 rctx->framebuffer = r600_context_state_decref(rctx->framebuffer);
160 rctx->framebuffer = r600_context_state_incref(rstate);
161 break;
162 case pipe_stencil_ref_type:
163 rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref);
164 rctx->stencil_ref = r600_context_state_incref(rstate);
165 break;
166 case pipe_viewport_type:
167 rctx->viewport = r600_context_state_decref(rctx->viewport);
168 rctx->viewport = r600_context_state_incref(rstate);
169 break;
170 case pipe_shader_type:
171 case pipe_sampler_type:
172 case pipe_sampler_view_type:
173 default:
174 R600_ERR("invalid type %d\n", rstate->type);
175 return;
176 }
177 }
178
179 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
180 {
181 struct r600_context *rctx = r600_context(ctx);
182 struct r600_context_state *rstate = (struct r600_context_state *)state;
183
184 rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
185 rctx->ps_shader = r600_context_state_incref(rstate);
186 }
187
188 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
189 {
190 struct r600_context *rctx = r600_context(ctx);
191 struct r600_context_state *rstate = (struct r600_context_state *)state;
192
193 rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
194 rctx->vs_shader = r600_context_state_incref(rstate);
195 }
196
197 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
198 {
199 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
200
201 if (v == NULL)
202 return;
203 if (--v->refcount)
204 return;
205 free(v);
206 }
207
208 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
209 {
210 struct r600_context *rctx = r600_context(ctx);
211 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
212
213 r600_delete_vertex_element(ctx, rctx->vertex_elements);
214 rctx->vertex_elements = v;
215 if (v) {
216 v->refcount++;
217 }
218 }
219
220 static void r600_bind_ps_sampler(struct pipe_context *ctx,
221 unsigned count, void **states)
222 {
223 struct r600_context *rctx = r600_context(ctx);
224 struct r600_context_state *rstate;
225 unsigned i;
226
227 for (i = 0; i < rctx->ps_nsampler; i++) {
228 rctx->ps_sampler[i] = r600_context_state_decref(rctx->ps_sampler[i]);
229 }
230 for (i = 0; i < count; i++) {
231 rstate = (struct r600_context_state *)states[i];
232 rctx->ps_sampler[i] = r600_context_state_incref(rstate);
233 }
234 rctx->ps_nsampler = count;
235 }
236
237 static void r600_bind_vs_sampler(struct pipe_context *ctx,
238 unsigned count, void **states)
239 {
240 struct r600_context *rctx = r600_context(ctx);
241 struct r600_context_state *rstate;
242 unsigned i;
243
244 for (i = 0; i < rctx->vs_nsampler; i++) {
245 rctx->vs_sampler[i] = r600_context_state_decref(rctx->vs_sampler[i]);
246 }
247 for (i = 0; i < count; i++) {
248 rstate = (struct r600_context_state *)states[i];
249 rctx->vs_sampler[i] = r600_context_state_incref(rstate);
250 }
251 rctx->vs_nsampler = count;
252 }
253
254 static void r600_delete_state(struct pipe_context *ctx, void *state)
255 {
256 struct r600_context_state *rstate = (struct r600_context_state *)state;
257
258 r600_context_state_decref(rstate);
259 }
260
261 static void r600_set_blend_color(struct pipe_context *ctx,
262 const struct pipe_blend_color *color)
263 {
264 struct r600_context *rctx = r600_context(ctx);
265
266 rctx->blend_color = *color;
267 }
268
269 static void r600_set_clip_state(struct pipe_context *ctx,
270 const struct pipe_clip_state *state)
271 {
272 }
273
274 static void r600_set_constant_buffer(struct pipe_context *ctx,
275 uint shader, uint index,
276 struct pipe_resource *buffer)
277 {
278 struct r600_screen *rscreen = r600_screen(ctx->screen);
279 struct r600_context *rctx = r600_context(ctx);
280 unsigned nconstant = 0, i, type, id;
281 struct radeon_state *rstate;
282 struct pipe_transfer *transfer;
283 u32 *ptr;
284
285 switch (shader) {
286 case PIPE_SHADER_VERTEX:
287 id = R600_VS_CONSTANT;
288 type = R600_VS_CONSTANT_TYPE;
289 break;
290 case PIPE_SHADER_FRAGMENT:
291 id = R600_PS_CONSTANT;
292 type = R600_PS_CONSTANT_TYPE;
293 break;
294 default:
295 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, shader);
296 return;
297 }
298 if (buffer && buffer->width0 > 0) {
299 nconstant = buffer->width0 / 16;
300 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
301 if (ptr == NULL)
302 return;
303 for (i = 0; i < nconstant; i++) {
304 rstate = radeon_state(rscreen->rw, type, id + i);
305 if (rstate == NULL)
306 return;
307 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
308 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
309 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
310 rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
311 if (radeon_state_pm4(rstate))
312 return;
313 if (radeon_draw_set_new(rctx->draw, rstate))
314 return;
315 }
316 pipe_buffer_unmap(ctx, buffer, transfer);
317 }
318 }
319
320 static void r600_set_ps_sampler_view(struct pipe_context *ctx,
321 unsigned count,
322 struct pipe_sampler_view **views)
323 {
324 struct r600_context *rctx = r600_context(ctx);
325 struct r600_context_state *rstate;
326 unsigned i;
327
328 for (i = 0; i < rctx->ps_nsampler_view; i++) {
329 rctx->ps_sampler_view[i] = r600_context_state_decref(rctx->ps_sampler_view[i]);
330 }
331 for (i = 0; i < count; i++) {
332 rstate = (struct r600_context_state *)views[i];
333 rctx->ps_sampler_view[i] = r600_context_state_incref(rstate);
334 }
335 rctx->ps_nsampler_view = count;
336 }
337
338 static void r600_set_vs_sampler_view(struct pipe_context *ctx,
339 unsigned count,
340 struct pipe_sampler_view **views)
341 {
342 struct r600_context *rctx = r600_context(ctx);
343 struct r600_context_state *rstate;
344 unsigned i;
345
346 for (i = 0; i < rctx->vs_nsampler_view; i++) {
347 rctx->vs_sampler_view[i] = r600_context_state_decref(rctx->vs_sampler_view[i]);
348 }
349 for (i = 0; i < count; i++) {
350 rstate = (struct r600_context_state *)views[i];
351 rctx->vs_sampler_view[i] = r600_context_state_incref(rstate);
352 }
353 rctx->vs_nsampler_view = count;
354 }
355
356 static void r600_set_framebuffer_state(struct pipe_context *ctx,
357 const struct pipe_framebuffer_state *state)
358 {
359 struct r600_context *rctx = r600_context(ctx);
360 struct r600_context_state *rstate;
361
362 rstate = r600_context_state(rctx, pipe_framebuffer_type, state);
363 r600_bind_state(ctx, rstate);
364 }
365
366 static void r600_set_polygon_stipple(struct pipe_context *ctx,
367 const struct pipe_poly_stipple *state)
368 {
369 }
370
371 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
372 {
373 }
374
375 static void r600_set_scissor_state(struct pipe_context *ctx,
376 const struct pipe_scissor_state *state)
377 {
378 struct r600_context *rctx = r600_context(ctx);
379 struct r600_context_state *rstate;
380
381 rstate = r600_context_state(rctx, pipe_scissor_type, state);
382 r600_bind_state(ctx, rstate);
383 }
384
385 static void r600_set_stencil_ref(struct pipe_context *ctx,
386 const struct pipe_stencil_ref *state)
387 {
388 struct r600_context *rctx = r600_context(ctx);
389 struct r600_context_state *rstate;
390
391 rstate = r600_context_state(rctx, pipe_stencil_ref_type, state);
392 r600_bind_state(ctx, rstate);
393 }
394
395 static void r600_set_vertex_buffers(struct pipe_context *ctx,
396 unsigned count,
397 const struct pipe_vertex_buffer *buffers)
398 {
399 struct r600_context *rctx = r600_context(ctx);
400 unsigned i;
401
402 for (i = 0; i < rctx->nvertex_buffer; i++) {
403 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
404 }
405 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
406 for (i = 0; i < count; i++) {
407 rctx->vertex_buffer[i].buffer = NULL;
408 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
409 }
410 rctx->nvertex_buffer = count;
411 }
412
413 static void r600_set_index_buffer(struct pipe_context *ctx,
414 const struct pipe_index_buffer *ib)
415 {
416 struct r600_context *rctx = r600_context(ctx);
417
418 if (ib) {
419 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
420 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
421 }
422 else {
423 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
424 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
425 }
426
427 /* TODO make this more like a state */
428 }
429
430 static void r600_set_viewport_state(struct pipe_context *ctx,
431 const struct pipe_viewport_state *state)
432 {
433 struct r600_context *rctx = r600_context(ctx);
434 struct r600_context_state *rstate;
435
436 rstate = r600_context_state(rctx, pipe_viewport_type, state);
437 r600_bind_state(ctx, rstate);
438 }
439
440 void r600_init_state_functions(struct r600_context *rctx)
441 {
442 rctx->context.create_blend_state = r600_create_blend_state;
443 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
444 rctx->context.create_fs_state = r600_create_shader_state;
445 rctx->context.create_rasterizer_state = r600_create_rs_state;
446 rctx->context.create_sampler_state = r600_create_sampler_state;
447 rctx->context.create_sampler_view = r600_create_sampler_view;
448 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
449 rctx->context.create_vs_state = r600_create_shader_state;
450 rctx->context.bind_blend_state = r600_bind_state;
451 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
452 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
453 rctx->context.bind_fs_state = r600_bind_ps_shader;
454 rctx->context.bind_rasterizer_state = r600_bind_state;
455 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
456 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
457 rctx->context.bind_vs_state = r600_bind_vs_shader;
458 rctx->context.delete_blend_state = r600_delete_state;
459 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
460 rctx->context.delete_fs_state = r600_delete_state;
461 rctx->context.delete_rasterizer_state = r600_delete_state;
462 rctx->context.delete_sampler_state = r600_delete_state;
463 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
464 rctx->context.delete_vs_state = r600_delete_state;
465 rctx->context.set_blend_color = r600_set_blend_color;
466 rctx->context.set_clip_state = r600_set_clip_state;
467 rctx->context.set_constant_buffer = r600_set_constant_buffer;
468 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
469 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
470 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
471 rctx->context.set_sample_mask = r600_set_sample_mask;
472 rctx->context.set_scissor_state = r600_set_scissor_state;
473 rctx->context.set_stencil_ref = r600_set_stencil_ref;
474 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
475 rctx->context.set_index_buffer = r600_set_index_buffer;
476 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
477 rctx->context.set_viewport_state = r600_set_viewport_state;
478 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
479 }
480
481 struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate)
482 {
483 if (rstate == NULL)
484 return NULL;
485 rstate->refcount++;
486 return rstate;
487 }
488
489 struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate)
490 {
491 unsigned i;
492
493 if (rstate == NULL)
494 return NULL;
495 if (--rstate->refcount)
496 return NULL;
497 switch (rstate->type) {
498 case pipe_sampler_view_type:
499 pipe_resource_reference(&rstate->state.sampler_view.texture, NULL);
500 break;
501 case pipe_framebuffer_type:
502 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
503 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], NULL);
504 }
505 pipe_surface_reference(&rstate->state.framebuffer.zsbuf, NULL);
506 break;
507 case pipe_viewport_type:
508 case pipe_depth_type:
509 case pipe_rasterizer_type:
510 case pipe_poly_stipple_type:
511 case pipe_scissor_type:
512 case pipe_clip_type:
513 case pipe_stencil_type:
514 case pipe_alpha_type:
515 case pipe_dsa_type:
516 case pipe_blend_type:
517 case pipe_stencil_ref_type:
518 case pipe_shader_type:
519 case pipe_sampler_type:
520 break;
521 default:
522 R600_ERR("invalid type %d\n", rstate->type);
523 return NULL;
524 }
525 radeon_state_decref(rstate->rstate);
526 FREE(rstate);
527 return NULL;
528 }
529
530 struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state)
531 {
532 struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state);
533 const union pipe_states *states = state;
534 unsigned i;
535 int r;
536
537 if (rstate == NULL)
538 return NULL;
539 rstate->type = type;
540 rstate->refcount = 1;
541
542 switch (rstate->type) {
543 case pipe_sampler_view_type:
544 rstate->state.sampler_view = (*states).sampler_view;
545 rstate->state.sampler_view.texture = NULL;
546 break;
547 case pipe_framebuffer_type:
548 rstate->state.framebuffer = (*states).framebuffer;
549 for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
550 pipe_surface_reference(&rstate->state.framebuffer.cbufs[i],
551 (*states).framebuffer.cbufs[i]);
552 }
553 pipe_surface_reference(&rstate->state.framebuffer.zsbuf,
554 (*states).framebuffer.zsbuf);
555 break;
556 case pipe_viewport_type:
557 rstate->state.viewport = (*states).viewport;
558 break;
559 case pipe_depth_type:
560 rstate->state.depth = (*states).depth;
561 break;
562 case pipe_rasterizer_type:
563 rstate->state.rasterizer = (*states).rasterizer;
564 break;
565 case pipe_poly_stipple_type:
566 rstate->state.poly_stipple = (*states).poly_stipple;
567 break;
568 case pipe_scissor_type:
569 rstate->state.scissor = (*states).scissor;
570 break;
571 case pipe_clip_type:
572 rstate->state.clip = (*states).clip;
573 break;
574 case pipe_stencil_type:
575 rstate->state.stencil = (*states).stencil;
576 break;
577 case pipe_alpha_type:
578 rstate->state.alpha = (*states).alpha;
579 break;
580 case pipe_dsa_type:
581 rstate->state.dsa = (*states).dsa;
582 break;
583 case pipe_blend_type:
584 rstate->state.blend = (*states).blend;
585 break;
586 case pipe_stencil_ref_type:
587 rstate->state.stencil_ref = (*states).stencil_ref;
588 break;
589 case pipe_shader_type:
590 rstate->state.shader = (*states).shader;
591 r = r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens);
592 if (r) {
593 r600_context_state_decref(rstate);
594 return NULL;
595 }
596 break;
597 case pipe_sampler_type:
598 rstate->state.sampler = (*states).sampler;
599 break;
600 default:
601 R600_ERR("invalid type %d\n", rstate->type);
602 FREE(rstate);
603 return NULL;
604 }
605 return rstate;
606 }
607
608 static struct radeon_state *r600_blend(struct r600_context *rctx)
609 {
610 struct r600_screen *rscreen = rctx->screen;
611 struct radeon_state *rstate;
612 const struct pipe_blend_state *state = &rctx->blend->state.blend;
613 int i;
614
615 rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
616 if (rstate == NULL)
617 return NULL;
618 rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
619 rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
620 rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
621 rstate->states[R600_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
622 rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
623 rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
624 rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
625 rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
626 rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
627 rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
628 rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
629 rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
630 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
631
632 for (i = 0; i < 8; i++) {
633
634 unsigned eqRGB = state->rt[i].rgb_func;
635 unsigned srcRGB = state->rt[i].rgb_src_factor;
636 unsigned dstRGB = state->rt[i].rgb_dst_factor;
637
638 unsigned eqA = state->rt[i].alpha_func;
639 unsigned srcA = state->rt[i].alpha_src_factor;
640 unsigned dstA = state->rt[i].alpha_dst_factor;
641 uint32_t bc = 0;
642
643 if (!state->rt[i].blend_enable)
644 continue;
645
646 bc |= r600_translate_blend_function(eqRGB) << CB_BLEND_COLOR_COMB_FCN_SHIFT;
647 bc |= r600_translate_blend_factor(srcRGB) << CB_BLEND_COLOR_SRCBLEND_SHIFT;
648 bc |= r600_translate_blend_factor(dstRGB) << CB_BLEND_COLOR_DESTBLEND_SHIFT;
649
650 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
651 bc |= CB_BLEND_SEPARATE_ALPHA_BLEND;
652 bc |= r600_translate_blend_function(eqA) << CB_BLEND_ALPHA_COMB_FCN_SHIFT;
653 bc |= r600_translate_blend_factor(srcA) << CB_BLEND_ALPHA_SRCBLEND_SHIFT;
654 bc |= r600_translate_blend_factor(dstA) << CB_BLEND_ALPHA_DESTBLEND_SHIFT;
655 }
656
657 rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc;
658 if (i == 0)
659 rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
660 }
661
662 if (radeon_state_pm4(rstate)) {
663 radeon_state_decref(rstate);
664 return NULL;
665 }
666 return rstate;
667 }
668
669 static struct radeon_state *r600_cb0(struct r600_context *rctx)
670 {
671 struct r600_screen *rscreen = rctx->screen;
672 struct r600_resource_texture *rtex;
673 struct r600_resource *rbuffer;
674 struct radeon_state *rstate;
675 const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
676 unsigned level = state->cbufs[0]->level;
677 unsigned pitch, slice;
678
679 rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, R600_CB0);
680 if (rstate == NULL)
681 return NULL;
682 rtex = (struct r600_resource_texture*)state->cbufs[0]->texture;
683 rbuffer = &rtex->resource;
684 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
685 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
686 rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
687 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
688 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
689 rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
690 rstate->nbo = 3;
691 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
692 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[0]->height / 64 - 1;
693 rstate->states[R600_CB0__CB_COLOR0_BASE] = 0x00000000;
694 rstate->states[R600_CB0__CB_COLOR0_INFO] = 0x08110068;
695 rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
696 S_028060_SLICE_TILE_MAX(slice);
697 rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
698 rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
699 rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
700 rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
701 if (radeon_state_pm4(rstate)) {
702 radeon_state_decref(rstate);
703 return NULL;
704 }
705 return rstate;
706 }
707
708 static int r600_db_format(unsigned pformat, unsigned *format)
709 {
710 switch (pformat) {
711 case PIPE_FORMAT_Z24X8_UNORM:
712 *format = V_028010_DEPTH_X8_24;
713 return 0;
714 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
715 *format = V_028010_DEPTH_8_24;
716 return 0;
717 default:
718 *format = V_028010_DEPTH_INVALID;
719 R600_ERR("unsupported %d\n", pformat);
720 return -EINVAL;
721 }
722 }
723
724 static struct radeon_state *r600_db(struct r600_context *rctx)
725 {
726 struct r600_screen *rscreen = rctx->screen;
727 struct r600_resource_texture *rtex;
728 struct r600_resource *rbuffer;
729 struct radeon_state *rstate;
730 const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
731 unsigned level = state->cbufs[0]->level;
732 unsigned pitch, slice, format;
733
734 if (state->zsbuf == NULL)
735 return NULL;
736
737 rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
738 if (rstate == NULL)
739 return NULL;
740
741 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
742 rbuffer = &rtex->resource;
743 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
744 rstate->nbo = 1;
745 rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
746 level = state->zsbuf->level;
747 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
748 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
749 if (r600_db_format(state->zsbuf->texture->format, &format)) {
750 radeon_state_decref(rstate);
751 return NULL;
752 }
753 rstate->states[R600_DB__DB_DEPTH_BASE] = 0x00000000;
754 rstate->states[R600_DB__DB_DEPTH_INFO] = 0x00010000 |
755 S_028010_FORMAT(format);
756 rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
757 rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
758 rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
759 S_028000_SLICE_TILE_MAX(slice);
760 if (radeon_state_pm4(rstate)) {
761 radeon_state_decref(rstate);
762 return NULL;
763 }
764 return rstate;
765 }
766
767 static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
768 {
769 const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
770 struct r600_screen *rscreen = rctx->screen;
771 struct radeon_state *rstate;
772
773 rctx->flat_shade = state->flatshade;
774 rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
775 if (rstate == NULL)
776 return NULL;
777 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
778 rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0x00000000;
779 rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080000 |
780 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
781 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
782 S_028814_FACE(!state->front_ccw);
783 rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] = 0x00000000;
784 rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
785 rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = 0x00080008;
786 rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x00000000;
787 rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
788 rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
789 rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
790 rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
791 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
792 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
793 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
794 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
795 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = 0x00000000;
796 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
797 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = 0x00000000;
798 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = 0x00000000;
799 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = 0x00000000;
800 rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = 0x00000000;
801 if (radeon_state_pm4(rstate)) {
802 radeon_state_decref(rstate);
803 return NULL;
804 }
805 return rstate;
806 }
807
808 static struct radeon_state *r600_scissor(struct r600_context *rctx)
809 {
810 const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
811 struct r600_screen *rscreen = rctx->screen;
812 struct radeon_state *rstate;
813 u32 tl, br;
814
815 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
816 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
817 rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
818 if (rstate == NULL)
819 return NULL;
820 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
821 rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
822 rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
823 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
824 rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
825 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
826 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
827 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
828 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
829 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
830 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
831 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
832 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
833 rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
834 rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
835 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
836 rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
837 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
838 rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
839 if (radeon_state_pm4(rstate)) {
840 radeon_state_decref(rstate);
841 return NULL;
842 }
843 return rstate;
844 }
845
846 static struct radeon_state *r600_viewport(struct r600_context *rctx)
847 {
848 const struct pipe_viewport_state *state = &rctx->viewport->state.viewport;
849 struct r600_screen *rscreen = rctx->screen;
850 struct radeon_state *rstate;
851
852 rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
853 if (rstate == NULL)
854 return NULL;
855 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
856 rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
857 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
858 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
859 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
860 rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
861 rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
862 rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
863 rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
864 if (radeon_state_pm4(rstate)) {
865 radeon_state_decref(rstate);
866 return NULL;
867 }
868 return rstate;
869 }
870
871 static struct radeon_state *r600_dsa(struct r600_context *rctx)
872 {
873 const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
874 struct r600_screen *rscreen = rctx->screen;
875 struct radeon_state *rstate;
876 unsigned db_depth_control, alpha_test_control, alpha_ref;
877
878 rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
879 if (rstate == NULL)
880 return NULL;
881
882 db_depth_control = 0x00700700 | S_028800_Z_ENABLE(state->depth.enabled) | S_028800_Z_WRITE_ENABLE(state->depth.writemask) | S_028800_ZFUNC(state->depth.func);
883 alpha_test_control = 0;
884 alpha_ref = 0;
885 if (state->alpha.enabled) {
886 alpha_test_control = (state->alpha.func) << 0;
887 alpha_test_control |= SX_ALPHA_TEST_ENABLE;
888 alpha_ref = fui(state->alpha.ref_value);
889 }
890
891 rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
892 rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
893 rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
894 rstate->states[R600_DSA__DB_STENCILREFMASK] = 0xFFFFFF00;
895 rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = 0xFFFFFF00;
896 rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref;
897 rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
898 rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
899 rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
900 rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
901 rstate->states[R600_DSA__DB_SHADER_CONTROL] = 0x00000210;
902 rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060;
903 rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
904 rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
905 rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
906 rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
907 if (radeon_state_pm4(rstate)) {
908 radeon_state_decref(rstate);
909 return NULL;
910 }
911 return rstate;
912 }
913
914 static inline unsigned r600_tex_wrap(unsigned wrap)
915 {
916 switch (wrap) {
917 default:
918 case PIPE_TEX_WRAP_REPEAT:
919 return V_03C000_SQ_TEX_WRAP;
920 case PIPE_TEX_WRAP_CLAMP:
921 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
922 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
923 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
924 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
925 return V_03C000_SQ_TEX_CLAMP_BORDER;
926 case PIPE_TEX_WRAP_MIRROR_REPEAT:
927 return V_03C000_SQ_TEX_MIRROR;
928 case PIPE_TEX_WRAP_MIRROR_CLAMP:
929 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
930 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
931 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
932 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
933 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
934 }
935 }
936
937 static inline unsigned r600_tex_filter(unsigned filter)
938 {
939 switch (filter) {
940 default:
941 case PIPE_TEX_FILTER_NEAREST:
942 return V_03C000_SQ_TEX_XY_FILTER_POINT;
943 case PIPE_TEX_FILTER_LINEAR:
944 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
945 }
946 }
947
948 static inline unsigned r600_tex_mipfilter(unsigned filter)
949 {
950 switch (filter) {
951 case PIPE_TEX_MIPFILTER_NEAREST:
952 return V_03C000_SQ_TEX_Z_FILTER_POINT;
953 case PIPE_TEX_MIPFILTER_LINEAR:
954 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
955 default:
956 case PIPE_TEX_MIPFILTER_NONE:
957 return V_03C000_SQ_TEX_Z_FILTER_NONE;
958 }
959 }
960
961 static inline unsigned r600_tex_compare(unsigned compare)
962 {
963 switch (compare) {
964 default:
965 case PIPE_FUNC_NEVER:
966 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
967 case PIPE_FUNC_LESS:
968 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
969 case PIPE_FUNC_EQUAL:
970 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
971 case PIPE_FUNC_LEQUAL:
972 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
973 case PIPE_FUNC_GREATER:
974 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
975 case PIPE_FUNC_NOTEQUAL:
976 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
977 case PIPE_FUNC_GEQUAL:
978 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
979 case PIPE_FUNC_ALWAYS:
980 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
981 }
982 }
983
984 static INLINE u32 S_FIXED(float value, u32 frac_bits)
985 {
986 return value * (1 << frac_bits);
987 }
988
989 static struct radeon_state *r600_sampler(struct r600_context *rctx,
990 const struct pipe_sampler_state *state,
991 unsigned id)
992 {
993 struct r600_screen *rscreen = rctx->screen;
994 struct radeon_state *rstate;
995
996 rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, id);
997 if (rstate == NULL)
998 return NULL;
999 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
1000 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1001 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1002 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1003 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
1004 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
1005 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1006 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func));
1007 /* FIXME LOD it depends on texture base level ... */
1008 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
1009 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1010 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1011 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
1012 rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
1013 if (radeon_state_pm4(rstate)) {
1014 radeon_state_decref(rstate);
1015 return NULL;
1016 }
1017 return rstate;
1018 }
1019
1020 static inline unsigned r600_tex_swizzle(unsigned swizzle)
1021 {
1022 switch (swizzle) {
1023 case PIPE_SWIZZLE_RED:
1024 return V_038010_SQ_SEL_X;
1025 case PIPE_SWIZZLE_GREEN:
1026 return V_038010_SQ_SEL_Y;
1027 case PIPE_SWIZZLE_BLUE:
1028 return V_038010_SQ_SEL_Z;
1029 case PIPE_SWIZZLE_ALPHA:
1030 return V_038010_SQ_SEL_W;
1031 case PIPE_SWIZZLE_ZERO:
1032 return V_038010_SQ_SEL_0;
1033 default:
1034 case PIPE_SWIZZLE_ONE:
1035 return V_038010_SQ_SEL_1;
1036 }
1037 }
1038
1039 static inline unsigned r600_format_type(unsigned format_type)
1040 {
1041 switch (format_type) {
1042 default:
1043 case UTIL_FORMAT_TYPE_UNSIGNED:
1044 return V_038010_SQ_FORMAT_COMP_UNSIGNED;
1045 case UTIL_FORMAT_TYPE_SIGNED:
1046 return V_038010_SQ_FORMAT_COMP_SIGNED;
1047 case UTIL_FORMAT_TYPE_FIXED:
1048 return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED;
1049 }
1050 }
1051
1052 static inline unsigned r600_tex_dim(unsigned dim)
1053 {
1054 switch (dim) {
1055 default:
1056 case PIPE_TEXTURE_1D:
1057 return V_038000_SQ_TEX_DIM_1D;
1058 case PIPE_TEXTURE_2D:
1059 return V_038000_SQ_TEX_DIM_2D;
1060 case PIPE_TEXTURE_3D:
1061 return V_038000_SQ_TEX_DIM_3D;
1062 case PIPE_TEXTURE_CUBE:
1063 return V_038000_SQ_TEX_DIM_CUBEMAP;
1064 }
1065 }
1066
1067 static struct radeon_state *r600_resource(struct r600_context *rctx,
1068 const struct pipe_sampler_view *view,
1069 unsigned id)
1070 {
1071 struct r600_screen *rscreen = rctx->screen;
1072 const struct util_format_description *desc;
1073 struct r600_resource_texture *tmp;
1074 struct r600_resource *rbuffer;
1075 struct radeon_state *rstate;
1076 unsigned format;
1077
1078 if (r600_conv_pipe_format(view->texture->format, &format))
1079 return NULL;
1080 desc = util_format_description(view->texture->format);
1081 assert(desc == NULL);
1082 rstate = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, id);
1083 if (rstate == NULL) {
1084 return NULL;
1085 }
1086 tmp = (struct r600_resource_texture*)view->texture;
1087 rbuffer = &tmp->resource;
1088 rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1089 rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
1090 rstate->nbo = 2;
1091 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
1092 rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
1093 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
1094 rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
1095
1096 /* FIXME properly handle first level != 0 */
1097 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
1098 S_038000_DIM(r600_tex_dim(view->texture->target)) |
1099 S_038000_PITCH(((tmp->pitch[0] / tmp->bpt) / 8) - 1) |
1100 S_038000_TEX_WIDTH(view->texture->width0 - 1);
1101 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
1102 S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
1103 S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
1104 S_038004_DATA_FORMAT(format);
1105 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = 0;
1106 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
1107 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
1108 S_038010_FORMAT_COMP_X(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
1109 S_038010_FORMAT_COMP_Y(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
1110 S_038010_FORMAT_COMP_Z(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
1111 S_038010_FORMAT_COMP_W(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
1112 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
1113 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
1114 S_038010_REQUEST_SIZE(1) |
1115 S_038010_DST_SEL_X(r600_tex_swizzle(view->swizzle_b)) |
1116 S_038010_DST_SEL_Y(r600_tex_swizzle(view->swizzle_g)) |
1117 S_038010_DST_SEL_Z(r600_tex_swizzle(view->swizzle_r)) |
1118 S_038010_DST_SEL_W(r600_tex_swizzle(view->swizzle_a)) |
1119 S_038010_BASE_LEVEL(view->first_level);
1120 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
1121 S_038014_LAST_LEVEL(view->last_level) |
1122 S_038014_BASE_ARRAY(0) |
1123 S_038014_LAST_ARRAY(0);
1124 rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
1125 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
1126 if (radeon_state_pm4(rstate)) {
1127 radeon_state_decref(rstate);
1128 return NULL;
1129 }
1130 return rstate;
1131 }
1132
1133 static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
1134 {
1135 struct r600_screen *rscreen = rctx->screen;
1136 struct radeon_state *rstate;
1137 const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
1138 uint32_t color_control, target_mask;
1139 int i;
1140
1141 target_mask = 0;
1142 color_control = 0;
1143
1144 if (pbs->logicop_enable) {
1145 color_control |= (pbs->logicop_func) << 16;
1146 } else
1147 color_control |= (0xcc << 16);
1148
1149 target_mask |= (pbs->rt[0].colormask);
1150 for (i = 0; i < 8; i++) {
1151 if (pbs->rt[i].blend_enable) {
1152 color_control |= (1 << (8 + i));
1153 target_mask |= (pbs->rt[0].colormask << (4 * i));
1154 } else if (i == 0)
1155 target_mask |= 0xf;
1156 }
1157 rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
1158 rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = 0x0000000F;
1159 rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
1160 rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
1161 rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
1162 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
1163 rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
1164 rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
1165 rstate->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
1166 rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
1167 rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
1168 rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
1169 if (radeon_state_pm4(rstate)) {
1170 radeon_state_decref(rstate);
1171 return NULL;
1172 }
1173 return rstate;
1174 }
1175
1176 int r600_context_hw_states(struct r600_context *rctx)
1177 {
1178 unsigned i;
1179 int r;
1180
1181 /* free previous TODO determine what need to be updated, what
1182 * doesn't
1183 */
1184 //radeon_state_decref(rctx->hw_states.config);
1185 radeon_state_decref(rctx->hw_states.cb_cntl);
1186 radeon_state_decref(rctx->hw_states.db);
1187 radeon_state_decref(rctx->hw_states.rasterizer);
1188 radeon_state_decref(rctx->hw_states.scissor);
1189 radeon_state_decref(rctx->hw_states.dsa);
1190 radeon_state_decref(rctx->hw_states.blend);
1191 radeon_state_decref(rctx->hw_states.viewport);
1192 radeon_state_decref(rctx->hw_states.cb0);
1193 for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
1194 radeon_state_decref(rctx->hw_states.ps_resource[i]);
1195 rctx->hw_states.ps_resource[i] = NULL;
1196 }
1197 rctx->hw_states.ps_nresource = 0;
1198 for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
1199 radeon_state_decref(rctx->hw_states.ps_sampler[i]);
1200 rctx->hw_states.ps_sampler[i] = NULL;
1201 }
1202 rctx->hw_states.ps_nsampler = 0;
1203
1204 /* build new states */
1205 rctx->hw_states.rasterizer = r600_rasterizer(rctx);
1206 rctx->hw_states.scissor = r600_scissor(rctx);
1207 rctx->hw_states.dsa = r600_dsa(rctx);
1208 rctx->hw_states.blend = r600_blend(rctx);
1209 rctx->hw_states.viewport = r600_viewport(rctx);
1210 rctx->hw_states.cb0 = r600_cb0(rctx);
1211 rctx->hw_states.db = r600_db(rctx);
1212 rctx->hw_states.cb_cntl = r600_cb_cntl(rctx);
1213
1214 for (i = 0; i < rctx->ps_nsampler; i++) {
1215 if (rctx->ps_sampler[i]) {
1216 rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
1217 &rctx->ps_sampler[i]->state.sampler,
1218 R600_PS_SAMPLER + i);
1219 }
1220 }
1221 rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
1222 for (i = 0; i < rctx->ps_nsampler_view; i++) {
1223 if (rctx->ps_sampler_view[i]) {
1224 rctx->hw_states.ps_resource[i] = r600_resource(rctx,
1225 &rctx->ps_sampler_view[i]->state.sampler_view,
1226 R600_PS_RESOURCE + i);
1227 }
1228 }
1229 rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
1230
1231 /* bind states */
1232 r = radeon_draw_set(rctx->draw, rctx->hw_states.db);
1233 if (r)
1234 return r;
1235 r = radeon_draw_set(rctx->draw, rctx->hw_states.rasterizer);
1236 if (r)
1237 return r;
1238 r = radeon_draw_set(rctx->draw, rctx->hw_states.scissor);
1239 if (r)
1240 return r;
1241 r = radeon_draw_set(rctx->draw, rctx->hw_states.dsa);
1242 if (r)
1243 return r;
1244 r = radeon_draw_set(rctx->draw, rctx->hw_states.blend);
1245 if (r)
1246 return r;
1247 r = radeon_draw_set(rctx->draw, rctx->hw_states.viewport);
1248 if (r)
1249 return r;
1250 r = radeon_draw_set(rctx->draw, rctx->hw_states.cb0);
1251 if (r)
1252 return r;
1253 r = radeon_draw_set(rctx->draw, rctx->hw_states.config);
1254 if (r)
1255 return r;
1256 r = radeon_draw_set(rctx->draw, rctx->hw_states.cb_cntl);
1257 if (r)
1258 return r;
1259 for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
1260 if (rctx->hw_states.ps_resource[i]) {
1261 r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_resource[i]);
1262 if (r)
1263 return r;
1264 }
1265 }
1266 for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
1267 if (rctx->hw_states.ps_sampler[i]) {
1268 r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_sampler[i]);
1269 if (r)
1270 return r;
1271 }
1272 }
1273 return 0;
1274 }