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r600g: move shader structures into r600_shader.h
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 return V_038000_SQ_TEX_DIM_CUBEMAP;
122 }
123 }
124
125 static uint32_t r600_translate_dbformat(enum pipe_format format)
126 {
127 switch (format) {
128 case PIPE_FORMAT_Z16_UNORM:
129 return V_028010_DEPTH_16;
130 case PIPE_FORMAT_Z24X8_UNORM:
131 return V_028010_DEPTH_X8_24;
132 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
133 return V_028010_DEPTH_8_24;
134 case PIPE_FORMAT_Z32_FLOAT:
135 return V_028010_DEPTH_32_FLOAT;
136 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
137 return V_028010_DEPTH_X24_8_32_FLOAT;
138 default:
139 return ~0U;
140 }
141 }
142
143 static uint32_t r600_translate_colorswap(enum pipe_format format)
144 {
145 switch (format) {
146 /* 8-bit buffers. */
147 case PIPE_FORMAT_A8_UNORM:
148 case PIPE_FORMAT_A8_SNORM:
149 case PIPE_FORMAT_A8_UINT:
150 case PIPE_FORMAT_A8_SINT:
151 case PIPE_FORMAT_A16_UNORM:
152 case PIPE_FORMAT_A16_SNORM:
153 case PIPE_FORMAT_A16_UINT:
154 case PIPE_FORMAT_A16_SINT:
155 case PIPE_FORMAT_A16_FLOAT:
156 case PIPE_FORMAT_A32_UINT:
157 case PIPE_FORMAT_A32_SINT:
158 case PIPE_FORMAT_A32_FLOAT:
159 case PIPE_FORMAT_R4A4_UNORM:
160 return V_0280A0_SWAP_ALT_REV;
161 case PIPE_FORMAT_I8_UNORM:
162 case PIPE_FORMAT_I8_SNORM:
163 case PIPE_FORMAT_I8_UINT:
164 case PIPE_FORMAT_I8_SINT:
165 case PIPE_FORMAT_L8_UNORM:
166 case PIPE_FORMAT_L8_SNORM:
167 case PIPE_FORMAT_L8_UINT:
168 case PIPE_FORMAT_L8_SINT:
169 case PIPE_FORMAT_L8_SRGB:
170 case PIPE_FORMAT_L16_UNORM:
171 case PIPE_FORMAT_L16_SNORM:
172 case PIPE_FORMAT_L16_UINT:
173 case PIPE_FORMAT_L16_SINT:
174 case PIPE_FORMAT_L16_FLOAT:
175 case PIPE_FORMAT_L32_UINT:
176 case PIPE_FORMAT_L32_SINT:
177 case PIPE_FORMAT_L32_FLOAT:
178 case PIPE_FORMAT_I16_UNORM:
179 case PIPE_FORMAT_I16_SNORM:
180 case PIPE_FORMAT_I16_UINT:
181 case PIPE_FORMAT_I16_SINT:
182 case PIPE_FORMAT_I16_FLOAT:
183 case PIPE_FORMAT_I32_UINT:
184 case PIPE_FORMAT_I32_SINT:
185 case PIPE_FORMAT_I32_FLOAT:
186 case PIPE_FORMAT_R8_UNORM:
187 case PIPE_FORMAT_R8_SNORM:
188 case PIPE_FORMAT_R8_UINT:
189 case PIPE_FORMAT_R8_SINT:
190 return V_0280A0_SWAP_STD;
191
192 case PIPE_FORMAT_L4A4_UNORM:
193 case PIPE_FORMAT_A4R4_UNORM:
194 return V_0280A0_SWAP_ALT;
195
196 /* 16-bit buffers. */
197 case PIPE_FORMAT_B5G6R5_UNORM:
198 return V_0280A0_SWAP_STD_REV;
199
200 case PIPE_FORMAT_B5G5R5A1_UNORM:
201 case PIPE_FORMAT_B5G5R5X1_UNORM:
202 return V_0280A0_SWAP_ALT;
203
204 case PIPE_FORMAT_B4G4R4A4_UNORM:
205 case PIPE_FORMAT_B4G4R4X4_UNORM:
206 return V_0280A0_SWAP_ALT;
207
208 case PIPE_FORMAT_Z16_UNORM:
209 return V_0280A0_SWAP_STD;
210
211 case PIPE_FORMAT_L8A8_UNORM:
212 case PIPE_FORMAT_L8A8_SNORM:
213 case PIPE_FORMAT_L8A8_UINT:
214 case PIPE_FORMAT_L8A8_SINT:
215 case PIPE_FORMAT_L8A8_SRGB:
216 case PIPE_FORMAT_L16A16_UNORM:
217 case PIPE_FORMAT_L16A16_SNORM:
218 case PIPE_FORMAT_L16A16_UINT:
219 case PIPE_FORMAT_L16A16_SINT:
220 case PIPE_FORMAT_L16A16_FLOAT:
221 case PIPE_FORMAT_L32A32_UINT:
222 case PIPE_FORMAT_L32A32_SINT:
223 case PIPE_FORMAT_L32A32_FLOAT:
224 return V_0280A0_SWAP_ALT;
225 case PIPE_FORMAT_R8G8_UNORM:
226 case PIPE_FORMAT_R8G8_SNORM:
227 case PIPE_FORMAT_R8G8_UINT:
228 case PIPE_FORMAT_R8G8_SINT:
229 return V_0280A0_SWAP_STD;
230
231 case PIPE_FORMAT_R16_UNORM:
232 case PIPE_FORMAT_R16_SNORM:
233 case PIPE_FORMAT_R16_UINT:
234 case PIPE_FORMAT_R16_SINT:
235 case PIPE_FORMAT_R16_FLOAT:
236 return V_0280A0_SWAP_STD;
237
238 /* 32-bit buffers. */
239
240 case PIPE_FORMAT_A8B8G8R8_SRGB:
241 return V_0280A0_SWAP_STD_REV;
242 case PIPE_FORMAT_B8G8R8A8_SRGB:
243 return V_0280A0_SWAP_ALT;
244
245 case PIPE_FORMAT_B8G8R8A8_UNORM:
246 case PIPE_FORMAT_B8G8R8X8_UNORM:
247 return V_0280A0_SWAP_ALT;
248
249 case PIPE_FORMAT_A8R8G8B8_UNORM:
250 case PIPE_FORMAT_X8R8G8B8_UNORM:
251 return V_0280A0_SWAP_ALT_REV;
252 case PIPE_FORMAT_R8G8B8A8_SNORM:
253 case PIPE_FORMAT_R8G8B8A8_UNORM:
254 case PIPE_FORMAT_R8G8B8X8_UNORM:
255 case PIPE_FORMAT_R8G8B8A8_SINT:
256 case PIPE_FORMAT_R8G8B8A8_UINT:
257 return V_0280A0_SWAP_STD;
258
259 case PIPE_FORMAT_A8B8G8R8_UNORM:
260 case PIPE_FORMAT_X8B8G8R8_UNORM:
261 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
262 return V_0280A0_SWAP_STD_REV;
263
264 case PIPE_FORMAT_Z24X8_UNORM:
265 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
266 return V_0280A0_SWAP_STD;
267
268 case PIPE_FORMAT_X8Z24_UNORM:
269 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
270 return V_0280A0_SWAP_STD;
271
272 case PIPE_FORMAT_R10G10B10A2_UNORM:
273 case PIPE_FORMAT_R10G10B10X2_SNORM:
274 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
275 return V_0280A0_SWAP_STD;
276
277 case PIPE_FORMAT_B10G10R10A2_UNORM:
278 case PIPE_FORMAT_B10G10R10A2_UINT:
279 return V_0280A0_SWAP_ALT;
280
281 case PIPE_FORMAT_R11G11B10_FLOAT:
282 case PIPE_FORMAT_R16G16_UNORM:
283 case PIPE_FORMAT_R16G16_SNORM:
284 case PIPE_FORMAT_R16G16_FLOAT:
285 case PIPE_FORMAT_R16G16_UINT:
286 case PIPE_FORMAT_R16G16_SINT:
287 case PIPE_FORMAT_R32_UINT:
288 case PIPE_FORMAT_R32_SINT:
289 case PIPE_FORMAT_R32_FLOAT:
290 case PIPE_FORMAT_Z32_FLOAT:
291 return V_0280A0_SWAP_STD;
292
293 /* 64-bit buffers. */
294 case PIPE_FORMAT_R32G32_FLOAT:
295 case PIPE_FORMAT_R32G32_UINT:
296 case PIPE_FORMAT_R32G32_SINT:
297 case PIPE_FORMAT_R16G16B16A16_UNORM:
298 case PIPE_FORMAT_R16G16B16A16_SNORM:
299 case PIPE_FORMAT_R16G16B16A16_UINT:
300 case PIPE_FORMAT_R16G16B16A16_SINT:
301 case PIPE_FORMAT_R16G16B16A16_FLOAT:
302 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
303
304 /* 128-bit buffers. */
305 case PIPE_FORMAT_R32G32B32A32_FLOAT:
306 case PIPE_FORMAT_R32G32B32A32_SNORM:
307 case PIPE_FORMAT_R32G32B32A32_UNORM:
308 case PIPE_FORMAT_R32G32B32A32_SINT:
309 case PIPE_FORMAT_R32G32B32A32_UINT:
310 return V_0280A0_SWAP_STD;
311 default:
312 R600_ERR("unsupported colorswap format %d\n", format);
313 return ~0U;
314 }
315 return ~0U;
316 }
317
318 static uint32_t r600_translate_colorformat(enum pipe_format format)
319 {
320 switch (format) {
321 case PIPE_FORMAT_L4A4_UNORM:
322 case PIPE_FORMAT_R4A4_UNORM:
323 case PIPE_FORMAT_A4R4_UNORM:
324 return V_0280A0_COLOR_4_4;
325
326 /* 8-bit buffers. */
327 case PIPE_FORMAT_A8_UNORM:
328 case PIPE_FORMAT_A8_SNORM:
329 case PIPE_FORMAT_A8_UINT:
330 case PIPE_FORMAT_A8_SINT:
331 case PIPE_FORMAT_I8_UNORM:
332 case PIPE_FORMAT_I8_SNORM:
333 case PIPE_FORMAT_I8_UINT:
334 case PIPE_FORMAT_I8_SINT:
335 case PIPE_FORMAT_L8_UNORM:
336 case PIPE_FORMAT_L8_SNORM:
337 case PIPE_FORMAT_L8_UINT:
338 case PIPE_FORMAT_L8_SINT:
339 case PIPE_FORMAT_L8_SRGB:
340 case PIPE_FORMAT_R8_UNORM:
341 case PIPE_FORMAT_R8_SNORM:
342 case PIPE_FORMAT_R8_UINT:
343 case PIPE_FORMAT_R8_SINT:
344 return V_0280A0_COLOR_8;
345
346 /* 16-bit buffers. */
347 case PIPE_FORMAT_B5G6R5_UNORM:
348 return V_0280A0_COLOR_5_6_5;
349
350 case PIPE_FORMAT_B5G5R5A1_UNORM:
351 case PIPE_FORMAT_B5G5R5X1_UNORM:
352 return V_0280A0_COLOR_1_5_5_5;
353
354 case PIPE_FORMAT_B4G4R4A4_UNORM:
355 case PIPE_FORMAT_B4G4R4X4_UNORM:
356 return V_0280A0_COLOR_4_4_4_4;
357
358 case PIPE_FORMAT_Z16_UNORM:
359 return V_0280A0_COLOR_16;
360
361 case PIPE_FORMAT_L8A8_UNORM:
362 case PIPE_FORMAT_L8A8_SNORM:
363 case PIPE_FORMAT_L8A8_UINT:
364 case PIPE_FORMAT_L8A8_SINT:
365 case PIPE_FORMAT_L8A8_SRGB:
366 case PIPE_FORMAT_R8G8_UNORM:
367 case PIPE_FORMAT_R8G8_SNORM:
368 case PIPE_FORMAT_R8G8_UINT:
369 case PIPE_FORMAT_R8G8_SINT:
370 return V_0280A0_COLOR_8_8;
371
372 case PIPE_FORMAT_R16_UNORM:
373 case PIPE_FORMAT_R16_SNORM:
374 case PIPE_FORMAT_R16_UINT:
375 case PIPE_FORMAT_R16_SINT:
376 case PIPE_FORMAT_A16_UNORM:
377 case PIPE_FORMAT_A16_SNORM:
378 case PIPE_FORMAT_A16_UINT:
379 case PIPE_FORMAT_A16_SINT:
380 case PIPE_FORMAT_L16_UNORM:
381 case PIPE_FORMAT_L16_SNORM:
382 case PIPE_FORMAT_L16_UINT:
383 case PIPE_FORMAT_L16_SINT:
384 case PIPE_FORMAT_I16_UNORM:
385 case PIPE_FORMAT_I16_SNORM:
386 case PIPE_FORMAT_I16_UINT:
387 case PIPE_FORMAT_I16_SINT:
388 return V_0280A0_COLOR_16;
389
390 case PIPE_FORMAT_R16_FLOAT:
391 case PIPE_FORMAT_A16_FLOAT:
392 case PIPE_FORMAT_L16_FLOAT:
393 case PIPE_FORMAT_I16_FLOAT:
394 return V_0280A0_COLOR_16_FLOAT;
395
396 /* 32-bit buffers. */
397 case PIPE_FORMAT_A8B8G8R8_SRGB:
398 case PIPE_FORMAT_A8B8G8R8_UNORM:
399 case PIPE_FORMAT_A8R8G8B8_UNORM:
400 case PIPE_FORMAT_B8G8R8A8_SRGB:
401 case PIPE_FORMAT_B8G8R8A8_UNORM:
402 case PIPE_FORMAT_B8G8R8X8_UNORM:
403 case PIPE_FORMAT_R8G8B8A8_SNORM:
404 case PIPE_FORMAT_R8G8B8A8_UNORM:
405 case PIPE_FORMAT_R8G8B8X8_UNORM:
406 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
407 case PIPE_FORMAT_X8B8G8R8_UNORM:
408 case PIPE_FORMAT_X8R8G8B8_UNORM:
409 case PIPE_FORMAT_R8G8B8A8_SINT:
410 case PIPE_FORMAT_R8G8B8A8_UINT:
411 return V_0280A0_COLOR_8_8_8_8;
412
413 case PIPE_FORMAT_R10G10B10A2_UNORM:
414 case PIPE_FORMAT_R10G10B10X2_SNORM:
415 case PIPE_FORMAT_B10G10R10A2_UNORM:
416 case PIPE_FORMAT_B10G10R10A2_UINT:
417 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
418 return V_0280A0_COLOR_2_10_10_10;
419
420 case PIPE_FORMAT_Z24X8_UNORM:
421 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
422 return V_0280A0_COLOR_8_24;
423
424 case PIPE_FORMAT_X8Z24_UNORM:
425 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
426 return V_0280A0_COLOR_24_8;
427
428 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
429 return V_0280A0_COLOR_X24_8_32_FLOAT;
430
431 case PIPE_FORMAT_R32_UINT:
432 case PIPE_FORMAT_R32_SINT:
433 case PIPE_FORMAT_A32_UINT:
434 case PIPE_FORMAT_A32_SINT:
435 case PIPE_FORMAT_L32_UINT:
436 case PIPE_FORMAT_L32_SINT:
437 case PIPE_FORMAT_I32_UINT:
438 case PIPE_FORMAT_I32_SINT:
439 return V_0280A0_COLOR_32;
440
441 case PIPE_FORMAT_R32_FLOAT:
442 case PIPE_FORMAT_A32_FLOAT:
443 case PIPE_FORMAT_L32_FLOAT:
444 case PIPE_FORMAT_I32_FLOAT:
445 case PIPE_FORMAT_Z32_FLOAT:
446 return V_0280A0_COLOR_32_FLOAT;
447
448 case PIPE_FORMAT_R16G16_FLOAT:
449 case PIPE_FORMAT_L16A16_FLOAT:
450 return V_0280A0_COLOR_16_16_FLOAT;
451
452 case PIPE_FORMAT_R16G16_UNORM:
453 case PIPE_FORMAT_R16G16_SNORM:
454 case PIPE_FORMAT_R16G16_UINT:
455 case PIPE_FORMAT_R16G16_SINT:
456 case PIPE_FORMAT_L16A16_UNORM:
457 case PIPE_FORMAT_L16A16_SNORM:
458 case PIPE_FORMAT_L16A16_UINT:
459 case PIPE_FORMAT_L16A16_SINT:
460 return V_0280A0_COLOR_16_16;
461
462 case PIPE_FORMAT_R11G11B10_FLOAT:
463 return V_0280A0_COLOR_10_11_11_FLOAT;
464
465 /* 64-bit buffers. */
466 case PIPE_FORMAT_R16G16B16A16_UINT:
467 case PIPE_FORMAT_R16G16B16A16_SINT:
468 case PIPE_FORMAT_R16G16B16A16_UNORM:
469 case PIPE_FORMAT_R16G16B16A16_SNORM:
470 return V_0280A0_COLOR_16_16_16_16;
471
472 case PIPE_FORMAT_R16G16B16A16_FLOAT:
473 return V_0280A0_COLOR_16_16_16_16_FLOAT;
474
475 case PIPE_FORMAT_R32G32_FLOAT:
476 case PIPE_FORMAT_L32A32_FLOAT:
477 return V_0280A0_COLOR_32_32_FLOAT;
478
479 case PIPE_FORMAT_R32G32_SINT:
480 case PIPE_FORMAT_R32G32_UINT:
481 case PIPE_FORMAT_L32A32_UINT:
482 case PIPE_FORMAT_L32A32_SINT:
483 return V_0280A0_COLOR_32_32;
484
485 /* 128-bit buffers. */
486 case PIPE_FORMAT_R32G32B32A32_FLOAT:
487 return V_0280A0_COLOR_32_32_32_32_FLOAT;
488 case PIPE_FORMAT_R32G32B32A32_SNORM:
489 case PIPE_FORMAT_R32G32B32A32_UNORM:
490 case PIPE_FORMAT_R32G32B32A32_SINT:
491 case PIPE_FORMAT_R32G32B32A32_UINT:
492 return V_0280A0_COLOR_32_32_32_32;
493
494 /* YUV buffers. */
495 case PIPE_FORMAT_UYVY:
496 case PIPE_FORMAT_YUYV:
497 default:
498 return ~0U; /* Unsupported. */
499 }
500 }
501
502 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
503 {
504 if (R600_BIG_ENDIAN) {
505 switch(colorformat) {
506 case V_0280A0_COLOR_4_4:
507 return ENDIAN_NONE;
508
509 /* 8-bit buffers. */
510 case V_0280A0_COLOR_8:
511 return ENDIAN_NONE;
512
513 /* 16-bit buffers. */
514 case V_0280A0_COLOR_5_6_5:
515 case V_0280A0_COLOR_1_5_5_5:
516 case V_0280A0_COLOR_4_4_4_4:
517 case V_0280A0_COLOR_16:
518 case V_0280A0_COLOR_8_8:
519 return ENDIAN_8IN16;
520
521 /* 32-bit buffers. */
522 case V_0280A0_COLOR_8_8_8_8:
523 case V_0280A0_COLOR_2_10_10_10:
524 case V_0280A0_COLOR_8_24:
525 case V_0280A0_COLOR_24_8:
526 case V_0280A0_COLOR_32_FLOAT:
527 case V_0280A0_COLOR_16_16_FLOAT:
528 case V_0280A0_COLOR_16_16:
529 return ENDIAN_8IN32;
530
531 /* 64-bit buffers. */
532 case V_0280A0_COLOR_16_16_16_16:
533 case V_0280A0_COLOR_16_16_16_16_FLOAT:
534 return ENDIAN_8IN16;
535
536 case V_0280A0_COLOR_32_32_FLOAT:
537 case V_0280A0_COLOR_32_32:
538 case V_0280A0_COLOR_X24_8_32_FLOAT:
539 return ENDIAN_8IN32;
540
541 /* 128-bit buffers. */
542 case V_0280A0_COLOR_32_32_32_FLOAT:
543 case V_0280A0_COLOR_32_32_32_32_FLOAT:
544 case V_0280A0_COLOR_32_32_32_32:
545 return ENDIAN_8IN32;
546 default:
547 return ENDIAN_NONE; /* Unsupported. */
548 }
549 } else {
550 return ENDIAN_NONE;
551 }
552 }
553
554 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
555 {
556 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
557 }
558
559 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
560 {
561 return r600_translate_colorformat(format) != ~0U &&
562 r600_translate_colorswap(format) != ~0U;
563 }
564
565 static bool r600_is_zs_format_supported(enum pipe_format format)
566 {
567 return r600_translate_dbformat(format) != ~0U;
568 }
569
570 boolean r600_is_format_supported(struct pipe_screen *screen,
571 enum pipe_format format,
572 enum pipe_texture_target target,
573 unsigned sample_count,
574 unsigned usage)
575 {
576 struct r600_screen *rscreen = (struct r600_screen*)screen;
577 unsigned retval = 0;
578
579 if (target >= PIPE_MAX_TEXTURE_TYPES) {
580 R600_ERR("r600: unsupported texture type %d\n", target);
581 return FALSE;
582 }
583
584 if (!util_format_is_supported(format, usage))
585 return FALSE;
586
587 if (sample_count > 1) {
588 if (rscreen->info.drm_minor < 22)
589 return FALSE;
590
591 /* R11G11B10 is broken on R6xx. */
592 if (rscreen->chip_class == R600 &&
593 format == PIPE_FORMAT_R11G11B10_FLOAT)
594 return FALSE;
595
596 /* MSAA integer colorbuffers hang. */
597 if (util_format_is_pure_integer(format) &&
598 !util_format_is_depth_or_stencil(format))
599 return FALSE;
600
601 switch (sample_count) {
602 case 2:
603 case 4:
604 case 8:
605 break;
606 default:
607 return FALSE;
608 }
609 }
610
611 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
612 r600_is_sampler_format_supported(screen, format)) {
613 retval |= PIPE_BIND_SAMPLER_VIEW;
614 }
615
616 if ((usage & (PIPE_BIND_RENDER_TARGET |
617 PIPE_BIND_DISPLAY_TARGET |
618 PIPE_BIND_SCANOUT |
619 PIPE_BIND_SHARED)) &&
620 r600_is_colorbuffer_format_supported(format)) {
621 retval |= usage &
622 (PIPE_BIND_RENDER_TARGET |
623 PIPE_BIND_DISPLAY_TARGET |
624 PIPE_BIND_SCANOUT |
625 PIPE_BIND_SHARED);
626 }
627
628 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
629 r600_is_zs_format_supported(format)) {
630 retval |= PIPE_BIND_DEPTH_STENCIL;
631 }
632
633 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
634 r600_is_vertex_format_supported(format)) {
635 retval |= PIPE_BIND_VERTEX_BUFFER;
636 }
637
638 if (usage & PIPE_BIND_TRANSFER_READ)
639 retval |= PIPE_BIND_TRANSFER_READ;
640 if (usage & PIPE_BIND_TRANSFER_WRITE)
641 retval |= PIPE_BIND_TRANSFER_WRITE;
642
643 return retval == usage;
644 }
645
646 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
647 {
648 struct radeon_winsys_cs *cs = rctx->cs;
649 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
650 float offset_units = state->offset_units;
651 float offset_scale = state->offset_scale;
652
653 switch (state->zs_format) {
654 case PIPE_FORMAT_Z24X8_UNORM:
655 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
656 offset_units *= 2.0f;
657 break;
658 case PIPE_FORMAT_Z16_UNORM:
659 offset_units *= 4.0f;
660 break;
661 default:;
662 }
663
664 r600_write_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
665 r600_write_value(cs, fui(offset_scale));
666 r600_write_value(cs, fui(offset_units));
667 r600_write_value(cs, fui(offset_scale));
668 r600_write_value(cs, fui(offset_units));
669 }
670
671 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
672 {
673 int j = state->independent_blend_enable ? i : 0;
674
675 unsigned eqRGB = state->rt[j].rgb_func;
676 unsigned srcRGB = state->rt[j].rgb_src_factor;
677 unsigned dstRGB = state->rt[j].rgb_dst_factor;
678
679 unsigned eqA = state->rt[j].alpha_func;
680 unsigned srcA = state->rt[j].alpha_src_factor;
681 unsigned dstA = state->rt[j].alpha_dst_factor;
682 uint32_t bc = 0;
683
684 if (!state->rt[j].blend_enable)
685 return 0;
686
687 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
688 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
689 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
690
691 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
692 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
693 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
694 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
695 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
696 }
697 return bc;
698 }
699
700 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
701 const struct pipe_blend_state *state,
702 int mode)
703 {
704 struct r600_context *rctx = (struct r600_context *)ctx;
705 uint32_t color_control = 0, target_mask = 0;
706 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
707
708 if (!blend) {
709 return NULL;
710 }
711
712 r600_init_command_buffer(&blend->buffer, 20);
713 r600_init_command_buffer(&blend->buffer_no_blend, 20);
714
715 /* R600 does not support per-MRT blends */
716 if (rctx->family > CHIP_R600)
717 color_control |= S_028808_PER_MRT_BLEND(1);
718
719 if (state->logicop_enable) {
720 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
721 } else {
722 color_control |= (0xcc << 16);
723 }
724 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
725 if (state->independent_blend_enable) {
726 for (int i = 0; i < 8; i++) {
727 if (state->rt[i].blend_enable) {
728 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
729 }
730 target_mask |= (state->rt[i].colormask << (4 * i));
731 }
732 } else {
733 for (int i = 0; i < 8; i++) {
734 if (state->rt[0].blend_enable) {
735 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
736 }
737 target_mask |= (state->rt[0].colormask << (4 * i));
738 }
739 }
740
741 if (target_mask)
742 color_control |= S_028808_SPECIAL_OP(mode);
743 else
744 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
745
746 /* only MRT0 has dual src blend */
747 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
748 blend->cb_target_mask = target_mask;
749 blend->cb_color_control = color_control;
750 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
751 blend->alpha_to_one = state->alpha_to_one;
752
753 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
754 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
755 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
756 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
757 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
758 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
759
760 /* Copy over the registers set so far into buffer_no_blend. */
761 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
762 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
763
764 /* Only add blend registers if blending is enabled. */
765 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
766 return blend;
767 }
768
769 /* The first R600 does not support per-MRT blends */
770 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
771 r600_get_blend_control(state, 0));
772
773 if (rctx->family > CHIP_R600) {
774 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
775 for (int i = 0; i < 8; i++) {
776 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
777 }
778 }
779 return blend;
780 }
781
782 static void *r600_create_blend_state(struct pipe_context *ctx,
783 const struct pipe_blend_state *state)
784 {
785 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
786 }
787
788 static void *r600_create_dsa_state(struct pipe_context *ctx,
789 const struct pipe_depth_stencil_alpha_state *state)
790 {
791 unsigned db_depth_control, alpha_test_control, alpha_ref;
792 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
793
794 if (dsa == NULL) {
795 return NULL;
796 }
797
798 r600_init_command_buffer(&dsa->buffer, 3);
799
800 dsa->valuemask[0] = state->stencil[0].valuemask;
801 dsa->valuemask[1] = state->stencil[1].valuemask;
802 dsa->writemask[0] = state->stencil[0].writemask;
803 dsa->writemask[1] = state->stencil[1].writemask;
804
805 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
806 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
807 S_028800_ZFUNC(state->depth.func);
808
809 /* stencil */
810 if (state->stencil[0].enabled) {
811 db_depth_control |= S_028800_STENCIL_ENABLE(1);
812 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
813 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
814 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
815 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
816
817 if (state->stencil[1].enabled) {
818 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
819 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
820 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
821 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
822 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
823 }
824 }
825
826 /* alpha */
827 alpha_test_control = 0;
828 alpha_ref = 0;
829 if (state->alpha.enabled) {
830 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
831 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
832 alpha_ref = fui(state->alpha.ref_value);
833 }
834 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
835 dsa->alpha_ref = alpha_ref;
836
837 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
838 return dsa;
839 }
840
841 static void *r600_create_rs_state(struct pipe_context *ctx,
842 const struct pipe_rasterizer_state *state)
843 {
844 struct r600_context *rctx = (struct r600_context *)ctx;
845 unsigned tmp, sc_mode_cntl, spi_interp;
846 float psize_min, psize_max;
847 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
848
849 if (rs == NULL) {
850 return NULL;
851 }
852
853 r600_init_command_buffer(&rs->buffer, 30);
854
855 rs->flatshade = state->flatshade;
856 rs->sprite_coord_enable = state->sprite_coord_enable;
857 rs->two_side = state->light_twoside;
858 rs->clip_plane_enable = state->clip_plane_enable;
859 rs->pa_sc_line_stipple = state->line_stipple_enable ?
860 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
861 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
862 rs->pa_cl_clip_cntl =
863 S_028810_PS_UCP_MODE(3) |
864 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
865 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
866 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
867 rs->multisample_enable = state->multisample;
868
869 /* offset */
870 rs->offset_units = state->offset_units;
871 rs->offset_scale = state->offset_scale * 12.0f;
872 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
873
874 if (state->point_size_per_vertex) {
875 psize_min = util_get_min_point_size(state);
876 psize_max = 8192;
877 } else {
878 /* Force the point size to be as if the vertex output was disabled. */
879 psize_min = state->point_size;
880 psize_max = state->point_size;
881 }
882
883 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
884 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
885 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
886 if (rctx->chip_class >= R700) {
887 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
888 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
889 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
890 } else {
891 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
892 rs->scissor_enable = state->scissor;
893 }
894
895 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
896 if (state->sprite_coord_enable) {
897 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
898 S_0286D4_PNT_SPRITE_OVRD_X(2) |
899 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
900 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
901 S_0286D4_PNT_SPRITE_OVRD_W(1);
902 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
903 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
904 }
905 }
906
907 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
908 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
909 tmp = r600_pack_float_12p4(state->point_size/2);
910 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
911 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
912 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
913 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
914 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
915 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
916 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
917
918 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
919 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
920 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
921 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
922 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
923 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
924 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
925 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
926 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
927 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
928 S_028814_FACE(!state->front_ccw) |
929 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
930 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
931 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
932 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
933 state->fill_back != PIPE_POLYGON_MODE_FILL) |
934 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
935 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
936 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
937 return rs;
938 }
939
940 static void *r600_create_sampler_state(struct pipe_context *ctx,
941 const struct pipe_sampler_state *state)
942 {
943 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
944 union util_color uc;
945 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
946
947 if (ss == NULL) {
948 return NULL;
949 }
950
951 ss->seamless_cube_map = state->seamless_cube_map;
952 ss->border_color_use = false;
953 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
954 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
955 ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
956 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
957 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
958 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
959 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
960 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
961 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
962 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
963 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
964 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
965 ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
966 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
967 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
968 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
969 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
970 if (uc.ui) {
971 ss->border_color_use = true;
972 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
973 ss->border_color[0] = fui(state->border_color.f[0]);
974 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
975 ss->border_color[1] = fui(state->border_color.f[1]);
976 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
977 ss->border_color[2] = fui(state->border_color.f[2]);
978 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
979 ss->border_color[3] = fui(state->border_color.f[3]);
980 }
981 return ss;
982 }
983
984 struct pipe_sampler_view *
985 r600_create_sampler_view_custom(struct pipe_context *ctx,
986 struct pipe_resource *texture,
987 const struct pipe_sampler_view *state,
988 unsigned width_first_level, unsigned height_first_level)
989 {
990 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
991 struct r600_texture *tmp = (struct r600_texture*)texture;
992 unsigned format, endian;
993 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
994 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
995 unsigned width, height, depth, offset_level, last_level;
996
997 if (view == NULL)
998 return NULL;
999
1000 /* initialize base object */
1001 view->base = *state;
1002 view->base.texture = NULL;
1003 pipe_reference(NULL, &texture->reference);
1004 view->base.texture = texture;
1005 view->base.reference.count = 1;
1006 view->base.context = ctx;
1007
1008 swizzle[0] = state->swizzle_r;
1009 swizzle[1] = state->swizzle_g;
1010 swizzle[2] = state->swizzle_b;
1011 swizzle[3] = state->swizzle_a;
1012
1013 format = r600_translate_texformat(ctx->screen, state->format,
1014 swizzle,
1015 &word4, &yuv_format);
1016 assert(format != ~0);
1017 if (format == ~0) {
1018 FREE(view);
1019 return NULL;
1020 }
1021
1022 if (tmp->is_depth && !tmp->is_flushing_texture) {
1023 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1024 FREE(view);
1025 return NULL;
1026 }
1027 tmp = tmp->flushed_depth_texture;
1028 }
1029
1030 endian = r600_colorformat_endian_swap(format);
1031
1032 offset_level = state->u.tex.first_level;
1033 last_level = state->u.tex.last_level - offset_level;
1034 width = width_first_level;
1035 height = height_first_level;
1036 depth = tmp->surface.level[offset_level].npix_z;
1037 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1038 tile_type = tmp->tile_type;
1039
1040 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1041 height = 1;
1042 depth = texture->array_size;
1043 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1044 depth = texture->array_size;
1045 }
1046 switch (tmp->surface.level[offset_level].mode) {
1047 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1048 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1049 break;
1050 case RADEON_SURF_MODE_1D:
1051 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1052 break;
1053 case RADEON_SURF_MODE_2D:
1054 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1055 break;
1056 case RADEON_SURF_MODE_LINEAR:
1057 default:
1058 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1059 break;
1060 }
1061
1062 view->tex_resource = &tmp->resource;
1063 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1064 S_038000_TILE_MODE(array_mode) |
1065 S_038000_TILE_TYPE(tile_type) |
1066 S_038000_PITCH((pitch / 8) - 1) |
1067 S_038000_TEX_WIDTH(width - 1));
1068 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
1069 S_038004_TEX_DEPTH(depth - 1) |
1070 S_038004_DATA_FORMAT(format));
1071 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
1072 if (offset_level >= tmp->surface.last_level) {
1073 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
1074 } else {
1075 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1076 }
1077 view->tex_resource_words[4] = (word4 |
1078 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1079 S_038010_REQUEST_SIZE(1) |
1080 S_038010_ENDIAN_SWAP(endian) |
1081 S_038010_BASE_LEVEL(0));
1082 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1083 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1084 if (texture->nr_samples > 1) {
1085 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1086 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
1087 } else {
1088 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
1089 }
1090 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1091 S_038018_MAX_ANISO(4 /* max 16 samples */));
1092 return &view->base;
1093 }
1094
1095 static struct pipe_sampler_view *
1096 r600_create_sampler_view(struct pipe_context *ctx,
1097 struct pipe_resource *tex,
1098 const struct pipe_sampler_view *state)
1099 {
1100 struct r600_texture *rtex = (struct r600_texture*)tex;
1101
1102 return r600_create_sampler_view_custom(ctx, tex, state,
1103 rtex->surface.level[state->u.tex.first_level].npix_x,
1104 rtex->surface.level[state->u.tex.first_level].npix_y);
1105 }
1106
1107 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1108 {
1109 struct radeon_winsys_cs *cs = rctx->cs;
1110 struct pipe_clip_state *state = &rctx->clip_state.state;
1111
1112 r600_write_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
1113 r600_write_array(cs, 6*4, (unsigned*)state);
1114 }
1115
1116 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1117 const struct pipe_poly_stipple *state)
1118 {
1119 }
1120
1121 static void r600_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
1122 {
1123 struct radeon_winsys_cs *cs = rctx->cs;
1124 struct pipe_scissor_state *state = &rctx->scissor.scissor;
1125
1126 if (rctx->chip_class != R600 || rctx->scissor.enable) {
1127 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1128 r600_write_value(cs, S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) |
1129 S_028240_WINDOW_OFFSET_DISABLE(1));
1130 r600_write_value(cs, S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy));
1131 } else {
1132 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1133 r600_write_value(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1134 S_028240_WINDOW_OFFSET_DISABLE(1));
1135 r600_write_value(cs, S_028244_BR_X(8192) | S_028244_BR_Y(8192));
1136 }
1137 }
1138
1139 static void r600_set_scissor_state(struct pipe_context *ctx,
1140 const struct pipe_scissor_state *state)
1141 {
1142 struct r600_context *rctx = (struct r600_context *)ctx;
1143
1144 rctx->scissor.scissor = *state;
1145
1146 if (rctx->chip_class == R600 && !rctx->scissor.enable)
1147 return;
1148
1149 rctx->scissor.atom.dirty = true;
1150 }
1151
1152 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
1153 unsigned size, unsigned alignment)
1154 {
1155 struct pipe_resource buffer;
1156
1157 memset(&buffer, 0, sizeof buffer);
1158 buffer.target = PIPE_BUFFER;
1159 buffer.format = PIPE_FORMAT_R8_UNORM;
1160 buffer.bind = PIPE_BIND_CUSTOM;
1161 buffer.usage = PIPE_USAGE_STATIC;
1162 buffer.flags = 0;
1163 buffer.width0 = size;
1164 buffer.height0 = 1;
1165 buffer.depth0 = 1;
1166 buffer.array_size = 1;
1167
1168 return (struct r600_resource*)
1169 r600_buffer_create(&rscreen->screen, &buffer, alignment);
1170 }
1171
1172 static void r600_init_color_surface(struct r600_context *rctx,
1173 struct r600_surface *surf,
1174 bool force_cmask_fmask)
1175 {
1176 struct r600_screen *rscreen = rctx->screen;
1177 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1178 unsigned level = surf->base.u.tex.level;
1179 unsigned pitch, slice;
1180 unsigned color_info;
1181 unsigned format, swap, ntype, endian;
1182 unsigned offset;
1183 const struct util_format_description *desc;
1184 int i;
1185 bool blend_bypass = 0, blend_clamp = 1;
1186
1187 if (rtex->is_depth && !rtex->is_flushing_texture) {
1188 r600_init_flushed_depth_texture(&rctx->context, surf->base.texture, NULL);
1189 rtex = rtex->flushed_depth_texture;
1190 assert(rtex);
1191 }
1192
1193 offset = rtex->surface.level[level].offset;
1194 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1195 offset += rtex->surface.level[level].slice_size *
1196 surf->base.u.tex.first_layer;
1197 }
1198 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1199 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1200 if (slice) {
1201 slice = slice - 1;
1202 }
1203 color_info = 0;
1204 switch (rtex->surface.level[level].mode) {
1205 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1206 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1207 break;
1208 case RADEON_SURF_MODE_1D:
1209 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1210 break;
1211 case RADEON_SURF_MODE_2D:
1212 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1213 break;
1214 case RADEON_SURF_MODE_LINEAR:
1215 default:
1216 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1217 break;
1218 }
1219
1220 desc = util_format_description(surf->base.format);
1221
1222 for (i = 0; i < 4; i++) {
1223 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1224 break;
1225 }
1226 }
1227
1228 ntype = V_0280A0_NUMBER_UNORM;
1229 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1230 ntype = V_0280A0_NUMBER_SRGB;
1231 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1232 if (desc->channel[i].normalized)
1233 ntype = V_0280A0_NUMBER_SNORM;
1234 else if (desc->channel[i].pure_integer)
1235 ntype = V_0280A0_NUMBER_SINT;
1236 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1237 if (desc->channel[i].normalized)
1238 ntype = V_0280A0_NUMBER_UNORM;
1239 else if (desc->channel[i].pure_integer)
1240 ntype = V_0280A0_NUMBER_UINT;
1241 }
1242
1243 format = r600_translate_colorformat(surf->base.format);
1244 assert(format != ~0);
1245
1246 swap = r600_translate_colorswap(surf->base.format);
1247 assert(swap != ~0);
1248
1249 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1250 endian = ENDIAN_NONE;
1251 } else {
1252 endian = r600_colorformat_endian_swap(format);
1253 }
1254
1255 /* set blend bypass according to docs if SINT/UINT or
1256 8/24 COLOR variants */
1257 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1258 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1259 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1260 blend_clamp = 0;
1261 blend_bypass = 1;
1262 }
1263
1264 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
1265
1266 color_info |= S_0280A0_FORMAT(format) |
1267 S_0280A0_COMP_SWAP(swap) |
1268 S_0280A0_BLEND_BYPASS(blend_bypass) |
1269 S_0280A0_BLEND_CLAMP(blend_clamp) |
1270 S_0280A0_NUMBER_TYPE(ntype) |
1271 S_0280A0_ENDIAN(endian);
1272
1273 /* EXPORT_NORM is an optimzation that can be enabled for better
1274 * performance in certain cases
1275 */
1276 if (rctx->chip_class == R600) {
1277 /* EXPORT_NORM can be enabled if:
1278 * - 11-bit or smaller UNORM/SNORM/SRGB
1279 * - BLEND_CLAMP is enabled
1280 * - BLEND_FLOAT32 is disabled
1281 */
1282 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1283 (desc->channel[i].size < 12 &&
1284 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1285 ntype != V_0280A0_NUMBER_UINT &&
1286 ntype != V_0280A0_NUMBER_SINT) &&
1287 G_0280A0_BLEND_CLAMP(color_info) &&
1288 !G_0280A0_BLEND_FLOAT32(color_info)) {
1289 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1290 surf->export_16bpc = true;
1291 }
1292 } else {
1293 /* EXPORT_NORM can be enabled if:
1294 * - 11-bit or smaller UNORM/SNORM/SRGB
1295 * - 16-bit or smaller FLOAT
1296 */
1297 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1298 ((desc->channel[i].size < 12 &&
1299 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1300 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1301 (desc->channel[i].size < 17 &&
1302 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1303 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1304 surf->export_16bpc = true;
1305 }
1306 }
1307
1308 /* These might not always be initialized to zero. */
1309 surf->cb_color_base = offset >> 8;
1310 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
1311 S_028060_SLICE_TILE_MAX(slice);
1312 surf->cb_color_fmask = surf->cb_color_base;
1313 surf->cb_color_cmask = surf->cb_color_base;
1314 surf->cb_color_mask = 0;
1315
1316 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1317 &rtex->resource.b.b);
1318 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1319 &rtex->resource.b.b);
1320
1321 if (rtex->cmask_size) {
1322 surf->cb_color_cmask = rtex->cmask_offset >> 8;
1323 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask_slice_tile_max);
1324
1325 if (rtex->fmask_size) {
1326 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1327 surf->cb_color_fmask = rtex->fmask_offset >> 8;
1328 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(slice);
1329 } else { /* cmask only */
1330 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
1331 }
1332 } else if (force_cmask_fmask) {
1333 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1334 *
1335 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1336 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1337 * because it's not an MSAA buffer.
1338 */
1339 struct r600_cmask_info cmask;
1340 struct r600_fmask_info fmask;
1341
1342 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
1343 r600_texture_get_fmask_info(rscreen, rtex, 8, &fmask);
1344
1345 /* CMASK. */
1346 if (!rctx->dummy_cmask ||
1347 rctx->dummy_cmask->buf->size < cmask.size ||
1348 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1349 struct pipe_transfer *transfer;
1350 void *ptr;
1351
1352 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1353 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1354
1355 /* Set the contents to 0xCC. */
1356 ptr = pipe_buffer_map(&rctx->context, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1357 memset(ptr, 0xCC, cmask.size);
1358 pipe_buffer_unmap(&rctx->context, transfer);
1359 }
1360 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1361 &rctx->dummy_cmask->b.b);
1362
1363 /* FMASK. */
1364 if (!rctx->dummy_fmask ||
1365 rctx->dummy_fmask->buf->size < fmask.size ||
1366 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1367 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1368 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1369
1370 }
1371 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1372 &rctx->dummy_fmask->b.b);
1373
1374 /* Init the registers. */
1375 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1376 surf->cb_color_cmask = 0;
1377 surf->cb_color_fmask = 0;
1378 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1379 S_028100_FMASK_TILE_MAX(slice);
1380 }
1381
1382 surf->cb_color_info = color_info;
1383
1384 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1385 surf->cb_color_view = 0;
1386 } else {
1387 surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
1388 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
1389 }
1390
1391 surf->color_initialized = true;
1392 }
1393
1394 static void r600_init_depth_surface(struct r600_context *rctx,
1395 struct r600_surface *surf)
1396 {
1397 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1398 unsigned level, pitch, slice, format, offset, array_mode;
1399
1400 level = surf->base.u.tex.level;
1401 offset = rtex->surface.level[level].offset;
1402 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1403 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1404 if (slice) {
1405 slice = slice - 1;
1406 }
1407 switch (rtex->surface.level[level].mode) {
1408 case RADEON_SURF_MODE_2D:
1409 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1410 break;
1411 case RADEON_SURF_MODE_1D:
1412 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1413 case RADEON_SURF_MODE_LINEAR:
1414 default:
1415 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1416 break;
1417 }
1418
1419 format = r600_translate_dbformat(surf->base.format);
1420 assert(format != ~0);
1421
1422 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1423 surf->db_depth_base = offset >> 8;
1424 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1425 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1426 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1427 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1428
1429 switch (surf->base.format) {
1430 case PIPE_FORMAT_Z24X8_UNORM:
1431 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1432 surf->pa_su_poly_offset_db_fmt_cntl =
1433 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1434 break;
1435 case PIPE_FORMAT_Z32_FLOAT:
1436 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1437 surf->pa_su_poly_offset_db_fmt_cntl =
1438 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1439 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1440 break;
1441 case PIPE_FORMAT_Z16_UNORM:
1442 surf->pa_su_poly_offset_db_fmt_cntl =
1443 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1444 break;
1445 default:;
1446 }
1447
1448 surf->depth_initialized = true;
1449 }
1450
1451 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1452 const struct pipe_framebuffer_state *state)
1453 {
1454 struct r600_context *rctx = (struct r600_context *)ctx;
1455 struct r600_surface *surf;
1456 struct r600_texture *rtex;
1457 unsigned i;
1458
1459 if (rctx->framebuffer.state.nr_cbufs) {
1460 rctx->flags |= R600_CONTEXT_CB_FLUSH;
1461
1462 if (rctx->chip_class >= R700 &&
1463 rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
1464 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
1465 }
1466 }
1467 if (rctx->framebuffer.state.zsbuf) {
1468 rctx->flags |= R600_CONTEXT_DB_FLUSH;
1469 }
1470 /* R6xx errata */
1471 if (rctx->chip_class == R600) {
1472 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
1473 }
1474
1475 /* Set the new state. */
1476 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1477
1478 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1479 rctx->framebuffer.cb0_is_integer = state->nr_cbufs &&
1480 util_format_is_pure_integer(state->cbufs[0]->format);
1481 rctx->framebuffer.compressed_cb_mask = 0;
1482 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1483 state->cbufs[0]->texture->nr_samples > 1 &&
1484 state->cbufs[1]->texture->nr_samples <= 1;
1485
1486 if (state->nr_cbufs)
1487 rctx->framebuffer.nr_samples = state->cbufs[0]->texture->nr_samples;
1488 else if (state->zsbuf)
1489 rctx->framebuffer.nr_samples = state->zsbuf->texture->nr_samples;
1490 else
1491 rctx->framebuffer.nr_samples = 0;
1492
1493 /* Colorbuffers. */
1494 for (i = 0; i < state->nr_cbufs; i++) {
1495 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1496 bool force_cmask_fmask = rctx->chip_class == R600 &&
1497 rctx->framebuffer.is_msaa_resolve &&
1498 i == 1;
1499
1500 surf = (struct r600_surface*)state->cbufs[i];
1501 rtex = (struct r600_texture*)surf->base.texture;
1502
1503 if (!surf->color_initialized || force_cmask_fmask) {
1504 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1505 if (force_cmask_fmask) {
1506 /* re-initialize later without compression */
1507 surf->color_initialized = false;
1508 }
1509 }
1510
1511 if (!surf->export_16bpc) {
1512 rctx->framebuffer.export_16bpc = false;
1513 }
1514
1515 if (rtex->fmask_size && rtex->cmask_size) {
1516 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1517 }
1518 }
1519
1520 /* Update alpha-test state dependencies.
1521 * Alpha-test is done on the first colorbuffer only. */
1522 if (state->nr_cbufs) {
1523 surf = (struct r600_surface*)state->cbufs[0];
1524 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1525 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1526 rctx->alphatest_state.atom.dirty = true;
1527 }
1528 }
1529
1530 /* ZS buffer. */
1531 if (state->zsbuf) {
1532 surf = (struct r600_surface*)state->zsbuf;
1533
1534 if (!surf->depth_initialized) {
1535 r600_init_depth_surface(rctx, surf);
1536 }
1537
1538 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1539 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1540 rctx->poly_offset_state.atom.dirty = true;
1541 }
1542 }
1543
1544 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1545 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1546 rctx->cb_misc_state.atom.dirty = true;
1547 }
1548
1549 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1550 rctx->alphatest_state.bypass = false;
1551 rctx->alphatest_state.atom.dirty = true;
1552 }
1553
1554 r600_update_db_shader_control(rctx);
1555
1556 /* Calculate the CS size. */
1557 rctx->framebuffer.atom.num_dw =
1558 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1559
1560 if (rctx->framebuffer.state.nr_cbufs) {
1561 rctx->framebuffer.atom.num_dw += 6 * (2 + rctx->framebuffer.state.nr_cbufs);
1562 rctx->framebuffer.atom.num_dw += 6 * rctx->framebuffer.state.nr_cbufs; /* relocs */
1563
1564 }
1565 if (rctx->framebuffer.state.zsbuf) {
1566 rctx->framebuffer.atom.num_dw += 16;
1567 } else if (rctx->screen->info.drm_minor >= 18) {
1568 rctx->framebuffer.atom.num_dw += 3;
1569 }
1570 if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770) {
1571 rctx->framebuffer.atom.num_dw += 2;
1572 }
1573
1574 rctx->framebuffer.atom.dirty = true;
1575 }
1576
1577 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1578 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1579 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1580 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1581 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1582
1583 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1584 {
1585 static uint32_t sample_locs_2x[] = {
1586 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1587 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1588 };
1589 static unsigned max_dist_2x = 4;
1590 static uint32_t sample_locs_4x[] = {
1591 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1592 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1593 };
1594 static unsigned max_dist_4x = 6;
1595 static uint32_t sample_locs_8x[] = {
1596 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1597 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1598 };
1599 static unsigned max_dist_8x = 8;
1600
1601 struct radeon_winsys_cs *cs = rctx->cs;
1602 unsigned max_dist = 0;
1603
1604 if (rctx->family == CHIP_R600) {
1605 switch (nr_samples) {
1606 default:
1607 nr_samples = 0;
1608 break;
1609 case 2:
1610 r600_write_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1611 max_dist = max_dist_2x;
1612 break;
1613 case 4:
1614 r600_write_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1615 max_dist = max_dist_4x;
1616 break;
1617 case 8:
1618 r600_write_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1619 r600_write_value(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1620 r600_write_value(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1621 max_dist = max_dist_8x;
1622 break;
1623 }
1624 } else {
1625 switch (nr_samples) {
1626 default:
1627 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1628 r600_write_value(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1629 r600_write_value(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1630 nr_samples = 0;
1631 break;
1632 case 2:
1633 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1634 r600_write_value(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1635 r600_write_value(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1636 max_dist = max_dist_2x;
1637 break;
1638 case 4:
1639 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1640 r600_write_value(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1641 r600_write_value(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1642 max_dist = max_dist_4x;
1643 break;
1644 case 8:
1645 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1646 r600_write_value(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1647 r600_write_value(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1648 max_dist = max_dist_8x;
1649 break;
1650 }
1651 }
1652
1653 if (nr_samples > 1) {
1654 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1655 r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
1656 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1657 r600_write_value(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1658 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1659 } else {
1660 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1661 r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1662 r600_write_value(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1663 }
1664 }
1665
1666 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1667 {
1668 struct radeon_winsys_cs *cs = rctx->cs;
1669 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1670 unsigned nr_cbufs = state->nr_cbufs;
1671 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1672 unsigned i, sbu = 0;
1673
1674 /* Colorbuffers. */
1675 r600_write_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1676 for (i = 0; i < nr_cbufs; i++) {
1677 r600_write_value(cs, cb[i]->cb_color_info);
1678 }
1679 /* set CB_COLOR1_INFO for possible dual-src blending */
1680 if (i == 1) {
1681 r600_write_value(cs, cb[0]->cb_color_info);
1682 i++;
1683 }
1684 for (; i < 8; i++) {
1685 r600_write_value(cs, 0);
1686 }
1687
1688 if (nr_cbufs) {
1689 /* COLOR_BASE */
1690 r600_write_context_reg_seq(cs, R_028040_CB_COLOR0_BASE, nr_cbufs);
1691 for (i = 0; i < nr_cbufs; i++) {
1692 r600_write_value(cs, cb[i]->cb_color_base);
1693 }
1694
1695 /* relocations */
1696 for (i = 0; i < nr_cbufs; i++) {
1697 unsigned reloc = r600_context_bo_reloc(rctx,
1698 (struct r600_resource*)cb[i]->base.texture,
1699 RADEON_USAGE_READWRITE);
1700 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1701 r600_write_value(cs, reloc);
1702 }
1703
1704 r600_write_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1705 for (i = 0; i < nr_cbufs; i++) {
1706 r600_write_value(cs, cb[i]->cb_color_size);
1707 }
1708
1709 r600_write_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1710 for (i = 0; i < nr_cbufs; i++) {
1711 r600_write_value(cs, cb[i]->cb_color_view);
1712 }
1713
1714 r600_write_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1715 for (i = 0; i < nr_cbufs; i++) {
1716 r600_write_value(cs, cb[i]->cb_color_mask);
1717 }
1718
1719 /* FMASK. */
1720 r600_write_context_reg_seq(cs, R_0280E0_CB_COLOR0_FRAG, nr_cbufs);
1721 for (i = 0; i < nr_cbufs; i++) {
1722 r600_write_value(cs, cb[i]->cb_color_fmask);
1723 }
1724 /* relocations */
1725 for (i = 0; i < nr_cbufs; i++) {
1726 unsigned reloc = r600_context_bo_reloc(rctx,
1727 cb[i]->cb_buffer_fmask,
1728 RADEON_USAGE_READWRITE);
1729 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1730 r600_write_value(cs, reloc);
1731 }
1732
1733 /* CMASK. */
1734 r600_write_context_reg_seq(cs, R_0280C0_CB_COLOR0_TILE, nr_cbufs);
1735 for (i = 0; i < nr_cbufs; i++) {
1736 r600_write_value(cs, cb[i]->cb_color_cmask);
1737 }
1738 /* relocations */
1739 for (i = 0; i < nr_cbufs; i++) {
1740 unsigned reloc = r600_context_bo_reloc(rctx,
1741 cb[i]->cb_buffer_cmask,
1742 RADEON_USAGE_READWRITE);
1743 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1744 r600_write_value(cs, reloc);
1745 }
1746
1747 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1748 }
1749
1750 /* Zbuffer. */
1751 if (state->zsbuf) {
1752 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1753 unsigned reloc = r600_context_bo_reloc(rctx,
1754 (struct r600_resource*)state->zsbuf->texture,
1755 RADEON_USAGE_READWRITE);
1756
1757 r600_write_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1758 surf->pa_su_poly_offset_db_fmt_cntl);
1759
1760 r600_write_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1761 r600_write_value(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1762 r600_write_value(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1763 r600_write_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1764 r600_write_value(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1765 r600_write_value(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1766
1767 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1768 r600_write_value(cs, reloc);
1769
1770 r600_write_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1771
1772 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1773 } else if (rctx->screen->info.drm_minor >= 18) {
1774 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1775 * Older kernels are out of luck. */
1776 r600_write_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1777 }
1778
1779 /* SURFACE_BASE_UPDATE */
1780 if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770 && sbu) {
1781 r600_write_value(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1782 r600_write_value(cs, sbu);
1783 }
1784
1785 /* Framebuffer dimensions. */
1786 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1787 r600_write_value(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1788 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1789 r600_write_value(cs, S_028244_BR_X(state->width) |
1790 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1791
1792 if (rctx->framebuffer.is_msaa_resolve) {
1793 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1794 } else {
1795 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1796 * will assure that the alpha-test will work even if there is
1797 * no colorbuffer bound. */
1798 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1799 (1ull << MAX2(nr_cbufs, 1)) - 1);
1800 }
1801
1802 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1803 }
1804
1805 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1806 {
1807 struct radeon_winsys_cs *cs = rctx->cs;
1808 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1809
1810 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1811 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1812 if (rctx->chip_class == R600) {
1813 r600_write_value(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1814 r600_write_value(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1815 } else {
1816 r600_write_value(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1817 r600_write_value(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1818 }
1819 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1820 } else {
1821 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1822 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1823 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1824
1825 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1826 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1827 /* Always enable the first color output to make sure alpha-test works even without one. */
1828 r600_write_value(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1829 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1830 a->cb_color_control |
1831 S_028808_MULTIWRITE_ENABLE(multiwrite));
1832 }
1833 }
1834
1835 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1836 {
1837 struct radeon_winsys_cs *cs = rctx->cs;
1838 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1839 unsigned db_render_control = 0;
1840 unsigned db_render_override =
1841 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
1842 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1843 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1844
1845 if (a->occlusion_query_enabled) {
1846 if (rctx->chip_class >= R700) {
1847 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1848 }
1849 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1850 }
1851 if (a->flush_depthstencil_through_cb) {
1852 assert(a->copy_depth || a->copy_stencil);
1853
1854 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1855 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1856 S_028D0C_COPY_CENTROID(1) |
1857 S_028D0C_COPY_SAMPLE(a->copy_sample);
1858 }
1859
1860 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1861 r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1862 r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1863 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1864 }
1865
1866 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1867 {
1868 struct radeon_winsys_cs *cs = rctx->cs;
1869 struct r600_config_state *a = (struct r600_config_state*)atom;
1870
1871 r600_write_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1872 }
1873
1874 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1875 {
1876 struct radeon_winsys_cs *cs = rctx->cs;
1877 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1878
1879 while (dirty_mask) {
1880 struct pipe_vertex_buffer *vb;
1881 struct r600_resource *rbuffer;
1882 unsigned offset;
1883 unsigned buffer_index = u_bit_scan(&dirty_mask);
1884
1885 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1886 rbuffer = (struct r600_resource*)vb->buffer;
1887 assert(rbuffer);
1888
1889 offset = vb->buffer_offset;
1890
1891 /* fetch resources start at index 320 */
1892 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1893 r600_write_value(cs, (320 + buffer_index) * 7);
1894 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1895 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1896 r600_write_value(cs, /* RESOURCEi_WORD2 */
1897 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1898 S_038008_STRIDE(vb->stride));
1899 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1900 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1901 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1902 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1903
1904 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1905 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1906 }
1907 }
1908
1909 static void r600_emit_constant_buffers(struct r600_context *rctx,
1910 struct r600_constbuf_state *state,
1911 unsigned buffer_id_base,
1912 unsigned reg_alu_constbuf_size,
1913 unsigned reg_alu_const_cache)
1914 {
1915 struct radeon_winsys_cs *cs = rctx->cs;
1916 uint32_t dirty_mask = state->dirty_mask;
1917
1918 while (dirty_mask) {
1919 struct pipe_constant_buffer *cb;
1920 struct r600_resource *rbuffer;
1921 unsigned offset;
1922 unsigned buffer_index = ffs(dirty_mask) - 1;
1923
1924 cb = &state->cb[buffer_index];
1925 rbuffer = (struct r600_resource*)cb->buffer;
1926 assert(rbuffer);
1927
1928 offset = cb->buffer_offset;
1929
1930 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1931 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1932 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1933
1934 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1935 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1936
1937 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1938 r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
1939 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1940 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1941 r600_write_value(cs, /* RESOURCEi_WORD2 */
1942 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1943 S_038008_STRIDE(16));
1944 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1945 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1946 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1947 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1948
1949 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1950 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1951
1952 dirty_mask &= ~(1 << buffer_index);
1953 }
1954 state->dirty_mask = 0;
1955 }
1956
1957 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1958 {
1959 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 160,
1960 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1961 R_028980_ALU_CONST_CACHE_VS_0);
1962 }
1963
1964 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1965 {
1966 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
1967 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1968 R_0289C0_ALU_CONST_CACHE_GS_0);
1969 }
1970
1971 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1972 {
1973 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
1974 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1975 R_028940_ALU_CONST_CACHE_PS_0);
1976 }
1977
1978 static void r600_emit_sampler_views(struct r600_context *rctx,
1979 struct r600_samplerview_state *state,
1980 unsigned resource_id_base)
1981 {
1982 struct radeon_winsys_cs *cs = rctx->cs;
1983 uint32_t dirty_mask = state->dirty_mask;
1984
1985 while (dirty_mask) {
1986 struct r600_pipe_sampler_view *rview;
1987 unsigned resource_index = u_bit_scan(&dirty_mask);
1988 unsigned reloc;
1989
1990 rview = state->views[resource_index];
1991 assert(rview);
1992
1993 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1994 r600_write_value(cs, (resource_id_base + resource_index) * 7);
1995 r600_write_array(cs, 7, rview->tex_resource_words);
1996
1997 /* XXX The kernel needs two relocations. This is stupid. */
1998 reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
1999 RADEON_USAGE_READ);
2000 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2001 r600_write_value(cs, reloc);
2002 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2003 r600_write_value(cs, reloc);
2004 }
2005 state->dirty_mask = 0;
2006 }
2007
2008 /* Resource IDs:
2009 * PS: 0 .. +160
2010 * VS: 160 .. +160
2011 * FS: 320 .. +16
2012 * GS: 336 .. +160
2013 */
2014
2015 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2016 {
2017 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 160 + R600_MAX_CONST_BUFFERS);
2018 }
2019
2020 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2021 {
2022 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
2023 }
2024
2025 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2026 {
2027 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
2028 }
2029
2030 static void r600_emit_sampler_states(struct r600_context *rctx,
2031 struct r600_textures_info *texinfo,
2032 unsigned resource_id_base,
2033 unsigned border_color_reg)
2034 {
2035 struct radeon_winsys_cs *cs = rctx->cs;
2036 uint32_t dirty_mask = texinfo->states.dirty_mask;
2037
2038 while (dirty_mask) {
2039 struct r600_pipe_sampler_state *rstate;
2040 struct r600_pipe_sampler_view *rview;
2041 unsigned i = u_bit_scan(&dirty_mask);
2042
2043 rstate = texinfo->states.states[i];
2044 assert(rstate);
2045 rview = texinfo->views.views[i];
2046
2047 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
2048 * filtering between layers.
2049 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
2050 */
2051 if (rview) {
2052 enum pipe_texture_target target = rview->base.texture->target;
2053 if (target == PIPE_TEXTURE_1D_ARRAY ||
2054 target == PIPE_TEXTURE_2D_ARRAY) {
2055 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
2056 texinfo->is_array_sampler[i] = true;
2057 } else {
2058 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
2059 texinfo->is_array_sampler[i] = false;
2060 }
2061 }
2062
2063 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2064 r600_write_value(cs, (resource_id_base + i) * 3);
2065 r600_write_array(cs, 3, rstate->tex_sampler_words);
2066
2067 if (rstate->border_color_use) {
2068 unsigned offset;
2069
2070 offset = border_color_reg;
2071 offset += i * 16;
2072 r600_write_config_reg_seq(cs, offset, 4);
2073 r600_write_array(cs, 4, rstate->border_color);
2074 }
2075 }
2076 texinfo->states.dirty_mask = 0;
2077 }
2078
2079 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2080 {
2081 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
2082 }
2083
2084 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2085 {
2086 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
2087 }
2088
2089 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2090 {
2091 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
2092 }
2093
2094 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
2095 {
2096 struct radeon_winsys_cs *cs = rctx->cs;
2097 unsigned tmp;
2098
2099 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
2100 S_009508_SYNC_GRADIENT(1) |
2101 S_009508_SYNC_WALKER(1) |
2102 S_009508_SYNC_ALIGNER(1);
2103 if (!rctx->seamless_cube_map.enabled) {
2104 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
2105 }
2106 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
2107 }
2108
2109 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2110 {
2111 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2112 uint8_t mask = s->sample_mask;
2113
2114 r600_write_context_reg(rctx->cs, R_028C48_PA_SC_AA_MASK,
2115 mask | (mask << 8) | (mask << 16) | (mask << 24));
2116 }
2117
2118 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2119 {
2120 struct radeon_winsys_cs *cs = rctx->cs;
2121 struct r600_cso_state *state = (struct r600_cso_state*)a;
2122 struct r600_resource *shader = (struct r600_resource*)state->cso;
2123
2124 r600_write_context_reg(cs, R_028894_SQ_PGM_START_FS, 0);
2125 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2126 r600_write_value(cs, r600_context_bo_reloc(rctx, shader, RADEON_USAGE_READ));
2127 }
2128
2129 void r600_init_state_functions(struct r600_context *rctx)
2130 {
2131 unsigned id = 4;
2132
2133 /* !!!
2134 * To avoid GPU lockup registers must be emited in a specific order
2135 * (no kidding ...). The order below is important and have been
2136 * partialy infered from analyzing fglrx command stream.
2137 *
2138 * Don't reorder atom without carefully checking the effect (GPU lockup
2139 * or piglit regression).
2140 * !!!
2141 */
2142
2143 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
2144
2145 /* shader const */
2146 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
2147 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
2148 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
2149
2150 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2151 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
2152 */
2153 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
2154 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
2155 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
2156 /* resource */
2157 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
2158 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
2159 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
2160 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
2161
2162 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 6);
2163 r600_init_atom(rctx, &rctx->vgt2_state.atom, id++, r600_emit_vgt2_state, 3);
2164
2165 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
2166 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
2167 rctx->sample_mask.sample_mask = ~0;
2168
2169 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
2170 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
2171 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
2172 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
2173 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
2174 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
2175 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
2176 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
2177 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
2178 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
2179 r600_init_atom(rctx, &rctx->scissor.atom, id++, r600_emit_scissor_state, 4);
2180 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
2181 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
2182 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
2183 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
2184
2185 rctx->context.create_blend_state = r600_create_blend_state;
2186 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
2187 rctx->context.create_rasterizer_state = r600_create_rs_state;
2188 rctx->context.create_sampler_state = r600_create_sampler_state;
2189 rctx->context.create_sampler_view = r600_create_sampler_view;
2190 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
2191 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
2192 rctx->context.set_scissor_state = r600_set_scissor_state;
2193 }
2194
2195 /* Adjust GPR allocation on R6xx/R7xx */
2196 void r600_adjust_gprs(struct r600_context *rctx)
2197 {
2198 unsigned num_ps_gprs = rctx->default_ps_gprs;
2199 unsigned num_vs_gprs = rctx->default_vs_gprs;
2200 unsigned tmp;
2201 int diff;
2202
2203 if (rctx->ps_shader->current->shader.bc.ngpr > rctx->default_ps_gprs) {
2204 diff = rctx->ps_shader->current->shader.bc.ngpr - rctx->default_ps_gprs;
2205 num_vs_gprs -= diff;
2206 num_ps_gprs += diff;
2207 }
2208
2209 if (rctx->vs_shader->current->shader.bc.ngpr > rctx->default_vs_gprs)
2210 {
2211 diff = rctx->vs_shader->current->shader.bc.ngpr - rctx->default_vs_gprs;
2212 num_ps_gprs -= diff;
2213 num_vs_gprs += diff;
2214 }
2215
2216 tmp = 0;
2217 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2218 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2219 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
2220
2221 if (tmp != rctx->config_state.sq_gpr_resource_mgmt_1) {
2222 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2223 rctx->config_state.atom.dirty = true;
2224 rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
2225 }
2226 }
2227
2228 void r600_init_atom_start_cs(struct r600_context *rctx)
2229 {
2230 int ps_prio;
2231 int vs_prio;
2232 int gs_prio;
2233 int es_prio;
2234 int num_ps_gprs;
2235 int num_vs_gprs;
2236 int num_gs_gprs;
2237 int num_es_gprs;
2238 int num_temp_gprs;
2239 int num_ps_threads;
2240 int num_vs_threads;
2241 int num_gs_threads;
2242 int num_es_threads;
2243 int num_ps_stack_entries;
2244 int num_vs_stack_entries;
2245 int num_gs_stack_entries;
2246 int num_es_stack_entries;
2247 enum radeon_family family;
2248 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2249 uint32_t tmp;
2250
2251 r600_init_command_buffer(cb, 256);
2252
2253 /* R6xx requires this packet at the start of each command buffer */
2254 if (rctx->chip_class == R600) {
2255 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2256 r600_store_value(cb, 0);
2257 }
2258 /* All asics require this one */
2259 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2260 r600_store_value(cb, 0x80000000);
2261 r600_store_value(cb, 0x80000000);
2262
2263 /* We're setting config registers here. */
2264 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2265 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2266
2267 family = rctx->family;
2268 ps_prio = 0;
2269 vs_prio = 1;
2270 gs_prio = 2;
2271 es_prio = 3;
2272 switch (family) {
2273 case CHIP_R600:
2274 num_ps_gprs = 192;
2275 num_vs_gprs = 56;
2276 num_temp_gprs = 4;
2277 num_gs_gprs = 0;
2278 num_es_gprs = 0;
2279 num_ps_threads = 136;
2280 num_vs_threads = 48;
2281 num_gs_threads = 4;
2282 num_es_threads = 4;
2283 num_ps_stack_entries = 128;
2284 num_vs_stack_entries = 128;
2285 num_gs_stack_entries = 0;
2286 num_es_stack_entries = 0;
2287 break;
2288 case CHIP_RV630:
2289 case CHIP_RV635:
2290 num_ps_gprs = 84;
2291 num_vs_gprs = 36;
2292 num_temp_gprs = 4;
2293 num_gs_gprs = 0;
2294 num_es_gprs = 0;
2295 num_ps_threads = 144;
2296 num_vs_threads = 40;
2297 num_gs_threads = 4;
2298 num_es_threads = 4;
2299 num_ps_stack_entries = 40;
2300 num_vs_stack_entries = 40;
2301 num_gs_stack_entries = 32;
2302 num_es_stack_entries = 16;
2303 break;
2304 case CHIP_RV610:
2305 case CHIP_RV620:
2306 case CHIP_RS780:
2307 case CHIP_RS880:
2308 default:
2309 num_ps_gprs = 84;
2310 num_vs_gprs = 36;
2311 num_temp_gprs = 4;
2312 num_gs_gprs = 0;
2313 num_es_gprs = 0;
2314 num_ps_threads = 136;
2315 num_vs_threads = 48;
2316 num_gs_threads = 4;
2317 num_es_threads = 4;
2318 num_ps_stack_entries = 40;
2319 num_vs_stack_entries = 40;
2320 num_gs_stack_entries = 32;
2321 num_es_stack_entries = 16;
2322 break;
2323 case CHIP_RV670:
2324 num_ps_gprs = 144;
2325 num_vs_gprs = 40;
2326 num_temp_gprs = 4;
2327 num_gs_gprs = 0;
2328 num_es_gprs = 0;
2329 num_ps_threads = 136;
2330 num_vs_threads = 48;
2331 num_gs_threads = 4;
2332 num_es_threads = 4;
2333 num_ps_stack_entries = 40;
2334 num_vs_stack_entries = 40;
2335 num_gs_stack_entries = 32;
2336 num_es_stack_entries = 16;
2337 break;
2338 case CHIP_RV770:
2339 num_ps_gprs = 192;
2340 num_vs_gprs = 56;
2341 num_temp_gprs = 4;
2342 num_gs_gprs = 0;
2343 num_es_gprs = 0;
2344 num_ps_threads = 188;
2345 num_vs_threads = 60;
2346 num_gs_threads = 0;
2347 num_es_threads = 0;
2348 num_ps_stack_entries = 256;
2349 num_vs_stack_entries = 256;
2350 num_gs_stack_entries = 0;
2351 num_es_stack_entries = 0;
2352 break;
2353 case CHIP_RV730:
2354 case CHIP_RV740:
2355 num_ps_gprs = 84;
2356 num_vs_gprs = 36;
2357 num_temp_gprs = 4;
2358 num_gs_gprs = 0;
2359 num_es_gprs = 0;
2360 num_ps_threads = 188;
2361 num_vs_threads = 60;
2362 num_gs_threads = 0;
2363 num_es_threads = 0;
2364 num_ps_stack_entries = 128;
2365 num_vs_stack_entries = 128;
2366 num_gs_stack_entries = 0;
2367 num_es_stack_entries = 0;
2368 break;
2369 case CHIP_RV710:
2370 num_ps_gprs = 192;
2371 num_vs_gprs = 56;
2372 num_temp_gprs = 4;
2373 num_gs_gprs = 0;
2374 num_es_gprs = 0;
2375 num_ps_threads = 144;
2376 num_vs_threads = 48;
2377 num_gs_threads = 0;
2378 num_es_threads = 0;
2379 num_ps_stack_entries = 128;
2380 num_vs_stack_entries = 128;
2381 num_gs_stack_entries = 0;
2382 num_es_stack_entries = 0;
2383 break;
2384 }
2385
2386 rctx->default_ps_gprs = num_ps_gprs;
2387 rctx->default_vs_gprs = num_vs_gprs;
2388 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2389
2390 /* SQ_CONFIG */
2391 tmp = 0;
2392 switch (family) {
2393 case CHIP_RV610:
2394 case CHIP_RV620:
2395 case CHIP_RS780:
2396 case CHIP_RS880:
2397 case CHIP_RV710:
2398 break;
2399 default:
2400 tmp |= S_008C00_VC_ENABLE(1);
2401 break;
2402 }
2403 tmp |= S_008C00_DX9_CONSTS(0);
2404 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2405 tmp |= S_008C00_PS_PRIO(ps_prio);
2406 tmp |= S_008C00_VS_PRIO(vs_prio);
2407 tmp |= S_008C00_GS_PRIO(gs_prio);
2408 tmp |= S_008C00_ES_PRIO(es_prio);
2409 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2410
2411 /* SQ_GPR_RESOURCE_MGMT_2 */
2412 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2413 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2414 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2415 r600_store_value(cb, tmp);
2416
2417 /* SQ_THREAD_RESOURCE_MGMT */
2418 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2419 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2420 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2421 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2422 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2423
2424 /* SQ_STACK_RESOURCE_MGMT_1 */
2425 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2426 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2427 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2428
2429 /* SQ_STACK_RESOURCE_MGMT_2 */
2430 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2431 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2432 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2433
2434 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2435
2436 if (rctx->chip_class >= R700) {
2437 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2438 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2439 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2440 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2441 } else {
2442 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2443 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2444 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2445 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2446 }
2447 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2448 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2449 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2450 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2451 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2452 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2453 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2454 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2455 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2456 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2457
2458 /* to avoid GPU doing any preloading of constant from random address */
2459 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2460 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2461 r600_store_value(cb, 0);
2462 r600_store_value(cb, 0);
2463 r600_store_value(cb, 0);
2464 r600_store_value(cb, 0);
2465 r600_store_value(cb, 0);
2466 r600_store_value(cb, 0);
2467 r600_store_value(cb, 0);
2468 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2469 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2470 r600_store_value(cb, 0);
2471 r600_store_value(cb, 0);
2472 r600_store_value(cb, 0);
2473 r600_store_value(cb, 0);
2474 r600_store_value(cb, 0);
2475 r600_store_value(cb, 0);
2476 r600_store_value(cb, 0);
2477
2478 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2479 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2480 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2481 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2482 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2483 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2484 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2485 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2486 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2487 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2488 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2489 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2490 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2491 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2492
2493 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2494 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2495 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2496
2497 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2498 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2499 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2500 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2501
2502 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2503
2504 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2505
2506 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2507 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2508 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2509
2510 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2511 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2512 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2513 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2514
2515 r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2516 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2517 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2518
2519 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2520 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2521
2522 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2523 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2524 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2525 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2526 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2527
2528 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2529 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2530 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2531
2532 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2533
2534 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2535 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2536
2537 if (rctx->chip_class >= R700) {
2538 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2539 }
2540
2541 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2542 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2543 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2544 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2545 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2546
2547 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2548 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2549 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2550
2551 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2552 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2553 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2554
2555 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2556 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2557 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2558
2559 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2560 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2561 r600_store_value(cb, 0);
2562 r600_store_value(cb, 0);
2563 r600_store_value(cb, 0);
2564 r600_store_value(cb, 0);
2565 r600_store_value(cb, 0);
2566 r600_store_value(cb, 0);
2567 r600_store_value(cb, 0);
2568 r600_store_value(cb, 0);
2569 r600_store_value(cb, 0);
2570 r600_store_value(cb, 0);
2571 r600_store_value(cb, 0);
2572 r600_store_value(cb, 0);
2573 r600_store_value(cb, 0);
2574 r600_store_value(cb, 0);
2575 r600_store_value(cb, 0);
2576 r600_store_value(cb, 0);
2577 r600_store_value(cb, 0);
2578 r600_store_value(cb, 0);
2579 r600_store_value(cb, 0);
2580 r600_store_value(cb, 0);
2581 r600_store_value(cb, 0);
2582 r600_store_value(cb, 0);
2583 r600_store_value(cb, 0);
2584 r600_store_value(cb, 0);
2585 r600_store_value(cb, 0);
2586 r600_store_value(cb, 0);
2587 r600_store_value(cb, 0);
2588 r600_store_value(cb, 0);
2589 r600_store_value(cb, 0);
2590 r600_store_value(cb, 0);
2591 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2592 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2593 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2594
2595 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2596 r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2597
2598 if (rctx->chip_class == R700 && rctx->screen->has_streamout)
2599 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2600 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2601 if (rctx->screen->has_streamout) {
2602 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2603 }
2604
2605 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2606 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2607 }
2608
2609 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2610 {
2611 struct r600_context *rctx = (struct r600_context *)ctx;
2612 struct r600_pipe_state *rstate = &shader->rstate;
2613 struct r600_shader *rshader = &shader->shader;
2614 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2615 int pos_index = -1, face_index = -1;
2616 unsigned tmp, sid, ufi = 0;
2617 int need_linear = 0;
2618 unsigned z_export = 0, stencil_export = 0;
2619 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2620
2621 rstate->nregs = 0;
2622
2623 for (i = 0; i < rshader->ninput; i++) {
2624 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2625 pos_index = i;
2626 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2627 face_index = i;
2628
2629 sid = rshader->input[i].spi_sid;
2630
2631 tmp = S_028644_SEMANTIC(sid);
2632
2633 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2634 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2635 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2636 rctx->rasterizer && rctx->rasterizer->flatshade))
2637 tmp |= S_028644_FLAT_SHADE(1);
2638
2639 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2640 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2641 tmp |= S_028644_PT_SPRITE_TEX(1);
2642 }
2643
2644 if (rshader->input[i].centroid)
2645 tmp |= S_028644_SEL_CENTROID(1);
2646
2647 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2648 need_linear = 1;
2649 tmp |= S_028644_SEL_LINEAR(1);
2650 }
2651
2652 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2653 tmp);
2654 }
2655
2656 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2657 for (i = 0; i < rshader->noutput; i++) {
2658 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2659 z_export = 1;
2660 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2661 stencil_export = 1;
2662 }
2663 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2664 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2665 if (rshader->uses_kill)
2666 db_shader_control |= S_02880C_KILL_ENABLE(1);
2667
2668 exports_ps = 0;
2669 for (i = 0; i < rshader->noutput; i++) {
2670 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2671 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2672 exports_ps |= 1;
2673 }
2674 }
2675 num_cout = rshader->nr_ps_color_exports;
2676 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2677 if (!exports_ps) {
2678 /* always at least export 1 component per pixel */
2679 exports_ps = 2;
2680 }
2681
2682 shader->nr_ps_color_outputs = num_cout;
2683
2684 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2685 S_0286CC_PERSP_GRADIENT_ENA(1)|
2686 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2687 spi_input_z = 0;
2688 if (pos_index != -1) {
2689 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2690 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2691 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2692 S_0286CC_BARYC_SAMPLE_CNTL(1));
2693 spi_input_z |= 1;
2694 }
2695
2696 spi_ps_in_control_1 = 0;
2697 if (face_index != -1) {
2698 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2699 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2700 }
2701
2702 /* HW bug in original R600 */
2703 if (rctx->family == CHIP_R600)
2704 ufi = 1;
2705
2706 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2707 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2708 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2709 r600_pipe_state_add_reg_bo(rstate,
2710 R_028840_SQ_PGM_START_PS,
2711 0, shader->bo, RADEON_USAGE_READ);
2712 r600_pipe_state_add_reg(rstate,
2713 R_028850_SQ_PGM_RESOURCES_PS,
2714 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2715 S_028850_STACK_SIZE(rshader->bc.nstack) |
2716 S_028850_UNCACHED_FIRST_INST(ufi));
2717 r600_pipe_state_add_reg(rstate,
2718 R_028854_SQ_PGM_EXPORTS_PS,
2719 exports_ps);
2720 /* only set some bits here, the other bits are set in the dsa state */
2721 shader->db_shader_control = db_shader_control;
2722 shader->ps_depth_export = z_export | stencil_export;
2723
2724 shader->sprite_coord_enable = sprite_coord_enable;
2725 if (rctx->rasterizer)
2726 shader->flatshade = rctx->rasterizer->flatshade;
2727 }
2728
2729 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2730 {
2731 struct r600_context *rctx = (struct r600_context *)ctx;
2732 struct r600_pipe_state *rstate = &shader->rstate;
2733 struct r600_shader *rshader = &shader->shader;
2734 unsigned spi_vs_out_id[10] = {};
2735 unsigned i, tmp, nparams = 0;
2736
2737 /* clear previous register */
2738 rstate->nregs = 0;
2739
2740 for (i = 0; i < rshader->noutput; i++) {
2741 if (rshader->output[i].spi_sid) {
2742 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2743 spi_vs_out_id[nparams / 4] |= tmp;
2744 nparams++;
2745 }
2746 }
2747
2748 for (i = 0; i < 10; i++) {
2749 r600_pipe_state_add_reg(rstate,
2750 R_028614_SPI_VS_OUT_ID_0 + i * 4,
2751 spi_vs_out_id[i]);
2752 }
2753
2754 /* Certain attributes (position, psize, etc.) don't count as params.
2755 * VS is required to export at least one param and r600_shader_from_tgsi()
2756 * takes care of adding a dummy export.
2757 */
2758 if (nparams < 1)
2759 nparams = 1;
2760
2761 r600_pipe_state_add_reg(rstate,
2762 R_0286C4_SPI_VS_OUT_CONFIG,
2763 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2764 r600_pipe_state_add_reg(rstate,
2765 R_028868_SQ_PGM_RESOURCES_VS,
2766 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2767 S_028868_STACK_SIZE(rshader->bc.nstack));
2768 r600_pipe_state_add_reg_bo(rstate,
2769 R_028858_SQ_PGM_START_VS,
2770 0, shader->bo, RADEON_USAGE_READ);
2771
2772 shader->pa_cl_vs_out_cntl =
2773 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2774 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2775 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2776 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2777 }
2778
2779 void *r600_create_resolve_blend(struct r600_context *rctx)
2780 {
2781 struct pipe_blend_state blend;
2782 unsigned i;
2783
2784 memset(&blend, 0, sizeof(blend));
2785 blend.independent_blend_enable = true;
2786 for (i = 0; i < 2; i++) {
2787 blend.rt[i].colormask = 0xf;
2788 blend.rt[i].blend_enable = 1;
2789 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2790 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2791 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2792 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2793 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2794 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2795 }
2796 return r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2797 }
2798
2799 void *r700_create_resolve_blend(struct r600_context *rctx)
2800 {
2801 struct pipe_blend_state blend;
2802
2803 memset(&blend, 0, sizeof(blend));
2804 blend.independent_blend_enable = true;
2805 blend.rt[0].colormask = 0xf;
2806 return r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2807 }
2808
2809 void *r600_create_decompress_blend(struct r600_context *rctx)
2810 {
2811 struct pipe_blend_state blend;
2812
2813 memset(&blend, 0, sizeof(blend));
2814 blend.independent_blend_enable = true;
2815 blend.rt[0].colormask = 0xf;
2816 return r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2817 }
2818
2819 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2820 {
2821 struct pipe_depth_stencil_alpha_state dsa;
2822 boolean quirk = false;
2823
2824 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2825 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2826 quirk = true;
2827
2828 memset(&dsa, 0, sizeof(dsa));
2829
2830 if (quirk) {
2831 dsa.depth.enabled = 1;
2832 dsa.depth.func = PIPE_FUNC_LEQUAL;
2833 dsa.stencil[0].enabled = 1;
2834 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2835 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2836 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2837 dsa.stencil[0].writemask = 0xff;
2838 }
2839
2840 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2841 }
2842
2843 void r600_update_db_shader_control(struct r600_context * rctx)
2844 {
2845 bool dual_export = rctx->framebuffer.export_16bpc &&
2846 !rctx->ps_shader->current->ps_depth_export;
2847
2848 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2849 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2850
2851 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
2852 rctx->db_misc_state.db_shader_control = db_shader_control;
2853 rctx->db_misc_state.atom.dirty = true;
2854 }
2855 }