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r600g: init_flushed_depth_texture should be able to report errors
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600d.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31
32 static uint32_t r600_translate_blend_function(int blend_func)
33 {
34 switch (blend_func) {
35 case PIPE_BLEND_ADD:
36 return V_028804_COMB_DST_PLUS_SRC;
37 case PIPE_BLEND_SUBTRACT:
38 return V_028804_COMB_SRC_MINUS_DST;
39 case PIPE_BLEND_REVERSE_SUBTRACT:
40 return V_028804_COMB_DST_MINUS_SRC;
41 case PIPE_BLEND_MIN:
42 return V_028804_COMB_MIN_DST_SRC;
43 case PIPE_BLEND_MAX:
44 return V_028804_COMB_MAX_DST_SRC;
45 default:
46 R600_ERR("Unknown blend function %d\n", blend_func);
47 assert(0);
48 break;
49 }
50 return 0;
51 }
52
53 static uint32_t r600_translate_blend_factor(int blend_fact)
54 {
55 switch (blend_fact) {
56 case PIPE_BLENDFACTOR_ONE:
57 return V_028804_BLEND_ONE;
58 case PIPE_BLENDFACTOR_SRC_COLOR:
59 return V_028804_BLEND_SRC_COLOR;
60 case PIPE_BLENDFACTOR_SRC_ALPHA:
61 return V_028804_BLEND_SRC_ALPHA;
62 case PIPE_BLENDFACTOR_DST_ALPHA:
63 return V_028804_BLEND_DST_ALPHA;
64 case PIPE_BLENDFACTOR_DST_COLOR:
65 return V_028804_BLEND_DST_COLOR;
66 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
67 return V_028804_BLEND_SRC_ALPHA_SATURATE;
68 case PIPE_BLENDFACTOR_CONST_COLOR:
69 return V_028804_BLEND_CONST_COLOR;
70 case PIPE_BLENDFACTOR_CONST_ALPHA:
71 return V_028804_BLEND_CONST_ALPHA;
72 case PIPE_BLENDFACTOR_ZERO:
73 return V_028804_BLEND_ZERO;
74 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
75 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
76 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
77 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
78 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
79 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
80 case PIPE_BLENDFACTOR_INV_DST_COLOR:
81 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
82 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
83 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
84 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
85 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
86 case PIPE_BLENDFACTOR_SRC1_COLOR:
87 return V_028804_BLEND_SRC1_COLOR;
88 case PIPE_BLENDFACTOR_SRC1_ALPHA:
89 return V_028804_BLEND_SRC1_ALPHA;
90 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
91 return V_028804_BLEND_INV_SRC1_COLOR;
92 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
93 return V_028804_BLEND_INV_SRC1_ALPHA;
94 default:
95 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
96 assert(0);
97 break;
98 }
99 return 0;
100 }
101
102 static unsigned r600_tex_dim(unsigned dim)
103 {
104 switch (dim) {
105 default:
106 case PIPE_TEXTURE_1D:
107 return V_038000_SQ_TEX_DIM_1D;
108 case PIPE_TEXTURE_1D_ARRAY:
109 return V_038000_SQ_TEX_DIM_1D_ARRAY;
110 case PIPE_TEXTURE_2D:
111 case PIPE_TEXTURE_RECT:
112 return V_038000_SQ_TEX_DIM_2D;
113 case PIPE_TEXTURE_2D_ARRAY:
114 return V_038000_SQ_TEX_DIM_2D_ARRAY;
115 case PIPE_TEXTURE_3D:
116 return V_038000_SQ_TEX_DIM_3D;
117 case PIPE_TEXTURE_CUBE:
118 return V_038000_SQ_TEX_DIM_CUBEMAP;
119 }
120 }
121
122 static uint32_t r600_translate_dbformat(enum pipe_format format)
123 {
124 switch (format) {
125 case PIPE_FORMAT_Z16_UNORM:
126 return V_028010_DEPTH_16;
127 case PIPE_FORMAT_Z24X8_UNORM:
128 return V_028010_DEPTH_X8_24;
129 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
130 return V_028010_DEPTH_8_24;
131 case PIPE_FORMAT_Z32_FLOAT:
132 return V_028010_DEPTH_32_FLOAT;
133 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
134 return V_028010_DEPTH_X24_8_32_FLOAT;
135 default:
136 return ~0U;
137 }
138 }
139
140 static uint32_t r600_translate_colorswap(enum pipe_format format)
141 {
142 switch (format) {
143 /* 8-bit buffers. */
144 case PIPE_FORMAT_A8_UNORM:
145 case PIPE_FORMAT_A8_SNORM:
146 case PIPE_FORMAT_A8_UINT:
147 case PIPE_FORMAT_A8_SINT:
148 case PIPE_FORMAT_A16_UNORM:
149 case PIPE_FORMAT_A16_SNORM:
150 case PIPE_FORMAT_A16_UINT:
151 case PIPE_FORMAT_A16_SINT:
152 case PIPE_FORMAT_A16_FLOAT:
153 case PIPE_FORMAT_A32_UINT:
154 case PIPE_FORMAT_A32_SINT:
155 case PIPE_FORMAT_A32_FLOAT:
156 case PIPE_FORMAT_R4A4_UNORM:
157 return V_0280A0_SWAP_ALT_REV;
158 case PIPE_FORMAT_I8_UNORM:
159 case PIPE_FORMAT_I8_SNORM:
160 case PIPE_FORMAT_I8_UINT:
161 case PIPE_FORMAT_I8_SINT:
162 case PIPE_FORMAT_L8_UNORM:
163 case PIPE_FORMAT_L8_SNORM:
164 case PIPE_FORMAT_L8_UINT:
165 case PIPE_FORMAT_L8_SINT:
166 case PIPE_FORMAT_L8_SRGB:
167 case PIPE_FORMAT_L16_UNORM:
168 case PIPE_FORMAT_L16_SNORM:
169 case PIPE_FORMAT_L16_UINT:
170 case PIPE_FORMAT_L16_SINT:
171 case PIPE_FORMAT_L16_FLOAT:
172 case PIPE_FORMAT_L32_UINT:
173 case PIPE_FORMAT_L32_SINT:
174 case PIPE_FORMAT_L32_FLOAT:
175 case PIPE_FORMAT_I16_UNORM:
176 case PIPE_FORMAT_I16_SNORM:
177 case PIPE_FORMAT_I16_UINT:
178 case PIPE_FORMAT_I16_SINT:
179 case PIPE_FORMAT_I16_FLOAT:
180 case PIPE_FORMAT_I32_UINT:
181 case PIPE_FORMAT_I32_SINT:
182 case PIPE_FORMAT_I32_FLOAT:
183 case PIPE_FORMAT_R8_UNORM:
184 case PIPE_FORMAT_R8_SNORM:
185 case PIPE_FORMAT_R8_UINT:
186 case PIPE_FORMAT_R8_SINT:
187 return V_0280A0_SWAP_STD;
188
189 case PIPE_FORMAT_L4A4_UNORM:
190 case PIPE_FORMAT_A4R4_UNORM:
191 return V_0280A0_SWAP_ALT;
192
193 /* 16-bit buffers. */
194 case PIPE_FORMAT_B5G6R5_UNORM:
195 return V_0280A0_SWAP_STD_REV;
196
197 case PIPE_FORMAT_B5G5R5A1_UNORM:
198 case PIPE_FORMAT_B5G5R5X1_UNORM:
199 return V_0280A0_SWAP_ALT;
200
201 case PIPE_FORMAT_B4G4R4A4_UNORM:
202 case PIPE_FORMAT_B4G4R4X4_UNORM:
203 return V_0280A0_SWAP_ALT;
204
205 case PIPE_FORMAT_Z16_UNORM:
206 return V_0280A0_SWAP_STD;
207
208 case PIPE_FORMAT_L8A8_UNORM:
209 case PIPE_FORMAT_L8A8_SNORM:
210 case PIPE_FORMAT_L8A8_UINT:
211 case PIPE_FORMAT_L8A8_SINT:
212 case PIPE_FORMAT_L8A8_SRGB:
213 case PIPE_FORMAT_L16A16_UNORM:
214 case PIPE_FORMAT_L16A16_SNORM:
215 case PIPE_FORMAT_L16A16_UINT:
216 case PIPE_FORMAT_L16A16_SINT:
217 case PIPE_FORMAT_L16A16_FLOAT:
218 case PIPE_FORMAT_L32A32_UINT:
219 case PIPE_FORMAT_L32A32_SINT:
220 case PIPE_FORMAT_L32A32_FLOAT:
221 return V_0280A0_SWAP_ALT;
222 case PIPE_FORMAT_R8G8_UNORM:
223 case PIPE_FORMAT_R8G8_SNORM:
224 case PIPE_FORMAT_R8G8_UINT:
225 case PIPE_FORMAT_R8G8_SINT:
226 return V_0280A0_SWAP_STD;
227
228 case PIPE_FORMAT_R16_UNORM:
229 case PIPE_FORMAT_R16_SNORM:
230 case PIPE_FORMAT_R16_UINT:
231 case PIPE_FORMAT_R16_SINT:
232 case PIPE_FORMAT_R16_FLOAT:
233 return V_0280A0_SWAP_STD;
234
235 /* 32-bit buffers. */
236
237 case PIPE_FORMAT_A8B8G8R8_SRGB:
238 return V_0280A0_SWAP_STD_REV;
239 case PIPE_FORMAT_B8G8R8A8_SRGB:
240 return V_0280A0_SWAP_ALT;
241
242 case PIPE_FORMAT_B8G8R8A8_UNORM:
243 case PIPE_FORMAT_B8G8R8X8_UNORM:
244 return V_0280A0_SWAP_ALT;
245
246 case PIPE_FORMAT_A8R8G8B8_UNORM:
247 case PIPE_FORMAT_X8R8G8B8_UNORM:
248 return V_0280A0_SWAP_ALT_REV;
249 case PIPE_FORMAT_R8G8B8A8_SNORM:
250 case PIPE_FORMAT_R8G8B8A8_UNORM:
251 case PIPE_FORMAT_R8G8B8X8_UNORM:
252 case PIPE_FORMAT_R8G8B8A8_SINT:
253 case PIPE_FORMAT_R8G8B8A8_UINT:
254 return V_0280A0_SWAP_STD;
255
256 case PIPE_FORMAT_A8B8G8R8_UNORM:
257 case PIPE_FORMAT_X8B8G8R8_UNORM:
258 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
259 return V_0280A0_SWAP_STD_REV;
260
261 case PIPE_FORMAT_Z24X8_UNORM:
262 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
263 return V_0280A0_SWAP_STD;
264
265 case PIPE_FORMAT_X8Z24_UNORM:
266 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
267 return V_0280A0_SWAP_STD;
268
269 case PIPE_FORMAT_R10G10B10A2_UNORM:
270 case PIPE_FORMAT_R10G10B10X2_SNORM:
271 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
272 return V_0280A0_SWAP_STD;
273
274 case PIPE_FORMAT_B10G10R10A2_UNORM:
275 case PIPE_FORMAT_B10G10R10A2_UINT:
276 return V_0280A0_SWAP_ALT;
277
278 case PIPE_FORMAT_R11G11B10_FLOAT:
279 case PIPE_FORMAT_R16G16_UNORM:
280 case PIPE_FORMAT_R16G16_SNORM:
281 case PIPE_FORMAT_R16G16_FLOAT:
282 case PIPE_FORMAT_R16G16_UINT:
283 case PIPE_FORMAT_R16G16_SINT:
284 case PIPE_FORMAT_R16G16B16_FLOAT:
285 case PIPE_FORMAT_R32G32B32_FLOAT:
286 case PIPE_FORMAT_R32_UINT:
287 case PIPE_FORMAT_R32_SINT:
288 case PIPE_FORMAT_R32_FLOAT:
289 case PIPE_FORMAT_Z32_FLOAT:
290 return V_0280A0_SWAP_STD;
291
292 /* 64-bit buffers. */
293 case PIPE_FORMAT_R32G32_FLOAT:
294 case PIPE_FORMAT_R32G32_UINT:
295 case PIPE_FORMAT_R32G32_SINT:
296 case PIPE_FORMAT_R16G16B16A16_UNORM:
297 case PIPE_FORMAT_R16G16B16A16_SNORM:
298 case PIPE_FORMAT_R16G16B16A16_UINT:
299 case PIPE_FORMAT_R16G16B16A16_SINT:
300 case PIPE_FORMAT_R16G16B16A16_FLOAT:
301 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
302
303 /* 128-bit buffers. */
304 case PIPE_FORMAT_R32G32B32A32_FLOAT:
305 case PIPE_FORMAT_R32G32B32A32_SNORM:
306 case PIPE_FORMAT_R32G32B32A32_UNORM:
307 case PIPE_FORMAT_R32G32B32A32_SINT:
308 case PIPE_FORMAT_R32G32B32A32_UINT:
309 return V_0280A0_SWAP_STD;
310 default:
311 R600_ERR("unsupported colorswap format %d\n", format);
312 return ~0U;
313 }
314 return ~0U;
315 }
316
317 static uint32_t r600_translate_colorformat(enum pipe_format format)
318 {
319 switch (format) {
320 case PIPE_FORMAT_L4A4_UNORM:
321 case PIPE_FORMAT_R4A4_UNORM:
322 case PIPE_FORMAT_A4R4_UNORM:
323 return V_0280A0_COLOR_4_4;
324
325 /* 8-bit buffers. */
326 case PIPE_FORMAT_A8_UNORM:
327 case PIPE_FORMAT_A8_SNORM:
328 case PIPE_FORMAT_A8_UINT:
329 case PIPE_FORMAT_A8_SINT:
330 case PIPE_FORMAT_I8_UNORM:
331 case PIPE_FORMAT_I8_SNORM:
332 case PIPE_FORMAT_I8_UINT:
333 case PIPE_FORMAT_I8_SINT:
334 case PIPE_FORMAT_L8_UNORM:
335 case PIPE_FORMAT_L8_SNORM:
336 case PIPE_FORMAT_L8_UINT:
337 case PIPE_FORMAT_L8_SINT:
338 case PIPE_FORMAT_L8_SRGB:
339 case PIPE_FORMAT_R8_UNORM:
340 case PIPE_FORMAT_R8_SNORM:
341 case PIPE_FORMAT_R8_UINT:
342 case PIPE_FORMAT_R8_SINT:
343 return V_0280A0_COLOR_8;
344
345 /* 16-bit buffers. */
346 case PIPE_FORMAT_B5G6R5_UNORM:
347 return V_0280A0_COLOR_5_6_5;
348
349 case PIPE_FORMAT_B5G5R5A1_UNORM:
350 case PIPE_FORMAT_B5G5R5X1_UNORM:
351 return V_0280A0_COLOR_1_5_5_5;
352
353 case PIPE_FORMAT_B4G4R4A4_UNORM:
354 case PIPE_FORMAT_B4G4R4X4_UNORM:
355 return V_0280A0_COLOR_4_4_4_4;
356
357 case PIPE_FORMAT_Z16_UNORM:
358 return V_0280A0_COLOR_16;
359
360 case PIPE_FORMAT_L8A8_UNORM:
361 case PIPE_FORMAT_L8A8_SNORM:
362 case PIPE_FORMAT_L8A8_UINT:
363 case PIPE_FORMAT_L8A8_SINT:
364 case PIPE_FORMAT_L8A8_SRGB:
365 case PIPE_FORMAT_R8G8_UNORM:
366 case PIPE_FORMAT_R8G8_SNORM:
367 case PIPE_FORMAT_R8G8_UINT:
368 case PIPE_FORMAT_R8G8_SINT:
369 return V_0280A0_COLOR_8_8;
370
371 case PIPE_FORMAT_R16_UNORM:
372 case PIPE_FORMAT_R16_SNORM:
373 case PIPE_FORMAT_R16_UINT:
374 case PIPE_FORMAT_R16_SINT:
375 case PIPE_FORMAT_A16_UNORM:
376 case PIPE_FORMAT_A16_SNORM:
377 case PIPE_FORMAT_A16_UINT:
378 case PIPE_FORMAT_A16_SINT:
379 case PIPE_FORMAT_L16_UNORM:
380 case PIPE_FORMAT_L16_SNORM:
381 case PIPE_FORMAT_L16_UINT:
382 case PIPE_FORMAT_L16_SINT:
383 case PIPE_FORMAT_I16_UNORM:
384 case PIPE_FORMAT_I16_SNORM:
385 case PIPE_FORMAT_I16_UINT:
386 case PIPE_FORMAT_I16_SINT:
387 return V_0280A0_COLOR_16;
388
389 case PIPE_FORMAT_R16_FLOAT:
390 case PIPE_FORMAT_A16_FLOAT:
391 case PIPE_FORMAT_L16_FLOAT:
392 case PIPE_FORMAT_I16_FLOAT:
393 return V_0280A0_COLOR_16_FLOAT;
394
395 /* 32-bit buffers. */
396 case PIPE_FORMAT_A8B8G8R8_SRGB:
397 case PIPE_FORMAT_A8B8G8R8_UNORM:
398 case PIPE_FORMAT_A8R8G8B8_UNORM:
399 case PIPE_FORMAT_B8G8R8A8_SRGB:
400 case PIPE_FORMAT_B8G8R8A8_UNORM:
401 case PIPE_FORMAT_B8G8R8X8_UNORM:
402 case PIPE_FORMAT_R8G8B8A8_SNORM:
403 case PIPE_FORMAT_R8G8B8A8_UNORM:
404 case PIPE_FORMAT_R8G8B8X8_UNORM:
405 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
406 case PIPE_FORMAT_X8B8G8R8_UNORM:
407 case PIPE_FORMAT_X8R8G8B8_UNORM:
408 case PIPE_FORMAT_R8G8B8_UNORM:
409 case PIPE_FORMAT_R8G8B8A8_SINT:
410 case PIPE_FORMAT_R8G8B8A8_UINT:
411 return V_0280A0_COLOR_8_8_8_8;
412
413 case PIPE_FORMAT_R10G10B10A2_UNORM:
414 case PIPE_FORMAT_R10G10B10X2_SNORM:
415 case PIPE_FORMAT_B10G10R10A2_UNORM:
416 case PIPE_FORMAT_B10G10R10A2_UINT:
417 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
418 return V_0280A0_COLOR_2_10_10_10;
419
420 case PIPE_FORMAT_Z24X8_UNORM:
421 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
422 return V_0280A0_COLOR_8_24;
423
424 case PIPE_FORMAT_X8Z24_UNORM:
425 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
426 return V_0280A0_COLOR_24_8;
427
428 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
429 return V_0280A0_COLOR_X24_8_32_FLOAT;
430
431 case PIPE_FORMAT_R32_UINT:
432 case PIPE_FORMAT_R32_SINT:
433 case PIPE_FORMAT_A32_UINT:
434 case PIPE_FORMAT_A32_SINT:
435 case PIPE_FORMAT_L32_UINT:
436 case PIPE_FORMAT_L32_SINT:
437 case PIPE_FORMAT_I32_UINT:
438 case PIPE_FORMAT_I32_SINT:
439 return V_0280A0_COLOR_32;
440
441 case PIPE_FORMAT_R32_FLOAT:
442 case PIPE_FORMAT_A32_FLOAT:
443 case PIPE_FORMAT_L32_FLOAT:
444 case PIPE_FORMAT_I32_FLOAT:
445 case PIPE_FORMAT_Z32_FLOAT:
446 return V_0280A0_COLOR_32_FLOAT;
447
448 case PIPE_FORMAT_R16G16_FLOAT:
449 case PIPE_FORMAT_L16A16_FLOAT:
450 return V_0280A0_COLOR_16_16_FLOAT;
451
452 case PIPE_FORMAT_R16G16_UNORM:
453 case PIPE_FORMAT_R16G16_SNORM:
454 case PIPE_FORMAT_R16G16_UINT:
455 case PIPE_FORMAT_R16G16_SINT:
456 case PIPE_FORMAT_L16A16_UNORM:
457 case PIPE_FORMAT_L16A16_SNORM:
458 case PIPE_FORMAT_L16A16_UINT:
459 case PIPE_FORMAT_L16A16_SINT:
460 return V_0280A0_COLOR_16_16;
461
462 case PIPE_FORMAT_R11G11B10_FLOAT:
463 return V_0280A0_COLOR_10_11_11_FLOAT;
464
465 /* 64-bit buffers. */
466 case PIPE_FORMAT_R16G16B16A16_UINT:
467 case PIPE_FORMAT_R16G16B16A16_SINT:
468 case PIPE_FORMAT_R16G16B16A16_UNORM:
469 case PIPE_FORMAT_R16G16B16A16_SNORM:
470 return V_0280A0_COLOR_16_16_16_16;
471
472 case PIPE_FORMAT_R16G16B16_FLOAT:
473 case PIPE_FORMAT_R16G16B16A16_FLOAT:
474 return V_0280A0_COLOR_16_16_16_16_FLOAT;
475
476 case PIPE_FORMAT_R32G32_FLOAT:
477 case PIPE_FORMAT_L32A32_FLOAT:
478 return V_0280A0_COLOR_32_32_FLOAT;
479
480 case PIPE_FORMAT_R32G32_SINT:
481 case PIPE_FORMAT_R32G32_UINT:
482 case PIPE_FORMAT_L32A32_UINT:
483 case PIPE_FORMAT_L32A32_SINT:
484 return V_0280A0_COLOR_32_32;
485
486 /* 96-bit buffers. */
487 case PIPE_FORMAT_R32G32B32_FLOAT:
488 return V_0280A0_COLOR_32_32_32_FLOAT;
489
490 /* 128-bit buffers. */
491 case PIPE_FORMAT_R32G32B32A32_FLOAT:
492 return V_0280A0_COLOR_32_32_32_32_FLOAT;
493 case PIPE_FORMAT_R32G32B32A32_SNORM:
494 case PIPE_FORMAT_R32G32B32A32_UNORM:
495 case PIPE_FORMAT_R32G32B32A32_SINT:
496 case PIPE_FORMAT_R32G32B32A32_UINT:
497 return V_0280A0_COLOR_32_32_32_32;
498
499 /* YUV buffers. */
500 case PIPE_FORMAT_UYVY:
501 case PIPE_FORMAT_YUYV:
502 default:
503 return ~0U; /* Unsupported. */
504 }
505 }
506
507 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
508 {
509 if (R600_BIG_ENDIAN) {
510 switch(colorformat) {
511 case V_0280A0_COLOR_4_4:
512 return ENDIAN_NONE;
513
514 /* 8-bit buffers. */
515 case V_0280A0_COLOR_8:
516 return ENDIAN_NONE;
517
518 /* 16-bit buffers. */
519 case V_0280A0_COLOR_5_6_5:
520 case V_0280A0_COLOR_1_5_5_5:
521 case V_0280A0_COLOR_4_4_4_4:
522 case V_0280A0_COLOR_16:
523 case V_0280A0_COLOR_8_8:
524 return ENDIAN_8IN16;
525
526 /* 32-bit buffers. */
527 case V_0280A0_COLOR_8_8_8_8:
528 case V_0280A0_COLOR_2_10_10_10:
529 case V_0280A0_COLOR_8_24:
530 case V_0280A0_COLOR_24_8:
531 case V_0280A0_COLOR_32_FLOAT:
532 case V_0280A0_COLOR_16_16_FLOAT:
533 case V_0280A0_COLOR_16_16:
534 return ENDIAN_8IN32;
535
536 /* 64-bit buffers. */
537 case V_0280A0_COLOR_16_16_16_16:
538 case V_0280A0_COLOR_16_16_16_16_FLOAT:
539 return ENDIAN_8IN16;
540
541 case V_0280A0_COLOR_32_32_FLOAT:
542 case V_0280A0_COLOR_32_32:
543 case V_0280A0_COLOR_X24_8_32_FLOAT:
544 return ENDIAN_8IN32;
545
546 /* 128-bit buffers. */
547 case V_0280A0_COLOR_32_32_32_FLOAT:
548 case V_0280A0_COLOR_32_32_32_32_FLOAT:
549 case V_0280A0_COLOR_32_32_32_32:
550 return ENDIAN_8IN32;
551 default:
552 return ENDIAN_NONE; /* Unsupported. */
553 }
554 } else {
555 return ENDIAN_NONE;
556 }
557 }
558
559 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
560 {
561 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
562 }
563
564 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
565 {
566 return r600_translate_colorformat(format) != ~0U &&
567 r600_translate_colorswap(format) != ~0U;
568 }
569
570 static bool r600_is_zs_format_supported(enum pipe_format format)
571 {
572 return r600_translate_dbformat(format) != ~0U;
573 }
574
575 boolean r600_is_format_supported(struct pipe_screen *screen,
576 enum pipe_format format,
577 enum pipe_texture_target target,
578 unsigned sample_count,
579 unsigned usage)
580 {
581 unsigned retval = 0;
582
583 if (target >= PIPE_MAX_TEXTURE_TYPES) {
584 R600_ERR("r600: unsupported texture type %d\n", target);
585 return FALSE;
586 }
587
588 if (!util_format_is_supported(format, usage))
589 return FALSE;
590
591 /* Multisample */
592 if (sample_count > 1)
593 return FALSE;
594
595 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
596 r600_is_sampler_format_supported(screen, format)) {
597 retval |= PIPE_BIND_SAMPLER_VIEW;
598 }
599
600 if ((usage & (PIPE_BIND_RENDER_TARGET |
601 PIPE_BIND_DISPLAY_TARGET |
602 PIPE_BIND_SCANOUT |
603 PIPE_BIND_SHARED)) &&
604 r600_is_colorbuffer_format_supported(format)) {
605 retval |= usage &
606 (PIPE_BIND_RENDER_TARGET |
607 PIPE_BIND_DISPLAY_TARGET |
608 PIPE_BIND_SCANOUT |
609 PIPE_BIND_SHARED);
610 }
611
612 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
613 r600_is_zs_format_supported(format)) {
614 retval |= PIPE_BIND_DEPTH_STENCIL;
615 }
616
617 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
618 r600_is_vertex_format_supported(format)) {
619 retval |= PIPE_BIND_VERTEX_BUFFER;
620 }
621
622 if (usage & PIPE_BIND_TRANSFER_READ)
623 retval |= PIPE_BIND_TRANSFER_READ;
624 if (usage & PIPE_BIND_TRANSFER_WRITE)
625 retval |= PIPE_BIND_TRANSFER_WRITE;
626
627 return retval == usage;
628 }
629
630 void r600_polygon_offset_update(struct r600_context *rctx)
631 {
632 struct r600_pipe_state state;
633
634 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
635 state.nregs = 0;
636 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
637 float offset_units = rctx->rasterizer->offset_units;
638 unsigned offset_db_fmt_cntl = 0, depth;
639
640 switch (rctx->framebuffer.zsbuf->format) {
641 case PIPE_FORMAT_Z24X8_UNORM:
642 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
643 depth = -24;
644 offset_units *= 2.0f;
645 break;
646 case PIPE_FORMAT_Z32_FLOAT:
647 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
648 depth = -23;
649 offset_units *= 1.0f;
650 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
651 break;
652 case PIPE_FORMAT_Z16_UNORM:
653 depth = -16;
654 offset_units *= 4.0f;
655 break;
656 default:
657 return;
658 }
659 /* XXX some of those reg can be computed with cso */
660 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
661 r600_pipe_state_add_reg(&state,
662 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
663 fui(rctx->rasterizer->offset_scale));
664 r600_pipe_state_add_reg(&state,
665 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
666 fui(offset_units));
667 r600_pipe_state_add_reg(&state,
668 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
669 fui(rctx->rasterizer->offset_scale));
670 r600_pipe_state_add_reg(&state,
671 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
672 fui(offset_units));
673 r600_pipe_state_add_reg(&state,
674 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
675 offset_db_fmt_cntl);
676 r600_context_pipe_state_set(rctx, &state);
677 }
678 }
679
680 static void *r600_create_blend_state(struct pipe_context *ctx,
681 const struct pipe_blend_state *state)
682 {
683 struct r600_context *rctx = (struct r600_context *)ctx;
684 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
685 struct r600_pipe_state *rstate;
686 uint32_t color_control = 0, target_mask;
687
688 if (blend == NULL) {
689 return NULL;
690 }
691 rstate = &blend->rstate;
692
693 rstate->id = R600_PIPE_STATE_BLEND;
694
695 target_mask = 0;
696
697 /* R600 does not support per-MRT blends */
698 if (rctx->family > CHIP_R600)
699 color_control |= S_028808_PER_MRT_BLEND(1);
700 if (state->logicop_enable) {
701 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
702 } else {
703 color_control |= (0xcc << 16);
704 }
705 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
706 if (state->independent_blend_enable) {
707 for (int i = 0; i < 8; i++) {
708 if (state->rt[i].blend_enable) {
709 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
710 }
711 target_mask |= (state->rt[i].colormask << (4 * i));
712 }
713 } else {
714 for (int i = 0; i < 8; i++) {
715 if (state->rt[0].blend_enable) {
716 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
717 }
718 target_mask |= (state->rt[0].colormask << (4 * i));
719 }
720 }
721
722 if (target_mask)
723 color_control |= S_028808_SPECIAL_OP(V_028808_NORMAL);
724 else
725 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
726
727 blend->cb_target_mask = target_mask;
728 blend->cb_color_control = color_control;
729 /* only MRT0 has dual src blend */
730 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
731 for (int i = 0; i < 8; i++) {
732 /* state->rt entries > 0 only written if independent blending */
733 const int j = state->independent_blend_enable ? i : 0;
734
735 unsigned eqRGB = state->rt[j].rgb_func;
736 unsigned srcRGB = state->rt[j].rgb_src_factor;
737 unsigned dstRGB = state->rt[j].rgb_dst_factor;
738
739 unsigned eqA = state->rt[j].alpha_func;
740 unsigned srcA = state->rt[j].alpha_src_factor;
741 unsigned dstA = state->rt[j].alpha_dst_factor;
742 uint32_t bc = 0;
743
744 if (!state->rt[j].blend_enable)
745 continue;
746
747 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
748 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
749 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
750
751 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
752 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
753 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
754 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
755 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
756 }
757
758 /* R600 does not support per-MRT blends */
759 if (rctx->family > CHIP_R600)
760 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc);
761 if (i == 0)
762 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc);
763 }
764 return rstate;
765 }
766
767 static void *r600_create_dsa_state(struct pipe_context *ctx,
768 const struct pipe_depth_stencil_alpha_state *state)
769 {
770 struct r600_context *rctx = (struct r600_context *)ctx;
771 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
772 unsigned db_depth_control, alpha_test_control, alpha_ref;
773 struct r600_pipe_state *rstate;
774
775 if (dsa == NULL) {
776 return NULL;
777 }
778
779 dsa->valuemask[0] = state->stencil[0].valuemask;
780 dsa->valuemask[1] = state->stencil[1].valuemask;
781 dsa->writemask[0] = state->stencil[0].writemask;
782 dsa->writemask[1] = state->stencil[1].writemask;
783
784 rstate = &dsa->rstate;
785
786 rstate->id = R600_PIPE_STATE_DSA;
787 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
788 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
789 S_028800_ZFUNC(state->depth.func);
790
791 /* stencil */
792 if (state->stencil[0].enabled) {
793 db_depth_control |= S_028800_STENCIL_ENABLE(1);
794 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
795 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
796 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
797 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
798
799 if (state->stencil[1].enabled) {
800 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
801 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
802 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
803 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
804 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
805 }
806 }
807
808 /* alpha */
809 alpha_test_control = 0;
810 alpha_ref = 0;
811 if (state->alpha.enabled) {
812 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
813 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
814 alpha_ref = fui(state->alpha.ref_value);
815 }
816 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
817 dsa->alpha_ref = alpha_ref;
818
819 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
820 return rstate;
821 }
822
823 static void *r600_create_rs_state(struct pipe_context *ctx,
824 const struct pipe_rasterizer_state *state)
825 {
826 struct r600_context *rctx = (struct r600_context *)ctx;
827 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
828 struct r600_pipe_state *rstate;
829 unsigned tmp;
830 unsigned prov_vtx = 1, polygon_dual_mode;
831 unsigned sc_mode_cntl;
832 float psize_min, psize_max;
833
834 if (rs == NULL) {
835 return NULL;
836 }
837
838 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
839 state->fill_back != PIPE_POLYGON_MODE_FILL);
840
841 if (state->flatshade_first)
842 prov_vtx = 0;
843
844 rstate = &rs->rstate;
845 rs->flatshade = state->flatshade;
846 rs->sprite_coord_enable = state->sprite_coord_enable;
847 rs->two_side = state->light_twoside;
848 rs->clip_plane_enable = state->clip_plane_enable;
849 rs->pa_sc_line_stipple = state->line_stipple_enable ?
850 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
851 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
852 rs->pa_cl_clip_cntl =
853 S_028810_PS_UCP_MODE(3) |
854 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
855 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
856 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
857
858 /* offset */
859 rs->offset_units = state->offset_units;
860 rs->offset_scale = state->offset_scale * 12.0f;
861
862 rstate->id = R600_PIPE_STATE_RASTERIZER;
863 tmp = S_0286D4_FLAT_SHADE_ENA(1);
864 if (state->sprite_coord_enable) {
865 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
866 S_0286D4_PNT_SPRITE_OVRD_X(2) |
867 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
868 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
869 S_0286D4_PNT_SPRITE_OVRD_W(1);
870 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
871 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
872 }
873 }
874 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
875
876 /* point size 12.4 fixed point */
877 tmp = r600_pack_float_12p4(state->point_size/2);
878 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
879
880 if (state->point_size_per_vertex) {
881 psize_min = util_get_min_point_size(state);
882 psize_max = 8192;
883 } else {
884 /* Force the point size to be as if the vertex output was disabled. */
885 psize_min = state->point_size;
886 psize_max = state->point_size;
887 }
888 /* Divide by two, because 0.5 = 1 pixel. */
889 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
890 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
891 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
892
893 tmp = r600_pack_float_12p4(state->line_width/2);
894 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
895
896 if (rctx->chip_class >= R700) {
897 sc_mode_cntl =
898 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
899 S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
900 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
901 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
902 } else {
903 sc_mode_cntl =
904 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
905 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
906 rs->scissor_enable = state->scissor;
907 }
908 sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
909
910 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
911
912 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
913 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
914
915 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
916 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
917 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
918 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
919 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
920 S_028814_FACE(!state->front_ccw) |
921 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
922 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
923 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
924 S_028814_POLY_MODE(polygon_dual_mode) |
925 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
926 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
927 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
928 return rstate;
929 }
930
931 static void *r600_create_sampler_state(struct pipe_context *ctx,
932 const struct pipe_sampler_state *state)
933 {
934 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
935 struct r600_pipe_state *rstate;
936 union util_color uc;
937 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
938
939 if (ss == NULL) {
940 return NULL;
941 }
942
943 ss->seamless_cube_map = state->seamless_cube_map;
944 rstate = &ss->rstate;
945 rstate->id = R600_PIPE_STATE_SAMPLER;
946 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
947 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
948 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
949 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
950 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
951 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
952 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
953 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
954 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
955 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
956 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
957 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
958 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
959 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
960 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), NULL, 0);
961 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), NULL, 0);
962 if (uc.ui) {
963 r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
964 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
965 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
966 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
967 }
968 return rstate;
969 }
970
971 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
972 struct pipe_resource *texture,
973 const struct pipe_sampler_view *state)
974 {
975 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
976 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
977 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
978 unsigned format, endian;
979 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
980 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
981 unsigned width, height, depth, offset_level, last_level;
982
983 if (view == NULL)
984 return NULL;
985
986 /* initialize base object */
987 view->base = *state;
988 view->base.texture = NULL;
989 pipe_reference(NULL, &texture->reference);
990 view->base.texture = texture;
991 view->base.reference.count = 1;
992 view->base.context = ctx;
993
994 swizzle[0] = state->swizzle_r;
995 swizzle[1] = state->swizzle_g;
996 swizzle[2] = state->swizzle_b;
997 swizzle[3] = state->swizzle_a;
998
999 format = r600_translate_texformat(ctx->screen, state->format,
1000 swizzle,
1001 &word4, &yuv_format);
1002 assert(format != ~0);
1003 if (format == ~0) {
1004 FREE(view);
1005 return NULL;
1006 }
1007
1008 if (tmp->is_depth && !tmp->is_flushing_texture) {
1009 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1010 FREE(view);
1011 return NULL;
1012 }
1013 tmp = tmp->flushed_depth_texture;
1014 }
1015
1016 endian = r600_colorformat_endian_swap(format);
1017
1018 offset_level = state->u.tex.first_level;
1019 last_level = state->u.tex.last_level - offset_level;
1020 if (!rscreen->use_surface_alloc) {
1021 width = u_minify(texture->width0, offset_level);
1022 height = u_minify(texture->height0, offset_level);
1023 depth = u_minify(texture->depth0, offset_level);
1024
1025 pitch = align(tmp->pitch_in_blocks[offset_level] *
1026 util_format_get_blockwidth(state->format), 8);
1027 array_mode = tmp->array_mode[offset_level];
1028 tile_type = tmp->tile_type;
1029
1030 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1031 height = 1;
1032 depth = texture->array_size;
1033 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1034 depth = texture->array_size;
1035 }
1036
1037 view->tex_resource = &tmp->resource;
1038 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1039 S_038000_TILE_MODE(array_mode) |
1040 S_038000_TILE_TYPE(tile_type) |
1041 S_038000_PITCH((pitch / 8) - 1) |
1042 S_038000_TEX_WIDTH(width - 1));
1043 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
1044 S_038004_TEX_DEPTH(depth - 1) |
1045 S_038004_DATA_FORMAT(format));
1046 view->tex_resource_words[2] = tmp->offset[offset_level] >> 8;
1047 view->tex_resource_words[3] = tmp->offset[offset_level+1] >> 8;
1048 view->tex_resource_words[4] = (word4 |
1049 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1050 S_038010_REQUEST_SIZE(1) |
1051 S_038010_ENDIAN_SWAP(endian) |
1052 S_038010_BASE_LEVEL(0));
1053 view->tex_resource_words[5] = (S_038014_LAST_LEVEL(last_level) |
1054 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1055 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1056 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1057 S_038018_MAX_ANISO(4 /* max 16 samples */));
1058 } else {
1059 width = tmp->surface.level[offset_level].npix_x;
1060 height = tmp->surface.level[offset_level].npix_y;
1061 depth = tmp->surface.level[offset_level].npix_z;
1062 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1063 tile_type = tmp->tile_type;
1064
1065 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1066 height = 1;
1067 depth = texture->array_size;
1068 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1069 depth = texture->array_size;
1070 }
1071 switch (tmp->surface.level[offset_level].mode) {
1072 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1073 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1074 break;
1075 case RADEON_SURF_MODE_1D:
1076 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1077 break;
1078 case RADEON_SURF_MODE_2D:
1079 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1080 break;
1081 case RADEON_SURF_MODE_LINEAR:
1082 default:
1083 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1084 break;
1085 }
1086
1087 view->tex_resource = &tmp->resource;
1088 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1089 S_038000_TILE_MODE(array_mode) |
1090 S_038000_TILE_TYPE(tile_type) |
1091 S_038000_PITCH((pitch / 8) - 1) |
1092 S_038000_TEX_WIDTH(width - 1));
1093 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
1094 S_038004_TEX_DEPTH(depth - 1) |
1095 S_038004_DATA_FORMAT(format));
1096 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
1097 if (offset_level >= tmp->surface.last_level) {
1098 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
1099 } else {
1100 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1101 }
1102 view->tex_resource_words[4] = (word4 |
1103 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1104 S_038010_REQUEST_SIZE(1) |
1105 S_038010_ENDIAN_SWAP(endian) |
1106 S_038010_BASE_LEVEL(0));
1107 view->tex_resource_words[5] = (S_038014_LAST_LEVEL(last_level) |
1108 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1109 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1110 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1111 S_038018_MAX_ANISO(4 /* max 16 samples */));
1112 }
1113 return &view->base;
1114 }
1115
1116 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1117 struct pipe_sampler_view **views)
1118 {
1119 struct r600_context *rctx = (struct r600_context *)ctx;
1120 r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views);
1121 }
1122
1123 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1124 struct pipe_sampler_view **views)
1125 {
1126 struct r600_context *rctx = (struct r600_context *)ctx;
1127 r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views);
1128 }
1129
1130 static void r600_set_seamless_cubemap(struct r600_context *rctx, boolean enable)
1131 {
1132 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1133 if (rstate == NULL)
1134 return;
1135
1136 rstate->id = R600_PIPE_STATE_SEAMLESS_CUBEMAP;
1137 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1138 (enable ? 0 : S_009508_DISABLE_CUBE_WRAP(1)) |
1139 S_009508_DISABLE_CUBE_ANISO(1) |
1140 S_009508_SYNC_GRADIENT(1) |
1141 S_009508_SYNC_WALKER(1) |
1142 S_009508_SYNC_ALIGNER(1));
1143
1144 free(rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP]);
1145 rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP] = rstate;
1146 r600_context_pipe_state_set(rctx, rstate);
1147 }
1148
1149 static void r600_bind_samplers(struct r600_context *rctx,
1150 struct r600_textures_info *dst,
1151 unsigned count, void **states)
1152 {
1153 memcpy(dst->samplers, states, sizeof(void*) * count);
1154 dst->n_samplers = count;
1155 dst->samplers_dirty = true;
1156 }
1157
1158 static void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states)
1159 {
1160 struct r600_context *rctx = (struct r600_context *)ctx;
1161 r600_bind_samplers(rctx, &rctx->vs_samplers, count, states);
1162 }
1163
1164 static void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states)
1165 {
1166 struct r600_context *rctx = (struct r600_context *)ctx;
1167 r600_bind_samplers(rctx, &rctx->ps_samplers, count, states);
1168 }
1169
1170 static void r600_update_samplers(struct r600_context *rctx,
1171 struct r600_textures_info *tex,
1172 void (*set_sampler)(struct r600_context*, struct r600_pipe_state*, unsigned))
1173 {
1174 unsigned i;
1175
1176 if (tex->samplers_dirty) {
1177 int seamless = -1;
1178 for (i = 0; i < tex->n_samplers; i++) {
1179 if (!tex->samplers[i])
1180 continue;
1181
1182 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1183 * filtering between layers.
1184 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. */
1185 if (tex->views.views[i]) {
1186 if (tex->views.views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1187 tex->views.views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
1188 tex->samplers[i]->rstate.regs[0].value |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1189 tex->is_array_sampler[i] = true;
1190 } else {
1191 tex->samplers[i]->rstate.regs[0].value &= C_03C000_TEX_ARRAY_OVERRIDE;
1192 tex->is_array_sampler[i] = false;
1193 }
1194 }
1195
1196 set_sampler(rctx, &tex->samplers[i]->rstate, i);
1197
1198 if (tex->samplers[i])
1199 seamless = tex->samplers[i]->seamless_cube_map;
1200 }
1201
1202 if (seamless != -1)
1203 r600_set_seamless_cubemap(rctx, seamless);
1204
1205 tex->samplers_dirty = false;
1206 }
1207 }
1208
1209 void r600_update_sampler_states(struct r600_context *rctx)
1210 {
1211 r600_update_samplers(rctx, &rctx->vs_samplers,
1212 r600_context_pipe_state_set_vs_sampler);
1213 r600_update_samplers(rctx, &rctx->ps_samplers,
1214 r600_context_pipe_state_set_ps_sampler);
1215 }
1216
1217 static void r600_set_clip_state(struct pipe_context *ctx,
1218 const struct pipe_clip_state *state)
1219 {
1220 struct r600_context *rctx = (struct r600_context *)ctx;
1221 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1222 struct pipe_constant_buffer cb;
1223
1224 if (rstate == NULL)
1225 return;
1226
1227 rctx->clip = *state;
1228 rstate->id = R600_PIPE_STATE_CLIP;
1229 for (int i = 0; i < 6; i++) {
1230 r600_pipe_state_add_reg(rstate,
1231 R_028E20_PA_CL_UCP0_X + i * 16,
1232 fui(state->ucp[i][0]));
1233 r600_pipe_state_add_reg(rstate,
1234 R_028E24_PA_CL_UCP0_Y + i * 16,
1235 fui(state->ucp[i][1]) );
1236 r600_pipe_state_add_reg(rstate,
1237 R_028E28_PA_CL_UCP0_Z + i * 16,
1238 fui(state->ucp[i][2]));
1239 r600_pipe_state_add_reg(rstate,
1240 R_028E2C_PA_CL_UCP0_W + i * 16,
1241 fui(state->ucp[i][3]));
1242 }
1243
1244 free(rctx->states[R600_PIPE_STATE_CLIP]);
1245 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1246 r600_context_pipe_state_set(rctx, rstate);
1247
1248 cb.buffer = NULL;
1249 cb.user_buffer = state->ucp;
1250 cb.buffer_offset = 0;
1251 cb.buffer_size = 4*4*8;
1252 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1253 pipe_resource_reference(&cb.buffer, NULL);
1254 }
1255
1256 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1257 const struct pipe_poly_stipple *state)
1258 {
1259 }
1260
1261 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1262 {
1263 }
1264
1265 void r600_set_scissor_state(struct r600_context *rctx,
1266 const struct pipe_scissor_state *state)
1267 {
1268 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1269 uint32_t tl, br;
1270
1271 if (rstate == NULL)
1272 return;
1273
1274 rstate->id = R600_PIPE_STATE_SCISSOR;
1275 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1276 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1277 r600_pipe_state_add_reg(rstate,
1278 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1279 r600_pipe_state_add_reg(rstate,
1280 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1281
1282 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1283 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1284 r600_context_pipe_state_set(rctx, rstate);
1285 }
1286
1287 static void r600_pipe_set_scissor_state(struct pipe_context *ctx,
1288 const struct pipe_scissor_state *state)
1289 {
1290 struct r600_context *rctx = (struct r600_context *)ctx;
1291
1292 if (rctx->chip_class == R600) {
1293 rctx->scissor_state = *state;
1294
1295 if (!rctx->scissor_enable)
1296 return;
1297 }
1298
1299 r600_set_scissor_state(rctx, state);
1300 }
1301
1302 static void r600_set_viewport_state(struct pipe_context *ctx,
1303 const struct pipe_viewport_state *state)
1304 {
1305 struct r600_context *rctx = (struct r600_context *)ctx;
1306 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1307
1308 if (rstate == NULL)
1309 return;
1310
1311 rctx->viewport = *state;
1312 rstate->id = R600_PIPE_STATE_VIEWPORT;
1313 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1314 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1315 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1316 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1317 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1318 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1319
1320 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1321 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1322 r600_context_pipe_state_set(rctx, rstate);
1323 }
1324
1325 static void r600_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1326 const struct pipe_framebuffer_state *state, int cb)
1327 {
1328 struct r600_screen *rscreen = rctx->screen;
1329 struct r600_resource_texture *rtex;
1330 struct r600_surface *surf;
1331 unsigned level = state->cbufs[cb]->u.tex.level;
1332 unsigned pitch, slice;
1333 unsigned color_info;
1334 unsigned format, swap, ntype, endian;
1335 unsigned offset;
1336 const struct util_format_description *desc;
1337 int i;
1338 unsigned blend_bypass = 0, blend_clamp = 1;
1339
1340 surf = (struct r600_surface *)state->cbufs[cb];
1341 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1342
1343 if (rtex->is_depth && !rtex->is_flushing_texture) {
1344 rtex = rtex->flushed_depth_texture;
1345 }
1346
1347 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1348 if (!rscreen->use_surface_alloc) {
1349 offset = r600_texture_get_offset(rtex,
1350 level, state->cbufs[cb]->u.tex.first_layer);
1351 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1352 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1353 if (slice) {
1354 slice = slice - 1;
1355 }
1356 color_info = S_0280A0_ARRAY_MODE(rtex->array_mode[level]);
1357 } else {
1358 offset = rtex->surface.level[level].offset;
1359 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1360 offset += rtex->surface.level[level].slice_size *
1361 state->cbufs[cb]->u.tex.first_layer;
1362 }
1363 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1364 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1365 if (slice) {
1366 slice = slice - 1;
1367 }
1368 color_info = 0;
1369 switch (rtex->surface.level[level].mode) {
1370 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1371 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1372 break;
1373 case RADEON_SURF_MODE_1D:
1374 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1375 break;
1376 case RADEON_SURF_MODE_2D:
1377 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1378 break;
1379 case RADEON_SURF_MODE_LINEAR:
1380 default:
1381 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1382 break;
1383 }
1384 }
1385 desc = util_format_description(surf->base.format);
1386
1387 for (i = 0; i < 4; i++) {
1388 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1389 break;
1390 }
1391 }
1392
1393 ntype = V_0280A0_NUMBER_UNORM;
1394 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1395 ntype = V_0280A0_NUMBER_SRGB;
1396 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1397 if (desc->channel[i].normalized)
1398 ntype = V_0280A0_NUMBER_SNORM;
1399 else if (desc->channel[i].pure_integer)
1400 ntype = V_0280A0_NUMBER_SINT;
1401 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1402 if (desc->channel[i].normalized)
1403 ntype = V_0280A0_NUMBER_UNORM;
1404 else if (desc->channel[i].pure_integer)
1405 ntype = V_0280A0_NUMBER_UINT;
1406 }
1407
1408 format = r600_translate_colorformat(surf->base.format);
1409 assert(format != ~0);
1410
1411 swap = r600_translate_colorswap(surf->base.format);
1412 assert(swap != ~0);
1413
1414 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1415 endian = ENDIAN_NONE;
1416 } else {
1417 endian = r600_colorformat_endian_swap(format);
1418 }
1419
1420 /* set blend bypass according to docs if SINT/UINT or
1421 8/24 COLOR variants */
1422 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1423 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1424 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1425 blend_clamp = 0;
1426 blend_bypass = 1;
1427 }
1428
1429 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT)
1430 rctx->sx_alpha_test_control |= S_028410_ALPHA_TEST_BYPASS(1);
1431 else
1432 rctx->sx_alpha_test_control &= C_028410_ALPHA_TEST_BYPASS;
1433
1434 color_info |= S_0280A0_FORMAT(format) |
1435 S_0280A0_COMP_SWAP(swap) |
1436 S_0280A0_BLEND_BYPASS(blend_bypass) |
1437 S_0280A0_BLEND_CLAMP(blend_clamp) |
1438 S_0280A0_NUMBER_TYPE(ntype) |
1439 S_0280A0_ENDIAN(endian);
1440
1441 /* EXPORT_NORM is an optimzation that can be enabled for better
1442 * performance in certain cases
1443 */
1444 if (rctx->chip_class == R600) {
1445 /* EXPORT_NORM can be enabled if:
1446 * - 11-bit or smaller UNORM/SNORM/SRGB
1447 * - BLEND_CLAMP is enabled
1448 * - BLEND_FLOAT32 is disabled
1449 */
1450 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1451 (desc->channel[i].size < 12 &&
1452 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1453 ntype != V_0280A0_NUMBER_UINT &&
1454 ntype != V_0280A0_NUMBER_SINT) &&
1455 G_0280A0_BLEND_CLAMP(color_info) &&
1456 !G_0280A0_BLEND_FLOAT32(color_info)) {
1457 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1458 } else {
1459 rctx->export_16bpc = false;
1460 }
1461 } else {
1462 /* EXPORT_NORM can be enabled if:
1463 * - 11-bit or smaller UNORM/SNORM/SRGB
1464 * - 16-bit or smaller FLOAT
1465 */
1466 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1467 ((desc->channel[i].size < 12 &&
1468 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1469 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1470 (desc->channel[i].size < 17 &&
1471 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1472 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1473 } else {
1474 rctx->export_16bpc = false;
1475 }
1476 }
1477
1478 /* for possible dual-src MRT write color info 1 */
1479 if (cb == 0 && rctx->framebuffer.nr_cbufs == 1) {
1480 r600_pipe_state_add_reg_bo(rstate,
1481 R_0280A0_CB_COLOR0_INFO + 1 * 4,
1482 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1483 }
1484
1485 r600_pipe_state_add_reg_bo(rstate,
1486 R_028040_CB_COLOR0_BASE + cb * 4,
1487 offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE);
1488 r600_pipe_state_add_reg_bo(rstate,
1489 R_0280A0_CB_COLOR0_INFO + cb * 4,
1490 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1491 r600_pipe_state_add_reg(rstate,
1492 R_028060_CB_COLOR0_SIZE + cb * 4,
1493 S_028060_PITCH_TILE_MAX(pitch) |
1494 S_028060_SLICE_TILE_MAX(slice));
1495 if (!rscreen->use_surface_alloc) {
1496 r600_pipe_state_add_reg(rstate,
1497 R_028080_CB_COLOR0_VIEW + cb * 4,
1498 0x00000000);
1499 } else {
1500 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1501 r600_pipe_state_add_reg(rstate,
1502 R_028080_CB_COLOR0_VIEW + cb * 4,
1503 0x00000000);
1504 } else {
1505 r600_pipe_state_add_reg(rstate,
1506 R_028080_CB_COLOR0_VIEW + cb * 4,
1507 S_028080_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1508 S_028080_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1509 }
1510 }
1511 r600_pipe_state_add_reg_bo(rstate,
1512 R_0280E0_CB_COLOR0_FRAG + cb * 4,
1513 0, &rtex->resource, RADEON_USAGE_READWRITE);
1514 r600_pipe_state_add_reg_bo(rstate,
1515 R_0280C0_CB_COLOR0_TILE + cb * 4,
1516 0, &rtex->resource, RADEON_USAGE_READWRITE);
1517 }
1518
1519 static void r600_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1520 const struct pipe_framebuffer_state *state)
1521 {
1522 struct r600_screen *rscreen = rctx->screen;
1523 struct r600_resource_texture *rtex;
1524 struct r600_surface *surf;
1525 unsigned level, pitch, slice, format, offset, array_mode;
1526
1527 if (state->zsbuf == NULL)
1528 return;
1529
1530 level = state->zsbuf->u.tex.level;
1531
1532 surf = (struct r600_surface *)state->zsbuf;
1533 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1534
1535 if (!rscreen->use_surface_alloc) {
1536 /* XXX remove this once tiling is properly supported */
1537 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1538 V_0280A0_ARRAY_1D_TILED_THIN1;
1539
1540 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1541 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
1542 level, state->zsbuf->u.tex.first_layer);
1543 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1544 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1545 if (slice) {
1546 slice = slice - 1;
1547 }
1548 } else {
1549 offset = rtex->surface.level[level].offset;
1550 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1551 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1552 if (slice) {
1553 slice = slice - 1;
1554 }
1555 switch (rtex->surface.level[level].mode) {
1556 case RADEON_SURF_MODE_2D:
1557 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1558 break;
1559 case RADEON_SURF_MODE_1D:
1560 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1561 case RADEON_SURF_MODE_LINEAR:
1562 default:
1563 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1564 break;
1565 }
1566 }
1567
1568 format = r600_translate_dbformat(state->zsbuf->format);
1569 assert(format != ~0);
1570
1571 r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE,
1572 offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE);
1573 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1574 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice));
1575 if (!rscreen->use_surface_alloc) {
1576 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000);
1577 } else {
1578 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW,
1579 S_028004_SLICE_START(state->zsbuf->u.tex.first_layer) |
1580 S_028004_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1581 }
1582 r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO,
1583 S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format),
1584 &rtex->resource, RADEON_USAGE_READWRITE);
1585 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1586 (surf->aligned_height / 8) - 1);
1587 }
1588
1589 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1590 const struct pipe_framebuffer_state *state)
1591 {
1592 struct r600_context *rctx = (struct r600_context *)ctx;
1593 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1594 uint32_t tl, br, shader_control;
1595
1596 if (rstate == NULL)
1597 return;
1598
1599 r600_flush_framebuffer(rctx, false);
1600
1601 /* unreference old buffer and reference new one */
1602 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1603
1604 util_copy_framebuffer_state(&rctx->framebuffer, state);
1605
1606 /* build states */
1607 rctx->export_16bpc = true;
1608 rctx->nr_cbufs = state->nr_cbufs;
1609
1610 for (int i = 0; i < state->nr_cbufs; i++) {
1611 r600_cb(rctx, rstate, state, i);
1612 }
1613 if (state->zsbuf) {
1614 r600_db(rctx, rstate, state);
1615 }
1616
1617 shader_control = 0;
1618 for (int i = 0; i < state->nr_cbufs; i++) {
1619 shader_control |= 1 << i;
1620 }
1621 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1622 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1623
1624 r600_pipe_state_add_reg(rstate,
1625 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1626 r600_pipe_state_add_reg(rstate,
1627 R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1628
1629 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1630 shader_control);
1631
1632 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1633 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1634 r600_context_pipe_state_set(rctx, rstate);
1635
1636 if (state->zsbuf) {
1637 r600_polygon_offset_update(rctx);
1638 }
1639
1640 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1641 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1642 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1643 }
1644 }
1645
1646 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1647 {
1648 struct radeon_winsys_cs *cs = rctx->cs;
1649 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1650 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1651 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1652 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1653
1654 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1655 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1656 r600_write_value(cs, (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
1657 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1658 a->cb_color_control |
1659 S_028808_MULTIWRITE_ENABLE(multiwrite));
1660 }
1661
1662 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1663 {
1664 struct radeon_winsys_cs *cs = rctx->cs;
1665 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1666 unsigned db_render_control = 0;
1667 unsigned db_render_override =
1668 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
1669 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1670 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1671
1672 if (a->occlusion_query_enabled) {
1673 if (rctx->chip_class >= R700) {
1674 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1675 }
1676 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1677 }
1678 if (a->flush_depthstencil_through_cb) {
1679 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(1) |
1680 S_028D0C_STENCIL_COPY_ENABLE(1) |
1681 S_028D0C_COPY_CENTROID(1);
1682 }
1683
1684 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1685 r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1686 r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1687 }
1688
1689 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1690 {
1691 struct radeon_winsys_cs *cs = rctx->cs;
1692 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1693
1694 while (dirty_mask) {
1695 struct pipe_vertex_buffer *vb;
1696 struct r600_resource *rbuffer;
1697 unsigned offset;
1698 unsigned buffer_index = u_bit_scan(&dirty_mask);
1699
1700 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1701 rbuffer = (struct r600_resource*)vb->buffer;
1702 assert(rbuffer);
1703
1704 offset = vb->buffer_offset;
1705
1706 /* fetch resources start at index 320 */
1707 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1708 r600_write_value(cs, (320 + buffer_index) * 7);
1709 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1710 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1711 r600_write_value(cs, /* RESOURCEi_WORD2 */
1712 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1713 S_038008_STRIDE(vb->stride));
1714 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1715 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1716 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1717 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1718
1719 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1720 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1721 }
1722 }
1723
1724 static void r600_emit_constant_buffers(struct r600_context *rctx,
1725 struct r600_constbuf_state *state,
1726 unsigned buffer_id_base,
1727 unsigned reg_alu_constbuf_size,
1728 unsigned reg_alu_const_cache)
1729 {
1730 struct radeon_winsys_cs *cs = rctx->cs;
1731 uint32_t dirty_mask = state->dirty_mask;
1732
1733 while (dirty_mask) {
1734 struct pipe_constant_buffer *cb;
1735 struct r600_resource *rbuffer;
1736 unsigned offset;
1737 unsigned buffer_index = ffs(dirty_mask) - 1;
1738
1739 cb = &state->cb[buffer_index];
1740 rbuffer = (struct r600_resource*)cb->buffer;
1741 assert(rbuffer);
1742
1743 offset = cb->buffer_offset;
1744
1745 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1746 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1747 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1748
1749 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1750 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1751
1752 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1753 r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
1754 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1755 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1756 r600_write_value(cs, /* RESOURCEi_WORD2 */
1757 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1758 S_038008_STRIDE(16));
1759 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1760 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1761 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1762 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1763
1764 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1765 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1766
1767 dirty_mask &= ~(1 << buffer_index);
1768 }
1769 state->dirty_mask = 0;
1770 }
1771
1772 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1773 {
1774 r600_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 160,
1775 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1776 R_028980_ALU_CONST_CACHE_VS_0);
1777 }
1778
1779 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1780 {
1781 r600_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
1782 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1783 R_028940_ALU_CONST_CACHE_PS_0);
1784 }
1785
1786 static void r600_emit_sampler_views(struct r600_context *rctx,
1787 struct r600_samplerview_state *state,
1788 unsigned resource_id_base)
1789 {
1790 struct radeon_winsys_cs *cs = rctx->cs;
1791 uint32_t dirty_mask = state->dirty_mask;
1792
1793 while (dirty_mask) {
1794 struct r600_pipe_sampler_view *rview;
1795 unsigned resource_index = u_bit_scan(&dirty_mask);
1796 unsigned reloc;
1797
1798 rview = state->views[resource_index];
1799 assert(rview);
1800
1801 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1802 r600_write_value(cs, (resource_id_base + resource_index) * 7);
1803 r600_write_array(cs, 7, rview->tex_resource_words);
1804
1805 /* XXX The kernel needs two relocations. This is stupid. */
1806 reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
1807 RADEON_USAGE_READ);
1808 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1809 r600_write_value(cs, reloc);
1810 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1811 r600_write_value(cs, reloc);
1812 }
1813 state->dirty_mask = 0;
1814 }
1815
1816 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1817 {
1818 r600_emit_sampler_views(rctx, &rctx->vs_samplers.views, 160 + R600_MAX_CONST_BUFFERS);
1819 }
1820
1821 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1822 {
1823 r600_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS);
1824 }
1825
1826 void r600_init_state_functions(struct r600_context *rctx)
1827 {
1828 r600_init_atom(&rctx->cb_misc_state.atom, r600_emit_cb_misc_state, 0, 0);
1829 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1830 r600_init_atom(&rctx->db_misc_state.atom, r600_emit_db_misc_state, 4, 0);
1831 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1832 r600_init_atom(&rctx->vertex_buffer_state.atom, r600_emit_vertex_buffers, 0, 0);
1833 r600_init_atom(&rctx->vs_constbuf_state.atom, r600_emit_vs_constant_buffers, 0, 0);
1834 r600_init_atom(&rctx->ps_constbuf_state.atom, r600_emit_ps_constant_buffers, 0, 0);
1835 r600_init_atom(&rctx->vs_samplers.views.atom, r600_emit_vs_sampler_views, 0, 0);
1836 r600_init_atom(&rctx->ps_samplers.views.atom, r600_emit_ps_sampler_views, 0, 0);
1837
1838 rctx->context.create_blend_state = r600_create_blend_state;
1839 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1840 rctx->context.create_fs_state = r600_create_shader_state_ps;
1841 rctx->context.create_rasterizer_state = r600_create_rs_state;
1842 rctx->context.create_sampler_state = r600_create_sampler_state;
1843 rctx->context.create_sampler_view = r600_create_sampler_view;
1844 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1845 rctx->context.create_vs_state = r600_create_shader_state_vs;
1846 rctx->context.bind_blend_state = r600_bind_blend_state;
1847 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1848 rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
1849 rctx->context.bind_fs_state = r600_bind_ps_shader;
1850 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1851 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1852 rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
1853 rctx->context.bind_vs_state = r600_bind_vs_shader;
1854 rctx->context.delete_blend_state = r600_delete_state;
1855 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1856 rctx->context.delete_fs_state = r600_delete_ps_shader;
1857 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1858 rctx->context.delete_sampler_state = r600_delete_state;
1859 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1860 rctx->context.delete_vs_state = r600_delete_vs_shader;
1861 rctx->context.set_blend_color = r600_set_blend_color;
1862 rctx->context.set_clip_state = r600_set_clip_state;
1863 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1864 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1865 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1866 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1867 rctx->context.set_sample_mask = r600_set_sample_mask;
1868 rctx->context.set_scissor_state = r600_pipe_set_scissor_state;
1869 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1870 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1871 rctx->context.set_index_buffer = r600_set_index_buffer;
1872 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1873 rctx->context.set_viewport_state = r600_set_viewport_state;
1874 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1875 rctx->context.texture_barrier = r600_texture_barrier;
1876 rctx->context.create_stream_output_target = r600_create_so_target;
1877 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1878 rctx->context.set_stream_output_targets = r600_set_so_targets;
1879 }
1880
1881 /* Adjust GPR allocation on R6xx/R7xx */
1882 void r600_adjust_gprs(struct r600_context *rctx)
1883 {
1884 struct r600_pipe_state rstate;
1885 unsigned num_ps_gprs = rctx->default_ps_gprs;
1886 unsigned num_vs_gprs = rctx->default_vs_gprs;
1887 unsigned tmp;
1888 int diff;
1889
1890 /* XXX: Following call moved from r600_bind_[ps|vs]_shader,
1891 * it seems eg+ doesn't need it, r6xx/7xx probably need it only for
1892 * adjusting the GPR allocation?
1893 * Do we need this if we aren't really changing config below? */
1894 r600_inval_shader_cache(rctx);
1895
1896 if (rctx->ps_shader->current->shader.bc.ngpr > rctx->default_ps_gprs)
1897 {
1898 diff = rctx->ps_shader->current->shader.bc.ngpr - rctx->default_ps_gprs;
1899 num_vs_gprs -= diff;
1900 num_ps_gprs += diff;
1901 }
1902
1903 if (rctx->vs_shader->current->shader.bc.ngpr > rctx->default_vs_gprs)
1904 {
1905 diff = rctx->vs_shader->current->shader.bc.ngpr - rctx->default_vs_gprs;
1906 num_ps_gprs -= diff;
1907 num_vs_gprs += diff;
1908 }
1909
1910 tmp = 0;
1911 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1912 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1913 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
1914 rstate.nregs = 0;
1915 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp);
1916
1917 r600_context_pipe_state_set(rctx, &rstate);
1918 }
1919
1920 void r600_init_atom_start_cs(struct r600_context *rctx)
1921 {
1922 int ps_prio;
1923 int vs_prio;
1924 int gs_prio;
1925 int es_prio;
1926 int num_ps_gprs;
1927 int num_vs_gprs;
1928 int num_gs_gprs;
1929 int num_es_gprs;
1930 int num_temp_gprs;
1931 int num_ps_threads;
1932 int num_vs_threads;
1933 int num_gs_threads;
1934 int num_es_threads;
1935 int num_ps_stack_entries;
1936 int num_vs_stack_entries;
1937 int num_gs_stack_entries;
1938 int num_es_stack_entries;
1939 enum radeon_family family;
1940 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
1941 uint32_t tmp;
1942 unsigned i;
1943
1944 r600_init_command_buffer(cb, 256, EMIT_EARLY);
1945
1946 /* R6xx requires this packet at the start of each command buffer */
1947 if (rctx->chip_class == R600) {
1948 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
1949 r600_store_value(cb, 0);
1950 }
1951 /* All asics require this one */
1952 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1953 r600_store_value(cb, 0x80000000);
1954 r600_store_value(cb, 0x80000000);
1955
1956 family = rctx->family;
1957 ps_prio = 0;
1958 vs_prio = 1;
1959 gs_prio = 2;
1960 es_prio = 3;
1961 switch (family) {
1962 case CHIP_R600:
1963 num_ps_gprs = 192;
1964 num_vs_gprs = 56;
1965 num_temp_gprs = 4;
1966 num_gs_gprs = 0;
1967 num_es_gprs = 0;
1968 num_ps_threads = 136;
1969 num_vs_threads = 48;
1970 num_gs_threads = 4;
1971 num_es_threads = 4;
1972 num_ps_stack_entries = 128;
1973 num_vs_stack_entries = 128;
1974 num_gs_stack_entries = 0;
1975 num_es_stack_entries = 0;
1976 break;
1977 case CHIP_RV630:
1978 case CHIP_RV635:
1979 num_ps_gprs = 84;
1980 num_vs_gprs = 36;
1981 num_temp_gprs = 4;
1982 num_gs_gprs = 0;
1983 num_es_gprs = 0;
1984 num_ps_threads = 144;
1985 num_vs_threads = 40;
1986 num_gs_threads = 4;
1987 num_es_threads = 4;
1988 num_ps_stack_entries = 40;
1989 num_vs_stack_entries = 40;
1990 num_gs_stack_entries = 32;
1991 num_es_stack_entries = 16;
1992 break;
1993 case CHIP_RV610:
1994 case CHIP_RV620:
1995 case CHIP_RS780:
1996 case CHIP_RS880:
1997 default:
1998 num_ps_gprs = 84;
1999 num_vs_gprs = 36;
2000 num_temp_gprs = 4;
2001 num_gs_gprs = 0;
2002 num_es_gprs = 0;
2003 num_ps_threads = 136;
2004 num_vs_threads = 48;
2005 num_gs_threads = 4;
2006 num_es_threads = 4;
2007 num_ps_stack_entries = 40;
2008 num_vs_stack_entries = 40;
2009 num_gs_stack_entries = 32;
2010 num_es_stack_entries = 16;
2011 break;
2012 case CHIP_RV670:
2013 num_ps_gprs = 144;
2014 num_vs_gprs = 40;
2015 num_temp_gprs = 4;
2016 num_gs_gprs = 0;
2017 num_es_gprs = 0;
2018 num_ps_threads = 136;
2019 num_vs_threads = 48;
2020 num_gs_threads = 4;
2021 num_es_threads = 4;
2022 num_ps_stack_entries = 40;
2023 num_vs_stack_entries = 40;
2024 num_gs_stack_entries = 32;
2025 num_es_stack_entries = 16;
2026 break;
2027 case CHIP_RV770:
2028 num_ps_gprs = 192;
2029 num_vs_gprs = 56;
2030 num_temp_gprs = 4;
2031 num_gs_gprs = 0;
2032 num_es_gprs = 0;
2033 num_ps_threads = 188;
2034 num_vs_threads = 60;
2035 num_gs_threads = 0;
2036 num_es_threads = 0;
2037 num_ps_stack_entries = 256;
2038 num_vs_stack_entries = 256;
2039 num_gs_stack_entries = 0;
2040 num_es_stack_entries = 0;
2041 break;
2042 case CHIP_RV730:
2043 case CHIP_RV740:
2044 num_ps_gprs = 84;
2045 num_vs_gprs = 36;
2046 num_temp_gprs = 4;
2047 num_gs_gprs = 0;
2048 num_es_gprs = 0;
2049 num_ps_threads = 188;
2050 num_vs_threads = 60;
2051 num_gs_threads = 0;
2052 num_es_threads = 0;
2053 num_ps_stack_entries = 128;
2054 num_vs_stack_entries = 128;
2055 num_gs_stack_entries = 0;
2056 num_es_stack_entries = 0;
2057 break;
2058 case CHIP_RV710:
2059 num_ps_gprs = 192;
2060 num_vs_gprs = 56;
2061 num_temp_gprs = 4;
2062 num_gs_gprs = 0;
2063 num_es_gprs = 0;
2064 num_ps_threads = 144;
2065 num_vs_threads = 48;
2066 num_gs_threads = 0;
2067 num_es_threads = 0;
2068 num_ps_stack_entries = 128;
2069 num_vs_stack_entries = 128;
2070 num_gs_stack_entries = 0;
2071 num_es_stack_entries = 0;
2072 break;
2073 }
2074
2075 rctx->default_ps_gprs = num_ps_gprs;
2076 rctx->default_vs_gprs = num_vs_gprs;
2077 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2078
2079 /* SQ_CONFIG */
2080 tmp = 0;
2081 switch (family) {
2082 case CHIP_RV610:
2083 case CHIP_RV620:
2084 case CHIP_RS780:
2085 case CHIP_RS880:
2086 case CHIP_RV710:
2087 break;
2088 default:
2089 tmp |= S_008C00_VC_ENABLE(1);
2090 break;
2091 }
2092 tmp |= S_008C00_DX9_CONSTS(0);
2093 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2094 tmp |= S_008C00_PS_PRIO(ps_prio);
2095 tmp |= S_008C00_VS_PRIO(vs_prio);
2096 tmp |= S_008C00_GS_PRIO(gs_prio);
2097 tmp |= S_008C00_ES_PRIO(es_prio);
2098 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2099
2100 /* SQ_GPR_RESOURCE_MGMT_2 */
2101 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2102 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2103 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2104 r600_store_value(cb, tmp);
2105
2106 /* SQ_THREAD_RESOURCE_MGMT */
2107 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2108 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2109 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2110 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2111 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2112
2113 /* SQ_STACK_RESOURCE_MGMT_1 */
2114 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2115 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2116 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2117
2118 /* SQ_STACK_RESOURCE_MGMT_2 */
2119 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2120 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2121 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2122
2123 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2124
2125 if (rctx->chip_class >= R700) {
2126 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2127 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2128 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2129 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2130 } else {
2131 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2132 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2133 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2134 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2135 }
2136 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2137 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2138 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2139 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2140 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2141 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2142 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2143 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2144 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2145 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2146
2147 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2148 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2149 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2150 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2151 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2152 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2153 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2154 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2155 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2156 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2157 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2158 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2159 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2160 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2161
2162 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2163 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2164 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2165
2166 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2167 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2168 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2169 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2170
2171 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2172
2173 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2174 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2175 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2176
2177 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2178
2179 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2180 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2181 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2182
2183 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2184 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2185 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2186 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2187
2188 r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2189 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2190 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2191
2192 r600_store_context_reg(cb, R_028D44_DB_ALPHA_TO_MASK, 0xAA00);
2193
2194 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2195 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2196
2197 r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
2198 r600_store_value(cb, 0x400); /* R_028C00_PA_SC_LINE_CNTL */
2199 r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
2200
2201 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 6);
2202 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2203 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2204 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2205 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2206 r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
2207 r600_store_value(cb, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX */
2208
2209 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2210 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2211 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2212
2213 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2214
2215 r600_store_context_reg_seq(cb, R_028100_CB_COLOR0_MASK, 8);
2216 for (i = 0; i < 8; i++) {
2217 r600_store_value(cb, 0);
2218 }
2219
2220 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2221 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2222
2223 if (rctx->chip_class >= R700) {
2224 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2225 }
2226
2227 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2228 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2229 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2230 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2231 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2232
2233 r600_store_context_reg(cb, R_028C48_PA_SC_AA_MASK, 0xFFFFFFFF);
2234
2235 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2236 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2237 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2238
2239 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2240 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2241 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2242
2243 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2244 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2245 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2246
2247 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2248 r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2249
2250 if (rctx->chip_class == R700 && rctx->screen->has_streamout)
2251 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2252 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2253
2254 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2255 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2256 }
2257
2258 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2259 {
2260 struct r600_context *rctx = (struct r600_context *)ctx;
2261 struct r600_pipe_state *rstate = &shader->rstate;
2262 struct r600_shader *rshader = &shader->shader;
2263 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2264 int pos_index = -1, face_index = -1;
2265 unsigned tmp, sid, ufi = 0;
2266 int need_linear = 0;
2267 unsigned z_export = 0, stencil_export = 0;
2268
2269 rstate->nregs = 0;
2270
2271 for (i = 0; i < rshader->ninput; i++) {
2272 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2273 pos_index = i;
2274 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2275 face_index = i;
2276
2277 sid = rshader->input[i].spi_sid;
2278
2279 tmp = S_028644_SEMANTIC(sid);
2280
2281 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2282 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2283 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2284 rctx->rasterizer && rctx->rasterizer->flatshade))
2285 tmp |= S_028644_FLAT_SHADE(1);
2286
2287 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2288 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2289 tmp |= S_028644_PT_SPRITE_TEX(1);
2290 }
2291
2292 if (rshader->input[i].centroid)
2293 tmp |= S_028644_SEL_CENTROID(1);
2294
2295 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2296 need_linear = 1;
2297 tmp |= S_028644_SEL_LINEAR(1);
2298 }
2299
2300 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2301 tmp);
2302 }
2303
2304 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2305 for (i = 0; i < rshader->noutput; i++) {
2306 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2307 z_export = 1;
2308 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2309 stencil_export = 1;
2310 }
2311 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2312 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2313 if (rshader->uses_kill)
2314 db_shader_control |= S_02880C_KILL_ENABLE(1);
2315
2316 exports_ps = 0;
2317 for (i = 0; i < rshader->noutput; i++) {
2318 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2319 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2320 exports_ps |= 1;
2321 }
2322 }
2323 num_cout = rshader->nr_ps_color_exports;
2324 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2325 if (!exports_ps) {
2326 /* always at least export 1 component per pixel */
2327 exports_ps = 2;
2328 }
2329
2330 shader->nr_ps_color_outputs = num_cout;
2331
2332 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2333 S_0286CC_PERSP_GRADIENT_ENA(1)|
2334 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2335 spi_input_z = 0;
2336 if (pos_index != -1) {
2337 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2338 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2339 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2340 S_0286CC_BARYC_SAMPLE_CNTL(1));
2341 spi_input_z |= 1;
2342 }
2343
2344 spi_ps_in_control_1 = 0;
2345 if (face_index != -1) {
2346 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2347 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2348 }
2349
2350 /* HW bug in original R600 */
2351 if (rctx->family == CHIP_R600)
2352 ufi = 1;
2353
2354 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2355 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2356 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2357 r600_pipe_state_add_reg_bo(rstate,
2358 R_028840_SQ_PGM_START_PS,
2359 0, shader->bo, RADEON_USAGE_READ);
2360 r600_pipe_state_add_reg(rstate,
2361 R_028850_SQ_PGM_RESOURCES_PS,
2362 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2363 S_028850_STACK_SIZE(rshader->bc.nstack) |
2364 S_028850_UNCACHED_FIRST_INST(ufi));
2365 r600_pipe_state_add_reg(rstate,
2366 R_028854_SQ_PGM_EXPORTS_PS,
2367 exports_ps);
2368 /* only set some bits here, the other bits are set in the dsa state */
2369 shader->db_shader_control = db_shader_control;
2370 shader->ps_depth_export = z_export | stencil_export;
2371
2372 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2373 if (rctx->rasterizer)
2374 shader->flatshade = rctx->rasterizer->flatshade;
2375 }
2376
2377 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2378 {
2379 struct r600_context *rctx = (struct r600_context *)ctx;
2380 struct r600_pipe_state *rstate = &shader->rstate;
2381 struct r600_shader *rshader = &shader->shader;
2382 unsigned spi_vs_out_id[10] = {};
2383 unsigned i, tmp, nparams = 0;
2384
2385 /* clear previous register */
2386 rstate->nregs = 0;
2387
2388 for (i = 0; i < rshader->noutput; i++) {
2389 if (rshader->output[i].spi_sid) {
2390 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2391 spi_vs_out_id[nparams / 4] |= tmp;
2392 nparams++;
2393 }
2394 }
2395
2396 for (i = 0; i < 10; i++) {
2397 r600_pipe_state_add_reg(rstate,
2398 R_028614_SPI_VS_OUT_ID_0 + i * 4,
2399 spi_vs_out_id[i]);
2400 }
2401
2402 /* Certain attributes (position, psize, etc.) don't count as params.
2403 * VS is required to export at least one param and r600_shader_from_tgsi()
2404 * takes care of adding a dummy export.
2405 */
2406 if (nparams < 1)
2407 nparams = 1;
2408
2409 r600_pipe_state_add_reg(rstate,
2410 R_0286C4_SPI_VS_OUT_CONFIG,
2411 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2412 r600_pipe_state_add_reg(rstate,
2413 R_028868_SQ_PGM_RESOURCES_VS,
2414 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2415 S_028868_STACK_SIZE(rshader->bc.nstack));
2416 r600_pipe_state_add_reg_bo(rstate,
2417 R_028858_SQ_PGM_START_VS,
2418 0, shader->bo, RADEON_USAGE_READ);
2419
2420 shader->pa_cl_vs_out_cntl =
2421 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2422 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2423 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2424 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2425 }
2426
2427 void r600_fetch_shader(struct pipe_context *ctx,
2428 struct r600_vertex_element *ve)
2429 {
2430 struct r600_pipe_state *rstate;
2431 struct r600_context *rctx = (struct r600_context *)ctx;
2432
2433 rstate = &ve->rstate;
2434 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2435 rstate->nregs = 0;
2436 r600_pipe_state_add_reg_bo(rstate, R_028894_SQ_PGM_START_FS,
2437 0,
2438 ve->fetch_shader, RADEON_USAGE_READ);
2439 }
2440
2441 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2442 {
2443 struct pipe_depth_stencil_alpha_state dsa;
2444 boolean quirk = false;
2445
2446 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2447 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2448 quirk = true;
2449
2450 memset(&dsa, 0, sizeof(dsa));
2451
2452 if (quirk) {
2453 dsa.depth.enabled = 1;
2454 dsa.depth.func = PIPE_FUNC_LEQUAL;
2455 dsa.stencil[0].enabled = 1;
2456 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2457 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2458 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2459 dsa.stencil[0].writemask = 0xff;
2460 }
2461
2462 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2463 }
2464
2465 void r600_update_dual_export_state(struct r600_context * rctx)
2466 {
2467 unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
2468 !rctx->ps_shader->current->ps_depth_export;
2469 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2470 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2471
2472 if (db_shader_control != rctx->db_shader_control) {
2473 struct r600_pipe_state rstate;
2474
2475 rctx->db_shader_control = db_shader_control;
2476 rstate.nregs = 0;
2477 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2478 r600_context_pipe_state_set(rctx, &rstate);
2479 }
2480 }