2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
24 #include "r600_shader.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
33 static uint32_t r600_translate_blend_function(int blend_func
)
37 return V_028804_COMB_DST_PLUS_SRC
;
38 case PIPE_BLEND_SUBTRACT
:
39 return V_028804_COMB_SRC_MINUS_DST
;
40 case PIPE_BLEND_REVERSE_SUBTRACT
:
41 return V_028804_COMB_DST_MINUS_SRC
;
43 return V_028804_COMB_MIN_DST_SRC
;
45 return V_028804_COMB_MAX_DST_SRC
;
47 R600_ERR("Unknown blend function %d\n", blend_func
);
54 static uint32_t r600_translate_blend_factor(int blend_fact
)
57 case PIPE_BLENDFACTOR_ONE
:
58 return V_028804_BLEND_ONE
;
59 case PIPE_BLENDFACTOR_SRC_COLOR
:
60 return V_028804_BLEND_SRC_COLOR
;
61 case PIPE_BLENDFACTOR_SRC_ALPHA
:
62 return V_028804_BLEND_SRC_ALPHA
;
63 case PIPE_BLENDFACTOR_DST_ALPHA
:
64 return V_028804_BLEND_DST_ALPHA
;
65 case PIPE_BLENDFACTOR_DST_COLOR
:
66 return V_028804_BLEND_DST_COLOR
;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE
;
69 case PIPE_BLENDFACTOR_CONST_COLOR
:
70 return V_028804_BLEND_CONST_COLOR
;
71 case PIPE_BLENDFACTOR_CONST_ALPHA
:
72 return V_028804_BLEND_CONST_ALPHA
;
73 case PIPE_BLENDFACTOR_ZERO
:
74 return V_028804_BLEND_ZERO
;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR
;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA
;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA
;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR
;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR
;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA
;
87 case PIPE_BLENDFACTOR_SRC1_COLOR
:
88 return V_028804_BLEND_SRC1_COLOR
;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
90 return V_028804_BLEND_SRC1_ALPHA
;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
92 return V_028804_BLEND_INV_SRC1_COLOR
;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
94 return V_028804_BLEND_INV_SRC1_ALPHA
;
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
103 static unsigned r600_tex_dim(unsigned dim
, unsigned nr_samples
)
107 case PIPE_TEXTURE_1D
:
108 return V_038000_SQ_TEX_DIM_1D
;
109 case PIPE_TEXTURE_1D_ARRAY
:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY
;
111 case PIPE_TEXTURE_2D
:
112 case PIPE_TEXTURE_RECT
:
113 return nr_samples
> 1 ? V_038000_SQ_TEX_DIM_2D_MSAA
:
114 V_038000_SQ_TEX_DIM_2D
;
115 case PIPE_TEXTURE_2D_ARRAY
:
116 return nr_samples
> 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
117 V_038000_SQ_TEX_DIM_2D_ARRAY
;
118 case PIPE_TEXTURE_3D
:
119 return V_038000_SQ_TEX_DIM_3D
;
120 case PIPE_TEXTURE_CUBE
:
121 case PIPE_TEXTURE_CUBE_ARRAY
:
122 return V_038000_SQ_TEX_DIM_CUBEMAP
;
126 static uint32_t r600_translate_dbformat(enum pipe_format format
)
129 case PIPE_FORMAT_Z16_UNORM
:
130 return V_028010_DEPTH_16
;
131 case PIPE_FORMAT_Z24X8_UNORM
:
132 return V_028010_DEPTH_X8_24
;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
134 return V_028010_DEPTH_8_24
;
135 case PIPE_FORMAT_Z32_FLOAT
:
136 return V_028010_DEPTH_32_FLOAT
;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
138 return V_028010_DEPTH_X24_8_32_FLOAT
;
144 static uint32_t r600_translate_colorswap(enum pipe_format format
)
148 case PIPE_FORMAT_A8_UNORM
:
149 case PIPE_FORMAT_A8_SNORM
:
150 case PIPE_FORMAT_A8_UINT
:
151 case PIPE_FORMAT_A8_SINT
:
152 case PIPE_FORMAT_A16_UNORM
:
153 case PIPE_FORMAT_A16_SNORM
:
154 case PIPE_FORMAT_A16_UINT
:
155 case PIPE_FORMAT_A16_SINT
:
156 case PIPE_FORMAT_A16_FLOAT
:
157 case PIPE_FORMAT_A32_UINT
:
158 case PIPE_FORMAT_A32_SINT
:
159 case PIPE_FORMAT_A32_FLOAT
:
160 case PIPE_FORMAT_R4A4_UNORM
:
161 return V_0280A0_SWAP_ALT_REV
;
162 case PIPE_FORMAT_I8_UNORM
:
163 case PIPE_FORMAT_I8_SNORM
:
164 case PIPE_FORMAT_I8_UINT
:
165 case PIPE_FORMAT_I8_SINT
:
166 case PIPE_FORMAT_L8_UNORM
:
167 case PIPE_FORMAT_L8_SNORM
:
168 case PIPE_FORMAT_L8_UINT
:
169 case PIPE_FORMAT_L8_SINT
:
170 case PIPE_FORMAT_L8_SRGB
:
171 case PIPE_FORMAT_L16_UNORM
:
172 case PIPE_FORMAT_L16_SNORM
:
173 case PIPE_FORMAT_L16_UINT
:
174 case PIPE_FORMAT_L16_SINT
:
175 case PIPE_FORMAT_L16_FLOAT
:
176 case PIPE_FORMAT_L32_UINT
:
177 case PIPE_FORMAT_L32_SINT
:
178 case PIPE_FORMAT_L32_FLOAT
:
179 case PIPE_FORMAT_I16_UNORM
:
180 case PIPE_FORMAT_I16_SNORM
:
181 case PIPE_FORMAT_I16_UINT
:
182 case PIPE_FORMAT_I16_SINT
:
183 case PIPE_FORMAT_I16_FLOAT
:
184 case PIPE_FORMAT_I32_UINT
:
185 case PIPE_FORMAT_I32_SINT
:
186 case PIPE_FORMAT_I32_FLOAT
:
187 case PIPE_FORMAT_R8_UNORM
:
188 case PIPE_FORMAT_R8_SNORM
:
189 case PIPE_FORMAT_R8_UINT
:
190 case PIPE_FORMAT_R8_SINT
:
191 return V_0280A0_SWAP_STD
;
193 case PIPE_FORMAT_L4A4_UNORM
:
194 case PIPE_FORMAT_A4R4_UNORM
:
195 return V_0280A0_SWAP_ALT
;
197 /* 16-bit buffers. */
198 case PIPE_FORMAT_B5G6R5_UNORM
:
199 return V_0280A0_SWAP_STD_REV
;
201 case PIPE_FORMAT_B5G5R5A1_UNORM
:
202 case PIPE_FORMAT_B5G5R5X1_UNORM
:
203 return V_0280A0_SWAP_ALT
;
205 case PIPE_FORMAT_B4G4R4A4_UNORM
:
206 case PIPE_FORMAT_B4G4R4X4_UNORM
:
207 return V_0280A0_SWAP_ALT
;
209 case PIPE_FORMAT_Z16_UNORM
:
210 return V_0280A0_SWAP_STD
;
212 case PIPE_FORMAT_L8A8_UNORM
:
213 case PIPE_FORMAT_L8A8_SNORM
:
214 case PIPE_FORMAT_L8A8_UINT
:
215 case PIPE_FORMAT_L8A8_SINT
:
216 case PIPE_FORMAT_L8A8_SRGB
:
217 case PIPE_FORMAT_L16A16_UNORM
:
218 case PIPE_FORMAT_L16A16_SNORM
:
219 case PIPE_FORMAT_L16A16_UINT
:
220 case PIPE_FORMAT_L16A16_SINT
:
221 case PIPE_FORMAT_L16A16_FLOAT
:
222 case PIPE_FORMAT_L32A32_UINT
:
223 case PIPE_FORMAT_L32A32_SINT
:
224 case PIPE_FORMAT_L32A32_FLOAT
:
225 return V_0280A0_SWAP_ALT
;
226 case PIPE_FORMAT_R8G8_UNORM
:
227 case PIPE_FORMAT_R8G8_SNORM
:
228 case PIPE_FORMAT_R8G8_UINT
:
229 case PIPE_FORMAT_R8G8_SINT
:
230 return V_0280A0_SWAP_STD
;
232 case PIPE_FORMAT_R16_UNORM
:
233 case PIPE_FORMAT_R16_SNORM
:
234 case PIPE_FORMAT_R16_UINT
:
235 case PIPE_FORMAT_R16_SINT
:
236 case PIPE_FORMAT_R16_FLOAT
:
237 return V_0280A0_SWAP_STD
;
239 /* 32-bit buffers. */
241 case PIPE_FORMAT_A8B8G8R8_SRGB
:
242 return V_0280A0_SWAP_STD_REV
;
243 case PIPE_FORMAT_B8G8R8A8_SRGB
:
244 return V_0280A0_SWAP_ALT
;
246 case PIPE_FORMAT_B8G8R8A8_UNORM
:
247 case PIPE_FORMAT_B8G8R8X8_UNORM
:
248 return V_0280A0_SWAP_ALT
;
250 case PIPE_FORMAT_A8R8G8B8_UNORM
:
251 case PIPE_FORMAT_X8R8G8B8_UNORM
:
252 return V_0280A0_SWAP_ALT_REV
;
253 case PIPE_FORMAT_R8G8B8A8_SNORM
:
254 case PIPE_FORMAT_R8G8B8A8_UNORM
:
255 case PIPE_FORMAT_R8G8B8X8_UNORM
:
256 case PIPE_FORMAT_R8G8B8A8_SINT
:
257 case PIPE_FORMAT_R8G8B8A8_UINT
:
258 return V_0280A0_SWAP_STD
;
260 case PIPE_FORMAT_A8B8G8R8_UNORM
:
261 case PIPE_FORMAT_X8B8G8R8_UNORM
:
262 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
263 return V_0280A0_SWAP_STD_REV
;
265 case PIPE_FORMAT_Z24X8_UNORM
:
266 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
267 return V_0280A0_SWAP_STD
;
269 case PIPE_FORMAT_X8Z24_UNORM
:
270 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
271 return V_0280A0_SWAP_STD
;
273 case PIPE_FORMAT_R10G10B10A2_UNORM
:
274 case PIPE_FORMAT_R10G10B10X2_SNORM
:
275 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
276 return V_0280A0_SWAP_STD
;
278 case PIPE_FORMAT_B10G10R10A2_UNORM
:
279 case PIPE_FORMAT_B10G10R10A2_UINT
:
280 return V_0280A0_SWAP_ALT
;
282 case PIPE_FORMAT_R11G11B10_FLOAT
:
283 case PIPE_FORMAT_R16G16_UNORM
:
284 case PIPE_FORMAT_R16G16_SNORM
:
285 case PIPE_FORMAT_R16G16_FLOAT
:
286 case PIPE_FORMAT_R16G16_UINT
:
287 case PIPE_FORMAT_R16G16_SINT
:
288 case PIPE_FORMAT_R32_UINT
:
289 case PIPE_FORMAT_R32_SINT
:
290 case PIPE_FORMAT_R32_FLOAT
:
291 case PIPE_FORMAT_Z32_FLOAT
:
292 return V_0280A0_SWAP_STD
;
294 /* 64-bit buffers. */
295 case PIPE_FORMAT_R32G32_FLOAT
:
296 case PIPE_FORMAT_R32G32_UINT
:
297 case PIPE_FORMAT_R32G32_SINT
:
298 case PIPE_FORMAT_R16G16B16A16_UNORM
:
299 case PIPE_FORMAT_R16G16B16A16_SNORM
:
300 case PIPE_FORMAT_R16G16B16A16_UINT
:
301 case PIPE_FORMAT_R16G16B16A16_SINT
:
302 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
303 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
305 /* 128-bit buffers. */
306 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
307 case PIPE_FORMAT_R32G32B32A32_SNORM
:
308 case PIPE_FORMAT_R32G32B32A32_UNORM
:
309 case PIPE_FORMAT_R32G32B32A32_SINT
:
310 case PIPE_FORMAT_R32G32B32A32_UINT
:
311 return V_0280A0_SWAP_STD
;
313 R600_ERR("unsupported colorswap format %d\n", format
);
319 static uint32_t r600_translate_colorformat(enum pipe_format format
)
322 case PIPE_FORMAT_L4A4_UNORM
:
323 case PIPE_FORMAT_R4A4_UNORM
:
324 case PIPE_FORMAT_A4R4_UNORM
:
325 return V_0280A0_COLOR_4_4
;
328 case PIPE_FORMAT_A8_UNORM
:
329 case PIPE_FORMAT_A8_SNORM
:
330 case PIPE_FORMAT_A8_UINT
:
331 case PIPE_FORMAT_A8_SINT
:
332 case PIPE_FORMAT_I8_UNORM
:
333 case PIPE_FORMAT_I8_SNORM
:
334 case PIPE_FORMAT_I8_UINT
:
335 case PIPE_FORMAT_I8_SINT
:
336 case PIPE_FORMAT_L8_UNORM
:
337 case PIPE_FORMAT_L8_SNORM
:
338 case PIPE_FORMAT_L8_UINT
:
339 case PIPE_FORMAT_L8_SINT
:
340 case PIPE_FORMAT_L8_SRGB
:
341 case PIPE_FORMAT_R8_UNORM
:
342 case PIPE_FORMAT_R8_SNORM
:
343 case PIPE_FORMAT_R8_UINT
:
344 case PIPE_FORMAT_R8_SINT
:
345 return V_0280A0_COLOR_8
;
347 /* 16-bit buffers. */
348 case PIPE_FORMAT_B5G6R5_UNORM
:
349 return V_0280A0_COLOR_5_6_5
;
351 case PIPE_FORMAT_B5G5R5A1_UNORM
:
352 case PIPE_FORMAT_B5G5R5X1_UNORM
:
353 return V_0280A0_COLOR_1_5_5_5
;
355 case PIPE_FORMAT_B4G4R4A4_UNORM
:
356 case PIPE_FORMAT_B4G4R4X4_UNORM
:
357 return V_0280A0_COLOR_4_4_4_4
;
359 case PIPE_FORMAT_Z16_UNORM
:
360 return V_0280A0_COLOR_16
;
362 case PIPE_FORMAT_L8A8_UNORM
:
363 case PIPE_FORMAT_L8A8_SNORM
:
364 case PIPE_FORMAT_L8A8_UINT
:
365 case PIPE_FORMAT_L8A8_SINT
:
366 case PIPE_FORMAT_L8A8_SRGB
:
367 case PIPE_FORMAT_R8G8_UNORM
:
368 case PIPE_FORMAT_R8G8_SNORM
:
369 case PIPE_FORMAT_R8G8_UINT
:
370 case PIPE_FORMAT_R8G8_SINT
:
371 return V_0280A0_COLOR_8_8
;
373 case PIPE_FORMAT_R16_UNORM
:
374 case PIPE_FORMAT_R16_SNORM
:
375 case PIPE_FORMAT_R16_UINT
:
376 case PIPE_FORMAT_R16_SINT
:
377 case PIPE_FORMAT_A16_UNORM
:
378 case PIPE_FORMAT_A16_SNORM
:
379 case PIPE_FORMAT_A16_UINT
:
380 case PIPE_FORMAT_A16_SINT
:
381 case PIPE_FORMAT_L16_UNORM
:
382 case PIPE_FORMAT_L16_SNORM
:
383 case PIPE_FORMAT_L16_UINT
:
384 case PIPE_FORMAT_L16_SINT
:
385 case PIPE_FORMAT_I16_UNORM
:
386 case PIPE_FORMAT_I16_SNORM
:
387 case PIPE_FORMAT_I16_UINT
:
388 case PIPE_FORMAT_I16_SINT
:
389 return V_0280A0_COLOR_16
;
391 case PIPE_FORMAT_R16_FLOAT
:
392 case PIPE_FORMAT_A16_FLOAT
:
393 case PIPE_FORMAT_L16_FLOAT
:
394 case PIPE_FORMAT_I16_FLOAT
:
395 return V_0280A0_COLOR_16_FLOAT
;
397 /* 32-bit buffers. */
398 case PIPE_FORMAT_A8B8G8R8_SRGB
:
399 case PIPE_FORMAT_A8B8G8R8_UNORM
:
400 case PIPE_FORMAT_A8R8G8B8_UNORM
:
401 case PIPE_FORMAT_B8G8R8A8_SRGB
:
402 case PIPE_FORMAT_B8G8R8A8_UNORM
:
403 case PIPE_FORMAT_B8G8R8X8_UNORM
:
404 case PIPE_FORMAT_R8G8B8A8_SNORM
:
405 case PIPE_FORMAT_R8G8B8A8_UNORM
:
406 case PIPE_FORMAT_R8G8B8X8_UNORM
:
407 case PIPE_FORMAT_R8SG8SB8UX8U_NORM
:
408 case PIPE_FORMAT_X8B8G8R8_UNORM
:
409 case PIPE_FORMAT_X8R8G8B8_UNORM
:
410 case PIPE_FORMAT_R8G8B8A8_SINT
:
411 case PIPE_FORMAT_R8G8B8A8_UINT
:
412 return V_0280A0_COLOR_8_8_8_8
;
414 case PIPE_FORMAT_R10G10B10A2_UNORM
:
415 case PIPE_FORMAT_R10G10B10X2_SNORM
:
416 case PIPE_FORMAT_B10G10R10A2_UNORM
:
417 case PIPE_FORMAT_B10G10R10A2_UINT
:
418 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
419 return V_0280A0_COLOR_2_10_10_10
;
421 case PIPE_FORMAT_Z24X8_UNORM
:
422 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
423 return V_0280A0_COLOR_8_24
;
425 case PIPE_FORMAT_X8Z24_UNORM
:
426 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
427 return V_0280A0_COLOR_24_8
;
429 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
430 return V_0280A0_COLOR_X24_8_32_FLOAT
;
432 case PIPE_FORMAT_R32_UINT
:
433 case PIPE_FORMAT_R32_SINT
:
434 case PIPE_FORMAT_A32_UINT
:
435 case PIPE_FORMAT_A32_SINT
:
436 case PIPE_FORMAT_L32_UINT
:
437 case PIPE_FORMAT_L32_SINT
:
438 case PIPE_FORMAT_I32_UINT
:
439 case PIPE_FORMAT_I32_SINT
:
440 return V_0280A0_COLOR_32
;
442 case PIPE_FORMAT_R32_FLOAT
:
443 case PIPE_FORMAT_A32_FLOAT
:
444 case PIPE_FORMAT_L32_FLOAT
:
445 case PIPE_FORMAT_I32_FLOAT
:
446 case PIPE_FORMAT_Z32_FLOAT
:
447 return V_0280A0_COLOR_32_FLOAT
;
449 case PIPE_FORMAT_R16G16_FLOAT
:
450 case PIPE_FORMAT_L16A16_FLOAT
:
451 return V_0280A0_COLOR_16_16_FLOAT
;
453 case PIPE_FORMAT_R16G16_UNORM
:
454 case PIPE_FORMAT_R16G16_SNORM
:
455 case PIPE_FORMAT_R16G16_UINT
:
456 case PIPE_FORMAT_R16G16_SINT
:
457 case PIPE_FORMAT_L16A16_UNORM
:
458 case PIPE_FORMAT_L16A16_SNORM
:
459 case PIPE_FORMAT_L16A16_UINT
:
460 case PIPE_FORMAT_L16A16_SINT
:
461 return V_0280A0_COLOR_16_16
;
463 case PIPE_FORMAT_R11G11B10_FLOAT
:
464 return V_0280A0_COLOR_10_11_11_FLOAT
;
466 /* 64-bit buffers. */
467 case PIPE_FORMAT_R16G16B16A16_UINT
:
468 case PIPE_FORMAT_R16G16B16A16_SINT
:
469 case PIPE_FORMAT_R16G16B16A16_UNORM
:
470 case PIPE_FORMAT_R16G16B16A16_SNORM
:
471 return V_0280A0_COLOR_16_16_16_16
;
473 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
474 return V_0280A0_COLOR_16_16_16_16_FLOAT
;
476 case PIPE_FORMAT_R32G32_FLOAT
:
477 case PIPE_FORMAT_L32A32_FLOAT
:
478 return V_0280A0_COLOR_32_32_FLOAT
;
480 case PIPE_FORMAT_R32G32_SINT
:
481 case PIPE_FORMAT_R32G32_UINT
:
482 case PIPE_FORMAT_L32A32_UINT
:
483 case PIPE_FORMAT_L32A32_SINT
:
484 return V_0280A0_COLOR_32_32
;
486 /* 128-bit buffers. */
487 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
488 return V_0280A0_COLOR_32_32_32_32_FLOAT
;
489 case PIPE_FORMAT_R32G32B32A32_SNORM
:
490 case PIPE_FORMAT_R32G32B32A32_UNORM
:
491 case PIPE_FORMAT_R32G32B32A32_SINT
:
492 case PIPE_FORMAT_R32G32B32A32_UINT
:
493 return V_0280A0_COLOR_32_32_32_32
;
496 case PIPE_FORMAT_UYVY
:
497 case PIPE_FORMAT_YUYV
:
499 return ~0U; /* Unsupported. */
503 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat
)
505 if (R600_BIG_ENDIAN
) {
506 switch(colorformat
) {
507 case V_0280A0_COLOR_4_4
:
511 case V_0280A0_COLOR_8
:
514 /* 16-bit buffers. */
515 case V_0280A0_COLOR_5_6_5
:
516 case V_0280A0_COLOR_1_5_5_5
:
517 case V_0280A0_COLOR_4_4_4_4
:
518 case V_0280A0_COLOR_16
:
519 case V_0280A0_COLOR_8_8
:
522 /* 32-bit buffers. */
523 case V_0280A0_COLOR_8_8_8_8
:
524 case V_0280A0_COLOR_2_10_10_10
:
525 case V_0280A0_COLOR_8_24
:
526 case V_0280A0_COLOR_24_8
:
527 case V_0280A0_COLOR_32_FLOAT
:
528 case V_0280A0_COLOR_16_16_FLOAT
:
529 case V_0280A0_COLOR_16_16
:
532 /* 64-bit buffers. */
533 case V_0280A0_COLOR_16_16_16_16
:
534 case V_0280A0_COLOR_16_16_16_16_FLOAT
:
537 case V_0280A0_COLOR_32_32_FLOAT
:
538 case V_0280A0_COLOR_32_32
:
539 case V_0280A0_COLOR_X24_8_32_FLOAT
:
542 /* 128-bit buffers. */
543 case V_0280A0_COLOR_32_32_32_FLOAT
:
544 case V_0280A0_COLOR_32_32_32_32_FLOAT
:
545 case V_0280A0_COLOR_32_32_32_32
:
548 return ENDIAN_NONE
; /* Unsupported. */
555 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
557 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
) != ~0U;
560 static bool r600_is_colorbuffer_format_supported(enum pipe_format format
)
562 return r600_translate_colorformat(format
) != ~0U &&
563 r600_translate_colorswap(format
) != ~0U;
566 static bool r600_is_zs_format_supported(enum pipe_format format
)
568 return r600_translate_dbformat(format
) != ~0U;
571 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
572 enum pipe_format format
,
573 enum pipe_texture_target target
,
574 unsigned sample_count
,
577 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
580 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
581 R600_ERR("r600: unsupported texture type %d\n", target
);
585 if (!util_format_is_supported(format
, usage
))
588 if (sample_count
> 1) {
589 if (!rscreen
->has_msaa
)
592 /* R11G11B10 is broken on R6xx. */
593 if (rscreen
->chip_class
== R600
&&
594 format
== PIPE_FORMAT_R11G11B10_FLOAT
)
597 /* MSAA integer colorbuffers hang. */
598 if (util_format_is_pure_integer(format
) &&
599 !util_format_is_depth_or_stencil(format
))
602 switch (sample_count
) {
612 if ((usage
& PIPE_BIND_SAMPLER_VIEW
) &&
613 r600_is_sampler_format_supported(screen
, format
)) {
614 retval
|= PIPE_BIND_SAMPLER_VIEW
;
617 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
618 PIPE_BIND_DISPLAY_TARGET
|
620 PIPE_BIND_SHARED
)) &&
621 r600_is_colorbuffer_format_supported(format
)) {
623 (PIPE_BIND_RENDER_TARGET
|
624 PIPE_BIND_DISPLAY_TARGET
|
629 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
630 r600_is_zs_format_supported(format
)) {
631 retval
|= PIPE_BIND_DEPTH_STENCIL
;
634 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
635 r600_is_vertex_format_supported(format
)) {
636 retval
|= PIPE_BIND_VERTEX_BUFFER
;
639 if (usage
& PIPE_BIND_TRANSFER_READ
)
640 retval
|= PIPE_BIND_TRANSFER_READ
;
641 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
642 retval
|= PIPE_BIND_TRANSFER_WRITE
;
644 return retval
== usage
;
647 static void r600_emit_polygon_offset(struct r600_context
*rctx
, struct r600_atom
*a
)
649 struct radeon_winsys_cs
*cs
= rctx
->cs
;
650 struct r600_poly_offset_state
*state
= (struct r600_poly_offset_state
*)a
;
651 float offset_units
= state
->offset_units
;
652 float offset_scale
= state
->offset_scale
;
654 switch (state
->zs_format
) {
655 case PIPE_FORMAT_Z24X8_UNORM
:
656 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
657 offset_units
*= 2.0f
;
659 case PIPE_FORMAT_Z16_UNORM
:
660 offset_units
*= 4.0f
;
665 r600_write_context_reg_seq(cs
, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE
, 4);
666 r600_write_value(cs
, fui(offset_scale
));
667 r600_write_value(cs
, fui(offset_units
));
668 r600_write_value(cs
, fui(offset_scale
));
669 r600_write_value(cs
, fui(offset_units
));
672 static uint32_t r600_get_blend_control(const struct pipe_blend_state
*state
, unsigned i
)
674 int j
= state
->independent_blend_enable
? i
: 0;
676 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
677 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
678 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
680 unsigned eqA
= state
->rt
[j
].alpha_func
;
681 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
682 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
685 if (!state
->rt
[j
].blend_enable
)
688 bc
|= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
689 bc
|= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
690 bc
|= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
692 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
693 bc
|= S_028804_SEPARATE_ALPHA_BLEND(1);
694 bc
|= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
695 bc
|= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
696 bc
|= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
701 static void *r600_create_blend_state_mode(struct pipe_context
*ctx
,
702 const struct pipe_blend_state
*state
,
705 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
706 uint32_t color_control
= 0, target_mask
= 0;
707 struct r600_blend_state
*blend
= CALLOC_STRUCT(r600_blend_state
);
713 r600_init_command_buffer(&blend
->buffer
, 20);
714 r600_init_command_buffer(&blend
->buffer_no_blend
, 20);
716 /* R600 does not support per-MRT blends */
717 if (rctx
->family
> CHIP_R600
)
718 color_control
|= S_028808_PER_MRT_BLEND(1);
720 if (state
->logicop_enable
) {
721 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
723 color_control
|= (0xcc << 16);
725 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
726 if (state
->independent_blend_enable
) {
727 for (int i
= 0; i
< 8; i
++) {
728 if (state
->rt
[i
].blend_enable
) {
729 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
731 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
734 for (int i
= 0; i
< 8; i
++) {
735 if (state
->rt
[0].blend_enable
) {
736 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
738 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
743 color_control
|= S_028808_SPECIAL_OP(mode
);
745 color_control
|= S_028808_SPECIAL_OP(V_028808_DISABLE
);
747 /* only MRT0 has dual src blend */
748 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
749 blend
->cb_target_mask
= target_mask
;
750 blend
->cb_color_control
= color_control
;
751 blend
->cb_color_control_no_blend
= color_control
& C_028808_TARGET_BLEND_ENABLE
;
752 blend
->alpha_to_one
= state
->alpha_to_one
;
754 r600_store_context_reg(&blend
->buffer
, R_028D44_DB_ALPHA_TO_MASK
,
755 S_028D44_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
756 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
757 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
758 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
759 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
761 /* Copy over the registers set so far into buffer_no_blend. */
762 memcpy(blend
->buffer_no_blend
.buf
, blend
->buffer
.buf
, blend
->buffer
.num_dw
* 4);
763 blend
->buffer_no_blend
.num_dw
= blend
->buffer
.num_dw
;
765 /* Only add blend registers if blending is enabled. */
766 if (!G_028808_TARGET_BLEND_ENABLE(color_control
)) {
770 /* The first R600 does not support per-MRT blends */
771 r600_store_context_reg(&blend
->buffer
, R_028804_CB_BLEND_CONTROL
,
772 r600_get_blend_control(state
, 0));
774 if (rctx
->family
> CHIP_R600
) {
775 r600_store_context_reg_seq(&blend
->buffer
, R_028780_CB_BLEND0_CONTROL
, 8);
776 for (int i
= 0; i
< 8; i
++) {
777 r600_store_value(&blend
->buffer
, r600_get_blend_control(state
, i
));
783 static void *r600_create_blend_state(struct pipe_context
*ctx
,
784 const struct pipe_blend_state
*state
)
786 return r600_create_blend_state_mode(ctx
, state
, V_028808_SPECIAL_NORMAL
);
789 static void *r600_create_dsa_state(struct pipe_context
*ctx
,
790 const struct pipe_depth_stencil_alpha_state
*state
)
792 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
793 struct r600_dsa_state
*dsa
= CALLOC_STRUCT(r600_dsa_state
);
799 r600_init_command_buffer(&dsa
->buffer
, 3);
801 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
802 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
803 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
804 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
806 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
807 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
808 S_028800_ZFUNC(state
->depth
.func
);
811 if (state
->stencil
[0].enabled
) {
812 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
813 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
814 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
815 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
816 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
818 if (state
->stencil
[1].enabled
) {
819 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
820 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
821 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
822 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
823 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
828 alpha_test_control
= 0;
830 if (state
->alpha
.enabled
) {
831 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
832 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
833 alpha_ref
= fui(state
->alpha
.ref_value
);
835 dsa
->sx_alpha_test_control
= alpha_test_control
& 0xff;
836 dsa
->alpha_ref
= alpha_ref
;
838 r600_store_context_reg(&dsa
->buffer
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
842 static void *r600_create_rs_state(struct pipe_context
*ctx
,
843 const struct pipe_rasterizer_state
*state
)
845 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
846 unsigned tmp
, sc_mode_cntl
, spi_interp
;
847 float psize_min
, psize_max
;
848 struct r600_rasterizer_state
*rs
= CALLOC_STRUCT(r600_rasterizer_state
);
854 r600_init_command_buffer(&rs
->buffer
, 30);
856 rs
->flatshade
= state
->flatshade
;
857 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
858 rs
->two_side
= state
->light_twoside
;
859 rs
->clip_plane_enable
= state
->clip_plane_enable
;
860 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
861 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
862 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
863 rs
->pa_cl_clip_cntl
=
864 S_028810_PS_UCP_MODE(3) |
865 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
866 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
867 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
868 rs
->multisample_enable
= state
->multisample
;
871 rs
->offset_units
= state
->offset_units
;
872 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
873 rs
->offset_enable
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
875 if (state
->point_size_per_vertex
) {
876 psize_min
= util_get_min_point_size(state
);
879 /* Force the point size to be as if the vertex output was disabled. */
880 psize_min
= state
->point_size
;
881 psize_max
= state
->point_size
;
884 sc_mode_cntl
= S_028A4C_MSAA_ENABLE(state
->multisample
) |
885 S_028A4C_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
886 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
887 if (rctx
->chip_class
>= R700
) {
888 sc_mode_cntl
|= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
889 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
890 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state
->scissor
);
892 sc_mode_cntl
|= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
893 rs
->scissor_enable
= state
->scissor
;
896 spi_interp
= S_0286D4_FLAT_SHADE_ENA(1);
897 if (state
->sprite_coord_enable
) {
898 spi_interp
|= S_0286D4_PNT_SPRITE_ENA(1) |
899 S_0286D4_PNT_SPRITE_OVRD_X(2) |
900 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
901 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
902 S_0286D4_PNT_SPRITE_OVRD_W(1);
903 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
904 spi_interp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
908 r600_store_context_reg_seq(&rs
->buffer
, R_028A00_PA_SU_POINT_SIZE
, 3);
909 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
910 tmp
= r600_pack_float_12p4(state
->point_size
/2);
911 r600_store_value(&rs
->buffer
, /* R_028A00_PA_SU_POINT_SIZE */
912 S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
913 r600_store_value(&rs
->buffer
, /* R_028A04_PA_SU_POINT_MINMAX */
914 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
915 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
916 r600_store_value(&rs
->buffer
, /* R_028A08_PA_SU_LINE_CNTL */
917 S_028A08_WIDTH(r600_pack_float_12p4(state
->line_width
/2)));
919 r600_store_context_reg(&rs
->buffer
, R_0286D4_SPI_INTERP_CONTROL_0
, spi_interp
);
920 r600_store_context_reg(&rs
->buffer
, R_028A4C_PA_SC_MODE_CNTL
, sc_mode_cntl
);
921 r600_store_context_reg(&rs
->buffer
, R_028C08_PA_SU_VTX_CNTL
,
922 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
) |
923 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
924 r600_store_context_reg(&rs
->buffer
, R_028DFC_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
925 r600_store_context_reg(&rs
->buffer
, R_028814_PA_SU_SC_MODE_CNTL
,
926 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
927 S_028814_CULL_FRONT(state
->cull_face
& PIPE_FACE_FRONT
? 1 : 0) |
928 S_028814_CULL_BACK(state
->cull_face
& PIPE_FACE_BACK
? 1 : 0) |
929 S_028814_FACE(!state
->front_ccw
) |
930 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
931 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
932 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
933 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
934 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
935 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
936 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)));
937 r600_store_context_reg(&rs
->buffer
, R_028350_SX_MISC
, S_028350_MULTIPASS(state
->rasterizer_discard
));
941 static void *r600_create_sampler_state(struct pipe_context
*ctx
,
942 const struct pipe_sampler_state
*state
)
944 struct r600_pipe_sampler_state
*ss
= CALLOC_STRUCT(r600_pipe_sampler_state
);
945 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 4 : 0;
951 ss
->seamless_cube_map
= state
->seamless_cube_map
;
952 ss
->border_color_use
= sampler_state_needs_border_color(state
);
954 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
955 ss
->tex_sampler_words
[0] =
956 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
957 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
958 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
959 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
960 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
961 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
962 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
963 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
964 S_03C000_BORDER_COLOR_TYPE(ss
->border_color_use
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0);
965 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
966 ss
->tex_sampler_words
[1] =
967 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 6)) |
968 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 6)) |
969 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 6));
970 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
971 ss
->tex_sampler_words
[2] = S_03C008_TYPE(1);
973 if (ss
->border_color_use
) {
974 memcpy(&ss
->border_color
, &state
->border_color
, sizeof(state
->border_color
));
979 struct pipe_sampler_view
*
980 r600_create_sampler_view_custom(struct pipe_context
*ctx
,
981 struct pipe_resource
*texture
,
982 const struct pipe_sampler_view
*state
,
983 unsigned width_first_level
, unsigned height_first_level
)
985 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
986 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
987 unsigned format
, endian
;
988 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
989 unsigned char swizzle
[4], array_mode
= 0;
990 unsigned width
, height
, depth
, offset_level
, last_level
;
995 /* initialize base object */
997 view
->base
.texture
= NULL
;
998 pipe_reference(NULL
, &texture
->reference
);
999 view
->base
.texture
= texture
;
1000 view
->base
.reference
.count
= 1;
1001 view
->base
.context
= ctx
;
1003 swizzle
[0] = state
->swizzle_r
;
1004 swizzle
[1] = state
->swizzle_g
;
1005 swizzle
[2] = state
->swizzle_b
;
1006 swizzle
[3] = state
->swizzle_a
;
1008 format
= r600_translate_texformat(ctx
->screen
, state
->format
,
1010 &word4
, &yuv_format
);
1011 assert(format
!= ~0);
1017 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
&& !r600_can_read_depth(tmp
)) {
1018 if (!r600_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
1022 tmp
= tmp
->flushed_depth_texture
;
1025 endian
= r600_colorformat_endian_swap(format
);
1027 offset_level
= state
->u
.tex
.first_level
;
1028 last_level
= state
->u
.tex
.last_level
- offset_level
;
1029 width
= width_first_level
;
1030 height
= height_first_level
;
1031 depth
= tmp
->surface
.level
[offset_level
].npix_z
;
1032 pitch
= tmp
->surface
.level
[offset_level
].nblk_x
* util_format_get_blockwidth(state
->format
);
1034 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
1036 depth
= texture
->array_size
;
1037 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
1038 depth
= texture
->array_size
;
1039 } else if (texture
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
1040 depth
= texture
->array_size
/ 6;
1041 switch (tmp
->surface
.level
[offset_level
].mode
) {
1042 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1043 array_mode
= V_038000_ARRAY_LINEAR_ALIGNED
;
1045 case RADEON_SURF_MODE_1D
:
1046 array_mode
= V_038000_ARRAY_1D_TILED_THIN1
;
1048 case RADEON_SURF_MODE_2D
:
1049 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
1051 case RADEON_SURF_MODE_LINEAR
:
1053 array_mode
= V_038000_ARRAY_LINEAR_GENERAL
;
1057 view
->tex_resource
= &tmp
->resource
;
1058 view
->tex_resource_words
[0] = (S_038000_DIM(r600_tex_dim(texture
->target
, texture
->nr_samples
)) |
1059 S_038000_TILE_MODE(array_mode
) |
1060 S_038000_TILE_TYPE(tmp
->non_disp_tiling
) |
1061 S_038000_PITCH((pitch
/ 8) - 1) |
1062 S_038000_TEX_WIDTH(width
- 1));
1063 view
->tex_resource_words
[1] = (S_038004_TEX_HEIGHT(height
- 1) |
1064 S_038004_TEX_DEPTH(depth
- 1) |
1065 S_038004_DATA_FORMAT(format
));
1066 view
->tex_resource_words
[2] = tmp
->surface
.level
[offset_level
].offset
>> 8;
1067 if (offset_level
>= tmp
->surface
.last_level
) {
1068 view
->tex_resource_words
[3] = tmp
->surface
.level
[offset_level
].offset
>> 8;
1070 view
->tex_resource_words
[3] = tmp
->surface
.level
[offset_level
+ 1].offset
>> 8;
1072 view
->tex_resource_words
[4] = (word4
|
1073 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE
) |
1074 S_038010_REQUEST_SIZE(1) |
1075 S_038010_ENDIAN_SWAP(endian
) |
1076 S_038010_BASE_LEVEL(0));
1077 view
->tex_resource_words
[5] = (S_038014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
1078 S_038014_LAST_ARRAY(state
->u
.tex
.last_layer
));
1079 if (texture
->nr_samples
> 1) {
1080 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1081 view
->tex_resource_words
[5] |= S_038014_LAST_LEVEL(util_logbase2(texture
->nr_samples
));
1083 view
->tex_resource_words
[5] |= S_038014_LAST_LEVEL(last_level
);
1085 view
->tex_resource_words
[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE
) |
1086 S_038018_MAX_ANISO(4 /* max 16 samples */));
1090 static struct pipe_sampler_view
*
1091 r600_create_sampler_view(struct pipe_context
*ctx
,
1092 struct pipe_resource
*tex
,
1093 const struct pipe_sampler_view
*state
)
1095 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1097 return r600_create_sampler_view_custom(ctx
, tex
, state
,
1098 rtex
->surface
.level
[state
->u
.tex
.first_level
].npix_x
,
1099 rtex
->surface
.level
[state
->u
.tex
.first_level
].npix_y
);
1102 static void r600_emit_clip_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1104 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1105 struct pipe_clip_state
*state
= &rctx
->clip_state
.state
;
1107 r600_write_context_reg_seq(cs
, R_028E20_PA_CL_UCP0_X
, 6*4);
1108 r600_write_array(cs
, 6*4, (unsigned*)state
);
1111 static void r600_set_polygon_stipple(struct pipe_context
*ctx
,
1112 const struct pipe_poly_stipple
*state
)
1116 static void r600_emit_scissor_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1118 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1119 struct pipe_scissor_state
*state
= &rctx
->scissor
.scissor
;
1121 if (rctx
->chip_class
!= R600
|| rctx
->scissor
.enable
) {
1122 r600_write_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 2);
1123 r600_write_value(cs
, S_028240_TL_X(state
->minx
) | S_028240_TL_Y(state
->miny
) |
1124 S_028240_WINDOW_OFFSET_DISABLE(1));
1125 r600_write_value(cs
, S_028244_BR_X(state
->maxx
) | S_028244_BR_Y(state
->maxy
));
1127 r600_write_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 2);
1128 r600_write_value(cs
, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1129 S_028240_WINDOW_OFFSET_DISABLE(1));
1130 r600_write_value(cs
, S_028244_BR_X(8192) | S_028244_BR_Y(8192));
1134 static void r600_set_scissor_state(struct pipe_context
*ctx
,
1135 const struct pipe_scissor_state
*state
)
1137 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1139 rctx
->scissor
.scissor
= *state
;
1141 if (rctx
->chip_class
== R600
&& !rctx
->scissor
.enable
)
1144 rctx
->scissor
.atom
.dirty
= true;
1147 static struct r600_resource
*r600_buffer_create_helper(struct r600_screen
*rscreen
,
1148 unsigned size
, unsigned alignment
)
1150 struct pipe_resource buffer
;
1152 memset(&buffer
, 0, sizeof buffer
);
1153 buffer
.target
= PIPE_BUFFER
;
1154 buffer
.format
= PIPE_FORMAT_R8_UNORM
;
1155 buffer
.bind
= PIPE_BIND_CUSTOM
;
1156 buffer
.usage
= PIPE_USAGE_STATIC
;
1158 buffer
.width0
= size
;
1161 buffer
.array_size
= 1;
1163 return (struct r600_resource
*)
1164 r600_buffer_create(&rscreen
->screen
, &buffer
, alignment
);
1167 static void r600_init_color_surface(struct r600_context
*rctx
,
1168 struct r600_surface
*surf
,
1169 bool force_cmask_fmask
)
1171 struct r600_screen
*rscreen
= rctx
->screen
;
1172 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1173 unsigned level
= surf
->base
.u
.tex
.level
;
1174 unsigned pitch
, slice
;
1175 unsigned color_info
;
1176 unsigned format
, swap
, ntype
, endian
;
1178 const struct util_format_description
*desc
;
1180 bool blend_bypass
= 0, blend_clamp
= 1;
1182 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
&& !r600_can_read_depth(rtex
)) {
1183 r600_init_flushed_depth_texture(&rctx
->context
, surf
->base
.texture
, NULL
);
1184 rtex
= rtex
->flushed_depth_texture
;
1188 offset
= rtex
->surface
.level
[level
].offset
;
1189 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1190 offset
+= rtex
->surface
.level
[level
].slice_size
*
1191 surf
->base
.u
.tex
.first_layer
;
1193 pitch
= rtex
->surface
.level
[level
].nblk_x
/ 8 - 1;
1194 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1199 switch (rtex
->surface
.level
[level
].mode
) {
1200 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1201 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED
);
1203 case RADEON_SURF_MODE_1D
:
1204 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1
);
1206 case RADEON_SURF_MODE_2D
:
1207 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1
);
1209 case RADEON_SURF_MODE_LINEAR
:
1211 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL
);
1215 desc
= util_format_description(surf
->base
.format
);
1217 for (i
= 0; i
< 4; i
++) {
1218 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1223 ntype
= V_0280A0_NUMBER_UNORM
;
1224 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1225 ntype
= V_0280A0_NUMBER_SRGB
;
1226 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1227 if (desc
->channel
[i
].normalized
)
1228 ntype
= V_0280A0_NUMBER_SNORM
;
1229 else if (desc
->channel
[i
].pure_integer
)
1230 ntype
= V_0280A0_NUMBER_SINT
;
1231 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1232 if (desc
->channel
[i
].normalized
)
1233 ntype
= V_0280A0_NUMBER_UNORM
;
1234 else if (desc
->channel
[i
].pure_integer
)
1235 ntype
= V_0280A0_NUMBER_UINT
;
1238 format
= r600_translate_colorformat(surf
->base
.format
);
1239 assert(format
!= ~0);
1241 swap
= r600_translate_colorswap(surf
->base
.format
);
1244 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1245 endian
= ENDIAN_NONE
;
1247 endian
= r600_colorformat_endian_swap(format
);
1250 /* set blend bypass according to docs if SINT/UINT or
1251 8/24 COLOR variants */
1252 if (ntype
== V_0280A0_NUMBER_UINT
|| ntype
== V_0280A0_NUMBER_SINT
||
1253 format
== V_0280A0_COLOR_8_24
|| format
== V_0280A0_COLOR_24_8
||
1254 format
== V_0280A0_COLOR_X24_8_32_FLOAT
) {
1259 surf
->alphatest_bypass
= ntype
== V_0280A0_NUMBER_UINT
|| ntype
== V_0280A0_NUMBER_SINT
;
1261 color_info
|= S_0280A0_FORMAT(format
) |
1262 S_0280A0_COMP_SWAP(swap
) |
1263 S_0280A0_BLEND_BYPASS(blend_bypass
) |
1264 S_0280A0_BLEND_CLAMP(blend_clamp
) |
1265 S_0280A0_NUMBER_TYPE(ntype
) |
1266 S_0280A0_ENDIAN(endian
);
1268 /* EXPORT_NORM is an optimzation that can be enabled for better
1269 * performance in certain cases
1271 if (rctx
->chip_class
== R600
) {
1272 /* EXPORT_NORM can be enabled if:
1273 * - 11-bit or smaller UNORM/SNORM/SRGB
1274 * - BLEND_CLAMP is enabled
1275 * - BLEND_FLOAT32 is disabled
1277 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1278 (desc
->channel
[i
].size
< 12 &&
1279 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1280 ntype
!= V_0280A0_NUMBER_UINT
&&
1281 ntype
!= V_0280A0_NUMBER_SINT
) &&
1282 G_0280A0_BLEND_CLAMP(color_info
) &&
1283 !G_0280A0_BLEND_FLOAT32(color_info
)) {
1284 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
1285 surf
->export_16bpc
= true;
1288 /* EXPORT_NORM can be enabled if:
1289 * - 11-bit or smaller UNORM/SNORM/SRGB
1290 * - 16-bit or smaller FLOAT
1292 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1293 ((desc
->channel
[i
].size
< 12 &&
1294 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1295 ntype
!= V_0280A0_NUMBER_UINT
&& ntype
!= V_0280A0_NUMBER_SINT
) ||
1296 (desc
->channel
[i
].size
< 17 &&
1297 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
1298 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
1299 surf
->export_16bpc
= true;
1303 /* These might not always be initialized to zero. */
1304 surf
->cb_color_base
= offset
>> 8;
1305 surf
->cb_color_size
= S_028060_PITCH_TILE_MAX(pitch
) |
1306 S_028060_SLICE_TILE_MAX(slice
);
1307 surf
->cb_color_fmask
= surf
->cb_color_base
;
1308 surf
->cb_color_cmask
= surf
->cb_color_base
;
1309 surf
->cb_color_mask
= 0;
1311 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
,
1312 &rtex
->resource
.b
.b
);
1313 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
,
1314 &rtex
->resource
.b
.b
);
1316 if (rtex
->cmask_size
) {
1317 surf
->cb_color_cmask
= rtex
->cmask_offset
>> 8;
1318 surf
->cb_color_mask
|= S_028100_CMASK_BLOCK_MAX(rtex
->cmask_slice_tile_max
);
1320 if (rtex
->fmask_size
) {
1321 color_info
|= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE
);
1322 surf
->cb_color_fmask
= rtex
->fmask_offset
>> 8;
1323 surf
->cb_color_mask
|= S_028100_FMASK_TILE_MAX(slice
);
1324 } else { /* cmask only */
1325 color_info
|= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE
);
1327 } else if (force_cmask_fmask
) {
1328 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1330 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1331 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1332 * because it's not an MSAA buffer.
1334 struct r600_cmask_info cmask
;
1335 struct r600_fmask_info fmask
;
1337 r600_texture_get_cmask_info(rscreen
, rtex
, &cmask
);
1338 r600_texture_get_fmask_info(rscreen
, rtex
, 8, &fmask
);
1341 if (!rctx
->dummy_cmask
||
1342 rctx
->dummy_cmask
->buf
->size
< cmask
.size
||
1343 rctx
->dummy_cmask
->buf
->alignment
% cmask
.alignment
!= 0) {
1344 struct pipe_transfer
*transfer
;
1347 pipe_resource_reference((struct pipe_resource
**)&rctx
->dummy_cmask
, NULL
);
1348 rctx
->dummy_cmask
= r600_buffer_create_helper(rscreen
, cmask
.size
, cmask
.alignment
);
1350 /* Set the contents to 0xCC. */
1351 ptr
= pipe_buffer_map(&rctx
->context
, &rctx
->dummy_cmask
->b
.b
, PIPE_TRANSFER_WRITE
, &transfer
);
1352 memset(ptr
, 0xCC, cmask
.size
);
1353 pipe_buffer_unmap(&rctx
->context
, transfer
);
1355 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
,
1356 &rctx
->dummy_cmask
->b
.b
);
1359 if (!rctx
->dummy_fmask
||
1360 rctx
->dummy_fmask
->buf
->size
< fmask
.size
||
1361 rctx
->dummy_fmask
->buf
->alignment
% fmask
.alignment
!= 0) {
1362 pipe_resource_reference((struct pipe_resource
**)&rctx
->dummy_fmask
, NULL
);
1363 rctx
->dummy_fmask
= r600_buffer_create_helper(rscreen
, fmask
.size
, fmask
.alignment
);
1366 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
,
1367 &rctx
->dummy_fmask
->b
.b
);
1369 /* Init the registers. */
1370 color_info
|= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE
);
1371 surf
->cb_color_cmask
= 0;
1372 surf
->cb_color_fmask
= 0;
1373 surf
->cb_color_mask
= S_028100_CMASK_BLOCK_MAX(cmask
.slice_tile_max
) |
1374 S_028100_FMASK_TILE_MAX(slice
);
1377 surf
->cb_color_info
= color_info
;
1379 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1380 surf
->cb_color_view
= 0;
1382 surf
->cb_color_view
= S_028080_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1383 S_028080_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1386 surf
->color_initialized
= true;
1389 static void r600_init_depth_surface(struct r600_context
*rctx
,
1390 struct r600_surface
*surf
)
1392 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1393 unsigned level
, pitch
, slice
, format
, offset
, array_mode
;
1395 level
= surf
->base
.u
.tex
.level
;
1396 offset
= rtex
->surface
.level
[level
].offset
;
1397 pitch
= rtex
->surface
.level
[level
].nblk_x
/ 8 - 1;
1398 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1402 switch (rtex
->surface
.level
[level
].mode
) {
1403 case RADEON_SURF_MODE_2D
:
1404 array_mode
= V_0280A0_ARRAY_2D_TILED_THIN1
;
1406 case RADEON_SURF_MODE_1D
:
1407 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1408 case RADEON_SURF_MODE_LINEAR
:
1410 array_mode
= V_0280A0_ARRAY_1D_TILED_THIN1
;
1414 format
= r600_translate_dbformat(surf
->base
.format
);
1415 assert(format
!= ~0);
1417 surf
->db_depth_info
= S_028010_ARRAY_MODE(array_mode
) | S_028010_FORMAT(format
);
1418 surf
->db_depth_base
= offset
>> 8;
1419 surf
->db_depth_view
= S_028004_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1420 S_028004_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1421 surf
->db_depth_size
= S_028000_PITCH_TILE_MAX(pitch
) | S_028000_SLICE_TILE_MAX(slice
);
1422 surf
->db_prefetch_limit
= (rtex
->surface
.level
[level
].nblk_y
/ 8) - 1;
1424 switch (surf
->base
.format
) {
1425 case PIPE_FORMAT_Z24X8_UNORM
:
1426 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1427 surf
->pa_su_poly_offset_db_fmt_cntl
=
1428 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1430 case PIPE_FORMAT_Z32_FLOAT
:
1431 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1432 surf
->pa_su_poly_offset_db_fmt_cntl
=
1433 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1434 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1436 case PIPE_FORMAT_Z16_UNORM
:
1437 surf
->pa_su_poly_offset_db_fmt_cntl
=
1438 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1443 surf
->htile_enabled
= 0;
1444 /* use htile only for first level */
1445 if (rtex
->htile
&& !level
) {
1446 surf
->htile_enabled
= 1;
1447 surf
->db_htile_data_base
= 0;
1448 surf
->db_htile_surface
= S_028D24_HTILE_WIDTH(1) |
1449 S_028D24_HTILE_HEIGHT(1) |
1451 /* preload is not working properly on r6xx/r7xx */
1452 surf
->db_depth_info
|= S_028010_TILE_SURFACE_ENABLE(1);
1455 surf
->depth_initialized
= true;
1458 static void r600_set_framebuffer_state(struct pipe_context
*ctx
,
1459 const struct pipe_framebuffer_state
*state
)
1461 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1462 struct r600_surface
*surf
;
1463 struct r600_texture
*rtex
;
1466 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1467 rctx
->flags
|= R600_CONTEXT_WAIT_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
1469 if (rctx
->chip_class
>= R700
&&
1470 rctx
->framebuffer
.state
.cbufs
[0]->texture
->nr_samples
> 1) {
1471 rctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV_CB_META
;
1474 if (rctx
->framebuffer
.state
.zsbuf
) {
1475 rctx
->flags
|= R600_CONTEXT_WAIT_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
1478 /* Set the new state. */
1479 util_copy_framebuffer_state(&rctx
->framebuffer
.state
, state
);
1481 rctx
->framebuffer
.export_16bpc
= state
->nr_cbufs
!= 0;
1482 rctx
->framebuffer
.cb0_is_integer
= state
->nr_cbufs
&&
1483 util_format_is_pure_integer(state
->cbufs
[0]->format
);
1484 rctx
->framebuffer
.compressed_cb_mask
= 0;
1485 rctx
->framebuffer
.is_msaa_resolve
= state
->nr_cbufs
== 2 &&
1486 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
1487 state
->cbufs
[1]->texture
->nr_samples
<= 1;
1489 if (state
->nr_cbufs
)
1490 rctx
->framebuffer
.nr_samples
= state
->cbufs
[0]->texture
->nr_samples
;
1491 else if (state
->zsbuf
)
1492 rctx
->framebuffer
.nr_samples
= state
->zsbuf
->texture
->nr_samples
;
1494 rctx
->framebuffer
.nr_samples
= 0;
1497 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
1498 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1499 bool force_cmask_fmask
= rctx
->chip_class
== R600
&&
1500 rctx
->framebuffer
.is_msaa_resolve
&&
1503 surf
= (struct r600_surface
*)state
->cbufs
[i
];
1504 rtex
= (struct r600_texture
*)surf
->base
.texture
;
1506 if (!surf
->color_initialized
|| force_cmask_fmask
) {
1507 r600_init_color_surface(rctx
, surf
, force_cmask_fmask
);
1508 if (force_cmask_fmask
) {
1509 /* re-initialize later without compression */
1510 surf
->color_initialized
= false;
1514 if (!surf
->export_16bpc
) {
1515 rctx
->framebuffer
.export_16bpc
= false;
1518 if (rtex
->fmask_size
&& rtex
->cmask_size
) {
1519 rctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
1523 /* Update alpha-test state dependencies.
1524 * Alpha-test is done on the first colorbuffer only. */
1525 if (state
->nr_cbufs
) {
1526 surf
= (struct r600_surface
*)state
->cbufs
[0];
1527 if (rctx
->alphatest_state
.bypass
!= surf
->alphatest_bypass
) {
1528 rctx
->alphatest_state
.bypass
= surf
->alphatest_bypass
;
1529 rctx
->alphatest_state
.atom
.dirty
= true;
1535 surf
= (struct r600_surface
*)state
->zsbuf
;
1537 if (!surf
->depth_initialized
) {
1538 r600_init_depth_surface(rctx
, surf
);
1541 if (state
->zsbuf
->format
!= rctx
->poly_offset_state
.zs_format
) {
1542 rctx
->poly_offset_state
.zs_format
= state
->zsbuf
->format
;
1543 rctx
->poly_offset_state
.atom
.dirty
= true;
1546 if (rctx
->db_state
.rsurf
!= surf
) {
1547 rctx
->db_state
.rsurf
= surf
;
1548 rctx
->db_state
.atom
.dirty
= true;
1549 rctx
->db_misc_state
.atom
.dirty
= true;
1551 } else if (rctx
->db_state
.rsurf
) {
1552 rctx
->db_state
.rsurf
= NULL
;
1553 rctx
->db_state
.atom
.dirty
= true;
1554 rctx
->db_misc_state
.atom
.dirty
= true;
1557 if (rctx
->cb_misc_state
.nr_cbufs
!= state
->nr_cbufs
) {
1558 rctx
->cb_misc_state
.nr_cbufs
= state
->nr_cbufs
;
1559 rctx
->cb_misc_state
.atom
.dirty
= true;
1562 if (state
->nr_cbufs
== 0 && rctx
->alphatest_state
.bypass
) {
1563 rctx
->alphatest_state
.bypass
= false;
1564 rctx
->alphatest_state
.atom
.dirty
= true;
1567 r600_update_db_shader_control(rctx
);
1569 /* Calculate the CS size. */
1570 rctx
->framebuffer
.atom
.num_dw
=
1571 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1573 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1574 rctx
->framebuffer
.atom
.num_dw
+= 6 * (2 + rctx
->framebuffer
.state
.nr_cbufs
);
1575 rctx
->framebuffer
.atom
.num_dw
+= 6 * rctx
->framebuffer
.state
.nr_cbufs
; /* relocs */
1578 if (rctx
->framebuffer
.state
.zsbuf
) {
1579 rctx
->framebuffer
.atom
.num_dw
+= 18;
1580 } else if (rctx
->screen
->info
.drm_minor
>= 18) {
1581 rctx
->framebuffer
.atom
.num_dw
+= 3;
1583 if (rctx
->family
> CHIP_R600
&& rctx
->family
< CHIP_RV770
) {
1584 rctx
->framebuffer
.atom
.num_dw
+= 2;
1587 rctx
->framebuffer
.atom
.dirty
= true;
1590 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1591 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1592 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1593 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1594 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1596 static void r600_emit_msaa_state(struct r600_context
*rctx
, int nr_samples
)
1598 static uint32_t sample_locs_2x
[] = {
1599 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1600 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1602 static unsigned max_dist_2x
= 4;
1603 static uint32_t sample_locs_4x
[] = {
1604 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1605 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1607 static unsigned max_dist_4x
= 6;
1608 static uint32_t sample_locs_8x
[] = {
1609 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1610 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1612 static unsigned max_dist_8x
= 7;
1614 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1615 unsigned max_dist
= 0;
1617 if (rctx
->family
== CHIP_R600
) {
1618 switch (nr_samples
) {
1623 r600_write_config_reg(cs
, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S
, sample_locs_2x
[0]);
1624 max_dist
= max_dist_2x
;
1627 r600_write_config_reg(cs
, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S
, sample_locs_4x
[0]);
1628 max_dist
= max_dist_4x
;
1631 r600_write_config_reg_seq(cs
, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0
, 2);
1632 r600_write_value(cs
, sample_locs_8x
[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1633 r600_write_value(cs
, sample_locs_8x
[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1634 max_dist
= max_dist_8x
;
1638 switch (nr_samples
) {
1640 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1641 r600_write_value(cs
, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1642 r600_write_value(cs
, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1646 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1647 r600_write_value(cs
, sample_locs_2x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1648 r600_write_value(cs
, sample_locs_2x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1649 max_dist
= max_dist_2x
;
1652 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1653 r600_write_value(cs
, sample_locs_4x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1654 r600_write_value(cs
, sample_locs_4x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1655 max_dist
= max_dist_4x
;
1658 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1659 r600_write_value(cs
, sample_locs_8x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1660 r600_write_value(cs
, sample_locs_8x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1661 max_dist
= max_dist_8x
;
1666 if (nr_samples
> 1) {
1667 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1668 r600_write_value(cs
, S_028C00_LAST_PIXEL(1) |
1669 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1670 r600_write_value(cs
, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples
)) |
1671 S_028C04_MAX_SAMPLE_DIST(max_dist
)); /* R_028C04_PA_SC_AA_CONFIG */
1673 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1674 r600_write_value(cs
, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1675 r600_write_value(cs
, 0); /* R_028C04_PA_SC_AA_CONFIG */
1679 static void r600_emit_framebuffer_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1681 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1682 struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
.state
;
1683 unsigned nr_cbufs
= state
->nr_cbufs
;
1684 struct r600_surface
**cb
= (struct r600_surface
**)&state
->cbufs
[0];
1685 unsigned i
, sbu
= 0;
1688 r600_write_context_reg_seq(cs
, R_0280A0_CB_COLOR0_INFO
, 8);
1689 for (i
= 0; i
< nr_cbufs
; i
++) {
1690 r600_write_value(cs
, cb
[i
]->cb_color_info
);
1692 /* set CB_COLOR1_INFO for possible dual-src blending */
1694 r600_write_value(cs
, cb
[0]->cb_color_info
);
1697 for (; i
< 8; i
++) {
1698 r600_write_value(cs
, 0);
1703 r600_write_context_reg_seq(cs
, R_028040_CB_COLOR0_BASE
, nr_cbufs
);
1704 for (i
= 0; i
< nr_cbufs
; i
++) {
1705 r600_write_value(cs
, cb
[i
]->cb_color_base
);
1709 for (i
= 0; i
< nr_cbufs
; i
++) {
1710 unsigned reloc
= r600_context_bo_reloc(rctx
,
1711 (struct r600_resource
*)cb
[i
]->base
.texture
,
1712 RADEON_USAGE_READWRITE
);
1713 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1714 r600_write_value(cs
, reloc
);
1717 r600_write_context_reg_seq(cs
, R_028060_CB_COLOR0_SIZE
, nr_cbufs
);
1718 for (i
= 0; i
< nr_cbufs
; i
++) {
1719 r600_write_value(cs
, cb
[i
]->cb_color_size
);
1722 r600_write_context_reg_seq(cs
, R_028080_CB_COLOR0_VIEW
, nr_cbufs
);
1723 for (i
= 0; i
< nr_cbufs
; i
++) {
1724 r600_write_value(cs
, cb
[i
]->cb_color_view
);
1727 r600_write_context_reg_seq(cs
, R_028100_CB_COLOR0_MASK
, nr_cbufs
);
1728 for (i
= 0; i
< nr_cbufs
; i
++) {
1729 r600_write_value(cs
, cb
[i
]->cb_color_mask
);
1733 r600_write_context_reg_seq(cs
, R_0280E0_CB_COLOR0_FRAG
, nr_cbufs
);
1734 for (i
= 0; i
< nr_cbufs
; i
++) {
1735 r600_write_value(cs
, cb
[i
]->cb_color_fmask
);
1738 for (i
= 0; i
< nr_cbufs
; i
++) {
1739 unsigned reloc
= r600_context_bo_reloc(rctx
,
1740 cb
[i
]->cb_buffer_fmask
,
1741 RADEON_USAGE_READWRITE
);
1742 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1743 r600_write_value(cs
, reloc
);
1747 r600_write_context_reg_seq(cs
, R_0280C0_CB_COLOR0_TILE
, nr_cbufs
);
1748 for (i
= 0; i
< nr_cbufs
; i
++) {
1749 r600_write_value(cs
, cb
[i
]->cb_color_cmask
);
1752 for (i
= 0; i
< nr_cbufs
; i
++) {
1753 unsigned reloc
= r600_context_bo_reloc(rctx
,
1754 cb
[i
]->cb_buffer_cmask
,
1755 RADEON_USAGE_READWRITE
);
1756 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1757 r600_write_value(cs
, reloc
);
1760 sbu
|= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs
);
1763 /* SURFACE_BASE_UPDATE */
1764 if (rctx
->family
> CHIP_R600
&& rctx
->family
< CHIP_RV770
&& sbu
) {
1765 r600_write_value(cs
, PKT3(PKT3_SURFACE_BASE_UPDATE
, 0, 0));
1766 r600_write_value(cs
, sbu
);
1772 struct r600_surface
*surf
= (struct r600_surface
*)state
->zsbuf
;
1773 unsigned reloc
= r600_context_bo_reloc(rctx
,
1774 (struct r600_resource
*)state
->zsbuf
->texture
,
1775 RADEON_USAGE_READWRITE
);
1777 r600_write_context_reg(cs
, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1778 surf
->pa_su_poly_offset_db_fmt_cntl
);
1780 r600_write_context_reg_seq(cs
, R_028000_DB_DEPTH_SIZE
, 2);
1781 r600_write_value(cs
, surf
->db_depth_size
); /* R_028000_DB_DEPTH_SIZE */
1782 r600_write_value(cs
, surf
->db_depth_view
); /* R_028004_DB_DEPTH_VIEW */
1783 r600_write_context_reg_seq(cs
, R_02800C_DB_DEPTH_BASE
, 2);
1784 r600_write_value(cs
, surf
->db_depth_base
); /* R_02800C_DB_DEPTH_BASE */
1785 r600_write_value(cs
, surf
->db_depth_info
); /* R_028010_DB_DEPTH_INFO */
1787 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1788 r600_write_value(cs
, reloc
);
1790 r600_write_context_reg(cs
, R_028D34_DB_PREFETCH_LIMIT
, surf
->db_prefetch_limit
);
1792 sbu
|= SURFACE_BASE_UPDATE_DEPTH
;
1793 } else if (rctx
->screen
->info
.drm_minor
>= 18) {
1794 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1795 * Older kernels are out of luck. */
1796 r600_write_context_reg(cs
, R_028010_DB_DEPTH_INFO
, S_028010_FORMAT(V_028010_DEPTH_INVALID
));
1799 /* SURFACE_BASE_UPDATE */
1800 if (rctx
->family
> CHIP_R600
&& rctx
->family
< CHIP_RV770
&& sbu
) {
1801 r600_write_value(cs
, PKT3(PKT3_SURFACE_BASE_UPDATE
, 0, 0));
1802 r600_write_value(cs
, sbu
);
1806 /* Framebuffer dimensions. */
1807 r600_write_context_reg_seq(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, 2);
1808 r600_write_value(cs
, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1809 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1810 r600_write_value(cs
, S_028244_BR_X(state
->width
) |
1811 S_028244_BR_Y(state
->height
)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1813 if (rctx
->framebuffer
.is_msaa_resolve
) {
1814 r600_write_context_reg(cs
, R_0287A0_CB_SHADER_CONTROL
, 1);
1816 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1817 * will assure that the alpha-test will work even if there is
1818 * no colorbuffer bound. */
1819 r600_write_context_reg(cs
, R_0287A0_CB_SHADER_CONTROL
,
1820 (1ull << MAX2(nr_cbufs
, 1)) - 1);
1823 r600_emit_msaa_state(rctx
, rctx
->framebuffer
.nr_samples
);
1826 static void r600_emit_cb_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1828 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1829 struct r600_cb_misc_state
*a
= (struct r600_cb_misc_state
*)atom
;
1831 if (G_028808_SPECIAL_OP(a
->cb_color_control
) == V_028808_SPECIAL_RESOLVE_BOX
) {
1832 r600_write_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1833 if (rctx
->chip_class
== R600
) {
1834 r600_write_value(cs
, 0xff); /* R_028238_CB_TARGET_MASK */
1835 r600_write_value(cs
, 0xff); /* R_02823C_CB_SHADER_MASK */
1837 r600_write_value(cs
, 0xf); /* R_028238_CB_TARGET_MASK */
1838 r600_write_value(cs
, 0xf); /* R_02823C_CB_SHADER_MASK */
1840 r600_write_context_reg(cs
, R_028808_CB_COLOR_CONTROL
, a
->cb_color_control
);
1842 unsigned fb_colormask
= (1ULL << ((unsigned)a
->nr_cbufs
* 4)) - 1;
1843 unsigned ps_colormask
= (1ULL << ((unsigned)a
->nr_ps_color_outputs
* 4)) - 1;
1844 unsigned multiwrite
= a
->multiwrite
&& a
->nr_cbufs
> 1;
1846 r600_write_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1847 r600_write_value(cs
, a
->blend_colormask
& fb_colormask
); /* R_028238_CB_TARGET_MASK */
1848 /* Always enable the first color output to make sure alpha-test works even without one. */
1849 r600_write_value(cs
, 0xf | (multiwrite
? fb_colormask
: ps_colormask
)); /* R_02823C_CB_SHADER_MASK */
1850 r600_write_context_reg(cs
, R_028808_CB_COLOR_CONTROL
,
1851 a
->cb_color_control
|
1852 S_028808_MULTIWRITE_ENABLE(multiwrite
));
1856 static void r600_emit_db_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1858 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1859 struct r600_db_state
*a
= (struct r600_db_state
*)atom
;
1861 if (a
->rsurf
&& a
->rsurf
->htile_enabled
) {
1862 struct r600_texture
*rtex
= (struct r600_texture
*)a
->rsurf
->base
.texture
;
1865 r600_write_context_reg(cs
, R_02802C_DB_DEPTH_CLEAR
, fui(rtex
->depth_clear
));
1866 r600_write_context_reg(cs
, R_028D24_DB_HTILE_SURFACE
, a
->rsurf
->db_htile_surface
);
1867 r600_write_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, a
->rsurf
->db_htile_data_base
);
1868 reloc_idx
= r600_context_bo_reloc(rctx
, rtex
->htile
, RADEON_USAGE_READWRITE
);
1869 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1870 cs
->buf
[cs
->cdw
++] = reloc_idx
;
1872 r600_write_context_reg(cs
, R_028D24_DB_HTILE_SURFACE
, 0);
1876 static void r600_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1878 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1879 struct r600_db_misc_state
*a
= (struct r600_db_misc_state
*)atom
;
1880 unsigned db_render_control
= 0;
1881 unsigned db_render_override
=
1882 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE
) |
1883 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE
);
1885 if (a
->occlusion_query_enabled
) {
1886 if (rctx
->chip_class
>= R700
) {
1887 db_render_control
|= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1889 db_render_override
|= S_028D10_NOOP_CULL_DISABLE(1);
1891 if (rctx
->db_state
.rsurf
&& rctx
->db_state
.rsurf
->htile_enabled
) {
1892 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1893 db_render_override
|= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF
);
1895 db_render_override
|= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE
);
1897 if (a
->flush_depthstencil_through_cb
) {
1898 assert(a
->copy_depth
|| a
->copy_stencil
);
1900 db_render_control
|= S_028D0C_DEPTH_COPY_ENABLE(a
->copy_depth
) |
1901 S_028D0C_STENCIL_COPY_ENABLE(a
->copy_stencil
) |
1902 S_028D0C_COPY_CENTROID(1) |
1903 S_028D0C_COPY_SAMPLE(a
->copy_sample
);
1904 } else if (a
->flush_depthstencil_in_place
) {
1905 db_render_control
|= S_028D0C_DEPTH_COMPRESS_DISABLE(1) |
1906 S_028D0C_STENCIL_COMPRESS_DISABLE(1);
1907 db_render_override
|= S_028D10_NOOP_CULL_DISABLE(1);
1909 if (a
->htile_clear
) {
1910 db_render_control
|= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1913 r600_write_context_reg_seq(cs
, R_028D0C_DB_RENDER_CONTROL
, 2);
1914 r600_write_value(cs
, db_render_control
); /* R_028D0C_DB_RENDER_CONTROL */
1915 r600_write_value(cs
, db_render_override
); /* R_028D10_DB_RENDER_OVERRIDE */
1916 r600_write_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
, a
->db_shader_control
);
1919 static void r600_emit_config_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1921 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1922 struct r600_config_state
*a
= (struct r600_config_state
*)atom
;
1924 r600_write_config_reg(cs
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, a
->sq_gpr_resource_mgmt_1
);
1927 static void r600_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1929 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1930 uint32_t dirty_mask
= rctx
->vertex_buffer_state
.dirty_mask
;
1932 while (dirty_mask
) {
1933 struct pipe_vertex_buffer
*vb
;
1934 struct r600_resource
*rbuffer
;
1936 unsigned buffer_index
= u_bit_scan(&dirty_mask
);
1938 vb
= &rctx
->vertex_buffer_state
.vb
[buffer_index
];
1939 rbuffer
= (struct r600_resource
*)vb
->buffer
;
1942 offset
= vb
->buffer_offset
;
1944 /* fetch resources start at index 320 */
1945 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1946 r600_write_value(cs
, (320 + buffer_index
) * 7);
1947 r600_write_value(cs
, offset
); /* RESOURCEi_WORD0 */
1948 r600_write_value(cs
, rbuffer
->buf
->size
- offset
- 1); /* RESOURCEi_WORD1 */
1949 r600_write_value(cs
, /* RESOURCEi_WORD2 */
1950 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1951 S_038008_STRIDE(vb
->stride
));
1952 r600_write_value(cs
, 0); /* RESOURCEi_WORD3 */
1953 r600_write_value(cs
, 0); /* RESOURCEi_WORD4 */
1954 r600_write_value(cs
, 0); /* RESOURCEi_WORD5 */
1955 r600_write_value(cs
, 0xc0000000); /* RESOURCEi_WORD6 */
1957 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1958 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
1962 static void r600_emit_constant_buffers(struct r600_context
*rctx
,
1963 struct r600_constbuf_state
*state
,
1964 unsigned buffer_id_base
,
1965 unsigned reg_alu_constbuf_size
,
1966 unsigned reg_alu_const_cache
)
1968 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1969 uint32_t dirty_mask
= state
->dirty_mask
;
1971 while (dirty_mask
) {
1972 struct pipe_constant_buffer
*cb
;
1973 struct r600_resource
*rbuffer
;
1975 unsigned buffer_index
= ffs(dirty_mask
) - 1;
1977 cb
= &state
->cb
[buffer_index
];
1978 rbuffer
= (struct r600_resource
*)cb
->buffer
;
1981 offset
= cb
->buffer_offset
;
1983 r600_write_context_reg(cs
, reg_alu_constbuf_size
+ buffer_index
* 4,
1984 ALIGN_DIVUP(cb
->buffer_size
>> 4, 16));
1985 r600_write_context_reg(cs
, reg_alu_const_cache
+ buffer_index
* 4, offset
>> 8);
1987 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1988 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
1990 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1991 r600_write_value(cs
, (buffer_id_base
+ buffer_index
) * 7);
1992 r600_write_value(cs
, offset
); /* RESOURCEi_WORD0 */
1993 r600_write_value(cs
, rbuffer
->buf
->size
- offset
- 1); /* RESOURCEi_WORD1 */
1994 r600_write_value(cs
, /* RESOURCEi_WORD2 */
1995 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1996 S_038008_STRIDE(16));
1997 r600_write_value(cs
, 0); /* RESOURCEi_WORD3 */
1998 r600_write_value(cs
, 0); /* RESOURCEi_WORD4 */
1999 r600_write_value(cs
, 0); /* RESOURCEi_WORD5 */
2000 r600_write_value(cs
, 0xc0000000); /* RESOURCEi_WORD6 */
2002 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2003 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
2005 dirty_mask
&= ~(1 << buffer_index
);
2007 state
->dirty_mask
= 0;
2010 static void r600_emit_vs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2012 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
], 160,
2013 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
2014 R_028980_ALU_CONST_CACHE_VS_0
);
2017 static void r600_emit_gs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2019 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
], 336,
2020 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
,
2021 R_0289C0_ALU_CONST_CACHE_GS_0
);
2024 static void r600_emit_ps_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2026 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
], 0,
2027 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
2028 R_028940_ALU_CONST_CACHE_PS_0
);
2031 static void r600_emit_sampler_views(struct r600_context
*rctx
,
2032 struct r600_samplerview_state
*state
,
2033 unsigned resource_id_base
)
2035 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2036 uint32_t dirty_mask
= state
->dirty_mask
;
2038 while (dirty_mask
) {
2039 struct r600_pipe_sampler_view
*rview
;
2040 unsigned resource_index
= u_bit_scan(&dirty_mask
);
2043 rview
= state
->views
[resource_index
];
2046 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
2047 r600_write_value(cs
, (resource_id_base
+ resource_index
) * 7);
2048 r600_write_array(cs
, 7, rview
->tex_resource_words
);
2050 reloc
= r600_context_bo_reloc(rctx
, rview
->tex_resource
,
2052 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2053 r600_write_value(cs
, reloc
);
2054 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2055 r600_write_value(cs
, reloc
);
2057 state
->dirty_mask
= 0;
2067 static void r600_emit_vs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2069 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
, 160 + R600_MAX_CONST_BUFFERS
);
2072 static void r600_emit_gs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2074 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
, 336 + R600_MAX_CONST_BUFFERS
);
2077 static void r600_emit_ps_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2079 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
, R600_MAX_CONST_BUFFERS
);
2082 static void r600_emit_sampler_states(struct r600_context
*rctx
,
2083 struct r600_textures_info
*texinfo
,
2084 unsigned resource_id_base
,
2085 unsigned border_color_reg
)
2087 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2088 uint32_t dirty_mask
= texinfo
->states
.dirty_mask
;
2090 while (dirty_mask
) {
2091 struct r600_pipe_sampler_state
*rstate
;
2092 struct r600_pipe_sampler_view
*rview
;
2093 unsigned i
= u_bit_scan(&dirty_mask
);
2095 rstate
= texinfo
->states
.states
[i
];
2097 rview
= texinfo
->views
.views
[i
];
2099 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
2100 * filtering between layers.
2101 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
2104 enum pipe_texture_target target
= rview
->base
.texture
->target
;
2105 if (target
== PIPE_TEXTURE_1D_ARRAY
||
2106 target
== PIPE_TEXTURE_2D_ARRAY
) {
2107 rstate
->tex_sampler_words
[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
2108 texinfo
->is_array_sampler
[i
] = true;
2110 rstate
->tex_sampler_words
[0] &= C_03C000_TEX_ARRAY_OVERRIDE
;
2111 texinfo
->is_array_sampler
[i
] = false;
2115 r600_write_value(cs
, PKT3(PKT3_SET_SAMPLER
, 3, 0));
2116 r600_write_value(cs
, (resource_id_base
+ i
) * 3);
2117 r600_write_array(cs
, 3, rstate
->tex_sampler_words
);
2119 if (rstate
->border_color_use
) {
2122 offset
= border_color_reg
;
2124 r600_write_config_reg_seq(cs
, offset
, 4);
2125 r600_write_array(cs
, 4, rstate
->border_color
.ui
);
2128 texinfo
->states
.dirty_mask
= 0;
2131 static void r600_emit_vs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2133 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED
);
2136 static void r600_emit_gs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2138 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED
);
2141 static void r600_emit_ps_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2143 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED
);
2146 static void r600_emit_seamless_cube_map(struct r600_context
*rctx
, struct r600_atom
*atom
)
2148 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2151 tmp
= S_009508_DISABLE_CUBE_ANISO(1) |
2152 S_009508_SYNC_GRADIENT(1) |
2153 S_009508_SYNC_WALKER(1) |
2154 S_009508_SYNC_ALIGNER(1);
2155 if (!rctx
->seamless_cube_map
.enabled
) {
2156 tmp
|= S_009508_DISABLE_CUBE_WRAP(1);
2158 r600_write_config_reg(cs
, R_009508_TA_CNTL_AUX
, tmp
);
2161 static void r600_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2163 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2164 uint8_t mask
= s
->sample_mask
;
2166 r600_write_context_reg(rctx
->cs
, R_028C48_PA_SC_AA_MASK
,
2167 mask
| (mask
<< 8) | (mask
<< 16) | (mask
<< 24));
2170 static void r600_emit_vertex_fetch_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2172 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2173 struct r600_cso_state
*state
= (struct r600_cso_state
*)a
;
2174 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
->cso
;
2176 r600_write_context_reg(cs
, R_028894_SQ_PGM_START_FS
, shader
->offset
>> 8);
2177 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2178 r600_write_value(cs
, r600_context_bo_reloc(rctx
, shader
->buffer
, RADEON_USAGE_READ
));
2181 void r600_init_state_functions(struct r600_context
*rctx
)
2186 * To avoid GPU lockup registers must be emited in a specific order
2187 * (no kidding ...). The order below is important and have been
2188 * partialy infered from analyzing fglrx command stream.
2190 * Don't reorder atom without carefully checking the effect (GPU lockup
2191 * or piglit regression).
2195 r600_init_atom(rctx
, &rctx
->framebuffer
.atom
, id
++, r600_emit_framebuffer_state
, 0);
2198 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
].atom
, id
++, r600_emit_vs_constant_buffers
, 0);
2199 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
].atom
, id
++, r600_emit_gs_constant_buffers
, 0);
2200 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
].atom
, id
++, r600_emit_ps_constant_buffers
, 0);
2202 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2203 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
2205 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].states
.atom
, id
++, r600_emit_vs_sampler_states
, 0);
2206 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].states
.atom
, id
++, r600_emit_gs_sampler_states
, 0);
2207 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].states
.atom
, id
++, r600_emit_ps_sampler_states
, 0);
2209 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
.atom
, id
++, r600_emit_vs_sampler_views
, 0);
2210 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
.atom
, id
++, r600_emit_gs_sampler_views
, 0);
2211 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.atom
, id
++, r600_emit_ps_sampler_views
, 0);
2212 r600_init_atom(rctx
, &rctx
->vertex_buffer_state
.atom
, id
++, r600_emit_vertex_buffers
, 0);
2214 r600_init_atom(rctx
, &rctx
->vgt_state
.atom
, id
++, r600_emit_vgt_state
, 6);
2215 r600_init_atom(rctx
, &rctx
->vgt2_state
.atom
, id
++, r600_emit_vgt2_state
, 3);
2217 r600_init_atom(rctx
, &rctx
->seamless_cube_map
.atom
, id
++, r600_emit_seamless_cube_map
, 3);
2218 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, r600_emit_sample_mask
, 3);
2219 rctx
->sample_mask
.sample_mask
= ~0;
2221 r600_init_atom(rctx
, &rctx
->alphatest_state
.atom
, id
++, r600_emit_alphatest_state
, 6);
2222 r600_init_atom(rctx
, &rctx
->blend_color
.atom
, id
++, r600_emit_blend_color
, 6);
2223 r600_init_atom(rctx
, &rctx
->blend_state
.atom
, id
++, r600_emit_cso_state
, 0);
2224 r600_init_atom(rctx
, &rctx
->cb_misc_state
.atom
, id
++, r600_emit_cb_misc_state
, 7);
2225 r600_init_atom(rctx
, &rctx
->clip_misc_state
.atom
, id
++, r600_emit_clip_misc_state
, 6);
2226 r600_init_atom(rctx
, &rctx
->clip_state
.atom
, id
++, r600_emit_clip_state
, 26);
2227 r600_init_atom(rctx
, &rctx
->db_misc_state
.atom
, id
++, r600_emit_db_misc_state
, 7);
2228 r600_init_atom(rctx
, &rctx
->db_state
.atom
, id
++, r600_emit_db_state
, 11);
2229 r600_init_atom(rctx
, &rctx
->dsa_state
.atom
, id
++, r600_emit_cso_state
, 0);
2230 r600_init_atom(rctx
, &rctx
->poly_offset_state
.atom
, id
++, r600_emit_polygon_offset
, 6);
2231 r600_init_atom(rctx
, &rctx
->rasterizer_state
.atom
, id
++, r600_emit_cso_state
, 0);
2232 r600_init_atom(rctx
, &rctx
->scissor
.atom
, id
++, r600_emit_scissor_state
, 4);
2233 r600_init_atom(rctx
, &rctx
->config_state
.atom
, id
++, r600_emit_config_state
, 3);
2234 r600_init_atom(rctx
, &rctx
->stencil_ref
.atom
, id
++, r600_emit_stencil_ref
, 4);
2235 r600_init_atom(rctx
, &rctx
->viewport
.atom
, id
++, r600_emit_viewport_state
, 8);
2236 r600_init_atom(rctx
, &rctx
->vertex_fetch_shader
.atom
, id
++, r600_emit_vertex_fetch_shader
, 5);
2238 rctx
->context
.create_blend_state
= r600_create_blend_state
;
2239 rctx
->context
.create_depth_stencil_alpha_state
= r600_create_dsa_state
;
2240 rctx
->context
.create_rasterizer_state
= r600_create_rs_state
;
2241 rctx
->context
.create_sampler_state
= r600_create_sampler_state
;
2242 rctx
->context
.create_sampler_view
= r600_create_sampler_view
;
2243 rctx
->context
.set_framebuffer_state
= r600_set_framebuffer_state
;
2244 rctx
->context
.set_polygon_stipple
= r600_set_polygon_stipple
;
2245 rctx
->context
.set_scissor_state
= r600_set_scissor_state
;
2248 /* Adjust GPR allocation on R6xx/R7xx */
2249 bool r600_adjust_gprs(struct r600_context
*rctx
)
2251 unsigned num_ps_gprs
= rctx
->ps_shader
->current
->shader
.bc
.ngpr
;
2252 unsigned num_vs_gprs
= rctx
->vs_shader
->current
->shader
.bc
.ngpr
;
2253 unsigned new_num_ps_gprs
= num_ps_gprs
;
2254 unsigned new_num_vs_gprs
= num_vs_gprs
;
2255 unsigned cur_num_ps_gprs
= G_008C04_NUM_PS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_1
);
2256 unsigned cur_num_vs_gprs
= G_008C04_NUM_VS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_1
);
2257 unsigned def_num_ps_gprs
= rctx
->default_ps_gprs
;
2258 unsigned def_num_vs_gprs
= rctx
->default_vs_gprs
;
2259 unsigned def_num_clause_temp_gprs
= rctx
->r6xx_num_clause_temp_gprs
;
2260 /* hardware will reserve twice num_clause_temp_gprs */
2261 unsigned max_gprs
= def_num_ps_gprs
+ def_num_vs_gprs
+ def_num_clause_temp_gprs
* 2;
2264 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2265 if (new_num_ps_gprs
> cur_num_ps_gprs
|| new_num_vs_gprs
> cur_num_vs_gprs
) {
2266 /* try to use switch back to default */
2267 if (new_num_ps_gprs
> def_num_ps_gprs
|| new_num_vs_gprs
> def_num_vs_gprs
) {
2268 /* always privilege vs stage so that at worst we have the
2269 * pixel stage producing wrong output (not the vertex
2271 new_num_ps_gprs
= max_gprs
- (new_num_vs_gprs
+ def_num_clause_temp_gprs
* 2);
2272 new_num_vs_gprs
= num_vs_gprs
;
2274 new_num_ps_gprs
= def_num_ps_gprs
;
2275 new_num_vs_gprs
= def_num_vs_gprs
;
2281 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2282 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2283 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2284 * it will lockup. So in this case just discard the draw command
2285 * and don't change the current gprs repartitions.
2287 if (num_ps_gprs
> new_num_ps_gprs
|| num_vs_gprs
> new_num_vs_gprs
) {
2288 R600_ERR("ps & vs shader require too many register (%d + %d) "
2289 "for a combined maximum of %d\n",
2290 num_ps_gprs
, num_vs_gprs
, max_gprs
);
2294 /* in some case we endup recomputing the current value */
2295 tmp
= S_008C04_NUM_PS_GPRS(new_num_ps_gprs
) |
2296 S_008C04_NUM_VS_GPRS(new_num_vs_gprs
) |
2297 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs
);
2298 if (rctx
->config_state
.sq_gpr_resource_mgmt_1
!= tmp
) {
2299 rctx
->config_state
.sq_gpr_resource_mgmt_1
= tmp
;
2300 rctx
->config_state
.atom
.dirty
= true;
2301 rctx
->flags
|= R600_CONTEXT_WAIT_IDLE
;
2306 void r600_init_atom_start_cs(struct r600_context
*rctx
)
2321 int num_ps_stack_entries
;
2322 int num_vs_stack_entries
;
2323 int num_gs_stack_entries
;
2324 int num_es_stack_entries
;
2325 enum radeon_family family
;
2326 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2329 r600_init_command_buffer(cb
, 256);
2331 /* R6xx requires this packet at the start of each command buffer */
2332 if (rctx
->chip_class
== R600
) {
2333 r600_store_value(cb
, PKT3(PKT3_START_3D_CMDBUF
, 0, 0));
2334 r600_store_value(cb
, 0);
2336 /* All asics require this one */
2337 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2338 r600_store_value(cb
, 0x80000000);
2339 r600_store_value(cb
, 0x80000000);
2341 /* We're setting config registers here. */
2342 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2343 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2345 family
= rctx
->family
;
2357 num_ps_threads
= 136;
2358 num_vs_threads
= 48;
2361 num_ps_stack_entries
= 128;
2362 num_vs_stack_entries
= 128;
2363 num_gs_stack_entries
= 0;
2364 num_es_stack_entries
= 0;
2373 num_ps_threads
= 144;
2374 num_vs_threads
= 40;
2377 num_ps_stack_entries
= 40;
2378 num_vs_stack_entries
= 40;
2379 num_gs_stack_entries
= 32;
2380 num_es_stack_entries
= 16;
2392 num_ps_threads
= 136;
2393 num_vs_threads
= 48;
2396 num_ps_stack_entries
= 40;
2397 num_vs_stack_entries
= 40;
2398 num_gs_stack_entries
= 32;
2399 num_es_stack_entries
= 16;
2407 num_ps_threads
= 136;
2408 num_vs_threads
= 48;
2411 num_ps_stack_entries
= 40;
2412 num_vs_stack_entries
= 40;
2413 num_gs_stack_entries
= 32;
2414 num_es_stack_entries
= 16;
2422 num_ps_threads
= 188;
2423 num_vs_threads
= 60;
2426 num_ps_stack_entries
= 256;
2427 num_vs_stack_entries
= 256;
2428 num_gs_stack_entries
= 0;
2429 num_es_stack_entries
= 0;
2438 num_ps_threads
= 188;
2439 num_vs_threads
= 60;
2442 num_ps_stack_entries
= 128;
2443 num_vs_stack_entries
= 128;
2444 num_gs_stack_entries
= 0;
2445 num_es_stack_entries
= 0;
2453 num_ps_threads
= 144;
2454 num_vs_threads
= 48;
2457 num_ps_stack_entries
= 128;
2458 num_vs_stack_entries
= 128;
2459 num_gs_stack_entries
= 0;
2460 num_es_stack_entries
= 0;
2464 rctx
->default_ps_gprs
= num_ps_gprs
;
2465 rctx
->default_vs_gprs
= num_vs_gprs
;
2466 rctx
->r6xx_num_clause_temp_gprs
= num_temp_gprs
;
2478 tmp
|= S_008C00_VC_ENABLE(1);
2481 tmp
|= S_008C00_DX9_CONSTS(0);
2482 tmp
|= S_008C00_ALU_INST_PREFER_VECTOR(1);
2483 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2484 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2485 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2486 tmp
|= S_008C00_ES_PRIO(es_prio
);
2487 r600_store_config_reg(cb
, R_008C00_SQ_CONFIG
, tmp
);
2489 /* SQ_GPR_RESOURCE_MGMT_2 */
2490 tmp
= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
2491 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
2492 r600_store_config_reg_seq(cb
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, 4);
2493 r600_store_value(cb
, tmp
);
2495 /* SQ_THREAD_RESOURCE_MGMT */
2496 tmp
= S_008C0C_NUM_PS_THREADS(num_ps_threads
);
2497 tmp
|= S_008C0C_NUM_VS_THREADS(num_vs_threads
);
2498 tmp
|= S_008C0C_NUM_GS_THREADS(num_gs_threads
);
2499 tmp
|= S_008C0C_NUM_ES_THREADS(num_es_threads
);
2500 r600_store_value(cb
, tmp
); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2502 /* SQ_STACK_RESOURCE_MGMT_1 */
2503 tmp
= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
2504 tmp
|= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
2505 r600_store_value(cb
, tmp
); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2507 /* SQ_STACK_RESOURCE_MGMT_2 */
2508 tmp
= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
2509 tmp
|= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
2510 r600_store_value(cb
, tmp
); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2512 r600_store_config_reg(cb
, R_009714_VC_ENHANCE
, 0);
2514 if (rctx
->chip_class
>= R700
) {
2515 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0x00004000);
2516 r600_store_config_reg(cb
, R_009830_DB_DEBUG
, 0);
2517 r600_store_config_reg(cb
, R_009838_DB_WATERMARKS
, 0x00420204);
2518 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2520 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0);
2521 r600_store_config_reg(cb
, R_009830_DB_DEBUG
, 0x82000000);
2522 r600_store_config_reg(cb
, R_009838_DB_WATERMARKS
, 0x01020204);
2523 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 1);
2525 r600_store_context_reg_seq(cb
, R_0288A8_SQ_ESGS_RING_ITEMSIZE
, 9);
2526 r600_store_value(cb
, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2527 r600_store_value(cb
, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2528 r600_store_value(cb
, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2529 r600_store_value(cb
, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2530 r600_store_value(cb
, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2531 r600_store_value(cb
, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2532 r600_store_value(cb
, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2533 r600_store_value(cb
, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2534 r600_store_value(cb
, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2536 /* to avoid GPU doing any preloading of constant from random address */
2537 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 8);
2538 r600_store_value(cb
, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2539 r600_store_value(cb
, 0);
2540 r600_store_value(cb
, 0);
2541 r600_store_value(cb
, 0);
2542 r600_store_value(cb
, 0);
2543 r600_store_value(cb
, 0);
2544 r600_store_value(cb
, 0);
2545 r600_store_value(cb
, 0);
2546 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 8);
2547 r600_store_value(cb
, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2548 r600_store_value(cb
, 0);
2549 r600_store_value(cb
, 0);
2550 r600_store_value(cb
, 0);
2551 r600_store_value(cb
, 0);
2552 r600_store_value(cb
, 0);
2553 r600_store_value(cb
, 0);
2554 r600_store_value(cb
, 0);
2556 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2557 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2558 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2559 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2560 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2561 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2562 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2563 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2564 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2565 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2566 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2567 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2568 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2569 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE, 0); */
2571 r600_store_context_reg(cb
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
2572 r600_store_context_reg(cb
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 0);
2573 r600_store_context_reg(cb
, R_028AA4_VGT_INSTANCE_STEP_RATE_1
, 0);
2575 r600_store_context_reg_seq(cb
, R_028AB0_VGT_STRMOUT_EN
, 3);
2576 r600_store_value(cb
, 0); /* R_028AB0_VGT_STRMOUT_EN */
2577 r600_store_value(cb
, 1); /* R_028AB4_VGT_REUSE_OFF */
2578 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2580 r600_store_context_reg(cb
, R_028B20_VGT_STRMOUT_BUFFER_EN
, 0);
2582 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2584 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
2586 r600_store_context_reg_seq(cb
, R_0286DC_SPI_FOG_CNTL
, 3);
2587 r600_store_value(cb
, 0); /* R_0286DC_SPI_FOG_CNTL */
2588 r600_store_value(cb
, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2589 r600_store_value(cb
, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2591 r600_store_context_reg_seq(cb
, R_028D2C_DB_SRESULTS_COMPARE_STATE1
, 2);
2592 r600_store_value(cb
, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2593 r600_store_value(cb
, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2595 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2596 r600_store_context_reg(cb
, R_028A48_PA_SC_MPASS_PS_CNTL
, 0);
2598 r600_store_context_reg_seq(cb
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 4);
2599 r600_store_value(cb
, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2600 r600_store_value(cb
, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2601 r600_store_value(cb
, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2602 r600_store_value(cb
, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2604 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
2605 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2606 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2608 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x43F);
2610 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2611 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2613 if (rctx
->chip_class
>= R700
) {
2614 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2617 r600_store_context_reg_seq(cb
, R_028C30_CB_CLRCMP_CONTROL
, 4);
2618 r600_store_value(cb
, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2619 r600_store_value(cb
, 0); /* R_028C34_CB_CLRCMP_SRC */
2620 r600_store_value(cb
, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2621 r600_store_value(cb
, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2623 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2624 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2625 r600_store_value(cb
, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2627 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2628 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2629 r600_store_value(cb
, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2631 r600_store_context_reg_seq(cb
, R_0288CC_SQ_PGM_CF_OFFSET_PS
, 2);
2632 r600_store_value(cb
, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2633 r600_store_value(cb
, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2635 r600_store_context_reg(cb
, R_0288E0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
2637 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2638 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2639 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2641 r600_store_context_reg(cb
, R_0288A4_SQ_PGM_RESOURCES_FS
, 0);
2642 r600_store_context_reg(cb
, R_0288DC_SQ_PGM_CF_OFFSET_FS
, 0);
2644 if (rctx
->chip_class
== R700
&& rctx
->screen
->has_streamout
)
2645 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
2646 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2647 if (rctx
->screen
->has_streamout
) {
2648 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2651 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
, 0x1000FFF);
2652 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
+ (32 * 4), 0x1000FFF);
2655 void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2657 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2658 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2659 struct r600_shader
*rshader
= &shader
->shader
;
2660 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
;
2661 int pos_index
= -1, face_index
= -1;
2662 unsigned tmp
, sid
, ufi
= 0;
2663 int need_linear
= 0;
2664 unsigned z_export
= 0, stencil_export
= 0;
2665 unsigned sprite_coord_enable
= rctx
->rasterizer
? rctx
->rasterizer
->sprite_coord_enable
: 0;
2669 for (i
= 0; i
< rshader
->ninput
; i
++) {
2670 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
2672 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
2675 sid
= rshader
->input
[i
].spi_sid
;
2677 tmp
= S_028644_SEMANTIC(sid
);
2679 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
2680 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2681 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
2682 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
))
2683 tmp
|= S_028644_FLAT_SHADE(1);
2685 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
2686 sprite_coord_enable
& (1 << rshader
->input
[i
].sid
)) {
2687 tmp
|= S_028644_PT_SPRITE_TEX(1);
2690 if (rshader
->input
[i
].centroid
)
2691 tmp
|= S_028644_SEL_CENTROID(1);
2693 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
) {
2695 tmp
|= S_028644_SEL_LINEAR(1);
2698 r600_pipe_state_add_reg(rstate
, R_028644_SPI_PS_INPUT_CNTL_0
+ i
* 4,
2702 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2703 for (i
= 0; i
< rshader
->noutput
; i
++) {
2704 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2706 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2709 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(z_export
);
2710 db_shader_control
|= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export
);
2711 if (rshader
->uses_kill
)
2712 db_shader_control
|= S_02880C_KILL_ENABLE(1);
2715 for (i
= 0; i
< rshader
->noutput
; i
++) {
2716 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
2717 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
) {
2721 num_cout
= rshader
->nr_ps_color_exports
;
2722 exports_ps
|= S_028854_EXPORT_COLORS(num_cout
);
2724 /* always at least export 1 component per pixel */
2728 shader
->nr_ps_color_outputs
= num_cout
;
2730 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(rshader
->ninput
) |
2731 S_0286CC_PERSP_GRADIENT_ENA(1)|
2732 S_0286CC_LINEAR_GRADIENT_ENA(need_linear
);
2734 if (pos_index
!= -1) {
2735 spi_ps_in_control_0
|= (S_0286CC_POSITION_ENA(1) |
2736 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
2737 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
) |
2738 S_0286CC_BARYC_SAMPLE_CNTL(1));
2742 spi_ps_in_control_1
= 0;
2743 if (face_index
!= -1) {
2744 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
2745 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
2748 /* HW bug in original R600 */
2749 if (rctx
->family
== CHIP_R600
)
2752 r600_pipe_state_add_reg(rstate
, R_0286CC_SPI_PS_IN_CONTROL_0
, spi_ps_in_control_0
);
2753 r600_pipe_state_add_reg(rstate
, R_0286D0_SPI_PS_IN_CONTROL_1
, spi_ps_in_control_1
);
2754 r600_pipe_state_add_reg(rstate
, R_0286D8_SPI_INPUT_Z
, spi_input_z
);
2755 r600_pipe_state_add_reg_bo(rstate
,
2756 R_028840_SQ_PGM_START_PS
,
2757 0, shader
->bo
, RADEON_USAGE_READ
);
2758 r600_pipe_state_add_reg(rstate
,
2759 R_028850_SQ_PGM_RESOURCES_PS
,
2760 S_028850_NUM_GPRS(rshader
->bc
.ngpr
) |
2761 S_028850_STACK_SIZE(rshader
->bc
.nstack
) |
2762 S_028850_UNCACHED_FIRST_INST(ufi
));
2763 r600_pipe_state_add_reg(rstate
,
2764 R_028854_SQ_PGM_EXPORTS_PS
,
2766 /* only set some bits here, the other bits are set in the dsa state */
2767 shader
->db_shader_control
= db_shader_control
;
2768 shader
->ps_depth_export
= z_export
| stencil_export
;
2770 shader
->sprite_coord_enable
= sprite_coord_enable
;
2771 if (rctx
->rasterizer
)
2772 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
2775 void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2777 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2778 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2779 struct r600_shader
*rshader
= &shader
->shader
;
2780 unsigned spi_vs_out_id
[10] = {};
2781 unsigned i
, tmp
, nparams
= 0;
2783 /* clear previous register */
2786 for (i
= 0; i
< rshader
->noutput
; i
++) {
2787 if (rshader
->output
[i
].spi_sid
) {
2788 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
2789 spi_vs_out_id
[nparams
/ 4] |= tmp
;
2794 for (i
= 0; i
< 10; i
++) {
2795 r600_pipe_state_add_reg(rstate
,
2796 R_028614_SPI_VS_OUT_ID_0
+ i
* 4,
2800 /* Certain attributes (position, psize, etc.) don't count as params.
2801 * VS is required to export at least one param and r600_shader_from_tgsi()
2802 * takes care of adding a dummy export.
2807 r600_pipe_state_add_reg(rstate
,
2808 R_0286C4_SPI_VS_OUT_CONFIG
,
2809 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
2810 r600_pipe_state_add_reg(rstate
,
2811 R_028868_SQ_PGM_RESOURCES_VS
,
2812 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
2813 S_028868_STACK_SIZE(rshader
->bc
.nstack
));
2814 r600_pipe_state_add_reg_bo(rstate
,
2815 R_028858_SQ_PGM_START_VS
,
2816 0, shader
->bo
, RADEON_USAGE_READ
);
2818 shader
->pa_cl_vs_out_cntl
=
2819 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
2820 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
2821 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
2822 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
);
2825 void *r600_create_resolve_blend(struct r600_context
*rctx
)
2827 struct pipe_blend_state blend
;
2830 memset(&blend
, 0, sizeof(blend
));
2831 blend
.independent_blend_enable
= true;
2832 for (i
= 0; i
< 2; i
++) {
2833 blend
.rt
[i
].colormask
= 0xf;
2834 blend
.rt
[i
].blend_enable
= 1;
2835 blend
.rt
[i
].rgb_func
= PIPE_BLEND_ADD
;
2836 blend
.rt
[i
].alpha_func
= PIPE_BLEND_ADD
;
2837 blend
.rt
[i
].rgb_src_factor
= PIPE_BLENDFACTOR_ZERO
;
2838 blend
.rt
[i
].rgb_dst_factor
= PIPE_BLENDFACTOR_ZERO
;
2839 blend
.rt
[i
].alpha_src_factor
= PIPE_BLENDFACTOR_ZERO
;
2840 blend
.rt
[i
].alpha_dst_factor
= PIPE_BLENDFACTOR_ZERO
;
2842 return r600_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_SPECIAL_RESOLVE_BOX
);
2845 void *r700_create_resolve_blend(struct r600_context
*rctx
)
2847 struct pipe_blend_state blend
;
2849 memset(&blend
, 0, sizeof(blend
));
2850 blend
.independent_blend_enable
= true;
2851 blend
.rt
[0].colormask
= 0xf;
2852 return r600_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_SPECIAL_RESOLVE_BOX
);
2855 void *r600_create_decompress_blend(struct r600_context
*rctx
)
2857 struct pipe_blend_state blend
;
2859 memset(&blend
, 0, sizeof(blend
));
2860 blend
.independent_blend_enable
= true;
2861 blend
.rt
[0].colormask
= 0xf;
2862 return r600_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_SPECIAL_EXPAND_SAMPLES
);
2865 void *r600_create_db_flush_dsa(struct r600_context
*rctx
)
2867 struct pipe_depth_stencil_alpha_state dsa
;
2868 boolean quirk
= false;
2870 if (rctx
->family
== CHIP_RV610
|| rctx
->family
== CHIP_RV630
||
2871 rctx
->family
== CHIP_RV620
|| rctx
->family
== CHIP_RV635
)
2874 memset(&dsa
, 0, sizeof(dsa
));
2877 dsa
.depth
.enabled
= 1;
2878 dsa
.depth
.func
= PIPE_FUNC_LEQUAL
;
2879 dsa
.stencil
[0].enabled
= 1;
2880 dsa
.stencil
[0].func
= PIPE_FUNC_ALWAYS
;
2881 dsa
.stencil
[0].zpass_op
= PIPE_STENCIL_OP_KEEP
;
2882 dsa
.stencil
[0].zfail_op
= PIPE_STENCIL_OP_INCR
;
2883 dsa
.stencil
[0].writemask
= 0xff;
2886 return rctx
->context
.create_depth_stencil_alpha_state(&rctx
->context
, &dsa
);
2889 void r600_update_db_shader_control(struct r600_context
* rctx
)
2891 bool dual_export
= rctx
->framebuffer
.export_16bpc
&&
2892 !rctx
->ps_shader
->current
->ps_depth_export
;
2894 unsigned db_shader_control
= rctx
->ps_shader
->current
->db_shader_control
|
2895 S_02880C_DUAL_EXPORT_ENABLE(dual_export
);
2897 if (db_shader_control
!= rctx
->db_misc_state
.db_shader_control
) {
2898 rctx
->db_misc_state
.db_shader_control
= db_shader_control
;
2899 rctx
->db_misc_state
.atom
.dirty
= true;