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r600g: use common scissor and viewport code
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
145 {
146 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
147 }
148
149 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
150 {
151 return r600_translate_colorformat(chip, format) != ~0U &&
152 r600_translate_colorswap(format) != ~0U;
153 }
154
155 static bool r600_is_zs_format_supported(enum pipe_format format)
156 {
157 return r600_translate_dbformat(format) != ~0U;
158 }
159
160 boolean r600_is_format_supported(struct pipe_screen *screen,
161 enum pipe_format format,
162 enum pipe_texture_target target,
163 unsigned sample_count,
164 unsigned usage)
165 {
166 struct r600_screen *rscreen = (struct r600_screen*)screen;
167 unsigned retval = 0;
168
169 if (target >= PIPE_MAX_TEXTURE_TYPES) {
170 R600_ERR("r600: unsupported texture type %d\n", target);
171 return FALSE;
172 }
173
174 if (!util_format_is_supported(format, usage))
175 return FALSE;
176
177 if (sample_count > 1) {
178 if (!rscreen->has_msaa)
179 return FALSE;
180
181 /* R11G11B10 is broken on R6xx. */
182 if (rscreen->b.chip_class == R600 &&
183 format == PIPE_FORMAT_R11G11B10_FLOAT)
184 return FALSE;
185
186 /* MSAA integer colorbuffers hang. */
187 if (util_format_is_pure_integer(format) &&
188 !util_format_is_depth_or_stencil(format))
189 return FALSE;
190
191 switch (sample_count) {
192 case 2:
193 case 4:
194 case 8:
195 break;
196 default:
197 return FALSE;
198 }
199 }
200
201 if (usage & PIPE_BIND_SAMPLER_VIEW) {
202 if (target == PIPE_BUFFER) {
203 if (r600_is_vertex_format_supported(format))
204 retval |= PIPE_BIND_SAMPLER_VIEW;
205 } else {
206 if (r600_is_sampler_format_supported(screen, format))
207 retval |= PIPE_BIND_SAMPLER_VIEW;
208 }
209 }
210
211 if ((usage & (PIPE_BIND_RENDER_TARGET |
212 PIPE_BIND_DISPLAY_TARGET |
213 PIPE_BIND_SCANOUT |
214 PIPE_BIND_SHARED |
215 PIPE_BIND_BLENDABLE)) &&
216 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
217 retval |= usage &
218 (PIPE_BIND_RENDER_TARGET |
219 PIPE_BIND_DISPLAY_TARGET |
220 PIPE_BIND_SCANOUT |
221 PIPE_BIND_SHARED);
222 if (!util_format_is_pure_integer(format) &&
223 !util_format_is_depth_or_stencil(format))
224 retval |= usage & PIPE_BIND_BLENDABLE;
225 }
226
227 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
228 r600_is_zs_format_supported(format)) {
229 retval |= PIPE_BIND_DEPTH_STENCIL;
230 }
231
232 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
233 r600_is_vertex_format_supported(format)) {
234 retval |= PIPE_BIND_VERTEX_BUFFER;
235 }
236
237 if (usage & PIPE_BIND_TRANSFER_READ)
238 retval |= PIPE_BIND_TRANSFER_READ;
239 if (usage & PIPE_BIND_TRANSFER_WRITE)
240 retval |= PIPE_BIND_TRANSFER_WRITE;
241
242 if ((usage & PIPE_BIND_LINEAR) &&
243 !util_format_is_compressed(format) &&
244 !(usage & PIPE_BIND_DEPTH_STENCIL))
245 retval |= PIPE_BIND_LINEAR;
246
247 return retval == usage;
248 }
249
250 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
251 {
252 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
253 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
254 float offset_units = state->offset_units;
255 float offset_scale = state->offset_scale;
256
257 switch (state->zs_format) {
258 case PIPE_FORMAT_Z24X8_UNORM:
259 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
260 offset_units *= 2.0f;
261 break;
262 case PIPE_FORMAT_Z16_UNORM:
263 offset_units *= 4.0f;
264 break;
265 default:;
266 }
267
268 radeon_set_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
269 radeon_emit(cs, fui(offset_scale));
270 radeon_emit(cs, fui(offset_units));
271 radeon_emit(cs, fui(offset_scale));
272 radeon_emit(cs, fui(offset_units));
273 }
274
275 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
276 {
277 int j = state->independent_blend_enable ? i : 0;
278
279 unsigned eqRGB = state->rt[j].rgb_func;
280 unsigned srcRGB = state->rt[j].rgb_src_factor;
281 unsigned dstRGB = state->rt[j].rgb_dst_factor;
282
283 unsigned eqA = state->rt[j].alpha_func;
284 unsigned srcA = state->rt[j].alpha_src_factor;
285 unsigned dstA = state->rt[j].alpha_dst_factor;
286 uint32_t bc = 0;
287
288 if (!state->rt[j].blend_enable)
289 return 0;
290
291 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
292 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
293 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
294
295 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
296 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
297 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
298 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
299 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
300 }
301 return bc;
302 }
303
304 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
305 const struct pipe_blend_state *state,
306 int mode)
307 {
308 struct r600_context *rctx = (struct r600_context *)ctx;
309 uint32_t color_control = 0, target_mask = 0;
310 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
311
312 if (!blend) {
313 return NULL;
314 }
315
316 r600_init_command_buffer(&blend->buffer, 20);
317 r600_init_command_buffer(&blend->buffer_no_blend, 20);
318
319 /* R600 does not support per-MRT blends */
320 if (rctx->b.family > CHIP_R600)
321 color_control |= S_028808_PER_MRT_BLEND(1);
322
323 if (state->logicop_enable) {
324 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
325 } else {
326 color_control |= (0xcc << 16);
327 }
328 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
329 if (state->independent_blend_enable) {
330 for (int i = 0; i < 8; i++) {
331 if (state->rt[i].blend_enable) {
332 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
333 }
334 target_mask |= (state->rt[i].colormask << (4 * i));
335 }
336 } else {
337 for (int i = 0; i < 8; i++) {
338 if (state->rt[0].blend_enable) {
339 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
340 }
341 target_mask |= (state->rt[0].colormask << (4 * i));
342 }
343 }
344
345 if (target_mask)
346 color_control |= S_028808_SPECIAL_OP(mode);
347 else
348 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
349
350 /* only MRT0 has dual src blend */
351 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
352 blend->cb_target_mask = target_mask;
353 blend->cb_color_control = color_control;
354 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
355 blend->alpha_to_one = state->alpha_to_one;
356
357 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
358 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
359 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
360 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
361 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
362 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
363
364 /* Copy over the registers set so far into buffer_no_blend. */
365 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
366 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
367
368 /* Only add blend registers if blending is enabled. */
369 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
370 return blend;
371 }
372
373 /* The first R600 does not support per-MRT blends */
374 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
375 r600_get_blend_control(state, 0));
376
377 if (rctx->b.family > CHIP_R600) {
378 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
379 for (int i = 0; i < 8; i++) {
380 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
381 }
382 }
383 return blend;
384 }
385
386 static void *r600_create_blend_state(struct pipe_context *ctx,
387 const struct pipe_blend_state *state)
388 {
389 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
390 }
391
392 static void *r600_create_dsa_state(struct pipe_context *ctx,
393 const struct pipe_depth_stencil_alpha_state *state)
394 {
395 unsigned db_depth_control, alpha_test_control, alpha_ref;
396 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
397
398 if (!dsa) {
399 return NULL;
400 }
401
402 r600_init_command_buffer(&dsa->buffer, 3);
403
404 dsa->valuemask[0] = state->stencil[0].valuemask;
405 dsa->valuemask[1] = state->stencil[1].valuemask;
406 dsa->writemask[0] = state->stencil[0].writemask;
407 dsa->writemask[1] = state->stencil[1].writemask;
408 dsa->zwritemask = state->depth.writemask;
409
410 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
411 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
412 S_028800_ZFUNC(state->depth.func);
413
414 /* stencil */
415 if (state->stencil[0].enabled) {
416 db_depth_control |= S_028800_STENCIL_ENABLE(1);
417 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
418 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
419 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
420 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
421
422 if (state->stencil[1].enabled) {
423 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
424 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
425 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
426 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
427 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
428 }
429 }
430
431 /* alpha */
432 alpha_test_control = 0;
433 alpha_ref = 0;
434 if (state->alpha.enabled) {
435 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
436 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
437 alpha_ref = fui(state->alpha.ref_value);
438 }
439 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
440 dsa->alpha_ref = alpha_ref;
441
442 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
443 return dsa;
444 }
445
446 static void *r600_create_rs_state(struct pipe_context *ctx,
447 const struct pipe_rasterizer_state *state)
448 {
449 struct r600_context *rctx = (struct r600_context *)ctx;
450 unsigned tmp, sc_mode_cntl, spi_interp;
451 float psize_min, psize_max;
452 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
453
454 if (!rs) {
455 return NULL;
456 }
457
458 r600_init_command_buffer(&rs->buffer, 30);
459
460 rs->scissor_enable = state->scissor;
461 rs->flatshade = state->flatshade;
462 rs->sprite_coord_enable = state->sprite_coord_enable;
463 rs->two_side = state->light_twoside;
464 rs->clip_plane_enable = state->clip_plane_enable;
465 rs->pa_sc_line_stipple = state->line_stipple_enable ?
466 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
467 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
468 rs->pa_cl_clip_cntl =
469 S_028810_PS_UCP_MODE(3) |
470 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
471 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
472 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
473 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
474 if (rctx->b.chip_class == R700) {
475 rs->pa_cl_clip_cntl |=
476 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
477 }
478 rs->multisample_enable = state->multisample;
479
480 /* offset */
481 rs->offset_units = state->offset_units;
482 rs->offset_scale = state->offset_scale * 16.0f;
483 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
484
485 if (state->point_size_per_vertex) {
486 psize_min = util_get_min_point_size(state);
487 psize_max = 8192;
488 } else {
489 /* Force the point size to be as if the vertex output was disabled. */
490 psize_min = state->point_size;
491 psize_max = state->point_size;
492 }
493
494 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
495 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
496 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
497 S_028A4C_PS_ITER_SAMPLE(state->multisample && rctx->ps_iter_samples > 1);
498 if (rctx->b.family == CHIP_RV770) {
499 /* workaround possible rendering corruption on RV770 with hyperz together with sample shading */
500 sc_mode_cntl |= S_028A4C_TILE_COVER_DISABLE(state->multisample && rctx->ps_iter_samples > 1);
501 }
502 if (rctx->b.chip_class >= R700) {
503 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
504 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
505 S_028A4C_R700_VPORT_SCISSOR_ENABLE(1);
506 } else {
507 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
508 }
509
510 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
511 if (state->sprite_coord_enable) {
512 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
513 S_0286D4_PNT_SPRITE_OVRD_X(2) |
514 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
515 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
516 S_0286D4_PNT_SPRITE_OVRD_W(1);
517 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
518 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
519 }
520 }
521
522 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
523 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
524 tmp = r600_pack_float_12p4(state->point_size/2);
525 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
526 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
527 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
528 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
529 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
530 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
531 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
532
533 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
534 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
535 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
536 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
537 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
538 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
539
540 rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
541 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
542 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
543 S_028814_FACE(!state->front_ccw) |
544 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
545 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
546 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
547 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
548 state->fill_back != PIPE_POLYGON_MODE_FILL) |
549 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
550 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
551 if (rctx->b.chip_class == R700) {
552 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl);
553 }
554 if (rctx->b.chip_class == R600) {
555 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC,
556 S_028350_MULTIPASS(state->rasterizer_discard));
557 }
558 return rs;
559 }
560
561 static unsigned r600_tex_filter(unsigned filter, unsigned max_aniso)
562 {
563 if (filter == PIPE_TEX_FILTER_LINEAR)
564 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_BILINEAR
565 : V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
566 else
567 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_POINT
568 : V_03C000_SQ_TEX_XY_FILTER_POINT;
569 }
570
571 static void *r600_create_sampler_state(struct pipe_context *ctx,
572 const struct pipe_sampler_state *state)
573 {
574 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
575
576 if (!ss) {
577 return NULL;
578 }
579
580 ss->seamless_cube_map = state->seamless_cube_map;
581 ss->border_color_use = sampler_state_needs_border_color(state);
582
583 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
584 ss->tex_sampler_words[0] =
585 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
586 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
587 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
588 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter, state->max_anisotropy)) |
589 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter, state->max_anisotropy)) |
590 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
591 S_03C000_MAX_ANISO_RATIO(r600_tex_aniso_filter(state->max_anisotropy)) |
592 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
593 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
594 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
595 ss->tex_sampler_words[1] =
596 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
597 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
598 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
599 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
600 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
601
602 if (ss->border_color_use) {
603 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
604 }
605 return ss;
606 }
607
608 static struct pipe_sampler_view *
609 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
610 unsigned width0, unsigned height0)
611
612 {
613 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
614 int stride = util_format_get_blocksize(view->base.format);
615 unsigned format, num_format, format_comp, endian;
616 uint64_t offset = view->base.u.buf.first_element * stride;
617 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
618
619 r600_vertex_data_type(view->base.format,
620 &format, &num_format, &format_comp,
621 &endian);
622
623 view->tex_resource = &tmp->resource;
624 view->skip_mip_address_reloc = true;
625
626 view->tex_resource_words[0] = offset;
627 view->tex_resource_words[1] = size - 1;
628 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(offset >> 32UL) |
629 S_038008_STRIDE(stride) |
630 S_038008_DATA_FORMAT(format) |
631 S_038008_NUM_FORMAT_ALL(num_format) |
632 S_038008_FORMAT_COMP_ALL(format_comp) |
633 S_038008_ENDIAN_SWAP(endian);
634 view->tex_resource_words[3] = 0;
635 /*
636 * in theory dword 4 is for number of elements, for use with resinfo,
637 * but it seems to utterly fail to work, the amd gpu shader analyser
638 * uses a const buffer to store the element sizes for buffer txq
639 */
640 view->tex_resource_words[4] = 0;
641 view->tex_resource_words[5] = 0;
642 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
643 return &view->base;
644 }
645
646 struct pipe_sampler_view *
647 r600_create_sampler_view_custom(struct pipe_context *ctx,
648 struct pipe_resource *texture,
649 const struct pipe_sampler_view *state,
650 unsigned width_first_level, unsigned height_first_level)
651 {
652 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
653 struct r600_texture *tmp = (struct r600_texture*)texture;
654 unsigned format, endian;
655 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
656 unsigned char swizzle[4], array_mode = 0;
657 unsigned width, height, depth, offset_level, last_level;
658
659 if (!view)
660 return NULL;
661
662 /* initialize base object */
663 view->base = *state;
664 view->base.texture = NULL;
665 pipe_reference(NULL, &texture->reference);
666 view->base.texture = texture;
667 view->base.reference.count = 1;
668 view->base.context = ctx;
669
670 if (texture->target == PIPE_BUFFER)
671 return texture_buffer_sampler_view(view, texture->width0, 1);
672
673 swizzle[0] = state->swizzle_r;
674 swizzle[1] = state->swizzle_g;
675 swizzle[2] = state->swizzle_b;
676 swizzle[3] = state->swizzle_a;
677
678 format = r600_translate_texformat(ctx->screen, state->format,
679 swizzle,
680 &word4, &yuv_format);
681 assert(format != ~0);
682 if (format == ~0) {
683 FREE(view);
684 return NULL;
685 }
686
687 if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) {
688 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
689 FREE(view);
690 return NULL;
691 }
692 tmp = tmp->flushed_depth_texture;
693 }
694
695 endian = r600_colorformat_endian_swap(format);
696
697 offset_level = state->u.tex.first_level;
698 last_level = state->u.tex.last_level - offset_level;
699 width = width_first_level;
700 height = height_first_level;
701 depth = u_minify(texture->depth0, offset_level);
702 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
703
704 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
705 height = 1;
706 depth = texture->array_size;
707 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
708 depth = texture->array_size;
709 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
710 depth = texture->array_size / 6;
711 switch (tmp->surface.level[offset_level].mode) {
712 case RADEON_SURF_MODE_LINEAR_ALIGNED:
713 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
714 break;
715 case RADEON_SURF_MODE_1D:
716 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
717 break;
718 case RADEON_SURF_MODE_2D:
719 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
720 break;
721 case RADEON_SURF_MODE_LINEAR:
722 default:
723 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
724 break;
725 }
726
727 if (state->format == PIPE_FORMAT_X24S8_UINT ||
728 state->format == PIPE_FORMAT_S8X24_UINT ||
729 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
730 state->format == PIPE_FORMAT_S8_UINT)
731 view->is_stencil_sampler = true;
732
733 view->tex_resource = &tmp->resource;
734 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
735 S_038000_TILE_MODE(array_mode) |
736 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
737 S_038000_PITCH((pitch / 8) - 1) |
738 S_038000_TEX_WIDTH(width - 1));
739 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
740 S_038004_TEX_DEPTH(depth - 1) |
741 S_038004_DATA_FORMAT(format));
742 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
743 if (offset_level >= tmp->surface.last_level) {
744 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
745 } else {
746 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
747 }
748 view->tex_resource_words[4] = (word4 |
749 S_038010_REQUEST_SIZE(1) |
750 S_038010_ENDIAN_SWAP(endian) |
751 S_038010_BASE_LEVEL(0));
752 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
753 S_038014_LAST_ARRAY(state->u.tex.last_layer));
754 if (texture->nr_samples > 1) {
755 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
756 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
757 } else {
758 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
759 }
760 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
761 S_038018_MAX_ANISO(4 /* max 16 samples */));
762 return &view->base;
763 }
764
765 static struct pipe_sampler_view *
766 r600_create_sampler_view(struct pipe_context *ctx,
767 struct pipe_resource *tex,
768 const struct pipe_sampler_view *state)
769 {
770 return r600_create_sampler_view_custom(ctx, tex, state,
771 u_minify(tex->width0, state->u.tex.first_level),
772 u_minify(tex->height0, state->u.tex.first_level));
773 }
774
775 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
776 {
777 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
778 struct pipe_clip_state *state = &rctx->clip_state.state;
779
780 radeon_set_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
781 radeon_emit_array(cs, (unsigned*)state, 6*4);
782 }
783
784 static void r600_set_polygon_stipple(struct pipe_context *ctx,
785 const struct pipe_poly_stipple *state)
786 {
787 }
788
789 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
790 unsigned size, unsigned alignment)
791 {
792 struct pipe_resource buffer;
793
794 memset(&buffer, 0, sizeof buffer);
795 buffer.target = PIPE_BUFFER;
796 buffer.format = PIPE_FORMAT_R8_UNORM;
797 buffer.bind = PIPE_BIND_CUSTOM;
798 buffer.usage = PIPE_USAGE_DEFAULT;
799 buffer.flags = 0;
800 buffer.width0 = size;
801 buffer.height0 = 1;
802 buffer.depth0 = 1;
803 buffer.array_size = 1;
804
805 return (struct r600_resource*)
806 r600_buffer_create(&rscreen->b.b, &buffer, alignment);
807 }
808
809 static void r600_init_color_surface(struct r600_context *rctx,
810 struct r600_surface *surf,
811 bool force_cmask_fmask)
812 {
813 struct r600_screen *rscreen = rctx->screen;
814 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
815 unsigned level = surf->base.u.tex.level;
816 unsigned pitch, slice;
817 unsigned color_info;
818 unsigned color_view;
819 unsigned format, swap, ntype, endian;
820 unsigned offset;
821 const struct util_format_description *desc;
822 int i;
823 bool blend_bypass = 0, blend_clamp = 1;
824
825 if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
826 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
827 rtex = rtex->flushed_depth_texture;
828 assert(rtex);
829 }
830
831 offset = rtex->surface.level[level].offset;
832 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
833 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
834 offset += rtex->surface.level[level].slice_size *
835 surf->base.u.tex.first_layer;
836 color_view = 0;
837 } else
838 color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
839 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
840
841 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
842 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
843 if (slice) {
844 slice = slice - 1;
845 }
846 color_info = 0;
847 switch (rtex->surface.level[level].mode) {
848 case RADEON_SURF_MODE_LINEAR_ALIGNED:
849 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
850 break;
851 case RADEON_SURF_MODE_1D:
852 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
853 break;
854 case RADEON_SURF_MODE_2D:
855 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
856 break;
857 case RADEON_SURF_MODE_LINEAR:
858 default:
859 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
860 break;
861 }
862
863 desc = util_format_description(surf->base.format);
864
865 for (i = 0; i < 4; i++) {
866 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
867 break;
868 }
869 }
870
871 ntype = V_0280A0_NUMBER_UNORM;
872 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
873 ntype = V_0280A0_NUMBER_SRGB;
874 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
875 if (desc->channel[i].normalized)
876 ntype = V_0280A0_NUMBER_SNORM;
877 else if (desc->channel[i].pure_integer)
878 ntype = V_0280A0_NUMBER_SINT;
879 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
880 if (desc->channel[i].normalized)
881 ntype = V_0280A0_NUMBER_UNORM;
882 else if (desc->channel[i].pure_integer)
883 ntype = V_0280A0_NUMBER_UINT;
884 }
885
886 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
887 assert(format != ~0);
888
889 swap = r600_translate_colorswap(surf->base.format);
890 assert(swap != ~0);
891
892 endian = r600_colorformat_endian_swap(format);
893
894 /* set blend bypass according to docs if SINT/UINT or
895 8/24 COLOR variants */
896 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
897 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
898 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
899 blend_clamp = 0;
900 blend_bypass = 1;
901 }
902
903 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
904
905 color_info |= S_0280A0_FORMAT(format) |
906 S_0280A0_COMP_SWAP(swap) |
907 S_0280A0_BLEND_BYPASS(blend_bypass) |
908 S_0280A0_BLEND_CLAMP(blend_clamp) |
909 S_0280A0_NUMBER_TYPE(ntype) |
910 S_0280A0_ENDIAN(endian);
911
912 /* EXPORT_NORM is an optimzation that can be enabled for better
913 * performance in certain cases
914 */
915 if (rctx->b.chip_class == R600) {
916 /* EXPORT_NORM can be enabled if:
917 * - 11-bit or smaller UNORM/SNORM/SRGB
918 * - BLEND_CLAMP is enabled
919 * - BLEND_FLOAT32 is disabled
920 */
921 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
922 (desc->channel[i].size < 12 &&
923 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
924 ntype != V_0280A0_NUMBER_UINT &&
925 ntype != V_0280A0_NUMBER_SINT) &&
926 G_0280A0_BLEND_CLAMP(color_info) &&
927 !G_0280A0_BLEND_FLOAT32(color_info)) {
928 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
929 surf->export_16bpc = true;
930 }
931 } else {
932 /* EXPORT_NORM can be enabled if:
933 * - 11-bit or smaller UNORM/SNORM/SRGB
934 * - 16-bit or smaller FLOAT
935 */
936 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
937 ((desc->channel[i].size < 12 &&
938 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
939 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
940 (desc->channel[i].size < 17 &&
941 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
942 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
943 surf->export_16bpc = true;
944 }
945 }
946
947 /* These might not always be initialized to zero. */
948 surf->cb_color_base = offset >> 8;
949 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
950 S_028060_SLICE_TILE_MAX(slice);
951 surf->cb_color_fmask = surf->cb_color_base;
952 surf->cb_color_cmask = surf->cb_color_base;
953 surf->cb_color_mask = 0;
954
955 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
956 &rtex->resource.b.b);
957 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
958 &rtex->resource.b.b);
959
960 if (rtex->cmask.size) {
961 surf->cb_color_cmask = rtex->cmask.offset >> 8;
962 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
963
964 if (rtex->fmask.size) {
965 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
966 surf->cb_color_fmask = rtex->fmask.offset >> 8;
967 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
968 } else { /* cmask only */
969 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
970 }
971 } else if (force_cmask_fmask) {
972 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
973 *
974 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
975 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
976 * because it's not an MSAA buffer.
977 */
978 struct r600_cmask_info cmask;
979 struct r600_fmask_info fmask;
980
981 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
982 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
983
984 /* CMASK. */
985 if (!rctx->dummy_cmask ||
986 rctx->dummy_cmask->b.b.width0 < cmask.size ||
987 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
988 struct pipe_transfer *transfer;
989 void *ptr;
990
991 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
992 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
993
994 /* Set the contents to 0xCC. */
995 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
996 memset(ptr, 0xCC, cmask.size);
997 pipe_buffer_unmap(&rctx->b.b, transfer);
998 }
999 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1000 &rctx->dummy_cmask->b.b);
1001
1002 /* FMASK. */
1003 if (!rctx->dummy_fmask ||
1004 rctx->dummy_fmask->b.b.width0 < fmask.size ||
1005 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1006 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1007 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1008
1009 }
1010 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1011 &rctx->dummy_fmask->b.b);
1012
1013 /* Init the registers. */
1014 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1015 surf->cb_color_cmask = 0;
1016 surf->cb_color_fmask = 0;
1017 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1018 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1019 }
1020
1021 surf->cb_color_info = color_info;
1022 surf->cb_color_view = color_view;
1023 surf->color_initialized = true;
1024 }
1025
1026 static void r600_init_depth_surface(struct r600_context *rctx,
1027 struct r600_surface *surf)
1028 {
1029 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1030 unsigned level, pitch, slice, format, offset, array_mode;
1031
1032 level = surf->base.u.tex.level;
1033 offset = rtex->surface.level[level].offset;
1034 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1035 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1036 if (slice) {
1037 slice = slice - 1;
1038 }
1039 switch (rtex->surface.level[level].mode) {
1040 case RADEON_SURF_MODE_2D:
1041 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1042 break;
1043 case RADEON_SURF_MODE_1D:
1044 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1045 case RADEON_SURF_MODE_LINEAR:
1046 default:
1047 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1048 break;
1049 }
1050
1051 format = r600_translate_dbformat(surf->base.format);
1052 assert(format != ~0);
1053
1054 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1055 surf->db_depth_base = offset >> 8;
1056 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1057 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1058 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1059 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1060
1061 switch (surf->base.format) {
1062 case PIPE_FORMAT_Z24X8_UNORM:
1063 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1064 surf->pa_su_poly_offset_db_fmt_cntl =
1065 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1066 break;
1067 case PIPE_FORMAT_Z32_FLOAT:
1068 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1069 surf->pa_su_poly_offset_db_fmt_cntl =
1070 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1071 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1072 break;
1073 case PIPE_FORMAT_Z16_UNORM:
1074 surf->pa_su_poly_offset_db_fmt_cntl =
1075 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1076 break;
1077 default:;
1078 }
1079
1080 /* use htile only for first level */
1081 if (rtex->htile_buffer && !level) {
1082 surf->db_htile_data_base = 0;
1083 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1084 S_028D24_HTILE_HEIGHT(1) |
1085 S_028D24_FULL_CACHE(1);
1086 /* preload is not working properly on r6xx/r7xx */
1087 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1088 }
1089
1090 surf->depth_initialized = true;
1091 }
1092
1093 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1094 const struct pipe_framebuffer_state *state)
1095 {
1096 struct r600_context *rctx = (struct r600_context *)ctx;
1097 struct r600_surface *surf;
1098 struct r600_texture *rtex;
1099 unsigned i;
1100
1101 if (rctx->framebuffer.state.nr_cbufs) {
1102 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1103 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1104 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1105 }
1106 if (rctx->framebuffer.state.zsbuf) {
1107 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1108 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1109
1110 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1111 if (rctx->b.chip_class >= R700 && rtex->htile_buffer) {
1112 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1113 }
1114 }
1115
1116 /* Set the new state. */
1117 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1118
1119 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1120 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1121 util_format_is_pure_integer(state->cbufs[0]->format);
1122 rctx->framebuffer.compressed_cb_mask = 0;
1123 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1124 state->cbufs[0] && state->cbufs[1] &&
1125 state->cbufs[0]->texture->nr_samples > 1 &&
1126 state->cbufs[1]->texture->nr_samples <= 1;
1127 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1128
1129 /* Colorbuffers. */
1130 for (i = 0; i < state->nr_cbufs; i++) {
1131 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1132 bool force_cmask_fmask = rctx->b.chip_class == R600 &&
1133 rctx->framebuffer.is_msaa_resolve &&
1134 i == 1;
1135
1136 surf = (struct r600_surface*)state->cbufs[i];
1137 if (!surf)
1138 continue;
1139
1140 rtex = (struct r600_texture*)surf->base.texture;
1141 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1142
1143 if (!surf->color_initialized || force_cmask_fmask) {
1144 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1145 if (force_cmask_fmask) {
1146 /* re-initialize later without compression */
1147 surf->color_initialized = false;
1148 }
1149 }
1150
1151 if (!surf->export_16bpc) {
1152 rctx->framebuffer.export_16bpc = false;
1153 }
1154
1155 if (rtex->fmask.size && rtex->cmask.size) {
1156 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1157 }
1158 }
1159
1160 /* Update alpha-test state dependencies.
1161 * Alpha-test is done on the first colorbuffer only. */
1162 if (state->nr_cbufs) {
1163 bool alphatest_bypass = false;
1164
1165 surf = (struct r600_surface*)state->cbufs[0];
1166 if (surf) {
1167 alphatest_bypass = surf->alphatest_bypass;
1168 }
1169
1170 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1171 rctx->alphatest_state.bypass = alphatest_bypass;
1172 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1173 }
1174 }
1175
1176 /* ZS buffer. */
1177 if (state->zsbuf) {
1178 surf = (struct r600_surface*)state->zsbuf;
1179
1180 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1181
1182 if (!surf->depth_initialized) {
1183 r600_init_depth_surface(rctx, surf);
1184 }
1185
1186 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1187 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1188 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1189 }
1190
1191 if (rctx->db_state.rsurf != surf) {
1192 rctx->db_state.rsurf = surf;
1193 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1194 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1195 }
1196 } else if (rctx->db_state.rsurf) {
1197 rctx->db_state.rsurf = NULL;
1198 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1199 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1200 }
1201
1202 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1203 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1204 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1205 }
1206
1207 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1208 rctx->alphatest_state.bypass = false;
1209 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1210 }
1211
1212 /* Calculate the CS size. */
1213 rctx->framebuffer.atom.num_dw =
1214 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1215
1216 if (rctx->framebuffer.state.nr_cbufs) {
1217 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
1218 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
1219 }
1220 if (rctx->framebuffer.state.zsbuf) {
1221 rctx->framebuffer.atom.num_dw += 16;
1222 } else if (rctx->screen->b.info.drm_minor >= 18) {
1223 rctx->framebuffer.atom.num_dw += 3;
1224 }
1225 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1226 rctx->framebuffer.atom.num_dw += 2;
1227 }
1228
1229 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1230
1231 r600_set_sample_locations_constant_buffer(rctx);
1232 }
1233
1234 static uint32_t sample_locs_2x[] = {
1235 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1236 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1237 };
1238 static unsigned max_dist_2x = 4;
1239
1240 static uint32_t sample_locs_4x[] = {
1241 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1242 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1243 };
1244 static unsigned max_dist_4x = 6;
1245 static uint32_t sample_locs_8x[] = {
1246 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1247 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1248 };
1249 static unsigned max_dist_8x = 7;
1250
1251 static void r600_get_sample_position(struct pipe_context *ctx,
1252 unsigned sample_count,
1253 unsigned sample_index,
1254 float *out_value)
1255 {
1256 int offset, index;
1257 struct {
1258 int idx:4;
1259 } val;
1260 switch (sample_count) {
1261 case 1:
1262 default:
1263 out_value[0] = out_value[1] = 0.5;
1264 break;
1265 case 2:
1266 offset = 4 * (sample_index * 2);
1267 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1268 out_value[0] = (float)(val.idx + 8) / 16.0f;
1269 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1270 out_value[1] = (float)(val.idx + 8) / 16.0f;
1271 break;
1272 case 4:
1273 offset = 4 * (sample_index * 2);
1274 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1275 out_value[0] = (float)(val.idx + 8) / 16.0f;
1276 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1277 out_value[1] = (float)(val.idx + 8) / 16.0f;
1278 break;
1279 case 8:
1280 offset = 4 * (sample_index % 4 * 2);
1281 index = (sample_index / 4);
1282 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1283 out_value[0] = (float)(val.idx + 8) / 16.0f;
1284 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1285 out_value[1] = (float)(val.idx + 8) / 16.0f;
1286 break;
1287 }
1288 }
1289
1290 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1291 {
1292 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1293 unsigned max_dist = 0;
1294
1295 if (rctx->b.family == CHIP_R600) {
1296 switch (nr_samples) {
1297 default:
1298 nr_samples = 0;
1299 break;
1300 case 2:
1301 radeon_set_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1302 max_dist = max_dist_2x;
1303 break;
1304 case 4:
1305 radeon_set_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1306 max_dist = max_dist_4x;
1307 break;
1308 case 8:
1309 radeon_set_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1310 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1311 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1312 max_dist = max_dist_8x;
1313 break;
1314 }
1315 } else {
1316 switch (nr_samples) {
1317 default:
1318 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1319 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1320 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1321 nr_samples = 0;
1322 break;
1323 case 2:
1324 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1325 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1326 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1327 max_dist = max_dist_2x;
1328 break;
1329 case 4:
1330 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1331 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1332 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1333 max_dist = max_dist_4x;
1334 break;
1335 case 8:
1336 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1337 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1338 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1339 max_dist = max_dist_8x;
1340 break;
1341 }
1342 }
1343
1344 if (nr_samples > 1) {
1345 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1346 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1347 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1348 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1349 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1350 } else {
1351 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1352 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1353 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1354 }
1355 }
1356
1357 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1358 {
1359 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1360 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1361 unsigned nr_cbufs = state->nr_cbufs;
1362 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1363 unsigned i, sbu = 0;
1364
1365 /* Colorbuffers. */
1366 radeon_set_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1367 for (i = 0; i < nr_cbufs; i++) {
1368 radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0);
1369 }
1370 /* set CB_COLOR1_INFO for possible dual-src blending */
1371 if (i == 1 && cb[0]) {
1372 radeon_emit(cs, cb[0]->cb_color_info);
1373 i++;
1374 }
1375 for (; i < 8; i++) {
1376 radeon_emit(cs, 0);
1377 }
1378
1379 if (nr_cbufs) {
1380 for (i = 0; i < nr_cbufs; i++) {
1381 unsigned reloc;
1382
1383 if (!cb[i])
1384 continue;
1385
1386 /* COLOR_BASE */
1387 radeon_set_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1388
1389 reloc = radeon_add_to_buffer_list(&rctx->b,
1390 &rctx->b.gfx,
1391 (struct r600_resource*)cb[i]->base.texture,
1392 RADEON_USAGE_READWRITE,
1393 cb[i]->base.texture->nr_samples > 1 ?
1394 RADEON_PRIO_COLOR_BUFFER_MSAA :
1395 RADEON_PRIO_COLOR_BUFFER);
1396 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1397 radeon_emit(cs, reloc);
1398
1399 /* FMASK */
1400 radeon_set_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1401
1402 reloc = radeon_add_to_buffer_list(&rctx->b,
1403 &rctx->b.gfx,
1404 cb[i]->cb_buffer_fmask,
1405 RADEON_USAGE_READWRITE,
1406 cb[i]->base.texture->nr_samples > 1 ?
1407 RADEON_PRIO_COLOR_BUFFER_MSAA :
1408 RADEON_PRIO_COLOR_BUFFER);
1409 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1410 radeon_emit(cs, reloc);
1411
1412 /* CMASK */
1413 radeon_set_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1414
1415 reloc = radeon_add_to_buffer_list(&rctx->b,
1416 &rctx->b.gfx,
1417 cb[i]->cb_buffer_cmask,
1418 RADEON_USAGE_READWRITE,
1419 cb[i]->base.texture->nr_samples > 1 ?
1420 RADEON_PRIO_COLOR_BUFFER_MSAA :
1421 RADEON_PRIO_COLOR_BUFFER);
1422 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1423 radeon_emit(cs, reloc);
1424 }
1425
1426 radeon_set_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1427 for (i = 0; i < nr_cbufs; i++) {
1428 radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0);
1429 }
1430
1431 radeon_set_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1432 for (i = 0; i < nr_cbufs; i++) {
1433 radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0);
1434 }
1435
1436 radeon_set_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1437 for (i = 0; i < nr_cbufs; i++) {
1438 radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0);
1439 }
1440
1441 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1442 }
1443
1444 /* SURFACE_BASE_UPDATE */
1445 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1446 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1447 radeon_emit(cs, sbu);
1448 sbu = 0;
1449 }
1450
1451 /* Zbuffer. */
1452 if (state->zsbuf) {
1453 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1454 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1455 &rctx->b.gfx,
1456 (struct r600_resource*)state->zsbuf->texture,
1457 RADEON_USAGE_READWRITE,
1458 surf->base.texture->nr_samples > 1 ?
1459 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1460 RADEON_PRIO_DEPTH_BUFFER);
1461
1462 radeon_set_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1463 surf->pa_su_poly_offset_db_fmt_cntl);
1464
1465 radeon_set_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1466 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1467 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1468 radeon_set_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1469 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1470 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1471
1472 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1473 radeon_emit(cs, reloc);
1474
1475 radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1476
1477 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1478 } else if (rctx->screen->b.info.drm_minor >= 18) {
1479 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1480 * Older kernels are out of luck. */
1481 radeon_set_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1482 }
1483
1484 /* SURFACE_BASE_UPDATE */
1485 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1486 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1487 radeon_emit(cs, sbu);
1488 sbu = 0;
1489 }
1490
1491 /* Framebuffer dimensions. */
1492 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1493 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1494 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1495 radeon_emit(cs, S_028244_BR_X(state->width) |
1496 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1497
1498 if (rctx->framebuffer.is_msaa_resolve) {
1499 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1500 } else {
1501 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1502 * will assure that the alpha-test will work even if there is
1503 * no colorbuffer bound. */
1504 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1505 (1ull << MAX2(nr_cbufs, 1)) - 1);
1506 }
1507
1508 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1509 }
1510
1511 static void r600_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1512 {
1513 struct r600_context *rctx = (struct r600_context *)ctx;
1514
1515 if (rctx->ps_iter_samples == min_samples)
1516 return;
1517
1518 rctx->ps_iter_samples = min_samples;
1519 if (rctx->framebuffer.nr_samples > 1) {
1520 r600_mark_atom_dirty(rctx, &rctx->rasterizer_state.atom);
1521 if (rctx->b.chip_class == R600)
1522 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1523 }
1524 }
1525
1526 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1527 {
1528 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1529 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1530
1531 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1532 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1533 if (rctx->b.chip_class == R600) {
1534 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1535 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1536 } else {
1537 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1538 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1539 }
1540 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1541 } else {
1542 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1543 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1544 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1545
1546 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1547 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1548 /* Always enable the first color output to make sure alpha-test works even without one. */
1549 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1550 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1551 a->cb_color_control |
1552 S_028808_MULTIWRITE_ENABLE(multiwrite));
1553 }
1554 }
1555
1556 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1557 {
1558 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1559 struct r600_db_state *a = (struct r600_db_state*)atom;
1560
1561 if (a->rsurf && a->rsurf->db_htile_surface) {
1562 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1563 unsigned reloc_idx;
1564
1565 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1566 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1567 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1568 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
1569 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1570 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1571 cs->buf[cs->cdw++] = reloc_idx;
1572 } else {
1573 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1574 }
1575 }
1576
1577 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1578 {
1579 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1580 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1581 unsigned db_render_control = 0;
1582 unsigned db_render_override =
1583 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1584 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1585
1586 if (rctx->b.chip_class >= R700) {
1587 switch (a->ps_conservative_z) {
1588 default: /* fall through */
1589 case TGSI_FS_DEPTH_LAYOUT_ANY:
1590 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_ANY_Z);
1591 break;
1592 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1593 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_GREATER_THAN_Z);
1594 break;
1595 case TGSI_FS_DEPTH_LAYOUT_LESS:
1596 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_LESS_THAN_Z);
1597 break;
1598 }
1599 }
1600
1601 if (rctx->b.num_occlusion_queries > 0 &&
1602 !a->occlusion_queries_disabled) {
1603 if (rctx->b.chip_class >= R700) {
1604 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1605 }
1606 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1607 } else {
1608 db_render_control |= S_028D0C_ZPASS_INCREMENT_DISABLE(1);
1609 }
1610
1611 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
1612 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1613 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1614 /* This is to fix a lockup when hyperz and alpha test are enabled at
1615 * the same time somehow GPU get confuse on which order to pick for
1616 * z test
1617 */
1618 if (rctx->alphatest_state.sx_alpha_test_control) {
1619 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
1620 }
1621 } else {
1622 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1623 }
1624 if (rctx->b.chip_class == R600 && rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) {
1625 /* sample shading and hyperz causes lockups on R6xx chips */
1626 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1627 }
1628 if (a->flush_depthstencil_through_cb) {
1629 assert(a->copy_depth || a->copy_stencil);
1630
1631 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1632 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1633 S_028D0C_COPY_CENTROID(1) |
1634 S_028D0C_COPY_SAMPLE(a->copy_sample);
1635
1636 if (rctx->b.chip_class == R600)
1637 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1638
1639 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
1640 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
1641 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1642 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1643 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1644 S_028D0C_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1645 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1646 }
1647 if (a->htile_clear) {
1648 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1649 }
1650
1651 /* RV770 workaround for a hang with 8x MSAA. */
1652 if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) {
1653 db_render_override |= S_028D10_MAX_TILES_IN_DTT(6);
1654 }
1655
1656 radeon_set_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1657 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1658 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1659 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1660 }
1661
1662 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1663 {
1664 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1665 struct r600_config_state *a = (struct r600_config_state*)atom;
1666
1667 radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1668 radeon_set_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
1669 }
1670
1671 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1672 {
1673 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1674 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1675
1676 while (dirty_mask) {
1677 struct pipe_vertex_buffer *vb;
1678 struct r600_resource *rbuffer;
1679 unsigned offset;
1680 unsigned buffer_index = u_bit_scan(&dirty_mask);
1681
1682 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1683 rbuffer = (struct r600_resource*)vb->buffer;
1684 assert(rbuffer);
1685
1686 offset = vb->buffer_offset;
1687
1688 /* fetch resources start at index 320 (OFFSET_FS) */
1689 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1690 radeon_emit(cs, (R600_FETCH_CONSTANTS_OFFSET_FS + buffer_index) * 7);
1691 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1692 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1693 radeon_emit(cs, /* RESOURCEi_WORD2 */
1694 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1695 S_038008_STRIDE(vb->stride));
1696 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1697 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1698 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1699 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1700
1701 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1702 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1703 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1704 }
1705 }
1706
1707 static void r600_emit_constant_buffers(struct r600_context *rctx,
1708 struct r600_constbuf_state *state,
1709 unsigned buffer_id_base,
1710 unsigned reg_alu_constbuf_size,
1711 unsigned reg_alu_const_cache)
1712 {
1713 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1714 uint32_t dirty_mask = state->dirty_mask;
1715
1716 while (dirty_mask) {
1717 struct pipe_constant_buffer *cb;
1718 struct r600_resource *rbuffer;
1719 unsigned offset;
1720 unsigned buffer_index = ffs(dirty_mask) - 1;
1721 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1722 cb = &state->cb[buffer_index];
1723 rbuffer = (struct r600_resource*)cb->buffer;
1724 assert(rbuffer);
1725
1726 offset = cb->buffer_offset;
1727
1728 if (!gs_ring_buffer) {
1729 radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1730 DIV_ROUND_UP(cb->buffer_size, 256));
1731 radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1732 }
1733
1734 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1735 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1736 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1737
1738 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1739 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
1740 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1741 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1742 radeon_emit(cs, /* RESOURCEi_WORD2 */
1743 S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1744 S_038008_STRIDE(gs_ring_buffer ? 4 : 16));
1745 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1746 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1747 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1748 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1749
1750 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1751 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1752 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1753
1754 dirty_mask &= ~(1 << buffer_index);
1755 }
1756 state->dirty_mask = 0;
1757 }
1758
1759 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1760 {
1761 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1762 R600_FETCH_CONSTANTS_OFFSET_VS,
1763 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1764 R_028980_ALU_CONST_CACHE_VS_0);
1765 }
1766
1767 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1768 {
1769 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1770 R600_FETCH_CONSTANTS_OFFSET_GS,
1771 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1772 R_0289C0_ALU_CONST_CACHE_GS_0);
1773 }
1774
1775 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1776 {
1777 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1778 R600_FETCH_CONSTANTS_OFFSET_PS,
1779 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1780 R_028940_ALU_CONST_CACHE_PS_0);
1781 }
1782
1783 static void r600_emit_sampler_views(struct r600_context *rctx,
1784 struct r600_samplerview_state *state,
1785 unsigned resource_id_base)
1786 {
1787 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1788 uint32_t dirty_mask = state->dirty_mask;
1789
1790 while (dirty_mask) {
1791 struct r600_pipe_sampler_view *rview;
1792 unsigned resource_index = u_bit_scan(&dirty_mask);
1793 unsigned reloc;
1794
1795 rview = state->views[resource_index];
1796 assert(rview);
1797
1798 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1799 radeon_emit(cs, (resource_id_base + resource_index) * 7);
1800 radeon_emit_array(cs, rview->tex_resource_words, 7);
1801
1802 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
1803 RADEON_USAGE_READ,
1804 r600_get_sampler_view_priority(rview->tex_resource));
1805 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1806 radeon_emit(cs, reloc);
1807 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1808 radeon_emit(cs, reloc);
1809 }
1810 state->dirty_mask = 0;
1811 }
1812
1813
1814 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1815 {
1816 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, R600_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS);
1817 }
1818
1819 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1820 {
1821 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, R600_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS);
1822 }
1823
1824 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1825 {
1826 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS);
1827 }
1828
1829 static void r600_emit_sampler_states(struct r600_context *rctx,
1830 struct r600_textures_info *texinfo,
1831 unsigned resource_id_base,
1832 unsigned border_color_reg)
1833 {
1834 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1835 uint32_t dirty_mask = texinfo->states.dirty_mask;
1836
1837 while (dirty_mask) {
1838 struct r600_pipe_sampler_state *rstate;
1839 struct r600_pipe_sampler_view *rview;
1840 unsigned i = u_bit_scan(&dirty_mask);
1841
1842 rstate = texinfo->states.states[i];
1843 assert(rstate);
1844 rview = texinfo->views.views[i];
1845
1846 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1847 * filtering between layers.
1848 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1849 */
1850 if (rview) {
1851 enum pipe_texture_target target = rview->base.texture->target;
1852 if (target == PIPE_TEXTURE_1D_ARRAY ||
1853 target == PIPE_TEXTURE_2D_ARRAY) {
1854 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1855 texinfo->is_array_sampler[i] = true;
1856 } else {
1857 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1858 texinfo->is_array_sampler[i] = false;
1859 }
1860 }
1861
1862 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1863 radeon_emit(cs, (resource_id_base + i) * 3);
1864 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
1865
1866 if (rstate->border_color_use) {
1867 unsigned offset;
1868
1869 offset = border_color_reg;
1870 offset += i * 16;
1871 radeon_set_config_reg_seq(cs, offset, 4);
1872 radeon_emit_array(cs, rstate->border_color.ui, 4);
1873 }
1874 }
1875 texinfo->states.dirty_mask = 0;
1876 }
1877
1878 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1879 {
1880 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1881 }
1882
1883 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1884 {
1885 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1886 }
1887
1888 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1889 {
1890 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1891 }
1892
1893 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1894 {
1895 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1896 unsigned tmp;
1897
1898 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1899 S_009508_SYNC_GRADIENT(1) |
1900 S_009508_SYNC_WALKER(1) |
1901 S_009508_SYNC_ALIGNER(1);
1902 if (!rctx->seamless_cube_map.enabled) {
1903 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1904 }
1905 radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1906 }
1907
1908 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1909 {
1910 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1911 uint8_t mask = s->sample_mask;
1912
1913 radeon_set_context_reg(rctx->b.gfx.cs, R_028C48_PA_SC_AA_MASK,
1914 mask | (mask << 8) | (mask << 16) | (mask << 24));
1915 }
1916
1917 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
1918 {
1919 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1920 struct r600_cso_state *state = (struct r600_cso_state*)a;
1921 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
1922
1923 radeon_set_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
1924 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1925 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
1926 RADEON_USAGE_READ,
1927 RADEON_PRIO_INTERNAL_SHADER));
1928 }
1929
1930 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
1931 {
1932 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1933 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
1934
1935 uint32_t v2 = 0, primid = 0;
1936
1937 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
1938 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1939 primid = 1;
1940 }
1941
1942 if (state->geom_enable) {
1943 uint32_t cut_val;
1944
1945 if (rctx->gs_shader->gs_max_out_vertices <= 128)
1946 cut_val = V_028A40_GS_CUT_128;
1947 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
1948 cut_val = V_028A40_GS_CUT_256;
1949 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
1950 cut_val = V_028A40_GS_CUT_512;
1951 else
1952 cut_val = V_028A40_GS_CUT_1024;
1953
1954 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1955 S_028A40_CUT_MODE(cut_val);
1956
1957 if (rctx->gs_shader->current->shader.gs_prim_id_input)
1958 primid = 1;
1959 }
1960
1961 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
1962 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
1963 }
1964
1965 static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
1966 {
1967 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1968 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
1969 struct r600_resource *rbuffer;
1970
1971 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1972 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1973 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1974
1975 if (state->enable) {
1976 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
1977 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
1978 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1979 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1980 RADEON_USAGE_READWRITE,
1981 RADEON_PRIO_RINGS_STREAMOUT));
1982 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
1983 state->esgs_ring.buffer_size >> 8);
1984
1985 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
1986 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
1987 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1988 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1989 RADEON_USAGE_READWRITE,
1990 RADEON_PRIO_RINGS_STREAMOUT));
1991 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
1992 state->gsvs_ring.buffer_size >> 8);
1993 } else {
1994 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
1995 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
1996 }
1997
1998 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1999 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2000 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2001 }
2002
2003 /* Adjust GPR allocation on R6xx/R7xx */
2004 bool r600_adjust_gprs(struct r600_context *rctx)
2005 {
2006 unsigned num_gprs[R600_NUM_HW_STAGES];
2007 unsigned new_gprs[R600_NUM_HW_STAGES];
2008 unsigned cur_gprs[R600_NUM_HW_STAGES];
2009 unsigned def_gprs[R600_NUM_HW_STAGES];
2010 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
2011 unsigned max_gprs;
2012 unsigned tmp, tmp2;
2013 unsigned i;
2014 bool need_recalc = false, use_default = true;
2015
2016 /* hardware will reserve twice num_clause_temp_gprs */
2017 max_gprs = def_num_clause_temp_gprs * 2;
2018 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2019 def_gprs[i] = rctx->default_gprs[i];
2020 max_gprs += def_gprs[i];
2021 }
2022
2023 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2024 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2025 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2026 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2027
2028 num_gprs[R600_HW_STAGE_PS] = rctx->ps_shader->current->shader.bc.ngpr;
2029 if (rctx->gs_shader) {
2030 num_gprs[R600_HW_STAGE_ES] = rctx->vs_shader->current->shader.bc.ngpr;
2031 num_gprs[R600_HW_STAGE_GS] = rctx->gs_shader->current->shader.bc.ngpr;
2032 num_gprs[R600_HW_STAGE_VS] = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
2033 } else {
2034 num_gprs[R600_HW_STAGE_ES] = 0;
2035 num_gprs[R600_HW_STAGE_GS] = 0;
2036 num_gprs[R600_HW_STAGE_VS] = rctx->vs_shader->current->shader.bc.ngpr;
2037 }
2038
2039 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2040 new_gprs[i] = num_gprs[i];
2041 if (new_gprs[i] > cur_gprs[i])
2042 need_recalc = true;
2043 if (new_gprs[i] > def_gprs[i])
2044 use_default = false;
2045 }
2046
2047 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2048 if (!need_recalc)
2049 return true;
2050
2051 /* try to use switch back to default */
2052 if (!use_default) {
2053 /* always privilege vs stage so that at worst we have the
2054 * pixel stage producing wrong output (not the vertex
2055 * stage) */
2056 new_gprs[R600_HW_STAGE_PS] = max_gprs - def_num_clause_temp_gprs * 2;
2057 for (i = R600_HW_STAGE_VS; i < R600_NUM_HW_STAGES; i++)
2058 new_gprs[R600_HW_STAGE_PS] -= new_gprs[i];
2059 } else {
2060 for (i = 0; i < R600_NUM_HW_STAGES; i++)
2061 new_gprs[i] = def_gprs[i];
2062 }
2063
2064 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2065 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2066 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2067 * it will lockup. So in this case just discard the draw command
2068 * and don't change the current gprs repartitions.
2069 */
2070 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2071 if (num_gprs[i] > new_gprs[i]) {
2072 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2073 "for a combined maximum of %d\n",
2074 num_gprs[R600_HW_STAGE_PS], num_gprs[R600_HW_STAGE_VS], num_gprs[R600_HW_STAGE_ES], num_gprs[R600_HW_STAGE_GS], max_gprs);
2075 return false;
2076 }
2077 }
2078
2079 /* in some case we endup recomputing the current value */
2080 tmp = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
2081 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
2082 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2083
2084 tmp2 = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
2085 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
2086 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2087 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2088 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2;
2089 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
2090 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2091 }
2092 return true;
2093 }
2094
2095 void r600_init_atom_start_cs(struct r600_context *rctx)
2096 {
2097 int ps_prio;
2098 int vs_prio;
2099 int gs_prio;
2100 int es_prio;
2101 int num_ps_gprs;
2102 int num_vs_gprs;
2103 int num_gs_gprs;
2104 int num_es_gprs;
2105 int num_temp_gprs;
2106 int num_ps_threads;
2107 int num_vs_threads;
2108 int num_gs_threads;
2109 int num_es_threads;
2110 int num_ps_stack_entries;
2111 int num_vs_stack_entries;
2112 int num_gs_stack_entries;
2113 int num_es_stack_entries;
2114 enum radeon_family family;
2115 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2116 uint32_t tmp, i;
2117
2118 r600_init_command_buffer(cb, 256);
2119
2120 /* R6xx requires this packet at the start of each command buffer */
2121 if (rctx->b.chip_class == R600) {
2122 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2123 r600_store_value(cb, 0);
2124 }
2125 /* All asics require this one */
2126 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2127 r600_store_value(cb, 0x80000000);
2128 r600_store_value(cb, 0x80000000);
2129
2130 /* We're setting config registers here. */
2131 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2132 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2133
2134 /* This enables pipeline stat & streamout queries.
2135 * They are only disabled by blits.
2136 */
2137 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2138 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2139
2140 family = rctx->b.family;
2141 ps_prio = 0;
2142 vs_prio = 1;
2143 gs_prio = 2;
2144 es_prio = 3;
2145 switch (family) {
2146 case CHIP_R600:
2147 num_ps_gprs = 192;
2148 num_vs_gprs = 56;
2149 num_temp_gprs = 4;
2150 num_gs_gprs = 0;
2151 num_es_gprs = 0;
2152 num_ps_threads = 136;
2153 num_vs_threads = 48;
2154 num_gs_threads = 4;
2155 num_es_threads = 4;
2156 num_ps_stack_entries = 128;
2157 num_vs_stack_entries = 128;
2158 num_gs_stack_entries = 0;
2159 num_es_stack_entries = 0;
2160 break;
2161 case CHIP_RV630:
2162 case CHIP_RV635:
2163 num_ps_gprs = 84;
2164 num_vs_gprs = 36;
2165 num_temp_gprs = 4;
2166 num_gs_gprs = 0;
2167 num_es_gprs = 0;
2168 num_ps_threads = 144;
2169 num_vs_threads = 40;
2170 num_gs_threads = 4;
2171 num_es_threads = 4;
2172 num_ps_stack_entries = 40;
2173 num_vs_stack_entries = 40;
2174 num_gs_stack_entries = 32;
2175 num_es_stack_entries = 16;
2176 break;
2177 case CHIP_RV610:
2178 case CHIP_RV620:
2179 case CHIP_RS780:
2180 case CHIP_RS880:
2181 default:
2182 num_ps_gprs = 84;
2183 num_vs_gprs = 36;
2184 num_temp_gprs = 4;
2185 num_gs_gprs = 0;
2186 num_es_gprs = 0;
2187 /* use limits 40 VS and at least 16 ES/GS */
2188 num_ps_threads = 120;
2189 num_vs_threads = 40;
2190 num_gs_threads = 16;
2191 num_es_threads = 16;
2192 num_ps_stack_entries = 40;
2193 num_vs_stack_entries = 40;
2194 num_gs_stack_entries = 32;
2195 num_es_stack_entries = 16;
2196 break;
2197 case CHIP_RV670:
2198 num_ps_gprs = 144;
2199 num_vs_gprs = 40;
2200 num_temp_gprs = 4;
2201 num_gs_gprs = 0;
2202 num_es_gprs = 0;
2203 num_ps_threads = 136;
2204 num_vs_threads = 48;
2205 num_gs_threads = 4;
2206 num_es_threads = 4;
2207 num_ps_stack_entries = 40;
2208 num_vs_stack_entries = 40;
2209 num_gs_stack_entries = 32;
2210 num_es_stack_entries = 16;
2211 break;
2212 case CHIP_RV770:
2213 num_ps_gprs = 130;
2214 num_vs_gprs = 56;
2215 num_temp_gprs = 4;
2216 num_gs_gprs = 31;
2217 num_es_gprs = 31;
2218 num_ps_threads = 180;
2219 num_vs_threads = 60;
2220 num_gs_threads = 4;
2221 num_es_threads = 4;
2222 num_ps_stack_entries = 128;
2223 num_vs_stack_entries = 128;
2224 num_gs_stack_entries = 128;
2225 num_es_stack_entries = 128;
2226 break;
2227 case CHIP_RV730:
2228 case CHIP_RV740:
2229 num_ps_gprs = 84;
2230 num_vs_gprs = 36;
2231 num_temp_gprs = 4;
2232 num_gs_gprs = 0;
2233 num_es_gprs = 0;
2234 num_ps_threads = 180;
2235 num_vs_threads = 60;
2236 num_gs_threads = 4;
2237 num_es_threads = 4;
2238 num_ps_stack_entries = 128;
2239 num_vs_stack_entries = 128;
2240 num_gs_stack_entries = 0;
2241 num_es_stack_entries = 0;
2242 break;
2243 case CHIP_RV710:
2244 num_ps_gprs = 192;
2245 num_vs_gprs = 56;
2246 num_temp_gprs = 4;
2247 num_gs_gprs = 0;
2248 num_es_gprs = 0;
2249 num_ps_threads = 136;
2250 num_vs_threads = 48;
2251 num_gs_threads = 4;
2252 num_es_threads = 4;
2253 num_ps_stack_entries = 128;
2254 num_vs_stack_entries = 128;
2255 num_gs_stack_entries = 0;
2256 num_es_stack_entries = 0;
2257 break;
2258 }
2259
2260 rctx->default_gprs[R600_HW_STAGE_PS] = num_ps_gprs;
2261 rctx->default_gprs[R600_HW_STAGE_VS] = num_vs_gprs;
2262 rctx->default_gprs[R600_HW_STAGE_GS] = 0;
2263 rctx->default_gprs[R600_HW_STAGE_ES] = 0;
2264
2265 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2266
2267 /* SQ_CONFIG */
2268 tmp = 0;
2269 switch (family) {
2270 case CHIP_RV610:
2271 case CHIP_RV620:
2272 case CHIP_RS780:
2273 case CHIP_RS880:
2274 case CHIP_RV710:
2275 break;
2276 default:
2277 tmp |= S_008C00_VC_ENABLE(1);
2278 break;
2279 }
2280 tmp |= S_008C00_DX9_CONSTS(0);
2281 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2282 tmp |= S_008C00_PS_PRIO(ps_prio);
2283 tmp |= S_008C00_VS_PRIO(vs_prio);
2284 tmp |= S_008C00_GS_PRIO(gs_prio);
2285 tmp |= S_008C00_ES_PRIO(es_prio);
2286 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2287
2288 /* SQ_GPR_RESOURCE_MGMT_2 */
2289 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2290 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2291 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2292 r600_store_value(cb, tmp);
2293
2294 /* SQ_THREAD_RESOURCE_MGMT */
2295 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2296 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2297 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2298 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2299 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2300
2301 /* SQ_STACK_RESOURCE_MGMT_1 */
2302 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2303 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2304 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2305
2306 /* SQ_STACK_RESOURCE_MGMT_2 */
2307 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2308 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2309 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2310
2311 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2312
2313 if (rctx->b.chip_class >= R700) {
2314 r600_store_context_reg(cb, R_028A50_VGT_ENHANCE, 4);
2315 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2316 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2317 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2318 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2319 } else {
2320 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2321 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2322 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2323 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2324 }
2325 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2326 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2327 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2328 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2329 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2330 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2331 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2332 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2333 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2334 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2335
2336 /* to avoid GPU doing any preloading of constant from random address */
2337 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2338 for (i = 0; i < 16; i++)
2339 r600_store_value(cb, 0);
2340
2341 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2342 for (i = 0; i < 16; i++)
2343 r600_store_value(cb, 0);
2344
2345 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2346 for (i = 0; i < 16; i++)
2347 r600_store_value(cb, 0);
2348
2349 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2350 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2351 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2352 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2353 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2354 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2355 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2356 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2357 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2358 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2359 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2360 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2361 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2362 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2363
2364 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2365 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2366 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2367
2368 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2369 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2370 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2371
2372 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2373
2374 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2375
2376 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2377
2378 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2379 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2380 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2381 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2382
2383 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2384 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2385 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2386 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2387
2388 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2389 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2390
2391 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2392 for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2393 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2394 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2395 }
2396
2397 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2398 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2399
2400 if (rctx->b.chip_class >= R700) {
2401 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2402 }
2403
2404 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2405 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2406 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2407 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2408 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2409
2410 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2411 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2412 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2413
2414 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2415 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2416 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2417
2418 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5);
2419 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2420 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2421 r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2422 r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2423 r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2424
2425 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2426
2427 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2428 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2429 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2430
2431 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2432
2433 if (rctx->b.chip_class == R700)
2434 r600_store_context_reg(cb, R_028350_SX_MISC, 0);
2435 if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
2436 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2437
2438 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2439 if (rctx->screen->b.has_streamout) {
2440 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2441 }
2442
2443 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2444 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2445 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF);
2446 }
2447
2448 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2449 {
2450 struct r600_context *rctx = (struct r600_context *)ctx;
2451 struct r600_command_buffer *cb = &shader->command_buffer;
2452 struct r600_shader *rshader = &shader->shader;
2453 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2454 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2455 unsigned tmp, sid, ufi = 0;
2456 int need_linear = 0;
2457 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2458 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2459
2460 if (!cb->buf) {
2461 r600_init_command_buffer(cb, 64);
2462 } else {
2463 cb->num_dw = 0;
2464 }
2465
2466 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2467 for (i = 0; i < rshader->ninput; i++) {
2468 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2469 pos_index = i;
2470 if (rshader->input[i].name == TGSI_SEMANTIC_FACE && face_index == -1)
2471 face_index = i;
2472 if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID)
2473 fixed_pt_position_index = i;
2474
2475 sid = rshader->input[i].spi_sid;
2476
2477 tmp = S_028644_SEMANTIC(sid);
2478
2479 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2480 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2481 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2482 rctx->rasterizer && rctx->rasterizer->flatshade))
2483 tmp |= S_028644_FLAT_SHADE(1);
2484
2485 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2486 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2487 tmp |= S_028644_PT_SPRITE_TEX(1);
2488 }
2489
2490 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID)
2491 tmp |= S_028644_SEL_CENTROID(1);
2492
2493 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE)
2494 tmp |= S_028644_SEL_SAMPLE(1);
2495
2496 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2497 need_linear = 1;
2498 tmp |= S_028644_SEL_LINEAR(1);
2499 }
2500
2501 r600_store_value(cb, tmp);
2502 }
2503
2504 db_shader_control = 0;
2505 for (i = 0; i < rshader->noutput; i++) {
2506 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2507 z_export = 1;
2508 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2509 stencil_export = 1;
2510 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
2511 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
2512 mask_export = 1;
2513 }
2514 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2515 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2516 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
2517 if (rshader->uses_kill)
2518 db_shader_control |= S_02880C_KILL_ENABLE(1);
2519
2520 exports_ps = 0;
2521 for (i = 0; i < rshader->noutput; i++) {
2522 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2523 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
2524 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2525 exports_ps |= 1;
2526 }
2527 }
2528 num_cout = rshader->nr_ps_color_exports;
2529 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2530 if (!exports_ps) {
2531 /* always at least export 1 component per pixel */
2532 exports_ps = 2;
2533 }
2534
2535 shader->nr_ps_color_outputs = num_cout;
2536
2537 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2538 S_0286CC_PERSP_GRADIENT_ENA(1)|
2539 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2540 spi_input_z = 0;
2541 if (pos_index != -1) {
2542 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2543 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
2544 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2545 S_0286CC_BARYC_SAMPLE_CNTL(1)) |
2546 S_0286CC_POSITION_SAMPLE(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE);
2547 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2548 }
2549
2550 spi_ps_in_control_1 = 0;
2551 if (face_index != -1) {
2552 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2553 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2554 }
2555 if (fixed_pt_position_index != -1) {
2556 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
2557 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
2558 }
2559
2560 /* HW bug in original R600 */
2561 if (rctx->b.family == CHIP_R600)
2562 ufi = 1;
2563
2564 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2565 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2566 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2567
2568 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2569
2570 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2571 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2572 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2573 S_028850_STACK_SIZE(rshader->bc.nstack) |
2574 S_028850_UNCACHED_FIRST_INST(ufi));
2575 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2576
2577 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2578 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2579
2580 /* only set some bits here, the other bits are set in the dsa state */
2581 shader->db_shader_control = db_shader_control;
2582 shader->ps_depth_export = z_export | stencil_export | mask_export;
2583
2584 shader->sprite_coord_enable = sprite_coord_enable;
2585 if (rctx->rasterizer)
2586 shader->flatshade = rctx->rasterizer->flatshade;
2587 }
2588
2589 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2590 {
2591 struct r600_command_buffer *cb = &shader->command_buffer;
2592 struct r600_shader *rshader = &shader->shader;
2593 unsigned spi_vs_out_id[10] = {};
2594 unsigned i, tmp, nparams = 0;
2595
2596 for (i = 0; i < rshader->noutput; i++) {
2597 if (rshader->output[i].spi_sid) {
2598 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2599 spi_vs_out_id[nparams / 4] |= tmp;
2600 nparams++;
2601 }
2602 }
2603
2604 r600_init_command_buffer(cb, 32);
2605
2606 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2607 for (i = 0; i < 10; i++) {
2608 r600_store_value(cb, spi_vs_out_id[i]);
2609 }
2610
2611 /* Certain attributes (position, psize, etc.) don't count as params.
2612 * VS is required to export at least one param and r600_shader_from_tgsi()
2613 * takes care of adding a dummy export.
2614 */
2615 if (nparams < 1)
2616 nparams = 1;
2617
2618 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2619 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2620 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2621 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2622 S_028868_STACK_SIZE(rshader->bc.nstack));
2623 if (rshader->vs_position_window_space) {
2624 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2625 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
2626 } else {
2627 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2628 S_028818_VTX_W0_FMT(1) |
2629 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2630 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2631 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2632
2633 }
2634 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2635 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2636
2637 shader->pa_cl_vs_out_cntl =
2638 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2639 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2640 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2641 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
2642 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
2643 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) |
2644 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport);
2645 }
2646
2647 #define RV610_GSVS_ALIGN 32
2648 #define R600_GSVS_ALIGN 16
2649
2650 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2651 {
2652 struct r600_context *rctx = (struct r600_context *)ctx;
2653 struct r600_command_buffer *cb = &shader->command_buffer;
2654 struct r600_shader *rshader = &shader->shader;
2655 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
2656 unsigned gsvs_itemsize =
2657 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2;
2658
2659 /* some r600s needs gsvs itemsize aligned to cacheline size
2660 this was fixed in rs780 and above. */
2661 switch (rctx->b.family) {
2662 case CHIP_RV610:
2663 gsvs_itemsize = align(gsvs_itemsize, RV610_GSVS_ALIGN);
2664 break;
2665 case CHIP_R600:
2666 case CHIP_RV630:
2667 case CHIP_RV670:
2668 case CHIP_RV620:
2669 case CHIP_RV635:
2670 gsvs_itemsize = align(gsvs_itemsize, R600_GSVS_ALIGN);
2671 break;
2672 default:
2673 break;
2674 }
2675
2676 r600_init_command_buffer(cb, 64);
2677
2678 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2679 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
2680
2681 if (rctx->b.chip_class >= R700) {
2682 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
2683 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
2684 }
2685 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
2686 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
2687
2688 r600_store_context_reg(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE,
2689 cp_shader->ring_item_sizes[0] >> 2);
2690
2691 r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
2692 (rshader->ring_item_sizes[0]) >> 2);
2693
2694 r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE,
2695 gsvs_itemsize);
2696
2697 /* FIXME calculate these values somehow ??? */
2698 r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2);
2699 r600_store_value(cb, 0x80); /* GS_PER_ES */
2700 r600_store_value(cb, 0x100); /* ES_PER_GS */
2701 r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1);
2702 r600_store_value(cb, 0x2); /* GS_PER_VS */
2703
2704 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS,
2705 S_02887C_NUM_GPRS(rshader->bc.ngpr) |
2706 S_02887C_STACK_SIZE(rshader->bc.nstack));
2707 r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, 0);
2708 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2709 }
2710
2711 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2712 {
2713 struct r600_command_buffer *cb = &shader->command_buffer;
2714 struct r600_shader *rshader = &shader->shader;
2715
2716 r600_init_command_buffer(cb, 32);
2717
2718 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
2719 S_028890_NUM_GPRS(rshader->bc.ngpr) |
2720 S_028890_STACK_SIZE(rshader->bc.nstack));
2721 r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, 0);
2722 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2723 }
2724
2725
2726 void *r600_create_resolve_blend(struct r600_context *rctx)
2727 {
2728 struct pipe_blend_state blend;
2729 unsigned i;
2730
2731 memset(&blend, 0, sizeof(blend));
2732 blend.independent_blend_enable = true;
2733 for (i = 0; i < 2; i++) {
2734 blend.rt[i].colormask = 0xf;
2735 blend.rt[i].blend_enable = 1;
2736 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2737 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2738 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2739 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2740 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2741 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2742 }
2743 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2744 }
2745
2746 void *r700_create_resolve_blend(struct r600_context *rctx)
2747 {
2748 struct pipe_blend_state blend;
2749
2750 memset(&blend, 0, sizeof(blend));
2751 blend.independent_blend_enable = true;
2752 blend.rt[0].colormask = 0xf;
2753 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2754 }
2755
2756 void *r600_create_decompress_blend(struct r600_context *rctx)
2757 {
2758 struct pipe_blend_state blend;
2759
2760 memset(&blend, 0, sizeof(blend));
2761 blend.independent_blend_enable = true;
2762 blend.rt[0].colormask = 0xf;
2763 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2764 }
2765
2766 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2767 {
2768 struct pipe_depth_stencil_alpha_state dsa;
2769 boolean quirk = false;
2770
2771 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2772 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2773 quirk = true;
2774
2775 memset(&dsa, 0, sizeof(dsa));
2776
2777 if (quirk) {
2778 dsa.depth.enabled = 1;
2779 dsa.depth.func = PIPE_FUNC_LEQUAL;
2780 dsa.stencil[0].enabled = 1;
2781 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2782 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2783 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2784 dsa.stencil[0].writemask = 0xff;
2785 }
2786
2787 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2788 }
2789
2790 void r600_update_db_shader_control(struct r600_context * rctx)
2791 {
2792 bool dual_export;
2793 unsigned db_shader_control;
2794 uint8_t ps_conservative_z;
2795
2796 if (!rctx->ps_shader) {
2797 return;
2798 }
2799
2800 dual_export = rctx->framebuffer.export_16bpc &&
2801 !rctx->ps_shader->current->ps_depth_export;
2802
2803 db_shader_control = rctx->ps_shader->current->db_shader_control |
2804 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2805
2806 ps_conservative_z = rctx->ps_shader->current->shader.ps_conservative_z;
2807
2808 /* When alpha test is enabled we can't trust the hw to make the proper
2809 * decision on the order in which ztest should be run related to fragment
2810 * shader execution.
2811 *
2812 * If alpha test is enabled perform z test after fragment. RE_Z (early
2813 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2814 */
2815 if (rctx->alphatest_state.sx_alpha_test_control) {
2816 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2817 } else {
2818 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2819 }
2820
2821 if (db_shader_control != rctx->db_misc_state.db_shader_control ||
2822 ps_conservative_z != rctx->db_misc_state.ps_conservative_z) {
2823 rctx->db_misc_state.db_shader_control = db_shader_control;
2824 rctx->db_misc_state.ps_conservative_z = ps_conservative_z;
2825 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
2826 }
2827 }
2828
2829 static inline unsigned r600_array_mode(unsigned mode)
2830 {
2831 switch (mode) {
2832 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
2833 break;
2834 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
2835 break;
2836 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
2837 default:
2838 case RADEON_SURF_MODE_LINEAR: return V_0280A0_ARRAY_LINEAR_GENERAL;
2839 }
2840 }
2841
2842 static boolean r600_dma_copy_tile(struct r600_context *rctx,
2843 struct pipe_resource *dst,
2844 unsigned dst_level,
2845 unsigned dst_x,
2846 unsigned dst_y,
2847 unsigned dst_z,
2848 struct pipe_resource *src,
2849 unsigned src_level,
2850 unsigned src_x,
2851 unsigned src_y,
2852 unsigned src_z,
2853 unsigned copy_height,
2854 unsigned pitch,
2855 unsigned bpp)
2856 {
2857 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
2858 struct r600_texture *rsrc = (struct r600_texture*)src;
2859 struct r600_texture *rdst = (struct r600_texture*)dst;
2860 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
2861 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
2862 uint64_t base, addr;
2863
2864 dst_mode = rdst->surface.level[dst_level].mode;
2865 src_mode = rsrc->surface.level[src_level].mode;
2866 /* downcast linear aligned to linear to simplify test */
2867 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
2868 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
2869 assert(dst_mode != src_mode);
2870
2871 y = 0;
2872 lbpp = util_logbase2(bpp);
2873 pitch_tile_max = ((pitch / bpp) / 8) - 1;
2874
2875 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
2876 /* T2L */
2877 array_mode = r600_array_mode(src_mode);
2878 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
2879 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2880 /* linear height must be the same as the slice tile max height, it's ok even
2881 * if the linear destination/source have smaller heigh as the size of the
2882 * dma packet will be using the copy_height which is always smaller or equal
2883 * to the linear height
2884 */
2885 height = rsrc->surface.level[src_level].npix_y;
2886 detile = 1;
2887 x = src_x;
2888 y = src_y;
2889 z = src_z;
2890 base = rsrc->surface.level[src_level].offset;
2891 addr = rdst->surface.level[dst_level].offset;
2892 addr += rdst->surface.level[dst_level].slice_size * dst_z;
2893 addr += dst_y * pitch + dst_x * bpp;
2894 } else {
2895 /* L2T */
2896 array_mode = r600_array_mode(dst_mode);
2897 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
2898 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2899 /* linear height must be the same as the slice tile max height, it's ok even
2900 * if the linear destination/source have smaller heigh as the size of the
2901 * dma packet will be using the copy_height which is always smaller or equal
2902 * to the linear height
2903 */
2904 height = rdst->surface.level[dst_level].npix_y;
2905 detile = 0;
2906 x = dst_x;
2907 y = dst_y;
2908 z = dst_z;
2909 base = rdst->surface.level[dst_level].offset;
2910 addr = rsrc->surface.level[src_level].offset;
2911 addr += rsrc->surface.level[src_level].slice_size * src_z;
2912 addr += src_y * pitch + src_x * bpp;
2913 }
2914 /* check that we are in dw/base alignment constraint */
2915 if (addr % 4 || base % 256) {
2916 return FALSE;
2917 }
2918
2919 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2920 * line in the blit. Compute max 8 line we can copy in the size limit
2921 */
2922 cheight = ((R600_DMA_COPY_MAX_SIZE_DW * 4) / pitch) & 0xfffffff8;
2923 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
2924 r600_need_dma_space(&rctx->b, ncopy * 7);
2925
2926 for (i = 0; i < ncopy; i++) {
2927 cheight = cheight > copy_height ? copy_height : cheight;
2928 size = (cheight * pitch) / 4;
2929 /* emit reloc before writing cs so that cs is always in consistent state */
2930 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, RADEON_USAGE_READ,
2931 RADEON_PRIO_SDMA_TEXTURE);
2932 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE,
2933 RADEON_PRIO_SDMA_TEXTURE);
2934 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 1, 0, size);
2935 cs->buf[cs->cdw++] = base >> 8;
2936 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
2937 (lbpp << 24) | ((height - 1) << 10) |
2938 pitch_tile_max;
2939 cs->buf[cs->cdw++] = (slice_tile_max << 12) | (z << 0);
2940 cs->buf[cs->cdw++] = (x << 3) | (y << 17);
2941 cs->buf[cs->cdw++] = addr & 0xfffffffc;
2942 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
2943 copy_height -= cheight;
2944 addr += cheight * pitch;
2945 y += cheight;
2946 }
2947 return TRUE;
2948 }
2949
2950 static void r600_dma_copy(struct pipe_context *ctx,
2951 struct pipe_resource *dst,
2952 unsigned dst_level,
2953 unsigned dstx, unsigned dsty, unsigned dstz,
2954 struct pipe_resource *src,
2955 unsigned src_level,
2956 const struct pipe_box *src_box)
2957 {
2958 struct r600_context *rctx = (struct r600_context *)ctx;
2959 struct r600_texture *rsrc = (struct r600_texture*)src;
2960 struct r600_texture *rdst = (struct r600_texture*)dst;
2961 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
2962 unsigned src_w, dst_w;
2963 unsigned src_x, src_y;
2964 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
2965
2966 if (rctx->b.dma.cs == NULL) {
2967 goto fallback;
2968 }
2969
2970 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
2971 if (dst_x % 4 || src_box->x % 4 || src_box->width % 4)
2972 goto fallback;
2973
2974 r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
2975 return;
2976 }
2977
2978 if (src->format != dst->format || src_box->depth > 1) {
2979 goto fallback;
2980 }
2981
2982 src_x = util_format_get_nblocksx(src->format, src_box->x);
2983 dst_x = util_format_get_nblocksx(src->format, dst_x);
2984 src_y = util_format_get_nblocksy(src->format, src_box->y);
2985 dst_y = util_format_get_nblocksy(src->format, dst_y);
2986
2987 bpp = rdst->surface.bpe;
2988 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
2989 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
2990 src_w = rsrc->surface.level[src_level].npix_x;
2991 dst_w = rdst->surface.level[dst_level].npix_x;
2992 copy_height = src_box->height / rsrc->surface.blk_h;
2993
2994 dst_mode = rdst->surface.level[dst_level].mode;
2995 src_mode = rsrc->surface.level[src_level].mode;
2996 /* downcast linear aligned to linear to simplify test */
2997 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
2998 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
2999
3000 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3001 /* strict requirement on r6xx/r7xx */
3002 goto fallback;
3003 }
3004 /* lot of constraint on alignment this should capture them all */
3005 if (src_pitch % 8 || src_box->y % 8 || dst_y % 8) {
3006 goto fallback;
3007 }
3008
3009 if (src_mode == dst_mode) {
3010 uint64_t dst_offset, src_offset, size;
3011
3012 /* simple dma blit would do NOTE code here assume :
3013 * src_box.x/y == 0
3014 * dst_x/y == 0
3015 * dst_pitch == src_pitch
3016 */
3017 src_offset= rsrc->surface.level[src_level].offset;
3018 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3019 src_offset += src_y * src_pitch + src_x * bpp;
3020 dst_offset = rdst->surface.level[dst_level].offset;
3021 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3022 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3023 size = src_box->height * src_pitch;
3024 /* must be dw aligned */
3025 if (dst_offset % 4 || src_offset % 4 || size % 4) {
3026 goto fallback;
3027 }
3028 r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size);
3029 } else {
3030 if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3031 src, src_level, src_x, src_y, src_box->z,
3032 copy_height, dst_pitch, bpp)) {
3033 goto fallback;
3034 }
3035 }
3036 return;
3037
3038 fallback:
3039 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3040 src, src_level, src_box);
3041 }
3042
3043 void r600_init_state_functions(struct r600_context *rctx)
3044 {
3045 unsigned id = 1;
3046 unsigned i;
3047 /* !!!
3048 * To avoid GPU lockup registers must be emited in a specific order
3049 * (no kidding ...). The order below is important and have been
3050 * partialy infered from analyzing fglrx command stream.
3051 *
3052 * Don't reorder atom without carefully checking the effect (GPU lockup
3053 * or piglit regression).
3054 * !!!
3055 */
3056
3057 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
3058
3059 /* shader const */
3060 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
3061 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
3062 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
3063
3064 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3065 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
3066 */
3067 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
3068 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
3069 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
3070 /* resource */
3071 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
3072 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
3073 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
3074 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
3075
3076 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3077
3078 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3079 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3080 rctx->sample_mask.sample_mask = ~0;
3081
3082 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3083 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3084 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3085 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3086 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3087 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3088 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3089 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3090 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3091 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
3092 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3093 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
3094 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
3095 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3096 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3097 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3098 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3099 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3100 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3101 for (i = 0; i < R600_NUM_HW_STAGES; i++)
3102 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3103 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0);
3104 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0);
3105
3106 rctx->b.b.create_blend_state = r600_create_blend_state;
3107 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3108 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3109 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3110 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3111 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3112 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3113 rctx->b.b.set_min_samples = r600_set_min_samples;
3114 rctx->b.b.get_sample_position = r600_get_sample_position;
3115 rctx->b.dma_copy = r600_dma_copy;
3116 }
3117 /* this function must be last */