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r600g: use HTILE allocator from SI
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
145 {
146 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
147 }
148
149 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
150 {
151 return r600_translate_colorformat(chip, format) != ~0U &&
152 r600_translate_colorswap(format) != ~0U;
153 }
154
155 static bool r600_is_zs_format_supported(enum pipe_format format)
156 {
157 return r600_translate_dbformat(format) != ~0U;
158 }
159
160 boolean r600_is_format_supported(struct pipe_screen *screen,
161 enum pipe_format format,
162 enum pipe_texture_target target,
163 unsigned sample_count,
164 unsigned usage)
165 {
166 struct r600_screen *rscreen = (struct r600_screen*)screen;
167 unsigned retval = 0;
168
169 if (target >= PIPE_MAX_TEXTURE_TYPES) {
170 R600_ERR("r600: unsupported texture type %d\n", target);
171 return FALSE;
172 }
173
174 if (!util_format_is_supported(format, usage))
175 return FALSE;
176
177 if (sample_count > 1) {
178 if (!rscreen->has_msaa)
179 return FALSE;
180
181 /* R11G11B10 is broken on R6xx. */
182 if (rscreen->b.chip_class == R600 &&
183 format == PIPE_FORMAT_R11G11B10_FLOAT)
184 return FALSE;
185
186 /* MSAA integer colorbuffers hang. */
187 if (util_format_is_pure_integer(format) &&
188 !util_format_is_depth_or_stencil(format))
189 return FALSE;
190
191 switch (sample_count) {
192 case 2:
193 case 4:
194 case 8:
195 break;
196 default:
197 return FALSE;
198 }
199 }
200
201 if (usage & PIPE_BIND_SAMPLER_VIEW) {
202 if (target == PIPE_BUFFER) {
203 if (r600_is_vertex_format_supported(format))
204 retval |= PIPE_BIND_SAMPLER_VIEW;
205 } else {
206 if (r600_is_sampler_format_supported(screen, format))
207 retval |= PIPE_BIND_SAMPLER_VIEW;
208 }
209 }
210
211 if ((usage & (PIPE_BIND_RENDER_TARGET |
212 PIPE_BIND_DISPLAY_TARGET |
213 PIPE_BIND_SCANOUT |
214 PIPE_BIND_SHARED |
215 PIPE_BIND_BLENDABLE)) &&
216 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
217 retval |= usage &
218 (PIPE_BIND_RENDER_TARGET |
219 PIPE_BIND_DISPLAY_TARGET |
220 PIPE_BIND_SCANOUT |
221 PIPE_BIND_SHARED);
222 if (!util_format_is_pure_integer(format) &&
223 !util_format_is_depth_or_stencil(format))
224 retval |= usage & PIPE_BIND_BLENDABLE;
225 }
226
227 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
228 r600_is_zs_format_supported(format)) {
229 retval |= PIPE_BIND_DEPTH_STENCIL;
230 }
231
232 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
233 r600_is_vertex_format_supported(format)) {
234 retval |= PIPE_BIND_VERTEX_BUFFER;
235 }
236
237 if (usage & PIPE_BIND_TRANSFER_READ)
238 retval |= PIPE_BIND_TRANSFER_READ;
239 if (usage & PIPE_BIND_TRANSFER_WRITE)
240 retval |= PIPE_BIND_TRANSFER_WRITE;
241
242 return retval == usage;
243 }
244
245 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
246 {
247 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
248 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
249 float offset_units = state->offset_units;
250 float offset_scale = state->offset_scale;
251
252 switch (state->zs_format) {
253 case PIPE_FORMAT_Z24X8_UNORM:
254 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
255 offset_units *= 2.0f;
256 break;
257 case PIPE_FORMAT_Z16_UNORM:
258 offset_units *= 4.0f;
259 break;
260 default:;
261 }
262
263 r600_write_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
264 radeon_emit(cs, fui(offset_scale));
265 radeon_emit(cs, fui(offset_units));
266 radeon_emit(cs, fui(offset_scale));
267 radeon_emit(cs, fui(offset_units));
268 }
269
270 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
271 {
272 int j = state->independent_blend_enable ? i : 0;
273
274 unsigned eqRGB = state->rt[j].rgb_func;
275 unsigned srcRGB = state->rt[j].rgb_src_factor;
276 unsigned dstRGB = state->rt[j].rgb_dst_factor;
277
278 unsigned eqA = state->rt[j].alpha_func;
279 unsigned srcA = state->rt[j].alpha_src_factor;
280 unsigned dstA = state->rt[j].alpha_dst_factor;
281 uint32_t bc = 0;
282
283 if (!state->rt[j].blend_enable)
284 return 0;
285
286 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
287 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
288 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
289
290 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
291 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
292 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
293 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
294 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
295 }
296 return bc;
297 }
298
299 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
300 const struct pipe_blend_state *state,
301 int mode)
302 {
303 struct r600_context *rctx = (struct r600_context *)ctx;
304 uint32_t color_control = 0, target_mask = 0;
305 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
306
307 if (!blend) {
308 return NULL;
309 }
310
311 r600_init_command_buffer(&blend->buffer, 20);
312 r600_init_command_buffer(&blend->buffer_no_blend, 20);
313
314 /* R600 does not support per-MRT blends */
315 if (rctx->b.family > CHIP_R600)
316 color_control |= S_028808_PER_MRT_BLEND(1);
317
318 if (state->logicop_enable) {
319 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
320 } else {
321 color_control |= (0xcc << 16);
322 }
323 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
324 if (state->independent_blend_enable) {
325 for (int i = 0; i < 8; i++) {
326 if (state->rt[i].blend_enable) {
327 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
328 }
329 target_mask |= (state->rt[i].colormask << (4 * i));
330 }
331 } else {
332 for (int i = 0; i < 8; i++) {
333 if (state->rt[0].blend_enable) {
334 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
335 }
336 target_mask |= (state->rt[0].colormask << (4 * i));
337 }
338 }
339
340 if (target_mask)
341 color_control |= S_028808_SPECIAL_OP(mode);
342 else
343 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
344
345 /* only MRT0 has dual src blend */
346 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
347 blend->cb_target_mask = target_mask;
348 blend->cb_color_control = color_control;
349 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
350 blend->alpha_to_one = state->alpha_to_one;
351
352 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
353 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
354 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
355 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
356 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
357 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
358
359 /* Copy over the registers set so far into buffer_no_blend. */
360 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
361 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
362
363 /* Only add blend registers if blending is enabled. */
364 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
365 return blend;
366 }
367
368 /* The first R600 does not support per-MRT blends */
369 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
370 r600_get_blend_control(state, 0));
371
372 if (rctx->b.family > CHIP_R600) {
373 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
374 for (int i = 0; i < 8; i++) {
375 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
376 }
377 }
378 return blend;
379 }
380
381 static void *r600_create_blend_state(struct pipe_context *ctx,
382 const struct pipe_blend_state *state)
383 {
384 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
385 }
386
387 static void *r600_create_dsa_state(struct pipe_context *ctx,
388 const struct pipe_depth_stencil_alpha_state *state)
389 {
390 unsigned db_depth_control, alpha_test_control, alpha_ref;
391 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
392
393 if (dsa == NULL) {
394 return NULL;
395 }
396
397 r600_init_command_buffer(&dsa->buffer, 3);
398
399 dsa->valuemask[0] = state->stencil[0].valuemask;
400 dsa->valuemask[1] = state->stencil[1].valuemask;
401 dsa->writemask[0] = state->stencil[0].writemask;
402 dsa->writemask[1] = state->stencil[1].writemask;
403 dsa->zwritemask = state->depth.writemask;
404
405 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
406 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
407 S_028800_ZFUNC(state->depth.func);
408
409 /* stencil */
410 if (state->stencil[0].enabled) {
411 db_depth_control |= S_028800_STENCIL_ENABLE(1);
412 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
413 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
414 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
415 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
416
417 if (state->stencil[1].enabled) {
418 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
419 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
420 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
421 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
422 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
423 }
424 }
425
426 /* alpha */
427 alpha_test_control = 0;
428 alpha_ref = 0;
429 if (state->alpha.enabled) {
430 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
431 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
432 alpha_ref = fui(state->alpha.ref_value);
433 }
434 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
435 dsa->alpha_ref = alpha_ref;
436
437 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
438 return dsa;
439 }
440
441 static void *r600_create_rs_state(struct pipe_context *ctx,
442 const struct pipe_rasterizer_state *state)
443 {
444 struct r600_context *rctx = (struct r600_context *)ctx;
445 unsigned tmp, sc_mode_cntl, spi_interp;
446 float psize_min, psize_max;
447 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
448
449 if (rs == NULL) {
450 return NULL;
451 }
452
453 r600_init_command_buffer(&rs->buffer, 30);
454
455 rs->flatshade = state->flatshade;
456 rs->sprite_coord_enable = state->sprite_coord_enable;
457 rs->two_side = state->light_twoside;
458 rs->clip_plane_enable = state->clip_plane_enable;
459 rs->pa_sc_line_stipple = state->line_stipple_enable ?
460 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
461 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
462 rs->pa_cl_clip_cntl =
463 S_028810_PS_UCP_MODE(3) |
464 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
465 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
466 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
467 if (rctx->b.chip_class == R700) {
468 rs->pa_cl_clip_cntl |=
469 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
470 }
471 rs->multisample_enable = state->multisample;
472
473 /* offset */
474 rs->offset_units = state->offset_units;
475 rs->offset_scale = state->offset_scale * 12.0f;
476 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
477
478 if (state->point_size_per_vertex) {
479 psize_min = util_get_min_point_size(state);
480 psize_max = 8192;
481 } else {
482 /* Force the point size to be as if the vertex output was disabled. */
483 psize_min = state->point_size;
484 psize_max = state->point_size;
485 }
486
487 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
488 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
489 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
490 if (rctx->b.chip_class >= R700) {
491 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
492 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
493 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
494 } else {
495 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
496 rs->scissor_enable = state->scissor;
497 }
498
499 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
500 if (state->sprite_coord_enable) {
501 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
502 S_0286D4_PNT_SPRITE_OVRD_X(2) |
503 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
504 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
505 S_0286D4_PNT_SPRITE_OVRD_W(1);
506 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
507 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
508 }
509 }
510
511 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
512 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
513 tmp = r600_pack_float_12p4(state->point_size/2);
514 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
515 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
516 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
517 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
518 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
519 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
520 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
521
522 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
523 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
524 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
525 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
526 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
527 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
528
529 rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
530 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
531 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
532 S_028814_FACE(!state->front_ccw) |
533 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
534 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
535 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
536 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
537 state->fill_back != PIPE_POLYGON_MODE_FILL) |
538 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
539 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
540 if (rctx->b.chip_class == R700) {
541 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl);
542 }
543 if (rctx->b.chip_class == R600) {
544 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC,
545 S_028350_MULTIPASS(state->rasterizer_discard));
546 }
547 return rs;
548 }
549
550 static void *r600_create_sampler_state(struct pipe_context *ctx,
551 const struct pipe_sampler_state *state)
552 {
553 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
554 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
555
556 if (ss == NULL) {
557 return NULL;
558 }
559
560 ss->seamless_cube_map = state->seamless_cube_map;
561 ss->border_color_use = sampler_state_needs_border_color(state);
562
563 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
564 ss->tex_sampler_words[0] =
565 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
566 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
567 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
568 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
569 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
570 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
571 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
572 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
573 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
574 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
575 ss->tex_sampler_words[1] =
576 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
577 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
578 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
579 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
580 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
581
582 if (ss->border_color_use) {
583 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
584 }
585 return ss;
586 }
587
588 static struct pipe_sampler_view *
589 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
590 unsigned width0, unsigned height0)
591
592 {
593 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
594 int stride = util_format_get_blocksize(view->base.format);
595 unsigned format, num_format, format_comp, endian;
596 uint64_t offset = view->base.u.buf.first_element * stride;
597 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
598
599 r600_vertex_data_type(view->base.format,
600 &format, &num_format, &format_comp,
601 &endian);
602
603 view->tex_resource = &tmp->resource;
604 view->skip_mip_address_reloc = true;
605
606 view->tex_resource_words[0] = offset;
607 view->tex_resource_words[1] = size - 1;
608 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(offset >> 32UL) |
609 S_038008_STRIDE(stride) |
610 S_038008_DATA_FORMAT(format) |
611 S_038008_NUM_FORMAT_ALL(num_format) |
612 S_038008_FORMAT_COMP_ALL(format_comp) |
613 S_038008_ENDIAN_SWAP(endian);
614 view->tex_resource_words[3] = 0;
615 /*
616 * in theory dword 4 is for number of elements, for use with resinfo,
617 * but it seems to utterly fail to work, the amd gpu shader analyser
618 * uses a const buffer to store the element sizes for buffer txq
619 */
620 view->tex_resource_words[4] = 0;
621 view->tex_resource_words[5] = 0;
622 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
623 return &view->base;
624 }
625
626 struct pipe_sampler_view *
627 r600_create_sampler_view_custom(struct pipe_context *ctx,
628 struct pipe_resource *texture,
629 const struct pipe_sampler_view *state,
630 unsigned width_first_level, unsigned height_first_level)
631 {
632 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
633 struct r600_texture *tmp = (struct r600_texture*)texture;
634 unsigned format, endian;
635 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
636 unsigned char swizzle[4], array_mode = 0;
637 unsigned width, height, depth, offset_level, last_level;
638
639 if (view == NULL)
640 return NULL;
641
642 /* initialize base object */
643 view->base = *state;
644 view->base.texture = NULL;
645 pipe_reference(NULL, &texture->reference);
646 view->base.texture = texture;
647 view->base.reference.count = 1;
648 view->base.context = ctx;
649
650 if (texture->target == PIPE_BUFFER)
651 return texture_buffer_sampler_view(view, texture->width0, 1);
652
653 swizzle[0] = state->swizzle_r;
654 swizzle[1] = state->swizzle_g;
655 swizzle[2] = state->swizzle_b;
656 swizzle[3] = state->swizzle_a;
657
658 format = r600_translate_texformat(ctx->screen, state->format,
659 swizzle,
660 &word4, &yuv_format);
661 assert(format != ~0);
662 if (format == ~0) {
663 FREE(view);
664 return NULL;
665 }
666
667 if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) {
668 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
669 FREE(view);
670 return NULL;
671 }
672 tmp = tmp->flushed_depth_texture;
673 }
674
675 endian = r600_colorformat_endian_swap(format);
676
677 offset_level = state->u.tex.first_level;
678 last_level = state->u.tex.last_level - offset_level;
679 width = width_first_level;
680 height = height_first_level;
681 depth = u_minify(texture->depth0, offset_level);
682 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
683
684 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
685 height = 1;
686 depth = texture->array_size;
687 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
688 depth = texture->array_size;
689 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
690 depth = texture->array_size / 6;
691 switch (tmp->surface.level[offset_level].mode) {
692 case RADEON_SURF_MODE_LINEAR_ALIGNED:
693 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
694 break;
695 case RADEON_SURF_MODE_1D:
696 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
697 break;
698 case RADEON_SURF_MODE_2D:
699 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
700 break;
701 case RADEON_SURF_MODE_LINEAR:
702 default:
703 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
704 break;
705 }
706
707 view->tex_resource = &tmp->resource;
708 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
709 S_038000_TILE_MODE(array_mode) |
710 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
711 S_038000_PITCH((pitch / 8) - 1) |
712 S_038000_TEX_WIDTH(width - 1));
713 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
714 S_038004_TEX_DEPTH(depth - 1) |
715 S_038004_DATA_FORMAT(format));
716 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
717 if (offset_level >= tmp->surface.last_level) {
718 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
719 } else {
720 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
721 }
722 view->tex_resource_words[4] = (word4 |
723 S_038010_REQUEST_SIZE(1) |
724 S_038010_ENDIAN_SWAP(endian) |
725 S_038010_BASE_LEVEL(0));
726 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
727 S_038014_LAST_ARRAY(state->u.tex.last_layer));
728 if (texture->nr_samples > 1) {
729 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
730 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
731 } else {
732 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
733 }
734 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
735 S_038018_MAX_ANISO(4 /* max 16 samples */));
736 return &view->base;
737 }
738
739 static struct pipe_sampler_view *
740 r600_create_sampler_view(struct pipe_context *ctx,
741 struct pipe_resource *tex,
742 const struct pipe_sampler_view *state)
743 {
744 return r600_create_sampler_view_custom(ctx, tex, state,
745 u_minify(tex->width0, state->u.tex.first_level),
746 u_minify(tex->height0, state->u.tex.first_level));
747 }
748
749 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
750 {
751 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
752 struct pipe_clip_state *state = &rctx->clip_state.state;
753
754 r600_write_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
755 radeon_emit_array(cs, (unsigned*)state, 6*4);
756 }
757
758 static void r600_set_polygon_stipple(struct pipe_context *ctx,
759 const struct pipe_poly_stipple *state)
760 {
761 }
762
763 static void r600_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
764 {
765 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
766 struct r600_scissor_state *rstate = (struct r600_scissor_state *)atom;
767 struct pipe_scissor_state *state = &rstate->scissor;
768 unsigned offset = rstate->idx * 4 * 2;
769
770 if (rctx->b.chip_class != R600 || rctx->scissor[0].enable) {
771 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + offset, 2);
772 radeon_emit(cs, S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) |
773 S_028240_WINDOW_OFFSET_DISABLE(1));
774 radeon_emit(cs, S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy));
775 } else {
776 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
777 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
778 S_028240_WINDOW_OFFSET_DISABLE(1));
779 radeon_emit(cs, S_028244_BR_X(8192) | S_028244_BR_Y(8192));
780 }
781 }
782
783 static void r600_set_scissor_states(struct pipe_context *ctx,
784 unsigned start_slot,
785 unsigned num_scissors,
786 const struct pipe_scissor_state *state)
787 {
788 struct r600_context *rctx = (struct r600_context *)ctx;
789 int i;
790
791 for (i = start_slot ; i < start_slot + num_scissors; i++) {
792 rctx->scissor[i].scissor = state[i - start_slot];
793 }
794
795 if (rctx->b.chip_class == R600 && !rctx->scissor[0].enable)
796 return;
797
798 for (i = start_slot ; i < start_slot + num_scissors; i++) {
799 rctx->scissor[i].atom.dirty = true;
800 }
801 }
802
803 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
804 unsigned size, unsigned alignment)
805 {
806 struct pipe_resource buffer;
807
808 memset(&buffer, 0, sizeof buffer);
809 buffer.target = PIPE_BUFFER;
810 buffer.format = PIPE_FORMAT_R8_UNORM;
811 buffer.bind = PIPE_BIND_CUSTOM;
812 buffer.usage = PIPE_USAGE_DEFAULT;
813 buffer.flags = 0;
814 buffer.width0 = size;
815 buffer.height0 = 1;
816 buffer.depth0 = 1;
817 buffer.array_size = 1;
818
819 return (struct r600_resource*)
820 r600_buffer_create(&rscreen->b.b, &buffer, alignment);
821 }
822
823 static void r600_init_color_surface(struct r600_context *rctx,
824 struct r600_surface *surf,
825 bool force_cmask_fmask)
826 {
827 struct r600_screen *rscreen = rctx->screen;
828 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
829 unsigned level = surf->base.u.tex.level;
830 unsigned pitch, slice;
831 unsigned color_info;
832 unsigned color_view;
833 unsigned format, swap, ntype, endian;
834 unsigned offset;
835 const struct util_format_description *desc;
836 int i;
837 bool blend_bypass = 0, blend_clamp = 1;
838
839 if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
840 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
841 rtex = rtex->flushed_depth_texture;
842 assert(rtex);
843 }
844
845 offset = rtex->surface.level[level].offset;
846 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
847 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
848 offset += rtex->surface.level[level].slice_size *
849 surf->base.u.tex.first_layer;
850 color_view = 0;
851 } else
852 color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
853 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
854
855 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
856 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
857 if (slice) {
858 slice = slice - 1;
859 }
860 color_info = 0;
861 switch (rtex->surface.level[level].mode) {
862 case RADEON_SURF_MODE_LINEAR_ALIGNED:
863 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
864 break;
865 case RADEON_SURF_MODE_1D:
866 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
867 break;
868 case RADEON_SURF_MODE_2D:
869 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
870 break;
871 case RADEON_SURF_MODE_LINEAR:
872 default:
873 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
874 break;
875 }
876
877 desc = util_format_description(surf->base.format);
878
879 for (i = 0; i < 4; i++) {
880 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
881 break;
882 }
883 }
884
885 ntype = V_0280A0_NUMBER_UNORM;
886 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
887 ntype = V_0280A0_NUMBER_SRGB;
888 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
889 if (desc->channel[i].normalized)
890 ntype = V_0280A0_NUMBER_SNORM;
891 else if (desc->channel[i].pure_integer)
892 ntype = V_0280A0_NUMBER_SINT;
893 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
894 if (desc->channel[i].normalized)
895 ntype = V_0280A0_NUMBER_UNORM;
896 else if (desc->channel[i].pure_integer)
897 ntype = V_0280A0_NUMBER_UINT;
898 }
899
900 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
901 assert(format != ~0);
902
903 swap = r600_translate_colorswap(surf->base.format);
904 assert(swap != ~0);
905
906 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
907 endian = ENDIAN_NONE;
908 } else {
909 endian = r600_colorformat_endian_swap(format);
910 }
911
912 /* set blend bypass according to docs if SINT/UINT or
913 8/24 COLOR variants */
914 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
915 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
916 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
917 blend_clamp = 0;
918 blend_bypass = 1;
919 }
920
921 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
922
923 color_info |= S_0280A0_FORMAT(format) |
924 S_0280A0_COMP_SWAP(swap) |
925 S_0280A0_BLEND_BYPASS(blend_bypass) |
926 S_0280A0_BLEND_CLAMP(blend_clamp) |
927 S_0280A0_NUMBER_TYPE(ntype) |
928 S_0280A0_ENDIAN(endian);
929
930 /* EXPORT_NORM is an optimzation that can be enabled for better
931 * performance in certain cases
932 */
933 if (rctx->b.chip_class == R600) {
934 /* EXPORT_NORM can be enabled if:
935 * - 11-bit or smaller UNORM/SNORM/SRGB
936 * - BLEND_CLAMP is enabled
937 * - BLEND_FLOAT32 is disabled
938 */
939 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
940 (desc->channel[i].size < 12 &&
941 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
942 ntype != V_0280A0_NUMBER_UINT &&
943 ntype != V_0280A0_NUMBER_SINT) &&
944 G_0280A0_BLEND_CLAMP(color_info) &&
945 !G_0280A0_BLEND_FLOAT32(color_info)) {
946 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
947 surf->export_16bpc = true;
948 }
949 } else {
950 /* EXPORT_NORM can be enabled if:
951 * - 11-bit or smaller UNORM/SNORM/SRGB
952 * - 16-bit or smaller FLOAT
953 */
954 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
955 ((desc->channel[i].size < 12 &&
956 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
957 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
958 (desc->channel[i].size < 17 &&
959 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
960 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
961 surf->export_16bpc = true;
962 }
963 }
964
965 /* These might not always be initialized to zero. */
966 surf->cb_color_base = offset >> 8;
967 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
968 S_028060_SLICE_TILE_MAX(slice);
969 surf->cb_color_fmask = surf->cb_color_base;
970 surf->cb_color_cmask = surf->cb_color_base;
971 surf->cb_color_mask = 0;
972
973 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
974 &rtex->resource.b.b);
975 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
976 &rtex->resource.b.b);
977
978 if (rtex->cmask.size) {
979 surf->cb_color_cmask = rtex->cmask.offset >> 8;
980 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
981
982 if (rtex->fmask.size) {
983 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
984 surf->cb_color_fmask = rtex->fmask.offset >> 8;
985 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
986 } else { /* cmask only */
987 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
988 }
989 } else if (force_cmask_fmask) {
990 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
991 *
992 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
993 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
994 * because it's not an MSAA buffer.
995 */
996 struct r600_cmask_info cmask;
997 struct r600_fmask_info fmask;
998
999 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
1000 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
1001
1002 /* CMASK. */
1003 if (!rctx->dummy_cmask ||
1004 rctx->dummy_cmask->buf->size < cmask.size ||
1005 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1006 struct pipe_transfer *transfer;
1007 void *ptr;
1008
1009 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1010 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1011
1012 /* Set the contents to 0xCC. */
1013 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1014 memset(ptr, 0xCC, cmask.size);
1015 pipe_buffer_unmap(&rctx->b.b, transfer);
1016 }
1017 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1018 &rctx->dummy_cmask->b.b);
1019
1020 /* FMASK. */
1021 if (!rctx->dummy_fmask ||
1022 rctx->dummy_fmask->buf->size < fmask.size ||
1023 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1024 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1025 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1026
1027 }
1028 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1029 &rctx->dummy_fmask->b.b);
1030
1031 /* Init the registers. */
1032 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1033 surf->cb_color_cmask = 0;
1034 surf->cb_color_fmask = 0;
1035 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1036 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1037 }
1038
1039 surf->cb_color_info = color_info;
1040 surf->cb_color_view = color_view;
1041 surf->color_initialized = true;
1042 }
1043
1044 static void r600_init_depth_surface(struct r600_context *rctx,
1045 struct r600_surface *surf)
1046 {
1047 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1048 unsigned level, pitch, slice, format, offset, array_mode;
1049
1050 level = surf->base.u.tex.level;
1051 offset = rtex->surface.level[level].offset;
1052 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1053 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1054 if (slice) {
1055 slice = slice - 1;
1056 }
1057 switch (rtex->surface.level[level].mode) {
1058 case RADEON_SURF_MODE_2D:
1059 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1060 break;
1061 case RADEON_SURF_MODE_1D:
1062 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1063 case RADEON_SURF_MODE_LINEAR:
1064 default:
1065 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1066 break;
1067 }
1068
1069 format = r600_translate_dbformat(surf->base.format);
1070 assert(format != ~0);
1071
1072 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1073 surf->db_depth_base = offset >> 8;
1074 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1075 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1076 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1077 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1078
1079 switch (surf->base.format) {
1080 case PIPE_FORMAT_Z24X8_UNORM:
1081 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1082 surf->pa_su_poly_offset_db_fmt_cntl =
1083 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1084 break;
1085 case PIPE_FORMAT_Z32_FLOAT:
1086 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1087 surf->pa_su_poly_offset_db_fmt_cntl =
1088 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1089 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1090 break;
1091 case PIPE_FORMAT_Z16_UNORM:
1092 surf->pa_su_poly_offset_db_fmt_cntl =
1093 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1094 break;
1095 default:;
1096 }
1097
1098 /* use htile only for first level */
1099 if (rtex->htile_buffer && !level) {
1100 surf->db_htile_data_base = 0;
1101 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1102 S_028D24_HTILE_HEIGHT(1) |
1103 S_028D24_FULL_CACHE(1);
1104 /* preload is not working properly on r6xx/r7xx */
1105 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1106 }
1107
1108 surf->depth_initialized = true;
1109 }
1110
1111 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1112 const struct pipe_framebuffer_state *state)
1113 {
1114 struct r600_context *rctx = (struct r600_context *)ctx;
1115 struct r600_surface *surf;
1116 struct r600_texture *rtex;
1117 unsigned i;
1118
1119 if (rctx->framebuffer.state.nr_cbufs) {
1120 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1121 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1122 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1123 }
1124 if (rctx->framebuffer.state.zsbuf) {
1125 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1126 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1127
1128 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1129 if (rctx->b.chip_class >= R700 && rtex->htile_buffer) {
1130 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1131 }
1132 }
1133
1134 /* Set the new state. */
1135 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1136
1137 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1138 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1139 util_format_is_pure_integer(state->cbufs[0]->format);
1140 rctx->framebuffer.compressed_cb_mask = 0;
1141 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1142 state->cbufs[0] && state->cbufs[1] &&
1143 state->cbufs[0]->texture->nr_samples > 1 &&
1144 state->cbufs[1]->texture->nr_samples <= 1;
1145 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1146
1147 /* Colorbuffers. */
1148 for (i = 0; i < state->nr_cbufs; i++) {
1149 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1150 bool force_cmask_fmask = rctx->b.chip_class == R600 &&
1151 rctx->framebuffer.is_msaa_resolve &&
1152 i == 1;
1153
1154 surf = (struct r600_surface*)state->cbufs[i];
1155 if (!surf)
1156 continue;
1157
1158 rtex = (struct r600_texture*)surf->base.texture;
1159 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1160
1161 if (!surf->color_initialized || force_cmask_fmask) {
1162 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1163 if (force_cmask_fmask) {
1164 /* re-initialize later without compression */
1165 surf->color_initialized = false;
1166 }
1167 }
1168
1169 if (!surf->export_16bpc) {
1170 rctx->framebuffer.export_16bpc = false;
1171 }
1172
1173 if (rtex->fmask.size && rtex->cmask.size) {
1174 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1175 }
1176 }
1177
1178 /* Update alpha-test state dependencies.
1179 * Alpha-test is done on the first colorbuffer only. */
1180 if (state->nr_cbufs) {
1181 bool alphatest_bypass = false;
1182
1183 surf = (struct r600_surface*)state->cbufs[0];
1184 if (surf) {
1185 alphatest_bypass = surf->alphatest_bypass;
1186 }
1187
1188 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1189 rctx->alphatest_state.bypass = alphatest_bypass;
1190 rctx->alphatest_state.atom.dirty = true;
1191 }
1192 }
1193
1194 /* ZS buffer. */
1195 if (state->zsbuf) {
1196 surf = (struct r600_surface*)state->zsbuf;
1197
1198 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1199
1200 if (!surf->depth_initialized) {
1201 r600_init_depth_surface(rctx, surf);
1202 }
1203
1204 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1205 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1206 rctx->poly_offset_state.atom.dirty = true;
1207 }
1208
1209 if (rctx->db_state.rsurf != surf) {
1210 rctx->db_state.rsurf = surf;
1211 rctx->db_state.atom.dirty = true;
1212 rctx->db_misc_state.atom.dirty = true;
1213 }
1214 } else if (rctx->db_state.rsurf) {
1215 rctx->db_state.rsurf = NULL;
1216 rctx->db_state.atom.dirty = true;
1217 rctx->db_misc_state.atom.dirty = true;
1218 }
1219
1220 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1221 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1222 rctx->cb_misc_state.atom.dirty = true;
1223 }
1224
1225 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1226 rctx->alphatest_state.bypass = false;
1227 rctx->alphatest_state.atom.dirty = true;
1228 }
1229
1230 /* Calculate the CS size. */
1231 rctx->framebuffer.atom.num_dw =
1232 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1233
1234 if (rctx->framebuffer.state.nr_cbufs) {
1235 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
1236 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
1237 }
1238 if (rctx->framebuffer.state.zsbuf) {
1239 rctx->framebuffer.atom.num_dw += 16;
1240 } else if (rctx->screen->b.info.drm_minor >= 18) {
1241 rctx->framebuffer.atom.num_dw += 3;
1242 }
1243 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1244 rctx->framebuffer.atom.num_dw += 2;
1245 }
1246
1247 rctx->framebuffer.atom.dirty = true;
1248 }
1249
1250 static uint32_t sample_locs_2x[] = {
1251 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1252 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1253 };
1254 static unsigned max_dist_2x = 4;
1255
1256 static uint32_t sample_locs_4x[] = {
1257 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1258 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1259 };
1260 static unsigned max_dist_4x = 6;
1261 static uint32_t sample_locs_8x[] = {
1262 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1263 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1264 };
1265 static unsigned max_dist_8x = 7;
1266
1267 static void r600_get_sample_position(struct pipe_context *ctx,
1268 unsigned sample_count,
1269 unsigned sample_index,
1270 float *out_value)
1271 {
1272 int offset, index;
1273 struct {
1274 int idx:4;
1275 } val;
1276 switch (sample_count) {
1277 case 1:
1278 default:
1279 out_value[0] = out_value[1] = 0.5;
1280 break;
1281 case 2:
1282 offset = 4 * (sample_index * 2);
1283 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1284 out_value[0] = (float)(val.idx + 8) / 16.0f;
1285 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1286 out_value[1] = (float)(val.idx + 8) / 16.0f;
1287 break;
1288 case 4:
1289 offset = 4 * (sample_index * 2);
1290 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1291 out_value[0] = (float)(val.idx + 8) / 16.0f;
1292 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1293 out_value[1] = (float)(val.idx + 8) / 16.0f;
1294 break;
1295 case 8:
1296 offset = 4 * (sample_index % 4 * 2);
1297 index = (sample_index / 4);
1298 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1299 out_value[0] = (float)(val.idx + 8) / 16.0f;
1300 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1301 out_value[1] = (float)(val.idx + 8) / 16.0f;
1302 break;
1303 }
1304 }
1305
1306 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1307 {
1308 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1309 unsigned max_dist = 0;
1310
1311 if (rctx->b.family == CHIP_R600) {
1312 switch (nr_samples) {
1313 default:
1314 nr_samples = 0;
1315 break;
1316 case 2:
1317 r600_write_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1318 max_dist = max_dist_2x;
1319 break;
1320 case 4:
1321 r600_write_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1322 max_dist = max_dist_4x;
1323 break;
1324 case 8:
1325 r600_write_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1326 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1327 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1328 max_dist = max_dist_8x;
1329 break;
1330 }
1331 } else {
1332 switch (nr_samples) {
1333 default:
1334 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1335 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1336 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1337 nr_samples = 0;
1338 break;
1339 case 2:
1340 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1341 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1342 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1343 max_dist = max_dist_2x;
1344 break;
1345 case 4:
1346 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1347 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1348 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1349 max_dist = max_dist_4x;
1350 break;
1351 case 8:
1352 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1353 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1354 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1355 max_dist = max_dist_8x;
1356 break;
1357 }
1358 }
1359
1360 if (nr_samples > 1) {
1361 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1362 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1363 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1364 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1365 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1366 } else {
1367 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1368 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1369 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1370 }
1371 }
1372
1373 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1374 {
1375 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1376 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1377 unsigned nr_cbufs = state->nr_cbufs;
1378 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1379 unsigned i, sbu = 0;
1380
1381 /* Colorbuffers. */
1382 r600_write_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1383 for (i = 0; i < nr_cbufs; i++) {
1384 radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0);
1385 }
1386 /* set CB_COLOR1_INFO for possible dual-src blending */
1387 if (i == 1 && cb[0]) {
1388 radeon_emit(cs, cb[0]->cb_color_info);
1389 i++;
1390 }
1391 for (; i < 8; i++) {
1392 radeon_emit(cs, 0);
1393 }
1394
1395 if (nr_cbufs) {
1396 for (i = 0; i < nr_cbufs; i++) {
1397 unsigned reloc;
1398
1399 if (!cb[i])
1400 continue;
1401
1402 /* COLOR_BASE */
1403 r600_write_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1404
1405 reloc = r600_context_bo_reloc(&rctx->b,
1406 &rctx->b.rings.gfx,
1407 (struct r600_resource*)cb[i]->base.texture,
1408 RADEON_USAGE_READWRITE,
1409 cb[i]->base.texture->nr_samples > 1 ?
1410 RADEON_PRIO_COLOR_BUFFER_MSAA :
1411 RADEON_PRIO_COLOR_BUFFER);
1412 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1413 radeon_emit(cs, reloc);
1414
1415 /* FMASK */
1416 r600_write_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1417
1418 reloc = r600_context_bo_reloc(&rctx->b,
1419 &rctx->b.rings.gfx,
1420 cb[i]->cb_buffer_fmask,
1421 RADEON_USAGE_READWRITE,
1422 cb[i]->base.texture->nr_samples > 1 ?
1423 RADEON_PRIO_COLOR_BUFFER_MSAA :
1424 RADEON_PRIO_COLOR_BUFFER);
1425 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1426 radeon_emit(cs, reloc);
1427
1428 /* CMASK */
1429 r600_write_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1430
1431 reloc = r600_context_bo_reloc(&rctx->b,
1432 &rctx->b.rings.gfx,
1433 cb[i]->cb_buffer_cmask,
1434 RADEON_USAGE_READWRITE,
1435 cb[i]->base.texture->nr_samples > 1 ?
1436 RADEON_PRIO_COLOR_BUFFER_MSAA :
1437 RADEON_PRIO_COLOR_BUFFER);
1438 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1439 radeon_emit(cs, reloc);
1440 }
1441
1442 r600_write_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1443 for (i = 0; i < nr_cbufs; i++) {
1444 radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0);
1445 }
1446
1447 r600_write_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1448 for (i = 0; i < nr_cbufs; i++) {
1449 radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0);
1450 }
1451
1452 r600_write_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1453 for (i = 0; i < nr_cbufs; i++) {
1454 radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0);
1455 }
1456
1457 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1458 }
1459
1460 /* SURFACE_BASE_UPDATE */
1461 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1462 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1463 radeon_emit(cs, sbu);
1464 sbu = 0;
1465 }
1466
1467 /* Zbuffer. */
1468 if (state->zsbuf) {
1469 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1470 unsigned reloc = r600_context_bo_reloc(&rctx->b,
1471 &rctx->b.rings.gfx,
1472 (struct r600_resource*)state->zsbuf->texture,
1473 RADEON_USAGE_READWRITE,
1474 surf->base.texture->nr_samples > 1 ?
1475 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1476 RADEON_PRIO_DEPTH_BUFFER);
1477
1478 r600_write_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1479 surf->pa_su_poly_offset_db_fmt_cntl);
1480
1481 r600_write_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1482 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1483 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1484 r600_write_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1485 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1486 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1487
1488 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1489 radeon_emit(cs, reloc);
1490
1491 r600_write_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1492
1493 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1494 } else if (rctx->screen->b.info.drm_minor >= 18) {
1495 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1496 * Older kernels are out of luck. */
1497 r600_write_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1498 }
1499
1500 /* SURFACE_BASE_UPDATE */
1501 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1502 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1503 radeon_emit(cs, sbu);
1504 sbu = 0;
1505 }
1506
1507 /* Framebuffer dimensions. */
1508 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1509 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1510 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1511 radeon_emit(cs, S_028244_BR_X(state->width) |
1512 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1513
1514 if (rctx->framebuffer.is_msaa_resolve) {
1515 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1516 } else {
1517 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1518 * will assure that the alpha-test will work even if there is
1519 * no colorbuffer bound. */
1520 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1521 (1ull << MAX2(nr_cbufs, 1)) - 1);
1522 }
1523
1524 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1525 }
1526
1527 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1528 {
1529 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1530 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1531
1532 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1533 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1534 if (rctx->b.chip_class == R600) {
1535 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1536 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1537 } else {
1538 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1539 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1540 }
1541 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1542 } else {
1543 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1544 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1545 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1546
1547 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1548 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1549 /* Always enable the first color output to make sure alpha-test works even without one. */
1550 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1551 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1552 a->cb_color_control |
1553 S_028808_MULTIWRITE_ENABLE(multiwrite));
1554 }
1555 }
1556
1557 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1558 {
1559 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1560 struct r600_db_state *a = (struct r600_db_state*)atom;
1561
1562 if (a->rsurf && a->rsurf->db_htile_surface) {
1563 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1564 unsigned reloc_idx;
1565
1566 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1567 r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1568 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1569 reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer,
1570 RADEON_USAGE_READWRITE, RADEON_PRIO_DEPTH_META);
1571 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1572 cs->buf[cs->cdw++] = reloc_idx;
1573 } else {
1574 r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1575 }
1576 }
1577
1578 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1579 {
1580 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1581 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1582 unsigned db_render_control = 0;
1583 unsigned db_render_override =
1584 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1585 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1586
1587 if (a->occlusion_query_enabled) {
1588 if (rctx->b.chip_class >= R700) {
1589 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1590 }
1591 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1592 }
1593 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
1594 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1595 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1596 /* This is to fix a lockup when hyperz and alpha test are enabled at
1597 * the same time somehow GPU get confuse on which order to pick for
1598 * z test
1599 */
1600 if (rctx->alphatest_state.sx_alpha_test_control) {
1601 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
1602 }
1603 } else {
1604 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1605 }
1606 if (a->flush_depthstencil_through_cb) {
1607 assert(a->copy_depth || a->copy_stencil);
1608
1609 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1610 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1611 S_028D0C_COPY_CENTROID(1) |
1612 S_028D0C_COPY_SAMPLE(a->copy_sample);
1613 } else if (a->flush_depthstencil_in_place) {
1614 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(1) |
1615 S_028D0C_STENCIL_COMPRESS_DISABLE(1);
1616 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1617 }
1618 if (a->htile_clear) {
1619 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1620 }
1621
1622 /* RV770 workaround for a hang with 8x MSAA. */
1623 if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) {
1624 db_render_override |= S_028D10_MAX_TILES_IN_DTT(6);
1625 }
1626
1627 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1628 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1629 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1630 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1631 }
1632
1633 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1634 {
1635 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1636 struct r600_config_state *a = (struct r600_config_state*)atom;
1637
1638 r600_write_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1639 r600_write_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
1640 }
1641
1642 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1643 {
1644 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1645 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1646
1647 while (dirty_mask) {
1648 struct pipe_vertex_buffer *vb;
1649 struct r600_resource *rbuffer;
1650 unsigned offset;
1651 unsigned buffer_index = u_bit_scan(&dirty_mask);
1652
1653 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1654 rbuffer = (struct r600_resource*)vb->buffer;
1655 assert(rbuffer);
1656
1657 offset = vb->buffer_offset;
1658
1659 /* fetch resources start at index 320 */
1660 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1661 radeon_emit(cs, (320 + buffer_index) * 7);
1662 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1663 radeon_emit(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1664 radeon_emit(cs, /* RESOURCEi_WORD2 */
1665 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1666 S_038008_STRIDE(vb->stride));
1667 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1668 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1669 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1670 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1671
1672 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1673 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1674 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1675 }
1676 }
1677
1678 static void r600_emit_constant_buffers(struct r600_context *rctx,
1679 struct r600_constbuf_state *state,
1680 unsigned buffer_id_base,
1681 unsigned reg_alu_constbuf_size,
1682 unsigned reg_alu_const_cache)
1683 {
1684 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1685 uint32_t dirty_mask = state->dirty_mask;
1686
1687 while (dirty_mask) {
1688 struct pipe_constant_buffer *cb;
1689 struct r600_resource *rbuffer;
1690 unsigned offset;
1691 unsigned buffer_index = ffs(dirty_mask) - 1;
1692 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1693 cb = &state->cb[buffer_index];
1694 rbuffer = (struct r600_resource*)cb->buffer;
1695 assert(rbuffer);
1696
1697 offset = cb->buffer_offset;
1698
1699 if (!gs_ring_buffer) {
1700 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1701 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1702 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1703 }
1704
1705 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1706 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1707 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1708
1709 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1710 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
1711 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1712 radeon_emit(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1713 radeon_emit(cs, /* RESOURCEi_WORD2 */
1714 S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1715 S_038008_STRIDE(gs_ring_buffer ? 4 : 16));
1716 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1717 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1718 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1719 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1720
1721 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1722 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1723 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1724
1725 dirty_mask &= ~(1 << buffer_index);
1726 }
1727 state->dirty_mask = 0;
1728 }
1729
1730 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1731 {
1732 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 160,
1733 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1734 R_028980_ALU_CONST_CACHE_VS_0);
1735 }
1736
1737 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1738 {
1739 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
1740 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1741 R_0289C0_ALU_CONST_CACHE_GS_0);
1742 }
1743
1744 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1745 {
1746 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
1747 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1748 R_028940_ALU_CONST_CACHE_PS_0);
1749 }
1750
1751 static void r600_emit_sampler_views(struct r600_context *rctx,
1752 struct r600_samplerview_state *state,
1753 unsigned resource_id_base)
1754 {
1755 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1756 uint32_t dirty_mask = state->dirty_mask;
1757
1758 while (dirty_mask) {
1759 struct r600_pipe_sampler_view *rview;
1760 unsigned resource_index = u_bit_scan(&dirty_mask);
1761 unsigned reloc;
1762
1763 rview = state->views[resource_index];
1764 assert(rview);
1765
1766 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1767 radeon_emit(cs, (resource_id_base + resource_index) * 7);
1768 radeon_emit_array(cs, rview->tex_resource_words, 7);
1769
1770 reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->tex_resource,
1771 RADEON_USAGE_READ,
1772 rview->tex_resource->b.b.nr_samples > 1 ?
1773 RADEON_PRIO_SHADER_TEXTURE_MSAA :
1774 RADEON_PRIO_SHADER_TEXTURE_RO);
1775 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1776 radeon_emit(cs, reloc);
1777 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1778 radeon_emit(cs, reloc);
1779 }
1780 state->dirty_mask = 0;
1781 }
1782
1783 /* Resource IDs:
1784 * PS: 0 .. +160
1785 * VS: 160 .. +160
1786 * FS: 320 .. +16
1787 * GS: 336 .. +160
1788 */
1789
1790 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1791 {
1792 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 160 + R600_MAX_CONST_BUFFERS);
1793 }
1794
1795 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1796 {
1797 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
1798 }
1799
1800 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1801 {
1802 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
1803 }
1804
1805 static void r600_emit_sampler_states(struct r600_context *rctx,
1806 struct r600_textures_info *texinfo,
1807 unsigned resource_id_base,
1808 unsigned border_color_reg)
1809 {
1810 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1811 uint32_t dirty_mask = texinfo->states.dirty_mask;
1812
1813 while (dirty_mask) {
1814 struct r600_pipe_sampler_state *rstate;
1815 struct r600_pipe_sampler_view *rview;
1816 unsigned i = u_bit_scan(&dirty_mask);
1817
1818 rstate = texinfo->states.states[i];
1819 assert(rstate);
1820 rview = texinfo->views.views[i];
1821
1822 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1823 * filtering between layers.
1824 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1825 */
1826 if (rview) {
1827 enum pipe_texture_target target = rview->base.texture->target;
1828 if (target == PIPE_TEXTURE_1D_ARRAY ||
1829 target == PIPE_TEXTURE_2D_ARRAY) {
1830 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1831 texinfo->is_array_sampler[i] = true;
1832 } else {
1833 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1834 texinfo->is_array_sampler[i] = false;
1835 }
1836 }
1837
1838 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1839 radeon_emit(cs, (resource_id_base + i) * 3);
1840 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
1841
1842 if (rstate->border_color_use) {
1843 unsigned offset;
1844
1845 offset = border_color_reg;
1846 offset += i * 16;
1847 r600_write_config_reg_seq(cs, offset, 4);
1848 radeon_emit_array(cs, rstate->border_color.ui, 4);
1849 }
1850 }
1851 texinfo->states.dirty_mask = 0;
1852 }
1853
1854 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1855 {
1856 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1857 }
1858
1859 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1860 {
1861 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1862 }
1863
1864 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1865 {
1866 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1867 }
1868
1869 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1870 {
1871 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1872 unsigned tmp;
1873
1874 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1875 S_009508_SYNC_GRADIENT(1) |
1876 S_009508_SYNC_WALKER(1) |
1877 S_009508_SYNC_ALIGNER(1);
1878 if (!rctx->seamless_cube_map.enabled) {
1879 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1880 }
1881 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1882 }
1883
1884 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1885 {
1886 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1887 uint8_t mask = s->sample_mask;
1888
1889 r600_write_context_reg(rctx->b.rings.gfx.cs, R_028C48_PA_SC_AA_MASK,
1890 mask | (mask << 8) | (mask << 16) | (mask << 24));
1891 }
1892
1893 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
1894 {
1895 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1896 struct r600_cso_state *state = (struct r600_cso_state*)a;
1897 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
1898
1899 r600_write_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
1900 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1901 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->buffer,
1902 RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA));
1903 }
1904
1905 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
1906 {
1907 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1908 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
1909
1910 uint32_t v2 = 0, primid = 0;
1911
1912 if (state->geom_enable) {
1913 uint32_t cut_val;
1914
1915 if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 128)
1916 cut_val = V_028A40_GS_CUT_128;
1917 else if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 256)
1918 cut_val = V_028A40_GS_CUT_256;
1919 else if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 512)
1920 cut_val = V_028A40_GS_CUT_512;
1921 else
1922 cut_val = V_028A40_GS_CUT_1024;
1923
1924 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1925 S_028A40_CUT_MODE(cut_val);
1926
1927 if (rctx->gs_shader->current->shader.gs_prim_id_input)
1928 primid = 1;
1929 }
1930
1931 r600_write_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
1932 r600_write_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
1933 }
1934
1935 static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
1936 {
1937 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1938 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
1939 struct r600_resource *rbuffer;
1940
1941 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1942 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1943 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1944
1945 if (state->enable) {
1946 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
1947 r600_write_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
1948 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1949 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1950 RADEON_USAGE_READWRITE,
1951 RADEON_PRIO_SHADER_RESOURCE_RW));
1952 r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
1953 state->esgs_ring.buffer_size >> 8);
1954
1955 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
1956 r600_write_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
1957 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1958 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1959 RADEON_USAGE_READWRITE,
1960 RADEON_PRIO_SHADER_RESOURCE_RW));
1961 r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
1962 state->gsvs_ring.buffer_size >> 8);
1963 } else {
1964 r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
1965 r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
1966 }
1967
1968 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1969 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1970 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1971 }
1972
1973 /* Adjust GPR allocation on R6xx/R7xx */
1974 bool r600_adjust_gprs(struct r600_context *rctx)
1975 {
1976 unsigned num_ps_gprs = rctx->ps_shader->current->shader.bc.ngpr;
1977 unsigned num_vs_gprs, num_es_gprs, num_gs_gprs;
1978 unsigned new_num_ps_gprs = num_ps_gprs;
1979 unsigned new_num_vs_gprs, new_num_es_gprs, new_num_gs_gprs;
1980 unsigned cur_num_ps_gprs = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
1981 unsigned cur_num_vs_gprs = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
1982 unsigned cur_num_gs_gprs = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
1983 unsigned cur_num_es_gprs = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
1984 unsigned def_num_ps_gprs = rctx->default_ps_gprs;
1985 unsigned def_num_vs_gprs = rctx->default_vs_gprs;
1986 unsigned def_num_gs_gprs = 0;
1987 unsigned def_num_es_gprs = 0;
1988 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
1989 /* hardware will reserve twice num_clause_temp_gprs */
1990 unsigned max_gprs = def_num_gs_gprs + def_num_es_gprs + def_num_ps_gprs + def_num_vs_gprs + def_num_clause_temp_gprs * 2;
1991 unsigned tmp, tmp2;
1992
1993 if (rctx->gs_shader) {
1994 num_es_gprs = rctx->vs_shader->current->shader.bc.ngpr;
1995 num_gs_gprs = rctx->gs_shader->current->shader.bc.ngpr;
1996 num_vs_gprs = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
1997 } else {
1998 num_es_gprs = 0;
1999 num_gs_gprs = 0;
2000 num_vs_gprs = rctx->vs_shader->current->shader.bc.ngpr;
2001 }
2002 new_num_vs_gprs = num_vs_gprs;
2003 new_num_es_gprs = num_es_gprs;
2004 new_num_gs_gprs = num_gs_gprs;
2005
2006 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2007 if (new_num_ps_gprs > cur_num_ps_gprs || new_num_vs_gprs > cur_num_vs_gprs ||
2008 new_num_es_gprs > cur_num_es_gprs || new_num_gs_gprs > cur_num_gs_gprs) {
2009 /* try to use switch back to default */
2010 if (new_num_ps_gprs > def_num_ps_gprs || new_num_vs_gprs > def_num_vs_gprs ||
2011 new_num_gs_gprs > def_num_gs_gprs || new_num_es_gprs > def_num_es_gprs) {
2012 /* always privilege vs stage so that at worst we have the
2013 * pixel stage producing wrong output (not the vertex
2014 * stage) */
2015 new_num_ps_gprs = max_gprs - ((new_num_vs_gprs - new_num_es_gprs - new_num_gs_gprs) + def_num_clause_temp_gprs * 2);
2016 new_num_vs_gprs = num_vs_gprs;
2017 new_num_gs_gprs = num_gs_gprs;
2018 new_num_es_gprs = num_es_gprs;
2019 } else {
2020 new_num_ps_gprs = def_num_ps_gprs;
2021 new_num_vs_gprs = def_num_vs_gprs;
2022 new_num_es_gprs = def_num_es_gprs;
2023 new_num_gs_gprs = def_num_gs_gprs;
2024 }
2025 } else {
2026 return true;
2027 }
2028
2029 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2030 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2031 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2032 * it will lockup. So in this case just discard the draw command
2033 * and don't change the current gprs repartitions.
2034 */
2035 if (num_ps_gprs > new_num_ps_gprs || num_vs_gprs > new_num_vs_gprs ||
2036 num_gs_gprs > new_num_gs_gprs || num_es_gprs > new_num_es_gprs) {
2037 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2038 "for a combined maximum of %d\n",
2039 num_ps_gprs, num_vs_gprs, num_es_gprs, num_gs_gprs, max_gprs);
2040 return false;
2041 }
2042
2043 /* in some case we endup recomputing the current value */
2044 tmp = S_008C04_NUM_PS_GPRS(new_num_ps_gprs) |
2045 S_008C04_NUM_VS_GPRS(new_num_vs_gprs) |
2046 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2047
2048 tmp2 = S_008C08_NUM_ES_GPRS(new_num_es_gprs) |
2049 S_008C08_NUM_GS_GPRS(new_num_gs_gprs);
2050 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2051 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2052 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2;
2053 rctx->config_state.atom.dirty = true;
2054 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2055 }
2056 return true;
2057 }
2058
2059 void r600_init_atom_start_cs(struct r600_context *rctx)
2060 {
2061 int ps_prio;
2062 int vs_prio;
2063 int gs_prio;
2064 int es_prio;
2065 int num_ps_gprs;
2066 int num_vs_gprs;
2067 int num_gs_gprs;
2068 int num_es_gprs;
2069 int num_temp_gprs;
2070 int num_ps_threads;
2071 int num_vs_threads;
2072 int num_gs_threads;
2073 int num_es_threads;
2074 int num_ps_stack_entries;
2075 int num_vs_stack_entries;
2076 int num_gs_stack_entries;
2077 int num_es_stack_entries;
2078 enum radeon_family family;
2079 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2080 uint32_t tmp, i;
2081
2082 r600_init_command_buffer(cb, 256);
2083
2084 /* R6xx requires this packet at the start of each command buffer */
2085 if (rctx->b.chip_class == R600) {
2086 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2087 r600_store_value(cb, 0);
2088 }
2089 /* All asics require this one */
2090 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2091 r600_store_value(cb, 0x80000000);
2092 r600_store_value(cb, 0x80000000);
2093
2094 /* We're setting config registers here. */
2095 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2096 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2097
2098 family = rctx->b.family;
2099 ps_prio = 0;
2100 vs_prio = 1;
2101 gs_prio = 2;
2102 es_prio = 3;
2103 switch (family) {
2104 case CHIP_R600:
2105 num_ps_gprs = 192;
2106 num_vs_gprs = 56;
2107 num_temp_gprs = 4;
2108 num_gs_gprs = 0;
2109 num_es_gprs = 0;
2110 num_ps_threads = 136;
2111 num_vs_threads = 48;
2112 num_gs_threads = 4;
2113 num_es_threads = 4;
2114 num_ps_stack_entries = 128;
2115 num_vs_stack_entries = 128;
2116 num_gs_stack_entries = 0;
2117 num_es_stack_entries = 0;
2118 break;
2119 case CHIP_RV630:
2120 case CHIP_RV635:
2121 num_ps_gprs = 84;
2122 num_vs_gprs = 36;
2123 num_temp_gprs = 4;
2124 num_gs_gprs = 0;
2125 num_es_gprs = 0;
2126 num_ps_threads = 144;
2127 num_vs_threads = 40;
2128 num_gs_threads = 4;
2129 num_es_threads = 4;
2130 num_ps_stack_entries = 40;
2131 num_vs_stack_entries = 40;
2132 num_gs_stack_entries = 32;
2133 num_es_stack_entries = 16;
2134 break;
2135 case CHIP_RV610:
2136 case CHIP_RV620:
2137 case CHIP_RS780:
2138 case CHIP_RS880:
2139 default:
2140 num_ps_gprs = 84;
2141 num_vs_gprs = 36;
2142 num_temp_gprs = 4;
2143 num_gs_gprs = 0;
2144 num_es_gprs = 0;
2145 num_ps_threads = 136;
2146 num_vs_threads = 48;
2147 num_gs_threads = 4;
2148 num_es_threads = 4;
2149 num_ps_stack_entries = 40;
2150 num_vs_stack_entries = 40;
2151 num_gs_stack_entries = 32;
2152 num_es_stack_entries = 16;
2153 break;
2154 case CHIP_RV670:
2155 num_ps_gprs = 144;
2156 num_vs_gprs = 40;
2157 num_temp_gprs = 4;
2158 num_gs_gprs = 0;
2159 num_es_gprs = 0;
2160 num_ps_threads = 136;
2161 num_vs_threads = 48;
2162 num_gs_threads = 4;
2163 num_es_threads = 4;
2164 num_ps_stack_entries = 40;
2165 num_vs_stack_entries = 40;
2166 num_gs_stack_entries = 32;
2167 num_es_stack_entries = 16;
2168 break;
2169 case CHIP_RV770:
2170 num_ps_gprs = 130;
2171 num_vs_gprs = 56;
2172 num_temp_gprs = 4;
2173 num_gs_gprs = 31;
2174 num_es_gprs = 31;
2175 num_ps_threads = 180;
2176 num_vs_threads = 60;
2177 num_gs_threads = 4;
2178 num_es_threads = 4;
2179 num_ps_stack_entries = 128;
2180 num_vs_stack_entries = 128;
2181 num_gs_stack_entries = 128;
2182 num_es_stack_entries = 128;
2183 break;
2184 case CHIP_RV730:
2185 case CHIP_RV740:
2186 num_ps_gprs = 84;
2187 num_vs_gprs = 36;
2188 num_temp_gprs = 4;
2189 num_gs_gprs = 0;
2190 num_es_gprs = 0;
2191 num_ps_threads = 180;
2192 num_vs_threads = 60;
2193 num_gs_threads = 4;
2194 num_es_threads = 4;
2195 num_ps_stack_entries = 128;
2196 num_vs_stack_entries = 128;
2197 num_gs_stack_entries = 0;
2198 num_es_stack_entries = 0;
2199 break;
2200 case CHIP_RV710:
2201 num_ps_gprs = 192;
2202 num_vs_gprs = 56;
2203 num_temp_gprs = 4;
2204 num_gs_gprs = 0;
2205 num_es_gprs = 0;
2206 num_ps_threads = 136;
2207 num_vs_threads = 48;
2208 num_gs_threads = 4;
2209 num_es_threads = 4;
2210 num_ps_stack_entries = 128;
2211 num_vs_stack_entries = 128;
2212 num_gs_stack_entries = 0;
2213 num_es_stack_entries = 0;
2214 break;
2215 }
2216
2217 rctx->default_ps_gprs = num_ps_gprs;
2218 rctx->default_vs_gprs = num_vs_gprs;
2219 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2220
2221 /* SQ_CONFIG */
2222 tmp = 0;
2223 switch (family) {
2224 case CHIP_RV610:
2225 case CHIP_RV620:
2226 case CHIP_RS780:
2227 case CHIP_RS880:
2228 case CHIP_RV710:
2229 break;
2230 default:
2231 tmp |= S_008C00_VC_ENABLE(1);
2232 break;
2233 }
2234 tmp |= S_008C00_DX9_CONSTS(0);
2235 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2236 tmp |= S_008C00_PS_PRIO(ps_prio);
2237 tmp |= S_008C00_VS_PRIO(vs_prio);
2238 tmp |= S_008C00_GS_PRIO(gs_prio);
2239 tmp |= S_008C00_ES_PRIO(es_prio);
2240 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2241
2242 /* SQ_GPR_RESOURCE_MGMT_2 */
2243 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2244 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2245 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2246 r600_store_value(cb, tmp);
2247
2248 /* SQ_THREAD_RESOURCE_MGMT */
2249 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2250 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2251 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2252 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2253 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2254
2255 /* SQ_STACK_RESOURCE_MGMT_1 */
2256 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2257 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2258 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2259
2260 /* SQ_STACK_RESOURCE_MGMT_2 */
2261 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2262 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2263 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2264
2265 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2266
2267 if (rctx->b.chip_class >= R700) {
2268 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2269 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2270 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2271 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2272 } else {
2273 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2274 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2275 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2276 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2277 }
2278 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2279 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2280 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2281 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2282 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2283 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2284 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2285 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2286 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2287 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2288
2289 /* to avoid GPU doing any preloading of constant from random address */
2290 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2291 for (i = 0; i < 16; i++)
2292 r600_store_value(cb, 0);
2293
2294 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2295 for (i = 0; i < 16; i++)
2296 r600_store_value(cb, 0);
2297
2298 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2299 for (i = 0; i < 16; i++)
2300 r600_store_value(cb, 0);
2301
2302 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2303 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2304 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2305 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2306 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2307 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2308 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2309 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2310 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2311 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2312 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2313 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2314 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2315 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2316
2317 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2318 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2319 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2320
2321 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2322 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2323 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2324
2325 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2326
2327 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2328
2329 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2330
2331 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2332 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2333 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2334 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2335
2336 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2337 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2338 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2339 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2340
2341 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2342 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2343
2344 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2345 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2346 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2347 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2348 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2349
2350 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * 16);
2351 for (tmp = 0; tmp < 16; tmp++) {
2352 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2353 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2354 }
2355
2356 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2357 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2358
2359 if (rctx->b.chip_class >= R700) {
2360 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2361 }
2362
2363 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2364 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2365 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2366 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2367 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2368
2369 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2370 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2371 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2372
2373 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2374 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2375 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2376
2377 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5);
2378 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2379 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2380 r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2381 r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2382 r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2383
2384 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2385
2386 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2387 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2388 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2389
2390 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2391
2392 if (rctx->b.chip_class == R700)
2393 r600_store_context_reg(cb, R_028350_SX_MISC, 0);
2394 if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
2395 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2396
2397 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2398 if (rctx->screen->b.has_streamout) {
2399 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2400 }
2401
2402 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2403 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2404 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF);
2405 }
2406
2407 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2408 {
2409 struct r600_context *rctx = (struct r600_context *)ctx;
2410 struct r600_command_buffer *cb = &shader->command_buffer;
2411 struct r600_shader *rshader = &shader->shader;
2412 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2413 int pos_index = -1, face_index = -1;
2414 unsigned tmp, sid, ufi = 0;
2415 int need_linear = 0;
2416 unsigned z_export = 0, stencil_export = 0;
2417 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2418
2419 if (!cb->buf) {
2420 r600_init_command_buffer(cb, 64);
2421 } else {
2422 cb->num_dw = 0;
2423 }
2424
2425 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2426 for (i = 0; i < rshader->ninput; i++) {
2427 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2428 pos_index = i;
2429 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2430 face_index = i;
2431
2432 sid = rshader->input[i].spi_sid;
2433
2434 tmp = S_028644_SEMANTIC(sid);
2435
2436 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2437 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2438 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2439 rctx->rasterizer && rctx->rasterizer->flatshade))
2440 tmp |= S_028644_FLAT_SHADE(1);
2441
2442 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2443 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2444 tmp |= S_028644_PT_SPRITE_TEX(1);
2445 }
2446
2447 if (rshader->input[i].centroid)
2448 tmp |= S_028644_SEL_CENTROID(1);
2449
2450 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2451 need_linear = 1;
2452 tmp |= S_028644_SEL_LINEAR(1);
2453 }
2454
2455 r600_store_value(cb, tmp);
2456 }
2457
2458 db_shader_control = 0;
2459 for (i = 0; i < rshader->noutput; i++) {
2460 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2461 z_export = 1;
2462 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2463 stencil_export = 1;
2464 }
2465 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2466 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2467 if (rshader->uses_kill)
2468 db_shader_control |= S_02880C_KILL_ENABLE(1);
2469
2470 exports_ps = 0;
2471 for (i = 0; i < rshader->noutput; i++) {
2472 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2473 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2474 exports_ps |= 1;
2475 }
2476 }
2477 num_cout = rshader->nr_ps_color_exports;
2478 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2479 if (!exports_ps) {
2480 /* always at least export 1 component per pixel */
2481 exports_ps = 2;
2482 }
2483
2484 shader->nr_ps_color_outputs = num_cout;
2485
2486 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2487 S_0286CC_PERSP_GRADIENT_ENA(1)|
2488 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2489 spi_input_z = 0;
2490 if (pos_index != -1) {
2491 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2492 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2493 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2494 S_0286CC_BARYC_SAMPLE_CNTL(1));
2495 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2496 }
2497
2498 spi_ps_in_control_1 = 0;
2499 if (face_index != -1) {
2500 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2501 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2502 }
2503
2504 /* HW bug in original R600 */
2505 if (rctx->b.family == CHIP_R600)
2506 ufi = 1;
2507
2508 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2509 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2510 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2511
2512 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2513
2514 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2515 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2516 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2517 S_028850_STACK_SIZE(rshader->bc.nstack) |
2518 S_028850_UNCACHED_FIRST_INST(ufi));
2519 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2520
2521 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2522 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2523
2524 /* only set some bits here, the other bits are set in the dsa state */
2525 shader->db_shader_control = db_shader_control;
2526 shader->ps_depth_export = z_export | stencil_export;
2527
2528 shader->sprite_coord_enable = sprite_coord_enable;
2529 if (rctx->rasterizer)
2530 shader->flatshade = rctx->rasterizer->flatshade;
2531 }
2532
2533 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2534 {
2535 struct r600_command_buffer *cb = &shader->command_buffer;
2536 struct r600_shader *rshader = &shader->shader;
2537 unsigned spi_vs_out_id[10] = {};
2538 unsigned i, tmp, nparams = 0;
2539
2540 for (i = 0; i < rshader->noutput; i++) {
2541 if (rshader->output[i].spi_sid) {
2542 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2543 spi_vs_out_id[nparams / 4] |= tmp;
2544 nparams++;
2545 }
2546 }
2547
2548 r600_init_command_buffer(cb, 32);
2549
2550 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2551 for (i = 0; i < 10; i++) {
2552 r600_store_value(cb, spi_vs_out_id[i]);
2553 }
2554
2555 /* Certain attributes (position, psize, etc.) don't count as params.
2556 * VS is required to export at least one param and r600_shader_from_tgsi()
2557 * takes care of adding a dummy export.
2558 */
2559 if (nparams < 1)
2560 nparams = 1;
2561
2562 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2563 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2564 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2565 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2566 S_028868_STACK_SIZE(rshader->bc.nstack));
2567 if (rshader->vs_position_window_space) {
2568 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2569 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
2570 } else {
2571 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2572 S_028818_VTX_W0_FMT(1) |
2573 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2574 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2575 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2576
2577 }
2578 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2579 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2580
2581 shader->pa_cl_vs_out_cntl =
2582 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2583 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2584 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2585 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
2586 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
2587 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) |
2588 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport);
2589 }
2590
2591 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2592 {
2593 struct r600_context *rctx = (struct r600_context *)ctx;
2594 struct r600_command_buffer *cb = &shader->command_buffer;
2595 struct r600_shader *rshader = &shader->shader;
2596 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
2597 unsigned gsvs_itemsize =
2598 (cp_shader->ring_item_size * rshader->gs_max_out_vertices) >> 2;
2599
2600 r600_init_command_buffer(cb, 64);
2601
2602 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2603 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
2604
2605 if (rctx->b.chip_class >= R700) {
2606 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
2607 S_028B38_MAX_VERT_OUT(rshader->gs_max_out_vertices));
2608 }
2609 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
2610 r600_conv_prim_to_gs_out(rshader->gs_output_prim));
2611
2612 r600_store_context_reg_seq(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE, 4);
2613 r600_store_value(cb, cp_shader->ring_item_size >> 2);
2614 r600_store_value(cb, 0);
2615 r600_store_value(cb, 0);
2616 r600_store_value(cb, 0);
2617
2618 r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
2619 (rshader->ring_item_size) >> 2);
2620
2621 r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE,
2622 gsvs_itemsize);
2623
2624 /* FIXME calculate these values somehow ??? */
2625 r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2);
2626 r600_store_value(cb, 0x80); /* GS_PER_ES */
2627 r600_store_value(cb, 0x100); /* ES_PER_GS */
2628 r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1);
2629 r600_store_value(cb, 0x2); /* GS_PER_VS */
2630
2631 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS,
2632 S_02887C_NUM_GPRS(rshader->bc.ngpr) |
2633 S_02887C_STACK_SIZE(rshader->bc.nstack));
2634 r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, 0);
2635 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2636 }
2637
2638 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2639 {
2640 struct r600_command_buffer *cb = &shader->command_buffer;
2641 struct r600_shader *rshader = &shader->shader;
2642
2643 r600_init_command_buffer(cb, 32);
2644
2645 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
2646 S_028890_NUM_GPRS(rshader->bc.ngpr) |
2647 S_028890_STACK_SIZE(rshader->bc.nstack));
2648 r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, 0);
2649 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2650 }
2651
2652
2653 void *r600_create_resolve_blend(struct r600_context *rctx)
2654 {
2655 struct pipe_blend_state blend;
2656 unsigned i;
2657
2658 memset(&blend, 0, sizeof(blend));
2659 blend.independent_blend_enable = true;
2660 for (i = 0; i < 2; i++) {
2661 blend.rt[i].colormask = 0xf;
2662 blend.rt[i].blend_enable = 1;
2663 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2664 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2665 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2666 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2667 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2668 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2669 }
2670 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2671 }
2672
2673 void *r700_create_resolve_blend(struct r600_context *rctx)
2674 {
2675 struct pipe_blend_state blend;
2676
2677 memset(&blend, 0, sizeof(blend));
2678 blend.independent_blend_enable = true;
2679 blend.rt[0].colormask = 0xf;
2680 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2681 }
2682
2683 void *r600_create_decompress_blend(struct r600_context *rctx)
2684 {
2685 struct pipe_blend_state blend;
2686
2687 memset(&blend, 0, sizeof(blend));
2688 blend.independent_blend_enable = true;
2689 blend.rt[0].colormask = 0xf;
2690 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2691 }
2692
2693 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2694 {
2695 struct pipe_depth_stencil_alpha_state dsa;
2696 boolean quirk = false;
2697
2698 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2699 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2700 quirk = true;
2701
2702 memset(&dsa, 0, sizeof(dsa));
2703
2704 if (quirk) {
2705 dsa.depth.enabled = 1;
2706 dsa.depth.func = PIPE_FUNC_LEQUAL;
2707 dsa.stencil[0].enabled = 1;
2708 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2709 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2710 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2711 dsa.stencil[0].writemask = 0xff;
2712 }
2713
2714 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2715 }
2716
2717 void r600_update_db_shader_control(struct r600_context * rctx)
2718 {
2719 bool dual_export;
2720 unsigned db_shader_control;
2721
2722 if (!rctx->ps_shader) {
2723 return;
2724 }
2725
2726 dual_export = rctx->framebuffer.export_16bpc &&
2727 !rctx->ps_shader->current->ps_depth_export;
2728
2729 db_shader_control = rctx->ps_shader->current->db_shader_control |
2730 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2731
2732 /* When alpha test is enabled we can't trust the hw to make the proper
2733 * decision on the order in which ztest should be run related to fragment
2734 * shader execution.
2735 *
2736 * If alpha test is enabled perform z test after fragment. RE_Z (early
2737 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2738 */
2739 if (rctx->alphatest_state.sx_alpha_test_control) {
2740 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2741 } else {
2742 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2743 }
2744
2745 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
2746 rctx->db_misc_state.db_shader_control = db_shader_control;
2747 rctx->db_misc_state.atom.dirty = true;
2748 }
2749 }
2750
2751 static INLINE unsigned r600_array_mode(unsigned mode)
2752 {
2753 switch (mode) {
2754 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
2755 break;
2756 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
2757 break;
2758 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
2759 default:
2760 case RADEON_SURF_MODE_LINEAR: return V_0280A0_ARRAY_LINEAR_GENERAL;
2761 }
2762 }
2763
2764 static boolean r600_dma_copy_tile(struct r600_context *rctx,
2765 struct pipe_resource *dst,
2766 unsigned dst_level,
2767 unsigned dst_x,
2768 unsigned dst_y,
2769 unsigned dst_z,
2770 struct pipe_resource *src,
2771 unsigned src_level,
2772 unsigned src_x,
2773 unsigned src_y,
2774 unsigned src_z,
2775 unsigned copy_height,
2776 unsigned pitch,
2777 unsigned bpp)
2778 {
2779 struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs;
2780 struct r600_texture *rsrc = (struct r600_texture*)src;
2781 struct r600_texture *rdst = (struct r600_texture*)dst;
2782 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
2783 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
2784 uint64_t base, addr;
2785
2786 dst_mode = rdst->surface.level[dst_level].mode;
2787 src_mode = rsrc->surface.level[src_level].mode;
2788 /* downcast linear aligned to linear to simplify test */
2789 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
2790 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
2791 assert(dst_mode != src_mode);
2792
2793 y = 0;
2794 lbpp = util_logbase2(bpp);
2795 pitch_tile_max = ((pitch / bpp) / 8) - 1;
2796
2797 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
2798 /* T2L */
2799 array_mode = r600_array_mode(src_mode);
2800 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
2801 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2802 /* linear height must be the same as the slice tile max height, it's ok even
2803 * if the linear destination/source have smaller heigh as the size of the
2804 * dma packet will be using the copy_height which is always smaller or equal
2805 * to the linear height
2806 */
2807 height = rsrc->surface.level[src_level].npix_y;
2808 detile = 1;
2809 x = src_x;
2810 y = src_y;
2811 z = src_z;
2812 base = rsrc->surface.level[src_level].offset;
2813 addr = rdst->surface.level[dst_level].offset;
2814 addr += rdst->surface.level[dst_level].slice_size * dst_z;
2815 addr += dst_y * pitch + dst_x * bpp;
2816 } else {
2817 /* L2T */
2818 array_mode = r600_array_mode(dst_mode);
2819 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
2820 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2821 /* linear height must be the same as the slice tile max height, it's ok even
2822 * if the linear destination/source have smaller heigh as the size of the
2823 * dma packet will be using the copy_height which is always smaller or equal
2824 * to the linear height
2825 */
2826 height = rdst->surface.level[dst_level].npix_y;
2827 detile = 0;
2828 x = dst_x;
2829 y = dst_y;
2830 z = dst_z;
2831 base = rdst->surface.level[dst_level].offset;
2832 addr = rsrc->surface.level[src_level].offset;
2833 addr += rsrc->surface.level[src_level].slice_size * src_z;
2834 addr += src_y * pitch + src_x * bpp;
2835 }
2836 /* check that we are in dw/base alignment constraint */
2837 if (addr % 4 || base % 256) {
2838 return FALSE;
2839 }
2840
2841 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2842 * line in the blit. Compute max 8 line we can copy in the size limit
2843 */
2844 cheight = ((R600_DMA_COPY_MAX_SIZE_DW * 4) / pitch) & 0xfffffff8;
2845 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
2846 r600_need_dma_space(&rctx->b, ncopy * 7);
2847
2848 for (i = 0; i < ncopy; i++) {
2849 cheight = cheight > copy_height ? copy_height : cheight;
2850 size = (cheight * pitch) / 4;
2851 /* emit reloc before writting cs so that cs is always in consistent state */
2852 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rsrc->resource, RADEON_USAGE_READ,
2853 RADEON_PRIO_MIN);
2854 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rdst->resource, RADEON_USAGE_WRITE,
2855 RADEON_PRIO_MIN);
2856 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 1, 0, size);
2857 cs->buf[cs->cdw++] = base >> 8;
2858 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
2859 (lbpp << 24) | ((height - 1) << 10) |
2860 pitch_tile_max;
2861 cs->buf[cs->cdw++] = (slice_tile_max << 12) | (z << 0);
2862 cs->buf[cs->cdw++] = (x << 3) | (y << 17);
2863 cs->buf[cs->cdw++] = addr & 0xfffffffc;
2864 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
2865 copy_height -= cheight;
2866 addr += cheight * pitch;
2867 y += cheight;
2868 }
2869 return TRUE;
2870 }
2871
2872 static void r600_dma_copy(struct pipe_context *ctx,
2873 struct pipe_resource *dst,
2874 unsigned dst_level,
2875 unsigned dstx, unsigned dsty, unsigned dstz,
2876 struct pipe_resource *src,
2877 unsigned src_level,
2878 const struct pipe_box *src_box)
2879 {
2880 struct r600_context *rctx = (struct r600_context *)ctx;
2881 struct r600_texture *rsrc = (struct r600_texture*)src;
2882 struct r600_texture *rdst = (struct r600_texture*)dst;
2883 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
2884 unsigned src_w, dst_w;
2885 unsigned src_x, src_y;
2886 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
2887
2888 if (rctx->b.rings.dma.cs == NULL) {
2889 goto fallback;
2890 }
2891
2892 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
2893 if (dst_x % 4 || src_box->x % 4 || src_box->width % 4)
2894 goto fallback;
2895
2896 r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
2897 return;
2898 }
2899
2900 if (src->format != dst->format || src_box->depth > 1) {
2901 goto fallback;
2902 }
2903
2904 src_x = util_format_get_nblocksx(src->format, src_box->x);
2905 dst_x = util_format_get_nblocksx(src->format, dst_x);
2906 src_y = util_format_get_nblocksy(src->format, src_box->y);
2907 dst_y = util_format_get_nblocksy(src->format, dst_y);
2908
2909 bpp = rdst->surface.bpe;
2910 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
2911 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
2912 src_w = rsrc->surface.level[src_level].npix_x;
2913 dst_w = rdst->surface.level[dst_level].npix_x;
2914 copy_height = src_box->height / rsrc->surface.blk_h;
2915
2916 dst_mode = rdst->surface.level[dst_level].mode;
2917 src_mode = rsrc->surface.level[src_level].mode;
2918 /* downcast linear aligned to linear to simplify test */
2919 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
2920 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
2921
2922 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
2923 /* strict requirement on r6xx/r7xx */
2924 goto fallback;
2925 }
2926 /* lot of constraint on alignment this should capture them all */
2927 if (src_pitch % 8 || src_box->y % 8 || dst_y % 8) {
2928 goto fallback;
2929 }
2930
2931 if (src_mode == dst_mode) {
2932 uint64_t dst_offset, src_offset, size;
2933
2934 /* simple dma blit would do NOTE code here assume :
2935 * src_box.x/y == 0
2936 * dst_x/y == 0
2937 * dst_pitch == src_pitch
2938 */
2939 src_offset= rsrc->surface.level[src_level].offset;
2940 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
2941 src_offset += src_y * src_pitch + src_x * bpp;
2942 dst_offset = rdst->surface.level[dst_level].offset;
2943 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
2944 dst_offset += dst_y * dst_pitch + dst_x * bpp;
2945 size = src_box->height * src_pitch;
2946 /* must be dw aligned */
2947 if (dst_offset % 4 || src_offset % 4 || size % 4) {
2948 goto fallback;
2949 }
2950 r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size);
2951 } else {
2952 if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
2953 src, src_level, src_x, src_y, src_box->z,
2954 copy_height, dst_pitch, bpp)) {
2955 goto fallback;
2956 }
2957 }
2958 return;
2959
2960 fallback:
2961 ctx->resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
2962 src, src_level, src_box);
2963 }
2964
2965 void r600_init_state_functions(struct r600_context *rctx)
2966 {
2967 unsigned id = 4;
2968 int i;
2969
2970 /* !!!
2971 * To avoid GPU lockup registers must be emited in a specific order
2972 * (no kidding ...). The order below is important and have been
2973 * partialy infered from analyzing fglrx command stream.
2974 *
2975 * Don't reorder atom without carefully checking the effect (GPU lockup
2976 * or piglit regression).
2977 * !!!
2978 */
2979
2980 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
2981
2982 /* shader const */
2983 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
2984 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
2985 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
2986
2987 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2988 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
2989 */
2990 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
2991 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
2992 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
2993 /* resource */
2994 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
2995 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
2996 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
2997 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
2998
2999 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 7);
3000
3001 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3002 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3003 rctx->sample_mask.sample_mask = ~0;
3004
3005 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3006 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3007 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3008 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3009 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3010 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3011 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3012 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3013 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3014 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
3015 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3016 for (i = 0;i < 16; i++) {
3017 r600_init_atom(rctx, &rctx->scissor[i].atom, id++, r600_emit_scissor_state, 4);
3018 r600_init_atom(rctx, &rctx->viewport[i].atom, id++, r600_emit_viewport_state, 8);
3019 rctx->scissor[i].idx = i;
3020 rctx->viewport[i].idx = i;
3021 }
3022 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3023 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3024 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3025 rctx->atoms[id++] = &rctx->b.streamout.begin_atom;
3026 rctx->atoms[id++] = &rctx->b.streamout.enable_atom;
3027 r600_init_atom(rctx, &rctx->vertex_shader.atom, id++, r600_emit_shader, 23);
3028 r600_init_atom(rctx, &rctx->pixel_shader.atom, id++, r600_emit_shader, 0);
3029 r600_init_atom(rctx, &rctx->geometry_shader.atom, id++, r600_emit_shader, 0);
3030 r600_init_atom(rctx, &rctx->export_shader.atom, id++, r600_emit_shader, 0);
3031 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0);
3032 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0);
3033
3034 rctx->b.b.create_blend_state = r600_create_blend_state;
3035 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3036 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3037 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3038 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3039 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3040 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3041 rctx->b.b.set_scissor_states = r600_set_scissor_states;
3042 rctx->b.b.get_sample_position = r600_get_sample_position;
3043 rctx->b.dma_copy = r600_dma_copy;
3044 }
3045 /* this function must be last */