2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
24 #include "r600_shader.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
33 static uint32_t r600_translate_blend_function(int blend_func
)
37 return V_028804_COMB_DST_PLUS_SRC
;
38 case PIPE_BLEND_SUBTRACT
:
39 return V_028804_COMB_SRC_MINUS_DST
;
40 case PIPE_BLEND_REVERSE_SUBTRACT
:
41 return V_028804_COMB_DST_MINUS_SRC
;
43 return V_028804_COMB_MIN_DST_SRC
;
45 return V_028804_COMB_MAX_DST_SRC
;
47 R600_ERR("Unknown blend function %d\n", blend_func
);
54 static uint32_t r600_translate_blend_factor(int blend_fact
)
57 case PIPE_BLENDFACTOR_ONE
:
58 return V_028804_BLEND_ONE
;
59 case PIPE_BLENDFACTOR_SRC_COLOR
:
60 return V_028804_BLEND_SRC_COLOR
;
61 case PIPE_BLENDFACTOR_SRC_ALPHA
:
62 return V_028804_BLEND_SRC_ALPHA
;
63 case PIPE_BLENDFACTOR_DST_ALPHA
:
64 return V_028804_BLEND_DST_ALPHA
;
65 case PIPE_BLENDFACTOR_DST_COLOR
:
66 return V_028804_BLEND_DST_COLOR
;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE
;
69 case PIPE_BLENDFACTOR_CONST_COLOR
:
70 return V_028804_BLEND_CONST_COLOR
;
71 case PIPE_BLENDFACTOR_CONST_ALPHA
:
72 return V_028804_BLEND_CONST_ALPHA
;
73 case PIPE_BLENDFACTOR_ZERO
:
74 return V_028804_BLEND_ZERO
;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR
;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA
;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA
;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR
;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR
;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA
;
87 case PIPE_BLENDFACTOR_SRC1_COLOR
:
88 return V_028804_BLEND_SRC1_COLOR
;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
90 return V_028804_BLEND_SRC1_ALPHA
;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
92 return V_028804_BLEND_INV_SRC1_COLOR
;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
94 return V_028804_BLEND_INV_SRC1_ALPHA
;
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
103 static unsigned r600_tex_dim(unsigned dim
, unsigned nr_samples
)
107 case PIPE_TEXTURE_1D
:
108 return V_038000_SQ_TEX_DIM_1D
;
109 case PIPE_TEXTURE_1D_ARRAY
:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY
;
111 case PIPE_TEXTURE_2D
:
112 case PIPE_TEXTURE_RECT
:
113 return nr_samples
> 1 ? V_038000_SQ_TEX_DIM_2D_MSAA
:
114 V_038000_SQ_TEX_DIM_2D
;
115 case PIPE_TEXTURE_2D_ARRAY
:
116 return nr_samples
> 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
117 V_038000_SQ_TEX_DIM_2D_ARRAY
;
118 case PIPE_TEXTURE_3D
:
119 return V_038000_SQ_TEX_DIM_3D
;
120 case PIPE_TEXTURE_CUBE
:
121 case PIPE_TEXTURE_CUBE_ARRAY
:
122 return V_038000_SQ_TEX_DIM_CUBEMAP
;
126 static uint32_t r600_translate_dbformat(enum pipe_format format
)
129 case PIPE_FORMAT_Z16_UNORM
:
130 return V_028010_DEPTH_16
;
131 case PIPE_FORMAT_Z24X8_UNORM
:
132 return V_028010_DEPTH_X8_24
;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
134 return V_028010_DEPTH_8_24
;
135 case PIPE_FORMAT_Z32_FLOAT
:
136 return V_028010_DEPTH_32_FLOAT
;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
138 return V_028010_DEPTH_X24_8_32_FLOAT
;
144 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
146 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
) != ~0U;
149 static bool r600_is_colorbuffer_format_supported(enum chip_class chip
, enum pipe_format format
)
151 return r600_translate_colorformat(chip
, format
) != ~0U &&
152 r600_translate_colorswap(format
) != ~0U;
155 static bool r600_is_zs_format_supported(enum pipe_format format
)
157 return r600_translate_dbformat(format
) != ~0U;
160 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
161 enum pipe_format format
,
162 enum pipe_texture_target target
,
163 unsigned sample_count
,
166 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
169 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
170 R600_ERR("r600: unsupported texture type %d\n", target
);
174 if (!util_format_is_supported(format
, usage
))
177 if (sample_count
> 1) {
178 if (!rscreen
->has_msaa
)
181 /* R11G11B10 is broken on R6xx. */
182 if (rscreen
->b
.chip_class
== R600
&&
183 format
== PIPE_FORMAT_R11G11B10_FLOAT
)
186 /* MSAA integer colorbuffers hang. */
187 if (util_format_is_pure_integer(format
) &&
188 !util_format_is_depth_or_stencil(format
))
191 switch (sample_count
) {
201 if (usage
& PIPE_BIND_SAMPLER_VIEW
) {
202 if (target
== PIPE_BUFFER
) {
203 if (r600_is_vertex_format_supported(format
))
204 retval
|= PIPE_BIND_SAMPLER_VIEW
;
206 if (r600_is_sampler_format_supported(screen
, format
))
207 retval
|= PIPE_BIND_SAMPLER_VIEW
;
211 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
212 PIPE_BIND_DISPLAY_TARGET
|
215 PIPE_BIND_BLENDABLE
)) &&
216 r600_is_colorbuffer_format_supported(rscreen
->b
.chip_class
, format
)) {
218 (PIPE_BIND_RENDER_TARGET
|
219 PIPE_BIND_DISPLAY_TARGET
|
222 if (!util_format_is_pure_integer(format
) &&
223 !util_format_is_depth_or_stencil(format
))
224 retval
|= usage
& PIPE_BIND_BLENDABLE
;
227 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
228 r600_is_zs_format_supported(format
)) {
229 retval
|= PIPE_BIND_DEPTH_STENCIL
;
232 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
233 r600_is_vertex_format_supported(format
)) {
234 retval
|= PIPE_BIND_VERTEX_BUFFER
;
237 if (usage
& PIPE_BIND_TRANSFER_READ
)
238 retval
|= PIPE_BIND_TRANSFER_READ
;
239 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
240 retval
|= PIPE_BIND_TRANSFER_WRITE
;
242 return retval
== usage
;
245 static void r600_emit_polygon_offset(struct r600_context
*rctx
, struct r600_atom
*a
)
247 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
248 struct r600_poly_offset_state
*state
= (struct r600_poly_offset_state
*)a
;
249 float offset_units
= state
->offset_units
;
250 float offset_scale
= state
->offset_scale
;
252 switch (state
->zs_format
) {
253 case PIPE_FORMAT_Z24X8_UNORM
:
254 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
255 offset_units
*= 2.0f
;
257 case PIPE_FORMAT_Z16_UNORM
:
258 offset_units
*= 4.0f
;
263 r600_write_context_reg_seq(cs
, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE
, 4);
264 radeon_emit(cs
, fui(offset_scale
));
265 radeon_emit(cs
, fui(offset_units
));
266 radeon_emit(cs
, fui(offset_scale
));
267 radeon_emit(cs
, fui(offset_units
));
270 static uint32_t r600_get_blend_control(const struct pipe_blend_state
*state
, unsigned i
)
272 int j
= state
->independent_blend_enable
? i
: 0;
274 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
275 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
276 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
278 unsigned eqA
= state
->rt
[j
].alpha_func
;
279 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
280 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
283 if (!state
->rt
[j
].blend_enable
)
286 bc
|= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
287 bc
|= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
288 bc
|= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
290 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
291 bc
|= S_028804_SEPARATE_ALPHA_BLEND(1);
292 bc
|= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
293 bc
|= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
294 bc
|= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
299 static void *r600_create_blend_state_mode(struct pipe_context
*ctx
,
300 const struct pipe_blend_state
*state
,
303 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
304 uint32_t color_control
= 0, target_mask
= 0;
305 struct r600_blend_state
*blend
= CALLOC_STRUCT(r600_blend_state
);
311 r600_init_command_buffer(&blend
->buffer
, 20);
312 r600_init_command_buffer(&blend
->buffer_no_blend
, 20);
314 /* R600 does not support per-MRT blends */
315 if (rctx
->b
.family
> CHIP_R600
)
316 color_control
|= S_028808_PER_MRT_BLEND(1);
318 if (state
->logicop_enable
) {
319 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
321 color_control
|= (0xcc << 16);
323 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
324 if (state
->independent_blend_enable
) {
325 for (int i
= 0; i
< 8; i
++) {
326 if (state
->rt
[i
].blend_enable
) {
327 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
329 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
332 for (int i
= 0; i
< 8; i
++) {
333 if (state
->rt
[0].blend_enable
) {
334 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
336 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
341 color_control
|= S_028808_SPECIAL_OP(mode
);
343 color_control
|= S_028808_SPECIAL_OP(V_028808_DISABLE
);
345 /* only MRT0 has dual src blend */
346 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
347 blend
->cb_target_mask
= target_mask
;
348 blend
->cb_color_control
= color_control
;
349 blend
->cb_color_control_no_blend
= color_control
& C_028808_TARGET_BLEND_ENABLE
;
350 blend
->alpha_to_one
= state
->alpha_to_one
;
352 r600_store_context_reg(&blend
->buffer
, R_028D44_DB_ALPHA_TO_MASK
,
353 S_028D44_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
354 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
355 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
356 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
357 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
359 /* Copy over the registers set so far into buffer_no_blend. */
360 memcpy(blend
->buffer_no_blend
.buf
, blend
->buffer
.buf
, blend
->buffer
.num_dw
* 4);
361 blend
->buffer_no_blend
.num_dw
= blend
->buffer
.num_dw
;
363 /* Only add blend registers if blending is enabled. */
364 if (!G_028808_TARGET_BLEND_ENABLE(color_control
)) {
368 /* The first R600 does not support per-MRT blends */
369 r600_store_context_reg(&blend
->buffer
, R_028804_CB_BLEND_CONTROL
,
370 r600_get_blend_control(state
, 0));
372 if (rctx
->b
.family
> CHIP_R600
) {
373 r600_store_context_reg_seq(&blend
->buffer
, R_028780_CB_BLEND0_CONTROL
, 8);
374 for (int i
= 0; i
< 8; i
++) {
375 r600_store_value(&blend
->buffer
, r600_get_blend_control(state
, i
));
381 static void *r600_create_blend_state(struct pipe_context
*ctx
,
382 const struct pipe_blend_state
*state
)
384 return r600_create_blend_state_mode(ctx
, state
, V_028808_SPECIAL_NORMAL
);
387 static void *r600_create_dsa_state(struct pipe_context
*ctx
,
388 const struct pipe_depth_stencil_alpha_state
*state
)
390 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
391 struct r600_dsa_state
*dsa
= CALLOC_STRUCT(r600_dsa_state
);
397 r600_init_command_buffer(&dsa
->buffer
, 3);
399 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
400 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
401 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
402 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
403 dsa
->zwritemask
= state
->depth
.writemask
;
405 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
406 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
407 S_028800_ZFUNC(state
->depth
.func
);
410 if (state
->stencil
[0].enabled
) {
411 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
412 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
413 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
414 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
415 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
417 if (state
->stencil
[1].enabled
) {
418 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
419 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
420 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
421 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
422 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
427 alpha_test_control
= 0;
429 if (state
->alpha
.enabled
) {
430 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
431 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
432 alpha_ref
= fui(state
->alpha
.ref_value
);
434 dsa
->sx_alpha_test_control
= alpha_test_control
& 0xff;
435 dsa
->alpha_ref
= alpha_ref
;
437 r600_store_context_reg(&dsa
->buffer
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
441 static void *r600_create_rs_state(struct pipe_context
*ctx
,
442 const struct pipe_rasterizer_state
*state
)
444 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
445 unsigned tmp
, sc_mode_cntl
, spi_interp
;
446 float psize_min
, psize_max
;
447 struct r600_rasterizer_state
*rs
= CALLOC_STRUCT(r600_rasterizer_state
);
453 r600_init_command_buffer(&rs
->buffer
, 30);
455 rs
->flatshade
= state
->flatshade
;
456 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
457 rs
->two_side
= state
->light_twoside
;
458 rs
->clip_plane_enable
= state
->clip_plane_enable
;
459 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
460 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
461 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
462 rs
->pa_cl_clip_cntl
=
463 S_028810_PS_UCP_MODE(3) |
464 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
465 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
466 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
467 if (rctx
->b
.chip_class
== R700
) {
468 rs
->pa_cl_clip_cntl
|=
469 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
);
471 rs
->multisample_enable
= state
->multisample
;
474 rs
->offset_units
= state
->offset_units
;
475 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
476 rs
->offset_enable
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
478 if (state
->point_size_per_vertex
) {
479 psize_min
= util_get_min_point_size(state
);
482 /* Force the point size to be as if the vertex output was disabled. */
483 psize_min
= state
->point_size
;
484 psize_max
= state
->point_size
;
487 sc_mode_cntl
= S_028A4C_MSAA_ENABLE(state
->multisample
) |
488 S_028A4C_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
489 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
490 if (rctx
->b
.chip_class
>= R700
) {
491 sc_mode_cntl
|= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
492 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
493 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state
->scissor
);
495 sc_mode_cntl
|= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
496 rs
->scissor_enable
= state
->scissor
;
499 spi_interp
= S_0286D4_FLAT_SHADE_ENA(1);
500 if (state
->sprite_coord_enable
) {
501 spi_interp
|= S_0286D4_PNT_SPRITE_ENA(1) |
502 S_0286D4_PNT_SPRITE_OVRD_X(2) |
503 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
504 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
505 S_0286D4_PNT_SPRITE_OVRD_W(1);
506 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
507 spi_interp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
511 r600_store_context_reg_seq(&rs
->buffer
, R_028A00_PA_SU_POINT_SIZE
, 3);
512 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
513 tmp
= r600_pack_float_12p4(state
->point_size
/2);
514 r600_store_value(&rs
->buffer
, /* R_028A00_PA_SU_POINT_SIZE */
515 S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
516 r600_store_value(&rs
->buffer
, /* R_028A04_PA_SU_POINT_MINMAX */
517 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
518 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
519 r600_store_value(&rs
->buffer
, /* R_028A08_PA_SU_LINE_CNTL */
520 S_028A08_WIDTH(r600_pack_float_12p4(state
->line_width
/2)));
522 r600_store_context_reg(&rs
->buffer
, R_0286D4_SPI_INTERP_CONTROL_0
, spi_interp
);
523 r600_store_context_reg(&rs
->buffer
, R_028A4C_PA_SC_MODE_CNTL
, sc_mode_cntl
);
524 r600_store_context_reg(&rs
->buffer
, R_028C08_PA_SU_VTX_CNTL
,
525 S_028C08_PIX_CENTER_HALF(state
->half_pixel_center
) |
526 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
527 r600_store_context_reg(&rs
->buffer
, R_028DFC_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
529 rs
->pa_su_sc_mode_cntl
= S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
530 S_028814_CULL_FRONT(state
->cull_face
& PIPE_FACE_FRONT
? 1 : 0) |
531 S_028814_CULL_BACK(state
->cull_face
& PIPE_FACE_BACK
? 1 : 0) |
532 S_028814_FACE(!state
->front_ccw
) |
533 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
534 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
535 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
536 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
537 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
538 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
539 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
));
540 if (rctx
->b
.chip_class
== R700
) {
541 r600_store_context_reg(&rs
->buffer
, R_028814_PA_SU_SC_MODE_CNTL
, rs
->pa_su_sc_mode_cntl
);
543 if (rctx
->b
.chip_class
== R600
) {
544 r600_store_context_reg(&rs
->buffer
, R_028350_SX_MISC
,
545 S_028350_MULTIPASS(state
->rasterizer_discard
));
550 static void *r600_create_sampler_state(struct pipe_context
*ctx
,
551 const struct pipe_sampler_state
*state
)
553 struct r600_pipe_sampler_state
*ss
= CALLOC_STRUCT(r600_pipe_sampler_state
);
554 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 4 : 0;
560 ss
->seamless_cube_map
= state
->seamless_cube_map
;
561 ss
->border_color_use
= sampler_state_needs_border_color(state
);
563 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
564 ss
->tex_sampler_words
[0] =
565 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
566 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
567 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
568 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
569 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
570 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
571 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
572 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
573 S_03C000_BORDER_COLOR_TYPE(ss
->border_color_use
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0);
574 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
575 ss
->tex_sampler_words
[1] =
576 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 6)) |
577 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 6)) |
578 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 6));
579 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
580 ss
->tex_sampler_words
[2] = S_03C008_TYPE(1);
582 if (ss
->border_color_use
) {
583 memcpy(&ss
->border_color
, &state
->border_color
, sizeof(state
->border_color
));
588 static struct pipe_sampler_view
*
589 texture_buffer_sampler_view(struct r600_pipe_sampler_view
*view
,
590 unsigned width0
, unsigned height0
)
593 struct r600_texture
*tmp
= (struct r600_texture
*)view
->base
.texture
;
594 int stride
= util_format_get_blocksize(view
->base
.format
);
595 unsigned format
, num_format
, format_comp
, endian
;
596 uint64_t offset
= view
->base
.u
.buf
.first_element
* stride
;
597 unsigned size
= (view
->base
.u
.buf
.last_element
- view
->base
.u
.buf
.first_element
+ 1) * stride
;
599 r600_vertex_data_type(view
->base
.format
,
600 &format
, &num_format
, &format_comp
,
603 view
->tex_resource
= &tmp
->resource
;
604 view
->skip_mip_address_reloc
= true;
606 view
->tex_resource_words
[0] = offset
;
607 view
->tex_resource_words
[1] = size
- 1;
608 view
->tex_resource_words
[2] = S_038008_BASE_ADDRESS_HI(offset
>> 32UL) |
609 S_038008_STRIDE(stride
) |
610 S_038008_DATA_FORMAT(format
) |
611 S_038008_NUM_FORMAT_ALL(num_format
) |
612 S_038008_FORMAT_COMP_ALL(format_comp
) |
613 S_038008_ENDIAN_SWAP(endian
);
614 view
->tex_resource_words
[3] = 0;
616 * in theory dword 4 is for number of elements, for use with resinfo,
617 * but it seems to utterly fail to work, the amd gpu shader analyser
618 * uses a const buffer to store the element sizes for buffer txq
620 view
->tex_resource_words
[4] = 0;
621 view
->tex_resource_words
[5] = 0;
622 view
->tex_resource_words
[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER
);
626 struct pipe_sampler_view
*
627 r600_create_sampler_view_custom(struct pipe_context
*ctx
,
628 struct pipe_resource
*texture
,
629 const struct pipe_sampler_view
*state
,
630 unsigned width_first_level
, unsigned height_first_level
)
632 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
633 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
634 unsigned format
, endian
;
635 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
636 unsigned char swizzle
[4], array_mode
= 0;
637 unsigned width
, height
, depth
, offset_level
, last_level
;
642 /* initialize base object */
644 view
->base
.texture
= NULL
;
645 pipe_reference(NULL
, &texture
->reference
);
646 view
->base
.texture
= texture
;
647 view
->base
.reference
.count
= 1;
648 view
->base
.context
= ctx
;
650 if (texture
->target
== PIPE_BUFFER
)
651 return texture_buffer_sampler_view(view
, texture
->width0
, 1);
653 swizzle
[0] = state
->swizzle_r
;
654 swizzle
[1] = state
->swizzle_g
;
655 swizzle
[2] = state
->swizzle_b
;
656 swizzle
[3] = state
->swizzle_a
;
658 format
= r600_translate_texformat(ctx
->screen
, state
->format
,
660 &word4
, &yuv_format
);
661 assert(format
!= ~0);
667 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
&& !r600_can_read_depth(tmp
)) {
668 if (!r600_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
672 tmp
= tmp
->flushed_depth_texture
;
675 endian
= r600_colorformat_endian_swap(format
);
677 offset_level
= state
->u
.tex
.first_level
;
678 last_level
= state
->u
.tex
.last_level
- offset_level
;
679 width
= width_first_level
;
680 height
= height_first_level
;
681 depth
= u_minify(texture
->depth0
, offset_level
);
682 pitch
= tmp
->surface
.level
[offset_level
].nblk_x
* util_format_get_blockwidth(state
->format
);
684 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
686 depth
= texture
->array_size
;
687 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
688 depth
= texture
->array_size
;
689 } else if (texture
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
690 depth
= texture
->array_size
/ 6;
691 switch (tmp
->surface
.level
[offset_level
].mode
) {
692 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
693 array_mode
= V_038000_ARRAY_LINEAR_ALIGNED
;
695 case RADEON_SURF_MODE_1D
:
696 array_mode
= V_038000_ARRAY_1D_TILED_THIN1
;
698 case RADEON_SURF_MODE_2D
:
699 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
701 case RADEON_SURF_MODE_LINEAR
:
703 array_mode
= V_038000_ARRAY_LINEAR_GENERAL
;
707 view
->tex_resource
= &tmp
->resource
;
708 view
->tex_resource_words
[0] = (S_038000_DIM(r600_tex_dim(texture
->target
, texture
->nr_samples
)) |
709 S_038000_TILE_MODE(array_mode
) |
710 S_038000_TILE_TYPE(tmp
->non_disp_tiling
) |
711 S_038000_PITCH((pitch
/ 8) - 1) |
712 S_038000_TEX_WIDTH(width
- 1));
713 view
->tex_resource_words
[1] = (S_038004_TEX_HEIGHT(height
- 1) |
714 S_038004_TEX_DEPTH(depth
- 1) |
715 S_038004_DATA_FORMAT(format
));
716 view
->tex_resource_words
[2] = tmp
->surface
.level
[offset_level
].offset
>> 8;
717 if (offset_level
>= tmp
->surface
.last_level
) {
718 view
->tex_resource_words
[3] = tmp
->surface
.level
[offset_level
].offset
>> 8;
720 view
->tex_resource_words
[3] = tmp
->surface
.level
[offset_level
+ 1].offset
>> 8;
722 view
->tex_resource_words
[4] = (word4
|
723 S_038010_REQUEST_SIZE(1) |
724 S_038010_ENDIAN_SWAP(endian
) |
725 S_038010_BASE_LEVEL(0));
726 view
->tex_resource_words
[5] = (S_038014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
727 S_038014_LAST_ARRAY(state
->u
.tex
.last_layer
));
728 if (texture
->nr_samples
> 1) {
729 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
730 view
->tex_resource_words
[5] |= S_038014_LAST_LEVEL(util_logbase2(texture
->nr_samples
));
732 view
->tex_resource_words
[5] |= S_038014_LAST_LEVEL(last_level
);
734 view
->tex_resource_words
[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE
) |
735 S_038018_MAX_ANISO(4 /* max 16 samples */));
739 static struct pipe_sampler_view
*
740 r600_create_sampler_view(struct pipe_context
*ctx
,
741 struct pipe_resource
*tex
,
742 const struct pipe_sampler_view
*state
)
744 return r600_create_sampler_view_custom(ctx
, tex
, state
,
745 u_minify(tex
->width0
, state
->u
.tex
.first_level
),
746 u_minify(tex
->height0
, state
->u
.tex
.first_level
));
749 static void r600_emit_clip_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
751 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
752 struct pipe_clip_state
*state
= &rctx
->clip_state
.state
;
754 r600_write_context_reg_seq(cs
, R_028E20_PA_CL_UCP0_X
, 6*4);
755 radeon_emit_array(cs
, (unsigned*)state
, 6*4);
758 static void r600_set_polygon_stipple(struct pipe_context
*ctx
,
759 const struct pipe_poly_stipple
*state
)
763 static void r600_emit_scissor_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
765 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
766 struct r600_scissor_state
*rstate
= (struct r600_scissor_state
*)atom
;
767 struct pipe_scissor_state
*state
= &rstate
->scissor
;
768 unsigned offset
= rstate
->idx
* 4 * 2;
770 if (rctx
->b
.chip_class
!= R600
|| rctx
->scissor
[0].enable
) {
771 r600_write_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
+ offset
, 2);
772 radeon_emit(cs
, S_028240_TL_X(state
->minx
) | S_028240_TL_Y(state
->miny
) |
773 S_028240_WINDOW_OFFSET_DISABLE(1));
774 radeon_emit(cs
, S_028244_BR_X(state
->maxx
) | S_028244_BR_Y(state
->maxy
));
776 r600_write_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 2);
777 radeon_emit(cs
, S_028240_TL_X(0) | S_028240_TL_Y(0) |
778 S_028240_WINDOW_OFFSET_DISABLE(1));
779 radeon_emit(cs
, S_028244_BR_X(8192) | S_028244_BR_Y(8192));
783 static void r600_set_scissor_states(struct pipe_context
*ctx
,
785 unsigned num_scissors
,
786 const struct pipe_scissor_state
*state
)
788 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
791 for (i
= start_slot
; i
< start_slot
+ num_scissors
; i
++) {
792 rctx
->scissor
[i
].scissor
= state
[i
- start_slot
];
795 if (rctx
->b
.chip_class
== R600
&& !rctx
->scissor
[0].enable
)
798 for (i
= start_slot
; i
< start_slot
+ num_scissors
; i
++) {
799 rctx
->scissor
[i
].atom
.dirty
= true;
803 static struct r600_resource
*r600_buffer_create_helper(struct r600_screen
*rscreen
,
804 unsigned size
, unsigned alignment
)
806 struct pipe_resource buffer
;
808 memset(&buffer
, 0, sizeof buffer
);
809 buffer
.target
= PIPE_BUFFER
;
810 buffer
.format
= PIPE_FORMAT_R8_UNORM
;
811 buffer
.bind
= PIPE_BIND_CUSTOM
;
812 buffer
.usage
= PIPE_USAGE_DEFAULT
;
814 buffer
.width0
= size
;
817 buffer
.array_size
= 1;
819 return (struct r600_resource
*)
820 r600_buffer_create(&rscreen
->b
.b
, &buffer
, alignment
);
823 static void r600_init_color_surface(struct r600_context
*rctx
,
824 struct r600_surface
*surf
,
825 bool force_cmask_fmask
)
827 struct r600_screen
*rscreen
= rctx
->screen
;
828 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
829 unsigned level
= surf
->base
.u
.tex
.level
;
830 unsigned pitch
, slice
;
833 unsigned format
, swap
, ntype
, endian
;
835 const struct util_format_description
*desc
;
837 bool blend_bypass
= 0, blend_clamp
= 1;
839 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
&& !r600_can_read_depth(rtex
)) {
840 r600_init_flushed_depth_texture(&rctx
->b
.b
, surf
->base
.texture
, NULL
);
841 rtex
= rtex
->flushed_depth_texture
;
845 offset
= rtex
->surface
.level
[level
].offset
;
846 if (rtex
->surface
.level
[level
].mode
== RADEON_SURF_MODE_LINEAR
) {
847 assert(surf
->base
.u
.tex
.first_layer
== surf
->base
.u
.tex
.last_layer
);
848 offset
+= rtex
->surface
.level
[level
].slice_size
*
849 surf
->base
.u
.tex
.first_layer
;
852 color_view
= S_028080_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
853 S_028080_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
855 pitch
= rtex
->surface
.level
[level
].nblk_x
/ 8 - 1;
856 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
861 switch (rtex
->surface
.level
[level
].mode
) {
862 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
863 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED
);
865 case RADEON_SURF_MODE_1D
:
866 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1
);
868 case RADEON_SURF_MODE_2D
:
869 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1
);
871 case RADEON_SURF_MODE_LINEAR
:
873 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL
);
877 desc
= util_format_description(surf
->base
.format
);
879 for (i
= 0; i
< 4; i
++) {
880 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
885 ntype
= V_0280A0_NUMBER_UNORM
;
886 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
887 ntype
= V_0280A0_NUMBER_SRGB
;
888 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
889 if (desc
->channel
[i
].normalized
)
890 ntype
= V_0280A0_NUMBER_SNORM
;
891 else if (desc
->channel
[i
].pure_integer
)
892 ntype
= V_0280A0_NUMBER_SINT
;
893 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
894 if (desc
->channel
[i
].normalized
)
895 ntype
= V_0280A0_NUMBER_UNORM
;
896 else if (desc
->channel
[i
].pure_integer
)
897 ntype
= V_0280A0_NUMBER_UINT
;
900 format
= r600_translate_colorformat(rctx
->b
.chip_class
, surf
->base
.format
);
901 assert(format
!= ~0);
903 swap
= r600_translate_colorswap(surf
->base
.format
);
906 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
907 endian
= ENDIAN_NONE
;
909 endian
= r600_colorformat_endian_swap(format
);
912 /* set blend bypass according to docs if SINT/UINT or
913 8/24 COLOR variants */
914 if (ntype
== V_0280A0_NUMBER_UINT
|| ntype
== V_0280A0_NUMBER_SINT
||
915 format
== V_0280A0_COLOR_8_24
|| format
== V_0280A0_COLOR_24_8
||
916 format
== V_0280A0_COLOR_X24_8_32_FLOAT
) {
921 surf
->alphatest_bypass
= ntype
== V_0280A0_NUMBER_UINT
|| ntype
== V_0280A0_NUMBER_SINT
;
923 color_info
|= S_0280A0_FORMAT(format
) |
924 S_0280A0_COMP_SWAP(swap
) |
925 S_0280A0_BLEND_BYPASS(blend_bypass
) |
926 S_0280A0_BLEND_CLAMP(blend_clamp
) |
927 S_0280A0_NUMBER_TYPE(ntype
) |
928 S_0280A0_ENDIAN(endian
);
930 /* EXPORT_NORM is an optimzation that can be enabled for better
931 * performance in certain cases
933 if (rctx
->b
.chip_class
== R600
) {
934 /* EXPORT_NORM can be enabled if:
935 * - 11-bit or smaller UNORM/SNORM/SRGB
936 * - BLEND_CLAMP is enabled
937 * - BLEND_FLOAT32 is disabled
939 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
940 (desc
->channel
[i
].size
< 12 &&
941 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
942 ntype
!= V_0280A0_NUMBER_UINT
&&
943 ntype
!= V_0280A0_NUMBER_SINT
) &&
944 G_0280A0_BLEND_CLAMP(color_info
) &&
945 !G_0280A0_BLEND_FLOAT32(color_info
)) {
946 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
947 surf
->export_16bpc
= true;
950 /* EXPORT_NORM can be enabled if:
951 * - 11-bit or smaller UNORM/SNORM/SRGB
952 * - 16-bit or smaller FLOAT
954 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
955 ((desc
->channel
[i
].size
< 12 &&
956 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
957 ntype
!= V_0280A0_NUMBER_UINT
&& ntype
!= V_0280A0_NUMBER_SINT
) ||
958 (desc
->channel
[i
].size
< 17 &&
959 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
960 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
961 surf
->export_16bpc
= true;
965 /* These might not always be initialized to zero. */
966 surf
->cb_color_base
= offset
>> 8;
967 surf
->cb_color_size
= S_028060_PITCH_TILE_MAX(pitch
) |
968 S_028060_SLICE_TILE_MAX(slice
);
969 surf
->cb_color_fmask
= surf
->cb_color_base
;
970 surf
->cb_color_cmask
= surf
->cb_color_base
;
971 surf
->cb_color_mask
= 0;
973 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
,
974 &rtex
->resource
.b
.b
);
975 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
,
976 &rtex
->resource
.b
.b
);
978 if (rtex
->cmask
.size
) {
979 surf
->cb_color_cmask
= rtex
->cmask
.offset
>> 8;
980 surf
->cb_color_mask
|= S_028100_CMASK_BLOCK_MAX(rtex
->cmask
.slice_tile_max
);
982 if (rtex
->fmask
.size
) {
983 color_info
|= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE
);
984 surf
->cb_color_fmask
= rtex
->fmask
.offset
>> 8;
985 surf
->cb_color_mask
|= S_028100_FMASK_TILE_MAX(rtex
->fmask
.slice_tile_max
);
986 } else { /* cmask only */
987 color_info
|= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE
);
989 } else if (force_cmask_fmask
) {
990 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
992 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
993 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
994 * because it's not an MSAA buffer.
996 struct r600_cmask_info cmask
;
997 struct r600_fmask_info fmask
;
999 r600_texture_get_cmask_info(&rscreen
->b
, rtex
, &cmask
);
1000 r600_texture_get_fmask_info(&rscreen
->b
, rtex
, 8, &fmask
);
1003 if (!rctx
->dummy_cmask
||
1004 rctx
->dummy_cmask
->buf
->size
< cmask
.size
||
1005 rctx
->dummy_cmask
->buf
->alignment
% cmask
.alignment
!= 0) {
1006 struct pipe_transfer
*transfer
;
1009 pipe_resource_reference((struct pipe_resource
**)&rctx
->dummy_cmask
, NULL
);
1010 rctx
->dummy_cmask
= r600_buffer_create_helper(rscreen
, cmask
.size
, cmask
.alignment
);
1012 /* Set the contents to 0xCC. */
1013 ptr
= pipe_buffer_map(&rctx
->b
.b
, &rctx
->dummy_cmask
->b
.b
, PIPE_TRANSFER_WRITE
, &transfer
);
1014 memset(ptr
, 0xCC, cmask
.size
);
1015 pipe_buffer_unmap(&rctx
->b
.b
, transfer
);
1017 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
,
1018 &rctx
->dummy_cmask
->b
.b
);
1021 if (!rctx
->dummy_fmask
||
1022 rctx
->dummy_fmask
->buf
->size
< fmask
.size
||
1023 rctx
->dummy_fmask
->buf
->alignment
% fmask
.alignment
!= 0) {
1024 pipe_resource_reference((struct pipe_resource
**)&rctx
->dummy_fmask
, NULL
);
1025 rctx
->dummy_fmask
= r600_buffer_create_helper(rscreen
, fmask
.size
, fmask
.alignment
);
1028 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
,
1029 &rctx
->dummy_fmask
->b
.b
);
1031 /* Init the registers. */
1032 color_info
|= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE
);
1033 surf
->cb_color_cmask
= 0;
1034 surf
->cb_color_fmask
= 0;
1035 surf
->cb_color_mask
= S_028100_CMASK_BLOCK_MAX(cmask
.slice_tile_max
) |
1036 S_028100_FMASK_TILE_MAX(fmask
.slice_tile_max
);
1039 surf
->cb_color_info
= color_info
;
1040 surf
->cb_color_view
= color_view
;
1041 surf
->color_initialized
= true;
1044 static void r600_init_depth_surface(struct r600_context
*rctx
,
1045 struct r600_surface
*surf
)
1047 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1048 unsigned level
, pitch
, slice
, format
, offset
, array_mode
;
1050 level
= surf
->base
.u
.tex
.level
;
1051 offset
= rtex
->surface
.level
[level
].offset
;
1052 pitch
= rtex
->surface
.level
[level
].nblk_x
/ 8 - 1;
1053 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1057 switch (rtex
->surface
.level
[level
].mode
) {
1058 case RADEON_SURF_MODE_2D
:
1059 array_mode
= V_0280A0_ARRAY_2D_TILED_THIN1
;
1061 case RADEON_SURF_MODE_1D
:
1062 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1063 case RADEON_SURF_MODE_LINEAR
:
1065 array_mode
= V_0280A0_ARRAY_1D_TILED_THIN1
;
1069 format
= r600_translate_dbformat(surf
->base
.format
);
1070 assert(format
!= ~0);
1072 surf
->db_depth_info
= S_028010_ARRAY_MODE(array_mode
) | S_028010_FORMAT(format
);
1073 surf
->db_depth_base
= offset
>> 8;
1074 surf
->db_depth_view
= S_028004_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1075 S_028004_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1076 surf
->db_depth_size
= S_028000_PITCH_TILE_MAX(pitch
) | S_028000_SLICE_TILE_MAX(slice
);
1077 surf
->db_prefetch_limit
= (rtex
->surface
.level
[level
].nblk_y
/ 8) - 1;
1079 switch (surf
->base
.format
) {
1080 case PIPE_FORMAT_Z24X8_UNORM
:
1081 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1082 surf
->pa_su_poly_offset_db_fmt_cntl
=
1083 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1085 case PIPE_FORMAT_Z32_FLOAT
:
1086 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1087 surf
->pa_su_poly_offset_db_fmt_cntl
=
1088 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1089 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1091 case PIPE_FORMAT_Z16_UNORM
:
1092 surf
->pa_su_poly_offset_db_fmt_cntl
=
1093 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1098 /* use htile only for first level */
1099 if (rtex
->htile_buffer
&& !level
) {
1100 surf
->db_htile_data_base
= 0;
1101 surf
->db_htile_surface
= S_028D24_HTILE_WIDTH(1) |
1102 S_028D24_HTILE_HEIGHT(1) |
1103 S_028D24_FULL_CACHE(1) |
1105 /* preload is not working properly on r6xx/r7xx */
1106 surf
->db_depth_info
|= S_028010_TILE_SURFACE_ENABLE(1);
1109 surf
->depth_initialized
= true;
1112 static void r600_set_framebuffer_state(struct pipe_context
*ctx
,
1113 const struct pipe_framebuffer_state
*state
)
1115 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1116 struct r600_surface
*surf
;
1117 struct r600_texture
*rtex
;
1120 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1121 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
1122 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_CB
|
1123 R600_CONTEXT_FLUSH_AND_INV_CB_META
;
1125 if (rctx
->framebuffer
.state
.zsbuf
) {
1126 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
1127 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_DB
;
1129 rtex
= (struct r600_texture
*)rctx
->framebuffer
.state
.zsbuf
->texture
;
1130 if (rctx
->b
.chip_class
>= R700
&& rtex
->htile_buffer
) {
1131 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_DB_META
;
1135 /* Set the new state. */
1136 util_copy_framebuffer_state(&rctx
->framebuffer
.state
, state
);
1138 rctx
->framebuffer
.export_16bpc
= state
->nr_cbufs
!= 0;
1139 rctx
->framebuffer
.cb0_is_integer
= state
->nr_cbufs
&& state
->cbufs
[0] &&
1140 util_format_is_pure_integer(state
->cbufs
[0]->format
);
1141 rctx
->framebuffer
.compressed_cb_mask
= 0;
1142 rctx
->framebuffer
.is_msaa_resolve
= state
->nr_cbufs
== 2 &&
1143 state
->cbufs
[0] && state
->cbufs
[1] &&
1144 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
1145 state
->cbufs
[1]->texture
->nr_samples
<= 1;
1146 rctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
1149 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
1150 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1151 bool force_cmask_fmask
= rctx
->b
.chip_class
== R600
&&
1152 rctx
->framebuffer
.is_msaa_resolve
&&
1155 surf
= (struct r600_surface
*)state
->cbufs
[i
];
1159 rtex
= (struct r600_texture
*)surf
->base
.texture
;
1160 r600_context_add_resource_size(ctx
, state
->cbufs
[i
]->texture
);
1162 if (!surf
->color_initialized
|| force_cmask_fmask
) {
1163 r600_init_color_surface(rctx
, surf
, force_cmask_fmask
);
1164 if (force_cmask_fmask
) {
1165 /* re-initialize later without compression */
1166 surf
->color_initialized
= false;
1170 if (!surf
->export_16bpc
) {
1171 rctx
->framebuffer
.export_16bpc
= false;
1174 if (rtex
->fmask
.size
&& rtex
->cmask
.size
) {
1175 rctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
1179 /* Update alpha-test state dependencies.
1180 * Alpha-test is done on the first colorbuffer only. */
1181 if (state
->nr_cbufs
) {
1182 bool alphatest_bypass
= false;
1184 surf
= (struct r600_surface
*)state
->cbufs
[0];
1186 alphatest_bypass
= surf
->alphatest_bypass
;
1189 if (rctx
->alphatest_state
.bypass
!= alphatest_bypass
) {
1190 rctx
->alphatest_state
.bypass
= alphatest_bypass
;
1191 rctx
->alphatest_state
.atom
.dirty
= true;
1197 surf
= (struct r600_surface
*)state
->zsbuf
;
1199 r600_context_add_resource_size(ctx
, state
->zsbuf
->texture
);
1201 if (!surf
->depth_initialized
) {
1202 r600_init_depth_surface(rctx
, surf
);
1205 if (state
->zsbuf
->format
!= rctx
->poly_offset_state
.zs_format
) {
1206 rctx
->poly_offset_state
.zs_format
= state
->zsbuf
->format
;
1207 rctx
->poly_offset_state
.atom
.dirty
= true;
1210 if (rctx
->db_state
.rsurf
!= surf
) {
1211 rctx
->db_state
.rsurf
= surf
;
1212 rctx
->db_state
.atom
.dirty
= true;
1213 rctx
->db_misc_state
.atom
.dirty
= true;
1215 } else if (rctx
->db_state
.rsurf
) {
1216 rctx
->db_state
.rsurf
= NULL
;
1217 rctx
->db_state
.atom
.dirty
= true;
1218 rctx
->db_misc_state
.atom
.dirty
= true;
1221 if (rctx
->cb_misc_state
.nr_cbufs
!= state
->nr_cbufs
) {
1222 rctx
->cb_misc_state
.nr_cbufs
= state
->nr_cbufs
;
1223 rctx
->cb_misc_state
.atom
.dirty
= true;
1226 if (state
->nr_cbufs
== 0 && rctx
->alphatest_state
.bypass
) {
1227 rctx
->alphatest_state
.bypass
= false;
1228 rctx
->alphatest_state
.atom
.dirty
= true;
1231 /* Calculate the CS size. */
1232 rctx
->framebuffer
.atom
.num_dw
=
1233 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1235 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1236 rctx
->framebuffer
.atom
.num_dw
+= 15 * rctx
->framebuffer
.state
.nr_cbufs
;
1237 rctx
->framebuffer
.atom
.num_dw
+= 3 * (2 + rctx
->framebuffer
.state
.nr_cbufs
);
1239 if (rctx
->framebuffer
.state
.zsbuf
) {
1240 rctx
->framebuffer
.atom
.num_dw
+= 16;
1241 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1242 rctx
->framebuffer
.atom
.num_dw
+= 3;
1244 if (rctx
->b
.family
> CHIP_R600
&& rctx
->b
.family
< CHIP_RV770
) {
1245 rctx
->framebuffer
.atom
.num_dw
+= 2;
1248 rctx
->framebuffer
.atom
.dirty
= true;
1251 static uint32_t sample_locs_2x
[] = {
1252 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1253 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1255 static unsigned max_dist_2x
= 4;
1257 static uint32_t sample_locs_4x
[] = {
1258 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1259 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1261 static unsigned max_dist_4x
= 6;
1262 static uint32_t sample_locs_8x
[] = {
1263 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1264 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1266 static unsigned max_dist_8x
= 7;
1268 static void r600_get_sample_position(struct pipe_context
*ctx
,
1269 unsigned sample_count
,
1270 unsigned sample_index
,
1277 switch (sample_count
) {
1280 out_value
[0] = out_value
[1] = 0.5;
1283 offset
= 4 * (sample_index
* 2);
1284 val
.idx
= (sample_locs_2x
[0] >> offset
) & 0xf;
1285 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1286 val
.idx
= (sample_locs_2x
[0] >> (offset
+ 4)) & 0xf;
1287 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1290 offset
= 4 * (sample_index
* 2);
1291 val
.idx
= (sample_locs_4x
[0] >> offset
) & 0xf;
1292 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1293 val
.idx
= (sample_locs_4x
[0] >> (offset
+ 4)) & 0xf;
1294 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1297 offset
= 4 * (sample_index
% 4 * 2);
1298 index
= (sample_index
/ 4);
1299 val
.idx
= (sample_locs_8x
[index
] >> offset
) & 0xf;
1300 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1301 val
.idx
= (sample_locs_8x
[index
] >> (offset
+ 4)) & 0xf;
1302 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1307 static void r600_emit_msaa_state(struct r600_context
*rctx
, int nr_samples
)
1309 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1310 unsigned max_dist
= 0;
1312 if (rctx
->b
.family
== CHIP_R600
) {
1313 switch (nr_samples
) {
1318 r600_write_config_reg(cs
, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S
, sample_locs_2x
[0]);
1319 max_dist
= max_dist_2x
;
1322 r600_write_config_reg(cs
, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S
, sample_locs_4x
[0]);
1323 max_dist
= max_dist_4x
;
1326 r600_write_config_reg_seq(cs
, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0
, 2);
1327 radeon_emit(cs
, sample_locs_8x
[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1328 radeon_emit(cs
, sample_locs_8x
[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1329 max_dist
= max_dist_8x
;
1333 switch (nr_samples
) {
1335 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1336 radeon_emit(cs
, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1337 radeon_emit(cs
, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1341 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1342 radeon_emit(cs
, sample_locs_2x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1343 radeon_emit(cs
, sample_locs_2x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1344 max_dist
= max_dist_2x
;
1347 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1348 radeon_emit(cs
, sample_locs_4x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1349 radeon_emit(cs
, sample_locs_4x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1350 max_dist
= max_dist_4x
;
1353 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1354 radeon_emit(cs
, sample_locs_8x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1355 radeon_emit(cs
, sample_locs_8x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1356 max_dist
= max_dist_8x
;
1361 if (nr_samples
> 1) {
1362 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1363 radeon_emit(cs
, S_028C00_LAST_PIXEL(1) |
1364 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1365 radeon_emit(cs
, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples
)) |
1366 S_028C04_MAX_SAMPLE_DIST(max_dist
)); /* R_028C04_PA_SC_AA_CONFIG */
1368 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1369 radeon_emit(cs
, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1370 radeon_emit(cs
, 0); /* R_028C04_PA_SC_AA_CONFIG */
1374 static void r600_emit_framebuffer_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1376 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1377 struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
.state
;
1378 unsigned nr_cbufs
= state
->nr_cbufs
;
1379 struct r600_surface
**cb
= (struct r600_surface
**)&state
->cbufs
[0];
1380 unsigned i
, sbu
= 0;
1383 r600_write_context_reg_seq(cs
, R_0280A0_CB_COLOR0_INFO
, 8);
1384 for (i
= 0; i
< nr_cbufs
; i
++) {
1385 radeon_emit(cs
, cb
[i
] ? cb
[i
]->cb_color_info
: 0);
1387 /* set CB_COLOR1_INFO for possible dual-src blending */
1388 if (i
== 1 && cb
[0]) {
1389 radeon_emit(cs
, cb
[0]->cb_color_info
);
1392 for (; i
< 8; i
++) {
1397 for (i
= 0; i
< nr_cbufs
; i
++) {
1404 r600_write_context_reg(cs
, R_028040_CB_COLOR0_BASE
+ i
*4, cb
[i
]->cb_color_base
);
1406 reloc
= r600_context_bo_reloc(&rctx
->b
,
1408 (struct r600_resource
*)cb
[i
]->base
.texture
,
1409 RADEON_USAGE_READWRITE
,
1410 cb
[i
]->base
.texture
->nr_samples
> 1 ?
1411 RADEON_PRIO_COLOR_BUFFER_MSAA
:
1412 RADEON_PRIO_COLOR_BUFFER
);
1413 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1414 radeon_emit(cs
, reloc
);
1417 r600_write_context_reg(cs
, R_0280E0_CB_COLOR0_FRAG
+ i
*4, cb
[i
]->cb_color_fmask
);
1419 reloc
= r600_context_bo_reloc(&rctx
->b
,
1421 cb
[i
]->cb_buffer_fmask
,
1422 RADEON_USAGE_READWRITE
,
1423 cb
[i
]->base
.texture
->nr_samples
> 1 ?
1424 RADEON_PRIO_COLOR_BUFFER_MSAA
:
1425 RADEON_PRIO_COLOR_BUFFER
);
1426 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1427 radeon_emit(cs
, reloc
);
1430 r600_write_context_reg(cs
, R_0280C0_CB_COLOR0_TILE
+ i
*4, cb
[i
]->cb_color_cmask
);
1432 reloc
= r600_context_bo_reloc(&rctx
->b
,
1434 cb
[i
]->cb_buffer_cmask
,
1435 RADEON_USAGE_READWRITE
,
1436 cb
[i
]->base
.texture
->nr_samples
> 1 ?
1437 RADEON_PRIO_COLOR_BUFFER_MSAA
:
1438 RADEON_PRIO_COLOR_BUFFER
);
1439 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1440 radeon_emit(cs
, reloc
);
1443 r600_write_context_reg_seq(cs
, R_028060_CB_COLOR0_SIZE
, nr_cbufs
);
1444 for (i
= 0; i
< nr_cbufs
; i
++) {
1445 radeon_emit(cs
, cb
[i
] ? cb
[i
]->cb_color_size
: 0);
1448 r600_write_context_reg_seq(cs
, R_028080_CB_COLOR0_VIEW
, nr_cbufs
);
1449 for (i
= 0; i
< nr_cbufs
; i
++) {
1450 radeon_emit(cs
, cb
[i
] ? cb
[i
]->cb_color_view
: 0);
1453 r600_write_context_reg_seq(cs
, R_028100_CB_COLOR0_MASK
, nr_cbufs
);
1454 for (i
= 0; i
< nr_cbufs
; i
++) {
1455 radeon_emit(cs
, cb
[i
] ? cb
[i
]->cb_color_mask
: 0);
1458 sbu
|= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs
);
1461 /* SURFACE_BASE_UPDATE */
1462 if (rctx
->b
.family
> CHIP_R600
&& rctx
->b
.family
< CHIP_RV770
&& sbu
) {
1463 radeon_emit(cs
, PKT3(PKT3_SURFACE_BASE_UPDATE
, 0, 0));
1464 radeon_emit(cs
, sbu
);
1470 struct r600_surface
*surf
= (struct r600_surface
*)state
->zsbuf
;
1471 unsigned reloc
= r600_context_bo_reloc(&rctx
->b
,
1473 (struct r600_resource
*)state
->zsbuf
->texture
,
1474 RADEON_USAGE_READWRITE
,
1475 surf
->base
.texture
->nr_samples
> 1 ?
1476 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
1477 RADEON_PRIO_DEPTH_BUFFER
);
1479 r600_write_context_reg(cs
, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1480 surf
->pa_su_poly_offset_db_fmt_cntl
);
1482 r600_write_context_reg_seq(cs
, R_028000_DB_DEPTH_SIZE
, 2);
1483 radeon_emit(cs
, surf
->db_depth_size
); /* R_028000_DB_DEPTH_SIZE */
1484 radeon_emit(cs
, surf
->db_depth_view
); /* R_028004_DB_DEPTH_VIEW */
1485 r600_write_context_reg_seq(cs
, R_02800C_DB_DEPTH_BASE
, 2);
1486 radeon_emit(cs
, surf
->db_depth_base
); /* R_02800C_DB_DEPTH_BASE */
1487 radeon_emit(cs
, surf
->db_depth_info
); /* R_028010_DB_DEPTH_INFO */
1489 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1490 radeon_emit(cs
, reloc
);
1492 r600_write_context_reg(cs
, R_028D34_DB_PREFETCH_LIMIT
, surf
->db_prefetch_limit
);
1494 sbu
|= SURFACE_BASE_UPDATE_DEPTH
;
1495 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1496 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1497 * Older kernels are out of luck. */
1498 r600_write_context_reg(cs
, R_028010_DB_DEPTH_INFO
, S_028010_FORMAT(V_028010_DEPTH_INVALID
));
1501 /* SURFACE_BASE_UPDATE */
1502 if (rctx
->b
.family
> CHIP_R600
&& rctx
->b
.family
< CHIP_RV770
&& sbu
) {
1503 radeon_emit(cs
, PKT3(PKT3_SURFACE_BASE_UPDATE
, 0, 0));
1504 radeon_emit(cs
, sbu
);
1508 /* Framebuffer dimensions. */
1509 r600_write_context_reg_seq(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, 2);
1510 radeon_emit(cs
, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1511 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1512 radeon_emit(cs
, S_028244_BR_X(state
->width
) |
1513 S_028244_BR_Y(state
->height
)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1515 if (rctx
->framebuffer
.is_msaa_resolve
) {
1516 r600_write_context_reg(cs
, R_0287A0_CB_SHADER_CONTROL
, 1);
1518 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1519 * will assure that the alpha-test will work even if there is
1520 * no colorbuffer bound. */
1521 r600_write_context_reg(cs
, R_0287A0_CB_SHADER_CONTROL
,
1522 (1ull << MAX2(nr_cbufs
, 1)) - 1);
1525 r600_emit_msaa_state(rctx
, rctx
->framebuffer
.nr_samples
);
1528 static void r600_emit_cb_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1530 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1531 struct r600_cb_misc_state
*a
= (struct r600_cb_misc_state
*)atom
;
1533 if (G_028808_SPECIAL_OP(a
->cb_color_control
) == V_028808_SPECIAL_RESOLVE_BOX
) {
1534 r600_write_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1535 if (rctx
->b
.chip_class
== R600
) {
1536 radeon_emit(cs
, 0xff); /* R_028238_CB_TARGET_MASK */
1537 radeon_emit(cs
, 0xff); /* R_02823C_CB_SHADER_MASK */
1539 radeon_emit(cs
, 0xf); /* R_028238_CB_TARGET_MASK */
1540 radeon_emit(cs
, 0xf); /* R_02823C_CB_SHADER_MASK */
1542 r600_write_context_reg(cs
, R_028808_CB_COLOR_CONTROL
, a
->cb_color_control
);
1544 unsigned fb_colormask
= (1ULL << ((unsigned)a
->nr_cbufs
* 4)) - 1;
1545 unsigned ps_colormask
= (1ULL << ((unsigned)a
->nr_ps_color_outputs
* 4)) - 1;
1546 unsigned multiwrite
= a
->multiwrite
&& a
->nr_cbufs
> 1;
1548 r600_write_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1549 radeon_emit(cs
, a
->blend_colormask
& fb_colormask
); /* R_028238_CB_TARGET_MASK */
1550 /* Always enable the first color output to make sure alpha-test works even without one. */
1551 radeon_emit(cs
, 0xf | (multiwrite
? fb_colormask
: ps_colormask
)); /* R_02823C_CB_SHADER_MASK */
1552 r600_write_context_reg(cs
, R_028808_CB_COLOR_CONTROL
,
1553 a
->cb_color_control
|
1554 S_028808_MULTIWRITE_ENABLE(multiwrite
));
1558 static void r600_emit_db_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1560 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1561 struct r600_db_state
*a
= (struct r600_db_state
*)atom
;
1563 if (a
->rsurf
&& a
->rsurf
->db_htile_surface
) {
1564 struct r600_texture
*rtex
= (struct r600_texture
*)a
->rsurf
->base
.texture
;
1567 r600_write_context_reg(cs
, R_02802C_DB_DEPTH_CLEAR
, fui(rtex
->depth_clear_value
));
1568 r600_write_context_reg(cs
, R_028D24_DB_HTILE_SURFACE
, a
->rsurf
->db_htile_surface
);
1569 r600_write_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, a
->rsurf
->db_htile_data_base
);
1570 reloc_idx
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rtex
->htile_buffer
,
1571 RADEON_USAGE_READWRITE
, RADEON_PRIO_DEPTH_META
);
1572 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1573 cs
->buf
[cs
->cdw
++] = reloc_idx
;
1575 r600_write_context_reg(cs
, R_028D24_DB_HTILE_SURFACE
, 0);
1579 static void r600_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1581 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1582 struct r600_db_misc_state
*a
= (struct r600_db_misc_state
*)atom
;
1583 unsigned db_render_control
= 0;
1584 unsigned db_render_override
=
1585 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE
) |
1586 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE
);
1588 if (a
->occlusion_query_enabled
) {
1589 if (rctx
->b
.chip_class
>= R700
) {
1590 db_render_control
|= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1592 db_render_override
|= S_028D10_NOOP_CULL_DISABLE(1);
1594 if (rctx
->db_state
.rsurf
&& rctx
->db_state
.rsurf
->db_htile_surface
) {
1595 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1596 db_render_override
|= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF
);
1597 /* This is to fix a lockup when hyperz and alpha test are enabled at
1598 * the same time somehow GPU get confuse on which order to pick for
1601 if (rctx
->alphatest_state
.sx_alpha_test_control
) {
1602 db_render_override
|= S_028D10_FORCE_SHADER_Z_ORDER(1);
1605 db_render_override
|= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE
);
1607 if (a
->flush_depthstencil_through_cb
) {
1608 assert(a
->copy_depth
|| a
->copy_stencil
);
1610 db_render_control
|= S_028D0C_DEPTH_COPY_ENABLE(a
->copy_depth
) |
1611 S_028D0C_STENCIL_COPY_ENABLE(a
->copy_stencil
) |
1612 S_028D0C_COPY_CENTROID(1) |
1613 S_028D0C_COPY_SAMPLE(a
->copy_sample
);
1614 } else if (a
->flush_depthstencil_in_place
) {
1615 db_render_control
|= S_028D0C_DEPTH_COMPRESS_DISABLE(1) |
1616 S_028D0C_STENCIL_COMPRESS_DISABLE(1);
1617 db_render_override
|= S_028D10_NOOP_CULL_DISABLE(1);
1619 if (a
->htile_clear
) {
1620 db_render_control
|= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1623 /* RV770 workaround for a hang with 8x MSAA. */
1624 if (rctx
->b
.family
== CHIP_RV770
&& a
->log_samples
== 3) {
1625 db_render_override
|= S_028D10_MAX_TILES_IN_DTT(6);
1628 r600_write_context_reg_seq(cs
, R_028D0C_DB_RENDER_CONTROL
, 2);
1629 radeon_emit(cs
, db_render_control
); /* R_028D0C_DB_RENDER_CONTROL */
1630 radeon_emit(cs
, db_render_override
); /* R_028D10_DB_RENDER_OVERRIDE */
1631 r600_write_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
, a
->db_shader_control
);
1634 static void r600_emit_config_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1636 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1637 struct r600_config_state
*a
= (struct r600_config_state
*)atom
;
1639 r600_write_config_reg(cs
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, a
->sq_gpr_resource_mgmt_1
);
1640 r600_write_config_reg(cs
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, a
->sq_gpr_resource_mgmt_2
);
1643 static void r600_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1645 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1646 uint32_t dirty_mask
= rctx
->vertex_buffer_state
.dirty_mask
;
1648 while (dirty_mask
) {
1649 struct pipe_vertex_buffer
*vb
;
1650 struct r600_resource
*rbuffer
;
1652 unsigned buffer_index
= u_bit_scan(&dirty_mask
);
1654 vb
= &rctx
->vertex_buffer_state
.vb
[buffer_index
];
1655 rbuffer
= (struct r600_resource
*)vb
->buffer
;
1658 offset
= vb
->buffer_offset
;
1660 /* fetch resources start at index 320 */
1661 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1662 radeon_emit(cs
, (320 + buffer_index
) * 7);
1663 radeon_emit(cs
, offset
); /* RESOURCEi_WORD0 */
1664 radeon_emit(cs
, rbuffer
->buf
->size
- offset
- 1); /* RESOURCEi_WORD1 */
1665 radeon_emit(cs
, /* RESOURCEi_WORD2 */
1666 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1667 S_038008_STRIDE(vb
->stride
));
1668 radeon_emit(cs
, 0); /* RESOURCEi_WORD3 */
1669 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
1670 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
1671 radeon_emit(cs
, 0xc0000000); /* RESOURCEi_WORD6 */
1673 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1674 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
1675 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BUFFER_RO
));
1679 static void r600_emit_constant_buffers(struct r600_context
*rctx
,
1680 struct r600_constbuf_state
*state
,
1681 unsigned buffer_id_base
,
1682 unsigned reg_alu_constbuf_size
,
1683 unsigned reg_alu_const_cache
)
1685 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1686 uint32_t dirty_mask
= state
->dirty_mask
;
1688 while (dirty_mask
) {
1689 struct pipe_constant_buffer
*cb
;
1690 struct r600_resource
*rbuffer
;
1692 unsigned buffer_index
= ffs(dirty_mask
) - 1;
1693 unsigned gs_ring_buffer
= (buffer_index
== R600_GS_RING_CONST_BUFFER
);
1694 cb
= &state
->cb
[buffer_index
];
1695 rbuffer
= (struct r600_resource
*)cb
->buffer
;
1698 offset
= cb
->buffer_offset
;
1700 if (!gs_ring_buffer
) {
1701 r600_write_context_reg(cs
, reg_alu_constbuf_size
+ buffer_index
* 4,
1702 ALIGN_DIVUP(cb
->buffer_size
>> 4, 16));
1703 r600_write_context_reg(cs
, reg_alu_const_cache
+ buffer_index
* 4, offset
>> 8);
1706 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1707 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
1708 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BUFFER_RO
));
1710 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1711 radeon_emit(cs
, (buffer_id_base
+ buffer_index
) * 7);
1712 radeon_emit(cs
, offset
); /* RESOURCEi_WORD0 */
1713 radeon_emit(cs
, rbuffer
->buf
->size
- offset
- 1); /* RESOURCEi_WORD1 */
1714 radeon_emit(cs
, /* RESOURCEi_WORD2 */
1715 S_038008_ENDIAN_SWAP(gs_ring_buffer
? ENDIAN_NONE
: r600_endian_swap(32)) |
1716 S_038008_STRIDE(gs_ring_buffer
? 4 : 16));
1717 radeon_emit(cs
, 0); /* RESOURCEi_WORD3 */
1718 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
1719 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
1720 radeon_emit(cs
, 0xc0000000); /* RESOURCEi_WORD6 */
1722 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1723 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
1724 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BUFFER_RO
));
1726 dirty_mask
&= ~(1 << buffer_index
);
1728 state
->dirty_mask
= 0;
1731 static void r600_emit_vs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1733 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
], 160,
1734 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
1735 R_028980_ALU_CONST_CACHE_VS_0
);
1738 static void r600_emit_gs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1740 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
], 336,
1741 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
,
1742 R_0289C0_ALU_CONST_CACHE_GS_0
);
1745 static void r600_emit_ps_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1747 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
], 0,
1748 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
1749 R_028940_ALU_CONST_CACHE_PS_0
);
1752 static void r600_emit_sampler_views(struct r600_context
*rctx
,
1753 struct r600_samplerview_state
*state
,
1754 unsigned resource_id_base
)
1756 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1757 uint32_t dirty_mask
= state
->dirty_mask
;
1759 while (dirty_mask
) {
1760 struct r600_pipe_sampler_view
*rview
;
1761 unsigned resource_index
= u_bit_scan(&dirty_mask
);
1764 rview
= state
->views
[resource_index
];
1767 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1768 radeon_emit(cs
, (resource_id_base
+ resource_index
) * 7);
1769 radeon_emit_array(cs
, rview
->tex_resource_words
, 7);
1771 reloc
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rview
->tex_resource
,
1773 rview
->tex_resource
->b
.b
.nr_samples
> 1 ?
1774 RADEON_PRIO_SHADER_TEXTURE_MSAA
:
1775 RADEON_PRIO_SHADER_TEXTURE_RO
);
1776 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1777 radeon_emit(cs
, reloc
);
1778 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1779 radeon_emit(cs
, reloc
);
1781 state
->dirty_mask
= 0;
1791 static void r600_emit_vs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
1793 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
, 160 + R600_MAX_CONST_BUFFERS
);
1796 static void r600_emit_gs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
1798 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
, 336 + R600_MAX_CONST_BUFFERS
);
1801 static void r600_emit_ps_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
1803 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
, R600_MAX_CONST_BUFFERS
);
1806 static void r600_emit_sampler_states(struct r600_context
*rctx
,
1807 struct r600_textures_info
*texinfo
,
1808 unsigned resource_id_base
,
1809 unsigned border_color_reg
)
1811 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1812 uint32_t dirty_mask
= texinfo
->states
.dirty_mask
;
1814 while (dirty_mask
) {
1815 struct r600_pipe_sampler_state
*rstate
;
1816 struct r600_pipe_sampler_view
*rview
;
1817 unsigned i
= u_bit_scan(&dirty_mask
);
1819 rstate
= texinfo
->states
.states
[i
];
1821 rview
= texinfo
->views
.views
[i
];
1823 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1824 * filtering between layers.
1825 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1828 enum pipe_texture_target target
= rview
->base
.texture
->target
;
1829 if (target
== PIPE_TEXTURE_1D_ARRAY
||
1830 target
== PIPE_TEXTURE_2D_ARRAY
) {
1831 rstate
->tex_sampler_words
[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1832 texinfo
->is_array_sampler
[i
] = true;
1834 rstate
->tex_sampler_words
[0] &= C_03C000_TEX_ARRAY_OVERRIDE
;
1835 texinfo
->is_array_sampler
[i
] = false;
1839 radeon_emit(cs
, PKT3(PKT3_SET_SAMPLER
, 3, 0));
1840 radeon_emit(cs
, (resource_id_base
+ i
) * 3);
1841 radeon_emit_array(cs
, rstate
->tex_sampler_words
, 3);
1843 if (rstate
->border_color_use
) {
1846 offset
= border_color_reg
;
1848 r600_write_config_reg_seq(cs
, offset
, 4);
1849 radeon_emit_array(cs
, rstate
->border_color
.ui
, 4);
1852 texinfo
->states
.dirty_mask
= 0;
1855 static void r600_emit_vs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
1857 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED
);
1860 static void r600_emit_gs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
1862 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED
);
1865 static void r600_emit_ps_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
1867 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED
);
1870 static void r600_emit_seamless_cube_map(struct r600_context
*rctx
, struct r600_atom
*atom
)
1872 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1875 tmp
= S_009508_DISABLE_CUBE_ANISO(1) |
1876 S_009508_SYNC_GRADIENT(1) |
1877 S_009508_SYNC_WALKER(1) |
1878 S_009508_SYNC_ALIGNER(1);
1879 if (!rctx
->seamless_cube_map
.enabled
) {
1880 tmp
|= S_009508_DISABLE_CUBE_WRAP(1);
1882 r600_write_config_reg(cs
, R_009508_TA_CNTL_AUX
, tmp
);
1885 static void r600_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
1887 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
1888 uint8_t mask
= s
->sample_mask
;
1890 r600_write_context_reg(rctx
->b
.rings
.gfx
.cs
, R_028C48_PA_SC_AA_MASK
,
1891 mask
| (mask
<< 8) | (mask
<< 16) | (mask
<< 24));
1894 static void r600_emit_vertex_fetch_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
1896 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1897 struct r600_cso_state
*state
= (struct r600_cso_state
*)a
;
1898 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
->cso
;
1900 r600_write_context_reg(cs
, R_028894_SQ_PGM_START_FS
, shader
->offset
>> 8);
1901 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1902 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, shader
->buffer
,
1903 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_DATA
));
1906 static void r600_emit_shader_stages(struct r600_context
*rctx
, struct r600_atom
*a
)
1908 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1909 struct r600_shader_stages_state
*state
= (struct r600_shader_stages_state
*)a
;
1911 uint32_t v2
= 0, primid
= 0;
1913 if (state
->geom_enable
) {
1916 if (rctx
->gs_shader
->current
->shader
.gs_max_out_vertices
<= 128)
1917 cut_val
= V_028A40_GS_CUT_128
;
1918 else if (rctx
->gs_shader
->current
->shader
.gs_max_out_vertices
<= 256)
1919 cut_val
= V_028A40_GS_CUT_256
;
1920 else if (rctx
->gs_shader
->current
->shader
.gs_max_out_vertices
<= 512)
1921 cut_val
= V_028A40_GS_CUT_512
;
1923 cut_val
= V_028A40_GS_CUT_1024
;
1925 v2
= S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
1926 S_028A40_CUT_MODE(cut_val
);
1928 if (rctx
->gs_shader
->current
->shader
.gs_prim_id_input
)
1932 r600_write_context_reg(cs
, R_028A40_VGT_GS_MODE
, v2
);
1933 r600_write_context_reg(cs
, R_028A84_VGT_PRIMITIVEID_EN
, primid
);
1936 static void r600_emit_gs_rings(struct r600_context
*rctx
, struct r600_atom
*a
)
1938 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1939 struct r600_gs_rings_state
*state
= (struct r600_gs_rings_state
*)a
;
1940 struct r600_resource
*rbuffer
;
1942 r600_write_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
1943 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1944 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
1946 if (state
->enable
) {
1947 rbuffer
=(struct r600_resource
*)state
->esgs_ring
.buffer
;
1948 r600_write_config_reg(cs
, R_008C40_SQ_ESGS_RING_BASE
, 0);
1949 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1950 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
1951 RADEON_USAGE_READWRITE
,
1952 RADEON_PRIO_SHADER_RESOURCE_RW
));
1953 r600_write_config_reg(cs
, R_008C44_SQ_ESGS_RING_SIZE
,
1954 state
->esgs_ring
.buffer_size
>> 8);
1956 rbuffer
=(struct r600_resource
*)state
->gsvs_ring
.buffer
;
1957 r600_write_config_reg(cs
, R_008C48_SQ_GSVS_RING_BASE
, 0);
1958 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1959 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
1960 RADEON_USAGE_READWRITE
,
1961 RADEON_PRIO_SHADER_RESOURCE_RW
));
1962 r600_write_config_reg(cs
, R_008C4C_SQ_GSVS_RING_SIZE
,
1963 state
->gsvs_ring
.buffer_size
>> 8);
1965 r600_write_config_reg(cs
, R_008C44_SQ_ESGS_RING_SIZE
, 0);
1966 r600_write_config_reg(cs
, R_008C4C_SQ_GSVS_RING_SIZE
, 0);
1969 r600_write_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
1970 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1971 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
1974 /* Adjust GPR allocation on R6xx/R7xx */
1975 bool r600_adjust_gprs(struct r600_context
*rctx
)
1977 unsigned num_ps_gprs
= rctx
->ps_shader
->current
->shader
.bc
.ngpr
;
1978 unsigned num_vs_gprs
, num_es_gprs
, num_gs_gprs
;
1979 unsigned new_num_ps_gprs
= num_ps_gprs
;
1980 unsigned new_num_vs_gprs
, new_num_es_gprs
, new_num_gs_gprs
;
1981 unsigned cur_num_ps_gprs
= G_008C04_NUM_PS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_1
);
1982 unsigned cur_num_vs_gprs
= G_008C04_NUM_VS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_1
);
1983 unsigned cur_num_gs_gprs
= G_008C08_NUM_GS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_2
);
1984 unsigned cur_num_es_gprs
= G_008C08_NUM_ES_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_2
);
1985 unsigned def_num_ps_gprs
= rctx
->default_ps_gprs
;
1986 unsigned def_num_vs_gprs
= rctx
->default_vs_gprs
;
1987 unsigned def_num_gs_gprs
= 0;
1988 unsigned def_num_es_gprs
= 0;
1989 unsigned def_num_clause_temp_gprs
= rctx
->r6xx_num_clause_temp_gprs
;
1990 /* hardware will reserve twice num_clause_temp_gprs */
1991 unsigned max_gprs
= def_num_gs_gprs
+ def_num_es_gprs
+ def_num_ps_gprs
+ def_num_vs_gprs
+ def_num_clause_temp_gprs
* 2;
1994 if (rctx
->gs_shader
) {
1995 num_es_gprs
= rctx
->vs_shader
->current
->shader
.bc
.ngpr
;
1996 num_gs_gprs
= rctx
->gs_shader
->current
->shader
.bc
.ngpr
;
1997 num_vs_gprs
= rctx
->gs_shader
->current
->gs_copy_shader
->shader
.bc
.ngpr
;
2001 num_vs_gprs
= rctx
->vs_shader
->current
->shader
.bc
.ngpr
;
2003 new_num_vs_gprs
= num_vs_gprs
;
2004 new_num_es_gprs
= num_es_gprs
;
2005 new_num_gs_gprs
= num_gs_gprs
;
2007 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2008 if (new_num_ps_gprs
> cur_num_ps_gprs
|| new_num_vs_gprs
> cur_num_vs_gprs
||
2009 new_num_es_gprs
> cur_num_es_gprs
|| new_num_gs_gprs
> cur_num_gs_gprs
) {
2010 /* try to use switch back to default */
2011 if (new_num_ps_gprs
> def_num_ps_gprs
|| new_num_vs_gprs
> def_num_vs_gprs
||
2012 new_num_gs_gprs
> def_num_gs_gprs
|| new_num_es_gprs
> def_num_es_gprs
) {
2013 /* always privilege vs stage so that at worst we have the
2014 * pixel stage producing wrong output (not the vertex
2016 new_num_ps_gprs
= max_gprs
- ((new_num_vs_gprs
- new_num_es_gprs
- new_num_gs_gprs
) + def_num_clause_temp_gprs
* 2);
2017 new_num_vs_gprs
= num_vs_gprs
;
2018 new_num_gs_gprs
= num_gs_gprs
;
2019 new_num_es_gprs
= num_es_gprs
;
2021 new_num_ps_gprs
= def_num_ps_gprs
;
2022 new_num_vs_gprs
= def_num_vs_gprs
;
2023 new_num_es_gprs
= def_num_es_gprs
;
2024 new_num_gs_gprs
= def_num_gs_gprs
;
2030 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2031 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2032 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2033 * it will lockup. So in this case just discard the draw command
2034 * and don't change the current gprs repartitions.
2036 if (num_ps_gprs
> new_num_ps_gprs
|| num_vs_gprs
> new_num_vs_gprs
||
2037 num_gs_gprs
> new_num_gs_gprs
|| num_es_gprs
> new_num_es_gprs
) {
2038 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2039 "for a combined maximum of %d\n",
2040 num_ps_gprs
, num_vs_gprs
, num_es_gprs
, num_gs_gprs
, max_gprs
);
2044 /* in some case we endup recomputing the current value */
2045 tmp
= S_008C04_NUM_PS_GPRS(new_num_ps_gprs
) |
2046 S_008C04_NUM_VS_GPRS(new_num_vs_gprs
) |
2047 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs
);
2049 tmp2
= S_008C08_NUM_ES_GPRS(new_num_es_gprs
) |
2050 S_008C08_NUM_GS_GPRS(new_num_gs_gprs
);
2051 if (rctx
->config_state
.sq_gpr_resource_mgmt_1
!= tmp
|| rctx
->config_state
.sq_gpr_resource_mgmt_2
!= tmp2
) {
2052 rctx
->config_state
.sq_gpr_resource_mgmt_1
= tmp
;
2053 rctx
->config_state
.sq_gpr_resource_mgmt_2
= tmp2
;
2054 rctx
->config_state
.atom
.dirty
= true;
2055 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
2060 void r600_init_atom_start_cs(struct r600_context
*rctx
)
2075 int num_ps_stack_entries
;
2076 int num_vs_stack_entries
;
2077 int num_gs_stack_entries
;
2078 int num_es_stack_entries
;
2079 enum radeon_family family
;
2080 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2083 r600_init_command_buffer(cb
, 256);
2085 /* R6xx requires this packet at the start of each command buffer */
2086 if (rctx
->b
.chip_class
== R600
) {
2087 r600_store_value(cb
, PKT3(PKT3_START_3D_CMDBUF
, 0, 0));
2088 r600_store_value(cb
, 0);
2090 /* All asics require this one */
2091 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2092 r600_store_value(cb
, 0x80000000);
2093 r600_store_value(cb
, 0x80000000);
2095 /* We're setting config registers here. */
2096 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2097 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2099 family
= rctx
->b
.family
;
2111 num_ps_threads
= 136;
2112 num_vs_threads
= 48;
2115 num_ps_stack_entries
= 128;
2116 num_vs_stack_entries
= 128;
2117 num_gs_stack_entries
= 0;
2118 num_es_stack_entries
= 0;
2127 num_ps_threads
= 144;
2128 num_vs_threads
= 40;
2131 num_ps_stack_entries
= 40;
2132 num_vs_stack_entries
= 40;
2133 num_gs_stack_entries
= 32;
2134 num_es_stack_entries
= 16;
2146 num_ps_threads
= 136;
2147 num_vs_threads
= 48;
2150 num_ps_stack_entries
= 40;
2151 num_vs_stack_entries
= 40;
2152 num_gs_stack_entries
= 32;
2153 num_es_stack_entries
= 16;
2161 num_ps_threads
= 136;
2162 num_vs_threads
= 48;
2165 num_ps_stack_entries
= 40;
2166 num_vs_stack_entries
= 40;
2167 num_gs_stack_entries
= 32;
2168 num_es_stack_entries
= 16;
2176 num_ps_threads
= 180;
2177 num_vs_threads
= 60;
2180 num_ps_stack_entries
= 128;
2181 num_vs_stack_entries
= 128;
2182 num_gs_stack_entries
= 128;
2183 num_es_stack_entries
= 128;
2192 num_ps_threads
= 180;
2193 num_vs_threads
= 60;
2196 num_ps_stack_entries
= 128;
2197 num_vs_stack_entries
= 128;
2198 num_gs_stack_entries
= 0;
2199 num_es_stack_entries
= 0;
2207 num_ps_threads
= 136;
2208 num_vs_threads
= 48;
2211 num_ps_stack_entries
= 128;
2212 num_vs_stack_entries
= 128;
2213 num_gs_stack_entries
= 0;
2214 num_es_stack_entries
= 0;
2218 rctx
->default_ps_gprs
= num_ps_gprs
;
2219 rctx
->default_vs_gprs
= num_vs_gprs
;
2220 rctx
->r6xx_num_clause_temp_gprs
= num_temp_gprs
;
2232 tmp
|= S_008C00_VC_ENABLE(1);
2235 tmp
|= S_008C00_DX9_CONSTS(0);
2236 tmp
|= S_008C00_ALU_INST_PREFER_VECTOR(1);
2237 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2238 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2239 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2240 tmp
|= S_008C00_ES_PRIO(es_prio
);
2241 r600_store_config_reg(cb
, R_008C00_SQ_CONFIG
, tmp
);
2243 /* SQ_GPR_RESOURCE_MGMT_2 */
2244 tmp
= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
2245 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
2246 r600_store_config_reg_seq(cb
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, 4);
2247 r600_store_value(cb
, tmp
);
2249 /* SQ_THREAD_RESOURCE_MGMT */
2250 tmp
= S_008C0C_NUM_PS_THREADS(num_ps_threads
);
2251 tmp
|= S_008C0C_NUM_VS_THREADS(num_vs_threads
);
2252 tmp
|= S_008C0C_NUM_GS_THREADS(num_gs_threads
);
2253 tmp
|= S_008C0C_NUM_ES_THREADS(num_es_threads
);
2254 r600_store_value(cb
, tmp
); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2256 /* SQ_STACK_RESOURCE_MGMT_1 */
2257 tmp
= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
2258 tmp
|= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
2259 r600_store_value(cb
, tmp
); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2261 /* SQ_STACK_RESOURCE_MGMT_2 */
2262 tmp
= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
2263 tmp
|= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
2264 r600_store_value(cb
, tmp
); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2266 r600_store_config_reg(cb
, R_009714_VC_ENHANCE
, 0);
2268 if (rctx
->b
.chip_class
>= R700
) {
2269 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0x00004000);
2270 r600_store_config_reg(cb
, R_009830_DB_DEBUG
, 0);
2271 r600_store_config_reg(cb
, R_009838_DB_WATERMARKS
, 0x00420204);
2272 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2274 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0);
2275 r600_store_config_reg(cb
, R_009830_DB_DEBUG
, 0x82000000);
2276 r600_store_config_reg(cb
, R_009838_DB_WATERMARKS
, 0x01020204);
2277 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 1);
2279 r600_store_context_reg_seq(cb
, R_0288A8_SQ_ESGS_RING_ITEMSIZE
, 9);
2280 r600_store_value(cb
, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2281 r600_store_value(cb
, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2282 r600_store_value(cb
, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2283 r600_store_value(cb
, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2284 r600_store_value(cb
, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2285 r600_store_value(cb
, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2286 r600_store_value(cb
, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2287 r600_store_value(cb
, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2288 r600_store_value(cb
, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2290 /* to avoid GPU doing any preloading of constant from random address */
2291 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 16);
2292 for (i
= 0; i
< 16; i
++)
2293 r600_store_value(cb
, 0);
2295 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 16);
2296 for (i
= 0; i
< 16; i
++)
2297 r600_store_value(cb
, 0);
2299 r600_store_context_reg_seq(cb
, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
, 16);
2300 for (i
= 0; i
< 16; i
++)
2301 r600_store_value(cb
, 0);
2303 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2304 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2305 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2306 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2307 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2308 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2309 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2310 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2311 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2312 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2313 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2314 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2315 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2316 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE, 0); */
2318 r600_store_context_reg(cb
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
2319 r600_store_context_reg(cb
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 0);
2320 r600_store_context_reg(cb
, R_028AA4_VGT_INSTANCE_STEP_RATE_1
, 0);
2322 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
2323 r600_store_value(cb
, 1); /* R_028AB4_VGT_REUSE_OFF */
2324 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2326 r600_store_context_reg(cb
, R_028B20_VGT_STRMOUT_BUFFER_EN
, 0);
2328 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2330 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
2332 r600_store_context_reg_seq(cb
, R_0286DC_SPI_FOG_CNTL
, 3);
2333 r600_store_value(cb
, 0); /* R_0286DC_SPI_FOG_CNTL */
2334 r600_store_value(cb
, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2335 r600_store_value(cb
, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2337 r600_store_context_reg_seq(cb
, R_028D28_DB_SRESULTS_COMPARE_STATE0
, 3);
2338 r600_store_value(cb
, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2339 r600_store_value(cb
, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2340 r600_store_value(cb
, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2342 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2343 r600_store_context_reg(cb
, R_028A48_PA_SC_MPASS_PS_CNTL
, 0);
2345 r600_store_context_reg_seq(cb
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 4);
2346 r600_store_value(cb
, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2347 r600_store_value(cb
, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2348 r600_store_value(cb
, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2349 r600_store_value(cb
, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2351 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2 * 16);
2352 for (tmp
= 0; tmp
< 16; tmp
++) {
2353 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2354 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2357 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2358 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2360 if (rctx
->b
.chip_class
>= R700
) {
2361 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2364 r600_store_context_reg_seq(cb
, R_028C30_CB_CLRCMP_CONTROL
, 4);
2365 r600_store_value(cb
, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2366 r600_store_value(cb
, 0); /* R_028C34_CB_CLRCMP_SRC */
2367 r600_store_value(cb
, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2368 r600_store_value(cb
, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2370 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2371 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2372 r600_store_value(cb
, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2374 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2375 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2376 r600_store_value(cb
, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2378 r600_store_context_reg_seq(cb
, R_0288CC_SQ_PGM_CF_OFFSET_PS
, 5);
2379 r600_store_value(cb
, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2380 r600_store_value(cb
, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2381 r600_store_value(cb
, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2382 r600_store_value(cb
, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2383 r600_store_value(cb
, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2385 r600_store_context_reg(cb
, R_0288E0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
2387 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2388 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2389 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2391 r600_store_context_reg(cb
, R_0288A4_SQ_PGM_RESOURCES_FS
, 0);
2393 if (rctx
->b
.chip_class
== R700
)
2394 r600_store_context_reg(cb
, R_028350_SX_MISC
, 0);
2395 if (rctx
->b
.chip_class
== R700
&& rctx
->screen
->b
.has_streamout
)
2396 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
2398 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2399 if (rctx
->screen
->b
.has_streamout
) {
2400 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2403 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
, 0x1000FFF);
2404 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
+ (32 * 4), 0x1000FFF);
2405 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
+ (64 * 4), 0x1000FFF);
2408 void r600_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2410 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2411 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2412 struct r600_shader
*rshader
= &shader
->shader
;
2413 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
;
2414 int pos_index
= -1, face_index
= -1;
2415 unsigned tmp
, sid
, ufi
= 0;
2416 int need_linear
= 0;
2417 unsigned z_export
= 0, stencil_export
= 0;
2418 unsigned sprite_coord_enable
= rctx
->rasterizer
? rctx
->rasterizer
->sprite_coord_enable
: 0;
2421 r600_init_command_buffer(cb
, 64);
2426 r600_store_context_reg_seq(cb
, R_028644_SPI_PS_INPUT_CNTL_0
, rshader
->ninput
);
2427 for (i
= 0; i
< rshader
->ninput
; i
++) {
2428 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
2430 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
2433 sid
= rshader
->input
[i
].spi_sid
;
2435 tmp
= S_028644_SEMANTIC(sid
);
2437 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
2438 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2439 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
2440 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
))
2441 tmp
|= S_028644_FLAT_SHADE(1);
2443 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
2444 sprite_coord_enable
& (1 << rshader
->input
[i
].sid
)) {
2445 tmp
|= S_028644_PT_SPRITE_TEX(1);
2448 if (rshader
->input
[i
].centroid
)
2449 tmp
|= S_028644_SEL_CENTROID(1);
2451 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
) {
2453 tmp
|= S_028644_SEL_LINEAR(1);
2456 r600_store_value(cb
, tmp
);
2459 db_shader_control
= 0;
2460 for (i
= 0; i
< rshader
->noutput
; i
++) {
2461 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2463 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2466 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(z_export
);
2467 db_shader_control
|= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export
);
2468 if (rshader
->uses_kill
)
2469 db_shader_control
|= S_02880C_KILL_ENABLE(1);
2472 for (i
= 0; i
< rshader
->noutput
; i
++) {
2473 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
2474 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
) {
2478 num_cout
= rshader
->nr_ps_color_exports
;
2479 exports_ps
|= S_028854_EXPORT_COLORS(num_cout
);
2481 /* always at least export 1 component per pixel */
2485 shader
->nr_ps_color_outputs
= num_cout
;
2487 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(rshader
->ninput
) |
2488 S_0286CC_PERSP_GRADIENT_ENA(1)|
2489 S_0286CC_LINEAR_GRADIENT_ENA(need_linear
);
2491 if (pos_index
!= -1) {
2492 spi_ps_in_control_0
|= (S_0286CC_POSITION_ENA(1) |
2493 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
2494 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
) |
2495 S_0286CC_BARYC_SAMPLE_CNTL(1));
2496 spi_input_z
|= S_0286D8_PROVIDE_Z_TO_SPI(1);
2499 spi_ps_in_control_1
= 0;
2500 if (face_index
!= -1) {
2501 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
2502 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
2505 /* HW bug in original R600 */
2506 if (rctx
->b
.family
== CHIP_R600
)
2509 r600_store_context_reg_seq(cb
, R_0286CC_SPI_PS_IN_CONTROL_0
, 2);
2510 r600_store_value(cb
, spi_ps_in_control_0
); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2511 r600_store_value(cb
, spi_ps_in_control_1
); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2513 r600_store_context_reg(cb
, R_0286D8_SPI_INPUT_Z
, spi_input_z
);
2515 r600_store_context_reg_seq(cb
, R_028850_SQ_PGM_RESOURCES_PS
, 2);
2516 r600_store_value(cb
, /* R_028850_SQ_PGM_RESOURCES_PS*/
2517 S_028850_NUM_GPRS(rshader
->bc
.ngpr
) |
2518 S_028850_STACK_SIZE(rshader
->bc
.nstack
) |
2519 S_028850_UNCACHED_FIRST_INST(ufi
));
2520 r600_store_value(cb
, exports_ps
); /* R_028854_SQ_PGM_EXPORTS_PS */
2522 r600_store_context_reg(cb
, R_028840_SQ_PGM_START_PS
, 0);
2523 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2525 /* only set some bits here, the other bits are set in the dsa state */
2526 shader
->db_shader_control
= db_shader_control
;
2527 shader
->ps_depth_export
= z_export
| stencil_export
;
2529 shader
->sprite_coord_enable
= sprite_coord_enable
;
2530 if (rctx
->rasterizer
)
2531 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
2534 void r600_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2536 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2537 struct r600_shader
*rshader
= &shader
->shader
;
2538 unsigned spi_vs_out_id
[10] = {};
2539 unsigned i
, tmp
, nparams
= 0;
2541 for (i
= 0; i
< rshader
->noutput
; i
++) {
2542 if (rshader
->output
[i
].spi_sid
) {
2543 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
2544 spi_vs_out_id
[nparams
/ 4] |= tmp
;
2549 r600_init_command_buffer(cb
, 32);
2551 r600_store_context_reg_seq(cb
, R_028614_SPI_VS_OUT_ID_0
, 10);
2552 for (i
= 0; i
< 10; i
++) {
2553 r600_store_value(cb
, spi_vs_out_id
[i
]);
2556 /* Certain attributes (position, psize, etc.) don't count as params.
2557 * VS is required to export at least one param and r600_shader_from_tgsi()
2558 * takes care of adding a dummy export.
2563 r600_store_context_reg(cb
, R_0286C4_SPI_VS_OUT_CONFIG
,
2564 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
2565 r600_store_context_reg(cb
, R_028868_SQ_PGM_RESOURCES_VS
,
2566 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
2567 S_028868_STACK_SIZE(rshader
->bc
.nstack
));
2568 if (rshader
->vs_position_window_space
) {
2569 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
,
2570 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
2572 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
,
2573 S_028818_VTX_W0_FMT(1) |
2574 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2575 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2576 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2579 r600_store_context_reg(cb
, R_028858_SQ_PGM_START_VS
, 0);
2580 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2582 shader
->pa_cl_vs_out_cntl
=
2583 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
2584 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
2585 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
2586 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
) |
2587 S_02881C_USE_VTX_EDGE_FLAG(rshader
->vs_out_edgeflag
) |
2588 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader
->vs_out_layer
) |
2589 S_02881C_USE_VTX_VIEWPORT_INDX(rshader
->vs_out_viewport
);
2592 void r600_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2594 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2595 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2596 struct r600_shader
*rshader
= &shader
->shader
;
2597 struct r600_shader
*cp_shader
= &shader
->gs_copy_shader
->shader
;
2598 unsigned gsvs_itemsize
=
2599 (cp_shader
->ring_item_size
* rshader
->gs_max_out_vertices
) >> 2;
2601 r600_init_command_buffer(cb
, 64);
2603 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2604 r600_store_context_reg(cb
, R_028AB8_VGT_VTX_CNT_EN
, 1);
2606 if (rctx
->b
.chip_class
>= R700
) {
2607 r600_store_context_reg(cb
, R_028B38_VGT_GS_MAX_VERT_OUT
,
2608 S_028B38_MAX_VERT_OUT(rshader
->gs_max_out_vertices
));
2610 r600_store_context_reg(cb
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
,
2611 r600_conv_prim_to_gs_out(rshader
->gs_output_prim
));
2613 r600_store_context_reg_seq(cb
, R_0288C8_SQ_GS_VERT_ITEMSIZE
, 4);
2614 r600_store_value(cb
, cp_shader
->ring_item_size
>> 2);
2615 r600_store_value(cb
, 0);
2616 r600_store_value(cb
, 0);
2617 r600_store_value(cb
, 0);
2619 r600_store_context_reg(cb
, R_0288A8_SQ_ESGS_RING_ITEMSIZE
,
2620 (rshader
->ring_item_size
) >> 2);
2622 r600_store_context_reg(cb
, R_0288AC_SQ_GSVS_RING_ITEMSIZE
,
2625 /* FIXME calculate these values somehow ??? */
2626 r600_store_config_reg_seq(cb
, R_0088C8_VGT_GS_PER_ES
, 2);
2627 r600_store_value(cb
, 0x80); /* GS_PER_ES */
2628 r600_store_value(cb
, 0x100); /* ES_PER_GS */
2629 r600_store_config_reg_seq(cb
, R_0088E8_VGT_GS_PER_VS
, 1);
2630 r600_store_value(cb
, 0x2); /* GS_PER_VS */
2632 r600_store_context_reg(cb
, R_02887C_SQ_PGM_RESOURCES_GS
,
2633 S_02887C_NUM_GPRS(rshader
->bc
.ngpr
) |
2634 S_02887C_STACK_SIZE(rshader
->bc
.nstack
));
2635 r600_store_context_reg(cb
, R_02886C_SQ_PGM_START_GS
, 0);
2636 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2639 void r600_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2641 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2642 struct r600_shader
*rshader
= &shader
->shader
;
2644 r600_init_command_buffer(cb
, 32);
2646 r600_store_context_reg(cb
, R_028890_SQ_PGM_RESOURCES_ES
,
2647 S_028890_NUM_GPRS(rshader
->bc
.ngpr
) |
2648 S_028890_STACK_SIZE(rshader
->bc
.nstack
));
2649 r600_store_context_reg(cb
, R_028880_SQ_PGM_START_ES
, 0);
2650 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2654 void *r600_create_resolve_blend(struct r600_context
*rctx
)
2656 struct pipe_blend_state blend
;
2659 memset(&blend
, 0, sizeof(blend
));
2660 blend
.independent_blend_enable
= true;
2661 for (i
= 0; i
< 2; i
++) {
2662 blend
.rt
[i
].colormask
= 0xf;
2663 blend
.rt
[i
].blend_enable
= 1;
2664 blend
.rt
[i
].rgb_func
= PIPE_BLEND_ADD
;
2665 blend
.rt
[i
].alpha_func
= PIPE_BLEND_ADD
;
2666 blend
.rt
[i
].rgb_src_factor
= PIPE_BLENDFACTOR_ZERO
;
2667 blend
.rt
[i
].rgb_dst_factor
= PIPE_BLENDFACTOR_ZERO
;
2668 blend
.rt
[i
].alpha_src_factor
= PIPE_BLENDFACTOR_ZERO
;
2669 blend
.rt
[i
].alpha_dst_factor
= PIPE_BLENDFACTOR_ZERO
;
2671 return r600_create_blend_state_mode(&rctx
->b
.b
, &blend
, V_028808_SPECIAL_RESOLVE_BOX
);
2674 void *r700_create_resolve_blend(struct r600_context
*rctx
)
2676 struct pipe_blend_state blend
;
2678 memset(&blend
, 0, sizeof(blend
));
2679 blend
.independent_blend_enable
= true;
2680 blend
.rt
[0].colormask
= 0xf;
2681 return r600_create_blend_state_mode(&rctx
->b
.b
, &blend
, V_028808_SPECIAL_RESOLVE_BOX
);
2684 void *r600_create_decompress_blend(struct r600_context
*rctx
)
2686 struct pipe_blend_state blend
;
2688 memset(&blend
, 0, sizeof(blend
));
2689 blend
.independent_blend_enable
= true;
2690 blend
.rt
[0].colormask
= 0xf;
2691 return r600_create_blend_state_mode(&rctx
->b
.b
, &blend
, V_028808_SPECIAL_EXPAND_SAMPLES
);
2694 void *r600_create_db_flush_dsa(struct r600_context
*rctx
)
2696 struct pipe_depth_stencil_alpha_state dsa
;
2697 boolean quirk
= false;
2699 if (rctx
->b
.family
== CHIP_RV610
|| rctx
->b
.family
== CHIP_RV630
||
2700 rctx
->b
.family
== CHIP_RV620
|| rctx
->b
.family
== CHIP_RV635
)
2703 memset(&dsa
, 0, sizeof(dsa
));
2706 dsa
.depth
.enabled
= 1;
2707 dsa
.depth
.func
= PIPE_FUNC_LEQUAL
;
2708 dsa
.stencil
[0].enabled
= 1;
2709 dsa
.stencil
[0].func
= PIPE_FUNC_ALWAYS
;
2710 dsa
.stencil
[0].zpass_op
= PIPE_STENCIL_OP_KEEP
;
2711 dsa
.stencil
[0].zfail_op
= PIPE_STENCIL_OP_INCR
;
2712 dsa
.stencil
[0].writemask
= 0xff;
2715 return rctx
->b
.b
.create_depth_stencil_alpha_state(&rctx
->b
.b
, &dsa
);
2718 void r600_update_db_shader_control(struct r600_context
* rctx
)
2721 unsigned db_shader_control
;
2723 if (!rctx
->ps_shader
) {
2727 dual_export
= rctx
->framebuffer
.export_16bpc
&&
2728 !rctx
->ps_shader
->current
->ps_depth_export
;
2730 db_shader_control
= rctx
->ps_shader
->current
->db_shader_control
|
2731 S_02880C_DUAL_EXPORT_ENABLE(dual_export
);
2733 /* When alpha test is enabled we can't trust the hw to make the proper
2734 * decision on the order in which ztest should be run related to fragment
2737 * If alpha test is enabled perform z test after fragment. RE_Z (early
2738 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2740 if (rctx
->alphatest_state
.sx_alpha_test_control
) {
2741 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
2743 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2746 if (db_shader_control
!= rctx
->db_misc_state
.db_shader_control
) {
2747 rctx
->db_misc_state
.db_shader_control
= db_shader_control
;
2748 rctx
->db_misc_state
.atom
.dirty
= true;
2752 static INLINE
unsigned r600_array_mode(unsigned mode
)
2755 case RADEON_SURF_MODE_LINEAR_ALIGNED
: return V_0280A0_ARRAY_LINEAR_ALIGNED
;
2757 case RADEON_SURF_MODE_1D
: return V_0280A0_ARRAY_1D_TILED_THIN1
;
2759 case RADEON_SURF_MODE_2D
: return V_0280A0_ARRAY_2D_TILED_THIN1
;
2761 case RADEON_SURF_MODE_LINEAR
: return V_0280A0_ARRAY_LINEAR_GENERAL
;
2765 static boolean
r600_dma_copy_tile(struct r600_context
*rctx
,
2766 struct pipe_resource
*dst
,
2771 struct pipe_resource
*src
,
2776 unsigned copy_height
,
2780 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.dma
.cs
;
2781 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
2782 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
2783 unsigned array_mode
, lbpp
, pitch_tile_max
, slice_tile_max
, size
;
2784 unsigned ncopy
, height
, cheight
, detile
, i
, x
, y
, z
, src_mode
, dst_mode
;
2785 uint64_t base
, addr
;
2787 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
2788 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
2789 /* downcast linear aligned to linear to simplify test */
2790 src_mode
= src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: src_mode
;
2791 dst_mode
= dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: dst_mode
;
2792 assert(dst_mode
!= src_mode
);
2795 lbpp
= util_logbase2(bpp
);
2796 pitch_tile_max
= ((pitch
/ bpp
) / 8) - 1;
2798 if (dst_mode
== RADEON_SURF_MODE_LINEAR
) {
2800 array_mode
= r600_array_mode(src_mode
);
2801 slice_tile_max
= (rsrc
->surface
.level
[src_level
].nblk_x
* rsrc
->surface
.level
[src_level
].nblk_y
) / (8*8);
2802 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
2803 /* linear height must be the same as the slice tile max height, it's ok even
2804 * if the linear destination/source have smaller heigh as the size of the
2805 * dma packet will be using the copy_height which is always smaller or equal
2806 * to the linear height
2808 height
= rsrc
->surface
.level
[src_level
].npix_y
;
2813 base
= rsrc
->surface
.level
[src_level
].offset
;
2814 addr
= rdst
->surface
.level
[dst_level
].offset
;
2815 addr
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
2816 addr
+= dst_y
* pitch
+ dst_x
* bpp
;
2819 array_mode
= r600_array_mode(dst_mode
);
2820 slice_tile_max
= (rdst
->surface
.level
[dst_level
].nblk_x
* rdst
->surface
.level
[dst_level
].nblk_y
) / (8*8);
2821 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
2822 /* linear height must be the same as the slice tile max height, it's ok even
2823 * if the linear destination/source have smaller heigh as the size of the
2824 * dma packet will be using the copy_height which is always smaller or equal
2825 * to the linear height
2827 height
= rdst
->surface
.level
[dst_level
].npix_y
;
2832 base
= rdst
->surface
.level
[dst_level
].offset
;
2833 addr
= rsrc
->surface
.level
[src_level
].offset
;
2834 addr
+= rsrc
->surface
.level
[src_level
].slice_size
* src_z
;
2835 addr
+= src_y
* pitch
+ src_x
* bpp
;
2837 /* check that we are in dw/base alignment constraint */
2838 if (addr
% 4 || base
% 256) {
2842 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2843 * line in the blit. Compute max 8 line we can copy in the size limit
2845 cheight
= ((R600_DMA_COPY_MAX_SIZE_DW
* 4) / pitch
) & 0xfffffff8;
2846 ncopy
= (copy_height
/ cheight
) + !!(copy_height
% cheight
);
2847 r600_need_dma_space(&rctx
->b
, ncopy
* 7);
2849 for (i
= 0; i
< ncopy
; i
++) {
2850 cheight
= cheight
> copy_height
? copy_height
: cheight
;
2851 size
= (cheight
* pitch
) / 4;
2852 /* emit reloc before writting cs so that cs is always in consistent state */
2853 r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.dma
, &rsrc
->resource
, RADEON_USAGE_READ
,
2855 r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.dma
, &rdst
->resource
, RADEON_USAGE_WRITE
,
2857 cs
->buf
[cs
->cdw
++] = DMA_PACKET(DMA_PACKET_COPY
, 1, 0, size
);
2858 cs
->buf
[cs
->cdw
++] = base
>> 8;
2859 cs
->buf
[cs
->cdw
++] = (detile
<< 31) | (array_mode
<< 27) |
2860 (lbpp
<< 24) | ((height
- 1) << 10) |
2862 cs
->buf
[cs
->cdw
++] = (slice_tile_max
<< 12) | (z
<< 0);
2863 cs
->buf
[cs
->cdw
++] = (x
<< 3) | (y
<< 17);
2864 cs
->buf
[cs
->cdw
++] = addr
& 0xfffffffc;
2865 cs
->buf
[cs
->cdw
++] = (addr
>> 32UL) & 0xff;
2866 copy_height
-= cheight
;
2867 addr
+= cheight
* pitch
;
2873 static void r600_dma_copy(struct pipe_context
*ctx
,
2874 struct pipe_resource
*dst
,
2876 unsigned dstx
, unsigned dsty
, unsigned dstz
,
2877 struct pipe_resource
*src
,
2879 const struct pipe_box
*src_box
)
2881 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2882 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
2883 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
2884 unsigned dst_pitch
, src_pitch
, bpp
, dst_mode
, src_mode
, copy_height
;
2885 unsigned src_w
, dst_w
;
2886 unsigned src_x
, src_y
;
2887 unsigned dst_x
= dstx
, dst_y
= dsty
, dst_z
= dstz
;
2889 if (rctx
->b
.rings
.dma
.cs
== NULL
) {
2893 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
2894 if (dst_x
% 4 || src_box
->x
% 4 || src_box
->width
% 4)
2897 r600_dma_copy_buffer(rctx
, dst
, src
, dst_x
, src_box
->x
, src_box
->width
);
2901 if (src
->format
!= dst
->format
|| src_box
->depth
> 1) {
2905 src_x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
2906 dst_x
= util_format_get_nblocksx(src
->format
, dst_x
);
2907 src_y
= util_format_get_nblocksy(src
->format
, src_box
->y
);
2908 dst_y
= util_format_get_nblocksy(src
->format
, dst_y
);
2910 bpp
= rdst
->surface
.bpe
;
2911 dst_pitch
= rdst
->surface
.level
[dst_level
].pitch_bytes
;
2912 src_pitch
= rsrc
->surface
.level
[src_level
].pitch_bytes
;
2913 src_w
= rsrc
->surface
.level
[src_level
].npix_x
;
2914 dst_w
= rdst
->surface
.level
[dst_level
].npix_x
;
2915 copy_height
= src_box
->height
/ rsrc
->surface
.blk_h
;
2917 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
2918 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
2919 /* downcast linear aligned to linear to simplify test */
2920 src_mode
= src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: src_mode
;
2921 dst_mode
= dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: dst_mode
;
2923 if (src_pitch
!= dst_pitch
|| src_box
->x
|| dst_x
|| src_w
!= dst_w
) {
2924 /* strict requirement on r6xx/r7xx */
2927 /* lot of constraint on alignment this should capture them all */
2928 if (src_pitch
% 8 || src_box
->y
% 8 || dst_y
% 8) {
2932 if (src_mode
== dst_mode
) {
2933 uint64_t dst_offset
, src_offset
, size
;
2935 /* simple dma blit would do NOTE code here assume :
2938 * dst_pitch == src_pitch
2940 src_offset
= rsrc
->surface
.level
[src_level
].offset
;
2941 src_offset
+= rsrc
->surface
.level
[src_level
].slice_size
* src_box
->z
;
2942 src_offset
+= src_y
* src_pitch
+ src_x
* bpp
;
2943 dst_offset
= rdst
->surface
.level
[dst_level
].offset
;
2944 dst_offset
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
2945 dst_offset
+= dst_y
* dst_pitch
+ dst_x
* bpp
;
2946 size
= src_box
->height
* src_pitch
;
2947 /* must be dw aligned */
2948 if (dst_offset
% 4 || src_offset
% 4 || size
% 4) {
2951 r600_dma_copy_buffer(rctx
, dst
, src
, dst_offset
, src_offset
, size
);
2953 if (!r600_dma_copy_tile(rctx
, dst
, dst_level
, dst_x
, dst_y
, dst_z
,
2954 src
, src_level
, src_x
, src_y
, src_box
->z
,
2955 copy_height
, dst_pitch
, bpp
)) {
2962 ctx
->resource_copy_region(ctx
, dst
, dst_level
, dstx
, dsty
, dstz
,
2963 src
, src_level
, src_box
);
2966 void r600_init_state_functions(struct r600_context
*rctx
)
2972 * To avoid GPU lockup registers must be emited in a specific order
2973 * (no kidding ...). The order below is important and have been
2974 * partialy infered from analyzing fglrx command stream.
2976 * Don't reorder atom without carefully checking the effect (GPU lockup
2977 * or piglit regression).
2981 r600_init_atom(rctx
, &rctx
->framebuffer
.atom
, id
++, r600_emit_framebuffer_state
, 0);
2984 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
].atom
, id
++, r600_emit_vs_constant_buffers
, 0);
2985 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
].atom
, id
++, r600_emit_gs_constant_buffers
, 0);
2986 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
].atom
, id
++, r600_emit_ps_constant_buffers
, 0);
2988 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2989 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
2991 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].states
.atom
, id
++, r600_emit_vs_sampler_states
, 0);
2992 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].states
.atom
, id
++, r600_emit_gs_sampler_states
, 0);
2993 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].states
.atom
, id
++, r600_emit_ps_sampler_states
, 0);
2995 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
.atom
, id
++, r600_emit_vs_sampler_views
, 0);
2996 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
.atom
, id
++, r600_emit_gs_sampler_views
, 0);
2997 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.atom
, id
++, r600_emit_ps_sampler_views
, 0);
2998 r600_init_atom(rctx
, &rctx
->vertex_buffer_state
.atom
, id
++, r600_emit_vertex_buffers
, 0);
3000 r600_init_atom(rctx
, &rctx
->vgt_state
.atom
, id
++, r600_emit_vgt_state
, 7);
3002 r600_init_atom(rctx
, &rctx
->seamless_cube_map
.atom
, id
++, r600_emit_seamless_cube_map
, 3);
3003 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, r600_emit_sample_mask
, 3);
3004 rctx
->sample_mask
.sample_mask
= ~0;
3006 r600_init_atom(rctx
, &rctx
->alphatest_state
.atom
, id
++, r600_emit_alphatest_state
, 6);
3007 r600_init_atom(rctx
, &rctx
->blend_color
.atom
, id
++, r600_emit_blend_color
, 6);
3008 r600_init_atom(rctx
, &rctx
->blend_state
.atom
, id
++, r600_emit_cso_state
, 0);
3009 r600_init_atom(rctx
, &rctx
->cb_misc_state
.atom
, id
++, r600_emit_cb_misc_state
, 7);
3010 r600_init_atom(rctx
, &rctx
->clip_misc_state
.atom
, id
++, r600_emit_clip_misc_state
, 6);
3011 r600_init_atom(rctx
, &rctx
->clip_state
.atom
, id
++, r600_emit_clip_state
, 26);
3012 r600_init_atom(rctx
, &rctx
->db_misc_state
.atom
, id
++, r600_emit_db_misc_state
, 7);
3013 r600_init_atom(rctx
, &rctx
->db_state
.atom
, id
++, r600_emit_db_state
, 11);
3014 r600_init_atom(rctx
, &rctx
->dsa_state
.atom
, id
++, r600_emit_cso_state
, 0);
3015 r600_init_atom(rctx
, &rctx
->poly_offset_state
.atom
, id
++, r600_emit_polygon_offset
, 6);
3016 r600_init_atom(rctx
, &rctx
->rasterizer_state
.atom
, id
++, r600_emit_cso_state
, 0);
3017 for (i
= 0;i
< 16; i
++) {
3018 r600_init_atom(rctx
, &rctx
->scissor
[i
].atom
, id
++, r600_emit_scissor_state
, 4);
3019 r600_init_atom(rctx
, &rctx
->viewport
[i
].atom
, id
++, r600_emit_viewport_state
, 8);
3020 rctx
->scissor
[i
].idx
= i
;
3021 rctx
->viewport
[i
].idx
= i
;
3023 r600_init_atom(rctx
, &rctx
->config_state
.atom
, id
++, r600_emit_config_state
, 3);
3024 r600_init_atom(rctx
, &rctx
->stencil_ref
.atom
, id
++, r600_emit_stencil_ref
, 4);
3025 r600_init_atom(rctx
, &rctx
->vertex_fetch_shader
.atom
, id
++, r600_emit_vertex_fetch_shader
, 5);
3026 rctx
->atoms
[id
++] = &rctx
->b
.streamout
.begin_atom
;
3027 rctx
->atoms
[id
++] = &rctx
->b
.streamout
.enable_atom
;
3028 r600_init_atom(rctx
, &rctx
->vertex_shader
.atom
, id
++, r600_emit_shader
, 23);
3029 r600_init_atom(rctx
, &rctx
->pixel_shader
.atom
, id
++, r600_emit_shader
, 0);
3030 r600_init_atom(rctx
, &rctx
->geometry_shader
.atom
, id
++, r600_emit_shader
, 0);
3031 r600_init_atom(rctx
, &rctx
->export_shader
.atom
, id
++, r600_emit_shader
, 0);
3032 r600_init_atom(rctx
, &rctx
->shader_stages
.atom
, id
++, r600_emit_shader_stages
, 0);
3033 r600_init_atom(rctx
, &rctx
->gs_rings
.atom
, id
++, r600_emit_gs_rings
, 0);
3035 rctx
->b
.b
.create_blend_state
= r600_create_blend_state
;
3036 rctx
->b
.b
.create_depth_stencil_alpha_state
= r600_create_dsa_state
;
3037 rctx
->b
.b
.create_rasterizer_state
= r600_create_rs_state
;
3038 rctx
->b
.b
.create_sampler_state
= r600_create_sampler_state
;
3039 rctx
->b
.b
.create_sampler_view
= r600_create_sampler_view
;
3040 rctx
->b
.b
.set_framebuffer_state
= r600_set_framebuffer_state
;
3041 rctx
->b
.b
.set_polygon_stipple
= r600_set_polygon_stipple
;
3042 rctx
->b
.b
.set_scissor_states
= r600_set_scissor_states
;
3043 rctx
->b
.b
.get_sample_position
= r600_get_sample_position
;
3044 rctx
->b
.dma_copy
= r600_dma_copy
;
3046 /* this function must be last */