2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
24 #include "r600_shader.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
33 static uint32_t r600_translate_blend_function(int blend_func
)
37 return V_028804_COMB_DST_PLUS_SRC
;
38 case PIPE_BLEND_SUBTRACT
:
39 return V_028804_COMB_SRC_MINUS_DST
;
40 case PIPE_BLEND_REVERSE_SUBTRACT
:
41 return V_028804_COMB_DST_MINUS_SRC
;
43 return V_028804_COMB_MIN_DST_SRC
;
45 return V_028804_COMB_MAX_DST_SRC
;
47 R600_ERR("Unknown blend function %d\n", blend_func
);
54 static uint32_t r600_translate_blend_factor(int blend_fact
)
57 case PIPE_BLENDFACTOR_ONE
:
58 return V_028804_BLEND_ONE
;
59 case PIPE_BLENDFACTOR_SRC_COLOR
:
60 return V_028804_BLEND_SRC_COLOR
;
61 case PIPE_BLENDFACTOR_SRC_ALPHA
:
62 return V_028804_BLEND_SRC_ALPHA
;
63 case PIPE_BLENDFACTOR_DST_ALPHA
:
64 return V_028804_BLEND_DST_ALPHA
;
65 case PIPE_BLENDFACTOR_DST_COLOR
:
66 return V_028804_BLEND_DST_COLOR
;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE
;
69 case PIPE_BLENDFACTOR_CONST_COLOR
:
70 return V_028804_BLEND_CONST_COLOR
;
71 case PIPE_BLENDFACTOR_CONST_ALPHA
:
72 return V_028804_BLEND_CONST_ALPHA
;
73 case PIPE_BLENDFACTOR_ZERO
:
74 return V_028804_BLEND_ZERO
;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR
;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA
;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA
;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR
;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR
;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA
;
87 case PIPE_BLENDFACTOR_SRC1_COLOR
:
88 return V_028804_BLEND_SRC1_COLOR
;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
90 return V_028804_BLEND_SRC1_ALPHA
;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
92 return V_028804_BLEND_INV_SRC1_COLOR
;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
94 return V_028804_BLEND_INV_SRC1_ALPHA
;
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
103 static unsigned r600_tex_dim(unsigned dim
, unsigned nr_samples
)
107 case PIPE_TEXTURE_1D
:
108 return V_038000_SQ_TEX_DIM_1D
;
109 case PIPE_TEXTURE_1D_ARRAY
:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY
;
111 case PIPE_TEXTURE_2D
:
112 case PIPE_TEXTURE_RECT
:
113 return nr_samples
> 1 ? V_038000_SQ_TEX_DIM_2D_MSAA
:
114 V_038000_SQ_TEX_DIM_2D
;
115 case PIPE_TEXTURE_2D_ARRAY
:
116 return nr_samples
> 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
117 V_038000_SQ_TEX_DIM_2D_ARRAY
;
118 case PIPE_TEXTURE_3D
:
119 return V_038000_SQ_TEX_DIM_3D
;
120 case PIPE_TEXTURE_CUBE
:
121 return V_038000_SQ_TEX_DIM_CUBEMAP
;
125 static uint32_t r600_translate_dbformat(enum pipe_format format
)
128 case PIPE_FORMAT_Z16_UNORM
:
129 return V_028010_DEPTH_16
;
130 case PIPE_FORMAT_Z24X8_UNORM
:
131 return V_028010_DEPTH_X8_24
;
132 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
133 return V_028010_DEPTH_8_24
;
134 case PIPE_FORMAT_Z32_FLOAT
:
135 return V_028010_DEPTH_32_FLOAT
;
136 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
137 return V_028010_DEPTH_X24_8_32_FLOAT
;
143 static uint32_t r600_translate_colorswap(enum pipe_format format
)
147 case PIPE_FORMAT_A8_UNORM
:
148 case PIPE_FORMAT_A8_SNORM
:
149 case PIPE_FORMAT_A8_UINT
:
150 case PIPE_FORMAT_A8_SINT
:
151 case PIPE_FORMAT_A16_UNORM
:
152 case PIPE_FORMAT_A16_SNORM
:
153 case PIPE_FORMAT_A16_UINT
:
154 case PIPE_FORMAT_A16_SINT
:
155 case PIPE_FORMAT_A16_FLOAT
:
156 case PIPE_FORMAT_A32_UINT
:
157 case PIPE_FORMAT_A32_SINT
:
158 case PIPE_FORMAT_A32_FLOAT
:
159 case PIPE_FORMAT_R4A4_UNORM
:
160 return V_0280A0_SWAP_ALT_REV
;
161 case PIPE_FORMAT_I8_UNORM
:
162 case PIPE_FORMAT_I8_SNORM
:
163 case PIPE_FORMAT_I8_UINT
:
164 case PIPE_FORMAT_I8_SINT
:
165 case PIPE_FORMAT_L8_UNORM
:
166 case PIPE_FORMAT_L8_SNORM
:
167 case PIPE_FORMAT_L8_UINT
:
168 case PIPE_FORMAT_L8_SINT
:
169 case PIPE_FORMAT_L8_SRGB
:
170 case PIPE_FORMAT_L16_UNORM
:
171 case PIPE_FORMAT_L16_SNORM
:
172 case PIPE_FORMAT_L16_UINT
:
173 case PIPE_FORMAT_L16_SINT
:
174 case PIPE_FORMAT_L16_FLOAT
:
175 case PIPE_FORMAT_L32_UINT
:
176 case PIPE_FORMAT_L32_SINT
:
177 case PIPE_FORMAT_L32_FLOAT
:
178 case PIPE_FORMAT_I16_UNORM
:
179 case PIPE_FORMAT_I16_SNORM
:
180 case PIPE_FORMAT_I16_UINT
:
181 case PIPE_FORMAT_I16_SINT
:
182 case PIPE_FORMAT_I16_FLOAT
:
183 case PIPE_FORMAT_I32_UINT
:
184 case PIPE_FORMAT_I32_SINT
:
185 case PIPE_FORMAT_I32_FLOAT
:
186 case PIPE_FORMAT_R8_UNORM
:
187 case PIPE_FORMAT_R8_SNORM
:
188 case PIPE_FORMAT_R8_UINT
:
189 case PIPE_FORMAT_R8_SINT
:
190 return V_0280A0_SWAP_STD
;
192 case PIPE_FORMAT_L4A4_UNORM
:
193 case PIPE_FORMAT_A4R4_UNORM
:
194 return V_0280A0_SWAP_ALT
;
196 /* 16-bit buffers. */
197 case PIPE_FORMAT_B5G6R5_UNORM
:
198 return V_0280A0_SWAP_STD_REV
;
200 case PIPE_FORMAT_B5G5R5A1_UNORM
:
201 case PIPE_FORMAT_B5G5R5X1_UNORM
:
202 return V_0280A0_SWAP_ALT
;
204 case PIPE_FORMAT_B4G4R4A4_UNORM
:
205 case PIPE_FORMAT_B4G4R4X4_UNORM
:
206 return V_0280A0_SWAP_ALT
;
208 case PIPE_FORMAT_Z16_UNORM
:
209 return V_0280A0_SWAP_STD
;
211 case PIPE_FORMAT_L8A8_UNORM
:
212 case PIPE_FORMAT_L8A8_SNORM
:
213 case PIPE_FORMAT_L8A8_UINT
:
214 case PIPE_FORMAT_L8A8_SINT
:
215 case PIPE_FORMAT_L8A8_SRGB
:
216 case PIPE_FORMAT_L16A16_UNORM
:
217 case PIPE_FORMAT_L16A16_SNORM
:
218 case PIPE_FORMAT_L16A16_UINT
:
219 case PIPE_FORMAT_L16A16_SINT
:
220 case PIPE_FORMAT_L16A16_FLOAT
:
221 case PIPE_FORMAT_L32A32_UINT
:
222 case PIPE_FORMAT_L32A32_SINT
:
223 case PIPE_FORMAT_L32A32_FLOAT
:
224 return V_0280A0_SWAP_ALT
;
225 case PIPE_FORMAT_R8G8_UNORM
:
226 case PIPE_FORMAT_R8G8_SNORM
:
227 case PIPE_FORMAT_R8G8_UINT
:
228 case PIPE_FORMAT_R8G8_SINT
:
229 return V_0280A0_SWAP_STD
;
231 case PIPE_FORMAT_R16_UNORM
:
232 case PIPE_FORMAT_R16_SNORM
:
233 case PIPE_FORMAT_R16_UINT
:
234 case PIPE_FORMAT_R16_SINT
:
235 case PIPE_FORMAT_R16_FLOAT
:
236 return V_0280A0_SWAP_STD
;
238 /* 32-bit buffers. */
240 case PIPE_FORMAT_A8B8G8R8_SRGB
:
241 return V_0280A0_SWAP_STD_REV
;
242 case PIPE_FORMAT_B8G8R8A8_SRGB
:
243 return V_0280A0_SWAP_ALT
;
245 case PIPE_FORMAT_B8G8R8A8_UNORM
:
246 case PIPE_FORMAT_B8G8R8X8_UNORM
:
247 return V_0280A0_SWAP_ALT
;
249 case PIPE_FORMAT_A8R8G8B8_UNORM
:
250 case PIPE_FORMAT_X8R8G8B8_UNORM
:
251 return V_0280A0_SWAP_ALT_REV
;
252 case PIPE_FORMAT_R8G8B8A8_SNORM
:
253 case PIPE_FORMAT_R8G8B8A8_UNORM
:
254 case PIPE_FORMAT_R8G8B8X8_UNORM
:
255 case PIPE_FORMAT_R8G8B8A8_SINT
:
256 case PIPE_FORMAT_R8G8B8A8_UINT
:
257 return V_0280A0_SWAP_STD
;
259 case PIPE_FORMAT_A8B8G8R8_UNORM
:
260 case PIPE_FORMAT_X8B8G8R8_UNORM
:
261 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
262 return V_0280A0_SWAP_STD_REV
;
264 case PIPE_FORMAT_Z24X8_UNORM
:
265 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
266 return V_0280A0_SWAP_STD
;
268 case PIPE_FORMAT_X8Z24_UNORM
:
269 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
270 return V_0280A0_SWAP_STD
;
272 case PIPE_FORMAT_R10G10B10A2_UNORM
:
273 case PIPE_FORMAT_R10G10B10X2_SNORM
:
274 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
275 return V_0280A0_SWAP_STD
;
277 case PIPE_FORMAT_B10G10R10A2_UNORM
:
278 case PIPE_FORMAT_B10G10R10A2_UINT
:
279 return V_0280A0_SWAP_ALT
;
281 case PIPE_FORMAT_R11G11B10_FLOAT
:
282 case PIPE_FORMAT_R16G16_UNORM
:
283 case PIPE_FORMAT_R16G16_SNORM
:
284 case PIPE_FORMAT_R16G16_FLOAT
:
285 case PIPE_FORMAT_R16G16_UINT
:
286 case PIPE_FORMAT_R16G16_SINT
:
287 case PIPE_FORMAT_R32_UINT
:
288 case PIPE_FORMAT_R32_SINT
:
289 case PIPE_FORMAT_R32_FLOAT
:
290 case PIPE_FORMAT_Z32_FLOAT
:
291 return V_0280A0_SWAP_STD
;
293 /* 64-bit buffers. */
294 case PIPE_FORMAT_R32G32_FLOAT
:
295 case PIPE_FORMAT_R32G32_UINT
:
296 case PIPE_FORMAT_R32G32_SINT
:
297 case PIPE_FORMAT_R16G16B16A16_UNORM
:
298 case PIPE_FORMAT_R16G16B16A16_SNORM
:
299 case PIPE_FORMAT_R16G16B16A16_UINT
:
300 case PIPE_FORMAT_R16G16B16A16_SINT
:
301 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
302 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
304 /* 128-bit buffers. */
305 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
306 case PIPE_FORMAT_R32G32B32A32_SNORM
:
307 case PIPE_FORMAT_R32G32B32A32_UNORM
:
308 case PIPE_FORMAT_R32G32B32A32_SINT
:
309 case PIPE_FORMAT_R32G32B32A32_UINT
:
310 return V_0280A0_SWAP_STD
;
312 R600_ERR("unsupported colorswap format %d\n", format
);
318 static uint32_t r600_translate_colorformat(enum pipe_format format
)
321 case PIPE_FORMAT_L4A4_UNORM
:
322 case PIPE_FORMAT_R4A4_UNORM
:
323 case PIPE_FORMAT_A4R4_UNORM
:
324 return V_0280A0_COLOR_4_4
;
327 case PIPE_FORMAT_A8_UNORM
:
328 case PIPE_FORMAT_A8_SNORM
:
329 case PIPE_FORMAT_A8_UINT
:
330 case PIPE_FORMAT_A8_SINT
:
331 case PIPE_FORMAT_I8_UNORM
:
332 case PIPE_FORMAT_I8_SNORM
:
333 case PIPE_FORMAT_I8_UINT
:
334 case PIPE_FORMAT_I8_SINT
:
335 case PIPE_FORMAT_L8_UNORM
:
336 case PIPE_FORMAT_L8_SNORM
:
337 case PIPE_FORMAT_L8_UINT
:
338 case PIPE_FORMAT_L8_SINT
:
339 case PIPE_FORMAT_L8_SRGB
:
340 case PIPE_FORMAT_R8_UNORM
:
341 case PIPE_FORMAT_R8_SNORM
:
342 case PIPE_FORMAT_R8_UINT
:
343 case PIPE_FORMAT_R8_SINT
:
344 return V_0280A0_COLOR_8
;
346 /* 16-bit buffers. */
347 case PIPE_FORMAT_B5G6R5_UNORM
:
348 return V_0280A0_COLOR_5_6_5
;
350 case PIPE_FORMAT_B5G5R5A1_UNORM
:
351 case PIPE_FORMAT_B5G5R5X1_UNORM
:
352 return V_0280A0_COLOR_1_5_5_5
;
354 case PIPE_FORMAT_B4G4R4A4_UNORM
:
355 case PIPE_FORMAT_B4G4R4X4_UNORM
:
356 return V_0280A0_COLOR_4_4_4_4
;
358 case PIPE_FORMAT_Z16_UNORM
:
359 return V_0280A0_COLOR_16
;
361 case PIPE_FORMAT_L8A8_UNORM
:
362 case PIPE_FORMAT_L8A8_SNORM
:
363 case PIPE_FORMAT_L8A8_UINT
:
364 case PIPE_FORMAT_L8A8_SINT
:
365 case PIPE_FORMAT_L8A8_SRGB
:
366 case PIPE_FORMAT_R8G8_UNORM
:
367 case PIPE_FORMAT_R8G8_SNORM
:
368 case PIPE_FORMAT_R8G8_UINT
:
369 case PIPE_FORMAT_R8G8_SINT
:
370 return V_0280A0_COLOR_8_8
;
372 case PIPE_FORMAT_R16_UNORM
:
373 case PIPE_FORMAT_R16_SNORM
:
374 case PIPE_FORMAT_R16_UINT
:
375 case PIPE_FORMAT_R16_SINT
:
376 case PIPE_FORMAT_A16_UNORM
:
377 case PIPE_FORMAT_A16_SNORM
:
378 case PIPE_FORMAT_A16_UINT
:
379 case PIPE_FORMAT_A16_SINT
:
380 case PIPE_FORMAT_L16_UNORM
:
381 case PIPE_FORMAT_L16_SNORM
:
382 case PIPE_FORMAT_L16_UINT
:
383 case PIPE_FORMAT_L16_SINT
:
384 case PIPE_FORMAT_I16_UNORM
:
385 case PIPE_FORMAT_I16_SNORM
:
386 case PIPE_FORMAT_I16_UINT
:
387 case PIPE_FORMAT_I16_SINT
:
388 return V_0280A0_COLOR_16
;
390 case PIPE_FORMAT_R16_FLOAT
:
391 case PIPE_FORMAT_A16_FLOAT
:
392 case PIPE_FORMAT_L16_FLOAT
:
393 case PIPE_FORMAT_I16_FLOAT
:
394 return V_0280A0_COLOR_16_FLOAT
;
396 /* 32-bit buffers. */
397 case PIPE_FORMAT_A8B8G8R8_SRGB
:
398 case PIPE_FORMAT_A8B8G8R8_UNORM
:
399 case PIPE_FORMAT_A8R8G8B8_UNORM
:
400 case PIPE_FORMAT_B8G8R8A8_SRGB
:
401 case PIPE_FORMAT_B8G8R8A8_UNORM
:
402 case PIPE_FORMAT_B8G8R8X8_UNORM
:
403 case PIPE_FORMAT_R8G8B8A8_SNORM
:
404 case PIPE_FORMAT_R8G8B8A8_UNORM
:
405 case PIPE_FORMAT_R8G8B8X8_UNORM
:
406 case PIPE_FORMAT_R8SG8SB8UX8U_NORM
:
407 case PIPE_FORMAT_X8B8G8R8_UNORM
:
408 case PIPE_FORMAT_X8R8G8B8_UNORM
:
409 case PIPE_FORMAT_R8G8B8A8_SINT
:
410 case PIPE_FORMAT_R8G8B8A8_UINT
:
411 return V_0280A0_COLOR_8_8_8_8
;
413 case PIPE_FORMAT_R10G10B10A2_UNORM
:
414 case PIPE_FORMAT_R10G10B10X2_SNORM
:
415 case PIPE_FORMAT_B10G10R10A2_UNORM
:
416 case PIPE_FORMAT_B10G10R10A2_UINT
:
417 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
418 return V_0280A0_COLOR_2_10_10_10
;
420 case PIPE_FORMAT_Z24X8_UNORM
:
421 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
422 return V_0280A0_COLOR_8_24
;
424 case PIPE_FORMAT_X8Z24_UNORM
:
425 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
426 return V_0280A0_COLOR_24_8
;
428 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
429 return V_0280A0_COLOR_X24_8_32_FLOAT
;
431 case PIPE_FORMAT_R32_UINT
:
432 case PIPE_FORMAT_R32_SINT
:
433 case PIPE_FORMAT_A32_UINT
:
434 case PIPE_FORMAT_A32_SINT
:
435 case PIPE_FORMAT_L32_UINT
:
436 case PIPE_FORMAT_L32_SINT
:
437 case PIPE_FORMAT_I32_UINT
:
438 case PIPE_FORMAT_I32_SINT
:
439 return V_0280A0_COLOR_32
;
441 case PIPE_FORMAT_R32_FLOAT
:
442 case PIPE_FORMAT_A32_FLOAT
:
443 case PIPE_FORMAT_L32_FLOAT
:
444 case PIPE_FORMAT_I32_FLOAT
:
445 case PIPE_FORMAT_Z32_FLOAT
:
446 return V_0280A0_COLOR_32_FLOAT
;
448 case PIPE_FORMAT_R16G16_FLOAT
:
449 case PIPE_FORMAT_L16A16_FLOAT
:
450 return V_0280A0_COLOR_16_16_FLOAT
;
452 case PIPE_FORMAT_R16G16_UNORM
:
453 case PIPE_FORMAT_R16G16_SNORM
:
454 case PIPE_FORMAT_R16G16_UINT
:
455 case PIPE_FORMAT_R16G16_SINT
:
456 case PIPE_FORMAT_L16A16_UNORM
:
457 case PIPE_FORMAT_L16A16_SNORM
:
458 case PIPE_FORMAT_L16A16_UINT
:
459 case PIPE_FORMAT_L16A16_SINT
:
460 return V_0280A0_COLOR_16_16
;
462 case PIPE_FORMAT_R11G11B10_FLOAT
:
463 return V_0280A0_COLOR_10_11_11_FLOAT
;
465 /* 64-bit buffers. */
466 case PIPE_FORMAT_R16G16B16A16_UINT
:
467 case PIPE_FORMAT_R16G16B16A16_SINT
:
468 case PIPE_FORMAT_R16G16B16A16_UNORM
:
469 case PIPE_FORMAT_R16G16B16A16_SNORM
:
470 return V_0280A0_COLOR_16_16_16_16
;
472 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
473 return V_0280A0_COLOR_16_16_16_16_FLOAT
;
475 case PIPE_FORMAT_R32G32_FLOAT
:
476 case PIPE_FORMAT_L32A32_FLOAT
:
477 return V_0280A0_COLOR_32_32_FLOAT
;
479 case PIPE_FORMAT_R32G32_SINT
:
480 case PIPE_FORMAT_R32G32_UINT
:
481 case PIPE_FORMAT_L32A32_UINT
:
482 case PIPE_FORMAT_L32A32_SINT
:
483 return V_0280A0_COLOR_32_32
;
485 /* 128-bit buffers. */
486 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
487 return V_0280A0_COLOR_32_32_32_32_FLOAT
;
488 case PIPE_FORMAT_R32G32B32A32_SNORM
:
489 case PIPE_FORMAT_R32G32B32A32_UNORM
:
490 case PIPE_FORMAT_R32G32B32A32_SINT
:
491 case PIPE_FORMAT_R32G32B32A32_UINT
:
492 return V_0280A0_COLOR_32_32_32_32
;
495 case PIPE_FORMAT_UYVY
:
496 case PIPE_FORMAT_YUYV
:
498 return ~0U; /* Unsupported. */
502 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat
)
504 if (R600_BIG_ENDIAN
) {
505 switch(colorformat
) {
506 case V_0280A0_COLOR_4_4
:
510 case V_0280A0_COLOR_8
:
513 /* 16-bit buffers. */
514 case V_0280A0_COLOR_5_6_5
:
515 case V_0280A0_COLOR_1_5_5_5
:
516 case V_0280A0_COLOR_4_4_4_4
:
517 case V_0280A0_COLOR_16
:
518 case V_0280A0_COLOR_8_8
:
521 /* 32-bit buffers. */
522 case V_0280A0_COLOR_8_8_8_8
:
523 case V_0280A0_COLOR_2_10_10_10
:
524 case V_0280A0_COLOR_8_24
:
525 case V_0280A0_COLOR_24_8
:
526 case V_0280A0_COLOR_32_FLOAT
:
527 case V_0280A0_COLOR_16_16_FLOAT
:
528 case V_0280A0_COLOR_16_16
:
531 /* 64-bit buffers. */
532 case V_0280A0_COLOR_16_16_16_16
:
533 case V_0280A0_COLOR_16_16_16_16_FLOAT
:
536 case V_0280A0_COLOR_32_32_FLOAT
:
537 case V_0280A0_COLOR_32_32
:
538 case V_0280A0_COLOR_X24_8_32_FLOAT
:
541 /* 128-bit buffers. */
542 case V_0280A0_COLOR_32_32_32_FLOAT
:
543 case V_0280A0_COLOR_32_32_32_32_FLOAT
:
544 case V_0280A0_COLOR_32_32_32_32
:
547 return ENDIAN_NONE
; /* Unsupported. */
554 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
556 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
) != ~0U;
559 static bool r600_is_colorbuffer_format_supported(enum pipe_format format
)
561 return r600_translate_colorformat(format
) != ~0U &&
562 r600_translate_colorswap(format
) != ~0U;
565 static bool r600_is_zs_format_supported(enum pipe_format format
)
567 return r600_translate_dbformat(format
) != ~0U;
570 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
571 enum pipe_format format
,
572 enum pipe_texture_target target
,
573 unsigned sample_count
,
576 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
579 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
580 R600_ERR("r600: unsupported texture type %d\n", target
);
584 if (!util_format_is_supported(format
, usage
))
587 if (sample_count
> 1) {
588 if (!rscreen
->has_msaa
)
591 /* R11G11B10 is broken on R6xx. */
592 if (rscreen
->chip_class
== R600
&&
593 format
== PIPE_FORMAT_R11G11B10_FLOAT
)
596 /* MSAA integer colorbuffers hang. */
597 if (util_format_is_pure_integer(format
) &&
598 !util_format_is_depth_or_stencil(format
))
601 switch (sample_count
) {
611 if ((usage
& PIPE_BIND_SAMPLER_VIEW
) &&
612 r600_is_sampler_format_supported(screen
, format
)) {
613 retval
|= PIPE_BIND_SAMPLER_VIEW
;
616 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
617 PIPE_BIND_DISPLAY_TARGET
|
619 PIPE_BIND_SHARED
)) &&
620 r600_is_colorbuffer_format_supported(format
)) {
622 (PIPE_BIND_RENDER_TARGET
|
623 PIPE_BIND_DISPLAY_TARGET
|
628 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
629 r600_is_zs_format_supported(format
)) {
630 retval
|= PIPE_BIND_DEPTH_STENCIL
;
633 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
634 r600_is_vertex_format_supported(format
)) {
635 retval
|= PIPE_BIND_VERTEX_BUFFER
;
638 if (usage
& PIPE_BIND_TRANSFER_READ
)
639 retval
|= PIPE_BIND_TRANSFER_READ
;
640 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
641 retval
|= PIPE_BIND_TRANSFER_WRITE
;
643 return retval
== usage
;
646 static void r600_emit_polygon_offset(struct r600_context
*rctx
, struct r600_atom
*a
)
648 struct radeon_winsys_cs
*cs
= rctx
->cs
;
649 struct r600_poly_offset_state
*state
= (struct r600_poly_offset_state
*)a
;
650 float offset_units
= state
->offset_units
;
651 float offset_scale
= state
->offset_scale
;
653 switch (state
->zs_format
) {
654 case PIPE_FORMAT_Z24X8_UNORM
:
655 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
656 offset_units
*= 2.0f
;
658 case PIPE_FORMAT_Z16_UNORM
:
659 offset_units
*= 4.0f
;
664 r600_write_context_reg_seq(cs
, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE
, 4);
665 r600_write_value(cs
, fui(offset_scale
));
666 r600_write_value(cs
, fui(offset_units
));
667 r600_write_value(cs
, fui(offset_scale
));
668 r600_write_value(cs
, fui(offset_units
));
671 static uint32_t r600_get_blend_control(const struct pipe_blend_state
*state
, unsigned i
)
673 int j
= state
->independent_blend_enable
? i
: 0;
675 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
676 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
677 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
679 unsigned eqA
= state
->rt
[j
].alpha_func
;
680 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
681 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
684 if (!state
->rt
[j
].blend_enable
)
687 bc
|= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
688 bc
|= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
689 bc
|= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
691 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
692 bc
|= S_028804_SEPARATE_ALPHA_BLEND(1);
693 bc
|= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
694 bc
|= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
695 bc
|= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
700 static void *r600_create_blend_state_mode(struct pipe_context
*ctx
,
701 const struct pipe_blend_state
*state
,
704 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
705 uint32_t color_control
= 0, target_mask
= 0;
706 struct r600_blend_state
*blend
= CALLOC_STRUCT(r600_blend_state
);
712 r600_init_command_buffer(&blend
->buffer
, 20);
713 r600_init_command_buffer(&blend
->buffer_no_blend
, 20);
715 /* R600 does not support per-MRT blends */
716 if (rctx
->family
> CHIP_R600
)
717 color_control
|= S_028808_PER_MRT_BLEND(1);
719 if (state
->logicop_enable
) {
720 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
722 color_control
|= (0xcc << 16);
724 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
725 if (state
->independent_blend_enable
) {
726 for (int i
= 0; i
< 8; i
++) {
727 if (state
->rt
[i
].blend_enable
) {
728 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
730 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
733 for (int i
= 0; i
< 8; i
++) {
734 if (state
->rt
[0].blend_enable
) {
735 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
737 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
742 color_control
|= S_028808_SPECIAL_OP(mode
);
744 color_control
|= S_028808_SPECIAL_OP(V_028808_DISABLE
);
746 /* only MRT0 has dual src blend */
747 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
748 blend
->cb_target_mask
= target_mask
;
749 blend
->cb_color_control
= color_control
;
750 blend
->cb_color_control_no_blend
= color_control
& C_028808_TARGET_BLEND_ENABLE
;
751 blend
->alpha_to_one
= state
->alpha_to_one
;
753 r600_store_context_reg(&blend
->buffer
, R_028D44_DB_ALPHA_TO_MASK
,
754 S_028D44_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
755 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
756 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
757 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
758 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
760 /* Copy over the registers set so far into buffer_no_blend. */
761 memcpy(blend
->buffer_no_blend
.buf
, blend
->buffer
.buf
, blend
->buffer
.num_dw
* 4);
762 blend
->buffer_no_blend
.num_dw
= blend
->buffer
.num_dw
;
764 /* Only add blend registers if blending is enabled. */
765 if (!G_028808_TARGET_BLEND_ENABLE(color_control
)) {
769 /* The first R600 does not support per-MRT blends */
770 r600_store_context_reg(&blend
->buffer
, R_028804_CB_BLEND_CONTROL
,
771 r600_get_blend_control(state
, 0));
773 if (rctx
->family
> CHIP_R600
) {
774 r600_store_context_reg_seq(&blend
->buffer
, R_028780_CB_BLEND0_CONTROL
, 8);
775 for (int i
= 0; i
< 8; i
++) {
776 r600_store_value(&blend
->buffer
, r600_get_blend_control(state
, i
));
782 static void *r600_create_blend_state(struct pipe_context
*ctx
,
783 const struct pipe_blend_state
*state
)
785 return r600_create_blend_state_mode(ctx
, state
, V_028808_SPECIAL_NORMAL
);
788 static void *r600_create_dsa_state(struct pipe_context
*ctx
,
789 const struct pipe_depth_stencil_alpha_state
*state
)
791 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
792 struct r600_dsa_state
*dsa
= CALLOC_STRUCT(r600_dsa_state
);
798 r600_init_command_buffer(&dsa
->buffer
, 3);
800 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
801 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
802 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
803 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
805 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
806 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
807 S_028800_ZFUNC(state
->depth
.func
);
810 if (state
->stencil
[0].enabled
) {
811 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
812 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
813 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
814 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
815 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
817 if (state
->stencil
[1].enabled
) {
818 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
819 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
820 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
821 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
822 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
827 alpha_test_control
= 0;
829 if (state
->alpha
.enabled
) {
830 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
831 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
832 alpha_ref
= fui(state
->alpha
.ref_value
);
834 dsa
->sx_alpha_test_control
= alpha_test_control
& 0xff;
835 dsa
->alpha_ref
= alpha_ref
;
837 r600_store_context_reg(&dsa
->buffer
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
841 static void *r600_create_rs_state(struct pipe_context
*ctx
,
842 const struct pipe_rasterizer_state
*state
)
844 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
845 unsigned tmp
, sc_mode_cntl
, spi_interp
;
846 float psize_min
, psize_max
;
847 struct r600_rasterizer_state
*rs
= CALLOC_STRUCT(r600_rasterizer_state
);
853 r600_init_command_buffer(&rs
->buffer
, 30);
855 rs
->flatshade
= state
->flatshade
;
856 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
857 rs
->two_side
= state
->light_twoside
;
858 rs
->clip_plane_enable
= state
->clip_plane_enable
;
859 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
860 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
861 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
862 rs
->pa_cl_clip_cntl
=
863 S_028810_PS_UCP_MODE(3) |
864 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
865 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
866 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
867 rs
->multisample_enable
= state
->multisample
;
870 rs
->offset_units
= state
->offset_units
;
871 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
872 rs
->offset_enable
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
874 if (state
->point_size_per_vertex
) {
875 psize_min
= util_get_min_point_size(state
);
878 /* Force the point size to be as if the vertex output was disabled. */
879 psize_min
= state
->point_size
;
880 psize_max
= state
->point_size
;
883 sc_mode_cntl
= S_028A4C_MSAA_ENABLE(state
->multisample
) |
884 S_028A4C_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
885 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
886 if (rctx
->chip_class
>= R700
) {
887 sc_mode_cntl
|= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
888 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
889 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state
->scissor
);
891 sc_mode_cntl
|= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
892 rs
->scissor_enable
= state
->scissor
;
895 spi_interp
= S_0286D4_FLAT_SHADE_ENA(1);
896 if (state
->sprite_coord_enable
) {
897 spi_interp
|= S_0286D4_PNT_SPRITE_ENA(1) |
898 S_0286D4_PNT_SPRITE_OVRD_X(2) |
899 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
900 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
901 S_0286D4_PNT_SPRITE_OVRD_W(1);
902 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
903 spi_interp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
907 r600_store_context_reg_seq(&rs
->buffer
, R_028A00_PA_SU_POINT_SIZE
, 3);
908 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
909 tmp
= r600_pack_float_12p4(state
->point_size
/2);
910 r600_store_value(&rs
->buffer
, /* R_028A00_PA_SU_POINT_SIZE */
911 S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
912 r600_store_value(&rs
->buffer
, /* R_028A04_PA_SU_POINT_MINMAX */
913 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
914 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
915 r600_store_value(&rs
->buffer
, /* R_028A08_PA_SU_LINE_CNTL */
916 S_028A08_WIDTH(r600_pack_float_12p4(state
->line_width
/2)));
918 r600_store_context_reg(&rs
->buffer
, R_0286D4_SPI_INTERP_CONTROL_0
, spi_interp
);
919 r600_store_context_reg(&rs
->buffer
, R_028A4C_PA_SC_MODE_CNTL
, sc_mode_cntl
);
920 r600_store_context_reg(&rs
->buffer
, R_028C08_PA_SU_VTX_CNTL
,
921 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
) |
922 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
923 r600_store_context_reg(&rs
->buffer
, R_028DFC_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
924 r600_store_context_reg(&rs
->buffer
, R_028814_PA_SU_SC_MODE_CNTL
,
925 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
926 S_028814_CULL_FRONT(state
->cull_face
& PIPE_FACE_FRONT
? 1 : 0) |
927 S_028814_CULL_BACK(state
->cull_face
& PIPE_FACE_BACK
? 1 : 0) |
928 S_028814_FACE(!state
->front_ccw
) |
929 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
930 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
931 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
932 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
933 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
934 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
935 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)));
936 r600_store_context_reg(&rs
->buffer
, R_028350_SX_MISC
, S_028350_MULTIPASS(state
->rasterizer_discard
));
940 static void *r600_create_sampler_state(struct pipe_context
*ctx
,
941 const struct pipe_sampler_state
*state
)
943 struct r600_pipe_sampler_state
*ss
= CALLOC_STRUCT(r600_pipe_sampler_state
);
944 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 4 : 0;
950 ss
->seamless_cube_map
= state
->seamless_cube_map
;
951 ss
->border_color_use
= sampler_state_needs_border_color(state
);
953 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
954 ss
->tex_sampler_words
[0] =
955 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
956 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
957 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
958 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
959 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
960 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
961 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
962 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
963 S_03C000_BORDER_COLOR_TYPE(ss
->border_color_use
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0);
964 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
965 ss
->tex_sampler_words
[1] =
966 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 6)) |
967 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 6)) |
968 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 6));
969 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
970 ss
->tex_sampler_words
[2] = S_03C008_TYPE(1);
972 if (ss
->border_color_use
) {
973 memcpy(&ss
->border_color
, &state
->border_color
, sizeof(state
->border_color
));
978 struct pipe_sampler_view
*
979 r600_create_sampler_view_custom(struct pipe_context
*ctx
,
980 struct pipe_resource
*texture
,
981 const struct pipe_sampler_view
*state
,
982 unsigned width_first_level
, unsigned height_first_level
)
984 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
985 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
986 unsigned format
, endian
;
987 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
988 unsigned char swizzle
[4], array_mode
= 0, tile_type
= 0;
989 unsigned width
, height
, depth
, offset_level
, last_level
;
994 /* initialize base object */
996 view
->base
.texture
= NULL
;
997 pipe_reference(NULL
, &texture
->reference
);
998 view
->base
.texture
= texture
;
999 view
->base
.reference
.count
= 1;
1000 view
->base
.context
= ctx
;
1002 swizzle
[0] = state
->swizzle_r
;
1003 swizzle
[1] = state
->swizzle_g
;
1004 swizzle
[2] = state
->swizzle_b
;
1005 swizzle
[3] = state
->swizzle_a
;
1007 format
= r600_translate_texformat(ctx
->screen
, state
->format
,
1009 &word4
, &yuv_format
);
1010 assert(format
!= ~0);
1016 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
) {
1017 if (!r600_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
1021 tmp
= tmp
->flushed_depth_texture
;
1024 endian
= r600_colorformat_endian_swap(format
);
1026 offset_level
= state
->u
.tex
.first_level
;
1027 last_level
= state
->u
.tex
.last_level
- offset_level
;
1028 width
= width_first_level
;
1029 height
= height_first_level
;
1030 depth
= tmp
->surface
.level
[offset_level
].npix_z
;
1031 pitch
= tmp
->surface
.level
[offset_level
].nblk_x
* util_format_get_blockwidth(state
->format
);
1032 tile_type
= tmp
->tile_type
;
1034 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
1036 depth
= texture
->array_size
;
1037 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
1038 depth
= texture
->array_size
;
1040 switch (tmp
->surface
.level
[offset_level
].mode
) {
1041 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1042 array_mode
= V_038000_ARRAY_LINEAR_ALIGNED
;
1044 case RADEON_SURF_MODE_1D
:
1045 array_mode
= V_038000_ARRAY_1D_TILED_THIN1
;
1047 case RADEON_SURF_MODE_2D
:
1048 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
1050 case RADEON_SURF_MODE_LINEAR
:
1052 array_mode
= V_038000_ARRAY_LINEAR_GENERAL
;
1056 view
->tex_resource
= &tmp
->resource
;
1057 view
->tex_resource_words
[0] = (S_038000_DIM(r600_tex_dim(texture
->target
, texture
->nr_samples
)) |
1058 S_038000_TILE_MODE(array_mode
) |
1059 S_038000_TILE_TYPE(tile_type
) |
1060 S_038000_PITCH((pitch
/ 8) - 1) |
1061 S_038000_TEX_WIDTH(width
- 1));
1062 view
->tex_resource_words
[1] = (S_038004_TEX_HEIGHT(height
- 1) |
1063 S_038004_TEX_DEPTH(depth
- 1) |
1064 S_038004_DATA_FORMAT(format
));
1065 view
->tex_resource_words
[2] = tmp
->surface
.level
[offset_level
].offset
>> 8;
1066 if (offset_level
>= tmp
->surface
.last_level
) {
1067 view
->tex_resource_words
[3] = tmp
->surface
.level
[offset_level
].offset
>> 8;
1069 view
->tex_resource_words
[3] = tmp
->surface
.level
[offset_level
+ 1].offset
>> 8;
1071 view
->tex_resource_words
[4] = (word4
|
1072 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE
) |
1073 S_038010_REQUEST_SIZE(1) |
1074 S_038010_ENDIAN_SWAP(endian
) |
1075 S_038010_BASE_LEVEL(0));
1076 view
->tex_resource_words
[5] = (S_038014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
1077 S_038014_LAST_ARRAY(state
->u
.tex
.last_layer
));
1078 if (texture
->nr_samples
> 1) {
1079 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1080 view
->tex_resource_words
[5] |= S_038014_LAST_LEVEL(util_logbase2(texture
->nr_samples
));
1082 view
->tex_resource_words
[5] |= S_038014_LAST_LEVEL(last_level
);
1084 view
->tex_resource_words
[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE
) |
1085 S_038018_MAX_ANISO(4 /* max 16 samples */));
1089 static struct pipe_sampler_view
*
1090 r600_create_sampler_view(struct pipe_context
*ctx
,
1091 struct pipe_resource
*tex
,
1092 const struct pipe_sampler_view
*state
)
1094 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1096 return r600_create_sampler_view_custom(ctx
, tex
, state
,
1097 rtex
->surface
.level
[state
->u
.tex
.first_level
].npix_x
,
1098 rtex
->surface
.level
[state
->u
.tex
.first_level
].npix_y
);
1101 static void r600_emit_clip_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1103 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1104 struct pipe_clip_state
*state
= &rctx
->clip_state
.state
;
1106 r600_write_context_reg_seq(cs
, R_028E20_PA_CL_UCP0_X
, 6*4);
1107 r600_write_array(cs
, 6*4, (unsigned*)state
);
1110 static void r600_set_polygon_stipple(struct pipe_context
*ctx
,
1111 const struct pipe_poly_stipple
*state
)
1115 static void r600_emit_scissor_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1117 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1118 struct pipe_scissor_state
*state
= &rctx
->scissor
.scissor
;
1120 if (rctx
->chip_class
!= R600
|| rctx
->scissor
.enable
) {
1121 r600_write_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 2);
1122 r600_write_value(cs
, S_028240_TL_X(state
->minx
) | S_028240_TL_Y(state
->miny
) |
1123 S_028240_WINDOW_OFFSET_DISABLE(1));
1124 r600_write_value(cs
, S_028244_BR_X(state
->maxx
) | S_028244_BR_Y(state
->maxy
));
1126 r600_write_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 2);
1127 r600_write_value(cs
, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1128 S_028240_WINDOW_OFFSET_DISABLE(1));
1129 r600_write_value(cs
, S_028244_BR_X(8192) | S_028244_BR_Y(8192));
1133 static void r600_set_scissor_state(struct pipe_context
*ctx
,
1134 const struct pipe_scissor_state
*state
)
1136 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1138 rctx
->scissor
.scissor
= *state
;
1140 if (rctx
->chip_class
== R600
&& !rctx
->scissor
.enable
)
1143 rctx
->scissor
.atom
.dirty
= true;
1146 static struct r600_resource
*r600_buffer_create_helper(struct r600_screen
*rscreen
,
1147 unsigned size
, unsigned alignment
)
1149 struct pipe_resource buffer
;
1151 memset(&buffer
, 0, sizeof buffer
);
1152 buffer
.target
= PIPE_BUFFER
;
1153 buffer
.format
= PIPE_FORMAT_R8_UNORM
;
1154 buffer
.bind
= PIPE_BIND_CUSTOM
;
1155 buffer
.usage
= PIPE_USAGE_STATIC
;
1157 buffer
.width0
= size
;
1160 buffer
.array_size
= 1;
1162 return (struct r600_resource
*)
1163 r600_buffer_create(&rscreen
->screen
, &buffer
, alignment
);
1166 static void r600_init_color_surface(struct r600_context
*rctx
,
1167 struct r600_surface
*surf
,
1168 bool force_cmask_fmask
)
1170 struct r600_screen
*rscreen
= rctx
->screen
;
1171 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1172 unsigned level
= surf
->base
.u
.tex
.level
;
1173 unsigned pitch
, slice
;
1174 unsigned color_info
;
1175 unsigned format
, swap
, ntype
, endian
;
1177 const struct util_format_description
*desc
;
1179 bool blend_bypass
= 0, blend_clamp
= 1;
1181 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
1182 r600_init_flushed_depth_texture(&rctx
->context
, surf
->base
.texture
, NULL
);
1183 rtex
= rtex
->flushed_depth_texture
;
1187 offset
= rtex
->surface
.level
[level
].offset
;
1188 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1189 offset
+= rtex
->surface
.level
[level
].slice_size
*
1190 surf
->base
.u
.tex
.first_layer
;
1192 pitch
= rtex
->surface
.level
[level
].nblk_x
/ 8 - 1;
1193 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1198 switch (rtex
->surface
.level
[level
].mode
) {
1199 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1200 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED
);
1202 case RADEON_SURF_MODE_1D
:
1203 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1
);
1205 case RADEON_SURF_MODE_2D
:
1206 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1
);
1208 case RADEON_SURF_MODE_LINEAR
:
1210 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL
);
1214 desc
= util_format_description(surf
->base
.format
);
1216 for (i
= 0; i
< 4; i
++) {
1217 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1222 ntype
= V_0280A0_NUMBER_UNORM
;
1223 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1224 ntype
= V_0280A0_NUMBER_SRGB
;
1225 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1226 if (desc
->channel
[i
].normalized
)
1227 ntype
= V_0280A0_NUMBER_SNORM
;
1228 else if (desc
->channel
[i
].pure_integer
)
1229 ntype
= V_0280A0_NUMBER_SINT
;
1230 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1231 if (desc
->channel
[i
].normalized
)
1232 ntype
= V_0280A0_NUMBER_UNORM
;
1233 else if (desc
->channel
[i
].pure_integer
)
1234 ntype
= V_0280A0_NUMBER_UINT
;
1237 format
= r600_translate_colorformat(surf
->base
.format
);
1238 assert(format
!= ~0);
1240 swap
= r600_translate_colorswap(surf
->base
.format
);
1243 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1244 endian
= ENDIAN_NONE
;
1246 endian
= r600_colorformat_endian_swap(format
);
1249 /* set blend bypass according to docs if SINT/UINT or
1250 8/24 COLOR variants */
1251 if (ntype
== V_0280A0_NUMBER_UINT
|| ntype
== V_0280A0_NUMBER_SINT
||
1252 format
== V_0280A0_COLOR_8_24
|| format
== V_0280A0_COLOR_24_8
||
1253 format
== V_0280A0_COLOR_X24_8_32_FLOAT
) {
1258 surf
->alphatest_bypass
= ntype
== V_0280A0_NUMBER_UINT
|| ntype
== V_0280A0_NUMBER_SINT
;
1260 color_info
|= S_0280A0_FORMAT(format
) |
1261 S_0280A0_COMP_SWAP(swap
) |
1262 S_0280A0_BLEND_BYPASS(blend_bypass
) |
1263 S_0280A0_BLEND_CLAMP(blend_clamp
) |
1264 S_0280A0_NUMBER_TYPE(ntype
) |
1265 S_0280A0_ENDIAN(endian
);
1267 /* EXPORT_NORM is an optimzation that can be enabled for better
1268 * performance in certain cases
1270 if (rctx
->chip_class
== R600
) {
1271 /* EXPORT_NORM can be enabled if:
1272 * - 11-bit or smaller UNORM/SNORM/SRGB
1273 * - BLEND_CLAMP is enabled
1274 * - BLEND_FLOAT32 is disabled
1276 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1277 (desc
->channel
[i
].size
< 12 &&
1278 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1279 ntype
!= V_0280A0_NUMBER_UINT
&&
1280 ntype
!= V_0280A0_NUMBER_SINT
) &&
1281 G_0280A0_BLEND_CLAMP(color_info
) &&
1282 !G_0280A0_BLEND_FLOAT32(color_info
)) {
1283 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
1284 surf
->export_16bpc
= true;
1287 /* EXPORT_NORM can be enabled if:
1288 * - 11-bit or smaller UNORM/SNORM/SRGB
1289 * - 16-bit or smaller FLOAT
1291 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1292 ((desc
->channel
[i
].size
< 12 &&
1293 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1294 ntype
!= V_0280A0_NUMBER_UINT
&& ntype
!= V_0280A0_NUMBER_SINT
) ||
1295 (desc
->channel
[i
].size
< 17 &&
1296 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
1297 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
1298 surf
->export_16bpc
= true;
1302 /* These might not always be initialized to zero. */
1303 surf
->cb_color_base
= offset
>> 8;
1304 surf
->cb_color_size
= S_028060_PITCH_TILE_MAX(pitch
) |
1305 S_028060_SLICE_TILE_MAX(slice
);
1306 surf
->cb_color_fmask
= surf
->cb_color_base
;
1307 surf
->cb_color_cmask
= surf
->cb_color_base
;
1308 surf
->cb_color_mask
= 0;
1310 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
,
1311 &rtex
->resource
.b
.b
);
1312 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
,
1313 &rtex
->resource
.b
.b
);
1315 if (rtex
->cmask_size
) {
1316 surf
->cb_color_cmask
= rtex
->cmask_offset
>> 8;
1317 surf
->cb_color_mask
|= S_028100_CMASK_BLOCK_MAX(rtex
->cmask_slice_tile_max
);
1319 if (rtex
->fmask_size
) {
1320 color_info
|= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE
);
1321 surf
->cb_color_fmask
= rtex
->fmask_offset
>> 8;
1322 surf
->cb_color_mask
|= S_028100_FMASK_TILE_MAX(slice
);
1323 } else { /* cmask only */
1324 color_info
|= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE
);
1326 } else if (force_cmask_fmask
) {
1327 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1329 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1330 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1331 * because it's not an MSAA buffer.
1333 struct r600_cmask_info cmask
;
1334 struct r600_fmask_info fmask
;
1336 r600_texture_get_cmask_info(rscreen
, rtex
, &cmask
);
1337 r600_texture_get_fmask_info(rscreen
, rtex
, 8, &fmask
);
1340 if (!rctx
->dummy_cmask
||
1341 rctx
->dummy_cmask
->buf
->size
< cmask
.size
||
1342 rctx
->dummy_cmask
->buf
->alignment
% cmask
.alignment
!= 0) {
1343 struct pipe_transfer
*transfer
;
1346 pipe_resource_reference((struct pipe_resource
**)&rctx
->dummy_cmask
, NULL
);
1347 rctx
->dummy_cmask
= r600_buffer_create_helper(rscreen
, cmask
.size
, cmask
.alignment
);
1349 /* Set the contents to 0xCC. */
1350 ptr
= pipe_buffer_map(&rctx
->context
, &rctx
->dummy_cmask
->b
.b
, PIPE_TRANSFER_WRITE
, &transfer
);
1351 memset(ptr
, 0xCC, cmask
.size
);
1352 pipe_buffer_unmap(&rctx
->context
, transfer
);
1354 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
,
1355 &rctx
->dummy_cmask
->b
.b
);
1358 if (!rctx
->dummy_fmask
||
1359 rctx
->dummy_fmask
->buf
->size
< fmask
.size
||
1360 rctx
->dummy_fmask
->buf
->alignment
% fmask
.alignment
!= 0) {
1361 pipe_resource_reference((struct pipe_resource
**)&rctx
->dummy_fmask
, NULL
);
1362 rctx
->dummy_fmask
= r600_buffer_create_helper(rscreen
, fmask
.size
, fmask
.alignment
);
1365 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
,
1366 &rctx
->dummy_fmask
->b
.b
);
1368 /* Init the registers. */
1369 color_info
|= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE
);
1370 surf
->cb_color_cmask
= 0;
1371 surf
->cb_color_fmask
= 0;
1372 surf
->cb_color_mask
= S_028100_CMASK_BLOCK_MAX(cmask
.slice_tile_max
) |
1373 S_028100_FMASK_TILE_MAX(slice
);
1376 surf
->cb_color_info
= color_info
;
1378 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1379 surf
->cb_color_view
= 0;
1381 surf
->cb_color_view
= S_028080_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1382 S_028080_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1385 surf
->color_initialized
= true;
1388 static void r600_init_depth_surface(struct r600_context
*rctx
,
1389 struct r600_surface
*surf
)
1391 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1392 unsigned level
, pitch
, slice
, format
, offset
, array_mode
;
1394 level
= surf
->base
.u
.tex
.level
;
1395 offset
= rtex
->surface
.level
[level
].offset
;
1396 pitch
= rtex
->surface
.level
[level
].nblk_x
/ 8 - 1;
1397 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1401 switch (rtex
->surface
.level
[level
].mode
) {
1402 case RADEON_SURF_MODE_2D
:
1403 array_mode
= V_0280A0_ARRAY_2D_TILED_THIN1
;
1405 case RADEON_SURF_MODE_1D
:
1406 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1407 case RADEON_SURF_MODE_LINEAR
:
1409 array_mode
= V_0280A0_ARRAY_1D_TILED_THIN1
;
1413 format
= r600_translate_dbformat(surf
->base
.format
);
1414 assert(format
!= ~0);
1416 surf
->db_depth_info
= S_028010_ARRAY_MODE(array_mode
) | S_028010_FORMAT(format
);
1417 surf
->db_depth_base
= offset
>> 8;
1418 surf
->db_depth_view
= S_028004_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1419 S_028004_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1420 surf
->db_depth_size
= S_028000_PITCH_TILE_MAX(pitch
) | S_028000_SLICE_TILE_MAX(slice
);
1421 surf
->db_prefetch_limit
= (rtex
->surface
.level
[level
].nblk_y
/ 8) - 1;
1423 switch (surf
->base
.format
) {
1424 case PIPE_FORMAT_Z24X8_UNORM
:
1425 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1426 surf
->pa_su_poly_offset_db_fmt_cntl
=
1427 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1429 case PIPE_FORMAT_Z32_FLOAT
:
1430 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1431 surf
->pa_su_poly_offset_db_fmt_cntl
=
1432 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1433 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1435 case PIPE_FORMAT_Z16_UNORM
:
1436 surf
->pa_su_poly_offset_db_fmt_cntl
=
1437 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1442 surf
->depth_initialized
= true;
1445 static void r600_set_framebuffer_state(struct pipe_context
*ctx
,
1446 const struct pipe_framebuffer_state
*state
)
1448 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1449 struct r600_surface
*surf
;
1450 struct r600_texture
*rtex
;
1453 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1454 rctx
->flags
|= R600_CONTEXT_CB_FLUSH
;
1456 if (rctx
->chip_class
>= R700
&&
1457 rctx
->framebuffer
.state
.cbufs
[0]->texture
->nr_samples
> 1) {
1458 rctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV_CB_META
;
1461 if (rctx
->framebuffer
.state
.zsbuf
) {
1462 rctx
->flags
|= R600_CONTEXT_DB_FLUSH
;
1465 if (rctx
->chip_class
== R600
) {
1466 rctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV
;
1469 /* Set the new state. */
1470 util_copy_framebuffer_state(&rctx
->framebuffer
.state
, state
);
1472 rctx
->framebuffer
.export_16bpc
= state
->nr_cbufs
!= 0;
1473 rctx
->framebuffer
.cb0_is_integer
= state
->nr_cbufs
&&
1474 util_format_is_pure_integer(state
->cbufs
[0]->format
);
1475 rctx
->framebuffer
.compressed_cb_mask
= 0;
1476 rctx
->framebuffer
.is_msaa_resolve
= state
->nr_cbufs
== 2 &&
1477 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
1478 state
->cbufs
[1]->texture
->nr_samples
<= 1;
1480 if (state
->nr_cbufs
)
1481 rctx
->framebuffer
.nr_samples
= state
->cbufs
[0]->texture
->nr_samples
;
1482 else if (state
->zsbuf
)
1483 rctx
->framebuffer
.nr_samples
= state
->zsbuf
->texture
->nr_samples
;
1485 rctx
->framebuffer
.nr_samples
= 0;
1488 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
1489 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1490 bool force_cmask_fmask
= rctx
->chip_class
== R600
&&
1491 rctx
->framebuffer
.is_msaa_resolve
&&
1494 surf
= (struct r600_surface
*)state
->cbufs
[i
];
1495 rtex
= (struct r600_texture
*)surf
->base
.texture
;
1497 if (!surf
->color_initialized
|| force_cmask_fmask
) {
1498 r600_init_color_surface(rctx
, surf
, force_cmask_fmask
);
1499 if (force_cmask_fmask
) {
1500 /* re-initialize later without compression */
1501 surf
->color_initialized
= false;
1505 if (!surf
->export_16bpc
) {
1506 rctx
->framebuffer
.export_16bpc
= false;
1509 if (rtex
->fmask_size
&& rtex
->cmask_size
) {
1510 rctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
1514 /* Update alpha-test state dependencies.
1515 * Alpha-test is done on the first colorbuffer only. */
1516 if (state
->nr_cbufs
) {
1517 surf
= (struct r600_surface
*)state
->cbufs
[0];
1518 if (rctx
->alphatest_state
.bypass
!= surf
->alphatest_bypass
) {
1519 rctx
->alphatest_state
.bypass
= surf
->alphatest_bypass
;
1520 rctx
->alphatest_state
.atom
.dirty
= true;
1526 surf
= (struct r600_surface
*)state
->zsbuf
;
1528 if (!surf
->depth_initialized
) {
1529 r600_init_depth_surface(rctx
, surf
);
1532 if (state
->zsbuf
->format
!= rctx
->poly_offset_state
.zs_format
) {
1533 rctx
->poly_offset_state
.zs_format
= state
->zsbuf
->format
;
1534 rctx
->poly_offset_state
.atom
.dirty
= true;
1538 if (rctx
->cb_misc_state
.nr_cbufs
!= state
->nr_cbufs
) {
1539 rctx
->cb_misc_state
.nr_cbufs
= state
->nr_cbufs
;
1540 rctx
->cb_misc_state
.atom
.dirty
= true;
1543 if (state
->nr_cbufs
== 0 && rctx
->alphatest_state
.bypass
) {
1544 rctx
->alphatest_state
.bypass
= false;
1545 rctx
->alphatest_state
.atom
.dirty
= true;
1548 r600_update_db_shader_control(rctx
);
1550 /* Calculate the CS size. */
1551 rctx
->framebuffer
.atom
.num_dw
=
1552 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1554 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1555 rctx
->framebuffer
.atom
.num_dw
+= 6 * (2 + rctx
->framebuffer
.state
.nr_cbufs
);
1556 rctx
->framebuffer
.atom
.num_dw
+= 6 * rctx
->framebuffer
.state
.nr_cbufs
; /* relocs */
1559 if (rctx
->framebuffer
.state
.zsbuf
) {
1560 rctx
->framebuffer
.atom
.num_dw
+= 16;
1561 } else if (rctx
->screen
->info
.drm_minor
>= 18) {
1562 rctx
->framebuffer
.atom
.num_dw
+= 3;
1564 if (rctx
->family
> CHIP_R600
&& rctx
->family
< CHIP_RV770
) {
1565 rctx
->framebuffer
.atom
.num_dw
+= 2;
1568 rctx
->framebuffer
.atom
.dirty
= true;
1571 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1572 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1573 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1574 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1575 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1577 static void r600_emit_msaa_state(struct r600_context
*rctx
, int nr_samples
)
1579 static uint32_t sample_locs_2x
[] = {
1580 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1581 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1583 static unsigned max_dist_2x
= 4;
1584 static uint32_t sample_locs_4x
[] = {
1585 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1586 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1588 static unsigned max_dist_4x
= 6;
1589 static uint32_t sample_locs_8x
[] = {
1590 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1591 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1593 static unsigned max_dist_8x
= 8;
1595 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1596 unsigned max_dist
= 0;
1598 if (rctx
->family
== CHIP_R600
) {
1599 switch (nr_samples
) {
1604 r600_write_config_reg(cs
, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S
, sample_locs_2x
[0]);
1605 max_dist
= max_dist_2x
;
1608 r600_write_config_reg(cs
, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S
, sample_locs_4x
[0]);
1609 max_dist
= max_dist_4x
;
1612 r600_write_config_reg_seq(cs
, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0
, 2);
1613 r600_write_value(cs
, sample_locs_8x
[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1614 r600_write_value(cs
, sample_locs_8x
[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1615 max_dist
= max_dist_8x
;
1619 switch (nr_samples
) {
1621 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1622 r600_write_value(cs
, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1623 r600_write_value(cs
, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1627 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1628 r600_write_value(cs
, sample_locs_2x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1629 r600_write_value(cs
, sample_locs_2x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1630 max_dist
= max_dist_2x
;
1633 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1634 r600_write_value(cs
, sample_locs_4x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1635 r600_write_value(cs
, sample_locs_4x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1636 max_dist
= max_dist_4x
;
1639 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1640 r600_write_value(cs
, sample_locs_8x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1641 r600_write_value(cs
, sample_locs_8x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1642 max_dist
= max_dist_8x
;
1647 if (nr_samples
> 1) {
1648 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1649 r600_write_value(cs
, S_028C00_LAST_PIXEL(1) |
1650 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1651 r600_write_value(cs
, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples
)) |
1652 S_028C04_MAX_SAMPLE_DIST(max_dist
)); /* R_028C04_PA_SC_AA_CONFIG */
1654 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1655 r600_write_value(cs
, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1656 r600_write_value(cs
, 0); /* R_028C04_PA_SC_AA_CONFIG */
1660 static void r600_emit_framebuffer_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1662 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1663 struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
.state
;
1664 unsigned nr_cbufs
= state
->nr_cbufs
;
1665 struct r600_surface
**cb
= (struct r600_surface
**)&state
->cbufs
[0];
1666 unsigned i
, sbu
= 0;
1669 r600_write_context_reg_seq(cs
, R_0280A0_CB_COLOR0_INFO
, 8);
1670 for (i
= 0; i
< nr_cbufs
; i
++) {
1671 r600_write_value(cs
, cb
[i
]->cb_color_info
);
1673 /* set CB_COLOR1_INFO for possible dual-src blending */
1675 r600_write_value(cs
, cb
[0]->cb_color_info
);
1678 for (; i
< 8; i
++) {
1679 r600_write_value(cs
, 0);
1684 r600_write_context_reg_seq(cs
, R_028040_CB_COLOR0_BASE
, nr_cbufs
);
1685 for (i
= 0; i
< nr_cbufs
; i
++) {
1686 r600_write_value(cs
, cb
[i
]->cb_color_base
);
1690 for (i
= 0; i
< nr_cbufs
; i
++) {
1691 unsigned reloc
= r600_context_bo_reloc(rctx
,
1692 (struct r600_resource
*)cb
[i
]->base
.texture
,
1693 RADEON_USAGE_READWRITE
);
1694 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1695 r600_write_value(cs
, reloc
);
1698 r600_write_context_reg_seq(cs
, R_028060_CB_COLOR0_SIZE
, nr_cbufs
);
1699 for (i
= 0; i
< nr_cbufs
; i
++) {
1700 r600_write_value(cs
, cb
[i
]->cb_color_size
);
1703 r600_write_context_reg_seq(cs
, R_028080_CB_COLOR0_VIEW
, nr_cbufs
);
1704 for (i
= 0; i
< nr_cbufs
; i
++) {
1705 r600_write_value(cs
, cb
[i
]->cb_color_view
);
1708 r600_write_context_reg_seq(cs
, R_028100_CB_COLOR0_MASK
, nr_cbufs
);
1709 for (i
= 0; i
< nr_cbufs
; i
++) {
1710 r600_write_value(cs
, cb
[i
]->cb_color_mask
);
1714 r600_write_context_reg_seq(cs
, R_0280E0_CB_COLOR0_FRAG
, nr_cbufs
);
1715 for (i
= 0; i
< nr_cbufs
; i
++) {
1716 r600_write_value(cs
, cb
[i
]->cb_color_fmask
);
1719 for (i
= 0; i
< nr_cbufs
; i
++) {
1720 unsigned reloc
= r600_context_bo_reloc(rctx
,
1721 cb
[i
]->cb_buffer_fmask
,
1722 RADEON_USAGE_READWRITE
);
1723 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1724 r600_write_value(cs
, reloc
);
1728 r600_write_context_reg_seq(cs
, R_0280C0_CB_COLOR0_TILE
, nr_cbufs
);
1729 for (i
= 0; i
< nr_cbufs
; i
++) {
1730 r600_write_value(cs
, cb
[i
]->cb_color_cmask
);
1733 for (i
= 0; i
< nr_cbufs
; i
++) {
1734 unsigned reloc
= r600_context_bo_reloc(rctx
,
1735 cb
[i
]->cb_buffer_cmask
,
1736 RADEON_USAGE_READWRITE
);
1737 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1738 r600_write_value(cs
, reloc
);
1741 sbu
|= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs
);
1746 struct r600_surface
*surf
= (struct r600_surface
*)state
->zsbuf
;
1747 unsigned reloc
= r600_context_bo_reloc(rctx
,
1748 (struct r600_resource
*)state
->zsbuf
->texture
,
1749 RADEON_USAGE_READWRITE
);
1751 r600_write_context_reg(cs
, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1752 surf
->pa_su_poly_offset_db_fmt_cntl
);
1754 r600_write_context_reg_seq(cs
, R_028000_DB_DEPTH_SIZE
, 2);
1755 r600_write_value(cs
, surf
->db_depth_size
); /* R_028000_DB_DEPTH_SIZE */
1756 r600_write_value(cs
, surf
->db_depth_view
); /* R_028004_DB_DEPTH_VIEW */
1757 r600_write_context_reg_seq(cs
, R_02800C_DB_DEPTH_BASE
, 2);
1758 r600_write_value(cs
, surf
->db_depth_base
); /* R_02800C_DB_DEPTH_BASE */
1759 r600_write_value(cs
, surf
->db_depth_info
); /* R_028010_DB_DEPTH_INFO */
1761 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1762 r600_write_value(cs
, reloc
);
1764 r600_write_context_reg(cs
, R_028D34_DB_PREFETCH_LIMIT
, surf
->db_prefetch_limit
);
1766 sbu
|= SURFACE_BASE_UPDATE_DEPTH
;
1767 } else if (rctx
->screen
->info
.drm_minor
>= 18) {
1768 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1769 * Older kernels are out of luck. */
1770 r600_write_context_reg(cs
, R_028010_DB_DEPTH_INFO
, S_028010_FORMAT(V_028010_DEPTH_INVALID
));
1773 /* SURFACE_BASE_UPDATE */
1774 if (rctx
->family
> CHIP_R600
&& rctx
->family
< CHIP_RV770
&& sbu
) {
1775 r600_write_value(cs
, PKT3(PKT3_SURFACE_BASE_UPDATE
, 0, 0));
1776 r600_write_value(cs
, sbu
);
1779 /* Framebuffer dimensions. */
1780 r600_write_context_reg_seq(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, 2);
1781 r600_write_value(cs
, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1782 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1783 r600_write_value(cs
, S_028244_BR_X(state
->width
) |
1784 S_028244_BR_Y(state
->height
)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1786 if (rctx
->framebuffer
.is_msaa_resolve
) {
1787 r600_write_context_reg(cs
, R_0287A0_CB_SHADER_CONTROL
, 1);
1789 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1790 * will assure that the alpha-test will work even if there is
1791 * no colorbuffer bound. */
1792 r600_write_context_reg(cs
, R_0287A0_CB_SHADER_CONTROL
,
1793 (1ull << MAX2(nr_cbufs
, 1)) - 1);
1796 r600_emit_msaa_state(rctx
, rctx
->framebuffer
.nr_samples
);
1799 static void r600_emit_cb_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1801 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1802 struct r600_cb_misc_state
*a
= (struct r600_cb_misc_state
*)atom
;
1804 if (G_028808_SPECIAL_OP(a
->cb_color_control
) == V_028808_SPECIAL_RESOLVE_BOX
) {
1805 r600_write_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1806 if (rctx
->chip_class
== R600
) {
1807 r600_write_value(cs
, 0xff); /* R_028238_CB_TARGET_MASK */
1808 r600_write_value(cs
, 0xff); /* R_02823C_CB_SHADER_MASK */
1810 r600_write_value(cs
, 0xf); /* R_028238_CB_TARGET_MASK */
1811 r600_write_value(cs
, 0xf); /* R_02823C_CB_SHADER_MASK */
1813 r600_write_context_reg(cs
, R_028808_CB_COLOR_CONTROL
, a
->cb_color_control
);
1815 unsigned fb_colormask
= (1ULL << ((unsigned)a
->nr_cbufs
* 4)) - 1;
1816 unsigned ps_colormask
= (1ULL << ((unsigned)a
->nr_ps_color_outputs
* 4)) - 1;
1817 unsigned multiwrite
= a
->multiwrite
&& a
->nr_cbufs
> 1;
1819 r600_write_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1820 r600_write_value(cs
, a
->blend_colormask
& fb_colormask
); /* R_028238_CB_TARGET_MASK */
1821 /* Always enable the first color output to make sure alpha-test works even without one. */
1822 r600_write_value(cs
, 0xf | (multiwrite
? fb_colormask
: ps_colormask
)); /* R_02823C_CB_SHADER_MASK */
1823 r600_write_context_reg(cs
, R_028808_CB_COLOR_CONTROL
,
1824 a
->cb_color_control
|
1825 S_028808_MULTIWRITE_ENABLE(multiwrite
));
1829 static void r600_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1831 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1832 struct r600_db_misc_state
*a
= (struct r600_db_misc_state
*)atom
;
1833 unsigned db_render_control
= 0;
1834 unsigned db_render_override
=
1835 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE
) |
1836 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE
) |
1837 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE
);
1839 if (a
->occlusion_query_enabled
) {
1840 if (rctx
->chip_class
>= R700
) {
1841 db_render_control
|= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1843 db_render_override
|= S_028D10_NOOP_CULL_DISABLE(1);
1845 if (a
->flush_depthstencil_through_cb
) {
1846 assert(a
->copy_depth
|| a
->copy_stencil
);
1848 db_render_control
|= S_028D0C_DEPTH_COPY_ENABLE(a
->copy_depth
) |
1849 S_028D0C_STENCIL_COPY_ENABLE(a
->copy_stencil
) |
1850 S_028D0C_COPY_CENTROID(1) |
1851 S_028D0C_COPY_SAMPLE(a
->copy_sample
);
1854 r600_write_context_reg_seq(cs
, R_028D0C_DB_RENDER_CONTROL
, 2);
1855 r600_write_value(cs
, db_render_control
); /* R_028D0C_DB_RENDER_CONTROL */
1856 r600_write_value(cs
, db_render_override
); /* R_028D10_DB_RENDER_OVERRIDE */
1857 r600_write_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
, a
->db_shader_control
);
1860 static void r600_emit_config_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1862 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1863 struct r600_config_state
*a
= (struct r600_config_state
*)atom
;
1865 r600_write_config_reg(cs
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, a
->sq_gpr_resource_mgmt_1
);
1868 static void r600_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1870 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1871 uint32_t dirty_mask
= rctx
->vertex_buffer_state
.dirty_mask
;
1873 while (dirty_mask
) {
1874 struct pipe_vertex_buffer
*vb
;
1875 struct r600_resource
*rbuffer
;
1877 unsigned buffer_index
= u_bit_scan(&dirty_mask
);
1879 vb
= &rctx
->vertex_buffer_state
.vb
[buffer_index
];
1880 rbuffer
= (struct r600_resource
*)vb
->buffer
;
1883 offset
= vb
->buffer_offset
;
1885 /* fetch resources start at index 320 */
1886 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1887 r600_write_value(cs
, (320 + buffer_index
) * 7);
1888 r600_write_value(cs
, offset
); /* RESOURCEi_WORD0 */
1889 r600_write_value(cs
, rbuffer
->buf
->size
- offset
- 1); /* RESOURCEi_WORD1 */
1890 r600_write_value(cs
, /* RESOURCEi_WORD2 */
1891 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1892 S_038008_STRIDE(vb
->stride
));
1893 r600_write_value(cs
, 0); /* RESOURCEi_WORD3 */
1894 r600_write_value(cs
, 0); /* RESOURCEi_WORD4 */
1895 r600_write_value(cs
, 0); /* RESOURCEi_WORD5 */
1896 r600_write_value(cs
, 0xc0000000); /* RESOURCEi_WORD6 */
1898 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1899 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
1903 static void r600_emit_constant_buffers(struct r600_context
*rctx
,
1904 struct r600_constbuf_state
*state
,
1905 unsigned buffer_id_base
,
1906 unsigned reg_alu_constbuf_size
,
1907 unsigned reg_alu_const_cache
)
1909 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1910 uint32_t dirty_mask
= state
->dirty_mask
;
1912 while (dirty_mask
) {
1913 struct pipe_constant_buffer
*cb
;
1914 struct r600_resource
*rbuffer
;
1916 unsigned buffer_index
= ffs(dirty_mask
) - 1;
1918 cb
= &state
->cb
[buffer_index
];
1919 rbuffer
= (struct r600_resource
*)cb
->buffer
;
1922 offset
= cb
->buffer_offset
;
1924 r600_write_context_reg(cs
, reg_alu_constbuf_size
+ buffer_index
* 4,
1925 ALIGN_DIVUP(cb
->buffer_size
>> 4, 16));
1926 r600_write_context_reg(cs
, reg_alu_const_cache
+ buffer_index
* 4, offset
>> 8);
1928 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1929 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
1931 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1932 r600_write_value(cs
, (buffer_id_base
+ buffer_index
) * 7);
1933 r600_write_value(cs
, offset
); /* RESOURCEi_WORD0 */
1934 r600_write_value(cs
, rbuffer
->buf
->size
- offset
- 1); /* RESOURCEi_WORD1 */
1935 r600_write_value(cs
, /* RESOURCEi_WORD2 */
1936 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1937 S_038008_STRIDE(16));
1938 r600_write_value(cs
, 0); /* RESOURCEi_WORD3 */
1939 r600_write_value(cs
, 0); /* RESOURCEi_WORD4 */
1940 r600_write_value(cs
, 0); /* RESOURCEi_WORD5 */
1941 r600_write_value(cs
, 0xc0000000); /* RESOURCEi_WORD6 */
1943 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1944 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
1946 dirty_mask
&= ~(1 << buffer_index
);
1948 state
->dirty_mask
= 0;
1951 static void r600_emit_vs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1953 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
], 160,
1954 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
1955 R_028980_ALU_CONST_CACHE_VS_0
);
1958 static void r600_emit_gs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1960 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
], 336,
1961 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
,
1962 R_0289C0_ALU_CONST_CACHE_GS_0
);
1965 static void r600_emit_ps_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1967 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
], 0,
1968 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
1969 R_028940_ALU_CONST_CACHE_PS_0
);
1972 static void r600_emit_sampler_views(struct r600_context
*rctx
,
1973 struct r600_samplerview_state
*state
,
1974 unsigned resource_id_base
)
1976 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1977 uint32_t dirty_mask
= state
->dirty_mask
;
1979 while (dirty_mask
) {
1980 struct r600_pipe_sampler_view
*rview
;
1981 unsigned resource_index
= u_bit_scan(&dirty_mask
);
1984 rview
= state
->views
[resource_index
];
1987 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1988 r600_write_value(cs
, (resource_id_base
+ resource_index
) * 7);
1989 r600_write_array(cs
, 7, rview
->tex_resource_words
);
1991 reloc
= r600_context_bo_reloc(rctx
, rview
->tex_resource
,
1993 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1994 r600_write_value(cs
, reloc
);
1995 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1996 r600_write_value(cs
, reloc
);
1998 state
->dirty_mask
= 0;
2008 static void r600_emit_vs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2010 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
, 160 + R600_MAX_CONST_BUFFERS
);
2013 static void r600_emit_gs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2015 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
, 336 + R600_MAX_CONST_BUFFERS
);
2018 static void r600_emit_ps_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2020 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
, R600_MAX_CONST_BUFFERS
);
2023 static void r600_emit_sampler_states(struct r600_context
*rctx
,
2024 struct r600_textures_info
*texinfo
,
2025 unsigned resource_id_base
,
2026 unsigned border_color_reg
)
2028 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2029 uint32_t dirty_mask
= texinfo
->states
.dirty_mask
;
2031 while (dirty_mask
) {
2032 struct r600_pipe_sampler_state
*rstate
;
2033 struct r600_pipe_sampler_view
*rview
;
2034 unsigned i
= u_bit_scan(&dirty_mask
);
2036 rstate
= texinfo
->states
.states
[i
];
2038 rview
= texinfo
->views
.views
[i
];
2040 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
2041 * filtering between layers.
2042 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
2045 enum pipe_texture_target target
= rview
->base
.texture
->target
;
2046 if (target
== PIPE_TEXTURE_1D_ARRAY
||
2047 target
== PIPE_TEXTURE_2D_ARRAY
) {
2048 rstate
->tex_sampler_words
[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
2049 texinfo
->is_array_sampler
[i
] = true;
2051 rstate
->tex_sampler_words
[0] &= C_03C000_TEX_ARRAY_OVERRIDE
;
2052 texinfo
->is_array_sampler
[i
] = false;
2056 r600_write_value(cs
, PKT3(PKT3_SET_SAMPLER
, 3, 0));
2057 r600_write_value(cs
, (resource_id_base
+ i
) * 3);
2058 r600_write_array(cs
, 3, rstate
->tex_sampler_words
);
2060 if (rstate
->border_color_use
) {
2063 offset
= border_color_reg
;
2065 r600_write_config_reg_seq(cs
, offset
, 4);
2066 r600_write_array(cs
, 4, rstate
->border_color
.ui
);
2069 texinfo
->states
.dirty_mask
= 0;
2072 static void r600_emit_vs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2074 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED
);
2077 static void r600_emit_gs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2079 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED
);
2082 static void r600_emit_ps_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2084 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED
);
2087 static void r600_emit_seamless_cube_map(struct r600_context
*rctx
, struct r600_atom
*atom
)
2089 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2092 tmp
= S_009508_DISABLE_CUBE_ANISO(1) |
2093 S_009508_SYNC_GRADIENT(1) |
2094 S_009508_SYNC_WALKER(1) |
2095 S_009508_SYNC_ALIGNER(1);
2096 if (!rctx
->seamless_cube_map
.enabled
) {
2097 tmp
|= S_009508_DISABLE_CUBE_WRAP(1);
2099 r600_write_config_reg(cs
, R_009508_TA_CNTL_AUX
, tmp
);
2102 static void r600_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2104 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2105 uint8_t mask
= s
->sample_mask
;
2107 r600_write_context_reg(rctx
->cs
, R_028C48_PA_SC_AA_MASK
,
2108 mask
| (mask
<< 8) | (mask
<< 16) | (mask
<< 24));
2111 static void r600_emit_vertex_fetch_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2113 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2114 struct r600_cso_state
*state
= (struct r600_cso_state
*)a
;
2115 struct r600_resource
*shader
= (struct r600_resource
*)state
->cso
;
2117 r600_write_context_reg(cs
, R_028894_SQ_PGM_START_FS
, 0);
2118 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2119 r600_write_value(cs
, r600_context_bo_reloc(rctx
, shader
, RADEON_USAGE_READ
));
2122 void r600_init_state_functions(struct r600_context
*rctx
)
2127 * To avoid GPU lockup registers must be emited in a specific order
2128 * (no kidding ...). The order below is important and have been
2129 * partialy infered from analyzing fglrx command stream.
2131 * Don't reorder atom without carefully checking the effect (GPU lockup
2132 * or piglit regression).
2136 r600_init_atom(rctx
, &rctx
->framebuffer
.atom
, id
++, r600_emit_framebuffer_state
, 0);
2139 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
].atom
, id
++, r600_emit_vs_constant_buffers
, 0);
2140 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
].atom
, id
++, r600_emit_gs_constant_buffers
, 0);
2141 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
].atom
, id
++, r600_emit_ps_constant_buffers
, 0);
2143 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2144 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
2146 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].states
.atom
, id
++, r600_emit_vs_sampler_states
, 0);
2147 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].states
.atom
, id
++, r600_emit_gs_sampler_states
, 0);
2148 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].states
.atom
, id
++, r600_emit_ps_sampler_states
, 0);
2150 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
.atom
, id
++, r600_emit_vs_sampler_views
, 0);
2151 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
.atom
, id
++, r600_emit_gs_sampler_views
, 0);
2152 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.atom
, id
++, r600_emit_ps_sampler_views
, 0);
2153 r600_init_atom(rctx
, &rctx
->vertex_buffer_state
.atom
, id
++, r600_emit_vertex_buffers
, 0);
2155 r600_init_atom(rctx
, &rctx
->vgt_state
.atom
, id
++, r600_emit_vgt_state
, 6);
2156 r600_init_atom(rctx
, &rctx
->vgt2_state
.atom
, id
++, r600_emit_vgt2_state
, 3);
2158 r600_init_atom(rctx
, &rctx
->seamless_cube_map
.atom
, id
++, r600_emit_seamless_cube_map
, 3);
2159 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, r600_emit_sample_mask
, 3);
2160 rctx
->sample_mask
.sample_mask
= ~0;
2162 r600_init_atom(rctx
, &rctx
->alphatest_state
.atom
, id
++, r600_emit_alphatest_state
, 6);
2163 r600_init_atom(rctx
, &rctx
->blend_color
.atom
, id
++, r600_emit_blend_color
, 6);
2164 r600_init_atom(rctx
, &rctx
->blend_state
.atom
, id
++, r600_emit_cso_state
, 0);
2165 r600_init_atom(rctx
, &rctx
->cb_misc_state
.atom
, id
++, r600_emit_cb_misc_state
, 7);
2166 r600_init_atom(rctx
, &rctx
->clip_misc_state
.atom
, id
++, r600_emit_clip_misc_state
, 6);
2167 r600_init_atom(rctx
, &rctx
->clip_state
.atom
, id
++, r600_emit_clip_state
, 26);
2168 r600_init_atom(rctx
, &rctx
->db_misc_state
.atom
, id
++, r600_emit_db_misc_state
, 7);
2169 r600_init_atom(rctx
, &rctx
->dsa_state
.atom
, id
++, r600_emit_cso_state
, 0);
2170 r600_init_atom(rctx
, &rctx
->poly_offset_state
.atom
, id
++, r600_emit_polygon_offset
, 6);
2171 r600_init_atom(rctx
, &rctx
->rasterizer_state
.atom
, id
++, r600_emit_cso_state
, 0);
2172 r600_init_atom(rctx
, &rctx
->scissor
.atom
, id
++, r600_emit_scissor_state
, 4);
2173 r600_init_atom(rctx
, &rctx
->config_state
.atom
, id
++, r600_emit_config_state
, 3);
2174 r600_init_atom(rctx
, &rctx
->stencil_ref
.atom
, id
++, r600_emit_stencil_ref
, 4);
2175 r600_init_atom(rctx
, &rctx
->viewport
.atom
, id
++, r600_emit_viewport_state
, 8);
2176 r600_init_atom(rctx
, &rctx
->vertex_fetch_shader
.atom
, id
++, r600_emit_vertex_fetch_shader
, 5);
2178 rctx
->context
.create_blend_state
= r600_create_blend_state
;
2179 rctx
->context
.create_depth_stencil_alpha_state
= r600_create_dsa_state
;
2180 rctx
->context
.create_rasterizer_state
= r600_create_rs_state
;
2181 rctx
->context
.create_sampler_state
= r600_create_sampler_state
;
2182 rctx
->context
.create_sampler_view
= r600_create_sampler_view
;
2183 rctx
->context
.set_framebuffer_state
= r600_set_framebuffer_state
;
2184 rctx
->context
.set_polygon_stipple
= r600_set_polygon_stipple
;
2185 rctx
->context
.set_scissor_state
= r600_set_scissor_state
;
2188 /* Adjust GPR allocation on R6xx/R7xx */
2189 void r600_adjust_gprs(struct r600_context
*rctx
)
2191 unsigned num_ps_gprs
= rctx
->default_ps_gprs
;
2192 unsigned num_vs_gprs
= rctx
->default_vs_gprs
;
2196 if (rctx
->ps_shader
->current
->shader
.bc
.ngpr
> rctx
->default_ps_gprs
) {
2197 diff
= rctx
->ps_shader
->current
->shader
.bc
.ngpr
- rctx
->default_ps_gprs
;
2198 num_vs_gprs
-= diff
;
2199 num_ps_gprs
+= diff
;
2202 if (rctx
->vs_shader
->current
->shader
.bc
.ngpr
> rctx
->default_vs_gprs
)
2204 diff
= rctx
->vs_shader
->current
->shader
.bc
.ngpr
- rctx
->default_vs_gprs
;
2205 num_ps_gprs
-= diff
;
2206 num_vs_gprs
+= diff
;
2210 tmp
|= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
2211 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
2212 tmp
|= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx
->r6xx_num_clause_temp_gprs
);
2214 if (tmp
!= rctx
->config_state
.sq_gpr_resource_mgmt_1
) {
2215 rctx
->config_state
.sq_gpr_resource_mgmt_1
= tmp
;
2216 rctx
->config_state
.atom
.dirty
= true;
2217 rctx
->flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
2221 void r600_init_atom_start_cs(struct r600_context
*rctx
)
2236 int num_ps_stack_entries
;
2237 int num_vs_stack_entries
;
2238 int num_gs_stack_entries
;
2239 int num_es_stack_entries
;
2240 enum radeon_family family
;
2241 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2244 r600_init_command_buffer(cb
, 256);
2246 /* R6xx requires this packet at the start of each command buffer */
2247 if (rctx
->chip_class
== R600
) {
2248 r600_store_value(cb
, PKT3(PKT3_START_3D_CMDBUF
, 0, 0));
2249 r600_store_value(cb
, 0);
2251 /* All asics require this one */
2252 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2253 r600_store_value(cb
, 0x80000000);
2254 r600_store_value(cb
, 0x80000000);
2256 /* We're setting config registers here. */
2257 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2258 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2260 family
= rctx
->family
;
2272 num_ps_threads
= 136;
2273 num_vs_threads
= 48;
2276 num_ps_stack_entries
= 128;
2277 num_vs_stack_entries
= 128;
2278 num_gs_stack_entries
= 0;
2279 num_es_stack_entries
= 0;
2288 num_ps_threads
= 144;
2289 num_vs_threads
= 40;
2292 num_ps_stack_entries
= 40;
2293 num_vs_stack_entries
= 40;
2294 num_gs_stack_entries
= 32;
2295 num_es_stack_entries
= 16;
2307 num_ps_threads
= 136;
2308 num_vs_threads
= 48;
2311 num_ps_stack_entries
= 40;
2312 num_vs_stack_entries
= 40;
2313 num_gs_stack_entries
= 32;
2314 num_es_stack_entries
= 16;
2322 num_ps_threads
= 136;
2323 num_vs_threads
= 48;
2326 num_ps_stack_entries
= 40;
2327 num_vs_stack_entries
= 40;
2328 num_gs_stack_entries
= 32;
2329 num_es_stack_entries
= 16;
2337 num_ps_threads
= 188;
2338 num_vs_threads
= 60;
2341 num_ps_stack_entries
= 256;
2342 num_vs_stack_entries
= 256;
2343 num_gs_stack_entries
= 0;
2344 num_es_stack_entries
= 0;
2353 num_ps_threads
= 188;
2354 num_vs_threads
= 60;
2357 num_ps_stack_entries
= 128;
2358 num_vs_stack_entries
= 128;
2359 num_gs_stack_entries
= 0;
2360 num_es_stack_entries
= 0;
2368 num_ps_threads
= 144;
2369 num_vs_threads
= 48;
2372 num_ps_stack_entries
= 128;
2373 num_vs_stack_entries
= 128;
2374 num_gs_stack_entries
= 0;
2375 num_es_stack_entries
= 0;
2379 rctx
->default_ps_gprs
= num_ps_gprs
;
2380 rctx
->default_vs_gprs
= num_vs_gprs
;
2381 rctx
->r6xx_num_clause_temp_gprs
= num_temp_gprs
;
2393 tmp
|= S_008C00_VC_ENABLE(1);
2396 tmp
|= S_008C00_DX9_CONSTS(0);
2397 tmp
|= S_008C00_ALU_INST_PREFER_VECTOR(1);
2398 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2399 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2400 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2401 tmp
|= S_008C00_ES_PRIO(es_prio
);
2402 r600_store_config_reg(cb
, R_008C00_SQ_CONFIG
, tmp
);
2404 /* SQ_GPR_RESOURCE_MGMT_2 */
2405 tmp
= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
2406 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
2407 r600_store_config_reg_seq(cb
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, 4);
2408 r600_store_value(cb
, tmp
);
2410 /* SQ_THREAD_RESOURCE_MGMT */
2411 tmp
= S_008C0C_NUM_PS_THREADS(num_ps_threads
);
2412 tmp
|= S_008C0C_NUM_VS_THREADS(num_vs_threads
);
2413 tmp
|= S_008C0C_NUM_GS_THREADS(num_gs_threads
);
2414 tmp
|= S_008C0C_NUM_ES_THREADS(num_es_threads
);
2415 r600_store_value(cb
, tmp
); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2417 /* SQ_STACK_RESOURCE_MGMT_1 */
2418 tmp
= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
2419 tmp
|= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
2420 r600_store_value(cb
, tmp
); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2422 /* SQ_STACK_RESOURCE_MGMT_2 */
2423 tmp
= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
2424 tmp
|= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
2425 r600_store_value(cb
, tmp
); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2427 r600_store_config_reg(cb
, R_009714_VC_ENHANCE
, 0);
2429 if (rctx
->chip_class
>= R700
) {
2430 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0x00004000);
2431 r600_store_config_reg(cb
, R_009830_DB_DEBUG
, 0);
2432 r600_store_config_reg(cb
, R_009838_DB_WATERMARKS
, 0x00420204);
2433 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2435 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0);
2436 r600_store_config_reg(cb
, R_009830_DB_DEBUG
, 0x82000000);
2437 r600_store_config_reg(cb
, R_009838_DB_WATERMARKS
, 0x01020204);
2438 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 1);
2440 r600_store_context_reg_seq(cb
, R_0288A8_SQ_ESGS_RING_ITEMSIZE
, 9);
2441 r600_store_value(cb
, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2442 r600_store_value(cb
, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2443 r600_store_value(cb
, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2444 r600_store_value(cb
, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2445 r600_store_value(cb
, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2446 r600_store_value(cb
, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2447 r600_store_value(cb
, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2448 r600_store_value(cb
, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2449 r600_store_value(cb
, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2451 /* to avoid GPU doing any preloading of constant from random address */
2452 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 8);
2453 r600_store_value(cb
, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2454 r600_store_value(cb
, 0);
2455 r600_store_value(cb
, 0);
2456 r600_store_value(cb
, 0);
2457 r600_store_value(cb
, 0);
2458 r600_store_value(cb
, 0);
2459 r600_store_value(cb
, 0);
2460 r600_store_value(cb
, 0);
2461 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 8);
2462 r600_store_value(cb
, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2463 r600_store_value(cb
, 0);
2464 r600_store_value(cb
, 0);
2465 r600_store_value(cb
, 0);
2466 r600_store_value(cb
, 0);
2467 r600_store_value(cb
, 0);
2468 r600_store_value(cb
, 0);
2469 r600_store_value(cb
, 0);
2471 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2472 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2473 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2474 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2475 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2476 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2477 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2478 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2479 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2480 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2481 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2482 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2483 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2484 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE, 0); */
2486 r600_store_context_reg(cb
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
2487 r600_store_context_reg(cb
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 0);
2488 r600_store_context_reg(cb
, R_028AA4_VGT_INSTANCE_STEP_RATE_1
, 0);
2490 r600_store_context_reg_seq(cb
, R_028AB0_VGT_STRMOUT_EN
, 3);
2491 r600_store_value(cb
, 0); /* R_028AB0_VGT_STRMOUT_EN */
2492 r600_store_value(cb
, 1); /* R_028AB4_VGT_REUSE_OFF */
2493 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2495 r600_store_context_reg(cb
, R_028B20_VGT_STRMOUT_BUFFER_EN
, 0);
2497 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2499 r600_store_context_reg_seq(cb
, R_028028_DB_STENCIL_CLEAR
, 2);
2500 r600_store_value(cb
, 0); /* R_028028_DB_STENCIL_CLEAR */
2501 r600_store_value(cb
, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2503 r600_store_context_reg_seq(cb
, R_0286DC_SPI_FOG_CNTL
, 3);
2504 r600_store_value(cb
, 0); /* R_0286DC_SPI_FOG_CNTL */
2505 r600_store_value(cb
, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2506 r600_store_value(cb
, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2508 r600_store_context_reg_seq(cb
, R_028D2C_DB_SRESULTS_COMPARE_STATE1
, 2);
2509 r600_store_value(cb
, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2510 r600_store_value(cb
, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2512 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2513 r600_store_context_reg(cb
, R_028A48_PA_SC_MPASS_PS_CNTL
, 0);
2515 r600_store_context_reg_seq(cb
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 4);
2516 r600_store_value(cb
, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2517 r600_store_value(cb
, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2518 r600_store_value(cb
, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2519 r600_store_value(cb
, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2521 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
2522 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2523 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2525 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x43F);
2527 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2528 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2530 if (rctx
->chip_class
>= R700
) {
2531 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2534 r600_store_context_reg_seq(cb
, R_028C30_CB_CLRCMP_CONTROL
, 4);
2535 r600_store_value(cb
, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2536 r600_store_value(cb
, 0); /* R_028C34_CB_CLRCMP_SRC */
2537 r600_store_value(cb
, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2538 r600_store_value(cb
, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2540 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2541 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2542 r600_store_value(cb
, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2544 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2545 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2546 r600_store_value(cb
, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2548 r600_store_context_reg_seq(cb
, R_0288CC_SQ_PGM_CF_OFFSET_PS
, 2);
2549 r600_store_value(cb
, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2550 r600_store_value(cb
, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2552 r600_store_context_reg_seq(cb
, R_028380_SQ_VTX_SEMANTIC_0
, 34);
2553 r600_store_value(cb
, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2554 r600_store_value(cb
, 0);
2555 r600_store_value(cb
, 0);
2556 r600_store_value(cb
, 0);
2557 r600_store_value(cb
, 0);
2558 r600_store_value(cb
, 0);
2559 r600_store_value(cb
, 0);
2560 r600_store_value(cb
, 0);
2561 r600_store_value(cb
, 0);
2562 r600_store_value(cb
, 0);
2563 r600_store_value(cb
, 0);
2564 r600_store_value(cb
, 0);
2565 r600_store_value(cb
, 0);
2566 r600_store_value(cb
, 0);
2567 r600_store_value(cb
, 0);
2568 r600_store_value(cb
, 0);
2569 r600_store_value(cb
, 0);
2570 r600_store_value(cb
, 0);
2571 r600_store_value(cb
, 0);
2572 r600_store_value(cb
, 0);
2573 r600_store_value(cb
, 0);
2574 r600_store_value(cb
, 0);
2575 r600_store_value(cb
, 0);
2576 r600_store_value(cb
, 0);
2577 r600_store_value(cb
, 0);
2578 r600_store_value(cb
, 0);
2579 r600_store_value(cb
, 0);
2580 r600_store_value(cb
, 0);
2581 r600_store_value(cb
, 0);
2582 r600_store_value(cb
, 0);
2583 r600_store_value(cb
, 0);
2584 r600_store_value(cb
, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2585 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2586 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2588 r600_store_context_reg(cb
, R_0288A4_SQ_PGM_RESOURCES_FS
, 0);
2589 r600_store_context_reg(cb
, R_0288DC_SQ_PGM_CF_OFFSET_FS
, 0);
2591 if (rctx
->chip_class
== R700
&& rctx
->screen
->has_streamout
)
2592 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
2593 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2594 if (rctx
->screen
->has_streamout
) {
2595 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2598 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
, 0x1000FFF);
2599 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
+ (32 * 4), 0x1000FFF);
2602 void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2604 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2605 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2606 struct r600_shader
*rshader
= &shader
->shader
;
2607 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
;
2608 int pos_index
= -1, face_index
= -1;
2609 unsigned tmp
, sid
, ufi
= 0;
2610 int need_linear
= 0;
2611 unsigned z_export
= 0, stencil_export
= 0;
2612 unsigned sprite_coord_enable
= rctx
->rasterizer
? rctx
->rasterizer
->sprite_coord_enable
: 0;
2616 for (i
= 0; i
< rshader
->ninput
; i
++) {
2617 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
2619 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
2622 sid
= rshader
->input
[i
].spi_sid
;
2624 tmp
= S_028644_SEMANTIC(sid
);
2626 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
2627 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2628 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
2629 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
))
2630 tmp
|= S_028644_FLAT_SHADE(1);
2632 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
2633 sprite_coord_enable
& (1 << rshader
->input
[i
].sid
)) {
2634 tmp
|= S_028644_PT_SPRITE_TEX(1);
2637 if (rshader
->input
[i
].centroid
)
2638 tmp
|= S_028644_SEL_CENTROID(1);
2640 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
) {
2642 tmp
|= S_028644_SEL_LINEAR(1);
2645 r600_pipe_state_add_reg(rstate
, R_028644_SPI_PS_INPUT_CNTL_0
+ i
* 4,
2649 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2650 for (i
= 0; i
< rshader
->noutput
; i
++) {
2651 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2653 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2656 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(z_export
);
2657 db_shader_control
|= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export
);
2658 if (rshader
->uses_kill
)
2659 db_shader_control
|= S_02880C_KILL_ENABLE(1);
2662 for (i
= 0; i
< rshader
->noutput
; i
++) {
2663 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
2664 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
) {
2668 num_cout
= rshader
->nr_ps_color_exports
;
2669 exports_ps
|= S_028854_EXPORT_COLORS(num_cout
);
2671 /* always at least export 1 component per pixel */
2675 shader
->nr_ps_color_outputs
= num_cout
;
2677 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(rshader
->ninput
) |
2678 S_0286CC_PERSP_GRADIENT_ENA(1)|
2679 S_0286CC_LINEAR_GRADIENT_ENA(need_linear
);
2681 if (pos_index
!= -1) {
2682 spi_ps_in_control_0
|= (S_0286CC_POSITION_ENA(1) |
2683 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
2684 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
) |
2685 S_0286CC_BARYC_SAMPLE_CNTL(1));
2689 spi_ps_in_control_1
= 0;
2690 if (face_index
!= -1) {
2691 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
2692 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
2695 /* HW bug in original R600 */
2696 if (rctx
->family
== CHIP_R600
)
2699 r600_pipe_state_add_reg(rstate
, R_0286CC_SPI_PS_IN_CONTROL_0
, spi_ps_in_control_0
);
2700 r600_pipe_state_add_reg(rstate
, R_0286D0_SPI_PS_IN_CONTROL_1
, spi_ps_in_control_1
);
2701 r600_pipe_state_add_reg(rstate
, R_0286D8_SPI_INPUT_Z
, spi_input_z
);
2702 r600_pipe_state_add_reg_bo(rstate
,
2703 R_028840_SQ_PGM_START_PS
,
2704 0, shader
->bo
, RADEON_USAGE_READ
);
2705 r600_pipe_state_add_reg(rstate
,
2706 R_028850_SQ_PGM_RESOURCES_PS
,
2707 S_028850_NUM_GPRS(rshader
->bc
.ngpr
) |
2708 S_028850_STACK_SIZE(rshader
->bc
.nstack
) |
2709 S_028850_UNCACHED_FIRST_INST(ufi
));
2710 r600_pipe_state_add_reg(rstate
,
2711 R_028854_SQ_PGM_EXPORTS_PS
,
2713 /* only set some bits here, the other bits are set in the dsa state */
2714 shader
->db_shader_control
= db_shader_control
;
2715 shader
->ps_depth_export
= z_export
| stencil_export
;
2717 shader
->sprite_coord_enable
= sprite_coord_enable
;
2718 if (rctx
->rasterizer
)
2719 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
2722 void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2724 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2725 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2726 struct r600_shader
*rshader
= &shader
->shader
;
2727 unsigned spi_vs_out_id
[10] = {};
2728 unsigned i
, tmp
, nparams
= 0;
2730 /* clear previous register */
2733 for (i
= 0; i
< rshader
->noutput
; i
++) {
2734 if (rshader
->output
[i
].spi_sid
) {
2735 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
2736 spi_vs_out_id
[nparams
/ 4] |= tmp
;
2741 for (i
= 0; i
< 10; i
++) {
2742 r600_pipe_state_add_reg(rstate
,
2743 R_028614_SPI_VS_OUT_ID_0
+ i
* 4,
2747 /* Certain attributes (position, psize, etc.) don't count as params.
2748 * VS is required to export at least one param and r600_shader_from_tgsi()
2749 * takes care of adding a dummy export.
2754 r600_pipe_state_add_reg(rstate
,
2755 R_0286C4_SPI_VS_OUT_CONFIG
,
2756 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
2757 r600_pipe_state_add_reg(rstate
,
2758 R_028868_SQ_PGM_RESOURCES_VS
,
2759 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
2760 S_028868_STACK_SIZE(rshader
->bc
.nstack
));
2761 r600_pipe_state_add_reg_bo(rstate
,
2762 R_028858_SQ_PGM_START_VS
,
2763 0, shader
->bo
, RADEON_USAGE_READ
);
2765 shader
->pa_cl_vs_out_cntl
=
2766 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
2767 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
2768 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
2769 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
);
2772 void *r600_create_resolve_blend(struct r600_context
*rctx
)
2774 struct pipe_blend_state blend
;
2777 memset(&blend
, 0, sizeof(blend
));
2778 blend
.independent_blend_enable
= true;
2779 for (i
= 0; i
< 2; i
++) {
2780 blend
.rt
[i
].colormask
= 0xf;
2781 blend
.rt
[i
].blend_enable
= 1;
2782 blend
.rt
[i
].rgb_func
= PIPE_BLEND_ADD
;
2783 blend
.rt
[i
].alpha_func
= PIPE_BLEND_ADD
;
2784 blend
.rt
[i
].rgb_src_factor
= PIPE_BLENDFACTOR_ZERO
;
2785 blend
.rt
[i
].rgb_dst_factor
= PIPE_BLENDFACTOR_ZERO
;
2786 blend
.rt
[i
].alpha_src_factor
= PIPE_BLENDFACTOR_ZERO
;
2787 blend
.rt
[i
].alpha_dst_factor
= PIPE_BLENDFACTOR_ZERO
;
2789 return r600_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_SPECIAL_RESOLVE_BOX
);
2792 void *r700_create_resolve_blend(struct r600_context
*rctx
)
2794 struct pipe_blend_state blend
;
2796 memset(&blend
, 0, sizeof(blend
));
2797 blend
.independent_blend_enable
= true;
2798 blend
.rt
[0].colormask
= 0xf;
2799 return r600_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_SPECIAL_RESOLVE_BOX
);
2802 void *r600_create_decompress_blend(struct r600_context
*rctx
)
2804 struct pipe_blend_state blend
;
2806 memset(&blend
, 0, sizeof(blend
));
2807 blend
.independent_blend_enable
= true;
2808 blend
.rt
[0].colormask
= 0xf;
2809 return r600_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_SPECIAL_EXPAND_SAMPLES
);
2812 void *r600_create_db_flush_dsa(struct r600_context
*rctx
)
2814 struct pipe_depth_stencil_alpha_state dsa
;
2815 boolean quirk
= false;
2817 if (rctx
->family
== CHIP_RV610
|| rctx
->family
== CHIP_RV630
||
2818 rctx
->family
== CHIP_RV620
|| rctx
->family
== CHIP_RV635
)
2821 memset(&dsa
, 0, sizeof(dsa
));
2824 dsa
.depth
.enabled
= 1;
2825 dsa
.depth
.func
= PIPE_FUNC_LEQUAL
;
2826 dsa
.stencil
[0].enabled
= 1;
2827 dsa
.stencil
[0].func
= PIPE_FUNC_ALWAYS
;
2828 dsa
.stencil
[0].zpass_op
= PIPE_STENCIL_OP_KEEP
;
2829 dsa
.stencil
[0].zfail_op
= PIPE_STENCIL_OP_INCR
;
2830 dsa
.stencil
[0].writemask
= 0xff;
2833 return rctx
->context
.create_depth_stencil_alpha_state(&rctx
->context
, &dsa
);
2836 void r600_update_db_shader_control(struct r600_context
* rctx
)
2838 bool dual_export
= rctx
->framebuffer
.export_16bpc
&&
2839 !rctx
->ps_shader
->current
->ps_depth_export
;
2841 unsigned db_shader_control
= rctx
->ps_shader
->current
->db_shader_control
|
2842 S_02880C_DUAL_EXPORT_ENABLE(dual_export
);
2844 if (db_shader_control
!= rctx
->db_misc_state
.db_shader_control
) {
2845 rctx
->db_misc_state
.db_shader_control
= db_shader_control
;
2846 rctx
->db_misc_state
.atom
.dirty
= true;