2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
32 static uint32_t r600_translate_blend_function(int blend_func
)
36 return V_028804_COMB_DST_PLUS_SRC
;
37 case PIPE_BLEND_SUBTRACT
:
38 return V_028804_COMB_SRC_MINUS_DST
;
39 case PIPE_BLEND_REVERSE_SUBTRACT
:
40 return V_028804_COMB_DST_MINUS_SRC
;
42 return V_028804_COMB_MIN_DST_SRC
;
44 return V_028804_COMB_MAX_DST_SRC
;
46 R600_ERR("Unknown blend function %d\n", blend_func
);
53 static uint32_t r600_translate_blend_factor(int blend_fact
)
56 case PIPE_BLENDFACTOR_ONE
:
57 return V_028804_BLEND_ONE
;
58 case PIPE_BLENDFACTOR_SRC_COLOR
:
59 return V_028804_BLEND_SRC_COLOR
;
60 case PIPE_BLENDFACTOR_SRC_ALPHA
:
61 return V_028804_BLEND_SRC_ALPHA
;
62 case PIPE_BLENDFACTOR_DST_ALPHA
:
63 return V_028804_BLEND_DST_ALPHA
;
64 case PIPE_BLENDFACTOR_DST_COLOR
:
65 return V_028804_BLEND_DST_COLOR
;
66 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
67 return V_028804_BLEND_SRC_ALPHA_SATURATE
;
68 case PIPE_BLENDFACTOR_CONST_COLOR
:
69 return V_028804_BLEND_CONST_COLOR
;
70 case PIPE_BLENDFACTOR_CONST_ALPHA
:
71 return V_028804_BLEND_CONST_ALPHA
;
72 case PIPE_BLENDFACTOR_ZERO
:
73 return V_028804_BLEND_ZERO
;
74 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
75 return V_028804_BLEND_ONE_MINUS_SRC_COLOR
;
76 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
77 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA
;
78 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
79 return V_028804_BLEND_ONE_MINUS_DST_ALPHA
;
80 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
81 return V_028804_BLEND_ONE_MINUS_DST_COLOR
;
82 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
83 return V_028804_BLEND_ONE_MINUS_CONST_COLOR
;
84 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
85 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA
;
86 case PIPE_BLENDFACTOR_SRC1_COLOR
:
87 return V_028804_BLEND_SRC1_COLOR
;
88 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
89 return V_028804_BLEND_SRC1_ALPHA
;
90 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
91 return V_028804_BLEND_INV_SRC1_COLOR
;
92 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
93 return V_028804_BLEND_INV_SRC1_ALPHA
;
95 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
102 static unsigned r600_tex_dim(unsigned dim
, unsigned nr_samples
)
106 case PIPE_TEXTURE_1D
:
107 return V_038000_SQ_TEX_DIM_1D
;
108 case PIPE_TEXTURE_1D_ARRAY
:
109 return V_038000_SQ_TEX_DIM_1D_ARRAY
;
110 case PIPE_TEXTURE_2D
:
111 case PIPE_TEXTURE_RECT
:
112 return nr_samples
> 1 ? V_038000_SQ_TEX_DIM_2D_MSAA
:
113 V_038000_SQ_TEX_DIM_2D
;
114 case PIPE_TEXTURE_2D_ARRAY
:
115 return nr_samples
> 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
116 V_038000_SQ_TEX_DIM_2D_ARRAY
;
117 case PIPE_TEXTURE_3D
:
118 return V_038000_SQ_TEX_DIM_3D
;
119 case PIPE_TEXTURE_CUBE
:
120 return V_038000_SQ_TEX_DIM_CUBEMAP
;
124 static uint32_t r600_translate_dbformat(enum pipe_format format
)
127 case PIPE_FORMAT_Z16_UNORM
:
128 return V_028010_DEPTH_16
;
129 case PIPE_FORMAT_Z24X8_UNORM
:
130 return V_028010_DEPTH_X8_24
;
131 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
132 return V_028010_DEPTH_8_24
;
133 case PIPE_FORMAT_Z32_FLOAT
:
134 return V_028010_DEPTH_32_FLOAT
;
135 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
136 return V_028010_DEPTH_X24_8_32_FLOAT
;
142 static uint32_t r600_translate_colorswap(enum pipe_format format
)
146 case PIPE_FORMAT_A8_UNORM
:
147 case PIPE_FORMAT_A8_SNORM
:
148 case PIPE_FORMAT_A8_UINT
:
149 case PIPE_FORMAT_A8_SINT
:
150 case PIPE_FORMAT_A16_UNORM
:
151 case PIPE_FORMAT_A16_SNORM
:
152 case PIPE_FORMAT_A16_UINT
:
153 case PIPE_FORMAT_A16_SINT
:
154 case PIPE_FORMAT_A16_FLOAT
:
155 case PIPE_FORMAT_A32_UINT
:
156 case PIPE_FORMAT_A32_SINT
:
157 case PIPE_FORMAT_A32_FLOAT
:
158 case PIPE_FORMAT_R4A4_UNORM
:
159 return V_0280A0_SWAP_ALT_REV
;
160 case PIPE_FORMAT_I8_UNORM
:
161 case PIPE_FORMAT_I8_SNORM
:
162 case PIPE_FORMAT_I8_UINT
:
163 case PIPE_FORMAT_I8_SINT
:
164 case PIPE_FORMAT_L8_UNORM
:
165 case PIPE_FORMAT_L8_SNORM
:
166 case PIPE_FORMAT_L8_UINT
:
167 case PIPE_FORMAT_L8_SINT
:
168 case PIPE_FORMAT_L8_SRGB
:
169 case PIPE_FORMAT_L16_UNORM
:
170 case PIPE_FORMAT_L16_SNORM
:
171 case PIPE_FORMAT_L16_UINT
:
172 case PIPE_FORMAT_L16_SINT
:
173 case PIPE_FORMAT_L16_FLOAT
:
174 case PIPE_FORMAT_L32_UINT
:
175 case PIPE_FORMAT_L32_SINT
:
176 case PIPE_FORMAT_L32_FLOAT
:
177 case PIPE_FORMAT_I16_UNORM
:
178 case PIPE_FORMAT_I16_SNORM
:
179 case PIPE_FORMAT_I16_UINT
:
180 case PIPE_FORMAT_I16_SINT
:
181 case PIPE_FORMAT_I16_FLOAT
:
182 case PIPE_FORMAT_I32_UINT
:
183 case PIPE_FORMAT_I32_SINT
:
184 case PIPE_FORMAT_I32_FLOAT
:
185 case PIPE_FORMAT_R8_UNORM
:
186 case PIPE_FORMAT_R8_SNORM
:
187 case PIPE_FORMAT_R8_UINT
:
188 case PIPE_FORMAT_R8_SINT
:
189 return V_0280A0_SWAP_STD
;
191 case PIPE_FORMAT_L4A4_UNORM
:
192 case PIPE_FORMAT_A4R4_UNORM
:
193 return V_0280A0_SWAP_ALT
;
195 /* 16-bit buffers. */
196 case PIPE_FORMAT_B5G6R5_UNORM
:
197 return V_0280A0_SWAP_STD_REV
;
199 case PIPE_FORMAT_B5G5R5A1_UNORM
:
200 case PIPE_FORMAT_B5G5R5X1_UNORM
:
201 return V_0280A0_SWAP_ALT
;
203 case PIPE_FORMAT_B4G4R4A4_UNORM
:
204 case PIPE_FORMAT_B4G4R4X4_UNORM
:
205 return V_0280A0_SWAP_ALT
;
207 case PIPE_FORMAT_Z16_UNORM
:
208 return V_0280A0_SWAP_STD
;
210 case PIPE_FORMAT_L8A8_UNORM
:
211 case PIPE_FORMAT_L8A8_SNORM
:
212 case PIPE_FORMAT_L8A8_UINT
:
213 case PIPE_FORMAT_L8A8_SINT
:
214 case PIPE_FORMAT_L8A8_SRGB
:
215 case PIPE_FORMAT_L16A16_UNORM
:
216 case PIPE_FORMAT_L16A16_SNORM
:
217 case PIPE_FORMAT_L16A16_UINT
:
218 case PIPE_FORMAT_L16A16_SINT
:
219 case PIPE_FORMAT_L16A16_FLOAT
:
220 case PIPE_FORMAT_L32A32_UINT
:
221 case PIPE_FORMAT_L32A32_SINT
:
222 case PIPE_FORMAT_L32A32_FLOAT
:
223 return V_0280A0_SWAP_ALT
;
224 case PIPE_FORMAT_R8G8_UNORM
:
225 case PIPE_FORMAT_R8G8_SNORM
:
226 case PIPE_FORMAT_R8G8_UINT
:
227 case PIPE_FORMAT_R8G8_SINT
:
228 return V_0280A0_SWAP_STD
;
230 case PIPE_FORMAT_R16_UNORM
:
231 case PIPE_FORMAT_R16_SNORM
:
232 case PIPE_FORMAT_R16_UINT
:
233 case PIPE_FORMAT_R16_SINT
:
234 case PIPE_FORMAT_R16_FLOAT
:
235 return V_0280A0_SWAP_STD
;
237 /* 32-bit buffers. */
239 case PIPE_FORMAT_A8B8G8R8_SRGB
:
240 return V_0280A0_SWAP_STD_REV
;
241 case PIPE_FORMAT_B8G8R8A8_SRGB
:
242 return V_0280A0_SWAP_ALT
;
244 case PIPE_FORMAT_B8G8R8A8_UNORM
:
245 case PIPE_FORMAT_B8G8R8X8_UNORM
:
246 return V_0280A0_SWAP_ALT
;
248 case PIPE_FORMAT_A8R8G8B8_UNORM
:
249 case PIPE_FORMAT_X8R8G8B8_UNORM
:
250 return V_0280A0_SWAP_ALT_REV
;
251 case PIPE_FORMAT_R8G8B8A8_SNORM
:
252 case PIPE_FORMAT_R8G8B8A8_UNORM
:
253 case PIPE_FORMAT_R8G8B8X8_UNORM
:
254 case PIPE_FORMAT_R8G8B8A8_SINT
:
255 case PIPE_FORMAT_R8G8B8A8_UINT
:
256 return V_0280A0_SWAP_STD
;
258 case PIPE_FORMAT_A8B8G8R8_UNORM
:
259 case PIPE_FORMAT_X8B8G8R8_UNORM
:
260 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
261 return V_0280A0_SWAP_STD_REV
;
263 case PIPE_FORMAT_Z24X8_UNORM
:
264 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
265 return V_0280A0_SWAP_STD
;
267 case PIPE_FORMAT_X8Z24_UNORM
:
268 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
269 return V_0280A0_SWAP_STD
;
271 case PIPE_FORMAT_R10G10B10A2_UNORM
:
272 case PIPE_FORMAT_R10G10B10X2_SNORM
:
273 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
274 return V_0280A0_SWAP_STD
;
276 case PIPE_FORMAT_B10G10R10A2_UNORM
:
277 case PIPE_FORMAT_B10G10R10A2_UINT
:
278 return V_0280A0_SWAP_ALT
;
280 case PIPE_FORMAT_R11G11B10_FLOAT
:
281 case PIPE_FORMAT_R16G16_UNORM
:
282 case PIPE_FORMAT_R16G16_SNORM
:
283 case PIPE_FORMAT_R16G16_FLOAT
:
284 case PIPE_FORMAT_R16G16_UINT
:
285 case PIPE_FORMAT_R16G16_SINT
:
286 case PIPE_FORMAT_R32_UINT
:
287 case PIPE_FORMAT_R32_SINT
:
288 case PIPE_FORMAT_R32_FLOAT
:
289 case PIPE_FORMAT_Z32_FLOAT
:
290 return V_0280A0_SWAP_STD
;
292 /* 64-bit buffers. */
293 case PIPE_FORMAT_R32G32_FLOAT
:
294 case PIPE_FORMAT_R32G32_UINT
:
295 case PIPE_FORMAT_R32G32_SINT
:
296 case PIPE_FORMAT_R16G16B16A16_UNORM
:
297 case PIPE_FORMAT_R16G16B16A16_SNORM
:
298 case PIPE_FORMAT_R16G16B16A16_UINT
:
299 case PIPE_FORMAT_R16G16B16A16_SINT
:
300 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
301 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
303 /* 128-bit buffers. */
304 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
305 case PIPE_FORMAT_R32G32B32A32_SNORM
:
306 case PIPE_FORMAT_R32G32B32A32_UNORM
:
307 case PIPE_FORMAT_R32G32B32A32_SINT
:
308 case PIPE_FORMAT_R32G32B32A32_UINT
:
309 return V_0280A0_SWAP_STD
;
311 R600_ERR("unsupported colorswap format %d\n", format
);
317 static uint32_t r600_translate_colorformat(enum pipe_format format
)
320 case PIPE_FORMAT_L4A4_UNORM
:
321 case PIPE_FORMAT_R4A4_UNORM
:
322 case PIPE_FORMAT_A4R4_UNORM
:
323 return V_0280A0_COLOR_4_4
;
326 case PIPE_FORMAT_A8_UNORM
:
327 case PIPE_FORMAT_A8_SNORM
:
328 case PIPE_FORMAT_A8_UINT
:
329 case PIPE_FORMAT_A8_SINT
:
330 case PIPE_FORMAT_I8_UNORM
:
331 case PIPE_FORMAT_I8_SNORM
:
332 case PIPE_FORMAT_I8_UINT
:
333 case PIPE_FORMAT_I8_SINT
:
334 case PIPE_FORMAT_L8_UNORM
:
335 case PIPE_FORMAT_L8_SNORM
:
336 case PIPE_FORMAT_L8_UINT
:
337 case PIPE_FORMAT_L8_SINT
:
338 case PIPE_FORMAT_L8_SRGB
:
339 case PIPE_FORMAT_R8_UNORM
:
340 case PIPE_FORMAT_R8_SNORM
:
341 case PIPE_FORMAT_R8_UINT
:
342 case PIPE_FORMAT_R8_SINT
:
343 return V_0280A0_COLOR_8
;
345 /* 16-bit buffers. */
346 case PIPE_FORMAT_B5G6R5_UNORM
:
347 return V_0280A0_COLOR_5_6_5
;
349 case PIPE_FORMAT_B5G5R5A1_UNORM
:
350 case PIPE_FORMAT_B5G5R5X1_UNORM
:
351 return V_0280A0_COLOR_1_5_5_5
;
353 case PIPE_FORMAT_B4G4R4A4_UNORM
:
354 case PIPE_FORMAT_B4G4R4X4_UNORM
:
355 return V_0280A0_COLOR_4_4_4_4
;
357 case PIPE_FORMAT_Z16_UNORM
:
358 return V_0280A0_COLOR_16
;
360 case PIPE_FORMAT_L8A8_UNORM
:
361 case PIPE_FORMAT_L8A8_SNORM
:
362 case PIPE_FORMAT_L8A8_UINT
:
363 case PIPE_FORMAT_L8A8_SINT
:
364 case PIPE_FORMAT_L8A8_SRGB
:
365 case PIPE_FORMAT_R8G8_UNORM
:
366 case PIPE_FORMAT_R8G8_SNORM
:
367 case PIPE_FORMAT_R8G8_UINT
:
368 case PIPE_FORMAT_R8G8_SINT
:
369 return V_0280A0_COLOR_8_8
;
371 case PIPE_FORMAT_R16_UNORM
:
372 case PIPE_FORMAT_R16_SNORM
:
373 case PIPE_FORMAT_R16_UINT
:
374 case PIPE_FORMAT_R16_SINT
:
375 case PIPE_FORMAT_A16_UNORM
:
376 case PIPE_FORMAT_A16_SNORM
:
377 case PIPE_FORMAT_A16_UINT
:
378 case PIPE_FORMAT_A16_SINT
:
379 case PIPE_FORMAT_L16_UNORM
:
380 case PIPE_FORMAT_L16_SNORM
:
381 case PIPE_FORMAT_L16_UINT
:
382 case PIPE_FORMAT_L16_SINT
:
383 case PIPE_FORMAT_I16_UNORM
:
384 case PIPE_FORMAT_I16_SNORM
:
385 case PIPE_FORMAT_I16_UINT
:
386 case PIPE_FORMAT_I16_SINT
:
387 return V_0280A0_COLOR_16
;
389 case PIPE_FORMAT_R16_FLOAT
:
390 case PIPE_FORMAT_A16_FLOAT
:
391 case PIPE_FORMAT_L16_FLOAT
:
392 case PIPE_FORMAT_I16_FLOAT
:
393 return V_0280A0_COLOR_16_FLOAT
;
395 /* 32-bit buffers. */
396 case PIPE_FORMAT_A8B8G8R8_SRGB
:
397 case PIPE_FORMAT_A8B8G8R8_UNORM
:
398 case PIPE_FORMAT_A8R8G8B8_UNORM
:
399 case PIPE_FORMAT_B8G8R8A8_SRGB
:
400 case PIPE_FORMAT_B8G8R8A8_UNORM
:
401 case PIPE_FORMAT_B8G8R8X8_UNORM
:
402 case PIPE_FORMAT_R8G8B8A8_SNORM
:
403 case PIPE_FORMAT_R8G8B8A8_UNORM
:
404 case PIPE_FORMAT_R8G8B8X8_UNORM
:
405 case PIPE_FORMAT_R8SG8SB8UX8U_NORM
:
406 case PIPE_FORMAT_X8B8G8R8_UNORM
:
407 case PIPE_FORMAT_X8R8G8B8_UNORM
:
408 case PIPE_FORMAT_R8G8B8A8_SINT
:
409 case PIPE_FORMAT_R8G8B8A8_UINT
:
410 return V_0280A0_COLOR_8_8_8_8
;
412 case PIPE_FORMAT_R10G10B10A2_UNORM
:
413 case PIPE_FORMAT_R10G10B10X2_SNORM
:
414 case PIPE_FORMAT_B10G10R10A2_UNORM
:
415 case PIPE_FORMAT_B10G10R10A2_UINT
:
416 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
417 return V_0280A0_COLOR_2_10_10_10
;
419 case PIPE_FORMAT_Z24X8_UNORM
:
420 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
421 return V_0280A0_COLOR_8_24
;
423 case PIPE_FORMAT_X8Z24_UNORM
:
424 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
425 return V_0280A0_COLOR_24_8
;
427 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
428 return V_0280A0_COLOR_X24_8_32_FLOAT
;
430 case PIPE_FORMAT_R32_UINT
:
431 case PIPE_FORMAT_R32_SINT
:
432 case PIPE_FORMAT_A32_UINT
:
433 case PIPE_FORMAT_A32_SINT
:
434 case PIPE_FORMAT_L32_UINT
:
435 case PIPE_FORMAT_L32_SINT
:
436 case PIPE_FORMAT_I32_UINT
:
437 case PIPE_FORMAT_I32_SINT
:
438 return V_0280A0_COLOR_32
;
440 case PIPE_FORMAT_R32_FLOAT
:
441 case PIPE_FORMAT_A32_FLOAT
:
442 case PIPE_FORMAT_L32_FLOAT
:
443 case PIPE_FORMAT_I32_FLOAT
:
444 case PIPE_FORMAT_Z32_FLOAT
:
445 return V_0280A0_COLOR_32_FLOAT
;
447 case PIPE_FORMAT_R16G16_FLOAT
:
448 case PIPE_FORMAT_L16A16_FLOAT
:
449 return V_0280A0_COLOR_16_16_FLOAT
;
451 case PIPE_FORMAT_R16G16_UNORM
:
452 case PIPE_FORMAT_R16G16_SNORM
:
453 case PIPE_FORMAT_R16G16_UINT
:
454 case PIPE_FORMAT_R16G16_SINT
:
455 case PIPE_FORMAT_L16A16_UNORM
:
456 case PIPE_FORMAT_L16A16_SNORM
:
457 case PIPE_FORMAT_L16A16_UINT
:
458 case PIPE_FORMAT_L16A16_SINT
:
459 return V_0280A0_COLOR_16_16
;
461 case PIPE_FORMAT_R11G11B10_FLOAT
:
462 return V_0280A0_COLOR_10_11_11_FLOAT
;
464 /* 64-bit buffers. */
465 case PIPE_FORMAT_R16G16B16A16_UINT
:
466 case PIPE_FORMAT_R16G16B16A16_SINT
:
467 case PIPE_FORMAT_R16G16B16A16_UNORM
:
468 case PIPE_FORMAT_R16G16B16A16_SNORM
:
469 return V_0280A0_COLOR_16_16_16_16
;
471 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
472 return V_0280A0_COLOR_16_16_16_16_FLOAT
;
474 case PIPE_FORMAT_R32G32_FLOAT
:
475 case PIPE_FORMAT_L32A32_FLOAT
:
476 return V_0280A0_COLOR_32_32_FLOAT
;
478 case PIPE_FORMAT_R32G32_SINT
:
479 case PIPE_FORMAT_R32G32_UINT
:
480 case PIPE_FORMAT_L32A32_UINT
:
481 case PIPE_FORMAT_L32A32_SINT
:
482 return V_0280A0_COLOR_32_32
;
484 /* 128-bit buffers. */
485 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
486 return V_0280A0_COLOR_32_32_32_32_FLOAT
;
487 case PIPE_FORMAT_R32G32B32A32_SNORM
:
488 case PIPE_FORMAT_R32G32B32A32_UNORM
:
489 case PIPE_FORMAT_R32G32B32A32_SINT
:
490 case PIPE_FORMAT_R32G32B32A32_UINT
:
491 return V_0280A0_COLOR_32_32_32_32
;
494 case PIPE_FORMAT_UYVY
:
495 case PIPE_FORMAT_YUYV
:
497 return ~0U; /* Unsupported. */
501 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat
)
503 if (R600_BIG_ENDIAN
) {
504 switch(colorformat
) {
505 case V_0280A0_COLOR_4_4
:
509 case V_0280A0_COLOR_8
:
512 /* 16-bit buffers. */
513 case V_0280A0_COLOR_5_6_5
:
514 case V_0280A0_COLOR_1_5_5_5
:
515 case V_0280A0_COLOR_4_4_4_4
:
516 case V_0280A0_COLOR_16
:
517 case V_0280A0_COLOR_8_8
:
520 /* 32-bit buffers. */
521 case V_0280A0_COLOR_8_8_8_8
:
522 case V_0280A0_COLOR_2_10_10_10
:
523 case V_0280A0_COLOR_8_24
:
524 case V_0280A0_COLOR_24_8
:
525 case V_0280A0_COLOR_32_FLOAT
:
526 case V_0280A0_COLOR_16_16_FLOAT
:
527 case V_0280A0_COLOR_16_16
:
530 /* 64-bit buffers. */
531 case V_0280A0_COLOR_16_16_16_16
:
532 case V_0280A0_COLOR_16_16_16_16_FLOAT
:
535 case V_0280A0_COLOR_32_32_FLOAT
:
536 case V_0280A0_COLOR_32_32
:
537 case V_0280A0_COLOR_X24_8_32_FLOAT
:
540 /* 128-bit buffers. */
541 case V_0280A0_COLOR_32_32_32_FLOAT
:
542 case V_0280A0_COLOR_32_32_32_32_FLOAT
:
543 case V_0280A0_COLOR_32_32_32_32
:
546 return ENDIAN_NONE
; /* Unsupported. */
553 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
555 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
) != ~0U;
558 static bool r600_is_colorbuffer_format_supported(enum pipe_format format
)
560 return r600_translate_colorformat(format
) != ~0U &&
561 r600_translate_colorswap(format
) != ~0U;
564 static bool r600_is_zs_format_supported(enum pipe_format format
)
566 return r600_translate_dbformat(format
) != ~0U;
569 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
570 enum pipe_format format
,
571 enum pipe_texture_target target
,
572 unsigned sample_count
,
575 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
578 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
579 R600_ERR("r600: unsupported texture type %d\n", target
);
583 if (!util_format_is_supported(format
, usage
))
586 if (sample_count
> 1) {
587 if (rscreen
->info
.drm_minor
< 22)
590 /* R11G11B10 is broken on R6xx. */
591 if (rscreen
->chip_class
== R600
&&
592 format
== PIPE_FORMAT_R11G11B10_FLOAT
)
595 /* MSAA integer colorbuffers hang. */
596 if (util_format_is_pure_integer(format
))
599 switch (sample_count
) {
609 if ((usage
& PIPE_BIND_SAMPLER_VIEW
) &&
610 r600_is_sampler_format_supported(screen
, format
)) {
611 retval
|= PIPE_BIND_SAMPLER_VIEW
;
614 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
615 PIPE_BIND_DISPLAY_TARGET
|
617 PIPE_BIND_SHARED
)) &&
618 r600_is_colorbuffer_format_supported(format
)) {
620 (PIPE_BIND_RENDER_TARGET
|
621 PIPE_BIND_DISPLAY_TARGET
|
626 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
627 r600_is_zs_format_supported(format
)) {
628 retval
|= PIPE_BIND_DEPTH_STENCIL
;
631 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
632 r600_is_vertex_format_supported(format
)) {
633 retval
|= PIPE_BIND_VERTEX_BUFFER
;
636 if (usage
& PIPE_BIND_TRANSFER_READ
)
637 retval
|= PIPE_BIND_TRANSFER_READ
;
638 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
639 retval
|= PIPE_BIND_TRANSFER_WRITE
;
641 return retval
== usage
;
644 void r600_polygon_offset_update(struct r600_context
*rctx
)
646 struct r600_pipe_state state
;
648 state
.id
= R600_PIPE_STATE_POLYGON_OFFSET
;
650 if (rctx
->rasterizer
&& rctx
->framebuffer
.state
.zsbuf
) {
651 float offset_units
= rctx
->rasterizer
->offset_units
;
652 unsigned offset_db_fmt_cntl
= 0, depth
;
654 switch (rctx
->framebuffer
.state
.zsbuf
->format
) {
655 case PIPE_FORMAT_Z24X8_UNORM
:
656 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
658 offset_units
*= 2.0f
;
660 case PIPE_FORMAT_Z32_FLOAT
:
661 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
663 offset_units
*= 1.0f
;
664 offset_db_fmt_cntl
|= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
666 case PIPE_FORMAT_Z16_UNORM
:
668 offset_units
*= 4.0f
;
673 /* XXX some of those reg can be computed with cso */
674 offset_db_fmt_cntl
|= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
675 r600_pipe_state_add_reg(&state
,
676 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE
,
677 fui(rctx
->rasterizer
->offset_scale
));
678 r600_pipe_state_add_reg(&state
,
679 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
681 r600_pipe_state_add_reg(&state
,
682 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE
,
683 fui(rctx
->rasterizer
->offset_scale
));
684 r600_pipe_state_add_reg(&state
,
685 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
687 r600_pipe_state_add_reg(&state
,
688 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
690 r600_context_pipe_state_set(rctx
, &state
);
694 static void *r600_create_blend_state_mode(struct pipe_context
*ctx
,
695 const struct pipe_blend_state
*state
,
698 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
699 struct r600_pipe_blend
*blend
= CALLOC_STRUCT(r600_pipe_blend
);
700 struct r600_pipe_state
*rstate
;
701 uint32_t color_control
= 0, target_mask
= 0;
706 rstate
= &blend
->rstate
;
708 rstate
->id
= R600_PIPE_STATE_BLEND
;
710 /* R600 does not support per-MRT blends */
711 if (rctx
->family
> CHIP_R600
)
712 color_control
|= S_028808_PER_MRT_BLEND(1);
714 if (state
->logicop_enable
) {
715 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
717 color_control
|= (0xcc << 16);
719 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
720 if (state
->independent_blend_enable
) {
721 for (int i
= 0; i
< 8; i
++) {
722 if (state
->rt
[i
].blend_enable
) {
723 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
725 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
728 for (int i
= 0; i
< 8; i
++) {
729 if (state
->rt
[0].blend_enable
) {
730 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
732 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
737 color_control
|= S_028808_SPECIAL_OP(mode
);
739 color_control
|= S_028808_SPECIAL_OP(V_028808_DISABLE
);
741 blend
->cb_target_mask
= target_mask
;
742 blend
->cb_color_control
= color_control
;
743 /* only MRT0 has dual src blend */
744 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
745 for (int i
= 0; i
< 8; i
++) {
746 /* state->rt entries > 0 only written if independent blending */
747 const int j
= state
->independent_blend_enable
? i
: 0;
749 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
750 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
751 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
753 unsigned eqA
= state
->rt
[j
].alpha_func
;
754 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
755 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
758 if (!state
->rt
[j
].blend_enable
)
761 bc
|= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
762 bc
|= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
763 bc
|= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
765 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
766 bc
|= S_028804_SEPARATE_ALPHA_BLEND(1);
767 bc
|= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
768 bc
|= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
769 bc
|= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
772 /* R600 does not support per-MRT blends */
773 if (rctx
->family
> CHIP_R600
)
774 r600_pipe_state_add_reg(rstate
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, bc
);
776 r600_pipe_state_add_reg(rstate
, R_028804_CB_BLEND_CONTROL
, bc
);
779 r600_pipe_state_add_reg(rstate
, R_028D44_DB_ALPHA_TO_MASK
,
780 S_028D44_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
781 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
782 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
783 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
784 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
786 blend
->alpha_to_one
= state
->alpha_to_one
;
791 static void *r600_create_blend_state(struct pipe_context
*ctx
,
792 const struct pipe_blend_state
*state
)
794 return r600_create_blend_state_mode(ctx
, state
, V_028808_SPECIAL_NORMAL
);
797 static void *r600_create_dsa_state(struct pipe_context
*ctx
,
798 const struct pipe_depth_stencil_alpha_state
*state
)
800 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
801 struct r600_pipe_dsa
*dsa
= CALLOC_STRUCT(r600_pipe_dsa
);
802 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
803 struct r600_pipe_state
*rstate
;
809 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
810 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
811 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
812 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
814 rstate
= &dsa
->rstate
;
816 rstate
->id
= R600_PIPE_STATE_DSA
;
817 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
818 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
819 S_028800_ZFUNC(state
->depth
.func
);
822 if (state
->stencil
[0].enabled
) {
823 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
824 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
825 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
826 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
827 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
829 if (state
->stencil
[1].enabled
) {
830 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
831 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
832 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
833 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
834 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
839 alpha_test_control
= 0;
841 if (state
->alpha
.enabled
) {
842 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
843 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
844 alpha_ref
= fui(state
->alpha
.ref_value
);
846 dsa
->sx_alpha_test_control
= alpha_test_control
& 0xff;
847 dsa
->alpha_ref
= alpha_ref
;
849 r600_pipe_state_add_reg(rstate
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
853 static void *r600_create_rs_state(struct pipe_context
*ctx
,
854 const struct pipe_rasterizer_state
*state
)
856 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
857 struct r600_pipe_rasterizer
*rs
= CALLOC_STRUCT(r600_pipe_rasterizer
);
858 struct r600_pipe_state
*rstate
;
860 unsigned prov_vtx
= 1, polygon_dual_mode
;
861 unsigned sc_mode_cntl
;
862 float psize_min
, psize_max
;
868 polygon_dual_mode
= (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
869 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
);
871 if (state
->flatshade_first
)
874 rstate
= &rs
->rstate
;
875 rs
->flatshade
= state
->flatshade
;
876 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
877 rs
->two_side
= state
->light_twoside
;
878 rs
->clip_plane_enable
= state
->clip_plane_enable
;
879 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
880 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
881 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
882 rs
->pa_cl_clip_cntl
=
883 S_028810_PS_UCP_MODE(3) |
884 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
885 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
886 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
887 rs
->multisample_enable
= state
->multisample
;
890 rs
->offset_units
= state
->offset_units
;
891 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
893 rstate
->id
= R600_PIPE_STATE_RASTERIZER
;
894 tmp
= S_0286D4_FLAT_SHADE_ENA(1);
895 if (state
->sprite_coord_enable
) {
896 tmp
|= S_0286D4_PNT_SPRITE_ENA(1) |
897 S_0286D4_PNT_SPRITE_OVRD_X(2) |
898 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
899 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
900 S_0286D4_PNT_SPRITE_OVRD_W(1);
901 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
902 tmp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
905 r600_pipe_state_add_reg(rstate
, R_0286D4_SPI_INTERP_CONTROL_0
, tmp
);
907 /* point size 12.4 fixed point */
908 tmp
= r600_pack_float_12p4(state
->point_size
/2);
909 r600_pipe_state_add_reg(rstate
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
911 if (state
->point_size_per_vertex
) {
912 psize_min
= util_get_min_point_size(state
);
915 /* Force the point size to be as if the vertex output was disabled. */
916 psize_min
= state
->point_size
;
917 psize_max
= state
->point_size
;
919 /* Divide by two, because 0.5 = 1 pixel. */
920 r600_pipe_state_add_reg(rstate
, R_028A04_PA_SU_POINT_MINMAX
,
921 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
922 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
924 tmp
= r600_pack_float_12p4(state
->line_width
/2);
925 r600_pipe_state_add_reg(rstate
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
));
927 if (rctx
->chip_class
>= R700
) {
929 S_028A4C_MSAA_ENABLE(state
->multisample
) |
930 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
931 S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
932 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
933 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state
->scissor
);
936 S_028A4C_MSAA_ENABLE(state
->multisample
) |
937 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
938 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
939 rs
->scissor_enable
= state
->scissor
;
941 sc_mode_cntl
|= S_028A4C_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
);
943 r600_pipe_state_add_reg(rstate
, R_028A4C_PA_SC_MODE_CNTL
, sc_mode_cntl
);
945 r600_pipe_state_add_reg(rstate
, R_028C08_PA_SU_VTX_CNTL
,
946 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
) |
947 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
949 r600_pipe_state_add_reg(rstate
, R_028DFC_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
950 r600_pipe_state_add_reg(rstate
, R_028814_PA_SU_SC_MODE_CNTL
,
951 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
952 S_028814_CULL_FRONT(state
->cull_face
& PIPE_FACE_FRONT
? 1 : 0) |
953 S_028814_CULL_BACK(state
->cull_face
& PIPE_FACE_BACK
? 1 : 0) |
954 S_028814_FACE(!state
->front_ccw
) |
955 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
956 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
957 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
958 S_028814_POLY_MODE(polygon_dual_mode
) |
959 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
960 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)));
961 r600_pipe_state_add_reg(rstate
, R_028350_SX_MISC
, S_028350_MULTIPASS(state
->rasterizer_discard
));
965 static void *r600_create_sampler_state(struct pipe_context
*ctx
,
966 const struct pipe_sampler_state
*state
)
968 struct r600_pipe_sampler_state
*ss
= CALLOC_STRUCT(r600_pipe_sampler_state
);
970 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 4 : 0;
976 ss
->seamless_cube_map
= state
->seamless_cube_map
;
977 ss
->border_color_use
= false;
978 util_pack_color(state
->border_color
.f
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
979 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
980 ss
->tex_sampler_words
[0] = S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
981 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
982 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
983 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
984 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
985 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
986 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
987 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
988 S_03C000_BORDER_COLOR_TYPE(uc
.ui
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0);
989 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
990 ss
->tex_sampler_words
[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 6)) |
991 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 6)) |
992 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 6));
993 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
994 ss
->tex_sampler_words
[2] = S_03C008_TYPE(1);
996 ss
->border_color_use
= true;
997 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
998 ss
->border_color
[0] = fui(state
->border_color
.f
[0]);
999 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
1000 ss
->border_color
[1] = fui(state
->border_color
.f
[1]);
1001 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
1002 ss
->border_color
[2] = fui(state
->border_color
.f
[2]);
1003 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
1004 ss
->border_color
[3] = fui(state
->border_color
.f
[3]);
1009 static struct pipe_sampler_view
*r600_create_sampler_view(struct pipe_context
*ctx
,
1010 struct pipe_resource
*texture
,
1011 const struct pipe_sampler_view
*state
)
1013 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
1014 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
1015 unsigned format
, endian
;
1016 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
1017 unsigned char swizzle
[4], array_mode
= 0, tile_type
= 0;
1018 unsigned width
, height
, depth
, offset_level
, last_level
;
1023 /* initialize base object */
1024 view
->base
= *state
;
1025 view
->base
.texture
= NULL
;
1026 pipe_reference(NULL
, &texture
->reference
);
1027 view
->base
.texture
= texture
;
1028 view
->base
.reference
.count
= 1;
1029 view
->base
.context
= ctx
;
1031 swizzle
[0] = state
->swizzle_r
;
1032 swizzle
[1] = state
->swizzle_g
;
1033 swizzle
[2] = state
->swizzle_b
;
1034 swizzle
[3] = state
->swizzle_a
;
1036 format
= r600_translate_texformat(ctx
->screen
, state
->format
,
1038 &word4
, &yuv_format
);
1039 assert(format
!= ~0);
1045 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
) {
1046 if (!r600_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
1050 tmp
= tmp
->flushed_depth_texture
;
1053 endian
= r600_colorformat_endian_swap(format
);
1055 offset_level
= state
->u
.tex
.first_level
;
1056 last_level
= state
->u
.tex
.last_level
- offset_level
;
1057 width
= tmp
->surface
.level
[offset_level
].npix_x
;
1058 height
= tmp
->surface
.level
[offset_level
].npix_y
;
1059 depth
= tmp
->surface
.level
[offset_level
].npix_z
;
1060 pitch
= tmp
->surface
.level
[offset_level
].nblk_x
* util_format_get_blockwidth(state
->format
);
1061 tile_type
= tmp
->tile_type
;
1063 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
1065 depth
= texture
->array_size
;
1066 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
1067 depth
= texture
->array_size
;
1069 switch (tmp
->surface
.level
[offset_level
].mode
) {
1070 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1071 array_mode
= V_038000_ARRAY_LINEAR_ALIGNED
;
1073 case RADEON_SURF_MODE_1D
:
1074 array_mode
= V_038000_ARRAY_1D_TILED_THIN1
;
1076 case RADEON_SURF_MODE_2D
:
1077 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
1079 case RADEON_SURF_MODE_LINEAR
:
1081 array_mode
= V_038000_ARRAY_LINEAR_GENERAL
;
1085 view
->tex_resource
= &tmp
->resource
;
1086 view
->tex_resource_words
[0] = (S_038000_DIM(r600_tex_dim(texture
->target
, texture
->nr_samples
)) |
1087 S_038000_TILE_MODE(array_mode
) |
1088 S_038000_TILE_TYPE(tile_type
) |
1089 S_038000_PITCH((pitch
/ 8) - 1) |
1090 S_038000_TEX_WIDTH(width
- 1));
1091 view
->tex_resource_words
[1] = (S_038004_TEX_HEIGHT(height
- 1) |
1092 S_038004_TEX_DEPTH(depth
- 1) |
1093 S_038004_DATA_FORMAT(format
));
1094 view
->tex_resource_words
[2] = tmp
->surface
.level
[offset_level
].offset
>> 8;
1095 if (offset_level
>= tmp
->surface
.last_level
) {
1096 view
->tex_resource_words
[3] = tmp
->surface
.level
[offset_level
].offset
>> 8;
1098 view
->tex_resource_words
[3] = tmp
->surface
.level
[offset_level
+ 1].offset
>> 8;
1100 view
->tex_resource_words
[4] = (word4
|
1101 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE
) |
1102 S_038010_REQUEST_SIZE(1) |
1103 S_038010_ENDIAN_SWAP(endian
) |
1104 S_038010_BASE_LEVEL(0));
1105 view
->tex_resource_words
[5] = (S_038014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
1106 S_038014_LAST_ARRAY(state
->u
.tex
.last_layer
));
1107 if (texture
->nr_samples
> 1) {
1108 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1109 view
->tex_resource_words
[5] |= S_038014_LAST_LEVEL(util_logbase2(texture
->nr_samples
));
1111 view
->tex_resource_words
[5] |= S_038014_LAST_LEVEL(last_level
);
1113 view
->tex_resource_words
[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE
) |
1114 S_038018_MAX_ANISO(4 /* max 16 samples */));
1118 static void r600_emit_clip_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1120 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1121 struct pipe_clip_state
*state
= &rctx
->clip_state
.state
;
1123 r600_write_context_reg_seq(cs
, R_028E20_PA_CL_UCP0_X
, 6*4);
1124 r600_write_array(cs
, 6*4, (unsigned*)state
);
1127 static void r600_set_polygon_stipple(struct pipe_context
*ctx
,
1128 const struct pipe_poly_stipple
*state
)
1132 void r600_set_scissor_state(struct r600_context
*rctx
,
1133 const struct pipe_scissor_state
*state
)
1135 struct r600_pipe_state
*rstate
= CALLOC_STRUCT(r600_pipe_state
);
1141 rstate
->id
= R600_PIPE_STATE_SCISSOR
;
1142 tl
= S_028240_TL_X(state
->minx
) | S_028240_TL_Y(state
->miny
) | S_028240_WINDOW_OFFSET_DISABLE(1);
1143 br
= S_028244_BR_X(state
->maxx
) | S_028244_BR_Y(state
->maxy
);
1144 r600_pipe_state_add_reg(rstate
,
1145 R_028250_PA_SC_VPORT_SCISSOR_0_TL
, tl
);
1146 r600_pipe_state_add_reg(rstate
,
1147 R_028254_PA_SC_VPORT_SCISSOR_0_BR
, br
);
1149 free(rctx
->states
[R600_PIPE_STATE_SCISSOR
]);
1150 rctx
->states
[R600_PIPE_STATE_SCISSOR
] = rstate
;
1151 r600_context_pipe_state_set(rctx
, rstate
);
1154 static void r600_pipe_set_scissor_state(struct pipe_context
*ctx
,
1155 const struct pipe_scissor_state
*state
)
1157 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1159 if (rctx
->chip_class
== R600
) {
1160 rctx
->scissor_state
= *state
;
1162 if (!rctx
->scissor_enable
)
1166 r600_set_scissor_state(rctx
, state
);
1169 static struct r600_resource
*r600_buffer_create_helper(struct r600_screen
*rscreen
,
1170 unsigned size
, unsigned alignment
)
1172 struct pipe_resource buffer
;
1174 memset(&buffer
, 0, sizeof buffer
);
1175 buffer
.target
= PIPE_BUFFER
;
1176 buffer
.format
= PIPE_FORMAT_R8_UNORM
;
1177 buffer
.bind
= PIPE_BIND_CUSTOM
;
1178 buffer
.usage
= PIPE_USAGE_STATIC
;
1180 buffer
.width0
= size
;
1183 buffer
.array_size
= 1;
1185 return (struct r600_resource
*)
1186 r600_buffer_create(&rscreen
->screen
, &buffer
, alignment
);
1189 static void r600_init_color_surface(struct r600_context
*rctx
,
1190 struct r600_surface
*surf
,
1191 bool force_cmask_fmask
)
1193 struct r600_screen
*rscreen
= rctx
->screen
;
1194 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1195 unsigned level
= surf
->base
.u
.tex
.level
;
1196 unsigned pitch
, slice
;
1197 unsigned color_info
;
1198 unsigned format
, swap
, ntype
, endian
;
1200 const struct util_format_description
*desc
;
1202 bool blend_bypass
= 0, blend_clamp
= 1;
1204 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
1205 r600_init_flushed_depth_texture(&rctx
->context
, surf
->base
.texture
, NULL
);
1206 rtex
= rtex
->flushed_depth_texture
;
1210 offset
= rtex
->surface
.level
[level
].offset
;
1211 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1212 offset
+= rtex
->surface
.level
[level
].slice_size
*
1213 surf
->base
.u
.tex
.first_layer
;
1215 pitch
= rtex
->surface
.level
[level
].nblk_x
/ 8 - 1;
1216 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1221 switch (rtex
->surface
.level
[level
].mode
) {
1222 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1223 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED
);
1225 case RADEON_SURF_MODE_1D
:
1226 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1
);
1228 case RADEON_SURF_MODE_2D
:
1229 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1
);
1231 case RADEON_SURF_MODE_LINEAR
:
1233 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL
);
1237 desc
= util_format_description(surf
->base
.format
);
1239 for (i
= 0; i
< 4; i
++) {
1240 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1245 ntype
= V_0280A0_NUMBER_UNORM
;
1246 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1247 ntype
= V_0280A0_NUMBER_SRGB
;
1248 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1249 if (desc
->channel
[i
].normalized
)
1250 ntype
= V_0280A0_NUMBER_SNORM
;
1251 else if (desc
->channel
[i
].pure_integer
)
1252 ntype
= V_0280A0_NUMBER_SINT
;
1253 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1254 if (desc
->channel
[i
].normalized
)
1255 ntype
= V_0280A0_NUMBER_UNORM
;
1256 else if (desc
->channel
[i
].pure_integer
)
1257 ntype
= V_0280A0_NUMBER_UINT
;
1260 format
= r600_translate_colorformat(surf
->base
.format
);
1261 assert(format
!= ~0);
1263 swap
= r600_translate_colorswap(surf
->base
.format
);
1266 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1267 endian
= ENDIAN_NONE
;
1269 endian
= r600_colorformat_endian_swap(format
);
1272 /* set blend bypass according to docs if SINT/UINT or
1273 8/24 COLOR variants */
1274 if (ntype
== V_0280A0_NUMBER_UINT
|| ntype
== V_0280A0_NUMBER_SINT
||
1275 format
== V_0280A0_COLOR_8_24
|| format
== V_0280A0_COLOR_24_8
||
1276 format
== V_0280A0_COLOR_X24_8_32_FLOAT
) {
1281 surf
->alphatest_bypass
= ntype
== V_0280A0_NUMBER_UINT
|| ntype
== V_0280A0_NUMBER_SINT
;
1283 color_info
|= S_0280A0_FORMAT(format
) |
1284 S_0280A0_COMP_SWAP(swap
) |
1285 S_0280A0_BLEND_BYPASS(blend_bypass
) |
1286 S_0280A0_BLEND_CLAMP(blend_clamp
) |
1287 S_0280A0_NUMBER_TYPE(ntype
) |
1288 S_0280A0_ENDIAN(endian
);
1290 /* EXPORT_NORM is an optimzation that can be enabled for better
1291 * performance in certain cases
1293 if (rctx
->chip_class
== R600
) {
1294 /* EXPORT_NORM can be enabled if:
1295 * - 11-bit or smaller UNORM/SNORM/SRGB
1296 * - BLEND_CLAMP is enabled
1297 * - BLEND_FLOAT32 is disabled
1299 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1300 (desc
->channel
[i
].size
< 12 &&
1301 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1302 ntype
!= V_0280A0_NUMBER_UINT
&&
1303 ntype
!= V_0280A0_NUMBER_SINT
) &&
1304 G_0280A0_BLEND_CLAMP(color_info
) &&
1305 !G_0280A0_BLEND_FLOAT32(color_info
)) {
1306 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
1307 surf
->export_16bpc
= true;
1310 /* EXPORT_NORM can be enabled if:
1311 * - 11-bit or smaller UNORM/SNORM/SRGB
1312 * - 16-bit or smaller FLOAT
1314 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1315 ((desc
->channel
[i
].size
< 12 &&
1316 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1317 ntype
!= V_0280A0_NUMBER_UINT
&& ntype
!= V_0280A0_NUMBER_SINT
) ||
1318 (desc
->channel
[i
].size
< 17 &&
1319 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
1320 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
1321 surf
->export_16bpc
= true;
1325 /* These might not always be initialized to zero. */
1326 surf
->cb_color_base
= offset
>> 8;
1327 surf
->cb_color_size
= S_028060_PITCH_TILE_MAX(pitch
) |
1328 S_028060_SLICE_TILE_MAX(slice
);
1329 surf
->cb_color_fmask
= surf
->cb_color_base
;
1330 surf
->cb_color_cmask
= surf
->cb_color_base
;
1331 surf
->cb_color_mask
= 0;
1333 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
,
1334 &rtex
->resource
.b
.b
);
1335 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
,
1336 &rtex
->resource
.b
.b
);
1338 if (rtex
->cmask_size
) {
1339 surf
->cb_color_cmask
= rtex
->cmask_offset
>> 8;
1340 surf
->cb_color_mask
|= S_028100_CMASK_BLOCK_MAX(rtex
->cmask_slice_tile_max
);
1342 if (rtex
->fmask_size
) {
1343 color_info
|= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE
);
1344 surf
->cb_color_fmask
= rtex
->fmask_offset
>> 8;
1345 surf
->cb_color_mask
|= S_028100_FMASK_TILE_MAX(slice
);
1346 } else { /* cmask only */
1347 color_info
|= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE
);
1349 } else if (force_cmask_fmask
) {
1350 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1352 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1353 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1354 * because it's not an MSAA buffer.
1356 struct r600_cmask_info cmask
;
1357 struct r600_fmask_info fmask
;
1359 r600_texture_get_cmask_info(rscreen
, rtex
, &cmask
);
1360 r600_texture_get_fmask_info(rscreen
, rtex
, 8, &fmask
);
1363 if (!rctx
->dummy_cmask
||
1364 rctx
->dummy_cmask
->buf
->size
< cmask
.size
||
1365 rctx
->dummy_cmask
->buf
->alignment
% cmask
.alignment
!= 0) {
1366 struct pipe_transfer
*transfer
;
1369 pipe_resource_reference((struct pipe_resource
**)&rctx
->dummy_cmask
, NULL
);
1370 rctx
->dummy_cmask
= r600_buffer_create_helper(rscreen
, cmask
.size
, cmask
.alignment
);
1372 /* Set the contents to 0xCC. */
1373 ptr
= pipe_buffer_map(&rctx
->context
, &rctx
->dummy_cmask
->b
.b
, PIPE_TRANSFER_WRITE
, &transfer
);
1374 memset(ptr
, 0xCC, cmask
.size
);
1375 pipe_buffer_unmap(&rctx
->context
, transfer
);
1377 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
,
1378 &rctx
->dummy_cmask
->b
.b
);
1381 if (!rctx
->dummy_fmask
||
1382 rctx
->dummy_fmask
->buf
->size
< fmask
.size
||
1383 rctx
->dummy_fmask
->buf
->alignment
% fmask
.alignment
!= 0) {
1384 pipe_resource_reference((struct pipe_resource
**)&rctx
->dummy_fmask
, NULL
);
1385 rctx
->dummy_fmask
= r600_buffer_create_helper(rscreen
, fmask
.size
, fmask
.alignment
);
1388 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
,
1389 &rctx
->dummy_fmask
->b
.b
);
1391 /* Init the registers. */
1392 color_info
|= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE
);
1393 surf
->cb_color_cmask
= 0;
1394 surf
->cb_color_fmask
= 0;
1395 surf
->cb_color_mask
= S_028100_CMASK_BLOCK_MAX(cmask
.slice_tile_max
) |
1396 S_028100_FMASK_TILE_MAX(slice
);
1399 surf
->cb_color_info
= color_info
;
1401 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1402 surf
->cb_color_view
= 0;
1404 surf
->cb_color_view
= S_028080_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1405 S_028080_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1408 surf
->color_initialized
= true;
1411 static void r600_init_depth_surface(struct r600_context
*rctx
,
1412 struct r600_surface
*surf
)
1414 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1415 unsigned level
, pitch
, slice
, format
, offset
, array_mode
;
1417 level
= surf
->base
.u
.tex
.level
;
1418 offset
= rtex
->surface
.level
[level
].offset
;
1419 pitch
= rtex
->surface
.level
[level
].nblk_x
/ 8 - 1;
1420 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1424 switch (rtex
->surface
.level
[level
].mode
) {
1425 case RADEON_SURF_MODE_2D
:
1426 array_mode
= V_0280A0_ARRAY_2D_TILED_THIN1
;
1428 case RADEON_SURF_MODE_1D
:
1429 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1430 case RADEON_SURF_MODE_LINEAR
:
1432 array_mode
= V_0280A0_ARRAY_1D_TILED_THIN1
;
1436 format
= r600_translate_dbformat(surf
->base
.format
);
1437 assert(format
!= ~0);
1439 surf
->db_depth_info
= S_028010_ARRAY_MODE(array_mode
) | S_028010_FORMAT(format
);
1440 surf
->db_depth_base
= offset
>> 8;
1441 surf
->db_depth_view
= S_028004_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1442 S_028004_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1443 surf
->db_depth_size
= S_028000_PITCH_TILE_MAX(pitch
) | S_028000_SLICE_TILE_MAX(slice
);
1444 surf
->db_prefetch_limit
= (rtex
->surface
.level
[level
].nblk_y
/ 8) - 1;
1446 surf
->depth_initialized
= true;
1449 static void r600_set_framebuffer_state(struct pipe_context
*ctx
,
1450 const struct pipe_framebuffer_state
*state
)
1452 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1453 struct r600_surface
*surf
;
1454 struct r600_texture
*rtex
;
1457 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1458 rctx
->flags
|= R600_CONTEXT_CB_FLUSH
;
1460 if (rctx
->framebuffer
.state
.zsbuf
) {
1461 rctx
->flags
|= R600_CONTEXT_DB_FLUSH
;
1464 if (rctx
->chip_class
== R600
) {
1465 rctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV
;
1468 /* Set the new state. */
1469 util_copy_framebuffer_state(&rctx
->framebuffer
.state
, state
);
1471 rctx
->framebuffer
.export_16bpc
= state
->nr_cbufs
!= 0;
1472 rctx
->framebuffer
.cb0_is_integer
= state
->nr_cbufs
&&
1473 util_format_is_pure_integer(state
->cbufs
[0]->format
);
1474 rctx
->framebuffer
.compressed_cb_mask
= 0;
1475 rctx
->framebuffer
.is_msaa_resolve
= state
->nr_cbufs
== 2 &&
1476 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
1477 state
->cbufs
[1]->texture
->nr_samples
<= 1;
1479 if (state
->nr_cbufs
)
1480 rctx
->framebuffer
.nr_samples
= state
->cbufs
[0]->texture
->nr_samples
;
1481 else if (state
->zsbuf
)
1482 rctx
->framebuffer
.nr_samples
= state
->zsbuf
->texture
->nr_samples
;
1484 rctx
->framebuffer
.nr_samples
= 0;
1487 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
1488 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1489 bool force_cmask_fmask
= rctx
->chip_class
== R600
&&
1490 rctx
->framebuffer
.is_msaa_resolve
&&
1493 surf
= (struct r600_surface
*)state
->cbufs
[i
];
1494 rtex
= (struct r600_texture
*)surf
->base
.texture
;
1496 if (!surf
->color_initialized
|| force_cmask_fmask
) {
1497 r600_init_color_surface(rctx
, surf
, force_cmask_fmask
);
1498 if (force_cmask_fmask
) {
1499 /* re-initialize later without compression */
1500 surf
->color_initialized
= false;
1504 if (!surf
->export_16bpc
) {
1505 rctx
->framebuffer
.export_16bpc
= false;
1508 if (rtex
->fmask_size
&& rtex
->cmask_size
) {
1509 rctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
1513 /* Update alpha-test state dependencies.
1514 * Alpha-test is done on the first colorbuffer only. */
1515 if (state
->nr_cbufs
) {
1516 surf
= (struct r600_surface
*)state
->cbufs
[0];
1517 if (rctx
->alphatest_state
.bypass
!= surf
->alphatest_bypass
) {
1518 rctx
->alphatest_state
.bypass
= surf
->alphatest_bypass
;
1519 r600_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1525 surf
= (struct r600_surface
*)state
->zsbuf
;
1527 if (!surf
->depth_initialized
) {
1528 r600_init_depth_surface(rctx
, surf
);
1531 r600_polygon_offset_update(rctx
);
1534 if (rctx
->cb_misc_state
.nr_cbufs
!= state
->nr_cbufs
) {
1535 rctx
->cb_misc_state
.nr_cbufs
= state
->nr_cbufs
;
1536 r600_atom_dirty(rctx
, &rctx
->cb_misc_state
.atom
);
1539 if (state
->nr_cbufs
== 0 && rctx
->alphatest_state
.bypass
) {
1540 rctx
->alphatest_state
.bypass
= false;
1541 r600_atom_dirty(rctx
, &rctx
->alphatest_state
.atom
);
1544 /* Calculate the CS size. */
1545 rctx
->framebuffer
.atom
.num_dw
=
1546 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1548 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1549 rctx
->framebuffer
.atom
.num_dw
+= 6 * (2 + rctx
->framebuffer
.state
.nr_cbufs
);
1550 rctx
->framebuffer
.atom
.num_dw
+= 6 * rctx
->framebuffer
.state
.nr_cbufs
; /* relocs */
1553 if (rctx
->framebuffer
.state
.zsbuf
) {
1554 rctx
->framebuffer
.atom
.num_dw
+= 13;
1555 } else if (rctx
->screen
->info
.drm_minor
>= 18) {
1556 rctx
->framebuffer
.atom
.num_dw
+= 3;
1558 if (rctx
->family
> CHIP_R600
&& rctx
->family
< CHIP_RV770
) {
1559 rctx
->framebuffer
.atom
.num_dw
+= 2;
1562 r600_atom_dirty(rctx
, &rctx
->framebuffer
.atom
);
1565 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1566 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1567 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1568 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1569 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1571 static void r600_emit_msaa_state(struct r600_context
*rctx
, int nr_samples
)
1573 static uint32_t sample_locs_2x
[] = {
1574 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1575 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1577 static unsigned max_dist_2x
= 4;
1578 static uint32_t sample_locs_4x
[] = {
1579 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1580 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1582 static unsigned max_dist_4x
= 6;
1583 static uint32_t sample_locs_8x
[] = {
1584 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1585 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1587 static unsigned max_dist_8x
= 8;
1589 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1590 unsigned max_dist
= 0;
1592 if (rctx
->family
== CHIP_R600
) {
1593 switch (nr_samples
) {
1598 r600_write_config_reg(cs
, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S
, sample_locs_2x
[0]);
1599 max_dist
= max_dist_2x
;
1602 r600_write_config_reg(cs
, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S
, sample_locs_4x
[0]);
1603 max_dist
= max_dist_4x
;
1606 r600_write_config_reg_seq(cs
, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0
, 2);
1607 r600_write_value(cs
, sample_locs_8x
[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1608 r600_write_value(cs
, sample_locs_8x
[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1609 max_dist
= max_dist_8x
;
1613 switch (nr_samples
) {
1615 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1616 r600_write_value(cs
, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1617 r600_write_value(cs
, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1621 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1622 r600_write_value(cs
, sample_locs_2x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1623 r600_write_value(cs
, sample_locs_2x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1624 max_dist
= max_dist_2x
;
1627 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1628 r600_write_value(cs
, sample_locs_4x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1629 r600_write_value(cs
, sample_locs_4x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1630 max_dist
= max_dist_4x
;
1633 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1634 r600_write_value(cs
, sample_locs_8x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1635 r600_write_value(cs
, sample_locs_8x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1636 max_dist
= max_dist_8x
;
1641 if (nr_samples
> 1) {
1642 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1643 r600_write_value(cs
, S_028C00_LAST_PIXEL(1) |
1644 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1645 r600_write_value(cs
, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples
)) |
1646 S_028C04_MAX_SAMPLE_DIST(max_dist
)); /* R_028C04_PA_SC_AA_CONFIG */
1648 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1649 r600_write_value(cs
, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1650 r600_write_value(cs
, 0); /* R_028C04_PA_SC_AA_CONFIG */
1654 static void r600_emit_framebuffer_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1656 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1657 struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
.state
;
1658 unsigned nr_cbufs
= state
->nr_cbufs
;
1659 struct r600_surface
**cb
= (struct r600_surface
**)&state
->cbufs
[0];
1660 unsigned i
, sbu
= 0;
1663 r600_write_context_reg_seq(cs
, R_0280A0_CB_COLOR0_INFO
, 8);
1664 for (i
= 0; i
< nr_cbufs
; i
++) {
1665 r600_write_value(cs
, cb
[i
]->cb_color_info
);
1667 /* set CB_COLOR1_INFO for possible dual-src blending */
1669 r600_write_value(cs
, cb
[0]->cb_color_info
);
1672 for (; i
< 8; i
++) {
1673 r600_write_value(cs
, 0);
1678 r600_write_context_reg_seq(cs
, R_028040_CB_COLOR0_BASE
, nr_cbufs
);
1679 for (i
= 0; i
< nr_cbufs
; i
++) {
1680 r600_write_value(cs
, cb
[i
]->cb_color_base
);
1684 for (i
= 0; i
< nr_cbufs
; i
++) {
1685 unsigned reloc
= r600_context_bo_reloc(rctx
,
1686 (struct r600_resource
*)cb
[i
]->base
.texture
,
1687 RADEON_USAGE_READWRITE
);
1688 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1689 r600_write_value(cs
, reloc
);
1692 r600_write_context_reg_seq(cs
, R_028060_CB_COLOR0_SIZE
, nr_cbufs
);
1693 for (i
= 0; i
< nr_cbufs
; i
++) {
1694 r600_write_value(cs
, cb
[i
]->cb_color_size
);
1697 r600_write_context_reg_seq(cs
, R_028080_CB_COLOR0_VIEW
, nr_cbufs
);
1698 for (i
= 0; i
< nr_cbufs
; i
++) {
1699 r600_write_value(cs
, cb
[i
]->cb_color_view
);
1702 r600_write_context_reg_seq(cs
, R_028100_CB_COLOR0_MASK
, nr_cbufs
);
1703 for (i
= 0; i
< nr_cbufs
; i
++) {
1704 r600_write_value(cs
, cb
[i
]->cb_color_mask
);
1708 r600_write_context_reg_seq(cs
, R_0280E0_CB_COLOR0_FRAG
, nr_cbufs
);
1709 for (i
= 0; i
< nr_cbufs
; i
++) {
1710 r600_write_value(cs
, cb
[i
]->cb_color_fmask
);
1713 for (i
= 0; i
< nr_cbufs
; i
++) {
1714 unsigned reloc
= r600_context_bo_reloc(rctx
,
1715 cb
[i
]->cb_buffer_fmask
,
1716 RADEON_USAGE_READWRITE
);
1717 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1718 r600_write_value(cs
, reloc
);
1722 r600_write_context_reg_seq(cs
, R_0280C0_CB_COLOR0_TILE
, nr_cbufs
);
1723 for (i
= 0; i
< nr_cbufs
; i
++) {
1724 r600_write_value(cs
, cb
[i
]->cb_color_cmask
);
1727 for (i
= 0; i
< nr_cbufs
; i
++) {
1728 unsigned reloc
= r600_context_bo_reloc(rctx
,
1729 cb
[i
]->cb_buffer_cmask
,
1730 RADEON_USAGE_READWRITE
);
1731 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1732 r600_write_value(cs
, reloc
);
1735 sbu
|= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs
);
1740 struct r600_surface
*surf
= (struct r600_surface
*)state
->zsbuf
;
1741 unsigned reloc
= r600_context_bo_reloc(rctx
,
1742 (struct r600_resource
*)state
->zsbuf
->texture
,
1743 RADEON_USAGE_READWRITE
);
1745 r600_write_context_reg_seq(cs
, R_028000_DB_DEPTH_SIZE
, 2);
1746 r600_write_value(cs
, surf
->db_depth_size
); /* R_028000_DB_DEPTH_SIZE */
1747 r600_write_value(cs
, surf
->db_depth_view
); /* R_028004_DB_DEPTH_VIEW */
1748 r600_write_context_reg_seq(cs
, R_02800C_DB_DEPTH_BASE
, 2);
1749 r600_write_value(cs
, surf
->db_depth_base
); /* R_02800C_DB_DEPTH_BASE */
1750 r600_write_value(cs
, surf
->db_depth_info
); /* R_028010_DB_DEPTH_INFO */
1752 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1753 r600_write_value(cs
, reloc
);
1755 r600_write_context_reg(cs
, R_028D34_DB_PREFETCH_LIMIT
, surf
->db_prefetch_limit
);
1757 sbu
|= SURFACE_BASE_UPDATE_DEPTH
;
1758 } else if (rctx
->screen
->info
.drm_minor
>= 18) {
1759 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1760 * Older kernels are out of luck. */
1761 r600_write_context_reg(cs
, R_028010_DB_DEPTH_INFO
, S_028010_FORMAT(V_028010_DEPTH_INVALID
));
1764 /* SURFACE_BASE_UPDATE */
1765 if (rctx
->family
> CHIP_R600
&& rctx
->family
< CHIP_RV770
&& sbu
) {
1766 r600_write_value(cs
, PKT3(PKT3_SURFACE_BASE_UPDATE
, 0, 0));
1767 r600_write_value(cs
, sbu
);
1770 /* Framebuffer dimensions. */
1771 r600_write_context_reg_seq(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, 2);
1772 r600_write_value(cs
, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1773 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1774 r600_write_value(cs
, S_028244_BR_X(state
->width
) |
1775 S_028244_BR_Y(state
->height
)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1777 if (rctx
->framebuffer
.is_msaa_resolve
) {
1778 r600_write_context_reg(cs
, R_0287A0_CB_SHADER_CONTROL
, 1);
1780 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1781 * will assure that the alpha-test will work even if there is
1782 * no colorbuffer bound. */
1783 r600_write_context_reg(cs
, R_0287A0_CB_SHADER_CONTROL
,
1784 (1ull << MAX2(nr_cbufs
, 1)) - 1);
1787 r600_emit_msaa_state(rctx
, rctx
->framebuffer
.nr_samples
);
1790 static void r600_emit_cb_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1792 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1793 struct r600_cb_misc_state
*a
= (struct r600_cb_misc_state
*)atom
;
1795 if (G_028808_SPECIAL_OP(a
->cb_color_control
) == V_028808_SPECIAL_RESOLVE_BOX
) {
1796 r600_write_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1797 if (rctx
->chip_class
== R600
) {
1798 r600_write_value(cs
, 0xff); /* R_028238_CB_TARGET_MASK */
1799 r600_write_value(cs
, 0xff); /* R_02823C_CB_SHADER_MASK */
1801 r600_write_value(cs
, 0xf); /* R_028238_CB_TARGET_MASK */
1802 r600_write_value(cs
, 0xf); /* R_02823C_CB_SHADER_MASK */
1804 r600_write_context_reg(cs
, R_028808_CB_COLOR_CONTROL
, a
->cb_color_control
);
1806 unsigned fb_colormask
= (1ULL << ((unsigned)a
->nr_cbufs
* 4)) - 1;
1807 unsigned ps_colormask
= (1ULL << ((unsigned)a
->nr_ps_color_outputs
* 4)) - 1;
1808 unsigned multiwrite
= a
->multiwrite
&& a
->nr_cbufs
> 1;
1810 r600_write_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1811 r600_write_value(cs
, a
->blend_colormask
& fb_colormask
); /* R_028238_CB_TARGET_MASK */
1812 /* Always enable the first color output to make sure alpha-test works even without one. */
1813 r600_write_value(cs
, 0xf | (multiwrite
? fb_colormask
: ps_colormask
)); /* R_02823C_CB_SHADER_MASK */
1814 r600_write_context_reg(cs
, R_028808_CB_COLOR_CONTROL
,
1815 a
->cb_color_control
|
1816 S_028808_MULTIWRITE_ENABLE(multiwrite
));
1820 static void r600_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1822 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1823 struct r600_db_misc_state
*a
= (struct r600_db_misc_state
*)atom
;
1824 unsigned db_render_control
= 0;
1825 unsigned db_render_override
=
1826 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE
) |
1827 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE
) |
1828 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE
);
1830 if (a
->occlusion_query_enabled
) {
1831 if (rctx
->chip_class
>= R700
) {
1832 db_render_control
|= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1834 db_render_override
|= S_028D10_NOOP_CULL_DISABLE(1);
1836 if (a
->flush_depthstencil_through_cb
) {
1837 assert(a
->copy_depth
|| a
->copy_stencil
);
1839 db_render_control
|= S_028D0C_DEPTH_COPY_ENABLE(a
->copy_depth
) |
1840 S_028D0C_STENCIL_COPY_ENABLE(a
->copy_stencil
) |
1841 S_028D0C_COPY_CENTROID(1) |
1842 S_028D0C_COPY_SAMPLE(a
->copy_sample
);
1845 r600_write_context_reg_seq(cs
, R_028D0C_DB_RENDER_CONTROL
, 2);
1846 r600_write_value(cs
, db_render_control
); /* R_028D0C_DB_RENDER_CONTROL */
1847 r600_write_value(cs
, db_render_override
); /* R_028D10_DB_RENDER_OVERRIDE */
1850 static void r600_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1852 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1853 uint32_t dirty_mask
= rctx
->vertex_buffer_state
.dirty_mask
;
1855 while (dirty_mask
) {
1856 struct pipe_vertex_buffer
*vb
;
1857 struct r600_resource
*rbuffer
;
1859 unsigned buffer_index
= u_bit_scan(&dirty_mask
);
1861 vb
= &rctx
->vertex_buffer_state
.vb
[buffer_index
];
1862 rbuffer
= (struct r600_resource
*)vb
->buffer
;
1865 offset
= vb
->buffer_offset
;
1867 /* fetch resources start at index 320 */
1868 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1869 r600_write_value(cs
, (320 + buffer_index
) * 7);
1870 r600_write_value(cs
, offset
); /* RESOURCEi_WORD0 */
1871 r600_write_value(cs
, rbuffer
->buf
->size
- offset
- 1); /* RESOURCEi_WORD1 */
1872 r600_write_value(cs
, /* RESOURCEi_WORD2 */
1873 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1874 S_038008_STRIDE(vb
->stride
));
1875 r600_write_value(cs
, 0); /* RESOURCEi_WORD3 */
1876 r600_write_value(cs
, 0); /* RESOURCEi_WORD4 */
1877 r600_write_value(cs
, 0); /* RESOURCEi_WORD5 */
1878 r600_write_value(cs
, 0xc0000000); /* RESOURCEi_WORD6 */
1880 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1881 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
1885 static void r600_emit_constant_buffers(struct r600_context
*rctx
,
1886 struct r600_constbuf_state
*state
,
1887 unsigned buffer_id_base
,
1888 unsigned reg_alu_constbuf_size
,
1889 unsigned reg_alu_const_cache
)
1891 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1892 uint32_t dirty_mask
= state
->dirty_mask
;
1894 while (dirty_mask
) {
1895 struct pipe_constant_buffer
*cb
;
1896 struct r600_resource
*rbuffer
;
1898 unsigned buffer_index
= ffs(dirty_mask
) - 1;
1900 cb
= &state
->cb
[buffer_index
];
1901 rbuffer
= (struct r600_resource
*)cb
->buffer
;
1904 offset
= cb
->buffer_offset
;
1906 r600_write_context_reg(cs
, reg_alu_constbuf_size
+ buffer_index
* 4,
1907 ALIGN_DIVUP(cb
->buffer_size
>> 4, 16));
1908 r600_write_context_reg(cs
, reg_alu_const_cache
+ buffer_index
* 4, offset
>> 8);
1910 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1911 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
1913 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1914 r600_write_value(cs
, (buffer_id_base
+ buffer_index
) * 7);
1915 r600_write_value(cs
, offset
); /* RESOURCEi_WORD0 */
1916 r600_write_value(cs
, rbuffer
->buf
->size
- offset
- 1); /* RESOURCEi_WORD1 */
1917 r600_write_value(cs
, /* RESOURCEi_WORD2 */
1918 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1919 S_038008_STRIDE(16));
1920 r600_write_value(cs
, 0); /* RESOURCEi_WORD3 */
1921 r600_write_value(cs
, 0); /* RESOURCEi_WORD4 */
1922 r600_write_value(cs
, 0); /* RESOURCEi_WORD5 */
1923 r600_write_value(cs
, 0xc0000000); /* RESOURCEi_WORD6 */
1925 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1926 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
1928 dirty_mask
&= ~(1 << buffer_index
);
1930 state
->dirty_mask
= 0;
1933 static void r600_emit_vs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1935 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
], 160,
1936 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
1937 R_028980_ALU_CONST_CACHE_VS_0
);
1940 static void r600_emit_gs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1942 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
], 336,
1943 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
,
1944 R_0289C0_ALU_CONST_CACHE_GS_0
);
1947 static void r600_emit_ps_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1949 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
], 0,
1950 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
1951 R_028940_ALU_CONST_CACHE_PS_0
);
1954 static void r600_emit_sampler_views(struct r600_context
*rctx
,
1955 struct r600_samplerview_state
*state
,
1956 unsigned resource_id_base
)
1958 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1959 uint32_t dirty_mask
= state
->dirty_mask
;
1961 while (dirty_mask
) {
1962 struct r600_pipe_sampler_view
*rview
;
1963 unsigned resource_index
= u_bit_scan(&dirty_mask
);
1966 rview
= state
->views
[resource_index
];
1969 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1970 r600_write_value(cs
, (resource_id_base
+ resource_index
) * 7);
1971 r600_write_array(cs
, 7, rview
->tex_resource_words
);
1973 /* XXX The kernel needs two relocations. This is stupid. */
1974 reloc
= r600_context_bo_reloc(rctx
, rview
->tex_resource
,
1976 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1977 r600_write_value(cs
, reloc
);
1978 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1979 r600_write_value(cs
, reloc
);
1981 state
->dirty_mask
= 0;
1991 static void r600_emit_vs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
1993 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
, 160 + R600_MAX_CONST_BUFFERS
);
1996 static void r600_emit_gs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
1998 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
, 336 + R600_MAX_CONST_BUFFERS
);
2001 static void r600_emit_ps_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2003 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
, R600_MAX_CONST_BUFFERS
);
2006 static void r600_emit_sampler_states(struct r600_context
*rctx
,
2007 struct r600_textures_info
*texinfo
,
2008 unsigned resource_id_base
,
2009 unsigned border_color_reg
)
2011 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2012 uint32_t dirty_mask
= texinfo
->states
.dirty_mask
;
2014 while (dirty_mask
) {
2015 struct r600_pipe_sampler_state
*rstate
;
2016 struct r600_pipe_sampler_view
*rview
;
2017 unsigned i
= u_bit_scan(&dirty_mask
);
2019 rstate
= texinfo
->states
.states
[i
];
2021 rview
= texinfo
->views
.views
[i
];
2023 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
2024 * filtering between layers.
2025 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
2028 enum pipe_texture_target target
= rview
->base
.texture
->target
;
2029 if (target
== PIPE_TEXTURE_1D_ARRAY
||
2030 target
== PIPE_TEXTURE_2D_ARRAY
) {
2031 rstate
->tex_sampler_words
[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
2032 texinfo
->is_array_sampler
[i
] = true;
2034 rstate
->tex_sampler_words
[0] &= C_03C000_TEX_ARRAY_OVERRIDE
;
2035 texinfo
->is_array_sampler
[i
] = false;
2039 r600_write_value(cs
, PKT3(PKT3_SET_SAMPLER
, 3, 0));
2040 r600_write_value(cs
, (resource_id_base
+ i
) * 3);
2041 r600_write_array(cs
, 3, rstate
->tex_sampler_words
);
2043 if (rstate
->border_color_use
) {
2046 offset
= border_color_reg
;
2048 r600_write_config_reg_seq(cs
, offset
, 4);
2049 r600_write_array(cs
, 4, rstate
->border_color
);
2052 texinfo
->states
.dirty_mask
= 0;
2055 static void r600_emit_vs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2057 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED
);
2060 static void r600_emit_gs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2062 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED
);
2065 static void r600_emit_ps_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2067 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED
);
2070 static void r600_emit_seamless_cube_map(struct r600_context
*rctx
, struct r600_atom
*atom
)
2072 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2075 tmp
= S_009508_DISABLE_CUBE_ANISO(1) |
2076 S_009508_SYNC_GRADIENT(1) |
2077 S_009508_SYNC_WALKER(1) |
2078 S_009508_SYNC_ALIGNER(1);
2079 if (!rctx
->seamless_cube_map
.enabled
) {
2080 tmp
|= S_009508_DISABLE_CUBE_WRAP(1);
2082 r600_write_config_reg(cs
, R_009508_TA_CNTL_AUX
, tmp
);
2085 static void r600_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2087 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2088 uint8_t mask
= s
->sample_mask
;
2090 r600_write_context_reg(rctx
->cs
, R_028C48_PA_SC_AA_MASK
,
2091 mask
| (mask
<< 8) | (mask
<< 16) | (mask
<< 24));
2094 void r600_init_state_functions(struct r600_context
*rctx
)
2099 * To avoid GPU lockup registers must be emited in a specific order
2100 * (no kidding ...). The order below is important and have been
2101 * partialy infered from analyzing fglrx command stream.
2103 * Don't reorder atom without carefully checking the effect (GPU lockup
2104 * or piglit regression).
2108 r600_init_atom(rctx
, &rctx
->framebuffer
.atom
, id
++, r600_emit_framebuffer_state
, 0);
2111 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
].atom
, id
++, r600_emit_vs_constant_buffers
, 0);
2112 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
].atom
, id
++, r600_emit_gs_constant_buffers
, 0);
2113 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
].atom
, id
++, r600_emit_ps_constant_buffers
, 0);
2115 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2116 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
2118 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].states
.atom
, id
++, r600_emit_vs_sampler_states
, 0);
2119 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].states
.atom
, id
++, r600_emit_gs_sampler_states
, 0);
2120 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].states
.atom
, id
++, r600_emit_ps_sampler_states
, 0);
2122 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
.atom
, id
++, r600_emit_vs_sampler_views
, 0);
2123 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
.atom
, id
++, r600_emit_gs_sampler_views
, 0);
2124 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.atom
, id
++, r600_emit_ps_sampler_views
, 0);
2125 r600_init_atom(rctx
, &rctx
->vertex_buffer_state
.atom
, id
++, r600_emit_vertex_buffers
, 0);
2127 r600_init_atom(rctx
, &rctx
->vgt_state
.atom
, id
++, r600_emit_vgt_state
, 6);
2128 r600_init_atom(rctx
, &rctx
->vgt2_state
.atom
, id
++, r600_emit_vgt2_state
, 3);
2130 r600_init_atom(rctx
, &rctx
->seamless_cube_map
.atom
, id
++, r600_emit_seamless_cube_map
, 3);
2131 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, r600_emit_sample_mask
, 3);
2132 rctx
->sample_mask
.sample_mask
= ~0;
2134 r600_init_atom(rctx
, &rctx
->alphatest_state
.atom
, id
++, r600_emit_alphatest_state
, 6);
2135 r600_init_atom(rctx
, &rctx
->blend_color
.atom
, id
++, r600_emit_blend_color
, 6);
2136 r600_init_atom(rctx
, &rctx
->cb_misc_state
.atom
, id
++, r600_emit_cb_misc_state
, 7);
2137 r600_init_atom(rctx
, &rctx
->clip_misc_state
.atom
, id
++, r600_emit_clip_misc_state
, 6);
2138 r600_init_atom(rctx
, &rctx
->clip_state
.atom
, id
++, r600_emit_clip_state
, 26);
2139 r600_init_atom(rctx
, &rctx
->db_misc_state
.atom
, id
++, r600_emit_db_misc_state
, 4);
2140 r600_init_atom(rctx
, &rctx
->stencil_ref
.atom
, id
++, r600_emit_stencil_ref
, 4);
2141 r600_init_atom(rctx
, &rctx
->viewport
.atom
, id
++, r600_emit_viewport_state
, 8);
2143 rctx
->context
.create_blend_state
= r600_create_blend_state
;
2144 rctx
->context
.create_depth_stencil_alpha_state
= r600_create_dsa_state
;
2145 rctx
->context
.create_rasterizer_state
= r600_create_rs_state
;
2146 rctx
->context
.create_sampler_state
= r600_create_sampler_state
;
2147 rctx
->context
.create_sampler_view
= r600_create_sampler_view
;
2148 rctx
->context
.set_framebuffer_state
= r600_set_framebuffer_state
;
2149 rctx
->context
.set_polygon_stipple
= r600_set_polygon_stipple
;
2150 rctx
->context
.set_scissor_state
= r600_pipe_set_scissor_state
;
2153 /* Adjust GPR allocation on R6xx/R7xx */
2154 void r600_adjust_gprs(struct r600_context
*rctx
)
2156 struct r600_pipe_state rstate
;
2157 unsigned num_ps_gprs
= rctx
->default_ps_gprs
;
2158 unsigned num_vs_gprs
= rctx
->default_vs_gprs
;
2162 if (rctx
->ps_shader
->current
->shader
.bc
.ngpr
> rctx
->default_ps_gprs
) {
2163 diff
= rctx
->ps_shader
->current
->shader
.bc
.ngpr
- rctx
->default_ps_gprs
;
2164 num_vs_gprs
-= diff
;
2165 num_ps_gprs
+= diff
;
2168 if (rctx
->vs_shader
->current
->shader
.bc
.ngpr
> rctx
->default_vs_gprs
)
2170 diff
= rctx
->vs_shader
->current
->shader
.bc
.ngpr
- rctx
->default_vs_gprs
;
2171 num_ps_gprs
-= diff
;
2172 num_vs_gprs
+= diff
;
2176 tmp
|= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
2177 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
2178 tmp
|= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx
->r6xx_num_clause_temp_gprs
);
2180 r600_pipe_state_add_reg(&rstate
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, tmp
);
2182 r600_context_pipe_state_set(rctx
, &rstate
);
2185 void r600_init_atom_start_cs(struct r600_context
*rctx
)
2200 int num_ps_stack_entries
;
2201 int num_vs_stack_entries
;
2202 int num_gs_stack_entries
;
2203 int num_es_stack_entries
;
2204 enum radeon_family family
;
2205 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2208 r600_init_command_buffer(rctx
, cb
, 0, 256);
2210 /* R6xx requires this packet at the start of each command buffer */
2211 if (rctx
->chip_class
== R600
) {
2212 r600_store_value(cb
, PKT3(PKT3_START_3D_CMDBUF
, 0, 0));
2213 r600_store_value(cb
, 0);
2215 /* All asics require this one */
2216 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2217 r600_store_value(cb
, 0x80000000);
2218 r600_store_value(cb
, 0x80000000);
2220 family
= rctx
->family
;
2232 num_ps_threads
= 136;
2233 num_vs_threads
= 48;
2236 num_ps_stack_entries
= 128;
2237 num_vs_stack_entries
= 128;
2238 num_gs_stack_entries
= 0;
2239 num_es_stack_entries
= 0;
2248 num_ps_threads
= 144;
2249 num_vs_threads
= 40;
2252 num_ps_stack_entries
= 40;
2253 num_vs_stack_entries
= 40;
2254 num_gs_stack_entries
= 32;
2255 num_es_stack_entries
= 16;
2267 num_ps_threads
= 136;
2268 num_vs_threads
= 48;
2271 num_ps_stack_entries
= 40;
2272 num_vs_stack_entries
= 40;
2273 num_gs_stack_entries
= 32;
2274 num_es_stack_entries
= 16;
2282 num_ps_threads
= 136;
2283 num_vs_threads
= 48;
2286 num_ps_stack_entries
= 40;
2287 num_vs_stack_entries
= 40;
2288 num_gs_stack_entries
= 32;
2289 num_es_stack_entries
= 16;
2297 num_ps_threads
= 188;
2298 num_vs_threads
= 60;
2301 num_ps_stack_entries
= 256;
2302 num_vs_stack_entries
= 256;
2303 num_gs_stack_entries
= 0;
2304 num_es_stack_entries
= 0;
2313 num_ps_threads
= 188;
2314 num_vs_threads
= 60;
2317 num_ps_stack_entries
= 128;
2318 num_vs_stack_entries
= 128;
2319 num_gs_stack_entries
= 0;
2320 num_es_stack_entries
= 0;
2328 num_ps_threads
= 144;
2329 num_vs_threads
= 48;
2332 num_ps_stack_entries
= 128;
2333 num_vs_stack_entries
= 128;
2334 num_gs_stack_entries
= 0;
2335 num_es_stack_entries
= 0;
2339 rctx
->default_ps_gprs
= num_ps_gprs
;
2340 rctx
->default_vs_gprs
= num_vs_gprs
;
2341 rctx
->r6xx_num_clause_temp_gprs
= num_temp_gprs
;
2353 tmp
|= S_008C00_VC_ENABLE(1);
2356 tmp
|= S_008C00_DX9_CONSTS(0);
2357 tmp
|= S_008C00_ALU_INST_PREFER_VECTOR(1);
2358 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2359 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2360 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2361 tmp
|= S_008C00_ES_PRIO(es_prio
);
2362 r600_store_config_reg(cb
, R_008C00_SQ_CONFIG
, tmp
);
2364 /* SQ_GPR_RESOURCE_MGMT_2 */
2365 tmp
= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
2366 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
2367 r600_store_config_reg_seq(cb
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, 4);
2368 r600_store_value(cb
, tmp
);
2370 /* SQ_THREAD_RESOURCE_MGMT */
2371 tmp
= S_008C0C_NUM_PS_THREADS(num_ps_threads
);
2372 tmp
|= S_008C0C_NUM_VS_THREADS(num_vs_threads
);
2373 tmp
|= S_008C0C_NUM_GS_THREADS(num_gs_threads
);
2374 tmp
|= S_008C0C_NUM_ES_THREADS(num_es_threads
);
2375 r600_store_value(cb
, tmp
); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2377 /* SQ_STACK_RESOURCE_MGMT_1 */
2378 tmp
= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
2379 tmp
|= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
2380 r600_store_value(cb
, tmp
); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2382 /* SQ_STACK_RESOURCE_MGMT_2 */
2383 tmp
= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
2384 tmp
|= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
2385 r600_store_value(cb
, tmp
); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2387 r600_store_config_reg(cb
, R_009714_VC_ENHANCE
, 0);
2389 if (rctx
->chip_class
>= R700
) {
2390 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0x00004000);
2391 r600_store_config_reg(cb
, R_009830_DB_DEBUG
, 0);
2392 r600_store_config_reg(cb
, R_009838_DB_WATERMARKS
, 0x00420204);
2393 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2395 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0);
2396 r600_store_config_reg(cb
, R_009830_DB_DEBUG
, 0x82000000);
2397 r600_store_config_reg(cb
, R_009838_DB_WATERMARKS
, 0x01020204);
2398 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 1);
2400 r600_store_context_reg_seq(cb
, R_0288A8_SQ_ESGS_RING_ITEMSIZE
, 9);
2401 r600_store_value(cb
, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2402 r600_store_value(cb
, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2403 r600_store_value(cb
, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2404 r600_store_value(cb
, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2405 r600_store_value(cb
, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2406 r600_store_value(cb
, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2407 r600_store_value(cb
, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2408 r600_store_value(cb
, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2409 r600_store_value(cb
, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2411 /* to avoid GPU doing any preloading of constant from random address */
2412 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 8);
2413 r600_store_value(cb
, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2414 r600_store_value(cb
, 0);
2415 r600_store_value(cb
, 0);
2416 r600_store_value(cb
, 0);
2417 r600_store_value(cb
, 0);
2418 r600_store_value(cb
, 0);
2419 r600_store_value(cb
, 0);
2420 r600_store_value(cb
, 0);
2421 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 8);
2422 r600_store_value(cb
, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2423 r600_store_value(cb
, 0);
2424 r600_store_value(cb
, 0);
2425 r600_store_value(cb
, 0);
2426 r600_store_value(cb
, 0);
2427 r600_store_value(cb
, 0);
2428 r600_store_value(cb
, 0);
2429 r600_store_value(cb
, 0);
2431 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2432 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2433 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2434 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2435 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2436 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2437 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2438 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2439 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2440 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2441 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2442 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2443 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2444 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE, 0); */
2446 r600_store_context_reg(cb
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
2447 r600_store_context_reg(cb
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 0);
2448 r600_store_context_reg(cb
, R_028AA4_VGT_INSTANCE_STEP_RATE_1
, 0);
2450 r600_store_context_reg_seq(cb
, R_028AB0_VGT_STRMOUT_EN
, 3);
2451 r600_store_value(cb
, 0); /* R_028AB0_VGT_STRMOUT_EN */
2452 r600_store_value(cb
, 1); /* R_028AB4_VGT_REUSE_OFF */
2453 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2455 r600_store_context_reg(cb
, R_028B20_VGT_STRMOUT_BUFFER_EN
, 0);
2457 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2458 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2459 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2461 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2463 r600_store_context_reg_seq(cb
, R_028028_DB_STENCIL_CLEAR
, 2);
2464 r600_store_value(cb
, 0); /* R_028028_DB_STENCIL_CLEAR */
2465 r600_store_value(cb
, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2467 r600_store_context_reg_seq(cb
, R_0286DC_SPI_FOG_CNTL
, 3);
2468 r600_store_value(cb
, 0); /* R_0286DC_SPI_FOG_CNTL */
2469 r600_store_value(cb
, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2470 r600_store_value(cb
, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2472 r600_store_context_reg_seq(cb
, R_028D2C_DB_SRESULTS_COMPARE_STATE1
, 2);
2473 r600_store_value(cb
, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2474 r600_store_value(cb
, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2476 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2477 r600_store_context_reg(cb
, R_028A48_PA_SC_MPASS_PS_CNTL
, 0);
2479 r600_store_context_reg_seq(cb
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 4);
2480 r600_store_value(cb
, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2481 r600_store_value(cb
, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2482 r600_store_value(cb
, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2483 r600_store_value(cb
, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2485 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
2486 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2487 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2489 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x43F);
2491 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2492 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2494 if (rctx
->chip_class
>= R700
) {
2495 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2498 r600_store_context_reg_seq(cb
, R_028C30_CB_CLRCMP_CONTROL
, 4);
2499 r600_store_value(cb
, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2500 r600_store_value(cb
, 0); /* R_028C34_CB_CLRCMP_SRC */
2501 r600_store_value(cb
, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2502 r600_store_value(cb
, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2504 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2505 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2506 r600_store_value(cb
, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2508 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2509 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2510 r600_store_value(cb
, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2512 r600_store_context_reg_seq(cb
, R_0288CC_SQ_PGM_CF_OFFSET_PS
, 2);
2513 r600_store_value(cb
, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2514 r600_store_value(cb
, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2516 r600_store_context_reg(cb
, R_0288A4_SQ_PGM_RESOURCES_FS
, 0);
2517 r600_store_context_reg(cb
, R_0288DC_SQ_PGM_CF_OFFSET_FS
, 0);
2519 if (rctx
->chip_class
== R700
&& rctx
->screen
->has_streamout
)
2520 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
2521 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2522 if (rctx
->screen
->has_streamout
) {
2523 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2526 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
, 0x1000FFF);
2527 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
+ (32 * 4), 0x1000FFF);
2530 void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2532 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2533 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2534 struct r600_shader
*rshader
= &shader
->shader
;
2535 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
;
2536 int pos_index
= -1, face_index
= -1;
2537 unsigned tmp
, sid
, ufi
= 0;
2538 int need_linear
= 0;
2539 unsigned z_export
= 0, stencil_export
= 0;
2543 for (i
= 0; i
< rshader
->ninput
; i
++) {
2544 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
2546 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
2549 sid
= rshader
->input
[i
].spi_sid
;
2551 tmp
= S_028644_SEMANTIC(sid
);
2553 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
2554 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2555 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
2556 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
))
2557 tmp
|= S_028644_FLAT_SHADE(1);
2559 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
2560 rctx
->sprite_coord_enable
& (1 << rshader
->input
[i
].sid
)) {
2561 tmp
|= S_028644_PT_SPRITE_TEX(1);
2564 if (rshader
->input
[i
].centroid
)
2565 tmp
|= S_028644_SEL_CENTROID(1);
2567 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
) {
2569 tmp
|= S_028644_SEL_LINEAR(1);
2572 r600_pipe_state_add_reg(rstate
, R_028644_SPI_PS_INPUT_CNTL_0
+ i
* 4,
2576 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2577 for (i
= 0; i
< rshader
->noutput
; i
++) {
2578 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2580 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2583 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(z_export
);
2584 db_shader_control
|= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export
);
2585 if (rshader
->uses_kill
)
2586 db_shader_control
|= S_02880C_KILL_ENABLE(1);
2589 for (i
= 0; i
< rshader
->noutput
; i
++) {
2590 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
2591 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
) {
2595 num_cout
= rshader
->nr_ps_color_exports
;
2596 exports_ps
|= S_028854_EXPORT_COLORS(num_cout
);
2598 /* always at least export 1 component per pixel */
2602 shader
->nr_ps_color_outputs
= num_cout
;
2604 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(rshader
->ninput
) |
2605 S_0286CC_PERSP_GRADIENT_ENA(1)|
2606 S_0286CC_LINEAR_GRADIENT_ENA(need_linear
);
2608 if (pos_index
!= -1) {
2609 spi_ps_in_control_0
|= (S_0286CC_POSITION_ENA(1) |
2610 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
2611 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
) |
2612 S_0286CC_BARYC_SAMPLE_CNTL(1));
2616 spi_ps_in_control_1
= 0;
2617 if (face_index
!= -1) {
2618 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
2619 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
2622 /* HW bug in original R600 */
2623 if (rctx
->family
== CHIP_R600
)
2626 r600_pipe_state_add_reg(rstate
, R_0286CC_SPI_PS_IN_CONTROL_0
, spi_ps_in_control_0
);
2627 r600_pipe_state_add_reg(rstate
, R_0286D0_SPI_PS_IN_CONTROL_1
, spi_ps_in_control_1
);
2628 r600_pipe_state_add_reg(rstate
, R_0286D8_SPI_INPUT_Z
, spi_input_z
);
2629 r600_pipe_state_add_reg_bo(rstate
,
2630 R_028840_SQ_PGM_START_PS
,
2631 0, shader
->bo
, RADEON_USAGE_READ
);
2632 r600_pipe_state_add_reg(rstate
,
2633 R_028850_SQ_PGM_RESOURCES_PS
,
2634 S_028850_NUM_GPRS(rshader
->bc
.ngpr
) |
2635 S_028850_STACK_SIZE(rshader
->bc
.nstack
) |
2636 S_028850_UNCACHED_FIRST_INST(ufi
));
2637 r600_pipe_state_add_reg(rstate
,
2638 R_028854_SQ_PGM_EXPORTS_PS
,
2640 /* only set some bits here, the other bits are set in the dsa state */
2641 shader
->db_shader_control
= db_shader_control
;
2642 shader
->ps_depth_export
= z_export
| stencil_export
;
2644 shader
->sprite_coord_enable
= rctx
->sprite_coord_enable
;
2645 if (rctx
->rasterizer
)
2646 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
2649 void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2651 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2652 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2653 struct r600_shader
*rshader
= &shader
->shader
;
2654 unsigned spi_vs_out_id
[10] = {};
2655 unsigned i
, tmp
, nparams
= 0;
2657 /* clear previous register */
2660 for (i
= 0; i
< rshader
->noutput
; i
++) {
2661 if (rshader
->output
[i
].spi_sid
) {
2662 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
2663 spi_vs_out_id
[nparams
/ 4] |= tmp
;
2668 for (i
= 0; i
< 10; i
++) {
2669 r600_pipe_state_add_reg(rstate
,
2670 R_028614_SPI_VS_OUT_ID_0
+ i
* 4,
2674 /* Certain attributes (position, psize, etc.) don't count as params.
2675 * VS is required to export at least one param and r600_shader_from_tgsi()
2676 * takes care of adding a dummy export.
2681 r600_pipe_state_add_reg(rstate
,
2682 R_0286C4_SPI_VS_OUT_CONFIG
,
2683 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
2684 r600_pipe_state_add_reg(rstate
,
2685 R_028868_SQ_PGM_RESOURCES_VS
,
2686 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
2687 S_028868_STACK_SIZE(rshader
->bc
.nstack
));
2688 r600_pipe_state_add_reg_bo(rstate
,
2689 R_028858_SQ_PGM_START_VS
,
2690 0, shader
->bo
, RADEON_USAGE_READ
);
2692 shader
->pa_cl_vs_out_cntl
=
2693 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
2694 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
2695 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
2696 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
);
2699 void r600_fetch_shader(struct pipe_context
*ctx
,
2700 struct r600_vertex_element
*ve
)
2702 struct r600_pipe_state
*rstate
;
2703 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2705 rstate
= &ve
->rstate
;
2706 rstate
->id
= R600_PIPE_STATE_FETCH_SHADER
;
2708 r600_pipe_state_add_reg_bo(rstate
, R_028894_SQ_PGM_START_FS
,
2710 ve
->fetch_shader
, RADEON_USAGE_READ
);
2713 void *r600_create_resolve_blend(struct r600_context
*rctx
)
2715 struct pipe_blend_state blend
;
2716 struct r600_pipe_state
*rstate
;
2719 memset(&blend
, 0, sizeof(blend
));
2720 blend
.independent_blend_enable
= true;
2721 for (i
= 0; i
< 2; i
++) {
2722 blend
.rt
[i
].colormask
= 0xf;
2723 blend
.rt
[i
].blend_enable
= 1;
2724 blend
.rt
[i
].rgb_func
= PIPE_BLEND_ADD
;
2725 blend
.rt
[i
].alpha_func
= PIPE_BLEND_ADD
;
2726 blend
.rt
[i
].rgb_src_factor
= PIPE_BLENDFACTOR_ZERO
;
2727 blend
.rt
[i
].rgb_dst_factor
= PIPE_BLENDFACTOR_ZERO
;
2728 blend
.rt
[i
].alpha_src_factor
= PIPE_BLENDFACTOR_ZERO
;
2729 blend
.rt
[i
].alpha_dst_factor
= PIPE_BLENDFACTOR_ZERO
;
2731 rstate
= r600_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_SPECIAL_RESOLVE_BOX
);
2735 void *r700_create_resolve_blend(struct r600_context
*rctx
)
2737 struct pipe_blend_state blend
;
2738 struct r600_pipe_state
*rstate
;
2740 memset(&blend
, 0, sizeof(blend
));
2741 blend
.independent_blend_enable
= true;
2742 blend
.rt
[0].colormask
= 0xf;
2743 rstate
= r600_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_SPECIAL_RESOLVE_BOX
);
2747 void *r600_create_decompress_blend(struct r600_context
*rctx
)
2749 struct pipe_blend_state blend
;
2750 struct r600_pipe_state
*rstate
;
2752 memset(&blend
, 0, sizeof(blend
));
2753 blend
.independent_blend_enable
= true;
2754 blend
.rt
[0].colormask
= 0xf;
2755 rstate
= r600_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_SPECIAL_EXPAND_SAMPLES
);
2759 void *r600_create_db_flush_dsa(struct r600_context
*rctx
)
2761 struct pipe_depth_stencil_alpha_state dsa
;
2762 boolean quirk
= false;
2764 if (rctx
->family
== CHIP_RV610
|| rctx
->family
== CHIP_RV630
||
2765 rctx
->family
== CHIP_RV620
|| rctx
->family
== CHIP_RV635
)
2768 memset(&dsa
, 0, sizeof(dsa
));
2771 dsa
.depth
.enabled
= 1;
2772 dsa
.depth
.func
= PIPE_FUNC_LEQUAL
;
2773 dsa
.stencil
[0].enabled
= 1;
2774 dsa
.stencil
[0].func
= PIPE_FUNC_ALWAYS
;
2775 dsa
.stencil
[0].zpass_op
= PIPE_STENCIL_OP_KEEP
;
2776 dsa
.stencil
[0].zfail_op
= PIPE_STENCIL_OP_INCR
;
2777 dsa
.stencil
[0].writemask
= 0xff;
2780 return rctx
->context
.create_depth_stencil_alpha_state(&rctx
->context
, &dsa
);
2783 void r600_update_dual_export_state(struct r600_context
* rctx
)
2785 bool dual_export
= rctx
->framebuffer
.export_16bpc
&&
2786 !rctx
->ps_shader
->current
->ps_depth_export
;
2788 unsigned db_shader_control
= rctx
->ps_shader
->current
->db_shader_control
|
2789 S_02880C_DUAL_EXPORT_ENABLE(dual_export
);
2791 if (db_shader_control
!= rctx
->db_shader_control
) {
2792 struct r600_pipe_state rstate
;
2794 rctx
->db_shader_control
= db_shader_control
;
2796 r600_pipe_state_add_reg(&rstate
, R_02880C_DB_SHADER_CONTROL
, db_shader_control
);
2797 r600_context_pipe_state_set(rctx
, &rstate
);