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r600g: atomize fetch shader
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600d.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31
32 static uint32_t r600_translate_blend_function(int blend_func)
33 {
34 switch (blend_func) {
35 case PIPE_BLEND_ADD:
36 return V_028804_COMB_DST_PLUS_SRC;
37 case PIPE_BLEND_SUBTRACT:
38 return V_028804_COMB_SRC_MINUS_DST;
39 case PIPE_BLEND_REVERSE_SUBTRACT:
40 return V_028804_COMB_DST_MINUS_SRC;
41 case PIPE_BLEND_MIN:
42 return V_028804_COMB_MIN_DST_SRC;
43 case PIPE_BLEND_MAX:
44 return V_028804_COMB_MAX_DST_SRC;
45 default:
46 R600_ERR("Unknown blend function %d\n", blend_func);
47 assert(0);
48 break;
49 }
50 return 0;
51 }
52
53 static uint32_t r600_translate_blend_factor(int blend_fact)
54 {
55 switch (blend_fact) {
56 case PIPE_BLENDFACTOR_ONE:
57 return V_028804_BLEND_ONE;
58 case PIPE_BLENDFACTOR_SRC_COLOR:
59 return V_028804_BLEND_SRC_COLOR;
60 case PIPE_BLENDFACTOR_SRC_ALPHA:
61 return V_028804_BLEND_SRC_ALPHA;
62 case PIPE_BLENDFACTOR_DST_ALPHA:
63 return V_028804_BLEND_DST_ALPHA;
64 case PIPE_BLENDFACTOR_DST_COLOR:
65 return V_028804_BLEND_DST_COLOR;
66 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
67 return V_028804_BLEND_SRC_ALPHA_SATURATE;
68 case PIPE_BLENDFACTOR_CONST_COLOR:
69 return V_028804_BLEND_CONST_COLOR;
70 case PIPE_BLENDFACTOR_CONST_ALPHA:
71 return V_028804_BLEND_CONST_ALPHA;
72 case PIPE_BLENDFACTOR_ZERO:
73 return V_028804_BLEND_ZERO;
74 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
75 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
76 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
77 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
78 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
79 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
80 case PIPE_BLENDFACTOR_INV_DST_COLOR:
81 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
82 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
83 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
84 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
85 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
86 case PIPE_BLENDFACTOR_SRC1_COLOR:
87 return V_028804_BLEND_SRC1_COLOR;
88 case PIPE_BLENDFACTOR_SRC1_ALPHA:
89 return V_028804_BLEND_SRC1_ALPHA;
90 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
91 return V_028804_BLEND_INV_SRC1_COLOR;
92 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
93 return V_028804_BLEND_INV_SRC1_ALPHA;
94 default:
95 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
96 assert(0);
97 break;
98 }
99 return 0;
100 }
101
102 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
103 {
104 switch (dim) {
105 default:
106 case PIPE_TEXTURE_1D:
107 return V_038000_SQ_TEX_DIM_1D;
108 case PIPE_TEXTURE_1D_ARRAY:
109 return V_038000_SQ_TEX_DIM_1D_ARRAY;
110 case PIPE_TEXTURE_2D:
111 case PIPE_TEXTURE_RECT:
112 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
113 V_038000_SQ_TEX_DIM_2D;
114 case PIPE_TEXTURE_2D_ARRAY:
115 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
116 V_038000_SQ_TEX_DIM_2D_ARRAY;
117 case PIPE_TEXTURE_3D:
118 return V_038000_SQ_TEX_DIM_3D;
119 case PIPE_TEXTURE_CUBE:
120 return V_038000_SQ_TEX_DIM_CUBEMAP;
121 }
122 }
123
124 static uint32_t r600_translate_dbformat(enum pipe_format format)
125 {
126 switch (format) {
127 case PIPE_FORMAT_Z16_UNORM:
128 return V_028010_DEPTH_16;
129 case PIPE_FORMAT_Z24X8_UNORM:
130 return V_028010_DEPTH_X8_24;
131 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
132 return V_028010_DEPTH_8_24;
133 case PIPE_FORMAT_Z32_FLOAT:
134 return V_028010_DEPTH_32_FLOAT;
135 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
136 return V_028010_DEPTH_X24_8_32_FLOAT;
137 default:
138 return ~0U;
139 }
140 }
141
142 static uint32_t r600_translate_colorswap(enum pipe_format format)
143 {
144 switch (format) {
145 /* 8-bit buffers. */
146 case PIPE_FORMAT_A8_UNORM:
147 case PIPE_FORMAT_A8_SNORM:
148 case PIPE_FORMAT_A8_UINT:
149 case PIPE_FORMAT_A8_SINT:
150 case PIPE_FORMAT_A16_UNORM:
151 case PIPE_FORMAT_A16_SNORM:
152 case PIPE_FORMAT_A16_UINT:
153 case PIPE_FORMAT_A16_SINT:
154 case PIPE_FORMAT_A16_FLOAT:
155 case PIPE_FORMAT_A32_UINT:
156 case PIPE_FORMAT_A32_SINT:
157 case PIPE_FORMAT_A32_FLOAT:
158 case PIPE_FORMAT_R4A4_UNORM:
159 return V_0280A0_SWAP_ALT_REV;
160 case PIPE_FORMAT_I8_UNORM:
161 case PIPE_FORMAT_I8_SNORM:
162 case PIPE_FORMAT_I8_UINT:
163 case PIPE_FORMAT_I8_SINT:
164 case PIPE_FORMAT_L8_UNORM:
165 case PIPE_FORMAT_L8_SNORM:
166 case PIPE_FORMAT_L8_UINT:
167 case PIPE_FORMAT_L8_SINT:
168 case PIPE_FORMAT_L8_SRGB:
169 case PIPE_FORMAT_L16_UNORM:
170 case PIPE_FORMAT_L16_SNORM:
171 case PIPE_FORMAT_L16_UINT:
172 case PIPE_FORMAT_L16_SINT:
173 case PIPE_FORMAT_L16_FLOAT:
174 case PIPE_FORMAT_L32_UINT:
175 case PIPE_FORMAT_L32_SINT:
176 case PIPE_FORMAT_L32_FLOAT:
177 case PIPE_FORMAT_I16_UNORM:
178 case PIPE_FORMAT_I16_SNORM:
179 case PIPE_FORMAT_I16_UINT:
180 case PIPE_FORMAT_I16_SINT:
181 case PIPE_FORMAT_I16_FLOAT:
182 case PIPE_FORMAT_I32_UINT:
183 case PIPE_FORMAT_I32_SINT:
184 case PIPE_FORMAT_I32_FLOAT:
185 case PIPE_FORMAT_R8_UNORM:
186 case PIPE_FORMAT_R8_SNORM:
187 case PIPE_FORMAT_R8_UINT:
188 case PIPE_FORMAT_R8_SINT:
189 return V_0280A0_SWAP_STD;
190
191 case PIPE_FORMAT_L4A4_UNORM:
192 case PIPE_FORMAT_A4R4_UNORM:
193 return V_0280A0_SWAP_ALT;
194
195 /* 16-bit buffers. */
196 case PIPE_FORMAT_B5G6R5_UNORM:
197 return V_0280A0_SWAP_STD_REV;
198
199 case PIPE_FORMAT_B5G5R5A1_UNORM:
200 case PIPE_FORMAT_B5G5R5X1_UNORM:
201 return V_0280A0_SWAP_ALT;
202
203 case PIPE_FORMAT_B4G4R4A4_UNORM:
204 case PIPE_FORMAT_B4G4R4X4_UNORM:
205 return V_0280A0_SWAP_ALT;
206
207 case PIPE_FORMAT_Z16_UNORM:
208 return V_0280A0_SWAP_STD;
209
210 case PIPE_FORMAT_L8A8_UNORM:
211 case PIPE_FORMAT_L8A8_SNORM:
212 case PIPE_FORMAT_L8A8_UINT:
213 case PIPE_FORMAT_L8A8_SINT:
214 case PIPE_FORMAT_L8A8_SRGB:
215 case PIPE_FORMAT_L16A16_UNORM:
216 case PIPE_FORMAT_L16A16_SNORM:
217 case PIPE_FORMAT_L16A16_UINT:
218 case PIPE_FORMAT_L16A16_SINT:
219 case PIPE_FORMAT_L16A16_FLOAT:
220 case PIPE_FORMAT_L32A32_UINT:
221 case PIPE_FORMAT_L32A32_SINT:
222 case PIPE_FORMAT_L32A32_FLOAT:
223 return V_0280A0_SWAP_ALT;
224 case PIPE_FORMAT_R8G8_UNORM:
225 case PIPE_FORMAT_R8G8_SNORM:
226 case PIPE_FORMAT_R8G8_UINT:
227 case PIPE_FORMAT_R8G8_SINT:
228 return V_0280A0_SWAP_STD;
229
230 case PIPE_FORMAT_R16_UNORM:
231 case PIPE_FORMAT_R16_SNORM:
232 case PIPE_FORMAT_R16_UINT:
233 case PIPE_FORMAT_R16_SINT:
234 case PIPE_FORMAT_R16_FLOAT:
235 return V_0280A0_SWAP_STD;
236
237 /* 32-bit buffers. */
238
239 case PIPE_FORMAT_A8B8G8R8_SRGB:
240 return V_0280A0_SWAP_STD_REV;
241 case PIPE_FORMAT_B8G8R8A8_SRGB:
242 return V_0280A0_SWAP_ALT;
243
244 case PIPE_FORMAT_B8G8R8A8_UNORM:
245 case PIPE_FORMAT_B8G8R8X8_UNORM:
246 return V_0280A0_SWAP_ALT;
247
248 case PIPE_FORMAT_A8R8G8B8_UNORM:
249 case PIPE_FORMAT_X8R8G8B8_UNORM:
250 return V_0280A0_SWAP_ALT_REV;
251 case PIPE_FORMAT_R8G8B8A8_SNORM:
252 case PIPE_FORMAT_R8G8B8A8_UNORM:
253 case PIPE_FORMAT_R8G8B8X8_UNORM:
254 case PIPE_FORMAT_R8G8B8A8_SINT:
255 case PIPE_FORMAT_R8G8B8A8_UINT:
256 return V_0280A0_SWAP_STD;
257
258 case PIPE_FORMAT_A8B8G8R8_UNORM:
259 case PIPE_FORMAT_X8B8G8R8_UNORM:
260 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
261 return V_0280A0_SWAP_STD_REV;
262
263 case PIPE_FORMAT_Z24X8_UNORM:
264 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
265 return V_0280A0_SWAP_STD;
266
267 case PIPE_FORMAT_X8Z24_UNORM:
268 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
269 return V_0280A0_SWAP_STD;
270
271 case PIPE_FORMAT_R10G10B10A2_UNORM:
272 case PIPE_FORMAT_R10G10B10X2_SNORM:
273 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
274 return V_0280A0_SWAP_STD;
275
276 case PIPE_FORMAT_B10G10R10A2_UNORM:
277 case PIPE_FORMAT_B10G10R10A2_UINT:
278 return V_0280A0_SWAP_ALT;
279
280 case PIPE_FORMAT_R11G11B10_FLOAT:
281 case PIPE_FORMAT_R16G16_UNORM:
282 case PIPE_FORMAT_R16G16_SNORM:
283 case PIPE_FORMAT_R16G16_FLOAT:
284 case PIPE_FORMAT_R16G16_UINT:
285 case PIPE_FORMAT_R16G16_SINT:
286 case PIPE_FORMAT_R32_UINT:
287 case PIPE_FORMAT_R32_SINT:
288 case PIPE_FORMAT_R32_FLOAT:
289 case PIPE_FORMAT_Z32_FLOAT:
290 return V_0280A0_SWAP_STD;
291
292 /* 64-bit buffers. */
293 case PIPE_FORMAT_R32G32_FLOAT:
294 case PIPE_FORMAT_R32G32_UINT:
295 case PIPE_FORMAT_R32G32_SINT:
296 case PIPE_FORMAT_R16G16B16A16_UNORM:
297 case PIPE_FORMAT_R16G16B16A16_SNORM:
298 case PIPE_FORMAT_R16G16B16A16_UINT:
299 case PIPE_FORMAT_R16G16B16A16_SINT:
300 case PIPE_FORMAT_R16G16B16A16_FLOAT:
301 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
302
303 /* 128-bit buffers. */
304 case PIPE_FORMAT_R32G32B32A32_FLOAT:
305 case PIPE_FORMAT_R32G32B32A32_SNORM:
306 case PIPE_FORMAT_R32G32B32A32_UNORM:
307 case PIPE_FORMAT_R32G32B32A32_SINT:
308 case PIPE_FORMAT_R32G32B32A32_UINT:
309 return V_0280A0_SWAP_STD;
310 default:
311 R600_ERR("unsupported colorswap format %d\n", format);
312 return ~0U;
313 }
314 return ~0U;
315 }
316
317 static uint32_t r600_translate_colorformat(enum pipe_format format)
318 {
319 switch (format) {
320 case PIPE_FORMAT_L4A4_UNORM:
321 case PIPE_FORMAT_R4A4_UNORM:
322 case PIPE_FORMAT_A4R4_UNORM:
323 return V_0280A0_COLOR_4_4;
324
325 /* 8-bit buffers. */
326 case PIPE_FORMAT_A8_UNORM:
327 case PIPE_FORMAT_A8_SNORM:
328 case PIPE_FORMAT_A8_UINT:
329 case PIPE_FORMAT_A8_SINT:
330 case PIPE_FORMAT_I8_UNORM:
331 case PIPE_FORMAT_I8_SNORM:
332 case PIPE_FORMAT_I8_UINT:
333 case PIPE_FORMAT_I8_SINT:
334 case PIPE_FORMAT_L8_UNORM:
335 case PIPE_FORMAT_L8_SNORM:
336 case PIPE_FORMAT_L8_UINT:
337 case PIPE_FORMAT_L8_SINT:
338 case PIPE_FORMAT_L8_SRGB:
339 case PIPE_FORMAT_R8_UNORM:
340 case PIPE_FORMAT_R8_SNORM:
341 case PIPE_FORMAT_R8_UINT:
342 case PIPE_FORMAT_R8_SINT:
343 return V_0280A0_COLOR_8;
344
345 /* 16-bit buffers. */
346 case PIPE_FORMAT_B5G6R5_UNORM:
347 return V_0280A0_COLOR_5_6_5;
348
349 case PIPE_FORMAT_B5G5R5A1_UNORM:
350 case PIPE_FORMAT_B5G5R5X1_UNORM:
351 return V_0280A0_COLOR_1_5_5_5;
352
353 case PIPE_FORMAT_B4G4R4A4_UNORM:
354 case PIPE_FORMAT_B4G4R4X4_UNORM:
355 return V_0280A0_COLOR_4_4_4_4;
356
357 case PIPE_FORMAT_Z16_UNORM:
358 return V_0280A0_COLOR_16;
359
360 case PIPE_FORMAT_L8A8_UNORM:
361 case PIPE_FORMAT_L8A8_SNORM:
362 case PIPE_FORMAT_L8A8_UINT:
363 case PIPE_FORMAT_L8A8_SINT:
364 case PIPE_FORMAT_L8A8_SRGB:
365 case PIPE_FORMAT_R8G8_UNORM:
366 case PIPE_FORMAT_R8G8_SNORM:
367 case PIPE_FORMAT_R8G8_UINT:
368 case PIPE_FORMAT_R8G8_SINT:
369 return V_0280A0_COLOR_8_8;
370
371 case PIPE_FORMAT_R16_UNORM:
372 case PIPE_FORMAT_R16_SNORM:
373 case PIPE_FORMAT_R16_UINT:
374 case PIPE_FORMAT_R16_SINT:
375 case PIPE_FORMAT_A16_UNORM:
376 case PIPE_FORMAT_A16_SNORM:
377 case PIPE_FORMAT_A16_UINT:
378 case PIPE_FORMAT_A16_SINT:
379 case PIPE_FORMAT_L16_UNORM:
380 case PIPE_FORMAT_L16_SNORM:
381 case PIPE_FORMAT_L16_UINT:
382 case PIPE_FORMAT_L16_SINT:
383 case PIPE_FORMAT_I16_UNORM:
384 case PIPE_FORMAT_I16_SNORM:
385 case PIPE_FORMAT_I16_UINT:
386 case PIPE_FORMAT_I16_SINT:
387 return V_0280A0_COLOR_16;
388
389 case PIPE_FORMAT_R16_FLOAT:
390 case PIPE_FORMAT_A16_FLOAT:
391 case PIPE_FORMAT_L16_FLOAT:
392 case PIPE_FORMAT_I16_FLOAT:
393 return V_0280A0_COLOR_16_FLOAT;
394
395 /* 32-bit buffers. */
396 case PIPE_FORMAT_A8B8G8R8_SRGB:
397 case PIPE_FORMAT_A8B8G8R8_UNORM:
398 case PIPE_FORMAT_A8R8G8B8_UNORM:
399 case PIPE_FORMAT_B8G8R8A8_SRGB:
400 case PIPE_FORMAT_B8G8R8A8_UNORM:
401 case PIPE_FORMAT_B8G8R8X8_UNORM:
402 case PIPE_FORMAT_R8G8B8A8_SNORM:
403 case PIPE_FORMAT_R8G8B8A8_UNORM:
404 case PIPE_FORMAT_R8G8B8X8_UNORM:
405 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
406 case PIPE_FORMAT_X8B8G8R8_UNORM:
407 case PIPE_FORMAT_X8R8G8B8_UNORM:
408 case PIPE_FORMAT_R8G8B8A8_SINT:
409 case PIPE_FORMAT_R8G8B8A8_UINT:
410 return V_0280A0_COLOR_8_8_8_8;
411
412 case PIPE_FORMAT_R10G10B10A2_UNORM:
413 case PIPE_FORMAT_R10G10B10X2_SNORM:
414 case PIPE_FORMAT_B10G10R10A2_UNORM:
415 case PIPE_FORMAT_B10G10R10A2_UINT:
416 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
417 return V_0280A0_COLOR_2_10_10_10;
418
419 case PIPE_FORMAT_Z24X8_UNORM:
420 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
421 return V_0280A0_COLOR_8_24;
422
423 case PIPE_FORMAT_X8Z24_UNORM:
424 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
425 return V_0280A0_COLOR_24_8;
426
427 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
428 return V_0280A0_COLOR_X24_8_32_FLOAT;
429
430 case PIPE_FORMAT_R32_UINT:
431 case PIPE_FORMAT_R32_SINT:
432 case PIPE_FORMAT_A32_UINT:
433 case PIPE_FORMAT_A32_SINT:
434 case PIPE_FORMAT_L32_UINT:
435 case PIPE_FORMAT_L32_SINT:
436 case PIPE_FORMAT_I32_UINT:
437 case PIPE_FORMAT_I32_SINT:
438 return V_0280A0_COLOR_32;
439
440 case PIPE_FORMAT_R32_FLOAT:
441 case PIPE_FORMAT_A32_FLOAT:
442 case PIPE_FORMAT_L32_FLOAT:
443 case PIPE_FORMAT_I32_FLOAT:
444 case PIPE_FORMAT_Z32_FLOAT:
445 return V_0280A0_COLOR_32_FLOAT;
446
447 case PIPE_FORMAT_R16G16_FLOAT:
448 case PIPE_FORMAT_L16A16_FLOAT:
449 return V_0280A0_COLOR_16_16_FLOAT;
450
451 case PIPE_FORMAT_R16G16_UNORM:
452 case PIPE_FORMAT_R16G16_SNORM:
453 case PIPE_FORMAT_R16G16_UINT:
454 case PIPE_FORMAT_R16G16_SINT:
455 case PIPE_FORMAT_L16A16_UNORM:
456 case PIPE_FORMAT_L16A16_SNORM:
457 case PIPE_FORMAT_L16A16_UINT:
458 case PIPE_FORMAT_L16A16_SINT:
459 return V_0280A0_COLOR_16_16;
460
461 case PIPE_FORMAT_R11G11B10_FLOAT:
462 return V_0280A0_COLOR_10_11_11_FLOAT;
463
464 /* 64-bit buffers. */
465 case PIPE_FORMAT_R16G16B16A16_UINT:
466 case PIPE_FORMAT_R16G16B16A16_SINT:
467 case PIPE_FORMAT_R16G16B16A16_UNORM:
468 case PIPE_FORMAT_R16G16B16A16_SNORM:
469 return V_0280A0_COLOR_16_16_16_16;
470
471 case PIPE_FORMAT_R16G16B16A16_FLOAT:
472 return V_0280A0_COLOR_16_16_16_16_FLOAT;
473
474 case PIPE_FORMAT_R32G32_FLOAT:
475 case PIPE_FORMAT_L32A32_FLOAT:
476 return V_0280A0_COLOR_32_32_FLOAT;
477
478 case PIPE_FORMAT_R32G32_SINT:
479 case PIPE_FORMAT_R32G32_UINT:
480 case PIPE_FORMAT_L32A32_UINT:
481 case PIPE_FORMAT_L32A32_SINT:
482 return V_0280A0_COLOR_32_32;
483
484 /* 128-bit buffers. */
485 case PIPE_FORMAT_R32G32B32A32_FLOAT:
486 return V_0280A0_COLOR_32_32_32_32_FLOAT;
487 case PIPE_FORMAT_R32G32B32A32_SNORM:
488 case PIPE_FORMAT_R32G32B32A32_UNORM:
489 case PIPE_FORMAT_R32G32B32A32_SINT:
490 case PIPE_FORMAT_R32G32B32A32_UINT:
491 return V_0280A0_COLOR_32_32_32_32;
492
493 /* YUV buffers. */
494 case PIPE_FORMAT_UYVY:
495 case PIPE_FORMAT_YUYV:
496 default:
497 return ~0U; /* Unsupported. */
498 }
499 }
500
501 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
502 {
503 if (R600_BIG_ENDIAN) {
504 switch(colorformat) {
505 case V_0280A0_COLOR_4_4:
506 return ENDIAN_NONE;
507
508 /* 8-bit buffers. */
509 case V_0280A0_COLOR_8:
510 return ENDIAN_NONE;
511
512 /* 16-bit buffers. */
513 case V_0280A0_COLOR_5_6_5:
514 case V_0280A0_COLOR_1_5_5_5:
515 case V_0280A0_COLOR_4_4_4_4:
516 case V_0280A0_COLOR_16:
517 case V_0280A0_COLOR_8_8:
518 return ENDIAN_8IN16;
519
520 /* 32-bit buffers. */
521 case V_0280A0_COLOR_8_8_8_8:
522 case V_0280A0_COLOR_2_10_10_10:
523 case V_0280A0_COLOR_8_24:
524 case V_0280A0_COLOR_24_8:
525 case V_0280A0_COLOR_32_FLOAT:
526 case V_0280A0_COLOR_16_16_FLOAT:
527 case V_0280A0_COLOR_16_16:
528 return ENDIAN_8IN32;
529
530 /* 64-bit buffers. */
531 case V_0280A0_COLOR_16_16_16_16:
532 case V_0280A0_COLOR_16_16_16_16_FLOAT:
533 return ENDIAN_8IN16;
534
535 case V_0280A0_COLOR_32_32_FLOAT:
536 case V_0280A0_COLOR_32_32:
537 case V_0280A0_COLOR_X24_8_32_FLOAT:
538 return ENDIAN_8IN32;
539
540 /* 128-bit buffers. */
541 case V_0280A0_COLOR_32_32_32_FLOAT:
542 case V_0280A0_COLOR_32_32_32_32_FLOAT:
543 case V_0280A0_COLOR_32_32_32_32:
544 return ENDIAN_8IN32;
545 default:
546 return ENDIAN_NONE; /* Unsupported. */
547 }
548 } else {
549 return ENDIAN_NONE;
550 }
551 }
552
553 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
554 {
555 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
556 }
557
558 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
559 {
560 return r600_translate_colorformat(format) != ~0U &&
561 r600_translate_colorswap(format) != ~0U;
562 }
563
564 static bool r600_is_zs_format_supported(enum pipe_format format)
565 {
566 return r600_translate_dbformat(format) != ~0U;
567 }
568
569 boolean r600_is_format_supported(struct pipe_screen *screen,
570 enum pipe_format format,
571 enum pipe_texture_target target,
572 unsigned sample_count,
573 unsigned usage)
574 {
575 struct r600_screen *rscreen = (struct r600_screen*)screen;
576 unsigned retval = 0;
577
578 if (target >= PIPE_MAX_TEXTURE_TYPES) {
579 R600_ERR("r600: unsupported texture type %d\n", target);
580 return FALSE;
581 }
582
583 if (!util_format_is_supported(format, usage))
584 return FALSE;
585
586 if (sample_count > 1) {
587 if (rscreen->info.drm_minor < 22)
588 return FALSE;
589
590 /* R11G11B10 is broken on R6xx. */
591 if (rscreen->chip_class == R600 &&
592 format == PIPE_FORMAT_R11G11B10_FLOAT)
593 return FALSE;
594
595 /* MSAA integer colorbuffers hang. */
596 if (util_format_is_pure_integer(format) &&
597 !util_format_is_depth_or_stencil(format))
598 return FALSE;
599
600 switch (sample_count) {
601 case 2:
602 case 4:
603 case 8:
604 break;
605 default:
606 return FALSE;
607 }
608 }
609
610 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
611 r600_is_sampler_format_supported(screen, format)) {
612 retval |= PIPE_BIND_SAMPLER_VIEW;
613 }
614
615 if ((usage & (PIPE_BIND_RENDER_TARGET |
616 PIPE_BIND_DISPLAY_TARGET |
617 PIPE_BIND_SCANOUT |
618 PIPE_BIND_SHARED)) &&
619 r600_is_colorbuffer_format_supported(format)) {
620 retval |= usage &
621 (PIPE_BIND_RENDER_TARGET |
622 PIPE_BIND_DISPLAY_TARGET |
623 PIPE_BIND_SCANOUT |
624 PIPE_BIND_SHARED);
625 }
626
627 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
628 r600_is_zs_format_supported(format)) {
629 retval |= PIPE_BIND_DEPTH_STENCIL;
630 }
631
632 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
633 r600_is_vertex_format_supported(format)) {
634 retval |= PIPE_BIND_VERTEX_BUFFER;
635 }
636
637 if (usage & PIPE_BIND_TRANSFER_READ)
638 retval |= PIPE_BIND_TRANSFER_READ;
639 if (usage & PIPE_BIND_TRANSFER_WRITE)
640 retval |= PIPE_BIND_TRANSFER_WRITE;
641
642 return retval == usage;
643 }
644
645 void r600_polygon_offset_update(struct r600_context *rctx)
646 {
647 struct r600_pipe_state state;
648
649 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
650 state.nregs = 0;
651 if (rctx->rasterizer && rctx->framebuffer.state.zsbuf) {
652 float offset_units = rctx->rasterizer->offset_units;
653 unsigned offset_db_fmt_cntl = 0, depth;
654
655 switch (rctx->framebuffer.state.zsbuf->format) {
656 case PIPE_FORMAT_Z24X8_UNORM:
657 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
658 depth = -24;
659 offset_units *= 2.0f;
660 break;
661 case PIPE_FORMAT_Z32_FLOAT:
662 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
663 depth = -23;
664 offset_units *= 1.0f;
665 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
666 break;
667 case PIPE_FORMAT_Z16_UNORM:
668 depth = -16;
669 offset_units *= 4.0f;
670 break;
671 default:
672 return;
673 }
674 /* XXX some of those reg can be computed with cso */
675 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
676 r600_pipe_state_add_reg(&state,
677 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
678 fui(rctx->rasterizer->offset_scale));
679 r600_pipe_state_add_reg(&state,
680 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
681 fui(offset_units));
682 r600_pipe_state_add_reg(&state,
683 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
684 fui(rctx->rasterizer->offset_scale));
685 r600_pipe_state_add_reg(&state,
686 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
687 fui(offset_units));
688 r600_pipe_state_add_reg(&state,
689 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
690 offset_db_fmt_cntl);
691 r600_context_pipe_state_set(rctx, &state);
692 }
693 }
694
695 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
696 {
697 int j = state->independent_blend_enable ? i : 0;
698
699 unsigned eqRGB = state->rt[j].rgb_func;
700 unsigned srcRGB = state->rt[j].rgb_src_factor;
701 unsigned dstRGB = state->rt[j].rgb_dst_factor;
702
703 unsigned eqA = state->rt[j].alpha_func;
704 unsigned srcA = state->rt[j].alpha_src_factor;
705 unsigned dstA = state->rt[j].alpha_dst_factor;
706 uint32_t bc = 0;
707
708 if (!state->rt[j].blend_enable)
709 return 0;
710
711 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
712 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
713 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
714
715 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
716 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
717 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
718 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
719 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
720 }
721 return bc;
722 }
723
724 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
725 const struct pipe_blend_state *state,
726 int mode)
727 {
728 struct r600_context *rctx = (struct r600_context *)ctx;
729 uint32_t color_control = 0, target_mask = 0;
730 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
731
732 if (!blend) {
733 return NULL;
734 }
735
736 r600_init_command_buffer(&blend->buffer, 20);
737 r600_init_command_buffer(&blend->buffer_no_blend, 20);
738
739 /* R600 does not support per-MRT blends */
740 if (rctx->family > CHIP_R600)
741 color_control |= S_028808_PER_MRT_BLEND(1);
742
743 if (state->logicop_enable) {
744 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
745 } else {
746 color_control |= (0xcc << 16);
747 }
748 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
749 if (state->independent_blend_enable) {
750 for (int i = 0; i < 8; i++) {
751 if (state->rt[i].blend_enable) {
752 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
753 }
754 target_mask |= (state->rt[i].colormask << (4 * i));
755 }
756 } else {
757 for (int i = 0; i < 8; i++) {
758 if (state->rt[0].blend_enable) {
759 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
760 }
761 target_mask |= (state->rt[0].colormask << (4 * i));
762 }
763 }
764
765 if (target_mask)
766 color_control |= S_028808_SPECIAL_OP(mode);
767 else
768 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
769
770 /* only MRT0 has dual src blend */
771 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
772 blend->cb_target_mask = target_mask;
773 blend->cb_color_control = color_control;
774 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
775 blend->alpha_to_one = state->alpha_to_one;
776
777 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
778 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
779 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
780 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
781 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
782 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
783
784 /* Copy over the registers set so far into buffer_no_blend. */
785 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
786 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
787
788 /* Only add blend registers if blending is enabled. */
789 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
790 return blend;
791 }
792
793 /* The first R600 does not support per-MRT blends */
794 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
795 r600_get_blend_control(state, 0));
796
797 if (rctx->family > CHIP_R600) {
798 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
799 for (int i = 0; i < 8; i++) {
800 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
801 }
802 }
803 return blend;
804 }
805
806 static void *r600_create_blend_state(struct pipe_context *ctx,
807 const struct pipe_blend_state *state)
808 {
809 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
810 }
811
812 static void *r600_create_dsa_state(struct pipe_context *ctx,
813 const struct pipe_depth_stencil_alpha_state *state)
814 {
815 struct r600_context *rctx = (struct r600_context *)ctx;
816 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
817 unsigned db_depth_control, alpha_test_control, alpha_ref;
818 struct r600_pipe_state *rstate;
819
820 if (dsa == NULL) {
821 return NULL;
822 }
823
824 dsa->valuemask[0] = state->stencil[0].valuemask;
825 dsa->valuemask[1] = state->stencil[1].valuemask;
826 dsa->writemask[0] = state->stencil[0].writemask;
827 dsa->writemask[1] = state->stencil[1].writemask;
828
829 rstate = &dsa->rstate;
830
831 rstate->id = R600_PIPE_STATE_DSA;
832 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
833 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
834 S_028800_ZFUNC(state->depth.func);
835
836 /* stencil */
837 if (state->stencil[0].enabled) {
838 db_depth_control |= S_028800_STENCIL_ENABLE(1);
839 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
840 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
841 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
842 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
843
844 if (state->stencil[1].enabled) {
845 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
846 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
847 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
848 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
849 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
850 }
851 }
852
853 /* alpha */
854 alpha_test_control = 0;
855 alpha_ref = 0;
856 if (state->alpha.enabled) {
857 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
858 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
859 alpha_ref = fui(state->alpha.ref_value);
860 }
861 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
862 dsa->alpha_ref = alpha_ref;
863
864 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
865 return rstate;
866 }
867
868 static void *r600_create_rs_state(struct pipe_context *ctx,
869 const struct pipe_rasterizer_state *state)
870 {
871 struct r600_context *rctx = (struct r600_context *)ctx;
872 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
873 struct r600_pipe_state *rstate;
874 unsigned tmp;
875 unsigned prov_vtx = 1, polygon_dual_mode;
876 unsigned sc_mode_cntl;
877 float psize_min, psize_max;
878
879 if (rs == NULL) {
880 return NULL;
881 }
882
883 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
884 state->fill_back != PIPE_POLYGON_MODE_FILL);
885
886 if (state->flatshade_first)
887 prov_vtx = 0;
888
889 rstate = &rs->rstate;
890 rs->flatshade = state->flatshade;
891 rs->sprite_coord_enable = state->sprite_coord_enable;
892 rs->two_side = state->light_twoside;
893 rs->clip_plane_enable = state->clip_plane_enable;
894 rs->pa_sc_line_stipple = state->line_stipple_enable ?
895 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
896 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
897 rs->pa_cl_clip_cntl =
898 S_028810_PS_UCP_MODE(3) |
899 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
900 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
901 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
902 rs->multisample_enable = state->multisample;
903
904 /* offset */
905 rs->offset_units = state->offset_units;
906 rs->offset_scale = state->offset_scale * 12.0f;
907
908 rstate->id = R600_PIPE_STATE_RASTERIZER;
909 tmp = S_0286D4_FLAT_SHADE_ENA(1);
910 if (state->sprite_coord_enable) {
911 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
912 S_0286D4_PNT_SPRITE_OVRD_X(2) |
913 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
914 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
915 S_0286D4_PNT_SPRITE_OVRD_W(1);
916 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
917 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
918 }
919 }
920 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
921
922 /* point size 12.4 fixed point */
923 tmp = r600_pack_float_12p4(state->point_size/2);
924 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
925
926 if (state->point_size_per_vertex) {
927 psize_min = util_get_min_point_size(state);
928 psize_max = 8192;
929 } else {
930 /* Force the point size to be as if the vertex output was disabled. */
931 psize_min = state->point_size;
932 psize_max = state->point_size;
933 }
934 /* Divide by two, because 0.5 = 1 pixel. */
935 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
936 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
937 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
938
939 tmp = r600_pack_float_12p4(state->line_width/2);
940 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
941
942 if (rctx->chip_class >= R700) {
943 sc_mode_cntl =
944 S_028A4C_MSAA_ENABLE(state->multisample) |
945 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
946 S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
947 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
948 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
949 } else {
950 sc_mode_cntl =
951 S_028A4C_MSAA_ENABLE(state->multisample) |
952 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
953 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
954 rs->scissor_enable = state->scissor;
955 }
956 sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
957
958 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
959
960 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
961 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
962 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
963
964 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
965 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
966 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
967 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
968 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
969 S_028814_FACE(!state->front_ccw) |
970 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
971 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
972 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
973 S_028814_POLY_MODE(polygon_dual_mode) |
974 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
975 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
976 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
977 return rstate;
978 }
979
980 static void *r600_create_sampler_state(struct pipe_context *ctx,
981 const struct pipe_sampler_state *state)
982 {
983 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
984 union util_color uc;
985 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
986
987 if (ss == NULL) {
988 return NULL;
989 }
990
991 ss->seamless_cube_map = state->seamless_cube_map;
992 ss->border_color_use = false;
993 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
994 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
995 ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
996 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
997 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
998 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
999 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
1000 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1001 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
1002 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1003 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
1004 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
1005 ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1006 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1007 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
1008 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
1009 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
1010 if (uc.ui) {
1011 ss->border_color_use = true;
1012 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
1013 ss->border_color[0] = fui(state->border_color.f[0]);
1014 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
1015 ss->border_color[1] = fui(state->border_color.f[1]);
1016 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
1017 ss->border_color[2] = fui(state->border_color.f[2]);
1018 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
1019 ss->border_color[3] = fui(state->border_color.f[3]);
1020 }
1021 return ss;
1022 }
1023
1024 struct pipe_sampler_view *
1025 r600_create_sampler_view_custom(struct pipe_context *ctx,
1026 struct pipe_resource *texture,
1027 const struct pipe_sampler_view *state,
1028 unsigned width_first_level, unsigned height_first_level)
1029 {
1030 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1031 struct r600_texture *tmp = (struct r600_texture*)texture;
1032 unsigned format, endian;
1033 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1034 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1035 unsigned width, height, depth, offset_level, last_level;
1036
1037 if (view == NULL)
1038 return NULL;
1039
1040 /* initialize base object */
1041 view->base = *state;
1042 view->base.texture = NULL;
1043 pipe_reference(NULL, &texture->reference);
1044 view->base.texture = texture;
1045 view->base.reference.count = 1;
1046 view->base.context = ctx;
1047
1048 swizzle[0] = state->swizzle_r;
1049 swizzle[1] = state->swizzle_g;
1050 swizzle[2] = state->swizzle_b;
1051 swizzle[3] = state->swizzle_a;
1052
1053 format = r600_translate_texformat(ctx->screen, state->format,
1054 swizzle,
1055 &word4, &yuv_format);
1056 assert(format != ~0);
1057 if (format == ~0) {
1058 FREE(view);
1059 return NULL;
1060 }
1061
1062 if (tmp->is_depth && !tmp->is_flushing_texture) {
1063 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1064 FREE(view);
1065 return NULL;
1066 }
1067 tmp = tmp->flushed_depth_texture;
1068 }
1069
1070 endian = r600_colorformat_endian_swap(format);
1071
1072 offset_level = state->u.tex.first_level;
1073 last_level = state->u.tex.last_level - offset_level;
1074 width = width_first_level;
1075 height = height_first_level;
1076 depth = tmp->surface.level[offset_level].npix_z;
1077 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1078 tile_type = tmp->tile_type;
1079
1080 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1081 height = 1;
1082 depth = texture->array_size;
1083 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1084 depth = texture->array_size;
1085 }
1086 switch (tmp->surface.level[offset_level].mode) {
1087 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1088 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1089 break;
1090 case RADEON_SURF_MODE_1D:
1091 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1092 break;
1093 case RADEON_SURF_MODE_2D:
1094 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1095 break;
1096 case RADEON_SURF_MODE_LINEAR:
1097 default:
1098 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1099 break;
1100 }
1101
1102 view->tex_resource = &tmp->resource;
1103 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1104 S_038000_TILE_MODE(array_mode) |
1105 S_038000_TILE_TYPE(tile_type) |
1106 S_038000_PITCH((pitch / 8) - 1) |
1107 S_038000_TEX_WIDTH(width - 1));
1108 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
1109 S_038004_TEX_DEPTH(depth - 1) |
1110 S_038004_DATA_FORMAT(format));
1111 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
1112 if (offset_level >= tmp->surface.last_level) {
1113 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
1114 } else {
1115 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1116 }
1117 view->tex_resource_words[4] = (word4 |
1118 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1119 S_038010_REQUEST_SIZE(1) |
1120 S_038010_ENDIAN_SWAP(endian) |
1121 S_038010_BASE_LEVEL(0));
1122 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1123 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1124 if (texture->nr_samples > 1) {
1125 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1126 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
1127 } else {
1128 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
1129 }
1130 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1131 S_038018_MAX_ANISO(4 /* max 16 samples */));
1132 return &view->base;
1133 }
1134
1135 static struct pipe_sampler_view *
1136 r600_create_sampler_view(struct pipe_context *ctx,
1137 struct pipe_resource *tex,
1138 const struct pipe_sampler_view *state)
1139 {
1140 struct r600_texture *rtex = (struct r600_texture*)tex;
1141
1142 return r600_create_sampler_view_custom(ctx, tex, state,
1143 rtex->surface.level[state->u.tex.first_level].npix_x,
1144 rtex->surface.level[state->u.tex.first_level].npix_y);
1145 }
1146
1147 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1148 {
1149 struct radeon_winsys_cs *cs = rctx->cs;
1150 struct pipe_clip_state *state = &rctx->clip_state.state;
1151
1152 r600_write_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
1153 r600_write_array(cs, 6*4, (unsigned*)state);
1154 }
1155
1156 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1157 const struct pipe_poly_stipple *state)
1158 {
1159 }
1160
1161 void r600_set_scissor_state(struct r600_context *rctx,
1162 const struct pipe_scissor_state *state)
1163 {
1164 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1165 uint32_t tl, br;
1166
1167 if (rstate == NULL)
1168 return;
1169
1170 rstate->id = R600_PIPE_STATE_SCISSOR;
1171 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1172 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1173 r600_pipe_state_add_reg(rstate,
1174 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1175 r600_pipe_state_add_reg(rstate,
1176 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1177
1178 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1179 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1180 r600_context_pipe_state_set(rctx, rstate);
1181 }
1182
1183 static void r600_pipe_set_scissor_state(struct pipe_context *ctx,
1184 const struct pipe_scissor_state *state)
1185 {
1186 struct r600_context *rctx = (struct r600_context *)ctx;
1187
1188 rctx->scissor = *state;
1189
1190 if (rctx->chip_class == R600 && !rctx->scissor_enable)
1191 return;
1192
1193 r600_set_scissor_state(rctx, state);
1194 }
1195
1196 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
1197 unsigned size, unsigned alignment)
1198 {
1199 struct pipe_resource buffer;
1200
1201 memset(&buffer, 0, sizeof buffer);
1202 buffer.target = PIPE_BUFFER;
1203 buffer.format = PIPE_FORMAT_R8_UNORM;
1204 buffer.bind = PIPE_BIND_CUSTOM;
1205 buffer.usage = PIPE_USAGE_STATIC;
1206 buffer.flags = 0;
1207 buffer.width0 = size;
1208 buffer.height0 = 1;
1209 buffer.depth0 = 1;
1210 buffer.array_size = 1;
1211
1212 return (struct r600_resource*)
1213 r600_buffer_create(&rscreen->screen, &buffer, alignment);
1214 }
1215
1216 static void r600_init_color_surface(struct r600_context *rctx,
1217 struct r600_surface *surf,
1218 bool force_cmask_fmask)
1219 {
1220 struct r600_screen *rscreen = rctx->screen;
1221 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1222 unsigned level = surf->base.u.tex.level;
1223 unsigned pitch, slice;
1224 unsigned color_info;
1225 unsigned format, swap, ntype, endian;
1226 unsigned offset;
1227 const struct util_format_description *desc;
1228 int i;
1229 bool blend_bypass = 0, blend_clamp = 1;
1230
1231 if (rtex->is_depth && !rtex->is_flushing_texture) {
1232 r600_init_flushed_depth_texture(&rctx->context, surf->base.texture, NULL);
1233 rtex = rtex->flushed_depth_texture;
1234 assert(rtex);
1235 }
1236
1237 offset = rtex->surface.level[level].offset;
1238 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1239 offset += rtex->surface.level[level].slice_size *
1240 surf->base.u.tex.first_layer;
1241 }
1242 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1243 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1244 if (slice) {
1245 slice = slice - 1;
1246 }
1247 color_info = 0;
1248 switch (rtex->surface.level[level].mode) {
1249 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1250 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1251 break;
1252 case RADEON_SURF_MODE_1D:
1253 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1254 break;
1255 case RADEON_SURF_MODE_2D:
1256 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1257 break;
1258 case RADEON_SURF_MODE_LINEAR:
1259 default:
1260 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1261 break;
1262 }
1263
1264 desc = util_format_description(surf->base.format);
1265
1266 for (i = 0; i < 4; i++) {
1267 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1268 break;
1269 }
1270 }
1271
1272 ntype = V_0280A0_NUMBER_UNORM;
1273 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1274 ntype = V_0280A0_NUMBER_SRGB;
1275 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1276 if (desc->channel[i].normalized)
1277 ntype = V_0280A0_NUMBER_SNORM;
1278 else if (desc->channel[i].pure_integer)
1279 ntype = V_0280A0_NUMBER_SINT;
1280 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1281 if (desc->channel[i].normalized)
1282 ntype = V_0280A0_NUMBER_UNORM;
1283 else if (desc->channel[i].pure_integer)
1284 ntype = V_0280A0_NUMBER_UINT;
1285 }
1286
1287 format = r600_translate_colorformat(surf->base.format);
1288 assert(format != ~0);
1289
1290 swap = r600_translate_colorswap(surf->base.format);
1291 assert(swap != ~0);
1292
1293 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1294 endian = ENDIAN_NONE;
1295 } else {
1296 endian = r600_colorformat_endian_swap(format);
1297 }
1298
1299 /* set blend bypass according to docs if SINT/UINT or
1300 8/24 COLOR variants */
1301 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1302 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1303 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1304 blend_clamp = 0;
1305 blend_bypass = 1;
1306 }
1307
1308 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
1309
1310 color_info |= S_0280A0_FORMAT(format) |
1311 S_0280A0_COMP_SWAP(swap) |
1312 S_0280A0_BLEND_BYPASS(blend_bypass) |
1313 S_0280A0_BLEND_CLAMP(blend_clamp) |
1314 S_0280A0_NUMBER_TYPE(ntype) |
1315 S_0280A0_ENDIAN(endian);
1316
1317 /* EXPORT_NORM is an optimzation that can be enabled for better
1318 * performance in certain cases
1319 */
1320 if (rctx->chip_class == R600) {
1321 /* EXPORT_NORM can be enabled if:
1322 * - 11-bit or smaller UNORM/SNORM/SRGB
1323 * - BLEND_CLAMP is enabled
1324 * - BLEND_FLOAT32 is disabled
1325 */
1326 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1327 (desc->channel[i].size < 12 &&
1328 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1329 ntype != V_0280A0_NUMBER_UINT &&
1330 ntype != V_0280A0_NUMBER_SINT) &&
1331 G_0280A0_BLEND_CLAMP(color_info) &&
1332 !G_0280A0_BLEND_FLOAT32(color_info)) {
1333 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1334 surf->export_16bpc = true;
1335 }
1336 } else {
1337 /* EXPORT_NORM can be enabled if:
1338 * - 11-bit or smaller UNORM/SNORM/SRGB
1339 * - 16-bit or smaller FLOAT
1340 */
1341 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1342 ((desc->channel[i].size < 12 &&
1343 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1344 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1345 (desc->channel[i].size < 17 &&
1346 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1347 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1348 surf->export_16bpc = true;
1349 }
1350 }
1351
1352 /* These might not always be initialized to zero. */
1353 surf->cb_color_base = offset >> 8;
1354 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
1355 S_028060_SLICE_TILE_MAX(slice);
1356 surf->cb_color_fmask = surf->cb_color_base;
1357 surf->cb_color_cmask = surf->cb_color_base;
1358 surf->cb_color_mask = 0;
1359
1360 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1361 &rtex->resource.b.b);
1362 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1363 &rtex->resource.b.b);
1364
1365 if (rtex->cmask_size) {
1366 surf->cb_color_cmask = rtex->cmask_offset >> 8;
1367 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask_slice_tile_max);
1368
1369 if (rtex->fmask_size) {
1370 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1371 surf->cb_color_fmask = rtex->fmask_offset >> 8;
1372 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(slice);
1373 } else { /* cmask only */
1374 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
1375 }
1376 } else if (force_cmask_fmask) {
1377 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1378 *
1379 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1380 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1381 * because it's not an MSAA buffer.
1382 */
1383 struct r600_cmask_info cmask;
1384 struct r600_fmask_info fmask;
1385
1386 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
1387 r600_texture_get_fmask_info(rscreen, rtex, 8, &fmask);
1388
1389 /* CMASK. */
1390 if (!rctx->dummy_cmask ||
1391 rctx->dummy_cmask->buf->size < cmask.size ||
1392 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1393 struct pipe_transfer *transfer;
1394 void *ptr;
1395
1396 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1397 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1398
1399 /* Set the contents to 0xCC. */
1400 ptr = pipe_buffer_map(&rctx->context, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1401 memset(ptr, 0xCC, cmask.size);
1402 pipe_buffer_unmap(&rctx->context, transfer);
1403 }
1404 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1405 &rctx->dummy_cmask->b.b);
1406
1407 /* FMASK. */
1408 if (!rctx->dummy_fmask ||
1409 rctx->dummy_fmask->buf->size < fmask.size ||
1410 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1411 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1412 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1413
1414 }
1415 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1416 &rctx->dummy_fmask->b.b);
1417
1418 /* Init the registers. */
1419 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1420 surf->cb_color_cmask = 0;
1421 surf->cb_color_fmask = 0;
1422 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1423 S_028100_FMASK_TILE_MAX(slice);
1424 }
1425
1426 surf->cb_color_info = color_info;
1427
1428 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1429 surf->cb_color_view = 0;
1430 } else {
1431 surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
1432 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
1433 }
1434
1435 surf->color_initialized = true;
1436 }
1437
1438 static void r600_init_depth_surface(struct r600_context *rctx,
1439 struct r600_surface *surf)
1440 {
1441 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1442 unsigned level, pitch, slice, format, offset, array_mode;
1443
1444 level = surf->base.u.tex.level;
1445 offset = rtex->surface.level[level].offset;
1446 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1447 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1448 if (slice) {
1449 slice = slice - 1;
1450 }
1451 switch (rtex->surface.level[level].mode) {
1452 case RADEON_SURF_MODE_2D:
1453 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1454 break;
1455 case RADEON_SURF_MODE_1D:
1456 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1457 case RADEON_SURF_MODE_LINEAR:
1458 default:
1459 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1460 break;
1461 }
1462
1463 format = r600_translate_dbformat(surf->base.format);
1464 assert(format != ~0);
1465
1466 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1467 surf->db_depth_base = offset >> 8;
1468 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1469 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1470 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1471 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1472
1473 surf->depth_initialized = true;
1474 }
1475
1476 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1477 const struct pipe_framebuffer_state *state)
1478 {
1479 struct r600_context *rctx = (struct r600_context *)ctx;
1480 struct r600_surface *surf;
1481 struct r600_texture *rtex;
1482 unsigned i;
1483
1484 if (rctx->framebuffer.state.nr_cbufs) {
1485 rctx->flags |= R600_CONTEXT_CB_FLUSH;
1486
1487 if (rctx->chip_class >= R700 &&
1488 rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
1489 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
1490 }
1491 }
1492 if (rctx->framebuffer.state.zsbuf) {
1493 rctx->flags |= R600_CONTEXT_DB_FLUSH;
1494 }
1495 /* R6xx errata */
1496 if (rctx->chip_class == R600) {
1497 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
1498 }
1499
1500 /* Set the new state. */
1501 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1502
1503 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1504 rctx->framebuffer.cb0_is_integer = state->nr_cbufs &&
1505 util_format_is_pure_integer(state->cbufs[0]->format);
1506 rctx->framebuffer.compressed_cb_mask = 0;
1507 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1508 state->cbufs[0]->texture->nr_samples > 1 &&
1509 state->cbufs[1]->texture->nr_samples <= 1;
1510
1511 if (state->nr_cbufs)
1512 rctx->framebuffer.nr_samples = state->cbufs[0]->texture->nr_samples;
1513 else if (state->zsbuf)
1514 rctx->framebuffer.nr_samples = state->zsbuf->texture->nr_samples;
1515 else
1516 rctx->framebuffer.nr_samples = 0;
1517
1518 /* Colorbuffers. */
1519 for (i = 0; i < state->nr_cbufs; i++) {
1520 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1521 bool force_cmask_fmask = rctx->chip_class == R600 &&
1522 rctx->framebuffer.is_msaa_resolve &&
1523 i == 1;
1524
1525 surf = (struct r600_surface*)state->cbufs[i];
1526 rtex = (struct r600_texture*)surf->base.texture;
1527
1528 if (!surf->color_initialized || force_cmask_fmask) {
1529 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1530 if (force_cmask_fmask) {
1531 /* re-initialize later without compression */
1532 surf->color_initialized = false;
1533 }
1534 }
1535
1536 if (!surf->export_16bpc) {
1537 rctx->framebuffer.export_16bpc = false;
1538 }
1539
1540 if (rtex->fmask_size && rtex->cmask_size) {
1541 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1542 }
1543 }
1544
1545 /* Update alpha-test state dependencies.
1546 * Alpha-test is done on the first colorbuffer only. */
1547 if (state->nr_cbufs) {
1548 surf = (struct r600_surface*)state->cbufs[0];
1549 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1550 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1551 rctx->alphatest_state.atom.dirty = true;
1552 }
1553 }
1554
1555 /* ZS buffer. */
1556 if (state->zsbuf) {
1557 surf = (struct r600_surface*)state->zsbuf;
1558
1559 if (!surf->depth_initialized) {
1560 r600_init_depth_surface(rctx, surf);
1561 }
1562
1563 r600_polygon_offset_update(rctx);
1564 }
1565
1566 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1567 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1568 rctx->cb_misc_state.atom.dirty = true;
1569 }
1570
1571 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1572 rctx->alphatest_state.bypass = false;
1573 rctx->alphatest_state.atom.dirty = true;
1574 }
1575
1576 /* Calculate the CS size. */
1577 rctx->framebuffer.atom.num_dw =
1578 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1579
1580 if (rctx->framebuffer.state.nr_cbufs) {
1581 rctx->framebuffer.atom.num_dw += 6 * (2 + rctx->framebuffer.state.nr_cbufs);
1582 rctx->framebuffer.atom.num_dw += 6 * rctx->framebuffer.state.nr_cbufs; /* relocs */
1583
1584 }
1585 if (rctx->framebuffer.state.zsbuf) {
1586 rctx->framebuffer.atom.num_dw += 13;
1587 } else if (rctx->screen->info.drm_minor >= 18) {
1588 rctx->framebuffer.atom.num_dw += 3;
1589 }
1590 if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770) {
1591 rctx->framebuffer.atom.num_dw += 2;
1592 }
1593
1594 rctx->framebuffer.atom.dirty = true;
1595 }
1596
1597 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1598 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1599 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1600 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1601 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1602
1603 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1604 {
1605 static uint32_t sample_locs_2x[] = {
1606 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1607 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1608 };
1609 static unsigned max_dist_2x = 4;
1610 static uint32_t sample_locs_4x[] = {
1611 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1612 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1613 };
1614 static unsigned max_dist_4x = 6;
1615 static uint32_t sample_locs_8x[] = {
1616 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1617 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1618 };
1619 static unsigned max_dist_8x = 8;
1620
1621 struct radeon_winsys_cs *cs = rctx->cs;
1622 unsigned max_dist = 0;
1623
1624 if (rctx->family == CHIP_R600) {
1625 switch (nr_samples) {
1626 default:
1627 nr_samples = 0;
1628 break;
1629 case 2:
1630 r600_write_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1631 max_dist = max_dist_2x;
1632 break;
1633 case 4:
1634 r600_write_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1635 max_dist = max_dist_4x;
1636 break;
1637 case 8:
1638 r600_write_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1639 r600_write_value(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1640 r600_write_value(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1641 max_dist = max_dist_8x;
1642 break;
1643 }
1644 } else {
1645 switch (nr_samples) {
1646 default:
1647 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1648 r600_write_value(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1649 r600_write_value(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1650 nr_samples = 0;
1651 break;
1652 case 2:
1653 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1654 r600_write_value(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1655 r600_write_value(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1656 max_dist = max_dist_2x;
1657 break;
1658 case 4:
1659 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1660 r600_write_value(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1661 r600_write_value(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1662 max_dist = max_dist_4x;
1663 break;
1664 case 8:
1665 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1666 r600_write_value(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1667 r600_write_value(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1668 max_dist = max_dist_8x;
1669 break;
1670 }
1671 }
1672
1673 if (nr_samples > 1) {
1674 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1675 r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
1676 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1677 r600_write_value(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1678 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1679 } else {
1680 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1681 r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1682 r600_write_value(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1683 }
1684 }
1685
1686 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1687 {
1688 struct radeon_winsys_cs *cs = rctx->cs;
1689 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1690 unsigned nr_cbufs = state->nr_cbufs;
1691 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1692 unsigned i, sbu = 0;
1693
1694 /* Colorbuffers. */
1695 r600_write_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1696 for (i = 0; i < nr_cbufs; i++) {
1697 r600_write_value(cs, cb[i]->cb_color_info);
1698 }
1699 /* set CB_COLOR1_INFO for possible dual-src blending */
1700 if (i == 1) {
1701 r600_write_value(cs, cb[0]->cb_color_info);
1702 i++;
1703 }
1704 for (; i < 8; i++) {
1705 r600_write_value(cs, 0);
1706 }
1707
1708 if (nr_cbufs) {
1709 /* COLOR_BASE */
1710 r600_write_context_reg_seq(cs, R_028040_CB_COLOR0_BASE, nr_cbufs);
1711 for (i = 0; i < nr_cbufs; i++) {
1712 r600_write_value(cs, cb[i]->cb_color_base);
1713 }
1714
1715 /* relocations */
1716 for (i = 0; i < nr_cbufs; i++) {
1717 unsigned reloc = r600_context_bo_reloc(rctx,
1718 (struct r600_resource*)cb[i]->base.texture,
1719 RADEON_USAGE_READWRITE);
1720 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1721 r600_write_value(cs, reloc);
1722 }
1723
1724 r600_write_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1725 for (i = 0; i < nr_cbufs; i++) {
1726 r600_write_value(cs, cb[i]->cb_color_size);
1727 }
1728
1729 r600_write_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1730 for (i = 0; i < nr_cbufs; i++) {
1731 r600_write_value(cs, cb[i]->cb_color_view);
1732 }
1733
1734 r600_write_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1735 for (i = 0; i < nr_cbufs; i++) {
1736 r600_write_value(cs, cb[i]->cb_color_mask);
1737 }
1738
1739 /* FMASK. */
1740 r600_write_context_reg_seq(cs, R_0280E0_CB_COLOR0_FRAG, nr_cbufs);
1741 for (i = 0; i < nr_cbufs; i++) {
1742 r600_write_value(cs, cb[i]->cb_color_fmask);
1743 }
1744 /* relocations */
1745 for (i = 0; i < nr_cbufs; i++) {
1746 unsigned reloc = r600_context_bo_reloc(rctx,
1747 cb[i]->cb_buffer_fmask,
1748 RADEON_USAGE_READWRITE);
1749 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1750 r600_write_value(cs, reloc);
1751 }
1752
1753 /* CMASK. */
1754 r600_write_context_reg_seq(cs, R_0280C0_CB_COLOR0_TILE, nr_cbufs);
1755 for (i = 0; i < nr_cbufs; i++) {
1756 r600_write_value(cs, cb[i]->cb_color_cmask);
1757 }
1758 /* relocations */
1759 for (i = 0; i < nr_cbufs; i++) {
1760 unsigned reloc = r600_context_bo_reloc(rctx,
1761 cb[i]->cb_buffer_cmask,
1762 RADEON_USAGE_READWRITE);
1763 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1764 r600_write_value(cs, reloc);
1765 }
1766
1767 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1768 }
1769
1770 /* Zbuffer. */
1771 if (state->zsbuf) {
1772 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1773 unsigned reloc = r600_context_bo_reloc(rctx,
1774 (struct r600_resource*)state->zsbuf->texture,
1775 RADEON_USAGE_READWRITE);
1776
1777 r600_write_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1778 r600_write_value(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1779 r600_write_value(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1780 r600_write_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1781 r600_write_value(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1782 r600_write_value(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1783
1784 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1785 r600_write_value(cs, reloc);
1786
1787 r600_write_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1788
1789 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1790 } else if (rctx->screen->info.drm_minor >= 18) {
1791 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1792 * Older kernels are out of luck. */
1793 r600_write_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1794 }
1795
1796 /* SURFACE_BASE_UPDATE */
1797 if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770 && sbu) {
1798 r600_write_value(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1799 r600_write_value(cs, sbu);
1800 }
1801
1802 /* Framebuffer dimensions. */
1803 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1804 r600_write_value(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1805 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1806 r600_write_value(cs, S_028244_BR_X(state->width) |
1807 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1808
1809 if (rctx->framebuffer.is_msaa_resolve) {
1810 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1811 } else {
1812 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1813 * will assure that the alpha-test will work even if there is
1814 * no colorbuffer bound. */
1815 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1816 (1ull << MAX2(nr_cbufs, 1)) - 1);
1817 }
1818
1819 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1820 }
1821
1822 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1823 {
1824 struct radeon_winsys_cs *cs = rctx->cs;
1825 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1826
1827 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1828 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1829 if (rctx->chip_class == R600) {
1830 r600_write_value(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1831 r600_write_value(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1832 } else {
1833 r600_write_value(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1834 r600_write_value(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1835 }
1836 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1837 } else {
1838 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1839 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1840 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1841
1842 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1843 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1844 /* Always enable the first color output to make sure alpha-test works even without one. */
1845 r600_write_value(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1846 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1847 a->cb_color_control |
1848 S_028808_MULTIWRITE_ENABLE(multiwrite));
1849 }
1850 }
1851
1852 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1853 {
1854 struct radeon_winsys_cs *cs = rctx->cs;
1855 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1856 unsigned db_render_control = 0;
1857 unsigned db_render_override =
1858 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
1859 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1860 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1861
1862 if (a->occlusion_query_enabled) {
1863 if (rctx->chip_class >= R700) {
1864 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1865 }
1866 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1867 }
1868 if (a->flush_depthstencil_through_cb) {
1869 assert(a->copy_depth || a->copy_stencil);
1870
1871 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1872 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1873 S_028D0C_COPY_CENTROID(1) |
1874 S_028D0C_COPY_SAMPLE(a->copy_sample);
1875 }
1876
1877 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1878 r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1879 r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1880 }
1881
1882 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1883 {
1884 struct radeon_winsys_cs *cs = rctx->cs;
1885 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1886
1887 while (dirty_mask) {
1888 struct pipe_vertex_buffer *vb;
1889 struct r600_resource *rbuffer;
1890 unsigned offset;
1891 unsigned buffer_index = u_bit_scan(&dirty_mask);
1892
1893 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1894 rbuffer = (struct r600_resource*)vb->buffer;
1895 assert(rbuffer);
1896
1897 offset = vb->buffer_offset;
1898
1899 /* fetch resources start at index 320 */
1900 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1901 r600_write_value(cs, (320 + buffer_index) * 7);
1902 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1903 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1904 r600_write_value(cs, /* RESOURCEi_WORD2 */
1905 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1906 S_038008_STRIDE(vb->stride));
1907 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1908 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1909 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1910 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1911
1912 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1913 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1914 }
1915 }
1916
1917 static void r600_emit_constant_buffers(struct r600_context *rctx,
1918 struct r600_constbuf_state *state,
1919 unsigned buffer_id_base,
1920 unsigned reg_alu_constbuf_size,
1921 unsigned reg_alu_const_cache)
1922 {
1923 struct radeon_winsys_cs *cs = rctx->cs;
1924 uint32_t dirty_mask = state->dirty_mask;
1925
1926 while (dirty_mask) {
1927 struct pipe_constant_buffer *cb;
1928 struct r600_resource *rbuffer;
1929 unsigned offset;
1930 unsigned buffer_index = ffs(dirty_mask) - 1;
1931
1932 cb = &state->cb[buffer_index];
1933 rbuffer = (struct r600_resource*)cb->buffer;
1934 assert(rbuffer);
1935
1936 offset = cb->buffer_offset;
1937
1938 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1939 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1940 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1941
1942 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1943 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1944
1945 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1946 r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
1947 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1948 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1949 r600_write_value(cs, /* RESOURCEi_WORD2 */
1950 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1951 S_038008_STRIDE(16));
1952 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1953 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1954 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1955 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1956
1957 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1958 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1959
1960 dirty_mask &= ~(1 << buffer_index);
1961 }
1962 state->dirty_mask = 0;
1963 }
1964
1965 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1966 {
1967 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 160,
1968 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1969 R_028980_ALU_CONST_CACHE_VS_0);
1970 }
1971
1972 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1973 {
1974 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
1975 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1976 R_0289C0_ALU_CONST_CACHE_GS_0);
1977 }
1978
1979 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1980 {
1981 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
1982 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1983 R_028940_ALU_CONST_CACHE_PS_0);
1984 }
1985
1986 static void r600_emit_sampler_views(struct r600_context *rctx,
1987 struct r600_samplerview_state *state,
1988 unsigned resource_id_base)
1989 {
1990 struct radeon_winsys_cs *cs = rctx->cs;
1991 uint32_t dirty_mask = state->dirty_mask;
1992
1993 while (dirty_mask) {
1994 struct r600_pipe_sampler_view *rview;
1995 unsigned resource_index = u_bit_scan(&dirty_mask);
1996 unsigned reloc;
1997
1998 rview = state->views[resource_index];
1999 assert(rview);
2000
2001 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
2002 r600_write_value(cs, (resource_id_base + resource_index) * 7);
2003 r600_write_array(cs, 7, rview->tex_resource_words);
2004
2005 /* XXX The kernel needs two relocations. This is stupid. */
2006 reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
2007 RADEON_USAGE_READ);
2008 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2009 r600_write_value(cs, reloc);
2010 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2011 r600_write_value(cs, reloc);
2012 }
2013 state->dirty_mask = 0;
2014 }
2015
2016 /* Resource IDs:
2017 * PS: 0 .. +160
2018 * VS: 160 .. +160
2019 * FS: 320 .. +16
2020 * GS: 336 .. +160
2021 */
2022
2023 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2024 {
2025 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 160 + R600_MAX_CONST_BUFFERS);
2026 }
2027
2028 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2029 {
2030 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
2031 }
2032
2033 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2034 {
2035 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
2036 }
2037
2038 static void r600_emit_sampler_states(struct r600_context *rctx,
2039 struct r600_textures_info *texinfo,
2040 unsigned resource_id_base,
2041 unsigned border_color_reg)
2042 {
2043 struct radeon_winsys_cs *cs = rctx->cs;
2044 uint32_t dirty_mask = texinfo->states.dirty_mask;
2045
2046 while (dirty_mask) {
2047 struct r600_pipe_sampler_state *rstate;
2048 struct r600_pipe_sampler_view *rview;
2049 unsigned i = u_bit_scan(&dirty_mask);
2050
2051 rstate = texinfo->states.states[i];
2052 assert(rstate);
2053 rview = texinfo->views.views[i];
2054
2055 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
2056 * filtering between layers.
2057 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
2058 */
2059 if (rview) {
2060 enum pipe_texture_target target = rview->base.texture->target;
2061 if (target == PIPE_TEXTURE_1D_ARRAY ||
2062 target == PIPE_TEXTURE_2D_ARRAY) {
2063 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
2064 texinfo->is_array_sampler[i] = true;
2065 } else {
2066 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
2067 texinfo->is_array_sampler[i] = false;
2068 }
2069 }
2070
2071 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2072 r600_write_value(cs, (resource_id_base + i) * 3);
2073 r600_write_array(cs, 3, rstate->tex_sampler_words);
2074
2075 if (rstate->border_color_use) {
2076 unsigned offset;
2077
2078 offset = border_color_reg;
2079 offset += i * 16;
2080 r600_write_config_reg_seq(cs, offset, 4);
2081 r600_write_array(cs, 4, rstate->border_color);
2082 }
2083 }
2084 texinfo->states.dirty_mask = 0;
2085 }
2086
2087 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2088 {
2089 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
2090 }
2091
2092 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2093 {
2094 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
2095 }
2096
2097 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2098 {
2099 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
2100 }
2101
2102 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
2103 {
2104 struct radeon_winsys_cs *cs = rctx->cs;
2105 unsigned tmp;
2106
2107 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
2108 S_009508_SYNC_GRADIENT(1) |
2109 S_009508_SYNC_WALKER(1) |
2110 S_009508_SYNC_ALIGNER(1);
2111 if (!rctx->seamless_cube_map.enabled) {
2112 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
2113 }
2114 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
2115 }
2116
2117 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2118 {
2119 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2120 uint8_t mask = s->sample_mask;
2121
2122 r600_write_context_reg(rctx->cs, R_028C48_PA_SC_AA_MASK,
2123 mask | (mask << 8) | (mask << 16) | (mask << 24));
2124 }
2125
2126 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2127 {
2128 struct radeon_winsys_cs *cs = rctx->cs;
2129 struct r600_cso_state *state = (struct r600_cso_state*)a;
2130 struct r600_resource *shader = (struct r600_resource*)state->cso;
2131
2132 r600_write_context_reg(cs, R_028894_SQ_PGM_START_FS, 0);
2133 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2134 r600_write_value(cs, r600_context_bo_reloc(rctx, shader, RADEON_USAGE_READ));
2135 }
2136
2137 void r600_init_state_functions(struct r600_context *rctx)
2138 {
2139 unsigned id = 4;
2140
2141 /* !!!
2142 * To avoid GPU lockup registers must be emited in a specific order
2143 * (no kidding ...). The order below is important and have been
2144 * partialy infered from analyzing fglrx command stream.
2145 *
2146 * Don't reorder atom without carefully checking the effect (GPU lockup
2147 * or piglit regression).
2148 * !!!
2149 */
2150
2151 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
2152
2153 /* shader const */
2154 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
2155 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
2156 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
2157
2158 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2159 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
2160 */
2161 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
2162 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
2163 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
2164 /* resource */
2165 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
2166 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
2167 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
2168 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
2169
2170 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 6);
2171 r600_init_atom(rctx, &rctx->vgt2_state.atom, id++, r600_emit_vgt2_state, 3);
2172
2173 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
2174 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
2175 rctx->sample_mask.sample_mask = ~0;
2176
2177 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
2178 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
2179 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
2180 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
2181 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
2182 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
2183 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 4);
2184 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
2185 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
2186 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
2187
2188 rctx->context.create_blend_state = r600_create_blend_state;
2189 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
2190 rctx->context.create_rasterizer_state = r600_create_rs_state;
2191 rctx->context.create_sampler_state = r600_create_sampler_state;
2192 rctx->context.create_sampler_view = r600_create_sampler_view;
2193 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
2194 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
2195 rctx->context.set_scissor_state = r600_pipe_set_scissor_state;
2196 }
2197
2198 /* Adjust GPR allocation on R6xx/R7xx */
2199 void r600_adjust_gprs(struct r600_context *rctx)
2200 {
2201 struct r600_pipe_state rstate;
2202 unsigned num_ps_gprs = rctx->default_ps_gprs;
2203 unsigned num_vs_gprs = rctx->default_vs_gprs;
2204 unsigned tmp;
2205 int diff;
2206
2207 if (rctx->ps_shader->current->shader.bc.ngpr > rctx->default_ps_gprs) {
2208 diff = rctx->ps_shader->current->shader.bc.ngpr - rctx->default_ps_gprs;
2209 num_vs_gprs -= diff;
2210 num_ps_gprs += diff;
2211 }
2212
2213 if (rctx->vs_shader->current->shader.bc.ngpr > rctx->default_vs_gprs)
2214 {
2215 diff = rctx->vs_shader->current->shader.bc.ngpr - rctx->default_vs_gprs;
2216 num_ps_gprs -= diff;
2217 num_vs_gprs += diff;
2218 }
2219
2220 tmp = 0;
2221 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2222 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2223 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
2224 rstate.nregs = 0;
2225 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp);
2226
2227 r600_context_pipe_state_set(rctx, &rstate);
2228 }
2229
2230 void r600_init_atom_start_cs(struct r600_context *rctx)
2231 {
2232 int ps_prio;
2233 int vs_prio;
2234 int gs_prio;
2235 int es_prio;
2236 int num_ps_gprs;
2237 int num_vs_gprs;
2238 int num_gs_gprs;
2239 int num_es_gprs;
2240 int num_temp_gprs;
2241 int num_ps_threads;
2242 int num_vs_threads;
2243 int num_gs_threads;
2244 int num_es_threads;
2245 int num_ps_stack_entries;
2246 int num_vs_stack_entries;
2247 int num_gs_stack_entries;
2248 int num_es_stack_entries;
2249 enum radeon_family family;
2250 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2251 uint32_t tmp;
2252
2253 r600_init_command_buffer(cb, 256);
2254
2255 /* R6xx requires this packet at the start of each command buffer */
2256 if (rctx->chip_class == R600) {
2257 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2258 r600_store_value(cb, 0);
2259 }
2260 /* All asics require this one */
2261 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2262 r600_store_value(cb, 0x80000000);
2263 r600_store_value(cb, 0x80000000);
2264
2265 family = rctx->family;
2266 ps_prio = 0;
2267 vs_prio = 1;
2268 gs_prio = 2;
2269 es_prio = 3;
2270 switch (family) {
2271 case CHIP_R600:
2272 num_ps_gprs = 192;
2273 num_vs_gprs = 56;
2274 num_temp_gprs = 4;
2275 num_gs_gprs = 0;
2276 num_es_gprs = 0;
2277 num_ps_threads = 136;
2278 num_vs_threads = 48;
2279 num_gs_threads = 4;
2280 num_es_threads = 4;
2281 num_ps_stack_entries = 128;
2282 num_vs_stack_entries = 128;
2283 num_gs_stack_entries = 0;
2284 num_es_stack_entries = 0;
2285 break;
2286 case CHIP_RV630:
2287 case CHIP_RV635:
2288 num_ps_gprs = 84;
2289 num_vs_gprs = 36;
2290 num_temp_gprs = 4;
2291 num_gs_gprs = 0;
2292 num_es_gprs = 0;
2293 num_ps_threads = 144;
2294 num_vs_threads = 40;
2295 num_gs_threads = 4;
2296 num_es_threads = 4;
2297 num_ps_stack_entries = 40;
2298 num_vs_stack_entries = 40;
2299 num_gs_stack_entries = 32;
2300 num_es_stack_entries = 16;
2301 break;
2302 case CHIP_RV610:
2303 case CHIP_RV620:
2304 case CHIP_RS780:
2305 case CHIP_RS880:
2306 default:
2307 num_ps_gprs = 84;
2308 num_vs_gprs = 36;
2309 num_temp_gprs = 4;
2310 num_gs_gprs = 0;
2311 num_es_gprs = 0;
2312 num_ps_threads = 136;
2313 num_vs_threads = 48;
2314 num_gs_threads = 4;
2315 num_es_threads = 4;
2316 num_ps_stack_entries = 40;
2317 num_vs_stack_entries = 40;
2318 num_gs_stack_entries = 32;
2319 num_es_stack_entries = 16;
2320 break;
2321 case CHIP_RV670:
2322 num_ps_gprs = 144;
2323 num_vs_gprs = 40;
2324 num_temp_gprs = 4;
2325 num_gs_gprs = 0;
2326 num_es_gprs = 0;
2327 num_ps_threads = 136;
2328 num_vs_threads = 48;
2329 num_gs_threads = 4;
2330 num_es_threads = 4;
2331 num_ps_stack_entries = 40;
2332 num_vs_stack_entries = 40;
2333 num_gs_stack_entries = 32;
2334 num_es_stack_entries = 16;
2335 break;
2336 case CHIP_RV770:
2337 num_ps_gprs = 192;
2338 num_vs_gprs = 56;
2339 num_temp_gprs = 4;
2340 num_gs_gprs = 0;
2341 num_es_gprs = 0;
2342 num_ps_threads = 188;
2343 num_vs_threads = 60;
2344 num_gs_threads = 0;
2345 num_es_threads = 0;
2346 num_ps_stack_entries = 256;
2347 num_vs_stack_entries = 256;
2348 num_gs_stack_entries = 0;
2349 num_es_stack_entries = 0;
2350 break;
2351 case CHIP_RV730:
2352 case CHIP_RV740:
2353 num_ps_gprs = 84;
2354 num_vs_gprs = 36;
2355 num_temp_gprs = 4;
2356 num_gs_gprs = 0;
2357 num_es_gprs = 0;
2358 num_ps_threads = 188;
2359 num_vs_threads = 60;
2360 num_gs_threads = 0;
2361 num_es_threads = 0;
2362 num_ps_stack_entries = 128;
2363 num_vs_stack_entries = 128;
2364 num_gs_stack_entries = 0;
2365 num_es_stack_entries = 0;
2366 break;
2367 case CHIP_RV710:
2368 num_ps_gprs = 192;
2369 num_vs_gprs = 56;
2370 num_temp_gprs = 4;
2371 num_gs_gprs = 0;
2372 num_es_gprs = 0;
2373 num_ps_threads = 144;
2374 num_vs_threads = 48;
2375 num_gs_threads = 0;
2376 num_es_threads = 0;
2377 num_ps_stack_entries = 128;
2378 num_vs_stack_entries = 128;
2379 num_gs_stack_entries = 0;
2380 num_es_stack_entries = 0;
2381 break;
2382 }
2383
2384 rctx->default_ps_gprs = num_ps_gprs;
2385 rctx->default_vs_gprs = num_vs_gprs;
2386 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2387
2388 /* SQ_CONFIG */
2389 tmp = 0;
2390 switch (family) {
2391 case CHIP_RV610:
2392 case CHIP_RV620:
2393 case CHIP_RS780:
2394 case CHIP_RS880:
2395 case CHIP_RV710:
2396 break;
2397 default:
2398 tmp |= S_008C00_VC_ENABLE(1);
2399 break;
2400 }
2401 tmp |= S_008C00_DX9_CONSTS(0);
2402 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2403 tmp |= S_008C00_PS_PRIO(ps_prio);
2404 tmp |= S_008C00_VS_PRIO(vs_prio);
2405 tmp |= S_008C00_GS_PRIO(gs_prio);
2406 tmp |= S_008C00_ES_PRIO(es_prio);
2407 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2408
2409 /* SQ_GPR_RESOURCE_MGMT_2 */
2410 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2411 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2412 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2413 r600_store_value(cb, tmp);
2414
2415 /* SQ_THREAD_RESOURCE_MGMT */
2416 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2417 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2418 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2419 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2420 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2421
2422 /* SQ_STACK_RESOURCE_MGMT_1 */
2423 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2424 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2425 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2426
2427 /* SQ_STACK_RESOURCE_MGMT_2 */
2428 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2429 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2430 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2431
2432 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2433
2434 if (rctx->chip_class >= R700) {
2435 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2436 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2437 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2438 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2439 } else {
2440 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2441 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2442 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2443 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2444 }
2445 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2446 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2447 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2448 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2449 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2450 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2451 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2452 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2453 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2454 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2455
2456 /* to avoid GPU doing any preloading of constant from random address */
2457 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2458 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2459 r600_store_value(cb, 0);
2460 r600_store_value(cb, 0);
2461 r600_store_value(cb, 0);
2462 r600_store_value(cb, 0);
2463 r600_store_value(cb, 0);
2464 r600_store_value(cb, 0);
2465 r600_store_value(cb, 0);
2466 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2467 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2468 r600_store_value(cb, 0);
2469 r600_store_value(cb, 0);
2470 r600_store_value(cb, 0);
2471 r600_store_value(cb, 0);
2472 r600_store_value(cb, 0);
2473 r600_store_value(cb, 0);
2474 r600_store_value(cb, 0);
2475
2476 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2477 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2478 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2479 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2480 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2481 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2482 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2483 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2484 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2485 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2486 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2487 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2488 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2489 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2490
2491 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2492 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2493 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2494
2495 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2496 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2497 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2498 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2499
2500 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2501
2502 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2503 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2504 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2505
2506 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2507
2508 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2509 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2510 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2511
2512 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2513 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2514 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2515 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2516
2517 r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2518 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2519 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2520
2521 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2522 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2523
2524 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2525 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2526 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2527 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2528 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2529
2530 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2531 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2532 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2533
2534 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2535
2536 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2537 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2538
2539 if (rctx->chip_class >= R700) {
2540 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2541 }
2542
2543 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2544 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2545 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2546 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2547 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2548
2549 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2550 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2551 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2552
2553 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2554 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2555 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2556
2557 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2558 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2559 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2560
2561 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2562 r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2563
2564 if (rctx->chip_class == R700 && rctx->screen->has_streamout)
2565 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2566 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2567 if (rctx->screen->has_streamout) {
2568 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2569 }
2570
2571 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2572 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2573 }
2574
2575 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2576 {
2577 struct r600_context *rctx = (struct r600_context *)ctx;
2578 struct r600_pipe_state *rstate = &shader->rstate;
2579 struct r600_shader *rshader = &shader->shader;
2580 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2581 int pos_index = -1, face_index = -1;
2582 unsigned tmp, sid, ufi = 0;
2583 int need_linear = 0;
2584 unsigned z_export = 0, stencil_export = 0;
2585
2586 rstate->nregs = 0;
2587
2588 for (i = 0; i < rshader->ninput; i++) {
2589 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2590 pos_index = i;
2591 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2592 face_index = i;
2593
2594 sid = rshader->input[i].spi_sid;
2595
2596 tmp = S_028644_SEMANTIC(sid);
2597
2598 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2599 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2600 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2601 rctx->rasterizer && rctx->rasterizer->flatshade))
2602 tmp |= S_028644_FLAT_SHADE(1);
2603
2604 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2605 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2606 tmp |= S_028644_PT_SPRITE_TEX(1);
2607 }
2608
2609 if (rshader->input[i].centroid)
2610 tmp |= S_028644_SEL_CENTROID(1);
2611
2612 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2613 need_linear = 1;
2614 tmp |= S_028644_SEL_LINEAR(1);
2615 }
2616
2617 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2618 tmp);
2619 }
2620
2621 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2622 for (i = 0; i < rshader->noutput; i++) {
2623 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2624 z_export = 1;
2625 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2626 stencil_export = 1;
2627 }
2628 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2629 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2630 if (rshader->uses_kill)
2631 db_shader_control |= S_02880C_KILL_ENABLE(1);
2632
2633 exports_ps = 0;
2634 for (i = 0; i < rshader->noutput; i++) {
2635 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2636 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2637 exports_ps |= 1;
2638 }
2639 }
2640 num_cout = rshader->nr_ps_color_exports;
2641 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2642 if (!exports_ps) {
2643 /* always at least export 1 component per pixel */
2644 exports_ps = 2;
2645 }
2646
2647 shader->nr_ps_color_outputs = num_cout;
2648
2649 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2650 S_0286CC_PERSP_GRADIENT_ENA(1)|
2651 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2652 spi_input_z = 0;
2653 if (pos_index != -1) {
2654 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2655 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2656 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2657 S_0286CC_BARYC_SAMPLE_CNTL(1));
2658 spi_input_z |= 1;
2659 }
2660
2661 spi_ps_in_control_1 = 0;
2662 if (face_index != -1) {
2663 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2664 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2665 }
2666
2667 /* HW bug in original R600 */
2668 if (rctx->family == CHIP_R600)
2669 ufi = 1;
2670
2671 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2672 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2673 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2674 r600_pipe_state_add_reg_bo(rstate,
2675 R_028840_SQ_PGM_START_PS,
2676 0, shader->bo, RADEON_USAGE_READ);
2677 r600_pipe_state_add_reg(rstate,
2678 R_028850_SQ_PGM_RESOURCES_PS,
2679 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2680 S_028850_STACK_SIZE(rshader->bc.nstack) |
2681 S_028850_UNCACHED_FIRST_INST(ufi));
2682 r600_pipe_state_add_reg(rstate,
2683 R_028854_SQ_PGM_EXPORTS_PS,
2684 exports_ps);
2685 /* only set some bits here, the other bits are set in the dsa state */
2686 shader->db_shader_control = db_shader_control;
2687 shader->ps_depth_export = z_export | stencil_export;
2688
2689 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2690 if (rctx->rasterizer)
2691 shader->flatshade = rctx->rasterizer->flatshade;
2692 }
2693
2694 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2695 {
2696 struct r600_context *rctx = (struct r600_context *)ctx;
2697 struct r600_pipe_state *rstate = &shader->rstate;
2698 struct r600_shader *rshader = &shader->shader;
2699 unsigned spi_vs_out_id[10] = {};
2700 unsigned i, tmp, nparams = 0;
2701
2702 /* clear previous register */
2703 rstate->nregs = 0;
2704
2705 for (i = 0; i < rshader->noutput; i++) {
2706 if (rshader->output[i].spi_sid) {
2707 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2708 spi_vs_out_id[nparams / 4] |= tmp;
2709 nparams++;
2710 }
2711 }
2712
2713 for (i = 0; i < 10; i++) {
2714 r600_pipe_state_add_reg(rstate,
2715 R_028614_SPI_VS_OUT_ID_0 + i * 4,
2716 spi_vs_out_id[i]);
2717 }
2718
2719 /* Certain attributes (position, psize, etc.) don't count as params.
2720 * VS is required to export at least one param and r600_shader_from_tgsi()
2721 * takes care of adding a dummy export.
2722 */
2723 if (nparams < 1)
2724 nparams = 1;
2725
2726 r600_pipe_state_add_reg(rstate,
2727 R_0286C4_SPI_VS_OUT_CONFIG,
2728 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2729 r600_pipe_state_add_reg(rstate,
2730 R_028868_SQ_PGM_RESOURCES_VS,
2731 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2732 S_028868_STACK_SIZE(rshader->bc.nstack));
2733 r600_pipe_state_add_reg_bo(rstate,
2734 R_028858_SQ_PGM_START_VS,
2735 0, shader->bo, RADEON_USAGE_READ);
2736
2737 shader->pa_cl_vs_out_cntl =
2738 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2739 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2740 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2741 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2742 }
2743
2744 void *r600_create_resolve_blend(struct r600_context *rctx)
2745 {
2746 struct pipe_blend_state blend;
2747 unsigned i;
2748
2749 memset(&blend, 0, sizeof(blend));
2750 blend.independent_blend_enable = true;
2751 for (i = 0; i < 2; i++) {
2752 blend.rt[i].colormask = 0xf;
2753 blend.rt[i].blend_enable = 1;
2754 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2755 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2756 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2757 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2758 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2759 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2760 }
2761 return r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2762 }
2763
2764 void *r700_create_resolve_blend(struct r600_context *rctx)
2765 {
2766 struct pipe_blend_state blend;
2767
2768 memset(&blend, 0, sizeof(blend));
2769 blend.independent_blend_enable = true;
2770 blend.rt[0].colormask = 0xf;
2771 return r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2772 }
2773
2774 void *r600_create_decompress_blend(struct r600_context *rctx)
2775 {
2776 struct pipe_blend_state blend;
2777
2778 memset(&blend, 0, sizeof(blend));
2779 blend.independent_blend_enable = true;
2780 blend.rt[0].colormask = 0xf;
2781 return r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2782 }
2783
2784 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2785 {
2786 struct pipe_depth_stencil_alpha_state dsa;
2787 boolean quirk = false;
2788
2789 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2790 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2791 quirk = true;
2792
2793 memset(&dsa, 0, sizeof(dsa));
2794
2795 if (quirk) {
2796 dsa.depth.enabled = 1;
2797 dsa.depth.func = PIPE_FUNC_LEQUAL;
2798 dsa.stencil[0].enabled = 1;
2799 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2800 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2801 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2802 dsa.stencil[0].writemask = 0xff;
2803 }
2804
2805 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2806 }
2807
2808 void r600_update_dual_export_state(struct r600_context * rctx)
2809 {
2810 bool dual_export = rctx->framebuffer.export_16bpc &&
2811 !rctx->ps_shader->current->ps_depth_export;
2812
2813 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2814 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2815
2816 if (db_shader_control != rctx->db_shader_control) {
2817 struct r600_pipe_state rstate;
2818
2819 rctx->db_shader_control = db_shader_control;
2820 rstate.nregs = 0;
2821 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2822 r600_context_pipe_state_set(rctx, &rstate);
2823 }
2824 }