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gallium/radeon: disable complicated point clipping against user clip planes
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
145 {
146 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
147 FALSE) != ~0U;
148 }
149
150 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
151 {
152 return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
153 r600_translate_colorswap(format, FALSE) != ~0U;
154 }
155
156 static bool r600_is_zs_format_supported(enum pipe_format format)
157 {
158 return r600_translate_dbformat(format) != ~0U;
159 }
160
161 boolean r600_is_format_supported(struct pipe_screen *screen,
162 enum pipe_format format,
163 enum pipe_texture_target target,
164 unsigned sample_count,
165 unsigned usage)
166 {
167 struct r600_screen *rscreen = (struct r600_screen*)screen;
168 unsigned retval = 0;
169
170 if (target >= PIPE_MAX_TEXTURE_TYPES) {
171 R600_ERR("r600: unsupported texture type %d\n", target);
172 return FALSE;
173 }
174
175 if (!util_format_is_supported(format, usage))
176 return FALSE;
177
178 if (sample_count > 1) {
179 if (!rscreen->has_msaa)
180 return FALSE;
181
182 /* R11G11B10 is broken on R6xx. */
183 if (rscreen->b.chip_class == R600 &&
184 format == PIPE_FORMAT_R11G11B10_FLOAT)
185 return FALSE;
186
187 /* MSAA integer colorbuffers hang. */
188 if (util_format_is_pure_integer(format) &&
189 !util_format_is_depth_or_stencil(format))
190 return FALSE;
191
192 switch (sample_count) {
193 case 2:
194 case 4:
195 case 8:
196 break;
197 default:
198 return FALSE;
199 }
200 }
201
202 if (usage & PIPE_BIND_SAMPLER_VIEW) {
203 if (target == PIPE_BUFFER) {
204 if (r600_is_vertex_format_supported(format))
205 retval |= PIPE_BIND_SAMPLER_VIEW;
206 } else {
207 if (r600_is_sampler_format_supported(screen, format))
208 retval |= PIPE_BIND_SAMPLER_VIEW;
209 }
210 }
211
212 if ((usage & (PIPE_BIND_RENDER_TARGET |
213 PIPE_BIND_DISPLAY_TARGET |
214 PIPE_BIND_SCANOUT |
215 PIPE_BIND_SHARED |
216 PIPE_BIND_BLENDABLE)) &&
217 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
218 retval |= usage &
219 (PIPE_BIND_RENDER_TARGET |
220 PIPE_BIND_DISPLAY_TARGET |
221 PIPE_BIND_SCANOUT |
222 PIPE_BIND_SHARED);
223 if (!util_format_is_pure_integer(format) &&
224 !util_format_is_depth_or_stencil(format))
225 retval |= usage & PIPE_BIND_BLENDABLE;
226 }
227
228 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
229 r600_is_zs_format_supported(format)) {
230 retval |= PIPE_BIND_DEPTH_STENCIL;
231 }
232
233 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
234 r600_is_vertex_format_supported(format)) {
235 retval |= PIPE_BIND_VERTEX_BUFFER;
236 }
237
238 if (usage & PIPE_BIND_TRANSFER_READ)
239 retval |= PIPE_BIND_TRANSFER_READ;
240 if (usage & PIPE_BIND_TRANSFER_WRITE)
241 retval |= PIPE_BIND_TRANSFER_WRITE;
242
243 if ((usage & PIPE_BIND_LINEAR) &&
244 !util_format_is_compressed(format) &&
245 !(usage & PIPE_BIND_DEPTH_STENCIL))
246 retval |= PIPE_BIND_LINEAR;
247
248 return retval == usage;
249 }
250
251 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
252 {
253 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
254 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
255 float offset_units = state->offset_units;
256 float offset_scale = state->offset_scale;
257
258 switch (state->zs_format) {
259 case PIPE_FORMAT_Z24X8_UNORM:
260 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
261 offset_units *= 2.0f;
262 break;
263 case PIPE_FORMAT_Z16_UNORM:
264 offset_units *= 4.0f;
265 break;
266 default:;
267 }
268
269 radeon_set_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
270 radeon_emit(cs, fui(offset_scale));
271 radeon_emit(cs, fui(offset_units));
272 radeon_emit(cs, fui(offset_scale));
273 radeon_emit(cs, fui(offset_units));
274 }
275
276 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
277 {
278 int j = state->independent_blend_enable ? i : 0;
279
280 unsigned eqRGB = state->rt[j].rgb_func;
281 unsigned srcRGB = state->rt[j].rgb_src_factor;
282 unsigned dstRGB = state->rt[j].rgb_dst_factor;
283
284 unsigned eqA = state->rt[j].alpha_func;
285 unsigned srcA = state->rt[j].alpha_src_factor;
286 unsigned dstA = state->rt[j].alpha_dst_factor;
287 uint32_t bc = 0;
288
289 if (!state->rt[j].blend_enable)
290 return 0;
291
292 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
293 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
294 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
295
296 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
297 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
298 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
299 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
300 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
301 }
302 return bc;
303 }
304
305 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
306 const struct pipe_blend_state *state,
307 int mode)
308 {
309 struct r600_context *rctx = (struct r600_context *)ctx;
310 uint32_t color_control = 0, target_mask = 0;
311 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
312
313 if (!blend) {
314 return NULL;
315 }
316
317 r600_init_command_buffer(&blend->buffer, 20);
318 r600_init_command_buffer(&blend->buffer_no_blend, 20);
319
320 /* R600 does not support per-MRT blends */
321 if (rctx->b.family > CHIP_R600)
322 color_control |= S_028808_PER_MRT_BLEND(1);
323
324 if (state->logicop_enable) {
325 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
326 } else {
327 color_control |= (0xcc << 16);
328 }
329 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
330 if (state->independent_blend_enable) {
331 for (int i = 0; i < 8; i++) {
332 if (state->rt[i].blend_enable) {
333 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
334 }
335 target_mask |= (state->rt[i].colormask << (4 * i));
336 }
337 } else {
338 for (int i = 0; i < 8; i++) {
339 if (state->rt[0].blend_enable) {
340 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
341 }
342 target_mask |= (state->rt[0].colormask << (4 * i));
343 }
344 }
345
346 if (target_mask)
347 color_control |= S_028808_SPECIAL_OP(mode);
348 else
349 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
350
351 /* only MRT0 has dual src blend */
352 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
353 blend->cb_target_mask = target_mask;
354 blend->cb_color_control = color_control;
355 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
356 blend->alpha_to_one = state->alpha_to_one;
357
358 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
359 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
360 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
361 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
362 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
363 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
364
365 /* Copy over the registers set so far into buffer_no_blend. */
366 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
367 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
368
369 /* Only add blend registers if blending is enabled. */
370 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
371 return blend;
372 }
373
374 /* The first R600 does not support per-MRT blends */
375 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
376 r600_get_blend_control(state, 0));
377
378 if (rctx->b.family > CHIP_R600) {
379 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
380 for (int i = 0; i < 8; i++) {
381 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
382 }
383 }
384 return blend;
385 }
386
387 static void *r600_create_blend_state(struct pipe_context *ctx,
388 const struct pipe_blend_state *state)
389 {
390 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
391 }
392
393 static void *r600_create_dsa_state(struct pipe_context *ctx,
394 const struct pipe_depth_stencil_alpha_state *state)
395 {
396 unsigned db_depth_control, alpha_test_control, alpha_ref;
397 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
398
399 if (!dsa) {
400 return NULL;
401 }
402
403 r600_init_command_buffer(&dsa->buffer, 3);
404
405 dsa->valuemask[0] = state->stencil[0].valuemask;
406 dsa->valuemask[1] = state->stencil[1].valuemask;
407 dsa->writemask[0] = state->stencil[0].writemask;
408 dsa->writemask[1] = state->stencil[1].writemask;
409 dsa->zwritemask = state->depth.writemask;
410
411 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
412 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
413 S_028800_ZFUNC(state->depth.func);
414
415 /* stencil */
416 if (state->stencil[0].enabled) {
417 db_depth_control |= S_028800_STENCIL_ENABLE(1);
418 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
419 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
420 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
421 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
422
423 if (state->stencil[1].enabled) {
424 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
425 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
426 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
427 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
428 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
429 }
430 }
431
432 /* alpha */
433 alpha_test_control = 0;
434 alpha_ref = 0;
435 if (state->alpha.enabled) {
436 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
437 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
438 alpha_ref = fui(state->alpha.ref_value);
439 }
440 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
441 dsa->alpha_ref = alpha_ref;
442
443 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
444 return dsa;
445 }
446
447 static void *r600_create_rs_state(struct pipe_context *ctx,
448 const struct pipe_rasterizer_state *state)
449 {
450 struct r600_context *rctx = (struct r600_context *)ctx;
451 unsigned tmp, sc_mode_cntl, spi_interp;
452 float psize_min, psize_max;
453 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
454
455 if (!rs) {
456 return NULL;
457 }
458
459 r600_init_command_buffer(&rs->buffer, 30);
460
461 rs->scissor_enable = state->scissor;
462 rs->flatshade = state->flatshade;
463 rs->sprite_coord_enable = state->sprite_coord_enable;
464 rs->two_side = state->light_twoside;
465 rs->clip_plane_enable = state->clip_plane_enable;
466 rs->pa_sc_line_stipple = state->line_stipple_enable ?
467 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
468 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
469 rs->pa_cl_clip_cntl =
470 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
471 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
472 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
473 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
474 if (rctx->b.chip_class == R700) {
475 rs->pa_cl_clip_cntl |=
476 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
477 }
478 rs->multisample_enable = state->multisample;
479
480 /* offset */
481 rs->offset_units = state->offset_units;
482 rs->offset_scale = state->offset_scale * 16.0f;
483 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
484
485 if (state->point_size_per_vertex) {
486 psize_min = util_get_min_point_size(state);
487 psize_max = 8192;
488 } else {
489 /* Force the point size to be as if the vertex output was disabled. */
490 psize_min = state->point_size;
491 psize_max = state->point_size;
492 }
493
494 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
495 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
496 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
497 S_028A4C_PS_ITER_SAMPLE(state->multisample && rctx->ps_iter_samples > 1);
498 if (rctx->b.family == CHIP_RV770) {
499 /* workaround possible rendering corruption on RV770 with hyperz together with sample shading */
500 sc_mode_cntl |= S_028A4C_TILE_COVER_DISABLE(state->multisample && rctx->ps_iter_samples > 1);
501 }
502 if (rctx->b.chip_class >= R700) {
503 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
504 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
505 S_028A4C_R700_VPORT_SCISSOR_ENABLE(1);
506 } else {
507 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
508 }
509
510 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
511 if (state->sprite_coord_enable) {
512 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
513 S_0286D4_PNT_SPRITE_OVRD_X(2) |
514 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
515 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
516 S_0286D4_PNT_SPRITE_OVRD_W(1);
517 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
518 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
519 }
520 }
521
522 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
523 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
524 tmp = r600_pack_float_12p4(state->point_size/2);
525 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
526 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
527 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
528 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
529 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
530 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
531 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
532
533 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
534 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
535 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
536 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
537 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
538 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
539
540 rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
541 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
542 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
543 S_028814_FACE(!state->front_ccw) |
544 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
545 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
546 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
547 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
548 state->fill_back != PIPE_POLYGON_MODE_FILL) |
549 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
550 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
551 if (rctx->b.chip_class == R700) {
552 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl);
553 }
554 if (rctx->b.chip_class == R600) {
555 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC,
556 S_028350_MULTIPASS(state->rasterizer_discard));
557 }
558 return rs;
559 }
560
561 static unsigned r600_tex_filter(unsigned filter, unsigned max_aniso)
562 {
563 if (filter == PIPE_TEX_FILTER_LINEAR)
564 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_BILINEAR
565 : V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
566 else
567 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_POINT
568 : V_03C000_SQ_TEX_XY_FILTER_POINT;
569 }
570
571 static void *r600_create_sampler_state(struct pipe_context *ctx,
572 const struct pipe_sampler_state *state)
573 {
574 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
575 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
576 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
577 : state->max_anisotropy;
578 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
579
580 if (!ss) {
581 return NULL;
582 }
583
584 ss->seamless_cube_map = state->seamless_cube_map;
585 ss->border_color_use = sampler_state_needs_border_color(state);
586
587 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
588 ss->tex_sampler_words[0] =
589 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
590 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
591 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
592 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter, max_aniso)) |
593 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter, max_aniso)) |
594 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
595 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
596 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
597 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
598 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
599 ss->tex_sampler_words[1] =
600 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
601 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
602 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
603 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
604 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
605
606 if (ss->border_color_use) {
607 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
608 }
609 return ss;
610 }
611
612 static struct pipe_sampler_view *
613 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
614 unsigned width0, unsigned height0)
615
616 {
617 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
618 int stride = util_format_get_blocksize(view->base.format);
619 unsigned format, num_format, format_comp, endian;
620 uint64_t offset = view->base.u.buf.first_element * stride;
621 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
622
623 r600_vertex_data_type(view->base.format,
624 &format, &num_format, &format_comp,
625 &endian);
626
627 view->tex_resource = &tmp->resource;
628 view->skip_mip_address_reloc = true;
629
630 view->tex_resource_words[0] = offset;
631 view->tex_resource_words[1] = size - 1;
632 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(offset >> 32UL) |
633 S_038008_STRIDE(stride) |
634 S_038008_DATA_FORMAT(format) |
635 S_038008_NUM_FORMAT_ALL(num_format) |
636 S_038008_FORMAT_COMP_ALL(format_comp) |
637 S_038008_ENDIAN_SWAP(endian);
638 view->tex_resource_words[3] = 0;
639 /*
640 * in theory dword 4 is for number of elements, for use with resinfo,
641 * but it seems to utterly fail to work, the amd gpu shader analyser
642 * uses a const buffer to store the element sizes for buffer txq
643 */
644 view->tex_resource_words[4] = 0;
645 view->tex_resource_words[5] = 0;
646 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
647 return &view->base;
648 }
649
650 struct pipe_sampler_view *
651 r600_create_sampler_view_custom(struct pipe_context *ctx,
652 struct pipe_resource *texture,
653 const struct pipe_sampler_view *state,
654 unsigned width_first_level, unsigned height_first_level)
655 {
656 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
657 struct r600_texture *tmp = (struct r600_texture*)texture;
658 unsigned format, endian;
659 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
660 unsigned char swizzle[4], array_mode = 0;
661 unsigned width, height, depth, offset_level, last_level;
662 bool do_endian_swap = FALSE;
663
664 if (!view)
665 return NULL;
666
667 /* initialize base object */
668 view->base = *state;
669 view->base.texture = NULL;
670 pipe_reference(NULL, &texture->reference);
671 view->base.texture = texture;
672 view->base.reference.count = 1;
673 view->base.context = ctx;
674
675 if (texture->target == PIPE_BUFFER)
676 return texture_buffer_sampler_view(view, texture->width0, 1);
677
678 swizzle[0] = state->swizzle_r;
679 swizzle[1] = state->swizzle_g;
680 swizzle[2] = state->swizzle_b;
681 swizzle[3] = state->swizzle_a;
682
683 if (R600_BIG_ENDIAN)
684 do_endian_swap = !(tmp->is_depth && !tmp->is_flushing_texture);
685
686 format = r600_translate_texformat(ctx->screen, state->format,
687 swizzle,
688 &word4, &yuv_format, do_endian_swap);
689 assert(format != ~0);
690 if (format == ~0) {
691 FREE(view);
692 return NULL;
693 }
694
695 if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) {
696 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
697 FREE(view);
698 return NULL;
699 }
700 tmp = tmp->flushed_depth_texture;
701 }
702
703 endian = r600_colorformat_endian_swap(format, do_endian_swap);
704
705 offset_level = state->u.tex.first_level;
706 last_level = state->u.tex.last_level - offset_level;
707 width = width_first_level;
708 height = height_first_level;
709 depth = u_minify(texture->depth0, offset_level);
710 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
711
712 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
713 height = 1;
714 depth = texture->array_size;
715 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
716 depth = texture->array_size;
717 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
718 depth = texture->array_size / 6;
719
720 switch (tmp->surface.level[offset_level].mode) {
721 default:
722 case RADEON_SURF_MODE_LINEAR_ALIGNED:
723 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
724 break;
725 case RADEON_SURF_MODE_1D:
726 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
727 break;
728 case RADEON_SURF_MODE_2D:
729 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
730 break;
731 }
732
733 if (state->format == PIPE_FORMAT_X24S8_UINT ||
734 state->format == PIPE_FORMAT_S8X24_UINT ||
735 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
736 state->format == PIPE_FORMAT_S8_UINT)
737 view->is_stencil_sampler = true;
738
739 view->tex_resource = &tmp->resource;
740 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
741 S_038000_TILE_MODE(array_mode) |
742 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
743 S_038000_PITCH((pitch / 8) - 1) |
744 S_038000_TEX_WIDTH(width - 1));
745 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
746 S_038004_TEX_DEPTH(depth - 1) |
747 S_038004_DATA_FORMAT(format));
748 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
749 if (offset_level >= tmp->surface.last_level) {
750 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
751 } else {
752 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
753 }
754 view->tex_resource_words[4] = (word4 |
755 S_038010_REQUEST_SIZE(1) |
756 S_038010_ENDIAN_SWAP(endian) |
757 S_038010_BASE_LEVEL(0));
758 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
759 S_038014_LAST_ARRAY(state->u.tex.last_layer));
760 if (texture->nr_samples > 1) {
761 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
762 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
763 } else {
764 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
765 }
766 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
767 S_038018_MAX_ANISO(4 /* max 16 samples */));
768 return &view->base;
769 }
770
771 static struct pipe_sampler_view *
772 r600_create_sampler_view(struct pipe_context *ctx,
773 struct pipe_resource *tex,
774 const struct pipe_sampler_view *state)
775 {
776 return r600_create_sampler_view_custom(ctx, tex, state,
777 u_minify(tex->width0, state->u.tex.first_level),
778 u_minify(tex->height0, state->u.tex.first_level));
779 }
780
781 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
782 {
783 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
784 struct pipe_clip_state *state = &rctx->clip_state.state;
785
786 radeon_set_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
787 radeon_emit_array(cs, (unsigned*)state, 6*4);
788 }
789
790 static void r600_set_polygon_stipple(struct pipe_context *ctx,
791 const struct pipe_poly_stipple *state)
792 {
793 }
794
795 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
796 unsigned size, unsigned alignment)
797 {
798 struct pipe_resource buffer;
799
800 memset(&buffer, 0, sizeof buffer);
801 buffer.target = PIPE_BUFFER;
802 buffer.format = PIPE_FORMAT_R8_UNORM;
803 buffer.bind = PIPE_BIND_CUSTOM;
804 buffer.usage = PIPE_USAGE_DEFAULT;
805 buffer.flags = 0;
806 buffer.width0 = size;
807 buffer.height0 = 1;
808 buffer.depth0 = 1;
809 buffer.array_size = 1;
810
811 return (struct r600_resource*)
812 r600_buffer_create(&rscreen->b.b, &buffer, alignment);
813 }
814
815 static void r600_init_color_surface(struct r600_context *rctx,
816 struct r600_surface *surf,
817 bool force_cmask_fmask)
818 {
819 struct r600_screen *rscreen = rctx->screen;
820 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
821 unsigned level = surf->base.u.tex.level;
822 unsigned pitch, slice;
823 unsigned color_info;
824 unsigned color_view;
825 unsigned format, swap, ntype, endian;
826 unsigned offset;
827 const struct util_format_description *desc;
828 int i;
829 bool blend_bypass = 0, blend_clamp = 1, do_endian_swap = FALSE;
830
831 if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
832 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
833 rtex = rtex->flushed_depth_texture;
834 assert(rtex);
835 }
836
837 offset = rtex->surface.level[level].offset;
838 color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
839 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
840
841 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
842 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
843 if (slice) {
844 slice = slice - 1;
845 }
846 color_info = 0;
847 switch (rtex->surface.level[level].mode) {
848 default:
849 case RADEON_SURF_MODE_LINEAR_ALIGNED:
850 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
851 break;
852 case RADEON_SURF_MODE_1D:
853 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
854 break;
855 case RADEON_SURF_MODE_2D:
856 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
857 break;
858 }
859
860 desc = util_format_description(surf->base.format);
861
862 for (i = 0; i < 4; i++) {
863 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
864 break;
865 }
866 }
867
868 ntype = V_0280A0_NUMBER_UNORM;
869 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
870 ntype = V_0280A0_NUMBER_SRGB;
871 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
872 if (desc->channel[i].normalized)
873 ntype = V_0280A0_NUMBER_SNORM;
874 else if (desc->channel[i].pure_integer)
875 ntype = V_0280A0_NUMBER_SINT;
876 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
877 if (desc->channel[i].normalized)
878 ntype = V_0280A0_NUMBER_UNORM;
879 else if (desc->channel[i].pure_integer)
880 ntype = V_0280A0_NUMBER_UINT;
881 }
882
883 if (R600_BIG_ENDIAN)
884 do_endian_swap = !(rtex->is_depth && !rtex->is_flushing_texture);
885
886 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format,
887 do_endian_swap);
888 assert(format != ~0);
889
890 swap = r600_translate_colorswap(surf->base.format, do_endian_swap);
891 assert(swap != ~0);
892
893 endian = r600_colorformat_endian_swap(format, do_endian_swap);
894
895 /* set blend bypass according to docs if SINT/UINT or
896 8/24 COLOR variants */
897 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
898 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
899 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
900 blend_clamp = 0;
901 blend_bypass = 1;
902 }
903
904 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
905
906 color_info |= S_0280A0_FORMAT(format) |
907 S_0280A0_COMP_SWAP(swap) |
908 S_0280A0_BLEND_BYPASS(blend_bypass) |
909 S_0280A0_BLEND_CLAMP(blend_clamp) |
910 S_0280A0_NUMBER_TYPE(ntype) |
911 S_0280A0_ENDIAN(endian);
912
913 /* EXPORT_NORM is an optimzation that can be enabled for better
914 * performance in certain cases
915 */
916 if (rctx->b.chip_class == R600) {
917 /* EXPORT_NORM can be enabled if:
918 * - 11-bit or smaller UNORM/SNORM/SRGB
919 * - BLEND_CLAMP is enabled
920 * - BLEND_FLOAT32 is disabled
921 */
922 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
923 (desc->channel[i].size < 12 &&
924 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
925 ntype != V_0280A0_NUMBER_UINT &&
926 ntype != V_0280A0_NUMBER_SINT) &&
927 G_0280A0_BLEND_CLAMP(color_info) &&
928 !G_0280A0_BLEND_FLOAT32(color_info)) {
929 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
930 surf->export_16bpc = true;
931 }
932 } else {
933 /* EXPORT_NORM can be enabled if:
934 * - 11-bit or smaller UNORM/SNORM/SRGB
935 * - 16-bit or smaller FLOAT
936 */
937 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
938 ((desc->channel[i].size < 12 &&
939 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
940 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
941 (desc->channel[i].size < 17 &&
942 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
943 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
944 surf->export_16bpc = true;
945 }
946 }
947
948 /* These might not always be initialized to zero. */
949 surf->cb_color_base = offset >> 8;
950 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
951 S_028060_SLICE_TILE_MAX(slice);
952 surf->cb_color_fmask = surf->cb_color_base;
953 surf->cb_color_cmask = surf->cb_color_base;
954 surf->cb_color_mask = 0;
955
956 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
957 &rtex->resource.b.b);
958 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
959 &rtex->resource.b.b);
960
961 if (rtex->cmask.size) {
962 surf->cb_color_cmask = rtex->cmask.offset >> 8;
963 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
964
965 if (rtex->fmask.size) {
966 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
967 surf->cb_color_fmask = rtex->fmask.offset >> 8;
968 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
969 } else { /* cmask only */
970 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
971 }
972 } else if (force_cmask_fmask) {
973 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
974 *
975 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
976 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
977 * because it's not an MSAA buffer.
978 */
979 struct r600_cmask_info cmask;
980 struct r600_fmask_info fmask;
981
982 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
983 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
984
985 /* CMASK. */
986 if (!rctx->dummy_cmask ||
987 rctx->dummy_cmask->b.b.width0 < cmask.size ||
988 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
989 struct pipe_transfer *transfer;
990 void *ptr;
991
992 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
993 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
994
995 /* Set the contents to 0xCC. */
996 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
997 memset(ptr, 0xCC, cmask.size);
998 pipe_buffer_unmap(&rctx->b.b, transfer);
999 }
1000 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1001 &rctx->dummy_cmask->b.b);
1002
1003 /* FMASK. */
1004 if (!rctx->dummy_fmask ||
1005 rctx->dummy_fmask->b.b.width0 < fmask.size ||
1006 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1007 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1008 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1009
1010 }
1011 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1012 &rctx->dummy_fmask->b.b);
1013
1014 /* Init the registers. */
1015 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1016 surf->cb_color_cmask = 0;
1017 surf->cb_color_fmask = 0;
1018 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1019 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1020 }
1021
1022 surf->cb_color_info = color_info;
1023 surf->cb_color_view = color_view;
1024 surf->color_initialized = true;
1025 }
1026
1027 static void r600_init_depth_surface(struct r600_context *rctx,
1028 struct r600_surface *surf)
1029 {
1030 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1031 unsigned level, pitch, slice, format, offset, array_mode;
1032
1033 level = surf->base.u.tex.level;
1034 offset = rtex->surface.level[level].offset;
1035 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1036 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1037 if (slice) {
1038 slice = slice - 1;
1039 }
1040 switch (rtex->surface.level[level].mode) {
1041 case RADEON_SURF_MODE_2D:
1042 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1043 break;
1044 case RADEON_SURF_MODE_1D:
1045 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1046 default:
1047 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1048 break;
1049 }
1050
1051 format = r600_translate_dbformat(surf->base.format);
1052 assert(format != ~0);
1053
1054 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1055 surf->db_depth_base = offset >> 8;
1056 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1057 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1058 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1059 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1060
1061 switch (surf->base.format) {
1062 case PIPE_FORMAT_Z24X8_UNORM:
1063 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1064 surf->pa_su_poly_offset_db_fmt_cntl =
1065 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1066 break;
1067 case PIPE_FORMAT_Z32_FLOAT:
1068 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1069 surf->pa_su_poly_offset_db_fmt_cntl =
1070 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1071 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1072 break;
1073 case PIPE_FORMAT_Z16_UNORM:
1074 surf->pa_su_poly_offset_db_fmt_cntl =
1075 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1076 break;
1077 default:;
1078 }
1079
1080 /* use htile only for first level */
1081 if (rtex->htile_buffer && !level) {
1082 surf->db_htile_data_base = 0;
1083 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1084 S_028D24_HTILE_HEIGHT(1) |
1085 S_028D24_FULL_CACHE(1);
1086 /* preload is not working properly on r6xx/r7xx */
1087 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1088 }
1089
1090 surf->depth_initialized = true;
1091 }
1092
1093 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1094 const struct pipe_framebuffer_state *state)
1095 {
1096 struct r600_context *rctx = (struct r600_context *)ctx;
1097 struct r600_surface *surf;
1098 struct r600_texture *rtex;
1099 unsigned i;
1100
1101 /* Flush TC when changing the framebuffer state, because the only
1102 * client not using TC that can change textures is the framebuffer.
1103 * Other places don't typically have to flush TC.
1104 */
1105 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1106 R600_CONTEXT_FLUSH_AND_INV |
1107 R600_CONTEXT_FLUSH_AND_INV_CB |
1108 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1109 R600_CONTEXT_FLUSH_AND_INV_DB |
1110 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1111 R600_CONTEXT_INV_TEX_CACHE;
1112
1113 /* Set the new state. */
1114 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1115
1116 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1117 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1118 util_format_is_pure_integer(state->cbufs[0]->format);
1119 rctx->framebuffer.compressed_cb_mask = 0;
1120 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1121 state->cbufs[0] && state->cbufs[1] &&
1122 state->cbufs[0]->texture->nr_samples > 1 &&
1123 state->cbufs[1]->texture->nr_samples <= 1;
1124 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1125
1126 /* Colorbuffers. */
1127 for (i = 0; i < state->nr_cbufs; i++) {
1128 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1129 bool force_cmask_fmask = rctx->b.chip_class == R600 &&
1130 rctx->framebuffer.is_msaa_resolve &&
1131 i == 1;
1132
1133 surf = (struct r600_surface*)state->cbufs[i];
1134 if (!surf)
1135 continue;
1136
1137 rtex = (struct r600_texture*)surf->base.texture;
1138 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1139
1140 if (!surf->color_initialized || force_cmask_fmask) {
1141 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1142 if (force_cmask_fmask) {
1143 /* re-initialize later without compression */
1144 surf->color_initialized = false;
1145 }
1146 }
1147
1148 if (!surf->export_16bpc) {
1149 rctx->framebuffer.export_16bpc = false;
1150 }
1151
1152 if (rtex->fmask.size && rtex->cmask.size) {
1153 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1154 }
1155 }
1156
1157 /* Update alpha-test state dependencies.
1158 * Alpha-test is done on the first colorbuffer only. */
1159 if (state->nr_cbufs) {
1160 bool alphatest_bypass = false;
1161
1162 surf = (struct r600_surface*)state->cbufs[0];
1163 if (surf) {
1164 alphatest_bypass = surf->alphatest_bypass;
1165 }
1166
1167 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1168 rctx->alphatest_state.bypass = alphatest_bypass;
1169 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1170 }
1171 }
1172
1173 /* ZS buffer. */
1174 if (state->zsbuf) {
1175 surf = (struct r600_surface*)state->zsbuf;
1176
1177 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1178
1179 if (!surf->depth_initialized) {
1180 r600_init_depth_surface(rctx, surf);
1181 }
1182
1183 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1184 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1185 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1186 }
1187
1188 if (rctx->db_state.rsurf != surf) {
1189 rctx->db_state.rsurf = surf;
1190 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1191 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1192 }
1193 } else if (rctx->db_state.rsurf) {
1194 rctx->db_state.rsurf = NULL;
1195 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1196 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1197 }
1198
1199 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1200 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1201 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1202 }
1203
1204 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1205 rctx->alphatest_state.bypass = false;
1206 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1207 }
1208
1209 /* Calculate the CS size. */
1210 rctx->framebuffer.atom.num_dw =
1211 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1212
1213 if (rctx->framebuffer.state.nr_cbufs) {
1214 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
1215 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
1216 }
1217 if (rctx->framebuffer.state.zsbuf) {
1218 rctx->framebuffer.atom.num_dw += 16;
1219 } else if (rctx->screen->b.info.drm_minor >= 18) {
1220 rctx->framebuffer.atom.num_dw += 3;
1221 }
1222 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1223 rctx->framebuffer.atom.num_dw += 2;
1224 }
1225
1226 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1227
1228 r600_set_sample_locations_constant_buffer(rctx);
1229 }
1230
1231 static uint32_t sample_locs_2x[] = {
1232 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1233 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1234 };
1235 static unsigned max_dist_2x = 4;
1236
1237 static uint32_t sample_locs_4x[] = {
1238 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1239 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1240 };
1241 static unsigned max_dist_4x = 6;
1242 static uint32_t sample_locs_8x[] = {
1243 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1244 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1245 };
1246 static unsigned max_dist_8x = 7;
1247
1248 static void r600_get_sample_position(struct pipe_context *ctx,
1249 unsigned sample_count,
1250 unsigned sample_index,
1251 float *out_value)
1252 {
1253 int offset, index;
1254 struct {
1255 int idx:4;
1256 } val;
1257 switch (sample_count) {
1258 case 1:
1259 default:
1260 out_value[0] = out_value[1] = 0.5;
1261 break;
1262 case 2:
1263 offset = 4 * (sample_index * 2);
1264 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1265 out_value[0] = (float)(val.idx + 8) / 16.0f;
1266 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1267 out_value[1] = (float)(val.idx + 8) / 16.0f;
1268 break;
1269 case 4:
1270 offset = 4 * (sample_index * 2);
1271 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1272 out_value[0] = (float)(val.idx + 8) / 16.0f;
1273 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1274 out_value[1] = (float)(val.idx + 8) / 16.0f;
1275 break;
1276 case 8:
1277 offset = 4 * (sample_index % 4 * 2);
1278 index = (sample_index / 4);
1279 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1280 out_value[0] = (float)(val.idx + 8) / 16.0f;
1281 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1282 out_value[1] = (float)(val.idx + 8) / 16.0f;
1283 break;
1284 }
1285 }
1286
1287 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1288 {
1289 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1290 unsigned max_dist = 0;
1291
1292 if (rctx->b.family == CHIP_R600) {
1293 switch (nr_samples) {
1294 default:
1295 nr_samples = 0;
1296 break;
1297 case 2:
1298 radeon_set_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1299 max_dist = max_dist_2x;
1300 break;
1301 case 4:
1302 radeon_set_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1303 max_dist = max_dist_4x;
1304 break;
1305 case 8:
1306 radeon_set_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1307 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1308 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1309 max_dist = max_dist_8x;
1310 break;
1311 }
1312 } else {
1313 switch (nr_samples) {
1314 default:
1315 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1316 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1317 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1318 nr_samples = 0;
1319 break;
1320 case 2:
1321 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1322 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1323 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1324 max_dist = max_dist_2x;
1325 break;
1326 case 4:
1327 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1328 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1329 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1330 max_dist = max_dist_4x;
1331 break;
1332 case 8:
1333 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1334 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1335 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1336 max_dist = max_dist_8x;
1337 break;
1338 }
1339 }
1340
1341 if (nr_samples > 1) {
1342 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1343 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1344 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1345 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1346 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1347 } else {
1348 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1349 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1350 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1351 }
1352 }
1353
1354 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1355 {
1356 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1357 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1358 unsigned nr_cbufs = state->nr_cbufs;
1359 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1360 unsigned i, sbu = 0;
1361
1362 /* Colorbuffers. */
1363 radeon_set_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1364 for (i = 0; i < nr_cbufs; i++) {
1365 radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0);
1366 }
1367 /* set CB_COLOR1_INFO for possible dual-src blending */
1368 if (i == 1 && cb[0]) {
1369 radeon_emit(cs, cb[0]->cb_color_info);
1370 i++;
1371 }
1372 for (; i < 8; i++) {
1373 radeon_emit(cs, 0);
1374 }
1375
1376 if (nr_cbufs) {
1377 for (i = 0; i < nr_cbufs; i++) {
1378 unsigned reloc;
1379
1380 if (!cb[i])
1381 continue;
1382
1383 /* COLOR_BASE */
1384 radeon_set_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1385
1386 reloc = radeon_add_to_buffer_list(&rctx->b,
1387 &rctx->b.gfx,
1388 (struct r600_resource*)cb[i]->base.texture,
1389 RADEON_USAGE_READWRITE,
1390 cb[i]->base.texture->nr_samples > 1 ?
1391 RADEON_PRIO_COLOR_BUFFER_MSAA :
1392 RADEON_PRIO_COLOR_BUFFER);
1393 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1394 radeon_emit(cs, reloc);
1395
1396 /* FMASK */
1397 radeon_set_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1398
1399 reloc = radeon_add_to_buffer_list(&rctx->b,
1400 &rctx->b.gfx,
1401 cb[i]->cb_buffer_fmask,
1402 RADEON_USAGE_READWRITE,
1403 cb[i]->base.texture->nr_samples > 1 ?
1404 RADEON_PRIO_COLOR_BUFFER_MSAA :
1405 RADEON_PRIO_COLOR_BUFFER);
1406 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1407 radeon_emit(cs, reloc);
1408
1409 /* CMASK */
1410 radeon_set_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1411
1412 reloc = radeon_add_to_buffer_list(&rctx->b,
1413 &rctx->b.gfx,
1414 cb[i]->cb_buffer_cmask,
1415 RADEON_USAGE_READWRITE,
1416 cb[i]->base.texture->nr_samples > 1 ?
1417 RADEON_PRIO_COLOR_BUFFER_MSAA :
1418 RADEON_PRIO_COLOR_BUFFER);
1419 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1420 radeon_emit(cs, reloc);
1421 }
1422
1423 radeon_set_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1424 for (i = 0; i < nr_cbufs; i++) {
1425 radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0);
1426 }
1427
1428 radeon_set_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1429 for (i = 0; i < nr_cbufs; i++) {
1430 radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0);
1431 }
1432
1433 radeon_set_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1434 for (i = 0; i < nr_cbufs; i++) {
1435 radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0);
1436 }
1437
1438 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1439 }
1440
1441 /* SURFACE_BASE_UPDATE */
1442 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1443 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1444 radeon_emit(cs, sbu);
1445 sbu = 0;
1446 }
1447
1448 /* Zbuffer. */
1449 if (state->zsbuf) {
1450 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1451 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1452 &rctx->b.gfx,
1453 (struct r600_resource*)state->zsbuf->texture,
1454 RADEON_USAGE_READWRITE,
1455 surf->base.texture->nr_samples > 1 ?
1456 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1457 RADEON_PRIO_DEPTH_BUFFER);
1458
1459 radeon_set_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1460 surf->pa_su_poly_offset_db_fmt_cntl);
1461
1462 radeon_set_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1463 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1464 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1465 radeon_set_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1466 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1467 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1468
1469 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1470 radeon_emit(cs, reloc);
1471
1472 radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1473
1474 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1475 } else if (rctx->screen->b.info.drm_minor >= 18) {
1476 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1477 * Older kernels are out of luck. */
1478 radeon_set_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1479 }
1480
1481 /* SURFACE_BASE_UPDATE */
1482 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1483 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1484 radeon_emit(cs, sbu);
1485 sbu = 0;
1486 }
1487
1488 /* Framebuffer dimensions. */
1489 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1490 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1491 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1492 radeon_emit(cs, S_028244_BR_X(state->width) |
1493 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1494
1495 if (rctx->framebuffer.is_msaa_resolve) {
1496 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1497 } else {
1498 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1499 * will assure that the alpha-test will work even if there is
1500 * no colorbuffer bound. */
1501 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1502 (1ull << MAX2(nr_cbufs, 1)) - 1);
1503 }
1504
1505 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1506 }
1507
1508 static void r600_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1509 {
1510 struct r600_context *rctx = (struct r600_context *)ctx;
1511
1512 if (rctx->ps_iter_samples == min_samples)
1513 return;
1514
1515 rctx->ps_iter_samples = min_samples;
1516 if (rctx->framebuffer.nr_samples > 1) {
1517 r600_mark_atom_dirty(rctx, &rctx->rasterizer_state.atom);
1518 if (rctx->b.chip_class == R600)
1519 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1520 }
1521 }
1522
1523 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1524 {
1525 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1526 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1527
1528 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1529 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1530 if (rctx->b.chip_class == R600) {
1531 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1532 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1533 } else {
1534 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1535 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1536 }
1537 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1538 } else {
1539 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1540 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1541 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1542
1543 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1544 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1545 /* Always enable the first color output to make sure alpha-test works even without one. */
1546 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1547 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1548 a->cb_color_control |
1549 S_028808_MULTIWRITE_ENABLE(multiwrite));
1550 }
1551 }
1552
1553 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1554 {
1555 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1556 struct r600_db_state *a = (struct r600_db_state*)atom;
1557
1558 if (a->rsurf && a->rsurf->db_htile_surface) {
1559 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1560 unsigned reloc_idx;
1561
1562 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1563 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1564 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1565 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
1566 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1567 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1568 radeon_emit(cs, reloc_idx);
1569 } else {
1570 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1571 }
1572 }
1573
1574 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1575 {
1576 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1577 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1578 unsigned db_render_control = 0;
1579 unsigned db_render_override =
1580 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1581 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1582
1583 if (rctx->b.chip_class >= R700) {
1584 switch (a->ps_conservative_z) {
1585 default: /* fall through */
1586 case TGSI_FS_DEPTH_LAYOUT_ANY:
1587 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_ANY_Z);
1588 break;
1589 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1590 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_GREATER_THAN_Z);
1591 break;
1592 case TGSI_FS_DEPTH_LAYOUT_LESS:
1593 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_LESS_THAN_Z);
1594 break;
1595 }
1596 }
1597
1598 if (rctx->b.num_occlusion_queries > 0 &&
1599 !a->occlusion_queries_disabled) {
1600 if (rctx->b.chip_class >= R700) {
1601 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1602 }
1603 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1604 } else {
1605 db_render_control |= S_028D0C_ZPASS_INCREMENT_DISABLE(1);
1606 }
1607
1608 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
1609 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1610 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1611 /* This is to fix a lockup when hyperz and alpha test are enabled at
1612 * the same time somehow GPU get confuse on which order to pick for
1613 * z test
1614 */
1615 if (rctx->alphatest_state.sx_alpha_test_control) {
1616 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
1617 }
1618 } else {
1619 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1620 }
1621 if (rctx->b.chip_class == R600 && rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) {
1622 /* sample shading and hyperz causes lockups on R6xx chips */
1623 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1624 }
1625 if (a->flush_depthstencil_through_cb) {
1626 assert(a->copy_depth || a->copy_stencil);
1627
1628 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1629 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1630 S_028D0C_COPY_CENTROID(1) |
1631 S_028D0C_COPY_SAMPLE(a->copy_sample);
1632
1633 if (rctx->b.chip_class == R600)
1634 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1635
1636 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
1637 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
1638 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1639 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1640 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1641 S_028D0C_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1642 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1643 }
1644 if (a->htile_clear) {
1645 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1646 }
1647
1648 /* RV770 workaround for a hang with 8x MSAA. */
1649 if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) {
1650 db_render_override |= S_028D10_MAX_TILES_IN_DTT(6);
1651 }
1652
1653 radeon_set_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1654 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1655 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1656 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1657 }
1658
1659 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1660 {
1661 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1662 struct r600_config_state *a = (struct r600_config_state*)atom;
1663
1664 radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1665 radeon_set_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
1666 }
1667
1668 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1669 {
1670 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1671 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1672
1673 while (dirty_mask) {
1674 struct pipe_vertex_buffer *vb;
1675 struct r600_resource *rbuffer;
1676 unsigned offset;
1677 unsigned buffer_index = u_bit_scan(&dirty_mask);
1678
1679 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1680 rbuffer = (struct r600_resource*)vb->buffer;
1681 assert(rbuffer);
1682
1683 offset = vb->buffer_offset;
1684
1685 /* fetch resources start at index 320 (OFFSET_FS) */
1686 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1687 radeon_emit(cs, (R600_FETCH_CONSTANTS_OFFSET_FS + buffer_index) * 7);
1688 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1689 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1690 radeon_emit(cs, /* RESOURCEi_WORD2 */
1691 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1692 S_038008_STRIDE(vb->stride));
1693 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1694 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1695 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1696 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1697
1698 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1699 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1700 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1701 }
1702 }
1703
1704 static void r600_emit_constant_buffers(struct r600_context *rctx,
1705 struct r600_constbuf_state *state,
1706 unsigned buffer_id_base,
1707 unsigned reg_alu_constbuf_size,
1708 unsigned reg_alu_const_cache)
1709 {
1710 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1711 uint32_t dirty_mask = state->dirty_mask;
1712
1713 while (dirty_mask) {
1714 struct pipe_constant_buffer *cb;
1715 struct r600_resource *rbuffer;
1716 unsigned offset;
1717 unsigned buffer_index = ffs(dirty_mask) - 1;
1718 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1719 cb = &state->cb[buffer_index];
1720 rbuffer = (struct r600_resource*)cb->buffer;
1721 assert(rbuffer);
1722
1723 offset = cb->buffer_offset;
1724
1725 if (!gs_ring_buffer) {
1726 radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1727 DIV_ROUND_UP(cb->buffer_size, 256));
1728 radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1729 }
1730
1731 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1732 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1733 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1734
1735 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1736 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
1737 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1738 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1739 radeon_emit(cs, /* RESOURCEi_WORD2 */
1740 S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1741 S_038008_STRIDE(gs_ring_buffer ? 4 : 16));
1742 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1743 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1744 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1745 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1746
1747 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1748 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1749 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1750
1751 dirty_mask &= ~(1 << buffer_index);
1752 }
1753 state->dirty_mask = 0;
1754 }
1755
1756 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1757 {
1758 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1759 R600_FETCH_CONSTANTS_OFFSET_VS,
1760 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1761 R_028980_ALU_CONST_CACHE_VS_0);
1762 }
1763
1764 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1765 {
1766 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1767 R600_FETCH_CONSTANTS_OFFSET_GS,
1768 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1769 R_0289C0_ALU_CONST_CACHE_GS_0);
1770 }
1771
1772 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1773 {
1774 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1775 R600_FETCH_CONSTANTS_OFFSET_PS,
1776 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1777 R_028940_ALU_CONST_CACHE_PS_0);
1778 }
1779
1780 static void r600_emit_sampler_views(struct r600_context *rctx,
1781 struct r600_samplerview_state *state,
1782 unsigned resource_id_base)
1783 {
1784 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1785 uint32_t dirty_mask = state->dirty_mask;
1786
1787 while (dirty_mask) {
1788 struct r600_pipe_sampler_view *rview;
1789 unsigned resource_index = u_bit_scan(&dirty_mask);
1790 unsigned reloc;
1791
1792 rview = state->views[resource_index];
1793 assert(rview);
1794
1795 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1796 radeon_emit(cs, (resource_id_base + resource_index) * 7);
1797 radeon_emit_array(cs, rview->tex_resource_words, 7);
1798
1799 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
1800 RADEON_USAGE_READ,
1801 r600_get_sampler_view_priority(rview->tex_resource));
1802 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1803 radeon_emit(cs, reloc);
1804 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1805 radeon_emit(cs, reloc);
1806 }
1807 state->dirty_mask = 0;
1808 }
1809
1810
1811 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1812 {
1813 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, R600_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS);
1814 }
1815
1816 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1817 {
1818 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, R600_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS);
1819 }
1820
1821 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1822 {
1823 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS);
1824 }
1825
1826 static void r600_emit_sampler_states(struct r600_context *rctx,
1827 struct r600_textures_info *texinfo,
1828 unsigned resource_id_base,
1829 unsigned border_color_reg)
1830 {
1831 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1832 uint32_t dirty_mask = texinfo->states.dirty_mask;
1833
1834 while (dirty_mask) {
1835 struct r600_pipe_sampler_state *rstate;
1836 struct r600_pipe_sampler_view *rview;
1837 unsigned i = u_bit_scan(&dirty_mask);
1838
1839 rstate = texinfo->states.states[i];
1840 assert(rstate);
1841 rview = texinfo->views.views[i];
1842
1843 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1844 * filtering between layers.
1845 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1846 */
1847 if (rview) {
1848 enum pipe_texture_target target = rview->base.texture->target;
1849 if (target == PIPE_TEXTURE_1D_ARRAY ||
1850 target == PIPE_TEXTURE_2D_ARRAY) {
1851 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1852 texinfo->is_array_sampler[i] = true;
1853 } else {
1854 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1855 texinfo->is_array_sampler[i] = false;
1856 }
1857 }
1858
1859 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1860 radeon_emit(cs, (resource_id_base + i) * 3);
1861 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
1862
1863 if (rstate->border_color_use) {
1864 unsigned offset;
1865
1866 offset = border_color_reg;
1867 offset += i * 16;
1868 radeon_set_config_reg_seq(cs, offset, 4);
1869 radeon_emit_array(cs, rstate->border_color.ui, 4);
1870 }
1871 }
1872 texinfo->states.dirty_mask = 0;
1873 }
1874
1875 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1876 {
1877 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1878 }
1879
1880 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1881 {
1882 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1883 }
1884
1885 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1886 {
1887 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1888 }
1889
1890 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1891 {
1892 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1893 unsigned tmp;
1894
1895 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1896 S_009508_SYNC_GRADIENT(1) |
1897 S_009508_SYNC_WALKER(1) |
1898 S_009508_SYNC_ALIGNER(1);
1899 if (!rctx->seamless_cube_map.enabled) {
1900 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1901 }
1902 radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1903 }
1904
1905 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1906 {
1907 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1908 uint8_t mask = s->sample_mask;
1909
1910 radeon_set_context_reg(rctx->b.gfx.cs, R_028C48_PA_SC_AA_MASK,
1911 mask | (mask << 8) | (mask << 16) | (mask << 24));
1912 }
1913
1914 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
1915 {
1916 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1917 struct r600_cso_state *state = (struct r600_cso_state*)a;
1918 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
1919
1920 radeon_set_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
1921 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1922 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
1923 RADEON_USAGE_READ,
1924 RADEON_PRIO_INTERNAL_SHADER));
1925 }
1926
1927 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
1928 {
1929 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1930 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
1931
1932 uint32_t v2 = 0, primid = 0;
1933
1934 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
1935 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1936 primid = 1;
1937 }
1938
1939 if (state->geom_enable) {
1940 uint32_t cut_val;
1941
1942 if (rctx->gs_shader->gs_max_out_vertices <= 128)
1943 cut_val = V_028A40_GS_CUT_128;
1944 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
1945 cut_val = V_028A40_GS_CUT_256;
1946 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
1947 cut_val = V_028A40_GS_CUT_512;
1948 else
1949 cut_val = V_028A40_GS_CUT_1024;
1950
1951 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1952 S_028A40_CUT_MODE(cut_val);
1953
1954 if (rctx->gs_shader->current->shader.gs_prim_id_input)
1955 primid = 1;
1956 }
1957
1958 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
1959 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
1960 }
1961
1962 static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
1963 {
1964 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1965 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
1966 struct r600_resource *rbuffer;
1967
1968 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1969 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1970 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1971
1972 if (state->enable) {
1973 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
1974 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
1975 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1976 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1977 RADEON_USAGE_READWRITE,
1978 RADEON_PRIO_RINGS_STREAMOUT));
1979 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
1980 state->esgs_ring.buffer_size >> 8);
1981
1982 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
1983 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
1984 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1985 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1986 RADEON_USAGE_READWRITE,
1987 RADEON_PRIO_RINGS_STREAMOUT));
1988 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
1989 state->gsvs_ring.buffer_size >> 8);
1990 } else {
1991 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
1992 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
1993 }
1994
1995 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1996 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1997 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1998 }
1999
2000 /* Adjust GPR allocation on R6xx/R7xx */
2001 bool r600_adjust_gprs(struct r600_context *rctx)
2002 {
2003 unsigned num_gprs[R600_NUM_HW_STAGES];
2004 unsigned new_gprs[R600_NUM_HW_STAGES];
2005 unsigned cur_gprs[R600_NUM_HW_STAGES];
2006 unsigned def_gprs[R600_NUM_HW_STAGES];
2007 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
2008 unsigned max_gprs;
2009 unsigned tmp, tmp2;
2010 unsigned i;
2011 bool need_recalc = false, use_default = true;
2012
2013 /* hardware will reserve twice num_clause_temp_gprs */
2014 max_gprs = def_num_clause_temp_gprs * 2;
2015 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2016 def_gprs[i] = rctx->default_gprs[i];
2017 max_gprs += def_gprs[i];
2018 }
2019
2020 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2021 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2022 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2023 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2024
2025 num_gprs[R600_HW_STAGE_PS] = rctx->ps_shader->current->shader.bc.ngpr;
2026 if (rctx->gs_shader) {
2027 num_gprs[R600_HW_STAGE_ES] = rctx->vs_shader->current->shader.bc.ngpr;
2028 num_gprs[R600_HW_STAGE_GS] = rctx->gs_shader->current->shader.bc.ngpr;
2029 num_gprs[R600_HW_STAGE_VS] = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
2030 } else {
2031 num_gprs[R600_HW_STAGE_ES] = 0;
2032 num_gprs[R600_HW_STAGE_GS] = 0;
2033 num_gprs[R600_HW_STAGE_VS] = rctx->vs_shader->current->shader.bc.ngpr;
2034 }
2035
2036 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2037 new_gprs[i] = num_gprs[i];
2038 if (new_gprs[i] > cur_gprs[i])
2039 need_recalc = true;
2040 if (new_gprs[i] > def_gprs[i])
2041 use_default = false;
2042 }
2043
2044 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2045 if (!need_recalc)
2046 return true;
2047
2048 /* try to use switch back to default */
2049 if (!use_default) {
2050 /* always privilege vs stage so that at worst we have the
2051 * pixel stage producing wrong output (not the vertex
2052 * stage) */
2053 new_gprs[R600_HW_STAGE_PS] = max_gprs - def_num_clause_temp_gprs * 2;
2054 for (i = R600_HW_STAGE_VS; i < R600_NUM_HW_STAGES; i++)
2055 new_gprs[R600_HW_STAGE_PS] -= new_gprs[i];
2056 } else {
2057 for (i = 0; i < R600_NUM_HW_STAGES; i++)
2058 new_gprs[i] = def_gprs[i];
2059 }
2060
2061 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2062 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2063 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2064 * it will lockup. So in this case just discard the draw command
2065 * and don't change the current gprs repartitions.
2066 */
2067 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2068 if (num_gprs[i] > new_gprs[i]) {
2069 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2070 "for a combined maximum of %d\n",
2071 num_gprs[R600_HW_STAGE_PS], num_gprs[R600_HW_STAGE_VS], num_gprs[R600_HW_STAGE_ES], num_gprs[R600_HW_STAGE_GS], max_gprs);
2072 return false;
2073 }
2074 }
2075
2076 /* in some case we endup recomputing the current value */
2077 tmp = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
2078 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
2079 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2080
2081 tmp2 = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
2082 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
2083 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2084 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2085 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2;
2086 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
2087 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2088 }
2089 return true;
2090 }
2091
2092 void r600_init_atom_start_cs(struct r600_context *rctx)
2093 {
2094 int ps_prio;
2095 int vs_prio;
2096 int gs_prio;
2097 int es_prio;
2098 int num_ps_gprs;
2099 int num_vs_gprs;
2100 int num_gs_gprs;
2101 int num_es_gprs;
2102 int num_temp_gprs;
2103 int num_ps_threads;
2104 int num_vs_threads;
2105 int num_gs_threads;
2106 int num_es_threads;
2107 int num_ps_stack_entries;
2108 int num_vs_stack_entries;
2109 int num_gs_stack_entries;
2110 int num_es_stack_entries;
2111 enum radeon_family family;
2112 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2113 uint32_t tmp, i;
2114
2115 r600_init_command_buffer(cb, 256);
2116
2117 /* R6xx requires this packet at the start of each command buffer */
2118 if (rctx->b.chip_class == R600) {
2119 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2120 r600_store_value(cb, 0);
2121 }
2122 /* All asics require this one */
2123 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2124 r600_store_value(cb, 0x80000000);
2125 r600_store_value(cb, 0x80000000);
2126
2127 /* We're setting config registers here. */
2128 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2129 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2130
2131 /* This enables pipeline stat & streamout queries.
2132 * They are only disabled by blits.
2133 */
2134 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2135 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2136
2137 family = rctx->b.family;
2138 ps_prio = 0;
2139 vs_prio = 1;
2140 gs_prio = 2;
2141 es_prio = 3;
2142 switch (family) {
2143 case CHIP_R600:
2144 num_ps_gprs = 192;
2145 num_vs_gprs = 56;
2146 num_temp_gprs = 4;
2147 num_gs_gprs = 0;
2148 num_es_gprs = 0;
2149 num_ps_threads = 136;
2150 num_vs_threads = 48;
2151 num_gs_threads = 4;
2152 num_es_threads = 4;
2153 num_ps_stack_entries = 128;
2154 num_vs_stack_entries = 128;
2155 num_gs_stack_entries = 0;
2156 num_es_stack_entries = 0;
2157 break;
2158 case CHIP_RV630:
2159 case CHIP_RV635:
2160 num_ps_gprs = 84;
2161 num_vs_gprs = 36;
2162 num_temp_gprs = 4;
2163 num_gs_gprs = 0;
2164 num_es_gprs = 0;
2165 num_ps_threads = 144;
2166 num_vs_threads = 40;
2167 num_gs_threads = 4;
2168 num_es_threads = 4;
2169 num_ps_stack_entries = 40;
2170 num_vs_stack_entries = 40;
2171 num_gs_stack_entries = 32;
2172 num_es_stack_entries = 16;
2173 break;
2174 case CHIP_RV610:
2175 case CHIP_RV620:
2176 case CHIP_RS780:
2177 case CHIP_RS880:
2178 default:
2179 num_ps_gprs = 84;
2180 num_vs_gprs = 36;
2181 num_temp_gprs = 4;
2182 num_gs_gprs = 0;
2183 num_es_gprs = 0;
2184 /* use limits 40 VS and at least 16 ES/GS */
2185 num_ps_threads = 120;
2186 num_vs_threads = 40;
2187 num_gs_threads = 16;
2188 num_es_threads = 16;
2189 num_ps_stack_entries = 40;
2190 num_vs_stack_entries = 40;
2191 num_gs_stack_entries = 32;
2192 num_es_stack_entries = 16;
2193 break;
2194 case CHIP_RV670:
2195 num_ps_gprs = 144;
2196 num_vs_gprs = 40;
2197 num_temp_gprs = 4;
2198 num_gs_gprs = 0;
2199 num_es_gprs = 0;
2200 num_ps_threads = 136;
2201 num_vs_threads = 48;
2202 num_gs_threads = 4;
2203 num_es_threads = 4;
2204 num_ps_stack_entries = 40;
2205 num_vs_stack_entries = 40;
2206 num_gs_stack_entries = 32;
2207 num_es_stack_entries = 16;
2208 break;
2209 case CHIP_RV770:
2210 num_ps_gprs = 130;
2211 num_vs_gprs = 56;
2212 num_temp_gprs = 4;
2213 num_gs_gprs = 31;
2214 num_es_gprs = 31;
2215 num_ps_threads = 180;
2216 num_vs_threads = 60;
2217 num_gs_threads = 4;
2218 num_es_threads = 4;
2219 num_ps_stack_entries = 128;
2220 num_vs_stack_entries = 128;
2221 num_gs_stack_entries = 128;
2222 num_es_stack_entries = 128;
2223 break;
2224 case CHIP_RV730:
2225 case CHIP_RV740:
2226 num_ps_gprs = 84;
2227 num_vs_gprs = 36;
2228 num_temp_gprs = 4;
2229 num_gs_gprs = 0;
2230 num_es_gprs = 0;
2231 num_ps_threads = 180;
2232 num_vs_threads = 60;
2233 num_gs_threads = 4;
2234 num_es_threads = 4;
2235 num_ps_stack_entries = 128;
2236 num_vs_stack_entries = 128;
2237 num_gs_stack_entries = 0;
2238 num_es_stack_entries = 0;
2239 break;
2240 case CHIP_RV710:
2241 num_ps_gprs = 192;
2242 num_vs_gprs = 56;
2243 num_temp_gprs = 4;
2244 num_gs_gprs = 0;
2245 num_es_gprs = 0;
2246 num_ps_threads = 136;
2247 num_vs_threads = 48;
2248 num_gs_threads = 4;
2249 num_es_threads = 4;
2250 num_ps_stack_entries = 128;
2251 num_vs_stack_entries = 128;
2252 num_gs_stack_entries = 0;
2253 num_es_stack_entries = 0;
2254 break;
2255 }
2256
2257 rctx->default_gprs[R600_HW_STAGE_PS] = num_ps_gprs;
2258 rctx->default_gprs[R600_HW_STAGE_VS] = num_vs_gprs;
2259 rctx->default_gprs[R600_HW_STAGE_GS] = 0;
2260 rctx->default_gprs[R600_HW_STAGE_ES] = 0;
2261
2262 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2263
2264 /* SQ_CONFIG */
2265 tmp = 0;
2266 switch (family) {
2267 case CHIP_RV610:
2268 case CHIP_RV620:
2269 case CHIP_RS780:
2270 case CHIP_RS880:
2271 case CHIP_RV710:
2272 break;
2273 default:
2274 tmp |= S_008C00_VC_ENABLE(1);
2275 break;
2276 }
2277 tmp |= S_008C00_DX9_CONSTS(0);
2278 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2279 tmp |= S_008C00_PS_PRIO(ps_prio);
2280 tmp |= S_008C00_VS_PRIO(vs_prio);
2281 tmp |= S_008C00_GS_PRIO(gs_prio);
2282 tmp |= S_008C00_ES_PRIO(es_prio);
2283 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2284
2285 /* SQ_GPR_RESOURCE_MGMT_2 */
2286 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2287 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2288 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2289 r600_store_value(cb, tmp);
2290
2291 /* SQ_THREAD_RESOURCE_MGMT */
2292 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2293 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2294 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2295 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2296 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2297
2298 /* SQ_STACK_RESOURCE_MGMT_1 */
2299 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2300 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2301 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2302
2303 /* SQ_STACK_RESOURCE_MGMT_2 */
2304 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2305 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2306 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2307
2308 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2309
2310 if (rctx->b.chip_class >= R700) {
2311 r600_store_context_reg(cb, R_028A50_VGT_ENHANCE, 4);
2312 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2313 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2314 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2315 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2316 } else {
2317 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2318 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2319 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2320 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2321 }
2322 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2323 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2324 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2325 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2326 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2327 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2328 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2329 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2330 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2331 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2332
2333 /* to avoid GPU doing any preloading of constant from random address */
2334 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2335 for (i = 0; i < 16; i++)
2336 r600_store_value(cb, 0);
2337
2338 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2339 for (i = 0; i < 16; i++)
2340 r600_store_value(cb, 0);
2341
2342 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2343 for (i = 0; i < 16; i++)
2344 r600_store_value(cb, 0);
2345
2346 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2347 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2348 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2349 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2350 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2351 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2352 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2353 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2354 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2355 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2356 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2357 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2358 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2359 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2360
2361 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2362 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2363 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2364
2365 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2366 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2367 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2368
2369 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2370
2371 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2372
2373 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2374
2375 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2376 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2377 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2378 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2379
2380 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2381 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2382 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2383 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2384
2385 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2386 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2387
2388 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2389 for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2390 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2391 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2392 }
2393
2394 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2395 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2396
2397 if (rctx->b.chip_class >= R700) {
2398 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2399 }
2400
2401 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2402 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2403 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2404 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2405 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2406
2407 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2408 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2409 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2410
2411 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2412 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2413 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2414
2415 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5);
2416 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2417 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2418 r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2419 r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2420 r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2421
2422 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2423
2424 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2425 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2426 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2427
2428 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2429
2430 if (rctx->b.chip_class == R700)
2431 r600_store_context_reg(cb, R_028350_SX_MISC, 0);
2432 if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
2433 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2434
2435 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2436 if (rctx->screen->b.has_streamout) {
2437 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2438 }
2439
2440 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2441 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2442 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF);
2443 }
2444
2445 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2446 {
2447 struct r600_context *rctx = (struct r600_context *)ctx;
2448 struct r600_command_buffer *cb = &shader->command_buffer;
2449 struct r600_shader *rshader = &shader->shader;
2450 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2451 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2452 unsigned tmp, sid, ufi = 0;
2453 int need_linear = 0;
2454 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2455 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2456
2457 if (!cb->buf) {
2458 r600_init_command_buffer(cb, 64);
2459 } else {
2460 cb->num_dw = 0;
2461 }
2462
2463 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2464 for (i = 0; i < rshader->ninput; i++) {
2465 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2466 pos_index = i;
2467 if (rshader->input[i].name == TGSI_SEMANTIC_FACE && face_index == -1)
2468 face_index = i;
2469 if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID)
2470 fixed_pt_position_index = i;
2471
2472 sid = rshader->input[i].spi_sid;
2473
2474 tmp = S_028644_SEMANTIC(sid);
2475
2476 /* D3D 9 behaviour. GL is undefined */
2477 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0)
2478 tmp |= S_028644_DEFAULT_VAL(3);
2479
2480 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2481 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2482 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2483 rctx->rasterizer && rctx->rasterizer->flatshade))
2484 tmp |= S_028644_FLAT_SHADE(1);
2485
2486 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2487 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2488 tmp |= S_028644_PT_SPRITE_TEX(1);
2489 }
2490
2491 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID)
2492 tmp |= S_028644_SEL_CENTROID(1);
2493
2494 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE)
2495 tmp |= S_028644_SEL_SAMPLE(1);
2496
2497 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2498 need_linear = 1;
2499 tmp |= S_028644_SEL_LINEAR(1);
2500 }
2501
2502 r600_store_value(cb, tmp);
2503 }
2504
2505 db_shader_control = 0;
2506 for (i = 0; i < rshader->noutput; i++) {
2507 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2508 z_export = 1;
2509 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2510 stencil_export = 1;
2511 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
2512 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
2513 mask_export = 1;
2514 }
2515 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2516 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2517 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
2518 if (rshader->uses_kill)
2519 db_shader_control |= S_02880C_KILL_ENABLE(1);
2520
2521 exports_ps = 0;
2522 for (i = 0; i < rshader->noutput; i++) {
2523 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2524 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
2525 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2526 exports_ps |= 1;
2527 }
2528 }
2529 num_cout = rshader->nr_ps_color_exports;
2530 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2531 if (!exports_ps) {
2532 /* always at least export 1 component per pixel */
2533 exports_ps = 2;
2534 }
2535
2536 shader->nr_ps_color_outputs = num_cout;
2537
2538 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2539 S_0286CC_PERSP_GRADIENT_ENA(1)|
2540 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2541 spi_input_z = 0;
2542 if (pos_index != -1) {
2543 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2544 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
2545 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2546 S_0286CC_BARYC_SAMPLE_CNTL(1)) |
2547 S_0286CC_POSITION_SAMPLE(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE);
2548 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2549 }
2550
2551 spi_ps_in_control_1 = 0;
2552 if (face_index != -1) {
2553 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2554 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2555 }
2556 if (fixed_pt_position_index != -1) {
2557 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
2558 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
2559 }
2560
2561 /* HW bug in original R600 */
2562 if (rctx->b.family == CHIP_R600)
2563 ufi = 1;
2564
2565 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2566 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2567 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2568
2569 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2570
2571 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2572 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2573 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2574 S_028850_STACK_SIZE(rshader->bc.nstack) |
2575 S_028850_UNCACHED_FIRST_INST(ufi));
2576 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2577
2578 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2579 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2580
2581 /* only set some bits here, the other bits are set in the dsa state */
2582 shader->db_shader_control = db_shader_control;
2583 shader->ps_depth_export = z_export | stencil_export | mask_export;
2584
2585 shader->sprite_coord_enable = sprite_coord_enable;
2586 if (rctx->rasterizer)
2587 shader->flatshade = rctx->rasterizer->flatshade;
2588 }
2589
2590 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2591 {
2592 struct r600_command_buffer *cb = &shader->command_buffer;
2593 struct r600_shader *rshader = &shader->shader;
2594 unsigned spi_vs_out_id[10] = {};
2595 unsigned i, tmp, nparams = 0;
2596
2597 for (i = 0; i < rshader->noutput; i++) {
2598 if (rshader->output[i].spi_sid) {
2599 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2600 spi_vs_out_id[nparams / 4] |= tmp;
2601 nparams++;
2602 }
2603 }
2604
2605 r600_init_command_buffer(cb, 32);
2606
2607 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2608 for (i = 0; i < 10; i++) {
2609 r600_store_value(cb, spi_vs_out_id[i]);
2610 }
2611
2612 /* Certain attributes (position, psize, etc.) don't count as params.
2613 * VS is required to export at least one param and r600_shader_from_tgsi()
2614 * takes care of adding a dummy export.
2615 */
2616 if (nparams < 1)
2617 nparams = 1;
2618
2619 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2620 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2621 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2622 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2623 S_028868_STACK_SIZE(rshader->bc.nstack));
2624 if (rshader->vs_position_window_space) {
2625 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2626 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
2627 } else {
2628 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2629 S_028818_VTX_W0_FMT(1) |
2630 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2631 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2632 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2633
2634 }
2635 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2636 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2637
2638 shader->pa_cl_vs_out_cntl =
2639 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2640 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2641 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2642 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
2643 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
2644 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) |
2645 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport);
2646 }
2647
2648 #define RV610_GSVS_ALIGN 32
2649 #define R600_GSVS_ALIGN 16
2650
2651 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2652 {
2653 struct r600_context *rctx = (struct r600_context *)ctx;
2654 struct r600_command_buffer *cb = &shader->command_buffer;
2655 struct r600_shader *rshader = &shader->shader;
2656 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
2657 unsigned gsvs_itemsize =
2658 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2;
2659
2660 /* some r600s needs gsvs itemsize aligned to cacheline size
2661 this was fixed in rs780 and above. */
2662 switch (rctx->b.family) {
2663 case CHIP_RV610:
2664 gsvs_itemsize = align(gsvs_itemsize, RV610_GSVS_ALIGN);
2665 break;
2666 case CHIP_R600:
2667 case CHIP_RV630:
2668 case CHIP_RV670:
2669 case CHIP_RV620:
2670 case CHIP_RV635:
2671 gsvs_itemsize = align(gsvs_itemsize, R600_GSVS_ALIGN);
2672 break;
2673 default:
2674 break;
2675 }
2676
2677 r600_init_command_buffer(cb, 64);
2678
2679 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2680 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
2681
2682 if (rctx->b.chip_class >= R700) {
2683 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
2684 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
2685 }
2686 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
2687 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
2688
2689 r600_store_context_reg(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE,
2690 cp_shader->ring_item_sizes[0] >> 2);
2691
2692 r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
2693 (rshader->ring_item_sizes[0]) >> 2);
2694
2695 r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE,
2696 gsvs_itemsize);
2697
2698 /* FIXME calculate these values somehow ??? */
2699 r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2);
2700 r600_store_value(cb, 0x80); /* GS_PER_ES */
2701 r600_store_value(cb, 0x100); /* ES_PER_GS */
2702 r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1);
2703 r600_store_value(cb, 0x2); /* GS_PER_VS */
2704
2705 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS,
2706 S_02887C_NUM_GPRS(rshader->bc.ngpr) |
2707 S_02887C_STACK_SIZE(rshader->bc.nstack));
2708 r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, 0);
2709 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2710 }
2711
2712 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2713 {
2714 struct r600_command_buffer *cb = &shader->command_buffer;
2715 struct r600_shader *rshader = &shader->shader;
2716
2717 r600_init_command_buffer(cb, 32);
2718
2719 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
2720 S_028890_NUM_GPRS(rshader->bc.ngpr) |
2721 S_028890_STACK_SIZE(rshader->bc.nstack));
2722 r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, 0);
2723 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2724 }
2725
2726
2727 void *r600_create_resolve_blend(struct r600_context *rctx)
2728 {
2729 struct pipe_blend_state blend;
2730 unsigned i;
2731
2732 memset(&blend, 0, sizeof(blend));
2733 blend.independent_blend_enable = true;
2734 for (i = 0; i < 2; i++) {
2735 blend.rt[i].colormask = 0xf;
2736 blend.rt[i].blend_enable = 1;
2737 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2738 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2739 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2740 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2741 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2742 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2743 }
2744 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2745 }
2746
2747 void *r700_create_resolve_blend(struct r600_context *rctx)
2748 {
2749 struct pipe_blend_state blend;
2750
2751 memset(&blend, 0, sizeof(blend));
2752 blend.independent_blend_enable = true;
2753 blend.rt[0].colormask = 0xf;
2754 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2755 }
2756
2757 void *r600_create_decompress_blend(struct r600_context *rctx)
2758 {
2759 struct pipe_blend_state blend;
2760
2761 memset(&blend, 0, sizeof(blend));
2762 blend.independent_blend_enable = true;
2763 blend.rt[0].colormask = 0xf;
2764 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2765 }
2766
2767 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2768 {
2769 struct pipe_depth_stencil_alpha_state dsa;
2770 boolean quirk = false;
2771
2772 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2773 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2774 quirk = true;
2775
2776 memset(&dsa, 0, sizeof(dsa));
2777
2778 if (quirk) {
2779 dsa.depth.enabled = 1;
2780 dsa.depth.func = PIPE_FUNC_LEQUAL;
2781 dsa.stencil[0].enabled = 1;
2782 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2783 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2784 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2785 dsa.stencil[0].writemask = 0xff;
2786 }
2787
2788 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2789 }
2790
2791 void r600_update_db_shader_control(struct r600_context * rctx)
2792 {
2793 bool dual_export;
2794 unsigned db_shader_control;
2795 uint8_t ps_conservative_z;
2796
2797 if (!rctx->ps_shader) {
2798 return;
2799 }
2800
2801 dual_export = rctx->framebuffer.export_16bpc &&
2802 !rctx->ps_shader->current->ps_depth_export;
2803
2804 db_shader_control = rctx->ps_shader->current->db_shader_control |
2805 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2806
2807 ps_conservative_z = rctx->ps_shader->current->shader.ps_conservative_z;
2808
2809 /* When alpha test is enabled we can't trust the hw to make the proper
2810 * decision on the order in which ztest should be run related to fragment
2811 * shader execution.
2812 *
2813 * If alpha test is enabled perform z test after fragment. RE_Z (early
2814 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2815 */
2816 if (rctx->alphatest_state.sx_alpha_test_control) {
2817 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2818 } else {
2819 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2820 }
2821
2822 if (db_shader_control != rctx->db_misc_state.db_shader_control ||
2823 ps_conservative_z != rctx->db_misc_state.ps_conservative_z) {
2824 rctx->db_misc_state.db_shader_control = db_shader_control;
2825 rctx->db_misc_state.ps_conservative_z = ps_conservative_z;
2826 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
2827 }
2828 }
2829
2830 static inline unsigned r600_array_mode(unsigned mode)
2831 {
2832 switch (mode) {
2833 default:
2834 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
2835 break;
2836 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
2837 break;
2838 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
2839 }
2840 }
2841
2842 static boolean r600_dma_copy_tile(struct r600_context *rctx,
2843 struct pipe_resource *dst,
2844 unsigned dst_level,
2845 unsigned dst_x,
2846 unsigned dst_y,
2847 unsigned dst_z,
2848 struct pipe_resource *src,
2849 unsigned src_level,
2850 unsigned src_x,
2851 unsigned src_y,
2852 unsigned src_z,
2853 unsigned copy_height,
2854 unsigned pitch,
2855 unsigned bpp)
2856 {
2857 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
2858 struct r600_texture *rsrc = (struct r600_texture*)src;
2859 struct r600_texture *rdst = (struct r600_texture*)dst;
2860 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
2861 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
2862 uint64_t base, addr;
2863
2864 dst_mode = rdst->surface.level[dst_level].mode;
2865 src_mode = rsrc->surface.level[src_level].mode;
2866 assert(dst_mode != src_mode);
2867
2868 y = 0;
2869 lbpp = util_logbase2(bpp);
2870 pitch_tile_max = ((pitch / bpp) / 8) - 1;
2871
2872 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
2873 /* T2L */
2874 array_mode = r600_array_mode(src_mode);
2875 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
2876 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2877 /* linear height must be the same as the slice tile max height, it's ok even
2878 * if the linear destination/source have smaller heigh as the size of the
2879 * dma packet will be using the copy_height which is always smaller or equal
2880 * to the linear height
2881 */
2882 height = rsrc->surface.level[src_level].npix_y;
2883 detile = 1;
2884 x = src_x;
2885 y = src_y;
2886 z = src_z;
2887 base = rsrc->surface.level[src_level].offset;
2888 addr = rdst->surface.level[dst_level].offset;
2889 addr += rdst->surface.level[dst_level].slice_size * dst_z;
2890 addr += dst_y * pitch + dst_x * bpp;
2891 } else {
2892 /* L2T */
2893 array_mode = r600_array_mode(dst_mode);
2894 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
2895 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2896 /* linear height must be the same as the slice tile max height, it's ok even
2897 * if the linear destination/source have smaller heigh as the size of the
2898 * dma packet will be using the copy_height which is always smaller or equal
2899 * to the linear height
2900 */
2901 height = rdst->surface.level[dst_level].npix_y;
2902 detile = 0;
2903 x = dst_x;
2904 y = dst_y;
2905 z = dst_z;
2906 base = rdst->surface.level[dst_level].offset;
2907 addr = rsrc->surface.level[src_level].offset;
2908 addr += rsrc->surface.level[src_level].slice_size * src_z;
2909 addr += src_y * pitch + src_x * bpp;
2910 }
2911 /* check that we are in dw/base alignment constraint */
2912 if (addr % 4 || base % 256) {
2913 return FALSE;
2914 }
2915
2916 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2917 * line in the blit. Compute max 8 line we can copy in the size limit
2918 */
2919 cheight = ((R600_DMA_COPY_MAX_SIZE_DW * 4) / pitch) & 0xfffffff8;
2920 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
2921 r600_need_dma_space(&rctx->b, ncopy * 7, &rdst->resource, &rsrc->resource);
2922
2923 for (i = 0; i < ncopy; i++) {
2924 cheight = cheight > copy_height ? copy_height : cheight;
2925 size = (cheight * pitch) / 4;
2926 /* emit reloc before writing cs so that cs is always in consistent state */
2927 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, RADEON_USAGE_READ,
2928 RADEON_PRIO_SDMA_TEXTURE);
2929 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE,
2930 RADEON_PRIO_SDMA_TEXTURE);
2931 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, 1, 0, size));
2932 radeon_emit(cs, base >> 8);
2933 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
2934 (lbpp << 24) | ((height - 1) << 10) |
2935 pitch_tile_max);
2936 radeon_emit(cs, (slice_tile_max << 12) | (z << 0));
2937 radeon_emit(cs, (x << 3) | (y << 17));
2938 radeon_emit(cs, addr & 0xfffffffc);
2939 radeon_emit(cs, (addr >> 32UL) & 0xff);
2940 copy_height -= cheight;
2941 addr += cheight * pitch;
2942 y += cheight;
2943 }
2944 r600_dma_emit_wait_idle(&rctx->b);
2945 return TRUE;
2946 }
2947
2948 static void r600_dma_copy(struct pipe_context *ctx,
2949 struct pipe_resource *dst,
2950 unsigned dst_level,
2951 unsigned dstx, unsigned dsty, unsigned dstz,
2952 struct pipe_resource *src,
2953 unsigned src_level,
2954 const struct pipe_box *src_box)
2955 {
2956 struct r600_context *rctx = (struct r600_context *)ctx;
2957 struct r600_texture *rsrc = (struct r600_texture*)src;
2958 struct r600_texture *rdst = (struct r600_texture*)dst;
2959 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
2960 unsigned src_w, dst_w;
2961 unsigned src_x, src_y;
2962 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
2963
2964 if (rctx->b.dma.cs == NULL) {
2965 goto fallback;
2966 }
2967
2968 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
2969 if (dst_x % 4 || src_box->x % 4 || src_box->width % 4)
2970 goto fallback;
2971
2972 r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
2973 return;
2974 }
2975
2976 if (src_box->depth > 1 ||
2977 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
2978 dstz, rsrc, src_level, src_box))
2979 goto fallback;
2980
2981 src_x = util_format_get_nblocksx(src->format, src_box->x);
2982 dst_x = util_format_get_nblocksx(src->format, dst_x);
2983 src_y = util_format_get_nblocksy(src->format, src_box->y);
2984 dst_y = util_format_get_nblocksy(src->format, dst_y);
2985
2986 bpp = rdst->surface.bpe;
2987 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
2988 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
2989 src_w = rsrc->surface.level[src_level].npix_x;
2990 dst_w = rdst->surface.level[dst_level].npix_x;
2991 copy_height = src_box->height / rsrc->surface.blk_h;
2992
2993 dst_mode = rdst->surface.level[dst_level].mode;
2994 src_mode = rsrc->surface.level[src_level].mode;
2995
2996 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
2997 /* strict requirement on r6xx/r7xx */
2998 goto fallback;
2999 }
3000 /* lot of constraint on alignment this should capture them all */
3001 if (src_pitch % 8 || src_box->y % 8 || dst_y % 8) {
3002 goto fallback;
3003 }
3004
3005 if (src_mode == dst_mode) {
3006 uint64_t dst_offset, src_offset, size;
3007
3008 /* simple dma blit would do NOTE code here assume :
3009 * src_box.x/y == 0
3010 * dst_x/y == 0
3011 * dst_pitch == src_pitch
3012 */
3013 src_offset= rsrc->surface.level[src_level].offset;
3014 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3015 src_offset += src_y * src_pitch + src_x * bpp;
3016 dst_offset = rdst->surface.level[dst_level].offset;
3017 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3018 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3019 size = src_box->height * src_pitch;
3020 /* must be dw aligned */
3021 if (dst_offset % 4 || src_offset % 4 || size % 4) {
3022 goto fallback;
3023 }
3024 r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size);
3025 } else {
3026 if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3027 src, src_level, src_x, src_y, src_box->z,
3028 copy_height, dst_pitch, bpp)) {
3029 goto fallback;
3030 }
3031 }
3032 return;
3033
3034 fallback:
3035 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3036 src, src_level, src_box);
3037 }
3038
3039 void r600_init_state_functions(struct r600_context *rctx)
3040 {
3041 unsigned id = 1;
3042 unsigned i;
3043 /* !!!
3044 * To avoid GPU lockup registers must be emited in a specific order
3045 * (no kidding ...). The order below is important and have been
3046 * partialy infered from analyzing fglrx command stream.
3047 *
3048 * Don't reorder atom without carefully checking the effect (GPU lockup
3049 * or piglit regression).
3050 * !!!
3051 */
3052
3053 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
3054
3055 /* shader const */
3056 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
3057 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
3058 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
3059
3060 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3061 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
3062 */
3063 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
3064 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
3065 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
3066 /* resource */
3067 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
3068 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
3069 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
3070 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
3071
3072 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3073
3074 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3075 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3076 rctx->sample_mask.sample_mask = ~0;
3077
3078 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3079 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3080 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3081 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3082 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3083 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3084 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3085 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3086 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3087 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
3088 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3089 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
3090 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
3091 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3092 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3093 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3094 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3095 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3096 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3097 for (i = 0; i < R600_NUM_HW_STAGES; i++)
3098 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3099 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0);
3100 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0);
3101
3102 rctx->b.b.create_blend_state = r600_create_blend_state;
3103 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3104 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3105 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3106 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3107 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3108 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3109 rctx->b.b.set_min_samples = r600_set_min_samples;
3110 rctx->b.b.get_sample_position = r600_get_sample_position;
3111 rctx->b.dma_copy = r600_dma_copy;
3112 }
3113 /* this function must be last */