2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "util/u_inlines.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "r600_screen.h"
32 #include "r600_context.h"
33 #include "r600_resource.h"
35 #include "r600_state_inlines.h"
37 static void *r600_create_blend_state(struct pipe_context
*ctx
,
38 const struct pipe_blend_state
*state
)
40 struct r600_context
*rctx
= r600_context(ctx
);
42 return r600_context_state(rctx
, pipe_blend_type
, state
);
45 static void *r600_create_dsa_state(struct pipe_context
*ctx
,
46 const struct pipe_depth_stencil_alpha_state
*state
)
48 struct r600_context
*rctx
= r600_context(ctx
);
50 return r600_context_state(rctx
, pipe_dsa_type
, state
);
53 static void *r600_create_rs_state(struct pipe_context
*ctx
,
54 const struct pipe_rasterizer_state
*state
)
56 struct r600_context
*rctx
= r600_context(ctx
);
58 return r600_context_state(rctx
, pipe_rasterizer_type
, state
);
61 static void *r600_create_sampler_state(struct pipe_context
*ctx
,
62 const struct pipe_sampler_state
*state
)
64 struct r600_context
*rctx
= r600_context(ctx
);
66 return r600_context_state(rctx
, pipe_sampler_type
, state
);
69 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
70 struct pipe_sampler_view
*state
)
72 struct r600_context_state
*rstate
= (struct r600_context_state
*)state
;
74 r600_context_state_decref(rstate
);
77 static struct pipe_sampler_view
*r600_create_sampler_view(struct pipe_context
*ctx
,
78 struct pipe_resource
*texture
,
79 const struct pipe_sampler_view
*state
)
81 struct r600_context
*rctx
= r600_context(ctx
);
82 struct r600_context_state
*rstate
;
84 rstate
= r600_context_state(rctx
, pipe_sampler_type
, state
);
85 pipe_reference(NULL
, &texture
->reference
);
86 rstate
->state
.sampler_view
.texture
= texture
;
87 rstate
->state
.sampler_view
.reference
.count
= 1;
88 rstate
->state
.sampler_view
.context
= ctx
;
89 return &rstate
->state
.sampler_view
;
92 static void *r600_create_shader_state(struct pipe_context
*ctx
,
93 const struct pipe_shader_state
*state
)
95 struct r600_context
*rctx
= r600_context(ctx
);
97 return r600_context_state(rctx
, pipe_shader_type
, state
);
100 static void *r600_create_vertex_elements(struct pipe_context
*ctx
,
102 const struct pipe_vertex_element
*elements
)
104 struct r600_vertex_element
*v
= CALLOC_STRUCT(r600_vertex_element
);
108 memcpy(v
->elements
, elements
, count
* sizeof(struct pipe_vertex_element
));
113 static void r600_bind_state(struct pipe_context
*ctx
, void *state
)
115 struct r600_context
*rctx
= r600_context(ctx
);
116 struct r600_context_state
*rstate
= (struct r600_context_state
*)state
;
120 switch (rstate
->type
) {
121 case pipe_rasterizer_type
:
122 rctx
->rasterizer
= r600_context_state_decref(rctx
->rasterizer
);
123 rctx
->rasterizer
= r600_context_state_incref(rstate
);
125 case pipe_poly_stipple_type
:
126 rctx
->poly_stipple
= r600_context_state_decref(rctx
->poly_stipple
);
127 rctx
->poly_stipple
= r600_context_state_incref(rstate
);
129 case pipe_scissor_type
:
130 rctx
->scissor
= r600_context_state_decref(rctx
->scissor
);
131 rctx
->scissor
= r600_context_state_incref(rstate
);
134 rctx
->clip
= r600_context_state_decref(rctx
->clip
);
135 rctx
->clip
= r600_context_state_incref(rstate
);
137 case pipe_depth_type
:
138 rctx
->depth
= r600_context_state_decref(rctx
->depth
);
139 rctx
->depth
= r600_context_state_incref(rstate
);
141 case pipe_stencil_type
:
142 rctx
->stencil
= r600_context_state_decref(rctx
->stencil
);
143 rctx
->stencil
= r600_context_state_incref(rstate
);
145 case pipe_alpha_type
:
146 rctx
->alpha
= r600_context_state_decref(rctx
->alpha
);
147 rctx
->alpha
= r600_context_state_incref(rstate
);
150 rctx
->dsa
= r600_context_state_decref(rctx
->dsa
);
151 rctx
->dsa
= r600_context_state_incref(rstate
);
153 case pipe_blend_type
:
154 rctx
->blend
= r600_context_state_decref(rctx
->blend
);
155 rctx
->blend
= r600_context_state_incref(rstate
);
157 case pipe_framebuffer_type
:
158 rctx
->framebuffer
= r600_context_state_decref(rctx
->framebuffer
);
159 rctx
->framebuffer
= r600_context_state_incref(rstate
);
161 case pipe_stencil_ref_type
:
162 rctx
->stencil_ref
= r600_context_state_decref(rctx
->stencil_ref
);
163 rctx
->stencil_ref
= r600_context_state_incref(rstate
);
165 case pipe_viewport_type
:
166 rctx
->viewport
= r600_context_state_decref(rctx
->viewport
);
167 rctx
->viewport
= r600_context_state_incref(rstate
);
169 case pipe_shader_type
:
170 case pipe_sampler_type
:
171 case pipe_sampler_view_type
:
173 R600_ERR("invalid type %d\n", rstate
->type
);
178 static void r600_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
180 struct r600_context
*rctx
= r600_context(ctx
);
181 struct r600_context_state
*rstate
= (struct r600_context_state
*)state
;
183 rctx
->ps_shader
= r600_context_state_decref(rctx
->ps_shader
);
184 rctx
->ps_shader
= r600_context_state_incref(rstate
);
187 static void r600_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
189 struct r600_context
*rctx
= r600_context(ctx
);
190 struct r600_context_state
*rstate
= (struct r600_context_state
*)state
;
192 rctx
->vs_shader
= r600_context_state_decref(rctx
->vs_shader
);
193 rctx
->vs_shader
= r600_context_state_incref(rstate
);
196 static void r600_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
198 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
207 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
209 struct r600_context
*rctx
= r600_context(ctx
);
210 struct r600_vertex_element
*v
= (struct r600_vertex_element
*)state
;
212 r600_delete_vertex_element(ctx
, rctx
->vertex_elements
);
213 rctx
->vertex_elements
= v
;
219 static void r600_bind_ps_sampler(struct pipe_context
*ctx
,
220 unsigned count
, void **states
)
222 struct r600_context
*rctx
= r600_context(ctx
);
223 struct r600_context_state
*rstate
;
226 for (i
= 0; i
< rctx
->ps_nsampler
; i
++) {
227 rctx
->ps_sampler
[i
] = r600_context_state_decref(rctx
->ps_sampler
[i
]);
229 for (i
= 0; i
< count
; i
++) {
230 rstate
= (struct r600_context_state
*)states
[i
];
231 rctx
->ps_sampler
[i
] = r600_context_state_incref(rstate
);
233 rctx
->ps_nsampler
= count
;
236 static void r600_bind_vs_sampler(struct pipe_context
*ctx
,
237 unsigned count
, void **states
)
239 struct r600_context
*rctx
= r600_context(ctx
);
240 struct r600_context_state
*rstate
;
243 for (i
= 0; i
< rctx
->vs_nsampler
; i
++) {
244 rctx
->vs_sampler
[i
] = r600_context_state_decref(rctx
->vs_sampler
[i
]);
246 for (i
= 0; i
< count
; i
++) {
247 rstate
= (struct r600_context_state
*)states
[i
];
248 rctx
->vs_sampler
[i
] = r600_context_state_incref(rstate
);
250 rctx
->vs_nsampler
= count
;
253 static void r600_delete_state(struct pipe_context
*ctx
, void *state
)
255 struct r600_context_state
*rstate
= (struct r600_context_state
*)state
;
257 r600_context_state_decref(rstate
);
260 static void r600_set_blend_color(struct pipe_context
*ctx
,
261 const struct pipe_blend_color
*color
)
263 struct r600_context
*rctx
= r600_context(ctx
);
265 rctx
->blend_color
= *color
;
268 static void r600_set_clip_state(struct pipe_context
*ctx
,
269 const struct pipe_clip_state
*state
)
271 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
272 struct r600_context
*rctx
= r600_context(ctx
);
273 struct r600_context_state
*rstate
;
275 rstate
= r600_context_state(rctx
, pipe_clip_type
, state
);
276 r600_bind_state(ctx
, rstate
);
277 /* refcount is taken care of this */
278 r600_delete_state(ctx
, rstate
);
281 static void r600_set_constant_buffer(struct pipe_context
*ctx
,
282 uint shader
, uint index
,
283 struct pipe_resource
*buffer
)
285 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
286 struct r600_context
*rctx
= r600_context(ctx
);
287 unsigned nconstant
= 0, i
, type
, id
;
288 struct radeon_state
*rstate
;
289 struct pipe_transfer
*transfer
;
293 case PIPE_SHADER_VERTEX
:
294 id
= R600_VS_CONSTANT
;
295 type
= R600_VS_CONSTANT_TYPE
;
297 case PIPE_SHADER_FRAGMENT
:
298 id
= R600_PS_CONSTANT
;
299 type
= R600_PS_CONSTANT_TYPE
;
302 R600_ERR("unsupported %d\n", shader
);
305 if (buffer
&& buffer
->width0
> 0) {
306 nconstant
= buffer
->width0
/ 16;
307 ptr
= pipe_buffer_map(ctx
, buffer
, PIPE_TRANSFER_READ
, &transfer
);
310 for (i
= 0; i
< nconstant
; i
++) {
311 rstate
= radeon_state(rscreen
->rw
, type
, id
+ i
);
314 rstate
->states
[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0
] = ptr
[i
* 4 + 0];
315 rstate
->states
[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0
] = ptr
[i
* 4 + 1];
316 rstate
->states
[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0
] = ptr
[i
* 4 + 2];
317 rstate
->states
[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0
] = ptr
[i
* 4 + 3];
318 if (radeon_state_pm4(rstate
))
320 if (radeon_draw_set_new(rctx
->draw
, rstate
))
323 pipe_buffer_unmap(ctx
, buffer
, transfer
);
327 static void r600_set_ps_sampler_view(struct pipe_context
*ctx
,
329 struct pipe_sampler_view
**views
)
331 struct r600_context
*rctx
= r600_context(ctx
);
332 struct r600_context_state
*rstate
;
335 for (i
= 0; i
< rctx
->ps_nsampler_view
; i
++) {
336 rctx
->ps_sampler_view
[i
] = r600_context_state_decref(rctx
->ps_sampler_view
[i
]);
338 for (i
= 0; i
< count
; i
++) {
339 rstate
= (struct r600_context_state
*)views
[i
];
340 rctx
->ps_sampler_view
[i
] = r600_context_state_incref(rstate
);
342 rctx
->ps_nsampler_view
= count
;
345 static void r600_set_vs_sampler_view(struct pipe_context
*ctx
,
347 struct pipe_sampler_view
**views
)
349 struct r600_context
*rctx
= r600_context(ctx
);
350 struct r600_context_state
*rstate
;
353 for (i
= 0; i
< rctx
->vs_nsampler_view
; i
++) {
354 rctx
->vs_sampler_view
[i
] = r600_context_state_decref(rctx
->vs_sampler_view
[i
]);
356 for (i
= 0; i
< count
; i
++) {
357 rstate
= (struct r600_context_state
*)views
[i
];
358 rctx
->vs_sampler_view
[i
] = r600_context_state_incref(rstate
);
360 rctx
->vs_nsampler_view
= count
;
363 static void r600_set_framebuffer_state(struct pipe_context
*ctx
,
364 const struct pipe_framebuffer_state
*state
)
366 struct r600_context
*rctx
= r600_context(ctx
);
367 struct r600_context_state
*rstate
;
369 rstate
= r600_context_state(rctx
, pipe_framebuffer_type
, state
);
370 r600_bind_state(ctx
, rstate
);
373 static void r600_set_polygon_stipple(struct pipe_context
*ctx
,
374 const struct pipe_poly_stipple
*state
)
378 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
382 static void r600_set_scissor_state(struct pipe_context
*ctx
,
383 const struct pipe_scissor_state
*state
)
385 struct r600_context
*rctx
= r600_context(ctx
);
386 struct r600_context_state
*rstate
;
388 rstate
= r600_context_state(rctx
, pipe_scissor_type
, state
);
389 r600_bind_state(ctx
, rstate
);
390 /* refcount is taken care of this */
391 r600_delete_state(ctx
, rstate
);
394 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
395 const struct pipe_stencil_ref
*state
)
397 struct r600_context
*rctx
= r600_context(ctx
);
398 struct r600_context_state
*rstate
;
400 rstate
= r600_context_state(rctx
, pipe_stencil_ref_type
, state
);
401 r600_bind_state(ctx
, rstate
);
402 /* refcount is taken care of this */
403 r600_delete_state(ctx
, rstate
);
406 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
408 const struct pipe_vertex_buffer
*buffers
)
410 struct r600_context
*rctx
= r600_context(ctx
);
413 for (i
= 0; i
< rctx
->nvertex_buffer
; i
++) {
414 pipe_resource_reference(&rctx
->vertex_buffer
[i
].buffer
, NULL
);
416 memcpy(rctx
->vertex_buffer
, buffers
, sizeof(struct pipe_vertex_buffer
) * count
);
417 for (i
= 0; i
< count
; i
++) {
418 rctx
->vertex_buffer
[i
].buffer
= NULL
;
419 pipe_resource_reference(&rctx
->vertex_buffer
[i
].buffer
, buffers
[i
].buffer
);
421 rctx
->nvertex_buffer
= count
;
424 static void r600_set_index_buffer(struct pipe_context
*ctx
,
425 const struct pipe_index_buffer
*ib
)
427 struct r600_context
*rctx
= r600_context(ctx
);
430 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
431 memcpy(&rctx
->index_buffer
, ib
, sizeof(rctx
->index_buffer
));
433 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
434 memset(&rctx
->index_buffer
, 0, sizeof(rctx
->index_buffer
));
437 /* TODO make this more like a state */
440 static void r600_set_viewport_state(struct pipe_context
*ctx
,
441 const struct pipe_viewport_state
*state
)
443 struct r600_context
*rctx
= r600_context(ctx
);
444 struct r600_context_state
*rstate
;
446 rstate
= r600_context_state(rctx
, pipe_viewport_type
, state
);
447 r600_bind_state(ctx
, rstate
);
448 r600_delete_state(ctx
, rstate
);
451 void r600_init_state_functions(struct r600_context
*rctx
)
453 rctx
->context
.create_blend_state
= r600_create_blend_state
;
454 rctx
->context
.create_depth_stencil_alpha_state
= r600_create_dsa_state
;
455 rctx
->context
.create_fs_state
= r600_create_shader_state
;
456 rctx
->context
.create_rasterizer_state
= r600_create_rs_state
;
457 rctx
->context
.create_sampler_state
= r600_create_sampler_state
;
458 rctx
->context
.create_sampler_view
= r600_create_sampler_view
;
459 rctx
->context
.create_vertex_elements_state
= r600_create_vertex_elements
;
460 rctx
->context
.create_vs_state
= r600_create_shader_state
;
461 rctx
->context
.bind_blend_state
= r600_bind_state
;
462 rctx
->context
.bind_depth_stencil_alpha_state
= r600_bind_state
;
463 rctx
->context
.bind_fragment_sampler_states
= r600_bind_ps_sampler
;
464 rctx
->context
.bind_fs_state
= r600_bind_ps_shader
;
465 rctx
->context
.bind_rasterizer_state
= r600_bind_state
;
466 rctx
->context
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
467 rctx
->context
.bind_vertex_sampler_states
= r600_bind_vs_sampler
;
468 rctx
->context
.bind_vs_state
= r600_bind_vs_shader
;
469 rctx
->context
.delete_blend_state
= r600_delete_state
;
470 rctx
->context
.delete_depth_stencil_alpha_state
= r600_delete_state
;
471 rctx
->context
.delete_fs_state
= r600_delete_state
;
472 rctx
->context
.delete_rasterizer_state
= r600_delete_state
;
473 rctx
->context
.delete_sampler_state
= r600_delete_state
;
474 rctx
->context
.delete_vertex_elements_state
= r600_delete_vertex_element
;
475 rctx
->context
.delete_vs_state
= r600_delete_state
;
476 rctx
->context
.set_blend_color
= r600_set_blend_color
;
477 rctx
->context
.set_clip_state
= r600_set_clip_state
;
478 rctx
->context
.set_constant_buffer
= r600_set_constant_buffer
;
479 rctx
->context
.set_fragment_sampler_views
= r600_set_ps_sampler_view
;
480 rctx
->context
.set_framebuffer_state
= r600_set_framebuffer_state
;
481 rctx
->context
.set_polygon_stipple
= r600_set_polygon_stipple
;
482 rctx
->context
.set_sample_mask
= r600_set_sample_mask
;
483 rctx
->context
.set_scissor_state
= r600_set_scissor_state
;
484 rctx
->context
.set_stencil_ref
= r600_set_stencil_ref
;
485 rctx
->context
.set_vertex_buffers
= r600_set_vertex_buffers
;
486 rctx
->context
.set_index_buffer
= r600_set_index_buffer
;
487 rctx
->context
.set_vertex_sampler_views
= r600_set_vs_sampler_view
;
488 rctx
->context
.set_viewport_state
= r600_set_viewport_state
;
489 rctx
->context
.sampler_view_destroy
= r600_sampler_view_destroy
;
492 struct r600_context_state
*r600_context_state_incref(struct r600_context_state
*rstate
)
500 struct r600_context_state
*r600_context_state_decref(struct r600_context_state
*rstate
)
506 if (--rstate
->refcount
)
508 switch (rstate
->type
) {
509 case pipe_sampler_view_type
:
510 pipe_resource_reference(&rstate
->state
.sampler_view
.texture
, NULL
);
512 case pipe_framebuffer_type
:
513 for (i
= 0; i
< rstate
->state
.framebuffer
.nr_cbufs
; i
++) {
514 pipe_surface_reference(&rstate
->state
.framebuffer
.cbufs
[i
], NULL
);
516 pipe_surface_reference(&rstate
->state
.framebuffer
.zsbuf
, NULL
);
518 case pipe_viewport_type
:
519 case pipe_depth_type
:
520 case pipe_rasterizer_type
:
521 case pipe_poly_stipple_type
:
522 case pipe_scissor_type
:
524 case pipe_stencil_type
:
525 case pipe_alpha_type
:
527 case pipe_blend_type
:
528 case pipe_stencil_ref_type
:
529 case pipe_shader_type
:
530 case pipe_sampler_type
:
533 R600_ERR("invalid type %d\n", rstate
->type
);
536 radeon_state_decref(rstate
->rstate
);
541 struct r600_context_state
*r600_context_state(struct r600_context
*rctx
, unsigned type
, const void *state
)
543 struct r600_context_state
*rstate
= CALLOC_STRUCT(r600_context_state
);
544 const union pipe_states
*states
= state
;
551 rstate
->refcount
= 1;
553 switch (rstate
->type
) {
554 case pipe_sampler_view_type
:
555 rstate
->state
.sampler_view
= (*states
).sampler_view
;
556 rstate
->state
.sampler_view
.texture
= NULL
;
558 case pipe_framebuffer_type
:
559 rstate
->state
.framebuffer
= (*states
).framebuffer
;
560 for (i
= 0; i
< rstate
->state
.framebuffer
.nr_cbufs
; i
++) {
561 pipe_surface_reference(&rstate
->state
.framebuffer
.cbufs
[i
],
562 (*states
).framebuffer
.cbufs
[i
]);
564 pipe_surface_reference(&rstate
->state
.framebuffer
.zsbuf
,
565 (*states
).framebuffer
.zsbuf
);
567 case pipe_viewport_type
:
568 rstate
->state
.viewport
= (*states
).viewport
;
570 case pipe_depth_type
:
571 rstate
->state
.depth
= (*states
).depth
;
573 case pipe_rasterizer_type
:
574 rstate
->state
.rasterizer
= (*states
).rasterizer
;
576 case pipe_poly_stipple_type
:
577 rstate
->state
.poly_stipple
= (*states
).poly_stipple
;
579 case pipe_scissor_type
:
580 rstate
->state
.scissor
= (*states
).scissor
;
583 rstate
->state
.clip
= (*states
).clip
;
585 case pipe_stencil_type
:
586 rstate
->state
.stencil
= (*states
).stencil
;
588 case pipe_alpha_type
:
589 rstate
->state
.alpha
= (*states
).alpha
;
592 rstate
->state
.dsa
= (*states
).dsa
;
594 case pipe_blend_type
:
595 rstate
->state
.blend
= (*states
).blend
;
597 case pipe_stencil_ref_type
:
598 rstate
->state
.stencil_ref
= (*states
).stencil_ref
;
600 case pipe_shader_type
:
601 rstate
->state
.shader
= (*states
).shader
;
602 r
= r600_pipe_shader_create(&rctx
->context
, rstate
, rstate
->state
.shader
.tokens
);
604 r600_context_state_decref(rstate
);
608 case pipe_sampler_type
:
609 rstate
->state
.sampler
= (*states
).sampler
;
612 R600_ERR("invalid type %d\n", rstate
->type
);
619 static struct radeon_state
*r600_blend(struct r600_context
*rctx
)
621 struct r600_screen
*rscreen
= rctx
->screen
;
622 struct radeon_state
*rstate
;
623 const struct pipe_blend_state
*state
= &rctx
->blend
->state
.blend
;
626 rstate
= radeon_state(rscreen
->rw
, R600_BLEND_TYPE
, R600_BLEND
);
629 rstate
->states
[R600_BLEND__CB_BLEND_RED
] = fui(rctx
->blend_color
.color
[0]);
630 rstate
->states
[R600_BLEND__CB_BLEND_GREEN
] = fui(rctx
->blend_color
.color
[1]);
631 rstate
->states
[R600_BLEND__CB_BLEND_BLUE
] = fui(rctx
->blend_color
.color
[2]);
632 rstate
->states
[R600_BLEND__CB_BLEND_ALPHA
] = fui(rctx
->blend_color
.color
[3]);
633 rstate
->states
[R600_BLEND__CB_BLEND0_CONTROL
] = 0x00000000;
634 rstate
->states
[R600_BLEND__CB_BLEND1_CONTROL
] = 0x00000000;
635 rstate
->states
[R600_BLEND__CB_BLEND2_CONTROL
] = 0x00000000;
636 rstate
->states
[R600_BLEND__CB_BLEND3_CONTROL
] = 0x00000000;
637 rstate
->states
[R600_BLEND__CB_BLEND4_CONTROL
] = 0x00000000;
638 rstate
->states
[R600_BLEND__CB_BLEND5_CONTROL
] = 0x00000000;
639 rstate
->states
[R600_BLEND__CB_BLEND6_CONTROL
] = 0x00000000;
640 rstate
->states
[R600_BLEND__CB_BLEND7_CONTROL
] = 0x00000000;
641 rstate
->states
[R600_BLEND__CB_BLEND_CONTROL
] = 0x00000000;
643 for (i
= 0; i
< 8; i
++) {
644 unsigned eqRGB
= state
->rt
[i
].rgb_func
;
645 unsigned srcRGB
= state
->rt
[i
].rgb_src_factor
;
646 unsigned dstRGB
= state
->rt
[i
].rgb_dst_factor
;
648 unsigned eqA
= state
->rt
[i
].alpha_func
;
649 unsigned srcA
= state
->rt
[i
].alpha_src_factor
;
650 unsigned dstA
= state
->rt
[i
].alpha_dst_factor
;
653 if (!state
->rt
[i
].blend_enable
)
656 bc
|= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
657 bc
|= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
658 bc
|= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
660 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
661 bc
|= S_028804_SEPARATE_ALPHA_BLEND(1);
662 bc
|= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
663 bc
|= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
664 bc
|= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
667 rstate
->states
[R600_BLEND__CB_BLEND0_CONTROL
+ i
] = bc
;
669 rstate
->states
[R600_BLEND__CB_BLEND_CONTROL
] = bc
;
672 if (radeon_state_pm4(rstate
)) {
673 radeon_state_decref(rstate
);
679 static struct radeon_state
*r600_ucp(struct r600_context
*rctx
, int clip
)
681 struct r600_screen
*rscreen
= rctx
->screen
;
682 struct radeon_state
*rstate
;
683 const struct pipe_clip_state
*state
= &rctx
->clip
->state
.clip
;
685 rstate
= radeon_state(rscreen
->rw
, R600_CLIP_TYPE
, R600_CLIP
+ clip
);
689 rstate
->states
[R600_CLIP__PA_CL_UCP_X_0
] = fui(state
->ucp
[clip
][0]);
690 rstate
->states
[R600_CLIP__PA_CL_UCP_Y_0
] = fui(state
->ucp
[clip
][1]);
691 rstate
->states
[R600_CLIP__PA_CL_UCP_Z_0
] = fui(state
->ucp
[clip
][2]);
692 rstate
->states
[R600_CLIP__PA_CL_UCP_W_0
] = fui(state
->ucp
[clip
][3]);
694 if (radeon_state_pm4(rstate
)) {
695 radeon_state_decref(rstate
);
702 static struct radeon_state
*r600_cb(struct r600_context
*rctx
, int cb
)
704 struct r600_screen
*rscreen
= rctx
->screen
;
705 struct r600_resource_texture
*rtex
;
706 struct r600_resource
*rbuffer
;
707 struct radeon_state
*rstate
;
708 const struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
->state
.framebuffer
;
709 unsigned level
= state
->cbufs
[cb
]->level
;
710 unsigned pitch
, slice
;
712 unsigned format
, swap
, ntype
;
713 const struct util_format_description
*desc
;
715 rstate
= radeon_state(rscreen
->rw
, R600_CB0_TYPE
+ cb
, R600_CB0
+ cb
);
718 rtex
= (struct r600_resource_texture
*)state
->cbufs
[cb
]->texture
;
719 rbuffer
= &rtex
->resource
;
720 rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
721 rstate
->bo
[1] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
722 rstate
->bo
[2] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
723 rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
724 rstate
->placement
[2] = RADEON_GEM_DOMAIN_GTT
;
725 rstate
->placement
[4] = RADEON_GEM_DOMAIN_GTT
;
727 pitch
= (rtex
->pitch
[level
] / rtex
->bpt
) / 8 - 1;
728 slice
= (rtex
->pitch
[level
] / rtex
->bpt
) * state
->cbufs
[cb
]->height
/ 64 - 1;
731 desc
= util_format_description(rtex
->resource
.base
.b
.format
);
732 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
733 ntype
= V_0280A0_NUMBER_SRGB
;
735 format
= r600_translate_colorformat(rtex
->resource
.base
.b
.format
);
736 swap
= r600_translate_colorswap(rtex
->resource
.base
.b
.format
);
738 color_info
= S_0280A0_FORMAT(format
) |
739 S_0280A0_COMP_SWAP(swap
) |
740 S_0280A0_BLEND_CLAMP(1) |
741 S_0280A0_SOURCE_FORMAT(1) |
742 S_0280A0_NUMBER_TYPE(ntype
);
744 rstate
->states
[R600_CB0__CB_COLOR0_BASE
] = rtex
->offset
[level
] >> 8;
745 rstate
->states
[R600_CB0__CB_COLOR0_INFO
] = color_info
;
746 rstate
->states
[R600_CB0__CB_COLOR0_SIZE
] = S_028060_PITCH_TILE_MAX(pitch
) |
747 S_028060_SLICE_TILE_MAX(slice
);
748 rstate
->states
[R600_CB0__CB_COLOR0_VIEW
] = 0x00000000;
749 rstate
->states
[R600_CB0__CB_COLOR0_FRAG
] = 0x00000000;
750 rstate
->states
[R600_CB0__CB_COLOR0_TILE
] = 0x00000000;
751 rstate
->states
[R600_CB0__CB_COLOR0_MASK
] = 0x00000000;
752 if (radeon_state_pm4(rstate
)) {
753 radeon_state_decref(rstate
);
759 static struct radeon_state
*r600_db(struct r600_context
*rctx
)
761 struct r600_screen
*rscreen
= rctx
->screen
;
762 struct r600_resource_texture
*rtex
;
763 struct r600_resource
*rbuffer
;
764 struct radeon_state
*rstate
;
765 const struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
->state
.framebuffer
;
767 unsigned pitch
, slice
, format
;
769 if (state
->zsbuf
== NULL
)
772 rstate
= radeon_state(rscreen
->rw
, R600_DB_TYPE
, R600_DB
);
776 rtex
= (struct r600_resource_texture
*)state
->zsbuf
->texture
;
777 rbuffer
= &rtex
->resource
;
778 rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
780 rstate
->placement
[0] = RADEON_GEM_DOMAIN_VRAM
;
781 level
= state
->zsbuf
->level
;
782 pitch
= (rtex
->pitch
[level
] / rtex
->bpt
) / 8 - 1;
783 slice
= (rtex
->pitch
[level
] / rtex
->bpt
) * state
->zsbuf
->height
/ 64 - 1;
784 format
= r600_translate_dbformat(state
->zsbuf
->texture
->format
);
785 rstate
->states
[R600_DB__DB_DEPTH_BASE
] = rtex
->offset
[level
] >> 8;
786 rstate
->states
[R600_DB__DB_DEPTH_INFO
] = 0x00010000 |
787 S_028010_FORMAT(format
);
788 rstate
->states
[R600_DB__DB_DEPTH_VIEW
] = 0x00000000;
789 rstate
->states
[R600_DB__DB_PREFETCH_LIMIT
] = (state
->zsbuf
->height
/ 8) -1;
790 rstate
->states
[R600_DB__DB_DEPTH_SIZE
] = S_028000_PITCH_TILE_MAX(pitch
) |
791 S_028000_SLICE_TILE_MAX(slice
);
792 if (radeon_state_pm4(rstate
)) {
793 radeon_state_decref(rstate
);
799 static struct radeon_state
*r600_rasterizer(struct r600_context
*rctx
)
801 const struct pipe_rasterizer_state
*state
= &rctx
->rasterizer
->state
.rasterizer
;
802 const struct pipe_framebuffer_state
*fb
= &rctx
->framebuffer
->state
.framebuffer
;
803 const struct pipe_clip_state
*clip
= NULL
;
804 struct r600_screen
*rscreen
= rctx
->screen
;
805 struct radeon_state
*rstate
;
806 float offset_units
= 0, offset_scale
= 0;
808 unsigned offset_db_fmt_cntl
= 0;
810 unsigned prov_vtx
= 1;
813 clip
= &rctx
->clip
->state
.clip
;
815 offset_units
= state
->offset_units
;
816 offset_scale
= state
->offset_scale
* 12.0f
;
817 switch (fb
->zsbuf
->texture
->format
) {
818 case PIPE_FORMAT_Z24X8_UNORM
:
819 case PIPE_FORMAT_Z24_UNORM_S8_USCALED
:
821 offset_units
*= 2.0f
;
823 case PIPE_FORMAT_Z32_FLOAT
:
825 offset_units
*= 1.0f
;
826 offset_db_fmt_cntl
|= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
828 case PIPE_FORMAT_Z16_UNORM
:
830 offset_units
*= 4.0f
;
833 R600_ERR("unsupported %d\n", fb
->zsbuf
->texture
->format
);
837 offset_db_fmt_cntl
|= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
839 if (state
->flatshade_first
)
842 rctx
->flat_shade
= state
->flatshade
;
843 rstate
= radeon_state(rscreen
->rw
, R600_RASTERIZER_TYPE
, R600_RASTERIZER
);
846 rstate
->states
[R600_RASTERIZER__SPI_INTERP_CONTROL_0
] = 0x00000001;
847 if (state
->sprite_coord_enable
) {
848 rstate
->states
[R600_RASTERIZER__SPI_INTERP_CONTROL_0
] |=
849 S_0286D4_PNT_SPRITE_ENA(1) |
850 S_0286D4_PNT_SPRITE_OVRD_X(2) |
851 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
852 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
853 S_0286D4_PNT_SPRITE_OVRD_W(1);
854 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
855 rstate
->states
[R600_RASTERIZER__SPI_INTERP_CONTROL_0
] |=
856 S_0286D4_PNT_SPRITE_TOP_1(1);
859 rstate
->states
[R600_RASTERIZER__PA_CL_CLIP_CNTL
] = 0;
860 if (clip
&& clip
->nr
) {
861 rstate
->states
[R600_RASTERIZER__PA_CL_CLIP_CNTL
] = S_028810_PS_UCP_MODE(3) | ((1 << clip
->nr
) - 1);
862 rstate
->states
[R600_RASTERIZER__PA_CL_CLIP_CNTL
] |= S_028810_CLIP_DISABLE(clip
->depth_clamp
);
864 rstate
->states
[R600_RASTERIZER__PA_SU_SC_MODE_CNTL
] =
865 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
866 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
867 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
868 S_028814_FACE(!state
->front_ccw
) |
869 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
870 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
871 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
);
872 rstate
->states
[R600_RASTERIZER__PA_CL_VS_OUT_CNTL
] =
873 S_02881C_USE_VTX_POINT_SIZE(state
->point_size_per_vertex
) |
874 S_02881C_VS_OUT_MISC_VEC_ENA(state
->point_size_per_vertex
);
875 rstate
->states
[R600_RASTERIZER__PA_CL_NANINF_CNTL
] = 0x00000000;
876 /* point size 12.4 fixed point */
877 tmp
= (unsigned)(state
->point_size
* 8.0);
878 rstate
->states
[R600_RASTERIZER__PA_SU_POINT_SIZE
] = S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
);
879 rstate
->states
[R600_RASTERIZER__PA_SU_POINT_MINMAX
] = 0x80000000;
880 rstate
->states
[R600_RASTERIZER__PA_SU_LINE_CNTL
] = 0x00000008;
881 rstate
->states
[R600_RASTERIZER__PA_SC_LINE_STIPPLE
] = 0x00000005;
882 rstate
->states
[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL
] = 0x00000000;
883 rstate
->states
[R600_RASTERIZER__PA_SC_LINE_CNTL
] = 0x00000400;
884 rstate
->states
[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ
] = 0x3F800000;
885 rstate
->states
[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ
] = 0x3F800000;
886 rstate
->states
[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ
] = 0x3F800000;
887 rstate
->states
[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ
] = 0x3F800000;
888 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL
] = offset_db_fmt_cntl
;
889 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP
] = 0x00000000;
890 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE
] = fui(offset_scale
);
891 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET
] = fui(offset_units
);
892 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE
] = fui(offset_scale
);
893 rstate
->states
[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET
] = fui(offset_units
);
894 if (radeon_state_pm4(rstate
)) {
895 radeon_state_decref(rstate
);
901 static struct radeon_state
*r600_scissor(struct r600_context
*rctx
)
903 const struct pipe_scissor_state
*state
= &rctx
->scissor
->state
.scissor
;
904 const struct pipe_framebuffer_state
*fb
= &rctx
->framebuffer
->state
.framebuffer
;
905 struct r600_screen
*rscreen
= rctx
->screen
;
906 struct radeon_state
*rstate
;
907 unsigned minx
, maxx
, miny
, maxy
;
913 maxx
= fb
->cbufs
[0]->width
;
914 maxy
= fb
->cbufs
[0]->height
;
921 tl
= S_028240_TL_X(minx
) | S_028240_TL_Y(miny
) | S_028240_WINDOW_OFFSET_DISABLE(1);
922 br
= S_028244_BR_X(maxx
) | S_028244_BR_Y(maxy
);
923 rstate
= radeon_state(rscreen
->rw
, R600_SCISSOR_TYPE
, R600_SCISSOR
);
926 rstate
->states
[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL
] = tl
;
927 rstate
->states
[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR
] = br
;
928 rstate
->states
[R600_SCISSOR__PA_SC_WINDOW_OFFSET
] = 0x00000000;
929 rstate
->states
[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL
] = tl
;
930 rstate
->states
[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR
] = br
;
931 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_RULE
] = 0x0000FFFF;
932 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_0_TL
] = tl
;
933 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_0_BR
] = br
;
934 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_1_TL
] = tl
;
935 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_1_BR
] = br
;
936 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_2_TL
] = tl
;
937 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_2_BR
] = br
;
938 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_3_TL
] = tl
;
939 rstate
->states
[R600_SCISSOR__PA_SC_CLIPRECT_3_BR
] = br
;
940 rstate
->states
[R600_SCISSOR__PA_SC_EDGERULE
] = 0xAAAAAAAA;
941 rstate
->states
[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL
] = tl
;
942 rstate
->states
[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR
] = br
;
943 rstate
->states
[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL
] = tl
;
944 rstate
->states
[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR
] = br
;
945 if (radeon_state_pm4(rstate
)) {
946 radeon_state_decref(rstate
);
952 static struct radeon_state
*r600_viewport(struct r600_context
*rctx
)
954 const struct pipe_viewport_state
*state
= &rctx
->viewport
->state
.viewport
;
955 struct r600_screen
*rscreen
= rctx
->screen
;
956 struct radeon_state
*rstate
;
958 rstate
= radeon_state(rscreen
->rw
, R600_VIEWPORT_TYPE
, R600_VIEWPORT
);
961 rstate
->states
[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0
] = 0x00000000;
962 rstate
->states
[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0
] = 0x3F800000;
963 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0
] = fui(state
->scale
[0]);
964 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0
] = fui(state
->scale
[1]);
965 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0
] = fui(state
->scale
[2]);
966 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0
] = fui(state
->translate
[0]);
967 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0
] = fui(state
->translate
[1]);
968 rstate
->states
[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0
] = fui(state
->translate
[2]);
969 rstate
->states
[R600_VIEWPORT__PA_CL_VTE_CNTL
] = 0x0000043F;
970 if (radeon_state_pm4(rstate
)) {
971 radeon_state_decref(rstate
);
977 static struct radeon_state
*r600_dsa(struct r600_context
*rctx
)
979 const struct pipe_depth_stencil_alpha_state
*state
= &rctx
->dsa
->state
.dsa
;
980 const struct pipe_stencil_ref
*stencil_ref
= &rctx
->stencil_ref
->state
.stencil_ref
;
981 struct r600_screen
*rscreen
= rctx
->screen
;
982 unsigned db_depth_control
, alpha_test_control
, alpha_ref
, db_shader_control
;
983 unsigned stencil_ref_mask
, stencil_ref_mask_bf
;
984 struct r600_shader
*rshader
= &rctx
->ps_shader
->shader
;
985 struct radeon_state
*rstate
;
988 rstate
= radeon_state(rscreen
->rw
, R600_DSA_TYPE
, R600_DSA
);
992 db_shader_control
= 0x210;
993 for (i
= 0; i
< rshader
->noutput
; i
++) {
994 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
995 db_shader_control
|= 1;
997 stencil_ref_mask
= 0;
998 stencil_ref_mask_bf
= 0;
999 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1000 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1001 S_028800_ZFUNC(state
->depth
.func
);
1002 /* set stencil enable */
1004 if (state
->stencil
[0].enabled
) {
1005 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1006 db_depth_control
|= S_028800_STENCILFUNC(r600_translate_ds_func(state
->stencil
[0].func
));
1007 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
1008 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
1009 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
1011 stencil_ref_mask
= S_028430_STENCILMASK(state
->stencil
[0].valuemask
) |
1012 S_028430_STENCILWRITEMASK(state
->stencil
[0].writemask
);
1013 stencil_ref_mask
|= S_028430_STENCILREF(stencil_ref
->ref_value
[0]);
1014 if (state
->stencil
[1].enabled
) {
1015 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1016 db_depth_control
|= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state
->stencil
[1].func
));
1017 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
1018 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
1019 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
1020 stencil_ref_mask_bf
= S_028434_STENCILMASK_BF(state
->stencil
[1].valuemask
) |
1021 S_028434_STENCILWRITEMASK_BF(state
->stencil
[1].writemask
);
1022 stencil_ref_mask_bf
|= S_028430_STENCILREF(stencil_ref
->ref_value
[1]);
1026 alpha_test_control
= 0;
1028 if (state
->alpha
.enabled
) {
1029 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
1030 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
1031 alpha_ref
= fui(state
->alpha
.ref_value
);
1034 rstate
->states
[R600_DSA__DB_STENCIL_CLEAR
] = 0x00000000;
1035 rstate
->states
[R600_DSA__DB_DEPTH_CLEAR
] = 0x3F800000;
1036 rstate
->states
[R600_DSA__SX_ALPHA_TEST_CONTROL
] = alpha_test_control
;
1037 rstate
->states
[R600_DSA__DB_STENCILREFMASK
] = stencil_ref_mask
;
1038 rstate
->states
[R600_DSA__DB_STENCILREFMASK_BF
] = stencil_ref_mask_bf
;
1039 rstate
->states
[R600_DSA__SX_ALPHA_REF
] = alpha_ref
;
1040 rstate
->states
[R600_DSA__SPI_FOG_FUNC_SCALE
] = 0x00000000;
1041 rstate
->states
[R600_DSA__SPI_FOG_FUNC_BIAS
] = 0x00000000;
1042 rstate
->states
[R600_DSA__SPI_FOG_CNTL
] = 0x00000000;
1043 rstate
->states
[R600_DSA__DB_DEPTH_CONTROL
] = db_depth_control
;
1044 rstate
->states
[R600_DSA__DB_SHADER_CONTROL
] = db_shader_control
;
1045 rstate
->states
[R600_DSA__DB_RENDER_CONTROL
] = 0x00000060;
1046 rstate
->states
[R600_DSA__DB_RENDER_OVERRIDE
] = 0x0000002A;
1047 rstate
->states
[R600_DSA__DB_SRESULTS_COMPARE_STATE1
] = 0x00000000;
1048 rstate
->states
[R600_DSA__DB_PRELOAD_CONTROL
] = 0x00000000;
1049 rstate
->states
[R600_DSA__DB_ALPHA_TO_MASK
] = 0x0000AA00;
1050 if (radeon_state_pm4(rstate
)) {
1051 radeon_state_decref(rstate
);
1057 static inline unsigned r600_tex_wrap(unsigned wrap
)
1061 case PIPE_TEX_WRAP_REPEAT
:
1062 return V_03C000_SQ_TEX_WRAP
;
1063 case PIPE_TEX_WRAP_CLAMP
:
1064 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1065 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1066 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1067 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1068 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1069 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1070 return V_03C000_SQ_TEX_MIRROR
;
1071 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1072 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1073 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1074 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1075 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1076 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1080 static inline unsigned r600_tex_filter(unsigned filter
)
1084 case PIPE_TEX_FILTER_NEAREST
:
1085 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1086 case PIPE_TEX_FILTER_LINEAR
:
1087 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1091 static inline unsigned r600_tex_mipfilter(unsigned filter
)
1094 case PIPE_TEX_MIPFILTER_NEAREST
:
1095 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1096 case PIPE_TEX_MIPFILTER_LINEAR
:
1097 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1099 case PIPE_TEX_MIPFILTER_NONE
:
1100 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1104 static inline unsigned r600_tex_compare(unsigned compare
)
1108 case PIPE_FUNC_NEVER
:
1109 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1110 case PIPE_FUNC_LESS
:
1111 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1112 case PIPE_FUNC_EQUAL
:
1113 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1114 case PIPE_FUNC_LEQUAL
:
1115 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1116 case PIPE_FUNC_GREATER
:
1117 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1118 case PIPE_FUNC_NOTEQUAL
:
1119 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1120 case PIPE_FUNC_GEQUAL
:
1121 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1122 case PIPE_FUNC_ALWAYS
:
1123 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1127 static INLINE u32
S_FIXED(float value
, u32 frac_bits
)
1129 return value
* (1 << frac_bits
);
1132 static struct radeon_state
*r600_sampler(struct r600_context
*rctx
,
1133 const struct pipe_sampler_state
*state
,
1136 struct r600_screen
*rscreen
= rctx
->screen
;
1137 struct radeon_state
*rstate
;
1139 rstate
= radeon_state(rscreen
->rw
, R600_PS_SAMPLER_TYPE
, id
);
1142 rstate
->states
[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0
] =
1143 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
1144 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
1145 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
1146 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
)) |
1147 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
)) |
1148 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
1149 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
));
1150 /* FIXME LOD it depends on texture base level ... */
1151 rstate
->states
[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0
] =
1152 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 6)) |
1153 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 6)) |
1154 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 6));
1155 rstate
->states
[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0
] = S_03C008_TYPE(1);
1156 if (radeon_state_pm4(rstate
)) {
1157 radeon_state_decref(rstate
);
1163 static inline unsigned r600_tex_swizzle(unsigned swizzle
)
1166 case PIPE_SWIZZLE_RED
:
1167 return V_038010_SQ_SEL_X
;
1168 case PIPE_SWIZZLE_GREEN
:
1169 return V_038010_SQ_SEL_Y
;
1170 case PIPE_SWIZZLE_BLUE
:
1171 return V_038010_SQ_SEL_Z
;
1172 case PIPE_SWIZZLE_ALPHA
:
1173 return V_038010_SQ_SEL_W
;
1174 case PIPE_SWIZZLE_ZERO
:
1175 return V_038010_SQ_SEL_0
;
1177 case PIPE_SWIZZLE_ONE
:
1178 return V_038010_SQ_SEL_1
;
1182 static inline unsigned r600_format_type(unsigned format_type
)
1184 switch (format_type
) {
1186 case UTIL_FORMAT_TYPE_UNSIGNED
:
1187 return V_038010_SQ_FORMAT_COMP_UNSIGNED
;
1188 case UTIL_FORMAT_TYPE_SIGNED
:
1189 return V_038010_SQ_FORMAT_COMP_SIGNED
;
1190 case UTIL_FORMAT_TYPE_FIXED
:
1191 return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED
;
1195 static inline unsigned r600_tex_dim(unsigned dim
)
1199 case PIPE_TEXTURE_1D
:
1200 return V_038000_SQ_TEX_DIM_1D
;
1201 case PIPE_TEXTURE_2D
:
1202 case PIPE_TEXTURE_RECT
:
1203 return V_038000_SQ_TEX_DIM_2D
;
1204 case PIPE_TEXTURE_3D
:
1205 return V_038000_SQ_TEX_DIM_3D
;
1206 case PIPE_TEXTURE_CUBE
:
1207 return V_038000_SQ_TEX_DIM_CUBEMAP
;
1211 static struct radeon_state
*r600_resource(struct r600_context
*rctx
,
1212 const struct pipe_sampler_view
*view
,
1215 struct r600_screen
*rscreen
= rctx
->screen
;
1216 const struct util_format_description
*desc
;
1217 struct r600_resource_texture
*tmp
;
1218 struct r600_resource
*rbuffer
;
1219 struct radeon_state
*rstate
;
1221 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
1222 unsigned char swizzle
[4];
1224 swizzle
[0] = view
->swizzle_r
;
1225 swizzle
[1] = view
->swizzle_g
;
1226 swizzle
[2] = view
->swizzle_b
;
1227 swizzle
[3] = view
->swizzle_a
;
1228 format
= r600_translate_texformat(view
->texture
->format
,
1230 &word4
, &yuv_format
);
1233 desc
= util_format_description(view
->texture
->format
);
1235 R600_ERR("unknow format %d\n", view
->texture
->format
);
1238 rstate
= radeon_state(rscreen
->rw
, R600_PS_RESOURCE_TYPE
, id
);
1239 if (rstate
== NULL
) {
1242 tmp
= (struct r600_resource_texture
*)view
->texture
;
1243 rbuffer
= &tmp
->resource
;
1244 rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
1245 rstate
->bo
[1] = radeon_bo_incref(rscreen
->rw
, rbuffer
->bo
);
1247 rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
1248 rstate
->placement
[1] = RADEON_GEM_DOMAIN_GTT
;
1249 rstate
->placement
[2] = RADEON_GEM_DOMAIN_GTT
;
1250 rstate
->placement
[3] = RADEON_GEM_DOMAIN_GTT
;
1252 pitch
= (tmp
->pitch
[0] / tmp
->bpt
);
1253 pitch
= (pitch
+ 0x7) & ~0x7;
1255 /* FIXME properly handle first level != 0 */
1256 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD0
] =
1257 S_038000_DIM(r600_tex_dim(view
->texture
->target
)) |
1258 S_038000_PITCH((pitch
/ 8) - 1) |
1259 S_038000_TEX_WIDTH(view
->texture
->width0
- 1);
1260 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD1
] =
1261 S_038004_TEX_HEIGHT(view
->texture
->height0
- 1) |
1262 S_038004_TEX_DEPTH(view
->texture
->depth0
- 1) |
1263 S_038004_DATA_FORMAT(format
);
1264 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD2
] = tmp
->offset
[0] >> 8;
1265 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD3
] = tmp
->offset
[1] >> 8;
1266 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD4
] =
1268 S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM
) |
1269 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO
) |
1270 S_038010_REQUEST_SIZE(1) |
1271 S_038010_BASE_LEVEL(view
->first_level
);
1272 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD5
] =
1273 S_038014_LAST_LEVEL(view
->last_level
) |
1274 S_038014_BASE_ARRAY(0) |
1275 S_038014_LAST_ARRAY(0);
1276 rstate
->states
[R600_PS_RESOURCE__RESOURCE0_WORD6
] =
1277 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE
);
1278 if (radeon_state_pm4(rstate
)) {
1279 radeon_state_decref(rstate
);
1285 static struct radeon_state
*r600_cb_cntl(struct r600_context
*rctx
)
1287 struct r600_screen
*rscreen
= rctx
->screen
;
1288 struct radeon_state
*rstate
;
1289 const struct pipe_blend_state
*pbs
= &rctx
->blend
->state
.blend
;
1290 int nr_cbufs
= rctx
->framebuffer
->state
.framebuffer
.nr_cbufs
;
1291 uint32_t color_control
, target_mask
, shader_mask
;
1296 color_control
= S_028808_PER_MRT_BLEND(1);
1298 for (i
= 0; i
< nr_cbufs
; i
++) {
1299 shader_mask
|= 0xf << (i
* 4);
1302 if (pbs
->logicop_enable
) {
1303 color_control
|= (pbs
->logicop_func
) << 16;
1305 color_control
|= (0xcc << 16);
1308 if (pbs
->independent_blend_enable
) {
1309 for (i
= 0; i
< nr_cbufs
; i
++) {
1310 if (pbs
->rt
[i
].blend_enable
) {
1311 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
1313 target_mask
|= (pbs
->rt
[i
].colormask
<< (4 * i
));
1316 for (i
= 0; i
< nr_cbufs
; i
++) {
1317 if (pbs
->rt
[0].blend_enable
) {
1318 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
1320 target_mask
|= (pbs
->rt
[0].colormask
<< (4 * i
));
1323 rstate
= radeon_state(rscreen
->rw
, R600_CB_CNTL_TYPE
, R600_CB_CNTL
);
1324 rstate
->states
[R600_CB_CNTL__CB_SHADER_MASK
] = shader_mask
;
1325 rstate
->states
[R600_CB_CNTL__CB_TARGET_MASK
] = target_mask
;
1326 rstate
->states
[R600_CB_CNTL__CB_COLOR_CONTROL
] = color_control
;
1327 rstate
->states
[R600_CB_CNTL__PA_SC_AA_CONFIG
] = 0x00000000;
1328 rstate
->states
[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX
] = 0x00000000;
1329 rstate
->states
[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX
] = 0x00000000;
1330 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_CONTROL
] = 0x01000000;
1331 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_SRC
] = 0x00000000;
1332 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_DST
] = 0x000000FF;
1333 rstate
->states
[R600_CB_CNTL__CB_CLRCMP_MSK
] = 0xFFFFFFFF;
1334 rstate
->states
[R600_CB_CNTL__PA_SC_AA_MASK
] = 0xFFFFFFFF;
1335 if (radeon_state_pm4(rstate
)) {
1336 radeon_state_decref(rstate
);
1342 int r600_context_hw_states(struct r600_context
*rctx
)
1346 int nr_cbufs
= rctx
->framebuffer
->state
.framebuffer
.nr_cbufs
;
1350 ucp_nclip
= rctx
->clip
->state
.clip
.nr
;
1352 /* free previous TODO determine what need to be updated, what
1355 //radeon_state_decref(rctx->hw_states.config);
1356 rctx
->hw_states
.cb_cntl
= radeon_state_decref(rctx
->hw_states
.cb_cntl
);
1357 rctx
->hw_states
.db
= radeon_state_decref(rctx
->hw_states
.db
);
1358 rctx
->hw_states
.rasterizer
= radeon_state_decref(rctx
->hw_states
.rasterizer
);
1359 rctx
->hw_states
.scissor
= radeon_state_decref(rctx
->hw_states
.scissor
);
1360 rctx
->hw_states
.dsa
= radeon_state_decref(rctx
->hw_states
.dsa
);
1361 rctx
->hw_states
.blend
= radeon_state_decref(rctx
->hw_states
.blend
);
1362 rctx
->hw_states
.viewport
= radeon_state_decref(rctx
->hw_states
.viewport
);
1363 for (i
= 0; i
< 8; i
++) {
1364 rctx
->hw_states
.cb
[i
] = radeon_state_decref(rctx
->hw_states
.cb
[i
]);
1366 for (i
= 0; i
< 6; i
++) {
1367 rctx
->hw_states
.ucp
[i
] = radeon_state_decref(rctx
->hw_states
.ucp
[i
]);
1369 for (i
= 0; i
< rctx
->hw_states
.ps_nresource
; i
++) {
1370 radeon_state_decref(rctx
->hw_states
.ps_resource
[i
]);
1371 rctx
->hw_states
.ps_resource
[i
] = NULL
;
1373 rctx
->hw_states
.ps_nresource
= 0;
1374 for (i
= 0; i
< rctx
->hw_states
.ps_nsampler
; i
++) {
1375 radeon_state_decref(rctx
->hw_states
.ps_sampler
[i
]);
1376 rctx
->hw_states
.ps_sampler
[i
] = NULL
;
1378 rctx
->hw_states
.ps_nsampler
= 0;
1380 /* build new states */
1381 rctx
->hw_states
.rasterizer
= r600_rasterizer(rctx
);
1382 rctx
->hw_states
.scissor
= r600_scissor(rctx
);
1383 rctx
->hw_states
.dsa
= r600_dsa(rctx
);
1384 rctx
->hw_states
.blend
= r600_blend(rctx
);
1385 rctx
->hw_states
.viewport
= r600_viewport(rctx
);
1386 for (i
= 0; i
< nr_cbufs
; i
++) {
1387 rctx
->hw_states
.cb
[i
] = r600_cb(rctx
, i
);
1389 for (i
= 0; i
< ucp_nclip
; i
++) {
1390 rctx
->hw_states
.ucp
[i
] = r600_ucp(rctx
, i
);
1392 rctx
->hw_states
.db
= r600_db(rctx
);
1393 rctx
->hw_states
.cb_cntl
= r600_cb_cntl(rctx
);
1395 for (i
= 0; i
< rctx
->ps_nsampler
; i
++) {
1396 if (rctx
->ps_sampler
[i
]) {
1397 rctx
->hw_states
.ps_sampler
[i
] = r600_sampler(rctx
,
1398 &rctx
->ps_sampler
[i
]->state
.sampler
,
1399 R600_PS_SAMPLER
+ i
);
1402 rctx
->hw_states
.ps_nsampler
= rctx
->ps_nsampler
;
1403 for (i
= 0; i
< rctx
->ps_nsampler_view
; i
++) {
1404 if (rctx
->ps_sampler_view
[i
]) {
1405 rctx
->hw_states
.ps_resource
[i
] = r600_resource(rctx
,
1406 &rctx
->ps_sampler_view
[i
]->state
.sampler_view
,
1407 R600_PS_RESOURCE
+ i
);
1410 rctx
->hw_states
.ps_nresource
= rctx
->ps_nsampler_view
;
1413 for (i
= 0; i
< ucp_nclip
; i
++) {
1414 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.ucp
[i
]);
1418 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.db
);
1421 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.rasterizer
);
1424 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.scissor
);
1427 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.dsa
);
1430 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.blend
);
1433 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.viewport
);
1436 for (i
= 0; i
< nr_cbufs
; i
++) {
1437 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.cb
[i
]);
1441 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.config
);
1444 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.cb_cntl
);
1447 for (i
= 0; i
< rctx
->hw_states
.ps_nresource
; i
++) {
1448 if (rctx
->hw_states
.ps_resource
[i
]) {
1449 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.ps_resource
[i
]);
1454 for (i
= 0; i
< rctx
->hw_states
.ps_nsampler
; i
++) {
1455 if (rctx
->hw_states
.ps_sampler
[i
]) {
1456 r
= radeon_draw_set(rctx
->draw
, rctx
->hw_states
.ps_sampler
[i
]);