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r600g: Store the chip class in r600_pipe_context.
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_double_list.h>
36 #include <util/u_pack_color.h>
37 #include <util/u_memory.h>
38 #include <util/u_inlines.h>
39 #include <util/u_framebuffer.h>
40 #include "util/u_transfer.h"
41 #include <pipebuffer/pb_buffer.h>
42 #include "r600.h"
43 #include "r600d.h"
44 #include "r600_resource.h"
45 #include "r600_shader.h"
46 #include "r600_pipe.h"
47 #include "r600_formats.h"
48
49 static uint32_t r600_translate_blend_function(int blend_func)
50 {
51 switch (blend_func) {
52 case PIPE_BLEND_ADD:
53 return V_028804_COMB_DST_PLUS_SRC;
54 case PIPE_BLEND_SUBTRACT:
55 return V_028804_COMB_SRC_MINUS_DST;
56 case PIPE_BLEND_REVERSE_SUBTRACT:
57 return V_028804_COMB_DST_MINUS_SRC;
58 case PIPE_BLEND_MIN:
59 return V_028804_COMB_MIN_DST_SRC;
60 case PIPE_BLEND_MAX:
61 return V_028804_COMB_MAX_DST_SRC;
62 default:
63 R600_ERR("Unknown blend function %d\n", blend_func);
64 assert(0);
65 break;
66 }
67 return 0;
68 }
69
70 static uint32_t r600_translate_blend_factor(int blend_fact)
71 {
72 switch (blend_fact) {
73 case PIPE_BLENDFACTOR_ONE:
74 return V_028804_BLEND_ONE;
75 case PIPE_BLENDFACTOR_SRC_COLOR:
76 return V_028804_BLEND_SRC_COLOR;
77 case PIPE_BLENDFACTOR_SRC_ALPHA:
78 return V_028804_BLEND_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_DST_ALPHA:
80 return V_028804_BLEND_DST_ALPHA;
81 case PIPE_BLENDFACTOR_DST_COLOR:
82 return V_028804_BLEND_DST_COLOR;
83 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
84 return V_028804_BLEND_SRC_ALPHA_SATURATE;
85 case PIPE_BLENDFACTOR_CONST_COLOR:
86 return V_028804_BLEND_CONST_COLOR;
87 case PIPE_BLENDFACTOR_CONST_ALPHA:
88 return V_028804_BLEND_CONST_ALPHA;
89 case PIPE_BLENDFACTOR_ZERO:
90 return V_028804_BLEND_ZERO;
91 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
92 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
94 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
95 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
96 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
97 case PIPE_BLENDFACTOR_INV_DST_COLOR:
98 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
99 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
100 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
101 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
102 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
103 case PIPE_BLENDFACTOR_SRC1_COLOR:
104 return V_028804_BLEND_SRC1_COLOR;
105 case PIPE_BLENDFACTOR_SRC1_ALPHA:
106 return V_028804_BLEND_SRC1_ALPHA;
107 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
108 return V_028804_BLEND_INV_SRC1_COLOR;
109 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
110 return V_028804_BLEND_INV_SRC1_ALPHA;
111 default:
112 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
113 assert(0);
114 break;
115 }
116 return 0;
117 }
118
119 static uint32_t r600_translate_stencil_op(int s_op)
120 {
121 switch (s_op) {
122 case PIPE_STENCIL_OP_KEEP:
123 return V_028800_STENCIL_KEEP;
124 case PIPE_STENCIL_OP_ZERO:
125 return V_028800_STENCIL_ZERO;
126 case PIPE_STENCIL_OP_REPLACE:
127 return V_028800_STENCIL_REPLACE;
128 case PIPE_STENCIL_OP_INCR:
129 return V_028800_STENCIL_INCR;
130 case PIPE_STENCIL_OP_DECR:
131 return V_028800_STENCIL_DECR;
132 case PIPE_STENCIL_OP_INCR_WRAP:
133 return V_028800_STENCIL_INCR_WRAP;
134 case PIPE_STENCIL_OP_DECR_WRAP:
135 return V_028800_STENCIL_DECR_WRAP;
136 case PIPE_STENCIL_OP_INVERT:
137 return V_028800_STENCIL_INVERT;
138 default:
139 R600_ERR("Unknown stencil op %d", s_op);
140 assert(0);
141 break;
142 }
143 return 0;
144 }
145
146 static uint32_t r600_translate_fill(uint32_t func)
147 {
148 switch(func) {
149 case PIPE_POLYGON_MODE_FILL:
150 return 2;
151 case PIPE_POLYGON_MODE_LINE:
152 return 1;
153 case PIPE_POLYGON_MODE_POINT:
154 return 0;
155 default:
156 assert(0);
157 return 0;
158 }
159 }
160
161 /* translates straight */
162 static uint32_t r600_translate_ds_func(int func)
163 {
164 return func;
165 }
166
167 static unsigned r600_tex_wrap(unsigned wrap)
168 {
169 switch (wrap) {
170 default:
171 case PIPE_TEX_WRAP_REPEAT:
172 return V_03C000_SQ_TEX_WRAP;
173 case PIPE_TEX_WRAP_CLAMP:
174 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
175 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
176 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
177 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
178 return V_03C000_SQ_TEX_CLAMP_BORDER;
179 case PIPE_TEX_WRAP_MIRROR_REPEAT:
180 return V_03C000_SQ_TEX_MIRROR;
181 case PIPE_TEX_WRAP_MIRROR_CLAMP:
182 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
183 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
184 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
185 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
186 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
187 }
188 }
189
190 static unsigned r600_tex_filter(unsigned filter)
191 {
192 switch (filter) {
193 default:
194 case PIPE_TEX_FILTER_NEAREST:
195 return V_03C000_SQ_TEX_XY_FILTER_POINT;
196 case PIPE_TEX_FILTER_LINEAR:
197 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
198 }
199 }
200
201 static unsigned r600_tex_mipfilter(unsigned filter)
202 {
203 switch (filter) {
204 case PIPE_TEX_MIPFILTER_NEAREST:
205 return V_03C000_SQ_TEX_Z_FILTER_POINT;
206 case PIPE_TEX_MIPFILTER_LINEAR:
207 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
208 default:
209 case PIPE_TEX_MIPFILTER_NONE:
210 return V_03C000_SQ_TEX_Z_FILTER_NONE;
211 }
212 }
213
214 static unsigned r600_tex_compare(unsigned compare)
215 {
216 switch (compare) {
217 default:
218 case PIPE_FUNC_NEVER:
219 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
220 case PIPE_FUNC_LESS:
221 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
222 case PIPE_FUNC_EQUAL:
223 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
224 case PIPE_FUNC_LEQUAL:
225 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
226 case PIPE_FUNC_GREATER:
227 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
228 case PIPE_FUNC_NOTEQUAL:
229 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
230 case PIPE_FUNC_GEQUAL:
231 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
232 case PIPE_FUNC_ALWAYS:
233 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
234 }
235 }
236
237 static unsigned r600_tex_dim(unsigned dim)
238 {
239 switch (dim) {
240 default:
241 case PIPE_TEXTURE_1D:
242 return V_038000_SQ_TEX_DIM_1D;
243 case PIPE_TEXTURE_1D_ARRAY:
244 return V_038000_SQ_TEX_DIM_1D_ARRAY;
245 case PIPE_TEXTURE_2D:
246 case PIPE_TEXTURE_RECT:
247 return V_038000_SQ_TEX_DIM_2D;
248 case PIPE_TEXTURE_2D_ARRAY:
249 return V_038000_SQ_TEX_DIM_2D_ARRAY;
250 case PIPE_TEXTURE_3D:
251 return V_038000_SQ_TEX_DIM_3D;
252 case PIPE_TEXTURE_CUBE:
253 return V_038000_SQ_TEX_DIM_CUBEMAP;
254 }
255 }
256
257 static uint32_t r600_translate_dbformat(enum pipe_format format)
258 {
259 switch (format) {
260 case PIPE_FORMAT_Z16_UNORM:
261 return V_028010_DEPTH_16;
262 case PIPE_FORMAT_Z24X8_UNORM:
263 return V_028010_DEPTH_X8_24;
264 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
265 return V_028010_DEPTH_8_24;
266 default:
267 return ~0U;
268 }
269 }
270
271 static uint32_t r600_translate_colorswap(enum pipe_format format)
272 {
273 switch (format) {
274 /* 8-bit buffers. */
275 case PIPE_FORMAT_A8_UNORM:
276 return V_0280A0_SWAP_ALT_REV;
277 case PIPE_FORMAT_I8_UNORM:
278 case PIPE_FORMAT_L8_UNORM:
279 case PIPE_FORMAT_L8_SRGB:
280 case PIPE_FORMAT_R8_UNORM:
281 case PIPE_FORMAT_R8_SNORM:
282 return V_0280A0_SWAP_STD;
283
284 case PIPE_FORMAT_L4A4_UNORM:
285 return V_0280A0_SWAP_ALT;
286
287 /* 16-bit buffers. */
288 case PIPE_FORMAT_B5G6R5_UNORM:
289 return V_0280A0_SWAP_STD_REV;
290
291 case PIPE_FORMAT_B5G5R5A1_UNORM:
292 case PIPE_FORMAT_B5G5R5X1_UNORM:
293 return V_0280A0_SWAP_ALT;
294
295 case PIPE_FORMAT_B4G4R4A4_UNORM:
296 case PIPE_FORMAT_B4G4R4X4_UNORM:
297 return V_0280A0_SWAP_ALT;
298
299 case PIPE_FORMAT_Z16_UNORM:
300 return V_0280A0_SWAP_STD;
301
302 case PIPE_FORMAT_L8A8_UNORM:
303 case PIPE_FORMAT_L8A8_SRGB:
304 return V_0280A0_SWAP_ALT;
305 case PIPE_FORMAT_R8G8_UNORM:
306 return V_0280A0_SWAP_STD;
307
308 case PIPE_FORMAT_R16_UNORM:
309 case PIPE_FORMAT_R16_FLOAT:
310 return V_0280A0_SWAP_STD;
311
312 /* 32-bit buffers. */
313
314 case PIPE_FORMAT_A8B8G8R8_SRGB:
315 return V_0280A0_SWAP_STD_REV;
316 case PIPE_FORMAT_B8G8R8A8_SRGB:
317 return V_0280A0_SWAP_ALT;
318
319 case PIPE_FORMAT_B8G8R8A8_UNORM:
320 case PIPE_FORMAT_B8G8R8X8_UNORM:
321 return V_0280A0_SWAP_ALT;
322
323 case PIPE_FORMAT_A8R8G8B8_UNORM:
324 case PIPE_FORMAT_X8R8G8B8_UNORM:
325 return V_0280A0_SWAP_ALT_REV;
326 case PIPE_FORMAT_R8G8B8A8_SNORM:
327 case PIPE_FORMAT_R8G8B8A8_UNORM:
328 case PIPE_FORMAT_R8G8B8X8_UNORM:
329 return V_0280A0_SWAP_STD;
330
331 case PIPE_FORMAT_A8B8G8R8_UNORM:
332 case PIPE_FORMAT_X8B8G8R8_UNORM:
333 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
334 return V_0280A0_SWAP_STD_REV;
335
336 case PIPE_FORMAT_Z24X8_UNORM:
337 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
338 return V_0280A0_SWAP_STD;
339
340 case PIPE_FORMAT_X8Z24_UNORM:
341 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
342 return V_0280A0_SWAP_STD;
343
344 case PIPE_FORMAT_R10G10B10A2_UNORM:
345 case PIPE_FORMAT_R10G10B10X2_SNORM:
346 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
347 return V_0280A0_SWAP_STD;
348
349 case PIPE_FORMAT_B10G10R10A2_UNORM:
350 return V_0280A0_SWAP_ALT;
351
352 case PIPE_FORMAT_R11G11B10_FLOAT:
353 case PIPE_FORMAT_R16G16_UNORM:
354 case PIPE_FORMAT_R16G16_FLOAT:
355 case PIPE_FORMAT_R32_FLOAT:
356 return V_0280A0_SWAP_STD;
357
358 /* 64-bit buffers. */
359 case PIPE_FORMAT_R32G32_FLOAT:
360 case PIPE_FORMAT_R16G16B16A16_UNORM:
361 case PIPE_FORMAT_R16G16B16A16_SNORM:
362 case PIPE_FORMAT_R16G16B16A16_FLOAT:
363
364 /* 128-bit buffers. */
365 case PIPE_FORMAT_R32G32B32A32_FLOAT:
366 case PIPE_FORMAT_R32G32B32A32_SNORM:
367 case PIPE_FORMAT_R32G32B32A32_UNORM:
368 return V_0280A0_SWAP_STD;
369 default:
370 R600_ERR("unsupported colorswap format %d\n", format);
371 return ~0U;
372 }
373 return ~0U;
374 }
375
376 static uint32_t r600_translate_colorformat(enum pipe_format format)
377 {
378 switch (format) {
379 case PIPE_FORMAT_L4A4_UNORM:
380 return V_0280A0_COLOR_4_4;
381
382 /* 8-bit buffers. */
383 case PIPE_FORMAT_A8_UNORM:
384 case PIPE_FORMAT_I8_UNORM:
385 case PIPE_FORMAT_L8_UNORM:
386 case PIPE_FORMAT_L8_SRGB:
387 case PIPE_FORMAT_R8_UNORM:
388 case PIPE_FORMAT_R8_SNORM:
389 return V_0280A0_COLOR_8;
390
391 /* 16-bit buffers. */
392 case PIPE_FORMAT_B5G6R5_UNORM:
393 return V_0280A0_COLOR_5_6_5;
394
395 case PIPE_FORMAT_B5G5R5A1_UNORM:
396 case PIPE_FORMAT_B5G5R5X1_UNORM:
397 return V_0280A0_COLOR_1_5_5_5;
398
399 case PIPE_FORMAT_B4G4R4A4_UNORM:
400 case PIPE_FORMAT_B4G4R4X4_UNORM:
401 return V_0280A0_COLOR_4_4_4_4;
402
403 case PIPE_FORMAT_Z16_UNORM:
404 return V_0280A0_COLOR_16;
405
406 case PIPE_FORMAT_L8A8_UNORM:
407 case PIPE_FORMAT_L8A8_SRGB:
408 case PIPE_FORMAT_R8G8_UNORM:
409 return V_0280A0_COLOR_8_8;
410
411 case PIPE_FORMAT_R16_UNORM:
412 return V_0280A0_COLOR_16;
413
414 case PIPE_FORMAT_R16_FLOAT:
415 return V_0280A0_COLOR_16_FLOAT;
416
417 /* 32-bit buffers. */
418 case PIPE_FORMAT_A8B8G8R8_SRGB:
419 case PIPE_FORMAT_A8B8G8R8_UNORM:
420 case PIPE_FORMAT_A8R8G8B8_UNORM:
421 case PIPE_FORMAT_B8G8R8A8_SRGB:
422 case PIPE_FORMAT_B8G8R8A8_UNORM:
423 case PIPE_FORMAT_B8G8R8X8_UNORM:
424 case PIPE_FORMAT_R8G8B8A8_SNORM:
425 case PIPE_FORMAT_R8G8B8A8_UNORM:
426 case PIPE_FORMAT_R8G8B8X8_UNORM:
427 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
428 case PIPE_FORMAT_X8B8G8R8_UNORM:
429 case PIPE_FORMAT_X8R8G8B8_UNORM:
430 case PIPE_FORMAT_R8G8B8_UNORM:
431 return V_0280A0_COLOR_8_8_8_8;
432
433 case PIPE_FORMAT_R10G10B10A2_UNORM:
434 case PIPE_FORMAT_R10G10B10X2_SNORM:
435 case PIPE_FORMAT_B10G10R10A2_UNORM:
436 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
437 return V_0280A0_COLOR_2_10_10_10;
438
439 case PIPE_FORMAT_Z24X8_UNORM:
440 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
441 return V_0280A0_COLOR_8_24;
442
443 case PIPE_FORMAT_X8Z24_UNORM:
444 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
445 return V_0280A0_COLOR_24_8;
446
447 case PIPE_FORMAT_R32_FLOAT:
448 return V_0280A0_COLOR_32_FLOAT;
449
450 case PIPE_FORMAT_R16G16_FLOAT:
451 return V_0280A0_COLOR_16_16_FLOAT;
452
453 case PIPE_FORMAT_R16G16_SSCALED:
454 case PIPE_FORMAT_R16G16_UNORM:
455 return V_0280A0_COLOR_16_16;
456
457 case PIPE_FORMAT_R11G11B10_FLOAT:
458 return V_0280A0_COLOR_10_11_11_FLOAT;
459
460 /* 64-bit buffers. */
461 case PIPE_FORMAT_R16G16B16_USCALED:
462 case PIPE_FORMAT_R16G16B16A16_USCALED:
463 case PIPE_FORMAT_R16G16B16_SSCALED:
464 case PIPE_FORMAT_R16G16B16A16_SSCALED:
465 case PIPE_FORMAT_R16G16B16A16_UNORM:
466 case PIPE_FORMAT_R16G16B16A16_SNORM:
467 return V_0280A0_COLOR_16_16_16_16;
468
469 case PIPE_FORMAT_R16G16B16_FLOAT:
470 case PIPE_FORMAT_R16G16B16A16_FLOAT:
471 return V_0280A0_COLOR_16_16_16_16_FLOAT;
472
473 case PIPE_FORMAT_R32G32_FLOAT:
474 return V_0280A0_COLOR_32_32_FLOAT;
475
476 case PIPE_FORMAT_R32G32_USCALED:
477 case PIPE_FORMAT_R32G32_SSCALED:
478 return V_0280A0_COLOR_32_32;
479
480 /* 96-bit buffers. */
481 case PIPE_FORMAT_R32G32B32_FLOAT:
482 return V_0280A0_COLOR_32_32_32_FLOAT;
483
484 /* 128-bit buffers. */
485 case PIPE_FORMAT_R32G32B32A32_FLOAT:
486 return V_0280A0_COLOR_32_32_32_32_FLOAT;
487 case PIPE_FORMAT_R32G32B32A32_SNORM:
488 case PIPE_FORMAT_R32G32B32A32_UNORM:
489 return V_0280A0_COLOR_32_32_32_32;
490
491 /* YUV buffers. */
492 case PIPE_FORMAT_UYVY:
493 case PIPE_FORMAT_YUYV:
494 default:
495 return ~0U; /* Unsupported. */
496 }
497 }
498
499 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
500 {
501 if (R600_BIG_ENDIAN) {
502 switch(colorformat) {
503 case V_0280A0_COLOR_4_4:
504 return(ENDIAN_NONE);
505
506 /* 8-bit buffers. */
507 case V_0280A0_COLOR_8:
508 return(ENDIAN_NONE);
509
510 /* 16-bit buffers. */
511 case V_0280A0_COLOR_5_6_5:
512 case V_0280A0_COLOR_1_5_5_5:
513 case V_0280A0_COLOR_4_4_4_4:
514 case V_0280A0_COLOR_16:
515 case V_0280A0_COLOR_8_8:
516 return(ENDIAN_8IN16);
517
518 /* 32-bit buffers. */
519 case V_0280A0_COLOR_8_8_8_8:
520 case V_0280A0_COLOR_2_10_10_10:
521 case V_0280A0_COLOR_8_24:
522 case V_0280A0_COLOR_24_8:
523 case V_0280A0_COLOR_32_FLOAT:
524 case V_0280A0_COLOR_16_16_FLOAT:
525 case V_0280A0_COLOR_16_16:
526 return(ENDIAN_8IN32);
527
528 /* 64-bit buffers. */
529 case V_0280A0_COLOR_16_16_16_16:
530 case V_0280A0_COLOR_16_16_16_16_FLOAT:
531 return(ENDIAN_8IN16);
532
533 case V_0280A0_COLOR_32_32_FLOAT:
534 case V_0280A0_COLOR_32_32:
535 return(ENDIAN_8IN32);
536
537 /* 128-bit buffers. */
538 case V_0280A0_COLOR_32_32_32_FLOAT:
539 case V_0280A0_COLOR_32_32_32_32_FLOAT:
540 case V_0280A0_COLOR_32_32_32_32:
541 return(ENDIAN_8IN32);
542 default:
543 return ENDIAN_NONE; /* Unsupported. */
544 }
545 } else {
546 return ENDIAN_NONE;
547 }
548 }
549
550 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
551 {
552 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
553 }
554
555 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
556 {
557 return r600_translate_colorformat(format) != ~0U &&
558 r600_translate_colorswap(format) != ~0U;
559 }
560
561 static bool r600_is_zs_format_supported(enum pipe_format format)
562 {
563 return r600_translate_dbformat(format) != ~0U;
564 }
565
566 boolean r600_is_format_supported(struct pipe_screen *screen,
567 enum pipe_format format,
568 enum pipe_texture_target target,
569 unsigned sample_count,
570 unsigned usage)
571 {
572 unsigned retval = 0;
573
574 if (target >= PIPE_MAX_TEXTURE_TYPES) {
575 R600_ERR("r600: unsupported texture type %d\n", target);
576 return FALSE;
577 }
578
579 if (!util_format_is_supported(format, usage))
580 return FALSE;
581
582 /* Multisample */
583 if (sample_count > 1)
584 return FALSE;
585
586 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
587 r600_is_sampler_format_supported(screen, format)) {
588 retval |= PIPE_BIND_SAMPLER_VIEW;
589 }
590
591 if ((usage & (PIPE_BIND_RENDER_TARGET |
592 PIPE_BIND_DISPLAY_TARGET |
593 PIPE_BIND_SCANOUT |
594 PIPE_BIND_SHARED)) &&
595 r600_is_colorbuffer_format_supported(format)) {
596 retval |= usage &
597 (PIPE_BIND_RENDER_TARGET |
598 PIPE_BIND_DISPLAY_TARGET |
599 PIPE_BIND_SCANOUT |
600 PIPE_BIND_SHARED);
601 }
602
603 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
604 r600_is_zs_format_supported(format)) {
605 retval |= PIPE_BIND_DEPTH_STENCIL;
606 }
607
608 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
609 r600_is_vertex_format_supported(format)) {
610 retval |= PIPE_BIND_VERTEX_BUFFER;
611 }
612
613 if (usage & PIPE_BIND_TRANSFER_READ)
614 retval |= PIPE_BIND_TRANSFER_READ;
615 if (usage & PIPE_BIND_TRANSFER_WRITE)
616 retval |= PIPE_BIND_TRANSFER_WRITE;
617
618 return retval == usage;
619 }
620
621 void r600_polygon_offset_update(struct r600_pipe_context *rctx)
622 {
623 struct r600_pipe_state state;
624
625 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
626 state.nregs = 0;
627 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
628 float offset_units = rctx->rasterizer->offset_units;
629 unsigned offset_db_fmt_cntl = 0, depth;
630
631 switch (rctx->framebuffer.zsbuf->texture->format) {
632 case PIPE_FORMAT_Z24X8_UNORM:
633 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
634 depth = -24;
635 offset_units *= 2.0f;
636 break;
637 case PIPE_FORMAT_Z32_FLOAT:
638 depth = -23;
639 offset_units *= 1.0f;
640 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
641 break;
642 case PIPE_FORMAT_Z16_UNORM:
643 depth = -16;
644 offset_units *= 4.0f;
645 break;
646 default:
647 return;
648 }
649 /* FIXME some of those reg can be computed with cso */
650 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
651 r600_pipe_state_add_reg(&state,
652 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
653 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
654 r600_pipe_state_add_reg(&state,
655 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
656 fui(offset_units), 0xFFFFFFFF, NULL);
657 r600_pipe_state_add_reg(&state,
658 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
659 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
660 r600_pipe_state_add_reg(&state,
661 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
662 fui(offset_units), 0xFFFFFFFF, NULL);
663 r600_pipe_state_add_reg(&state,
664 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
665 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
666 r600_context_pipe_state_set(&rctx->ctx, &state);
667 }
668 }
669
670 static void r600_set_blend_color(struct pipe_context *ctx,
671 const struct pipe_blend_color *state)
672 {
673 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
674 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
675
676 if (rstate == NULL)
677 return;
678
679 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
680 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
681 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
682 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
683 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
684 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
685 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
686 r600_context_pipe_state_set(&rctx->ctx, rstate);
687 }
688
689 static void *r600_create_blend_state(struct pipe_context *ctx,
690 const struct pipe_blend_state *state)
691 {
692 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
693 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
694 struct r600_pipe_state *rstate;
695 u32 color_control = 0, target_mask;
696
697 if (blend == NULL) {
698 return NULL;
699 }
700 rstate = &blend->rstate;
701
702 rstate->id = R600_PIPE_STATE_BLEND;
703
704 target_mask = 0;
705
706 /* R600 does not support per-MRT blends */
707 if (rctx->family > CHIP_R600)
708 color_control |= S_028808_PER_MRT_BLEND(1);
709 if (state->logicop_enable) {
710 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
711 } else {
712 color_control |= (0xcc << 16);
713 }
714 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
715 if (state->independent_blend_enable) {
716 for (int i = 0; i < 8; i++) {
717 if (state->rt[i].blend_enable) {
718 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
719 }
720 target_mask |= (state->rt[i].colormask << (4 * i));
721 }
722 } else {
723 for (int i = 0; i < 8; i++) {
724 if (state->rt[0].blend_enable) {
725 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
726 }
727 target_mask |= (state->rt[0].colormask << (4 * i));
728 }
729 }
730 blend->cb_target_mask = target_mask;
731 /* MULTIWRITE_ENABLE is controlled by r600_pipe_shader_ps(). */
732 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
733 color_control, 0xFFFFFFFD, NULL);
734
735 for (int i = 0; i < 8; i++) {
736 /* state->rt entries > 0 only written if independent blending */
737 const int j = state->independent_blend_enable ? i : 0;
738
739 unsigned eqRGB = state->rt[j].rgb_func;
740 unsigned srcRGB = state->rt[j].rgb_src_factor;
741 unsigned dstRGB = state->rt[j].rgb_dst_factor;
742
743 unsigned eqA = state->rt[j].alpha_func;
744 unsigned srcA = state->rt[j].alpha_src_factor;
745 unsigned dstA = state->rt[j].alpha_dst_factor;
746 uint32_t bc = 0;
747
748 if (!state->rt[j].blend_enable)
749 continue;
750
751 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
752 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
753 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
754
755 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
756 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
757 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
758 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
759 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
760 }
761
762 /* R600 does not support per-MRT blends */
763 if (rctx->family > CHIP_R600)
764 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
765 if (i == 0)
766 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
767 }
768 return rstate;
769 }
770
771 static void *r600_create_dsa_state(struct pipe_context *ctx,
772 const struct pipe_depth_stencil_alpha_state *state)
773 {
774 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
775 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
776 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
777 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
778 struct r600_pipe_state *rstate;
779
780 if (dsa == NULL) {
781 return NULL;
782 }
783
784 rstate = &dsa->rstate;
785
786 rstate->id = R600_PIPE_STATE_DSA;
787 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
788 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
789 stencil_ref_mask = 0;
790 stencil_ref_mask_bf = 0;
791 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
792 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
793 S_028800_ZFUNC(state->depth.func);
794
795 /* stencil */
796 if (state->stencil[0].enabled) {
797 db_depth_control |= S_028800_STENCIL_ENABLE(1);
798 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
799 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
800 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
801 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
802
803
804 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
805 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
806 if (state->stencil[1].enabled) {
807 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
808 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
809 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
810 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
811 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
812 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
813 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
814 }
815 }
816
817 /* alpha */
818 alpha_test_control = 0;
819 alpha_ref = 0;
820 if (state->alpha.enabled) {
821 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
822 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
823 alpha_ref = fui(state->alpha.ref_value);
824 }
825 dsa->alpha_ref = alpha_ref;
826
827 /* misc */
828 db_render_control = 0;
829 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
830 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
831 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
832 /* TODO db_render_override depends on query */
833 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
834 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
835 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
836 r600_pipe_state_add_reg(rstate,
837 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
838 0xFFFFFFFF & C_028430_STENCILREF, NULL);
839 r600_pipe_state_add_reg(rstate,
840 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
841 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
842 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
843 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
844 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
845 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
846 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
847 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
848 * r600_pipe_shader_ps().*/
849 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL);
850 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
851 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
852 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
853 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
854 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
855
856 return rstate;
857 }
858
859 static void *r600_create_rs_state(struct pipe_context *ctx,
860 const struct pipe_rasterizer_state *state)
861 {
862 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
863 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
864 struct r600_pipe_state *rstate;
865 unsigned tmp;
866 unsigned prov_vtx = 1, polygon_dual_mode;
867 unsigned clip_rule;
868
869 if (rs == NULL) {
870 return NULL;
871 }
872
873 rstate = &rs->rstate;
874 rs->clamp_vertex_color = state->clamp_vertex_color;
875 rs->clamp_fragment_color = state->clamp_fragment_color;
876 rs->flatshade = state->flatshade;
877 rs->sprite_coord_enable = state->sprite_coord_enable;
878
879 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
880 /* offset */
881 rs->offset_units = state->offset_units;
882 rs->offset_scale = state->offset_scale * 12.0f;
883
884 rstate->id = R600_PIPE_STATE_RASTERIZER;
885 if (state->flatshade_first)
886 prov_vtx = 0;
887 tmp = S_0286D4_FLAT_SHADE_ENA(1);
888 if (state->sprite_coord_enable) {
889 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
890 S_0286D4_PNT_SPRITE_OVRD_X(2) |
891 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
892 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
893 S_0286D4_PNT_SPRITE_OVRD_W(1);
894 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
895 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
896 }
897 }
898 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
899
900 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
901 state->fill_back != PIPE_POLYGON_MODE_FILL);
902 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
903 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
904 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
905 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
906 S_028814_FACE(!state->front_ccw) |
907 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
908 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
909 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
910 S_028814_POLY_MODE(polygon_dual_mode) |
911 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
912 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
913 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
914 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
915 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
916 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
917 /* point size 12.4 fixed point */
918 tmp = (unsigned)(state->point_size * 8.0);
919 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
920 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
921
922 tmp = (unsigned)state->line_width * 8;
923 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
924
925 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
926 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
927 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
928
929 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
930 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
931 0xFFFFFFFF, NULL);
932
933 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
934 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
935 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
936 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
937 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
938 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
939
940 return rstate;
941 }
942
943 static void *r600_create_sampler_state(struct pipe_context *ctx,
944 const struct pipe_sampler_state *state)
945 {
946 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
947 struct r600_pipe_state *rstate;
948 union util_color uc;
949 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
950
951 if (ss == NULL) {
952 return NULL;
953 }
954
955 ss->seamless_cube_map = state->seamless_cube_map;
956 rstate = &ss->rstate;
957 rstate->id = R600_PIPE_STATE_SAMPLER;
958 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
959 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
960 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
961 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
962 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
963 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
964 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
965 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
966 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
967 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
968 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
969 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
970 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
971 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
972 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
973 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
974 if (uc.ui) {
975 r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
976 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
977 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
978 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
979 }
980 return rstate;
981 }
982
983 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
984 struct pipe_resource *texture,
985 const struct pipe_sampler_view *state)
986 {
987 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
988 struct r600_pipe_resource_state *rstate;
989 const struct util_format_description *desc;
990 struct r600_resource_texture *tmp;
991 struct r600_resource *rbuffer;
992 unsigned format, endian;
993 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
994 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
995 struct r600_bo *bo[2];
996 unsigned width, height, depth, offset_level, last_level;
997
998 if (resource == NULL)
999 return NULL;
1000 rstate = &resource->state;
1001
1002 /* initialize base object */
1003 resource->base = *state;
1004 resource->base.texture = NULL;
1005 pipe_reference(NULL, &texture->reference);
1006 resource->base.texture = texture;
1007 resource->base.reference.count = 1;
1008 resource->base.context = ctx;
1009
1010 swizzle[0] = state->swizzle_r;
1011 swizzle[1] = state->swizzle_g;
1012 swizzle[2] = state->swizzle_b;
1013 swizzle[3] = state->swizzle_a;
1014 format = r600_translate_texformat(ctx->screen, state->format,
1015 swizzle,
1016 &word4, &yuv_format);
1017 if (format == ~0) {
1018 format = 0;
1019 }
1020 desc = util_format_description(state->format);
1021 if (desc == NULL) {
1022 R600_ERR("unknown format %d\n", state->format);
1023 }
1024 tmp = (struct r600_resource_texture *)texture;
1025 if (tmp->depth && !tmp->is_flushing_texture) {
1026 r600_texture_depth_flush(ctx, texture, TRUE);
1027 tmp = tmp->flushed_depth_texture;
1028 }
1029 endian = r600_colorformat_endian_swap(format);
1030
1031 if (tmp->force_int_type) {
1032 word4 &= C_038010_NUM_FORMAT_ALL;
1033 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1034 }
1035 rbuffer = &tmp->resource;
1036 bo[0] = rbuffer->bo;
1037 bo[1] = rbuffer->bo;
1038
1039 offset_level = state->u.tex.first_level;
1040 last_level = state->u.tex.last_level - offset_level;
1041 width = u_minify(texture->width0, offset_level);
1042 height = u_minify(texture->height0, offset_level);
1043 depth = u_minify(texture->depth0, offset_level);
1044
1045 pitch = align(tmp->pitch_in_blocks[offset_level] *
1046 util_format_get_blockwidth(state->format), 8);
1047 array_mode = tmp->array_mode[offset_level];
1048 tile_type = tmp->tile_type;
1049
1050 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1051 height = 1;
1052 depth = texture->array_size;
1053 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1054 depth = texture->array_size;
1055 }
1056
1057 rstate->bo[0] = bo[0];
1058 rstate->bo[1] = bo[1];
1059
1060 rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1061 S_038000_TILE_MODE(array_mode) |
1062 S_038000_TILE_TYPE(tile_type) |
1063 S_038000_PITCH((pitch / 8) - 1) |
1064 S_038000_TEX_WIDTH(width - 1));
1065 rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
1066 S_038004_TEX_DEPTH(depth - 1) |
1067 S_038004_DATA_FORMAT(format));
1068 rstate->val[2] = (tmp->offset[offset_level] + r600_bo_offset(bo[0])) >> 8;
1069 rstate->val[3] = (tmp->offset[offset_level+1] + r600_bo_offset(bo[1])) >> 8;
1070 rstate->val[4] = (word4 |
1071 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1072 S_038010_REQUEST_SIZE(1) |
1073 S_038010_ENDIAN_SWAP(endian) |
1074 S_038010_BASE_LEVEL(0));
1075 rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
1076 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1077 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1078 rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1079 S_038018_MAX_ANISO(4 /* max 16 samples */));
1080
1081 return &resource->base;
1082 }
1083
1084 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1085 struct pipe_sampler_view **views)
1086 {
1087 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1088 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1089
1090 for (int i = 0; i < count; i++) {
1091 if (resource[i]) {
1092 r600_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
1093 i + R600_MAX_CONST_BUFFERS);
1094 }
1095 }
1096 }
1097
1098 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1099 struct pipe_sampler_view **views)
1100 {
1101 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1102 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1103 int i;
1104 int has_depth = 0;
1105
1106 for (i = 0; i < count; i++) {
1107 if (&rctx->ps_samplers.views[i]->base != views[i]) {
1108 if (resource[i]) {
1109 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1110 has_depth = 1;
1111 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
1112 i + R600_MAX_CONST_BUFFERS);
1113 } else
1114 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
1115 i + R600_MAX_CONST_BUFFERS);
1116
1117 pipe_sampler_view_reference(
1118 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1119 views[i]);
1120
1121 } else {
1122 if (resource[i]) {
1123 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1124 has_depth = 1;
1125 }
1126 }
1127 }
1128 for (i = count; i < NUM_TEX_UNITS; i++) {
1129 if (rctx->ps_samplers.views[i]) {
1130 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
1131 i + R600_MAX_CONST_BUFFERS);
1132 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1133 }
1134 }
1135 rctx->have_depth_texture = has_depth;
1136 rctx->ps_samplers.n_views = count;
1137 }
1138
1139 static void r600_set_seamless_cubemap(struct r600_pipe_context *rctx, boolean enable)
1140 {
1141 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1142 if (rstate == NULL)
1143 return;
1144
1145 rstate->id = R600_PIPE_STATE_SEAMLESS_CUBEMAP;
1146 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1147 (enable ? 0 : S_009508_DISABLE_CUBE_WRAP(1)),
1148 1, NULL);
1149
1150 free(rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP]);
1151 rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP] = rstate;
1152 r600_context_pipe_state_set(&rctx->ctx, rstate);
1153 }
1154
1155 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1156 {
1157 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1158 struct r600_pipe_sampler_state **sstates = (struct r600_pipe_sampler_state **)states;
1159 int seamless = -1;
1160
1161 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1162 rctx->ps_samplers.n_samplers = count;
1163
1164 for (int i = 0; i < count; i++) {
1165 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, &sstates[i]->rstate, i);
1166
1167 if (sstates[i])
1168 seamless = sstates[i]->seamless_cube_map;
1169 }
1170
1171 if (seamless != -1)
1172 r600_set_seamless_cubemap(rctx, seamless);
1173 }
1174
1175 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1176 {
1177 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1178 struct r600_pipe_sampler_state **sstates = (struct r600_pipe_sampler_state **)states;
1179 int seamless = -1;
1180
1181 for (int i = 0; i < count; i++) {
1182 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, &sstates[i]->rstate, i);
1183
1184 if (sstates[i])
1185 seamless = sstates[i]->seamless_cube_map;
1186 }
1187
1188 if (seamless != -1)
1189 r600_set_seamless_cubemap(rctx, seamless);
1190 }
1191
1192 static void r600_set_clip_state(struct pipe_context *ctx,
1193 const struct pipe_clip_state *state)
1194 {
1195 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1196 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1197
1198 if (rstate == NULL)
1199 return;
1200
1201 rctx->clip = *state;
1202 rstate->id = R600_PIPE_STATE_CLIP;
1203 for (int i = 0; i < state->nr; i++) {
1204 r600_pipe_state_add_reg(rstate,
1205 R_028E20_PA_CL_UCP0_X + i * 16,
1206 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
1207 r600_pipe_state_add_reg(rstate,
1208 R_028E24_PA_CL_UCP0_Y + i * 16,
1209 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
1210 r600_pipe_state_add_reg(rstate,
1211 R_028E28_PA_CL_UCP0_Z + i * 16,
1212 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
1213 r600_pipe_state_add_reg(rstate,
1214 R_028E2C_PA_CL_UCP0_W + i * 16,
1215 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
1216 }
1217 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
1218 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
1219 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
1220 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
1221
1222 free(rctx->states[R600_PIPE_STATE_CLIP]);
1223 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1224 r600_context_pipe_state_set(&rctx->ctx, rstate);
1225 }
1226
1227 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1228 const struct pipe_poly_stipple *state)
1229 {
1230 }
1231
1232 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1233 {
1234 }
1235
1236 static void r600_set_scissor_state(struct pipe_context *ctx,
1237 const struct pipe_scissor_state *state)
1238 {
1239 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1240 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1241 u32 tl, br;
1242
1243 if (rstate == NULL)
1244 return;
1245
1246 rstate->id = R600_PIPE_STATE_SCISSOR;
1247 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1248 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1249 r600_pipe_state_add_reg(rstate,
1250 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1251 0xFFFFFFFF, NULL);
1252 r600_pipe_state_add_reg(rstate,
1253 R_028214_PA_SC_CLIPRECT_0_BR, br,
1254 0xFFFFFFFF, NULL);
1255 r600_pipe_state_add_reg(rstate,
1256 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1257 0xFFFFFFFF, NULL);
1258 r600_pipe_state_add_reg(rstate,
1259 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1260 0xFFFFFFFF, NULL);
1261 r600_pipe_state_add_reg(rstate,
1262 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1263 0xFFFFFFFF, NULL);
1264 r600_pipe_state_add_reg(rstate,
1265 R_028224_PA_SC_CLIPRECT_2_BR, br,
1266 0xFFFFFFFF, NULL);
1267 r600_pipe_state_add_reg(rstate,
1268 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1269 0xFFFFFFFF, NULL);
1270 r600_pipe_state_add_reg(rstate,
1271 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1272 0xFFFFFFFF, NULL);
1273
1274 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1275 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1276 r600_context_pipe_state_set(&rctx->ctx, rstate);
1277 }
1278
1279 static void r600_set_stencil_ref(struct pipe_context *ctx,
1280 const struct pipe_stencil_ref *state)
1281 {
1282 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1283 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1284 u32 tmp;
1285
1286 if (rstate == NULL)
1287 return;
1288
1289 rctx->stencil_ref = *state;
1290 rstate->id = R600_PIPE_STATE_STENCIL_REF;
1291 tmp = S_028430_STENCILREF(state->ref_value[0]);
1292 r600_pipe_state_add_reg(rstate,
1293 R_028430_DB_STENCILREFMASK, tmp,
1294 ~C_028430_STENCILREF, NULL);
1295 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
1296 r600_pipe_state_add_reg(rstate,
1297 R_028434_DB_STENCILREFMASK_BF, tmp,
1298 ~C_028434_STENCILREF_BF, NULL);
1299
1300 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
1301 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
1302 r600_context_pipe_state_set(&rctx->ctx, rstate);
1303 }
1304
1305 static void r600_set_viewport_state(struct pipe_context *ctx,
1306 const struct pipe_viewport_state *state)
1307 {
1308 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1309 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1310
1311 if (rstate == NULL)
1312 return;
1313
1314 rctx->viewport = *state;
1315 rstate->id = R600_PIPE_STATE_VIEWPORT;
1316 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
1317 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
1318 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
1319 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
1320 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
1321 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
1322 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
1323 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
1324 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
1325
1326 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1327 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1328 r600_context_pipe_state_set(&rctx->ctx, rstate);
1329 }
1330
1331 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1332 const struct pipe_framebuffer_state *state, int cb)
1333 {
1334 struct r600_resource_texture *rtex;
1335 struct r600_resource *rbuffer;
1336 struct r600_surface *surf;
1337 unsigned level = state->cbufs[cb]->u.tex.level;
1338 unsigned pitch, slice;
1339 unsigned color_info;
1340 unsigned format, swap, ntype, endian;
1341 unsigned offset;
1342 const struct util_format_description *desc;
1343 struct r600_bo *bo[3];
1344 int i;
1345
1346 surf = (struct r600_surface *)state->cbufs[cb];
1347 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1348
1349 if (rtex->depth)
1350 rctx->have_depth_fb = TRUE;
1351
1352 if (rtex->depth && !rtex->is_flushing_texture) {
1353 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1354 rtex = rtex->flushed_depth_texture;
1355 }
1356
1357 rbuffer = &rtex->resource;
1358 bo[0] = rbuffer->bo;
1359 bo[1] = rbuffer->bo;
1360 bo[2] = rbuffer->bo;
1361
1362 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1363 offset = r600_texture_get_offset(rtex,
1364 level, state->cbufs[cb]->u.tex.first_layer);
1365 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1366 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1367 desc = util_format_description(surf->base.format);
1368
1369 for (i = 0; i < 4; i++) {
1370 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1371 break;
1372 }
1373 }
1374 ntype = V_0280A0_NUMBER_UNORM;
1375 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1376 ntype = V_0280A0_NUMBER_SRGB;
1377 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED)
1378 ntype = V_0280A0_NUMBER_SNORM;
1379
1380 format = r600_translate_colorformat(surf->base.format);
1381 swap = r600_translate_colorswap(surf->base.format);
1382 if(rbuffer->b.b.b.usage == PIPE_USAGE_STAGING) {
1383 endian = ENDIAN_NONE;
1384 } else {
1385 endian = r600_colorformat_endian_swap(format);
1386 }
1387
1388 /* disable when gallium grows int textures */
1389 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
1390 ntype = V_0280A0_NUMBER_UINT;
1391
1392 color_info = S_0280A0_FORMAT(format) |
1393 S_0280A0_COMP_SWAP(swap) |
1394 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
1395 S_0280A0_BLEND_CLAMP(1) |
1396 S_0280A0_NUMBER_TYPE(ntype) |
1397 S_0280A0_ENDIAN(endian);
1398
1399 /* EXPORT_NORM is an optimzation that can be enabled for better
1400 * performance in certain cases
1401 */
1402 if (rctx->chip_class == R600) {
1403 /* EXPORT_NORM can be enabled if:
1404 * - 11-bit or smaller UNORM/SNORM/SRGB
1405 * - BLEND_CLAMP is enabled
1406 * - BLEND_FLOAT32 is disabled
1407 */
1408 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1409 (desc->channel[i].size < 12 &&
1410 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1411 ntype != V_0280A0_NUMBER_UINT &&
1412 ntype != V_0280A0_NUMBER_SINT) &&
1413 G_0280A0_BLEND_CLAMP(color_info) &&
1414 !G_0280A0_BLEND_FLOAT32(color_info))
1415 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1416 } else {
1417 /* EXPORT_NORM can be enabled if:
1418 * - 11-bit or smaller UNORM/SNORM/SRGB
1419 * - 16-bit or smaller FLOAT
1420 */
1421 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1422 ((desc->channel[i].size < 12 &&
1423 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1424 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1425 (desc->channel[i].size < 17 &&
1426 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT)))
1427 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1428 }
1429
1430 r600_pipe_state_add_reg(rstate,
1431 R_028040_CB_COLOR0_BASE + cb * 4,
1432 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
1433 r600_pipe_state_add_reg(rstate,
1434 R_0280A0_CB_COLOR0_INFO + cb * 4,
1435 color_info, 0xFFFFFFFF, bo[0]);
1436 r600_pipe_state_add_reg(rstate,
1437 R_028060_CB_COLOR0_SIZE + cb * 4,
1438 S_028060_PITCH_TILE_MAX(pitch) |
1439 S_028060_SLICE_TILE_MAX(slice),
1440 0xFFFFFFFF, NULL);
1441 r600_pipe_state_add_reg(rstate,
1442 R_028080_CB_COLOR0_VIEW + cb * 4,
1443 0x00000000, 0xFFFFFFFF, NULL);
1444 r600_pipe_state_add_reg(rstate,
1445 R_0280E0_CB_COLOR0_FRAG + cb * 4,
1446 r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]);
1447 r600_pipe_state_add_reg(rstate,
1448 R_0280C0_CB_COLOR0_TILE + cb * 4,
1449 r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]);
1450 r600_pipe_state_add_reg(rstate,
1451 R_028100_CB_COLOR0_MASK + cb * 4,
1452 0x00000000, 0xFFFFFFFF, NULL);
1453 }
1454
1455 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1456 const struct pipe_framebuffer_state *state)
1457 {
1458 struct r600_resource_texture *rtex;
1459 struct r600_resource *rbuffer;
1460 struct r600_surface *surf;
1461 unsigned level;
1462 unsigned pitch, slice, format;
1463 unsigned offset;
1464
1465 if (state->zsbuf == NULL)
1466 return;
1467
1468 level = state->zsbuf->u.tex.level;
1469
1470 surf = (struct r600_surface *)state->zsbuf;
1471 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1472
1473 rbuffer = &rtex->resource;
1474
1475 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1476 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
1477 level, state->zsbuf->u.tex.first_layer);
1478 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1479 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1480 format = r600_translate_dbformat(state->zsbuf->texture->format);
1481
1482 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
1483 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
1484 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1485 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1486 0xFFFFFFFF, NULL);
1487 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
1488 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
1489 S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format),
1490 0xFFFFFFFF, rbuffer->bo);
1491 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1492 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL);
1493 }
1494
1495 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1496 const struct pipe_framebuffer_state *state)
1497 {
1498 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1499 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1500 u32 shader_mask, tl, br, shader_control, target_mask;
1501
1502 if (rstate == NULL)
1503 return;
1504
1505 r600_context_flush_dest_caches(&rctx->ctx);
1506 rctx->ctx.num_dest_buffers = state->nr_cbufs;
1507
1508 /* unreference old buffer and reference new one */
1509 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1510
1511 util_copy_framebuffer_state(&rctx->framebuffer, state);
1512
1513 /* build states */
1514 rctx->have_depth_fb = 0;
1515 for (int i = 0; i < state->nr_cbufs; i++) {
1516 r600_cb(rctx, rstate, state, i);
1517 }
1518 if (state->zsbuf) {
1519 r600_db(rctx, rstate, state);
1520 rctx->ctx.num_dest_buffers++;
1521 }
1522
1523 target_mask = 0x00000000;
1524 target_mask = 0xFFFFFFFF;
1525 shader_mask = 0;
1526 shader_control = 0;
1527 for (int i = 0; i < state->nr_cbufs; i++) {
1528 target_mask ^= 0xf << (i * 4);
1529 shader_mask |= 0xf << (i * 4);
1530 shader_control |= 1 << i;
1531 }
1532 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1533 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1534
1535 r600_pipe_state_add_reg(rstate,
1536 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1537 0xFFFFFFFF, NULL);
1538 r600_pipe_state_add_reg(rstate,
1539 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1540 0xFFFFFFFF, NULL);
1541 r600_pipe_state_add_reg(rstate,
1542 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1543 0xFFFFFFFF, NULL);
1544 r600_pipe_state_add_reg(rstate,
1545 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1546 0xFFFFFFFF, NULL);
1547 r600_pipe_state_add_reg(rstate,
1548 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1549 0xFFFFFFFF, NULL);
1550 r600_pipe_state_add_reg(rstate,
1551 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1552 0xFFFFFFFF, NULL);
1553 r600_pipe_state_add_reg(rstate,
1554 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1555 0xFFFFFFFF, NULL);
1556 r600_pipe_state_add_reg(rstate,
1557 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1558 0xFFFFFFFF, NULL);
1559 r600_pipe_state_add_reg(rstate,
1560 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1561 0xFFFFFFFF, NULL);
1562 if (rctx->chip_class >= R700) {
1563 r600_pipe_state_add_reg(rstate,
1564 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1565 0xFFFFFFFF, NULL);
1566 }
1567
1568 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1569 shader_control, 0xFFFFFFFF, NULL);
1570 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1571 0x00000000, target_mask, NULL);
1572 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1573 shader_mask, 0xFFFFFFFF, NULL);
1574 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1575 0x00000000, 0xFFFFFFFF, NULL);
1576 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1577 0x00000000, 0xFFFFFFFF, NULL);
1578 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1579 0x00000000, 0xFFFFFFFF, NULL);
1580 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1581 0x01000000, 0xFFFFFFFF, NULL);
1582 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1583 0x00000000, 0xFFFFFFFF, NULL);
1584 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1585 0x000000FF, 0xFFFFFFFF, NULL);
1586 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1587 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1588 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1589 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1590
1591 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1592 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1593 r600_context_pipe_state_set(&rctx->ctx, rstate);
1594
1595 if (state->zsbuf) {
1596 r600_polygon_offset_update(rctx);
1597 }
1598 }
1599
1600 static void r600_texture_barrier(struct pipe_context *ctx)
1601 {
1602 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1603
1604 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
1605 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
1606 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
1607 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
1608 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1));
1609 }
1610
1611 void r600_init_state_functions(struct r600_pipe_context *rctx)
1612 {
1613 rctx->context.create_blend_state = r600_create_blend_state;
1614 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1615 rctx->context.create_fs_state = r600_create_shader_state;
1616 rctx->context.create_rasterizer_state = r600_create_rs_state;
1617 rctx->context.create_sampler_state = r600_create_sampler_state;
1618 rctx->context.create_sampler_view = r600_create_sampler_view;
1619 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1620 rctx->context.create_vs_state = r600_create_shader_state;
1621 rctx->context.bind_blend_state = r600_bind_blend_state;
1622 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1623 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
1624 rctx->context.bind_fs_state = r600_bind_ps_shader;
1625 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1626 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1627 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
1628 rctx->context.bind_vs_state = r600_bind_vs_shader;
1629 rctx->context.delete_blend_state = r600_delete_state;
1630 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1631 rctx->context.delete_fs_state = r600_delete_ps_shader;
1632 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1633 rctx->context.delete_sampler_state = r600_delete_state;
1634 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1635 rctx->context.delete_vs_state = r600_delete_vs_shader;
1636 rctx->context.set_blend_color = r600_set_blend_color;
1637 rctx->context.set_clip_state = r600_set_clip_state;
1638 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1639 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
1640 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1641 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1642 rctx->context.set_sample_mask = r600_set_sample_mask;
1643 rctx->context.set_scissor_state = r600_set_scissor_state;
1644 rctx->context.set_stencil_ref = r600_set_stencil_ref;
1645 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1646 rctx->context.set_index_buffer = r600_set_index_buffer;
1647 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
1648 rctx->context.set_viewport_state = r600_set_viewport_state;
1649 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1650 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1651 rctx->context.texture_barrier = r600_texture_barrier;
1652 }
1653
1654 void r600_adjust_gprs(struct r600_pipe_context *rctx)
1655 {
1656 struct r600_pipe_state rstate;
1657 unsigned num_ps_gprs = rctx->default_ps_gprs;
1658 unsigned num_vs_gprs = rctx->default_vs_gprs;
1659 unsigned tmp;
1660 int diff;
1661
1662 if (rctx->chip_class >= EVERGREEN)
1663 return;
1664
1665 if (!rctx->ps_shader && !rctx->vs_shader)
1666 return;
1667
1668 if (rctx->ps_shader->shader.bc.ngpr > rctx->default_ps_gprs)
1669 {
1670 diff = rctx->ps_shader->shader.bc.ngpr - rctx->default_ps_gprs;
1671 num_vs_gprs -= diff;
1672 num_ps_gprs += diff;
1673 }
1674
1675 if (rctx->vs_shader->shader.bc.ngpr > rctx->default_vs_gprs)
1676 {
1677 diff = rctx->vs_shader->shader.bc.ngpr - rctx->default_vs_gprs;
1678 num_ps_gprs -= diff;
1679 num_vs_gprs += diff;
1680 }
1681
1682 tmp = 0;
1683 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1684 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1685 rstate.nregs = 0;
1686 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0x0FFFFFFF, NULL);
1687
1688 r600_context_pipe_state_set(&rctx->ctx, &rstate);
1689 }
1690
1691 void r600_init_config(struct r600_pipe_context *rctx)
1692 {
1693 int ps_prio;
1694 int vs_prio;
1695 int gs_prio;
1696 int es_prio;
1697 int num_ps_gprs;
1698 int num_vs_gprs;
1699 int num_gs_gprs;
1700 int num_es_gprs;
1701 int num_temp_gprs;
1702 int num_ps_threads;
1703 int num_vs_threads;
1704 int num_gs_threads;
1705 int num_es_threads;
1706 int num_ps_stack_entries;
1707 int num_vs_stack_entries;
1708 int num_gs_stack_entries;
1709 int num_es_stack_entries;
1710 enum radeon_family family;
1711 struct r600_pipe_state *rstate = &rctx->config;
1712 u32 tmp;
1713
1714 family = rctx->family;
1715 ps_prio = 0;
1716 vs_prio = 1;
1717 gs_prio = 2;
1718 es_prio = 3;
1719 switch (family) {
1720 case CHIP_R600:
1721 num_ps_gprs = 192;
1722 num_vs_gprs = 56;
1723 num_temp_gprs = 4;
1724 num_gs_gprs = 0;
1725 num_es_gprs = 0;
1726 num_ps_threads = 136;
1727 num_vs_threads = 48;
1728 num_gs_threads = 4;
1729 num_es_threads = 4;
1730 num_ps_stack_entries = 128;
1731 num_vs_stack_entries = 128;
1732 num_gs_stack_entries = 0;
1733 num_es_stack_entries = 0;
1734 break;
1735 case CHIP_RV630:
1736 case CHIP_RV635:
1737 num_ps_gprs = 84;
1738 num_vs_gprs = 36;
1739 num_temp_gprs = 4;
1740 num_gs_gprs = 0;
1741 num_es_gprs = 0;
1742 num_ps_threads = 144;
1743 num_vs_threads = 40;
1744 num_gs_threads = 4;
1745 num_es_threads = 4;
1746 num_ps_stack_entries = 40;
1747 num_vs_stack_entries = 40;
1748 num_gs_stack_entries = 32;
1749 num_es_stack_entries = 16;
1750 break;
1751 case CHIP_RV610:
1752 case CHIP_RV620:
1753 case CHIP_RS780:
1754 case CHIP_RS880:
1755 default:
1756 num_ps_gprs = 84;
1757 num_vs_gprs = 36;
1758 num_temp_gprs = 4;
1759 num_gs_gprs = 0;
1760 num_es_gprs = 0;
1761 num_ps_threads = 136;
1762 num_vs_threads = 48;
1763 num_gs_threads = 4;
1764 num_es_threads = 4;
1765 num_ps_stack_entries = 40;
1766 num_vs_stack_entries = 40;
1767 num_gs_stack_entries = 32;
1768 num_es_stack_entries = 16;
1769 break;
1770 case CHIP_RV670:
1771 num_ps_gprs = 144;
1772 num_vs_gprs = 40;
1773 num_temp_gprs = 4;
1774 num_gs_gprs = 0;
1775 num_es_gprs = 0;
1776 num_ps_threads = 136;
1777 num_vs_threads = 48;
1778 num_gs_threads = 4;
1779 num_es_threads = 4;
1780 num_ps_stack_entries = 40;
1781 num_vs_stack_entries = 40;
1782 num_gs_stack_entries = 32;
1783 num_es_stack_entries = 16;
1784 break;
1785 case CHIP_RV770:
1786 num_ps_gprs = 192;
1787 num_vs_gprs = 56;
1788 num_temp_gprs = 4;
1789 num_gs_gprs = 0;
1790 num_es_gprs = 0;
1791 num_ps_threads = 188;
1792 num_vs_threads = 60;
1793 num_gs_threads = 0;
1794 num_es_threads = 0;
1795 num_ps_stack_entries = 256;
1796 num_vs_stack_entries = 256;
1797 num_gs_stack_entries = 0;
1798 num_es_stack_entries = 0;
1799 break;
1800 case CHIP_RV730:
1801 case CHIP_RV740:
1802 num_ps_gprs = 84;
1803 num_vs_gprs = 36;
1804 num_temp_gprs = 4;
1805 num_gs_gprs = 0;
1806 num_es_gprs = 0;
1807 num_ps_threads = 188;
1808 num_vs_threads = 60;
1809 num_gs_threads = 0;
1810 num_es_threads = 0;
1811 num_ps_stack_entries = 128;
1812 num_vs_stack_entries = 128;
1813 num_gs_stack_entries = 0;
1814 num_es_stack_entries = 0;
1815 break;
1816 case CHIP_RV710:
1817 num_ps_gprs = 192;
1818 num_vs_gprs = 56;
1819 num_temp_gprs = 4;
1820 num_gs_gprs = 0;
1821 num_es_gprs = 0;
1822 num_ps_threads = 144;
1823 num_vs_threads = 48;
1824 num_gs_threads = 0;
1825 num_es_threads = 0;
1826 num_ps_stack_entries = 128;
1827 num_vs_stack_entries = 128;
1828 num_gs_stack_entries = 0;
1829 num_es_stack_entries = 0;
1830 break;
1831 }
1832
1833 rctx->default_ps_gprs = num_ps_gprs;
1834 rctx->default_vs_gprs = num_vs_gprs;
1835
1836 rstate->id = R600_PIPE_STATE_CONFIG;
1837
1838 /* SQ_CONFIG */
1839 tmp = 0;
1840 switch (family) {
1841 case CHIP_RV610:
1842 case CHIP_RV620:
1843 case CHIP_RS780:
1844 case CHIP_RS880:
1845 case CHIP_RV710:
1846 break;
1847 default:
1848 tmp |= S_008C00_VC_ENABLE(1);
1849 break;
1850 }
1851 tmp |= S_008C00_DX9_CONSTS(0);
1852 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1853 tmp |= S_008C00_PS_PRIO(ps_prio);
1854 tmp |= S_008C00_VS_PRIO(vs_prio);
1855 tmp |= S_008C00_GS_PRIO(gs_prio);
1856 tmp |= S_008C00_ES_PRIO(es_prio);
1857 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1858
1859 /* SQ_GPR_RESOURCE_MGMT_1 */
1860 tmp = 0;
1861 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1862 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1863 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1864 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1865
1866 /* SQ_GPR_RESOURCE_MGMT_2 */
1867 tmp = 0;
1868 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1869 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1870 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1871
1872 /* SQ_THREAD_RESOURCE_MGMT */
1873 tmp = 0;
1874 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1875 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1876 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1877 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1878 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1879
1880 /* SQ_STACK_RESOURCE_MGMT_1 */
1881 tmp = 0;
1882 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1883 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1884 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1885
1886 /* SQ_STACK_RESOURCE_MGMT_2 */
1887 tmp = 0;
1888 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1889 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1890 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1891
1892 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1893 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1894
1895 if (rctx->chip_class >= R700) {
1896 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1897 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1898 S_009508_DISABLE_CUBE_ANISO(1) |
1899 S_009508_SYNC_GRADIENT(1) |
1900 S_009508_SYNC_WALKER(1) |
1901 S_009508_SYNC_ALIGNER(1), 0xFFFFFFFF, NULL);
1902 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1903 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1904 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1905 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL);
1906 } else {
1907 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1908 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1909 S_009508_DISABLE_CUBE_ANISO(1) |
1910 S_009508_SYNC_GRADIENT(1) |
1911 S_009508_SYNC_WALKER(1) |
1912 S_009508_SYNC_ALIGNER(1), 0xFFFFFFFF, NULL);
1913 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1914 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1915 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1916 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL);
1917 }
1918 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1919 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1920 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1921 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1922 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1923 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1924 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1925 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1926 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1927 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1928 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1929 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1930 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1931 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
1932 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
1933 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1934 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1935 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1936 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1937 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1938 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1939 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
1940 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1941 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1942 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1943 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
1944
1945 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1946 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
1947 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
1948 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
1949 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
1950 r600_context_pipe_state_set(&rctx->ctx, rstate);
1951 }
1952
1953 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1954 {
1955 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1956 struct r600_pipe_state *rstate = &shader->rstate;
1957 struct r600_shader *rshader = &shader->shader;
1958 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
1959 int pos_index = -1, face_index = -1;
1960
1961 rstate->nregs = 0;
1962
1963 for (i = 0; i < rshader->ninput; i++) {
1964 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1965 pos_index = i;
1966 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1967 face_index = i;
1968 }
1969
1970 db_shader_control = 0;
1971 for (i = 0; i < rshader->noutput; i++) {
1972 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1973 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1974 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1975 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1);
1976 }
1977 if (rshader->uses_kill)
1978 db_shader_control |= S_02880C_KILL_ENABLE(1);
1979
1980 exports_ps = 0;
1981 num_cout = 0;
1982 for (i = 0; i < rshader->noutput; i++) {
1983 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1984 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1985 exports_ps |= 1;
1986 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1987 num_cout++;
1988 }
1989 }
1990 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
1991 if (!exports_ps) {
1992 /* always at least export 1 component per pixel */
1993 exports_ps = 2;
1994 }
1995
1996 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
1997 S_0286CC_PERSP_GRADIENT_ENA(1);
1998 spi_input_z = 0;
1999 if (pos_index != -1) {
2000 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2001 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2002 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2003 S_0286CC_BARYC_SAMPLE_CNTL(1));
2004 spi_input_z |= 1;
2005 }
2006
2007 spi_ps_in_control_1 = 0;
2008 if (face_index != -1) {
2009 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2010 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2011 }
2012
2013 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
2014 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL);
2015 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
2016 r600_pipe_state_add_reg(rstate,
2017 R_028840_SQ_PGM_START_PS,
2018 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
2019 r600_pipe_state_add_reg(rstate,
2020 R_028850_SQ_PGM_RESOURCES_PS,
2021 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2022 S_028868_STACK_SIZE(rshader->bc.nstack),
2023 0xFFFFFFFF, NULL);
2024 r600_pipe_state_add_reg(rstate,
2025 R_028854_SQ_PGM_EXPORTS_PS,
2026 exports_ps, 0xFFFFFFFF, NULL);
2027 r600_pipe_state_add_reg(rstate,
2028 R_0288CC_SQ_PGM_CF_OFFSET_PS,
2029 0x00000000, 0xFFFFFFFF, NULL);
2030 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
2031 S_028808_MULTIWRITE_ENABLE(!!rshader->fs_write_all),
2032 S_028808_MULTIWRITE_ENABLE(1),
2033 NULL);
2034 /* only set some bits here, the other bits are set in the dsa state */
2035 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2036 db_shader_control,
2037 S_02880C_Z_EXPORT_ENABLE(1) |
2038 S_02880C_STENCIL_REF_EXPORT_ENABLE(1) |
2039 S_02880C_KILL_ENABLE(1),
2040 NULL);
2041
2042 r600_pipe_state_add_reg(rstate,
2043 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
2044 0xFFFFFFFF, NULL);
2045 }
2046
2047 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2048 {
2049 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2050 struct r600_pipe_state *rstate = &shader->rstate;
2051 struct r600_shader *rshader = &shader->shader;
2052 unsigned spi_vs_out_id[10];
2053 unsigned i, tmp;
2054
2055 /* clear previous register */
2056 rstate->nregs = 0;
2057
2058 /* so far never got proper semantic id from tgsi */
2059 /* FIXME better to move this in config things so they get emited
2060 * only one time per cs
2061 */
2062 for (i = 0; i < 10; i++) {
2063 spi_vs_out_id[i] = 0;
2064 }
2065 for (i = 0; i < 32; i++) {
2066 tmp = i << ((i & 3) * 8);
2067 spi_vs_out_id[i / 4] |= tmp;
2068 }
2069 for (i = 0; i < 10; i++) {
2070 r600_pipe_state_add_reg(rstate,
2071 R_028614_SPI_VS_OUT_ID_0 + i * 4,
2072 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
2073 }
2074
2075 r600_pipe_state_add_reg(rstate,
2076 R_0286C4_SPI_VS_OUT_CONFIG,
2077 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
2078 0xFFFFFFFF, NULL);
2079 r600_pipe_state_add_reg(rstate,
2080 R_028868_SQ_PGM_RESOURCES_VS,
2081 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2082 S_028868_STACK_SIZE(rshader->bc.nstack),
2083 0xFFFFFFFF, NULL);
2084 r600_pipe_state_add_reg(rstate,
2085 R_0288D0_SQ_PGM_CF_OFFSET_VS,
2086 0x00000000, 0xFFFFFFFF, NULL);
2087 r600_pipe_state_add_reg(rstate,
2088 R_028858_SQ_PGM_START_VS,
2089 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
2090
2091 r600_pipe_state_add_reg(rstate,
2092 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2093 0xFFFFFFFF, NULL);
2094 }
2095
2096 void r600_fetch_shader(struct pipe_context *ctx,
2097 struct r600_vertex_element *ve)
2098 {
2099 struct r600_pipe_state *rstate;
2100 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2101
2102 rstate = &ve->rstate;
2103 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2104 rstate->nregs = 0;
2105 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
2106 0x00000000, 0xFFFFFFFF, NULL);
2107 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
2108 0x00000000, 0xFFFFFFFF, NULL);
2109 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
2110 r600_bo_offset(ve->fetch_shader) >> 8,
2111 0xFFFFFFFF, ve->fetch_shader);
2112 }
2113
2114 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
2115 {
2116 struct pipe_depth_stencil_alpha_state dsa;
2117 struct r600_pipe_state *rstate;
2118 boolean quirk = false;
2119
2120 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2121 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2122 quirk = true;
2123
2124 memset(&dsa, 0, sizeof(dsa));
2125
2126 if (quirk) {
2127 dsa.depth.enabled = 1;
2128 dsa.depth.func = PIPE_FUNC_LEQUAL;
2129 dsa.stencil[0].enabled = 1;
2130 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2131 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2132 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2133 dsa.stencil[0].writemask = 0xff;
2134 }
2135
2136 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2137 r600_pipe_state_add_reg(rstate,
2138 R_02880C_DB_SHADER_CONTROL,
2139 0x0,
2140 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
2141 r600_pipe_state_add_reg(rstate,
2142 R_028D0C_DB_RENDER_CONTROL,
2143 S_028D0C_DEPTH_COPY_ENABLE(1) |
2144 S_028D0C_STENCIL_COPY_ENABLE(1) |
2145 S_028D0C_COPY_CENTROID(1),
2146 S_028D0C_DEPTH_COPY_ENABLE(1) |
2147 S_028D0C_STENCIL_COPY_ENABLE(1) |
2148 S_028D0C_COPY_CENTROID(1), NULL);
2149 return rstate;
2150 }
2151
2152 void r600_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
2153 struct r600_pipe_resource_state *rstate)
2154 {
2155 rstate->id = R600_PIPE_STATE_RESOURCE;
2156
2157 rstate->bo[0] = NULL;
2158 rstate->val[0] = 0;
2159 rstate->val[1] = 0;
2160 rstate->val[2] = 0;
2161 rstate->val[3] = 0;
2162 rstate->val[4] = 0;
2163 rstate->val[5] = 0;
2164 rstate->val[6] = 0xc0000000;
2165 }
2166
2167 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
2168 struct r600_resource *rbuffer,
2169 unsigned offset, unsigned stride)
2170 {
2171 rstate->val[0] = offset;
2172 rstate->bo[0] = rbuffer->bo;
2173 rstate->val[1] = rbuffer->bo_size - offset - 1;
2174 rstate->val[2] = S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
2175 S_038008_STRIDE(stride);
2176 }