src/gallium/drivers/r600/r600_state.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #include <stdio.h>
  27 #include <util/u_inlines.h>
  28 #include <util/u_format.h>
  29 #include <util/u_memory.h>
  30 #include "r600_screen.h"
  31 #include "r600_texture.h"
  32 #include "r600_context.h"
  33 #include "r600d.h"
  34
  35
  36 static void r600_delete_state(struct pipe_context *ctx, void *state)
  37 {
  38         struct radeon_state *rstate = state;
  39
  40         radeon_state_decref(rstate);
  41 }
  42
  43 static void *r600_create_blend_state(struct pipe_context *ctx,
  44                                         const struct pipe_blend_state *state)
  45 {
  46         struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
  47         struct radeon_state *rstate;
  48
  49         rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
  50         if (rstate == NULL)
  51                 return NULL;
  52         rstate->states[R600_BLEND__CB_BLEND_RED] = 0x00000000;
  53         rstate->states[R600_BLEND__CB_BLEND_GREEN] = 0x00000000;
  54         rstate->states[R600_BLEND__CB_BLEND_BLUE] = 0x00000000;
  55         rstate->states[R600_BLEND__CB_BLEND_ALPHA] = 0x00000000;
  56         rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00010001;
  57         rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
  58         rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
  59         rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
  60         rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
  61         rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
  62         rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
  63         rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
  64         rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
  65         if (radeon_state_pm4(rstate)) {
  66                 radeon_state_decref(rstate);
  67                 return NULL;
  68         }
  69         return rstate;
  70 }
  71
  72 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
  73 {
  74         struct r600_context *rctx = (struct r600_context*)ctx;
  75         radeon_draw_set(rctx->draw, state);
  76 }
  77
  78 static void r600_set_blend_color(struct pipe_context *ctx,
  79                                         const struct pipe_blend_color *color)
  80 {
  81 }
  82
  83 static void r600_set_clip_state(struct pipe_context *ctx,
  84                                 const struct pipe_clip_state *state)
  85 {
  86 }
  87
  88 static void r600_set_framebuffer_state(struct pipe_context *ctx,
  89                                         const struct pipe_framebuffer_state *state)
  90 {
  91         struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
  92         struct r600_context *rctx = (struct r600_context*)ctx;
  93         struct r600_texture *rtex;
  94         struct r600_buffer *rbuffer;
  95         struct radeon_state *rstate;
  96         unsigned level = state->cbufs[0]->level;
  97         unsigned pitch, slice;
  98
  99         rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, R600_CB0);
 100         if (rstate == NULL)
 101                 return;
 102         rtex = (struct r600_texture*)state->cbufs[0]->texture;
 103         rbuffer = (struct r600_buffer*)rtex->buffer;
 104         rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 105         rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 106         rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 107         rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 108         rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
 109         rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
 110         rstate->nbo = 3;
 111         pitch = rtex->pitch[level] / 8 - 1;
 112         slice = rtex->pitch[level] * state->cbufs[0]->height / 64 - 1;
 113         rstate->states[R600_CB0__CB_COLOR0_BASE] = 0x00000000;
 114         rstate->states[R600_CB0__CB_COLOR0_INFO] = 0x08110068;
 115         rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
 116                                                 S_028060_SLICE_TILE_MAX(slice);
 117         rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
 118         rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
 119         rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
 120         rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
 121         if (radeon_state_pm4(rstate)) {
 122                 radeon_state_decref(rstate);
 123                 return;
 124         }
 125         radeon_draw_set_new(rctx->draw, rstate);
 126         rctx->db = radeon_state_decref(rctx->db);
 127         rctx->db = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
 128         rctx->db->bo[0] = radeon_bo_incref(rscreen->rw, rstate->bo[0]);
 129         rctx->db->nbo = 1;
 130         rctx->db->placement[0] = RADEON_GEM_DOMAIN_GTT;
 131 }
 132
 133 static void *r600_create_fs_state(struct pipe_context *ctx,
 134                                         const struct pipe_shader_state *shader)
 135 {
 136         return r600_pipe_shader_create(ctx, C_PROGRAM_TYPE_FS, shader->tokens);
 137 }
 138
 139 static void r600_bind_fs_state(struct pipe_context *ctx, void *state)
 140 {
 141         struct r600_context *rctx = (struct r600_context*)ctx;
 142
 143         rctx->ps_shader = state;
 144 }
 145
 146 static void *r600_create_vs_state(struct pipe_context *ctx,
 147                                         const struct pipe_shader_state *shader)
 148 {
 149         return r600_pipe_shader_create(ctx, C_PROGRAM_TYPE_VS, shader->tokens);
 150 }
 151
 152 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
 153 {
 154         struct r600_context *rctx = (struct r600_context*)ctx;
 155
 156         rctx->vs_shader = state;
 157 }
 158
 159 static void r600_set_polygon_stipple(struct pipe_context *ctx,
 160                                          const struct pipe_poly_stipple *state)
 161 {
 162 }
 163
 164 static void *r600_create_rs_state(struct pipe_context *ctx,
 165                                         const struct pipe_rasterizer_state *state)
 166 {
 167         struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
 168         struct r600_context *rctx = (struct r600_context*)ctx;
 169         struct radeon_state *rstate;
 170
 171         rctx->flat_shade = state->flatshade;
 172         rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
 173         if (rstate == NULL)
 174                 return NULL;
 175         rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
 176         rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0x00000000;
 177         rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080000;
 178         rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] = 0x00000000;
 179         rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
 180         rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = 0x00080008;
 181         rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x00000000;
 182         rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
 183         rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
 184         rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
 185         rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
 186         rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
 187         rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
 188         rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
 189         rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
 190         rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = 0x00000000;
 191         rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
 192         rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = 0x00000000;
 193         rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = 0x00000000;
 194         rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = 0x00000000;
 195         rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = 0x00000000;
 196         if (radeon_state_pm4(rstate)) {
 197                 radeon_state_decref(rstate);
 198                 return NULL;
 199         }
 200         return rstate;
 201 }
 202
 203 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 204 {
 205         struct r600_context *rctx = (struct r600_context*)ctx;
 206         radeon_draw_set(rctx->draw, state);
 207 }
 208
 209 static void *r600_create_sampler_state(struct pipe_context *ctx,
 210                                         const struct pipe_sampler_state *state)
 211 {
 212         return NULL;
 213 }
 214
 215 static void r600_bind_sampler_states(struct pipe_context *ctx,
 216                                         unsigned count, void **states)
 217 {
 218 }
 219
 220 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
 221                                                           struct pipe_resource *texture,
 222                                                           const struct pipe_sampler_view *templ)
 223 {
 224         struct pipe_sampler_view *view = CALLOC_STRUCT(pipe_sampler_view);
 225
 226         *view = *templ;
 227         return view;
 228 }
 229
 230 static void r600_sampler_view_destroy(struct pipe_context *ctx,
 231                                       struct pipe_sampler_view *view)
 232 {
 233         FREE(view);
 234 }
 235
 236 static void r600_set_fragment_sampler_views(struct pipe_context *ctx,
 237                                             unsigned count,
 238                                             struct pipe_sampler_view **views)
 239 {
 240 }
 241
 242 static void r600_set_vertex_sampler_views(struct pipe_context *ctx,
 243                                           unsigned count,
 244                                           struct pipe_sampler_view **views)
 245 {
 246 }
 247
 248 static void r600_set_scissor_state(struct pipe_context *ctx,
 249                                         const struct pipe_scissor_state *state)
 250 {
 251         struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
 252         struct r600_context *rctx = (struct r600_context*)ctx;
 253         struct radeon_state *rstate;
 254         u32 tl, br;
 255
 256         tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
 257         br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
 258         rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
 259         if (rstate == NULL)
 260                 return;
 261         rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
 262         rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
 263         rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
 264         rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
 265         rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
 266         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
 267         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
 268         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
 269         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
 270         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
 271         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
 272         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
 273         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
 274         rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
 275         rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
 276         rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
 277         rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
 278         rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
 279         rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
 280         if (radeon_state_pm4(rstate)) {
 281                 radeon_state_decref(rstate);
 282                 return;
 283         }
 284         radeon_draw_set_new(rctx->draw, rstate);
 285 }
 286
 287 static void r600_set_viewport_state(struct pipe_context *ctx,
 288                                         const struct pipe_viewport_state *state)
 289 {
 290         struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
 291         struct r600_context *rctx = (struct r600_context*)ctx;
 292         struct radeon_state *rstate;
 293
 294         rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
 295         if (rstate == NULL)
 296                 return;
 297         rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
 298         rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
 299         rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = r600_float_to_u32(state->scale[0]);
 300         rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = r600_float_to_u32(state->scale[1]);
 301         rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = r600_float_to_u32(state->scale[2]);
 302         rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = r600_float_to_u32(state->translate[0]);
 303         rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = r600_float_to_u32(state->translate[1]);
 304         rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = r600_float_to_u32(state->translate[2]);
 305         rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
 306         if (radeon_state_pm4(rstate)) {
 307                 radeon_state_decref(rstate);
 308                 return;
 309         }
 310         radeon_draw_set_new(rctx->draw, rstate);
 311 }
 312
 313 static void r600_set_vertex_buffers(struct pipe_context *ctx,
 314                                         unsigned count,
 315                                         const struct pipe_vertex_buffer *buffers)
 316 {
 317         struct r600_context *rctx = (struct r600_context*)ctx;
 318
 319         memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
 320         rctx->nvertex_buffer = count;
 321 }
 322
 323 /* XXX move this to a more appropriate place */
 324 struct r600_vertex_elements_state
 325 {
 326         unsigned count;
 327         struct pipe_vertex_element elements[32];
 328 };
 329
 330 static void *r600_create_vertex_elements_state(struct pipe_context *ctx,
 331                                                unsigned count,
 332                                                const struct pipe_vertex_element *elements)
 333 {
 334         struct r600_vertex_elements_state *v = CALLOC_STRUCT(r600_vertex_elements_state);
 335
 336         assert(count < 32);
 337         v->count = count;
 338         memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
 339         return v;
 340 }
 341
 342 static void r600_bind_vertex_elements_state(struct pipe_context *ctx, void *state)
 343 {
 344         struct r600_context *rctx = (struct r600_context*)ctx;
 345         struct r600_vertex_elements_state *v = (struct r600_vertex_elements_state*)state;
 346
 347         memcpy(rctx->vertex_element, v->elements, v->count * sizeof(struct pipe_vertex_element));
 348         rctx->nvertex_element = v->count;
 349 }
 350
 351 static void r600_delete_vertex_elements_state(struct pipe_context *ctx, void *state)
 352 {
 353         FREE(state);
 354 }
 355
 356 static void *r600_create_dsa_state(struct pipe_context *ctx,
 357                                         const struct pipe_depth_stencil_alpha_state *state)
 358 {
 359         struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
 360         struct radeon_state *rstate;
 361
 362         rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
 363         if (rstate == NULL)
 364                 return NULL;
 365         rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
 366         rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
 367         rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = 0x00000000;
 368         rstate->states[R600_DSA__DB_STENCILREFMASK] = 0xFFFFFF00;
 369         rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = 0xFFFFFF00;
 370         rstate->states[R600_DSA__SX_ALPHA_REF] = 0x00000000;
 371         rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
 372         rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
 373         rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
 374         rstate->states[R600_DSA__DB_DEPTH_CONTROL] = 0x00700700;
 375         rstate->states[R600_DSA__DB_SHADER_CONTROL] = 0x00000210;
 376         rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060;
 377         rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
 378         rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
 379         rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
 380         rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
 381         if (radeon_state_pm4(rstate)) {
 382                 radeon_state_decref(rstate);
 383                 return NULL;
 384         }
 385         return rstate;
 386 }
 387
 388 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 389 {
 390         struct r600_context *rctx = (struct r600_context*)ctx;
 391         radeon_draw_set(rctx->draw, state);
 392 }
 393
 394 static void r600_set_constant_buffer(struct pipe_context *ctx,
 395                                      uint shader, uint index,
 396                                      struct pipe_resource *buffer)
 397 {
 398         struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
 399         struct r600_context *rctx = (struct r600_context*)ctx;
 400         unsigned nconstant = 0, i, type, id;
 401         struct radeon_state *rstate;
 402         struct pipe_transfer *transfer;
 403         u32 *ptr;
 404
 405         switch (shader) {
 406         case PIPE_SHADER_VERTEX:
 407                 id = R600_VS_CONSTANT;
 408                 type = R600_VS_CONSTANT_TYPE;
 409                 break;
 410         case PIPE_SHADER_FRAGMENT:
 411                 id = R600_PS_CONSTANT;
 412                 type = R600_PS_CONSTANT_TYPE;
 413                 break;
 414         default:
 415                 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, shader);
 416                 return;
 417         }
 418         if (buffer && buffer->width0 > 0) {
 419                 nconstant = buffer->width0 / 16;
 420                 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
 421                 if (ptr == NULL)
 422                         return;
 423                 for (i = 0; i < nconstant; i++) {
 424                         rstate = radeon_state(rscreen->rw, type, id + i);
 425                         if (rstate == NULL)
 426                                 return;
 427                         rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
 428                         rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
 429                         rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
 430                         rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
 431                         if (radeon_state_pm4(rstate))
 432                                 return;
 433                         if (radeon_draw_set_new(rctx->draw, rstate))
 434                                 return;
 435                 }
 436                 pipe_buffer_unmap(ctx, buffer, transfer);
 437         }
 438 }
 439
 440 static void r600_set_stencil_ref(struct pipe_context *ctx,
 441                                 const struct pipe_stencil_ref *sr)
 442 {
 443         struct r600_context *rctx = (struct r600_context*)ctx;
 444         rctx->stencil_ref = *sr;
 445 }
 446
 447 void r600_init_state_functions(struct r600_context *rctx)
 448 {
 449         rctx->context.create_blend_state = r600_create_blend_state;
 450         rctx->context.bind_blend_state = r600_bind_blend_state;
 451         rctx->context.delete_blend_state = r600_delete_state;
 452         rctx->context.set_blend_color = r600_set_blend_color;
 453         rctx->context.set_clip_state = r600_set_clip_state;
 454         rctx->context.set_constant_buffer = r600_set_constant_buffer;
 455         rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
 456         rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
 457         rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
 458         rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
 459         rctx->context.create_fs_state = r600_create_fs_state;
 460         rctx->context.bind_fs_state = r600_bind_fs_state;
 461         rctx->context.delete_fs_state = r600_delete_state;
 462         rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
 463         rctx->context.create_rasterizer_state = r600_create_rs_state;
 464         rctx->context.bind_rasterizer_state = r600_bind_rs_state;
 465         rctx->context.delete_rasterizer_state = r600_delete_state;
 466         rctx->context.create_sampler_state = r600_create_sampler_state;
 467         rctx->context.bind_fragment_sampler_states = r600_bind_sampler_states;
 468         rctx->context.bind_vertex_sampler_states = r600_bind_sampler_states;
 469         rctx->context.delete_sampler_state = r600_delete_state;
 470         rctx->context.create_sampler_view = r600_create_sampler_view;
 471         rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
 472         rctx->context.set_fragment_sampler_views = r600_set_fragment_sampler_views;
 473         rctx->context.set_vertex_sampler_views = r600_set_vertex_sampler_views;
 474         rctx->context.set_scissor_state = r600_set_scissor_state;
 475         rctx->context.set_viewport_state = r600_set_viewport_state;
 476         rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
 477         rctx->context.create_vertex_elements_state = r600_create_vertex_elements_state;
 478         rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements_state;
 479         rctx->context.delete_vertex_elements_state = r600_delete_vertex_elements_state;
 480         rctx->context.create_vs_state = r600_create_vs_state;
 481         rctx->context.bind_vs_state = r600_bind_vs_state;
 482         rctx->context.delete_vs_state = r600_delete_state;
 483         rctx->context.set_stencil_ref = r600_set_stencil_ref;
 484 }