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r600g: fix texture array filtering
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include "pipe/p_defines.h"
30 #include "pipe/p_state.h"
31 #include "pipe/p_context.h"
32 #include "tgsi/tgsi_scan.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_util.h"
35 #include "util/u_double_list.h"
36 #include "util/u_pack_color.h"
37 #include "util/u_memory.h"
38 #include "util/u_inlines.h"
39 #include "util/u_framebuffer.h"
40 #include "util/u_transfer.h"
41 #include "pipebuffer/pb_buffer.h"
42 #include "r600.h"
43 #include "r600d.h"
44 #include "r600_resource.h"
45 #include "r600_shader.h"
46 #include "r600_pipe.h"
47 #include "r600_formats.h"
48
49 static uint32_t r600_translate_blend_function(int blend_func)
50 {
51 switch (blend_func) {
52 case PIPE_BLEND_ADD:
53 return V_028804_COMB_DST_PLUS_SRC;
54 case PIPE_BLEND_SUBTRACT:
55 return V_028804_COMB_SRC_MINUS_DST;
56 case PIPE_BLEND_REVERSE_SUBTRACT:
57 return V_028804_COMB_DST_MINUS_SRC;
58 case PIPE_BLEND_MIN:
59 return V_028804_COMB_MIN_DST_SRC;
60 case PIPE_BLEND_MAX:
61 return V_028804_COMB_MAX_DST_SRC;
62 default:
63 R600_ERR("Unknown blend function %d\n", blend_func);
64 assert(0);
65 break;
66 }
67 return 0;
68 }
69
70 static uint32_t r600_translate_blend_factor(int blend_fact)
71 {
72 switch (blend_fact) {
73 case PIPE_BLENDFACTOR_ONE:
74 return V_028804_BLEND_ONE;
75 case PIPE_BLENDFACTOR_SRC_COLOR:
76 return V_028804_BLEND_SRC_COLOR;
77 case PIPE_BLENDFACTOR_SRC_ALPHA:
78 return V_028804_BLEND_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_DST_ALPHA:
80 return V_028804_BLEND_DST_ALPHA;
81 case PIPE_BLENDFACTOR_DST_COLOR:
82 return V_028804_BLEND_DST_COLOR;
83 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
84 return V_028804_BLEND_SRC_ALPHA_SATURATE;
85 case PIPE_BLENDFACTOR_CONST_COLOR:
86 return V_028804_BLEND_CONST_COLOR;
87 case PIPE_BLENDFACTOR_CONST_ALPHA:
88 return V_028804_BLEND_CONST_ALPHA;
89 case PIPE_BLENDFACTOR_ZERO:
90 return V_028804_BLEND_ZERO;
91 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
92 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
94 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
95 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
96 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
97 case PIPE_BLENDFACTOR_INV_DST_COLOR:
98 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
99 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
100 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
101 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
102 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
103 case PIPE_BLENDFACTOR_SRC1_COLOR:
104 return V_028804_BLEND_SRC1_COLOR;
105 case PIPE_BLENDFACTOR_SRC1_ALPHA:
106 return V_028804_BLEND_SRC1_ALPHA;
107 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
108 return V_028804_BLEND_INV_SRC1_COLOR;
109 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
110 return V_028804_BLEND_INV_SRC1_ALPHA;
111 default:
112 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
113 assert(0);
114 break;
115 }
116 return 0;
117 }
118
119 static uint32_t r600_translate_stencil_op(int s_op)
120 {
121 switch (s_op) {
122 case PIPE_STENCIL_OP_KEEP:
123 return V_028800_STENCIL_KEEP;
124 case PIPE_STENCIL_OP_ZERO:
125 return V_028800_STENCIL_ZERO;
126 case PIPE_STENCIL_OP_REPLACE:
127 return V_028800_STENCIL_REPLACE;
128 case PIPE_STENCIL_OP_INCR:
129 return V_028800_STENCIL_INCR;
130 case PIPE_STENCIL_OP_DECR:
131 return V_028800_STENCIL_DECR;
132 case PIPE_STENCIL_OP_INCR_WRAP:
133 return V_028800_STENCIL_INCR_WRAP;
134 case PIPE_STENCIL_OP_DECR_WRAP:
135 return V_028800_STENCIL_DECR_WRAP;
136 case PIPE_STENCIL_OP_INVERT:
137 return V_028800_STENCIL_INVERT;
138 default:
139 R600_ERR("Unknown stencil op %d", s_op);
140 assert(0);
141 break;
142 }
143 return 0;
144 }
145
146 static uint32_t r600_translate_fill(uint32_t func)
147 {
148 switch(func) {
149 case PIPE_POLYGON_MODE_FILL:
150 return 2;
151 case PIPE_POLYGON_MODE_LINE:
152 return 1;
153 case PIPE_POLYGON_MODE_POINT:
154 return 0;
155 default:
156 assert(0);
157 return 0;
158 }
159 }
160
161 /* translates straight */
162 static uint32_t r600_translate_ds_func(int func)
163 {
164 return func;
165 }
166
167 static unsigned r600_tex_wrap(unsigned wrap)
168 {
169 switch (wrap) {
170 default:
171 case PIPE_TEX_WRAP_REPEAT:
172 return V_03C000_SQ_TEX_WRAP;
173 case PIPE_TEX_WRAP_CLAMP:
174 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
175 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
176 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
177 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
178 return V_03C000_SQ_TEX_CLAMP_BORDER;
179 case PIPE_TEX_WRAP_MIRROR_REPEAT:
180 return V_03C000_SQ_TEX_MIRROR;
181 case PIPE_TEX_WRAP_MIRROR_CLAMP:
182 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
183 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
184 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
185 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
186 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
187 }
188 }
189
190 static unsigned r600_tex_filter(unsigned filter)
191 {
192 switch (filter) {
193 default:
194 case PIPE_TEX_FILTER_NEAREST:
195 return V_03C000_SQ_TEX_XY_FILTER_POINT;
196 case PIPE_TEX_FILTER_LINEAR:
197 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
198 }
199 }
200
201 static unsigned r600_tex_mipfilter(unsigned filter)
202 {
203 switch (filter) {
204 case PIPE_TEX_MIPFILTER_NEAREST:
205 return V_03C000_SQ_TEX_Z_FILTER_POINT;
206 case PIPE_TEX_MIPFILTER_LINEAR:
207 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
208 default:
209 case PIPE_TEX_MIPFILTER_NONE:
210 return V_03C000_SQ_TEX_Z_FILTER_NONE;
211 }
212 }
213
214 static unsigned r600_tex_compare(unsigned compare)
215 {
216 switch (compare) {
217 default:
218 case PIPE_FUNC_NEVER:
219 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
220 case PIPE_FUNC_LESS:
221 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
222 case PIPE_FUNC_EQUAL:
223 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
224 case PIPE_FUNC_LEQUAL:
225 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
226 case PIPE_FUNC_GREATER:
227 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
228 case PIPE_FUNC_NOTEQUAL:
229 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
230 case PIPE_FUNC_GEQUAL:
231 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
232 case PIPE_FUNC_ALWAYS:
233 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
234 }
235 }
236
237 static unsigned r600_tex_dim(unsigned dim)
238 {
239 switch (dim) {
240 default:
241 case PIPE_TEXTURE_1D:
242 return V_038000_SQ_TEX_DIM_1D;
243 case PIPE_TEXTURE_1D_ARRAY:
244 return V_038000_SQ_TEX_DIM_1D_ARRAY;
245 case PIPE_TEXTURE_2D:
246 case PIPE_TEXTURE_RECT:
247 return V_038000_SQ_TEX_DIM_2D;
248 case PIPE_TEXTURE_2D_ARRAY:
249 return V_038000_SQ_TEX_DIM_2D_ARRAY;
250 case PIPE_TEXTURE_3D:
251 return V_038000_SQ_TEX_DIM_3D;
252 case PIPE_TEXTURE_CUBE:
253 return V_038000_SQ_TEX_DIM_CUBEMAP;
254 }
255 }
256
257 static uint32_t r600_translate_dbformat(enum pipe_format format)
258 {
259 switch (format) {
260 case PIPE_FORMAT_Z16_UNORM:
261 return V_028010_DEPTH_16;
262 case PIPE_FORMAT_Z24X8_UNORM:
263 return V_028010_DEPTH_X8_24;
264 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
265 return V_028010_DEPTH_8_24;
266 case PIPE_FORMAT_Z32_FLOAT:
267 return V_028010_DEPTH_32_FLOAT;
268 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
269 return V_028010_DEPTH_X24_8_32_FLOAT;
270 default:
271 return ~0U;
272 }
273 }
274
275 static uint32_t r600_translate_colorswap(enum pipe_format format)
276 {
277 switch (format) {
278 /* 8-bit buffers. */
279 case PIPE_FORMAT_A8_UNORM:
280 case PIPE_FORMAT_R4A4_UNORM:
281 return V_0280A0_SWAP_ALT_REV;
282 case PIPE_FORMAT_I8_UNORM:
283 case PIPE_FORMAT_L8_UNORM:
284 case PIPE_FORMAT_L8_SRGB:
285 case PIPE_FORMAT_R8_UNORM:
286 case PIPE_FORMAT_R8_SNORM:
287 return V_0280A0_SWAP_STD;
288
289 case PIPE_FORMAT_L4A4_UNORM:
290 case PIPE_FORMAT_A4R4_UNORM:
291 return V_0280A0_SWAP_ALT;
292
293 /* 16-bit buffers. */
294 case PIPE_FORMAT_B5G6R5_UNORM:
295 return V_0280A0_SWAP_STD_REV;
296
297 case PIPE_FORMAT_B5G5R5A1_UNORM:
298 case PIPE_FORMAT_B5G5R5X1_UNORM:
299 return V_0280A0_SWAP_ALT;
300
301 case PIPE_FORMAT_B4G4R4A4_UNORM:
302 case PIPE_FORMAT_B4G4R4X4_UNORM:
303 return V_0280A0_SWAP_ALT;
304
305 case PIPE_FORMAT_Z16_UNORM:
306 return V_0280A0_SWAP_STD;
307
308 case PIPE_FORMAT_L8A8_UNORM:
309 case PIPE_FORMAT_L8A8_SRGB:
310 return V_0280A0_SWAP_ALT;
311 case PIPE_FORMAT_R8G8_UNORM:
312 return V_0280A0_SWAP_STD;
313
314 case PIPE_FORMAT_R16_UNORM:
315 case PIPE_FORMAT_R16_FLOAT:
316 return V_0280A0_SWAP_STD;
317
318 /* 32-bit buffers. */
319
320 case PIPE_FORMAT_A8B8G8R8_SRGB:
321 return V_0280A0_SWAP_STD_REV;
322 case PIPE_FORMAT_B8G8R8A8_SRGB:
323 return V_0280A0_SWAP_ALT;
324
325 case PIPE_FORMAT_B8G8R8A8_UNORM:
326 case PIPE_FORMAT_B8G8R8X8_UNORM:
327 return V_0280A0_SWAP_ALT;
328
329 case PIPE_FORMAT_A8R8G8B8_UNORM:
330 case PIPE_FORMAT_X8R8G8B8_UNORM:
331 return V_0280A0_SWAP_ALT_REV;
332 case PIPE_FORMAT_R8G8B8A8_SNORM:
333 case PIPE_FORMAT_R8G8B8A8_UNORM:
334 case PIPE_FORMAT_R8G8B8X8_UNORM:
335 return V_0280A0_SWAP_STD;
336
337 case PIPE_FORMAT_A8B8G8R8_UNORM:
338 case PIPE_FORMAT_X8B8G8R8_UNORM:
339 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
340 return V_0280A0_SWAP_STD_REV;
341
342 case PIPE_FORMAT_Z24X8_UNORM:
343 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
344 return V_0280A0_SWAP_STD;
345
346 case PIPE_FORMAT_X8Z24_UNORM:
347 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
348 return V_0280A0_SWAP_STD;
349
350 case PIPE_FORMAT_R10G10B10A2_UNORM:
351 case PIPE_FORMAT_R10G10B10X2_SNORM:
352 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
353 return V_0280A0_SWAP_STD;
354
355 case PIPE_FORMAT_B10G10R10A2_UNORM:
356 return V_0280A0_SWAP_ALT;
357
358 case PIPE_FORMAT_R11G11B10_FLOAT:
359 case PIPE_FORMAT_R16G16_UNORM:
360 case PIPE_FORMAT_R16G16_FLOAT:
361 case PIPE_FORMAT_R32_FLOAT:
362 case PIPE_FORMAT_Z32_FLOAT:
363 return V_0280A0_SWAP_STD;
364
365 /* 64-bit buffers. */
366 case PIPE_FORMAT_R32G32_FLOAT:
367 case PIPE_FORMAT_R16G16B16A16_UNORM:
368 case PIPE_FORMAT_R16G16B16A16_SNORM:
369 case PIPE_FORMAT_R16G16B16A16_FLOAT:
370 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
371
372 /* 128-bit buffers. */
373 case PIPE_FORMAT_R32G32B32A32_FLOAT:
374 case PIPE_FORMAT_R32G32B32A32_SNORM:
375 case PIPE_FORMAT_R32G32B32A32_UNORM:
376 return V_0280A0_SWAP_STD;
377 default:
378 R600_ERR("unsupported colorswap format %d\n", format);
379 return ~0U;
380 }
381 return ~0U;
382 }
383
384 static uint32_t r600_translate_colorformat(enum pipe_format format)
385 {
386 switch (format) {
387 case PIPE_FORMAT_L4A4_UNORM:
388 case PIPE_FORMAT_R4A4_UNORM:
389 case PIPE_FORMAT_A4R4_UNORM:
390 return V_0280A0_COLOR_4_4;
391
392 /* 8-bit buffers. */
393 case PIPE_FORMAT_A8_UNORM:
394 case PIPE_FORMAT_I8_UNORM:
395 case PIPE_FORMAT_L8_UNORM:
396 case PIPE_FORMAT_L8_SRGB:
397 case PIPE_FORMAT_R8_UNORM:
398 case PIPE_FORMAT_R8_SNORM:
399 return V_0280A0_COLOR_8;
400
401 /* 16-bit buffers. */
402 case PIPE_FORMAT_B5G6R5_UNORM:
403 return V_0280A0_COLOR_5_6_5;
404
405 case PIPE_FORMAT_B5G5R5A1_UNORM:
406 case PIPE_FORMAT_B5G5R5X1_UNORM:
407 return V_0280A0_COLOR_1_5_5_5;
408
409 case PIPE_FORMAT_B4G4R4A4_UNORM:
410 case PIPE_FORMAT_B4G4R4X4_UNORM:
411 return V_0280A0_COLOR_4_4_4_4;
412
413 case PIPE_FORMAT_Z16_UNORM:
414 return V_0280A0_COLOR_16;
415
416 case PIPE_FORMAT_L8A8_UNORM:
417 case PIPE_FORMAT_L8A8_SRGB:
418 case PIPE_FORMAT_R8G8_UNORM:
419 return V_0280A0_COLOR_8_8;
420
421 case PIPE_FORMAT_R16_UNORM:
422 return V_0280A0_COLOR_16;
423
424 case PIPE_FORMAT_R16_FLOAT:
425 return V_0280A0_COLOR_16_FLOAT;
426
427 /* 32-bit buffers. */
428 case PIPE_FORMAT_A8B8G8R8_SRGB:
429 case PIPE_FORMAT_A8B8G8R8_UNORM:
430 case PIPE_FORMAT_A8R8G8B8_UNORM:
431 case PIPE_FORMAT_B8G8R8A8_SRGB:
432 case PIPE_FORMAT_B8G8R8A8_UNORM:
433 case PIPE_FORMAT_B8G8R8X8_UNORM:
434 case PIPE_FORMAT_R8G8B8A8_SNORM:
435 case PIPE_FORMAT_R8G8B8A8_UNORM:
436 case PIPE_FORMAT_R8G8B8X8_UNORM:
437 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
438 case PIPE_FORMAT_X8B8G8R8_UNORM:
439 case PIPE_FORMAT_X8R8G8B8_UNORM:
440 case PIPE_FORMAT_R8G8B8_UNORM:
441 return V_0280A0_COLOR_8_8_8_8;
442
443 case PIPE_FORMAT_R10G10B10A2_UNORM:
444 case PIPE_FORMAT_R10G10B10X2_SNORM:
445 case PIPE_FORMAT_B10G10R10A2_UNORM:
446 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
447 return V_0280A0_COLOR_2_10_10_10;
448
449 case PIPE_FORMAT_Z24X8_UNORM:
450 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
451 return V_0280A0_COLOR_8_24;
452
453 case PIPE_FORMAT_X8Z24_UNORM:
454 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
455 return V_0280A0_COLOR_24_8;
456
457 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
458 return V_0280A0_COLOR_X24_8_32_FLOAT;
459
460 case PIPE_FORMAT_R32_FLOAT:
461 case PIPE_FORMAT_Z32_FLOAT:
462 return V_0280A0_COLOR_32_FLOAT;
463
464 case PIPE_FORMAT_R16G16_FLOAT:
465 return V_0280A0_COLOR_16_16_FLOAT;
466
467 case PIPE_FORMAT_R16G16_SSCALED:
468 case PIPE_FORMAT_R16G16_UNORM:
469 return V_0280A0_COLOR_16_16;
470
471 case PIPE_FORMAT_R11G11B10_FLOAT:
472 return V_0280A0_COLOR_10_11_11_FLOAT;
473
474 /* 64-bit buffers. */
475 case PIPE_FORMAT_R16G16B16_USCALED:
476 case PIPE_FORMAT_R16G16B16A16_USCALED:
477 case PIPE_FORMAT_R16G16B16_SSCALED:
478 case PIPE_FORMAT_R16G16B16A16_SSCALED:
479 case PIPE_FORMAT_R16G16B16A16_UNORM:
480 case PIPE_FORMAT_R16G16B16A16_SNORM:
481 return V_0280A0_COLOR_16_16_16_16;
482
483 case PIPE_FORMAT_R16G16B16_FLOAT:
484 case PIPE_FORMAT_R16G16B16A16_FLOAT:
485 return V_0280A0_COLOR_16_16_16_16_FLOAT;
486
487 case PIPE_FORMAT_R32G32_FLOAT:
488 return V_0280A0_COLOR_32_32_FLOAT;
489
490 case PIPE_FORMAT_R32G32_USCALED:
491 case PIPE_FORMAT_R32G32_SSCALED:
492 return V_0280A0_COLOR_32_32;
493
494 /* 96-bit buffers. */
495 case PIPE_FORMAT_R32G32B32_FLOAT:
496 return V_0280A0_COLOR_32_32_32_FLOAT;
497
498 /* 128-bit buffers. */
499 case PIPE_FORMAT_R32G32B32A32_FLOAT:
500 return V_0280A0_COLOR_32_32_32_32_FLOAT;
501 case PIPE_FORMAT_R32G32B32A32_SNORM:
502 case PIPE_FORMAT_R32G32B32A32_UNORM:
503 return V_0280A0_COLOR_32_32_32_32;
504
505 /* YUV buffers. */
506 case PIPE_FORMAT_UYVY:
507 case PIPE_FORMAT_YUYV:
508 default:
509 return ~0U; /* Unsupported. */
510 }
511 }
512
513 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
514 {
515 if (R600_BIG_ENDIAN) {
516 switch(colorformat) {
517 case V_0280A0_COLOR_4_4:
518 return ENDIAN_NONE;
519
520 /* 8-bit buffers. */
521 case V_0280A0_COLOR_8:
522 return ENDIAN_NONE;
523
524 /* 16-bit buffers. */
525 case V_0280A0_COLOR_5_6_5:
526 case V_0280A0_COLOR_1_5_5_5:
527 case V_0280A0_COLOR_4_4_4_4:
528 case V_0280A0_COLOR_16:
529 case V_0280A0_COLOR_8_8:
530 return ENDIAN_8IN16;
531
532 /* 32-bit buffers. */
533 case V_0280A0_COLOR_8_8_8_8:
534 case V_0280A0_COLOR_2_10_10_10:
535 case V_0280A0_COLOR_8_24:
536 case V_0280A0_COLOR_24_8:
537 case V_0280A0_COLOR_32_FLOAT:
538 case V_0280A0_COLOR_16_16_FLOAT:
539 case V_0280A0_COLOR_16_16:
540 return ENDIAN_8IN32;
541
542 /* 64-bit buffers. */
543 case V_0280A0_COLOR_16_16_16_16:
544 case V_0280A0_COLOR_16_16_16_16_FLOAT:
545 return ENDIAN_8IN16;
546
547 case V_0280A0_COLOR_32_32_FLOAT:
548 case V_0280A0_COLOR_32_32:
549 case V_0280A0_COLOR_X24_8_32_FLOAT:
550 return ENDIAN_8IN32;
551
552 /* 128-bit buffers. */
553 case V_0280A0_COLOR_32_32_32_FLOAT:
554 case V_0280A0_COLOR_32_32_32_32_FLOAT:
555 case V_0280A0_COLOR_32_32_32_32:
556 return ENDIAN_8IN32;
557 default:
558 return ENDIAN_NONE; /* Unsupported. */
559 }
560 } else {
561 return ENDIAN_NONE;
562 }
563 }
564
565 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
566 {
567 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
568 }
569
570 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
571 {
572 return r600_translate_colorformat(format) != ~0U &&
573 r600_translate_colorswap(format) != ~0U;
574 }
575
576 static bool r600_is_zs_format_supported(enum pipe_format format)
577 {
578 return r600_translate_dbformat(format) != ~0U;
579 }
580
581 boolean r600_is_format_supported(struct pipe_screen *screen,
582 enum pipe_format format,
583 enum pipe_texture_target target,
584 unsigned sample_count,
585 unsigned usage)
586 {
587 unsigned retval = 0;
588
589 if (target >= PIPE_MAX_TEXTURE_TYPES) {
590 R600_ERR("r600: unsupported texture type %d\n", target);
591 return FALSE;
592 }
593
594 if (!util_format_is_supported(format, usage))
595 return FALSE;
596
597 /* Multisample */
598 if (sample_count > 1)
599 return FALSE;
600
601 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
602 r600_is_sampler_format_supported(screen, format)) {
603 retval |= PIPE_BIND_SAMPLER_VIEW;
604 }
605
606 if ((usage & (PIPE_BIND_RENDER_TARGET |
607 PIPE_BIND_DISPLAY_TARGET |
608 PIPE_BIND_SCANOUT |
609 PIPE_BIND_SHARED)) &&
610 r600_is_colorbuffer_format_supported(format)) {
611 retval |= usage &
612 (PIPE_BIND_RENDER_TARGET |
613 PIPE_BIND_DISPLAY_TARGET |
614 PIPE_BIND_SCANOUT |
615 PIPE_BIND_SHARED);
616 }
617
618 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
619 r600_is_zs_format_supported(format)) {
620 retval |= PIPE_BIND_DEPTH_STENCIL;
621 }
622
623 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
624 r600_is_vertex_format_supported(format)) {
625 retval |= PIPE_BIND_VERTEX_BUFFER;
626 }
627
628 if (usage & PIPE_BIND_TRANSFER_READ)
629 retval |= PIPE_BIND_TRANSFER_READ;
630 if (usage & PIPE_BIND_TRANSFER_WRITE)
631 retval |= PIPE_BIND_TRANSFER_WRITE;
632
633 return retval == usage;
634 }
635
636 void r600_polygon_offset_update(struct r600_pipe_context *rctx)
637 {
638 struct r600_pipe_state state;
639
640 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
641 state.nregs = 0;
642 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
643 float offset_units = rctx->rasterizer->offset_units;
644 unsigned offset_db_fmt_cntl = 0, depth;
645
646 switch (rctx->framebuffer.zsbuf->texture->format) {
647 case PIPE_FORMAT_Z24X8_UNORM:
648 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
649 depth = -24;
650 offset_units *= 2.0f;
651 break;
652 case PIPE_FORMAT_Z32_FLOAT:
653 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
654 depth = -23;
655 offset_units *= 1.0f;
656 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
657 break;
658 case PIPE_FORMAT_Z16_UNORM:
659 depth = -16;
660 offset_units *= 4.0f;
661 break;
662 default:
663 return;
664 }
665 /* FIXME some of those reg can be computed with cso */
666 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
667 r600_pipe_state_add_reg(&state,
668 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
669 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
670 r600_pipe_state_add_reg(&state,
671 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
672 fui(offset_units), 0xFFFFFFFF, NULL, 0);
673 r600_pipe_state_add_reg(&state,
674 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
675 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL, 0);
676 r600_pipe_state_add_reg(&state,
677 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
678 fui(offset_units), 0xFFFFFFFF, NULL, 0);
679 r600_pipe_state_add_reg(&state,
680 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
681 offset_db_fmt_cntl, 0xFFFFFFFF, NULL, 0);
682 r600_context_pipe_state_set(&rctx->ctx, &state);
683 }
684 }
685
686 static void r600_set_blend_color(struct pipe_context *ctx,
687 const struct pipe_blend_color *state)
688 {
689 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
690 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
691
692 if (rstate == NULL)
693 return;
694
695 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
696 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL, 0);
697 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL, 0);
698 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL, 0);
699 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL, 0);
700 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
701 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
702 r600_context_pipe_state_set(&rctx->ctx, rstate);
703 }
704
705 static void *r600_create_blend_state(struct pipe_context *ctx,
706 const struct pipe_blend_state *state)
707 {
708 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
709 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
710 struct r600_pipe_state *rstate;
711 u32 color_control = 0, target_mask;
712
713 if (blend == NULL) {
714 return NULL;
715 }
716 rstate = &blend->rstate;
717
718 rstate->id = R600_PIPE_STATE_BLEND;
719
720 target_mask = 0;
721
722 /* R600 does not support per-MRT blends */
723 if (rctx->family > CHIP_R600)
724 color_control |= S_028808_PER_MRT_BLEND(1);
725 if (state->logicop_enable) {
726 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
727 } else {
728 color_control |= (0xcc << 16);
729 }
730 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
731 if (state->independent_blend_enable) {
732 for (int i = 0; i < 8; i++) {
733 if (state->rt[i].blend_enable) {
734 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
735 }
736 target_mask |= (state->rt[i].colormask << (4 * i));
737 }
738 } else {
739 for (int i = 0; i < 8; i++) {
740 if (state->rt[0].blend_enable) {
741 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
742 }
743 target_mask |= (state->rt[0].colormask << (4 * i));
744 }
745 }
746 blend->cb_target_mask = target_mask;
747 /* MULTIWRITE_ENABLE is controlled by r600_pipe_shader_ps(). */
748 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
749 color_control, 0xFFFFFFFD, NULL, 0);
750
751 for (int i = 0; i < 8; i++) {
752 /* state->rt entries > 0 only written if independent blending */
753 const int j = state->independent_blend_enable ? i : 0;
754
755 unsigned eqRGB = state->rt[j].rgb_func;
756 unsigned srcRGB = state->rt[j].rgb_src_factor;
757 unsigned dstRGB = state->rt[j].rgb_dst_factor;
758
759 unsigned eqA = state->rt[j].alpha_func;
760 unsigned srcA = state->rt[j].alpha_src_factor;
761 unsigned dstA = state->rt[j].alpha_dst_factor;
762 uint32_t bc = 0;
763
764 if (!state->rt[j].blend_enable)
765 continue;
766
767 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
768 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
769 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
770
771 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
772 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
773 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
774 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
775 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
776 }
777
778 /* R600 does not support per-MRT blends */
779 if (rctx->family > CHIP_R600)
780 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL, 0);
781 if (i == 0)
782 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL, 0);
783 }
784 return rstate;
785 }
786
787 static void *r600_create_dsa_state(struct pipe_context *ctx,
788 const struct pipe_depth_stencil_alpha_state *state)
789 {
790 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
791 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
792 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
793 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
794 struct r600_pipe_state *rstate;
795
796 if (dsa == NULL) {
797 return NULL;
798 }
799
800 rstate = &dsa->rstate;
801
802 rstate->id = R600_PIPE_STATE_DSA;
803 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
804 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
805 stencil_ref_mask = 0;
806 stencil_ref_mask_bf = 0;
807 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
808 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
809 S_028800_ZFUNC(state->depth.func);
810
811 /* stencil */
812 if (state->stencil[0].enabled) {
813 db_depth_control |= S_028800_STENCIL_ENABLE(1);
814 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
815 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
816 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
817 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
818
819
820 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
821 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
822 if (state->stencil[1].enabled) {
823 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
824 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
825 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
826 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
827 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
828 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
829 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
830 }
831 }
832
833 /* alpha */
834 alpha_test_control = 0;
835 alpha_ref = 0;
836 if (state->alpha.enabled) {
837 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
838 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
839 alpha_ref = fui(state->alpha.ref_value);
840 }
841 dsa->alpha_ref = alpha_ref;
842
843 /* misc */
844 db_render_control = 0;
845 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
846 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
847 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
848 /* TODO db_render_override depends on query */
849 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL, 0);
850 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL, 0);
851 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL, 0);
852 r600_pipe_state_add_reg(rstate,
853 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
854 0xFFFFFFFF & C_028430_STENCILREF, NULL, 0);
855 r600_pipe_state_add_reg(rstate,
856 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
857 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL, 0);
858 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL, 0);
859 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL, 0);
860 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
861 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL, 0);
862 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
863 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
864 * r600_pipe_shader_ps().*/
865 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL, 0);
866 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL, 0);
867 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL, 0);
868 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL, 0);
869 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL, 0);
870 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL, 0);
871
872 return rstate;
873 }
874
875 static void *r600_create_rs_state(struct pipe_context *ctx,
876 const struct pipe_rasterizer_state *state)
877 {
878 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
879 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
880 struct r600_pipe_state *rstate;
881 unsigned tmp;
882 unsigned prov_vtx = 1, polygon_dual_mode;
883 unsigned clip_rule;
884
885 if (rs == NULL) {
886 return NULL;
887 }
888
889 rstate = &rs->rstate;
890 rs->clamp_vertex_color = state->clamp_vertex_color;
891 rs->clamp_fragment_color = state->clamp_fragment_color;
892 rs->flatshade = state->flatshade;
893 rs->sprite_coord_enable = state->sprite_coord_enable;
894
895 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
896 /* offset */
897 rs->offset_units = state->offset_units;
898 rs->offset_scale = state->offset_scale * 12.0f;
899
900 rstate->id = R600_PIPE_STATE_RASTERIZER;
901 if (state->flatshade_first)
902 prov_vtx = 0;
903 tmp = S_0286D4_FLAT_SHADE_ENA(1);
904 if (state->sprite_coord_enable) {
905 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
906 S_0286D4_PNT_SPRITE_OVRD_X(2) |
907 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
908 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
909 S_0286D4_PNT_SPRITE_OVRD_W(1);
910 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
911 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
912 }
913 }
914 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL, 0);
915
916 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
917 state->fill_back != PIPE_POLYGON_MODE_FILL);
918 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
919 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
920 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
921 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
922 S_028814_FACE(!state->front_ccw) |
923 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
924 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
925 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
926 S_028814_POLY_MODE(polygon_dual_mode) |
927 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
928 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL, 0);
929 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
930 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
931 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL, 0);
932 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
933 /* point size 12.4 fixed point */
934 tmp = (unsigned)(state->point_size * 8.0);
935 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
936 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL, 0);
937
938 tmp = (unsigned)state->line_width * 8;
939 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
940
941 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL, 0);
942 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
943 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL, 0);
944
945 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
946 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
947 0xFFFFFFFF, NULL, 0);
948
949 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
950 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
951 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
952 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL, 0);
953 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL, 0);
954 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL, 0);
955
956 return rstate;
957 }
958
959 static void *r600_create_sampler_state(struct pipe_context *ctx,
960 const struct pipe_sampler_state *state)
961 {
962 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
963 struct r600_pipe_state *rstate;
964 union util_color uc;
965 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
966
967 if (ss == NULL) {
968 return NULL;
969 }
970
971 ss->seamless_cube_map = state->seamless_cube_map;
972 rstate = &ss->rstate;
973 rstate->id = R600_PIPE_STATE_SAMPLER;
974 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
975 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
976 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
977 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
978 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
979 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
980 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
981 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
982 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
983 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
984 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL, 0);
985 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
986 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
987 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
988 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL, 0);
989 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL, 0);
990 if (uc.ui) {
991 r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL, 0);
992 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL, 0);
993 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL, 0);
994 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL, 0);
995 }
996 return rstate;
997 }
998
999 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
1000 struct pipe_resource *texture,
1001 const struct pipe_sampler_view *state)
1002 {
1003 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1004 struct r600_pipe_resource_state *rstate;
1005 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1006 struct r600_resource *rbuffer;
1007 unsigned format, endian;
1008 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1009 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1010 struct r600_bo *bo[2];
1011 unsigned width, height, depth, offset_level, last_level;
1012
1013 if (view == NULL)
1014 return NULL;
1015 rstate = &view->state;
1016
1017 /* initialize base object */
1018 view->base = *state;
1019 view->base.texture = NULL;
1020 pipe_reference(NULL, &texture->reference);
1021 view->base.texture = texture;
1022 view->base.reference.count = 1;
1023 view->base.context = ctx;
1024
1025 swizzle[0] = state->swizzle_r;
1026 swizzle[1] = state->swizzle_g;
1027 swizzle[2] = state->swizzle_b;
1028 swizzle[3] = state->swizzle_a;
1029
1030 format = r600_translate_texformat(ctx->screen, state->format,
1031 swizzle,
1032 &word4, &yuv_format);
1033 if (format == ~0) {
1034 format = 0;
1035 }
1036
1037 if (tmp->depth && !tmp->is_flushing_texture) {
1038 r600_texture_depth_flush(ctx, texture, TRUE);
1039 tmp = tmp->flushed_depth_texture;
1040 }
1041
1042 endian = r600_colorformat_endian_swap(format);
1043
1044 if (tmp->force_int_type) {
1045 word4 &= C_038010_NUM_FORMAT_ALL;
1046 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1047 }
1048
1049 rbuffer = &tmp->resource;
1050 bo[0] = rbuffer->bo;
1051 bo[1] = rbuffer->bo;
1052
1053 offset_level = state->u.tex.first_level;
1054 last_level = state->u.tex.last_level - offset_level;
1055 width = u_minify(texture->width0, offset_level);
1056 height = u_minify(texture->height0, offset_level);
1057 depth = u_minify(texture->depth0, offset_level);
1058
1059 pitch = align(tmp->pitch_in_blocks[offset_level] *
1060 util_format_get_blockwidth(state->format), 8);
1061 array_mode = tmp->array_mode[offset_level];
1062 tile_type = tmp->tile_type;
1063
1064 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1065 height = 1;
1066 depth = texture->array_size;
1067 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1068 depth = texture->array_size;
1069 }
1070
1071 rstate->bo[0] = bo[0];
1072 rstate->bo[1] = bo[1];
1073 rstate->bo_usage[0] = RADEON_USAGE_READ;
1074 rstate->bo_usage[1] = RADEON_USAGE_READ;
1075
1076 rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1077 S_038000_TILE_MODE(array_mode) |
1078 S_038000_TILE_TYPE(tile_type) |
1079 S_038000_PITCH((pitch / 8) - 1) |
1080 S_038000_TEX_WIDTH(width - 1));
1081 rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
1082 S_038004_TEX_DEPTH(depth - 1) |
1083 S_038004_DATA_FORMAT(format));
1084 rstate->val[2] = tmp->offset[offset_level] >> 8;
1085 rstate->val[3] = tmp->offset[offset_level+1] >> 8;
1086 rstate->val[4] = (word4 |
1087 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1088 S_038010_REQUEST_SIZE(1) |
1089 S_038010_ENDIAN_SWAP(endian) |
1090 S_038010_BASE_LEVEL(0));
1091 rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
1092 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1093 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1094 rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1095 S_038018_MAX_ANISO(4 /* max 16 samples */));
1096
1097 return &view->base;
1098 }
1099
1100 static void r600_set_sampler_views(struct r600_pipe_context *rctx,
1101 struct r600_textures_info *dst,
1102 unsigned count,
1103 struct pipe_sampler_view **views,
1104 void (*set_resource)(struct r600_context*, struct r600_pipe_resource_state*, unsigned))
1105 {
1106 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
1107 unsigned i;
1108
1109 for (i = 0; i < count; i++) {
1110 if (rviews[i]) {
1111 if (((struct r600_resource_texture *)rviews[i]->base.texture)->depth)
1112 rctx->have_depth_texture = true;
1113
1114 /* Changing from array to non-arrays textures and vice versa requires updating TEX_ARRAY_OVERRIDE. */
1115 if ((rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1116 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i])
1117 dst->samplers_dirty = true;
1118
1119 set_resource(&rctx->ctx, &rviews[i]->state, i + R600_MAX_CONST_BUFFERS);
1120 } else {
1121 set_resource(&rctx->ctx, NULL, i + R600_MAX_CONST_BUFFERS);
1122 }
1123
1124 pipe_sampler_view_reference(
1125 (struct pipe_sampler_view **)&dst->views[i],
1126 views[i]);
1127 }
1128
1129 for (i = count; i < dst->n_views; i++) {
1130 if (dst->views[i]) {
1131 set_resource(&rctx->ctx, NULL, i + R600_MAX_CONST_BUFFERS);
1132 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], NULL);
1133 }
1134 }
1135
1136 dst->n_views = count;
1137 }
1138
1139 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1140 struct pipe_sampler_view **views)
1141 {
1142 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1143 r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views,
1144 r600_context_pipe_state_set_vs_resource);
1145 }
1146
1147 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1148 struct pipe_sampler_view **views)
1149 {
1150 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1151 r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views,
1152 r600_context_pipe_state_set_ps_resource);
1153 }
1154
1155 static void r600_set_seamless_cubemap(struct r600_pipe_context *rctx, boolean enable)
1156 {
1157 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1158 if (rstate == NULL)
1159 return;
1160
1161 rstate->id = R600_PIPE_STATE_SEAMLESS_CUBEMAP;
1162 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1163 (enable ? 0 : S_009508_DISABLE_CUBE_WRAP(1)),
1164 1, NULL, 0);
1165
1166 free(rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP]);
1167 rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP] = rstate;
1168 r600_context_pipe_state_set(&rctx->ctx, rstate);
1169 }
1170
1171 static void r600_bind_samplers(struct r600_pipe_context *rctx,
1172 struct r600_textures_info *dst,
1173 unsigned count, void **states)
1174 {
1175 memcpy(dst->samplers, states, sizeof(void*) * count);
1176 dst->n_samplers = count;
1177 dst->samplers_dirty = true;
1178 }
1179
1180 static void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states)
1181 {
1182 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1183 r600_bind_samplers(rctx, &rctx->vs_samplers, count, states);
1184 }
1185
1186 static void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states)
1187 {
1188 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1189 r600_bind_samplers(rctx, &rctx->ps_samplers, count, states);
1190 }
1191
1192 static void r600_update_samplers(struct r600_pipe_context *rctx,
1193 struct r600_textures_info *tex,
1194 void (*set_sampler)(struct r600_context*, struct r600_pipe_state*, unsigned))
1195 {
1196 unsigned i;
1197
1198 if (tex->samplers_dirty) {
1199 int seamless = -1;
1200 for (i = 0; i < tex->n_samplers; i++) {
1201 if (!tex->samplers[i])
1202 continue;
1203
1204 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1205 * filtering between layers.
1206 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. */
1207 if (tex->views[i]) {
1208 if (tex->views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1209 tex->views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
1210 tex->samplers[i]->rstate.regs[0].value |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1211 tex->is_array_sampler[i] = true;
1212 } else {
1213 tex->samplers[i]->rstate.regs[0].value &= C_03C000_TEX_ARRAY_OVERRIDE;
1214 tex->is_array_sampler[i] = false;
1215 }
1216 }
1217
1218 set_sampler(&rctx->ctx, &tex->samplers[i]->rstate, i);
1219
1220 if (tex->samplers[i])
1221 seamless = tex->samplers[i]->seamless_cube_map;
1222 }
1223
1224 if (seamless != -1)
1225 r600_set_seamless_cubemap(rctx, seamless);
1226
1227 tex->samplers_dirty = false;
1228 }
1229 }
1230
1231 void r600_update_sampler_states(struct r600_pipe_context *rctx)
1232 {
1233 r600_update_samplers(rctx, &rctx->vs_samplers,
1234 r600_context_pipe_state_set_vs_sampler);
1235 r600_update_samplers(rctx, &rctx->ps_samplers,
1236 r600_context_pipe_state_set_ps_sampler);
1237 }
1238
1239 static void r600_set_clip_state(struct pipe_context *ctx,
1240 const struct pipe_clip_state *state)
1241 {
1242 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1243 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1244
1245 if (rstate == NULL)
1246 return;
1247
1248 rctx->clip = *state;
1249 rstate->id = R600_PIPE_STATE_CLIP;
1250 for (int i = 0; i < state->nr; i++) {
1251 r600_pipe_state_add_reg(rstate,
1252 R_028E20_PA_CL_UCP0_X + i * 16,
1253 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL, 0);
1254 r600_pipe_state_add_reg(rstate,
1255 R_028E24_PA_CL_UCP0_Y + i * 16,
1256 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL, 0);
1257 r600_pipe_state_add_reg(rstate,
1258 R_028E28_PA_CL_UCP0_Z + i * 16,
1259 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL, 0);
1260 r600_pipe_state_add_reg(rstate,
1261 R_028E2C_PA_CL_UCP0_W + i * 16,
1262 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL, 0);
1263 }
1264 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
1265 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
1266 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
1267 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL, 0);
1268
1269 free(rctx->states[R600_PIPE_STATE_CLIP]);
1270 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1271 r600_context_pipe_state_set(&rctx->ctx, rstate);
1272 }
1273
1274 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1275 const struct pipe_poly_stipple *state)
1276 {
1277 }
1278
1279 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1280 {
1281 }
1282
1283 static void r600_set_scissor_state(struct pipe_context *ctx,
1284 const struct pipe_scissor_state *state)
1285 {
1286 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1287 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1288 u32 tl, br;
1289
1290 if (rstate == NULL)
1291 return;
1292
1293 rstate->id = R600_PIPE_STATE_SCISSOR;
1294 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1295 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1296 r600_pipe_state_add_reg(rstate,
1297 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1298 0xFFFFFFFF, NULL, 0);
1299 r600_pipe_state_add_reg(rstate,
1300 R_028214_PA_SC_CLIPRECT_0_BR, br,
1301 0xFFFFFFFF, NULL, 0);
1302 r600_pipe_state_add_reg(rstate,
1303 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1304 0xFFFFFFFF, NULL, 0);
1305 r600_pipe_state_add_reg(rstate,
1306 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1307 0xFFFFFFFF, NULL, 0);
1308 r600_pipe_state_add_reg(rstate,
1309 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1310 0xFFFFFFFF, NULL, 0);
1311 r600_pipe_state_add_reg(rstate,
1312 R_028224_PA_SC_CLIPRECT_2_BR, br,
1313 0xFFFFFFFF, NULL, 0);
1314 r600_pipe_state_add_reg(rstate,
1315 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1316 0xFFFFFFFF, NULL, 0);
1317 r600_pipe_state_add_reg(rstate,
1318 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1319 0xFFFFFFFF, NULL, 0);
1320
1321 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1322 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1323 r600_context_pipe_state_set(&rctx->ctx, rstate);
1324 }
1325
1326 static void r600_set_stencil_ref(struct pipe_context *ctx,
1327 const struct pipe_stencil_ref *state)
1328 {
1329 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1330 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1331 u32 tmp;
1332
1333 if (rstate == NULL)
1334 return;
1335
1336 rctx->stencil_ref = *state;
1337 rstate->id = R600_PIPE_STATE_STENCIL_REF;
1338 tmp = S_028430_STENCILREF(state->ref_value[0]);
1339 r600_pipe_state_add_reg(rstate,
1340 R_028430_DB_STENCILREFMASK, tmp,
1341 ~C_028430_STENCILREF, NULL, 0);
1342 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
1343 r600_pipe_state_add_reg(rstate,
1344 R_028434_DB_STENCILREFMASK_BF, tmp,
1345 ~C_028434_STENCILREF_BF, NULL, 0);
1346
1347 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
1348 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
1349 r600_context_pipe_state_set(&rctx->ctx, rstate);
1350 }
1351
1352 static void r600_set_viewport_state(struct pipe_context *ctx,
1353 const struct pipe_viewport_state *state)
1354 {
1355 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1356 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1357
1358 if (rstate == NULL)
1359 return;
1360
1361 rctx->viewport = *state;
1362 rstate->id = R600_PIPE_STATE_VIEWPORT;
1363 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL, 0);
1364 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL, 0);
1365 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL, 0);
1366 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL, 0);
1367 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL, 0);
1368 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL, 0);
1369 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL, 0);
1370 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL, 0);
1371 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL, 0);
1372
1373 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1374 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1375 r600_context_pipe_state_set(&rctx->ctx, rstate);
1376 }
1377
1378 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1379 const struct pipe_framebuffer_state *state, int cb)
1380 {
1381 struct r600_resource_texture *rtex;
1382 struct r600_resource *rbuffer;
1383 struct r600_surface *surf;
1384 unsigned level = state->cbufs[cb]->u.tex.level;
1385 unsigned pitch, slice;
1386 unsigned color_info;
1387 unsigned format, swap, ntype, endian;
1388 unsigned offset;
1389 const struct util_format_description *desc;
1390 struct r600_bo *bo[3];
1391 int i;
1392
1393 surf = (struct r600_surface *)state->cbufs[cb];
1394 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1395
1396 if (rtex->depth)
1397 rctx->have_depth_fb = TRUE;
1398
1399 if (rtex->depth && !rtex->is_flushing_texture) {
1400 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1401 rtex = rtex->flushed_depth_texture;
1402 }
1403
1404 rbuffer = &rtex->resource;
1405 bo[0] = rbuffer->bo;
1406 bo[1] = rbuffer->bo;
1407 bo[2] = rbuffer->bo;
1408
1409 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1410 offset = r600_texture_get_offset(rtex,
1411 level, state->cbufs[cb]->u.tex.first_layer);
1412 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1413 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1414 desc = util_format_description(surf->base.format);
1415
1416 for (i = 0; i < 4; i++) {
1417 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1418 break;
1419 }
1420 }
1421 ntype = V_0280A0_NUMBER_UNORM;
1422 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1423 ntype = V_0280A0_NUMBER_SRGB;
1424 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED)
1425 ntype = V_0280A0_NUMBER_SNORM;
1426
1427 format = r600_translate_colorformat(surf->base.format);
1428 swap = r600_translate_colorswap(surf->base.format);
1429 if(rbuffer->b.b.b.usage == PIPE_USAGE_STAGING) {
1430 endian = ENDIAN_NONE;
1431 } else {
1432 endian = r600_colorformat_endian_swap(format);
1433 }
1434
1435 /* disable when gallium grows int textures */
1436 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
1437 ntype = V_0280A0_NUMBER_UINT;
1438
1439 color_info = S_0280A0_FORMAT(format) |
1440 S_0280A0_COMP_SWAP(swap) |
1441 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
1442 S_0280A0_BLEND_CLAMP(1) |
1443 S_0280A0_NUMBER_TYPE(ntype) |
1444 S_0280A0_ENDIAN(endian);
1445
1446 /* EXPORT_NORM is an optimzation that can be enabled for better
1447 * performance in certain cases
1448 */
1449 if (rctx->chip_class == R600) {
1450 /* EXPORT_NORM can be enabled if:
1451 * - 11-bit or smaller UNORM/SNORM/SRGB
1452 * - BLEND_CLAMP is enabled
1453 * - BLEND_FLOAT32 is disabled
1454 */
1455 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1456 (desc->channel[i].size < 12 &&
1457 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1458 ntype != V_0280A0_NUMBER_UINT &&
1459 ntype != V_0280A0_NUMBER_SINT) &&
1460 G_0280A0_BLEND_CLAMP(color_info) &&
1461 !G_0280A0_BLEND_FLOAT32(color_info))
1462 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1463 } else {
1464 /* EXPORT_NORM can be enabled if:
1465 * - 11-bit or smaller UNORM/SNORM/SRGB
1466 * - 16-bit or smaller FLOAT
1467 */
1468 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1469 ((desc->channel[i].size < 12 &&
1470 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1471 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1472 (desc->channel[i].size < 17 &&
1473 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT)))
1474 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1475 }
1476
1477 r600_pipe_state_add_reg(rstate,
1478 R_028040_CB_COLOR0_BASE + cb * 4,
1479 offset >> 8, 0xFFFFFFFF, bo[0], RADEON_USAGE_READWRITE);
1480 r600_pipe_state_add_reg(rstate,
1481 R_0280A0_CB_COLOR0_INFO + cb * 4,
1482 color_info, 0xFFFFFFFF, bo[0], RADEON_USAGE_READWRITE);
1483 r600_pipe_state_add_reg(rstate,
1484 R_028060_CB_COLOR0_SIZE + cb * 4,
1485 S_028060_PITCH_TILE_MAX(pitch) |
1486 S_028060_SLICE_TILE_MAX(slice),
1487 0xFFFFFFFF, NULL, 0);
1488 r600_pipe_state_add_reg(rstate,
1489 R_028080_CB_COLOR0_VIEW + cb * 4,
1490 0x00000000, 0xFFFFFFFF, NULL, 0);
1491 r600_pipe_state_add_reg(rstate,
1492 R_0280E0_CB_COLOR0_FRAG + cb * 4,
1493 0, 0xFFFFFFFF, bo[1], RADEON_USAGE_READWRITE);
1494 r600_pipe_state_add_reg(rstate,
1495 R_0280C0_CB_COLOR0_TILE + cb * 4,
1496 0, 0xFFFFFFFF, bo[2], RADEON_USAGE_READWRITE);
1497 r600_pipe_state_add_reg(rstate,
1498 R_028100_CB_COLOR0_MASK + cb * 4,
1499 0x00000000, 0xFFFFFFFF, NULL, 0);
1500 }
1501
1502 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1503 const struct pipe_framebuffer_state *state)
1504 {
1505 struct r600_resource_texture *rtex;
1506 struct r600_resource *rbuffer;
1507 struct r600_surface *surf;
1508 unsigned level;
1509 unsigned pitch, slice, format;
1510 unsigned offset;
1511
1512 if (state->zsbuf == NULL)
1513 return;
1514
1515 level = state->zsbuf->u.tex.level;
1516
1517 surf = (struct r600_surface *)state->zsbuf;
1518 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1519
1520 rbuffer = &rtex->resource;
1521
1522 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1523 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
1524 level, state->zsbuf->u.tex.first_layer);
1525 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1526 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1527 format = r600_translate_dbformat(state->zsbuf->texture->format);
1528
1529 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
1530 offset >> 8, 0xFFFFFFFF, rbuffer->bo, RADEON_USAGE_READWRITE);
1531 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1532 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1533 0xFFFFFFFF, NULL, 0);
1534 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL, 0);
1535 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
1536 S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format),
1537 0xFFFFFFFF, rbuffer->bo, RADEON_USAGE_READWRITE);
1538 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1539 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL, 0);
1540 }
1541
1542 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1543 const struct pipe_framebuffer_state *state)
1544 {
1545 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1546 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1547 u32 shader_mask, tl, br, shader_control, target_mask;
1548
1549 if (rstate == NULL)
1550 return;
1551
1552 r600_context_flush_dest_caches(&rctx->ctx);
1553 rctx->ctx.num_dest_buffers = state->nr_cbufs;
1554
1555 /* unreference old buffer and reference new one */
1556 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1557
1558 util_copy_framebuffer_state(&rctx->framebuffer, state);
1559
1560 /* build states */
1561 rctx->have_depth_fb = 0;
1562 for (int i = 0; i < state->nr_cbufs; i++) {
1563 r600_cb(rctx, rstate, state, i);
1564 }
1565 if (state->zsbuf) {
1566 r600_db(rctx, rstate, state);
1567 rctx->ctx.num_dest_buffers++;
1568 }
1569
1570 target_mask = 0x00000000;
1571 target_mask = 0xFFFFFFFF;
1572 shader_mask = 0;
1573 shader_control = 0;
1574 for (int i = 0; i < state->nr_cbufs; i++) {
1575 target_mask ^= 0xf << (i * 4);
1576 shader_mask |= 0xf << (i * 4);
1577 shader_control |= 1 << i;
1578 }
1579 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1580 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1581
1582 r600_pipe_state_add_reg(rstate,
1583 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1584 0xFFFFFFFF, NULL, 0);
1585 r600_pipe_state_add_reg(rstate,
1586 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1587 0xFFFFFFFF, NULL, 0);
1588 r600_pipe_state_add_reg(rstate,
1589 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1590 0xFFFFFFFF, NULL, 0);
1591 r600_pipe_state_add_reg(rstate,
1592 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1593 0xFFFFFFFF, NULL, 0);
1594 r600_pipe_state_add_reg(rstate,
1595 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1596 0xFFFFFFFF, NULL, 0);
1597 r600_pipe_state_add_reg(rstate,
1598 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1599 0xFFFFFFFF, NULL, 0);
1600 r600_pipe_state_add_reg(rstate,
1601 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1602 0xFFFFFFFF, NULL, 0);
1603 r600_pipe_state_add_reg(rstate,
1604 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1605 0xFFFFFFFF, NULL, 0);
1606 r600_pipe_state_add_reg(rstate,
1607 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1608 0xFFFFFFFF, NULL, 0);
1609 if (rctx->chip_class >= R700) {
1610 r600_pipe_state_add_reg(rstate,
1611 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1612 0xFFFFFFFF, NULL, 0);
1613 }
1614
1615 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1616 shader_control, 0xFFFFFFFF, NULL, 0);
1617 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1618 0x00000000, target_mask, NULL, 0);
1619 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1620 shader_mask, 0xFFFFFFFF, NULL, 0);
1621 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1622 0x00000000, 0xFFFFFFFF, NULL, 0);
1623 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1624 0x00000000, 0xFFFFFFFF, NULL, 0);
1625 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1626 0x00000000, 0xFFFFFFFF, NULL, 0);
1627 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1628 0x01000000, 0xFFFFFFFF, NULL, 0);
1629 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1630 0x00000000, 0xFFFFFFFF, NULL, 0);
1631 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1632 0x000000FF, 0xFFFFFFFF, NULL, 0);
1633 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1634 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
1635 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1636 0xFFFFFFFF, 0xFFFFFFFF, NULL, 0);
1637
1638 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1639 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1640 r600_context_pipe_state_set(&rctx->ctx, rstate);
1641
1642 if (state->zsbuf) {
1643 r600_polygon_offset_update(rctx);
1644 }
1645 }
1646
1647 static void r600_texture_barrier(struct pipe_context *ctx)
1648 {
1649 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1650
1651 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
1652 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
1653 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
1654 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
1655 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1));
1656 }
1657
1658 void r600_init_state_functions(struct r600_pipe_context *rctx)
1659 {
1660 rctx->context.create_blend_state = r600_create_blend_state;
1661 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1662 rctx->context.create_fs_state = r600_create_shader_state;
1663 rctx->context.create_rasterizer_state = r600_create_rs_state;
1664 rctx->context.create_sampler_state = r600_create_sampler_state;
1665 rctx->context.create_sampler_view = r600_create_sampler_view;
1666 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1667 rctx->context.create_vs_state = r600_create_shader_state;
1668 rctx->context.bind_blend_state = r600_bind_blend_state;
1669 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1670 rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
1671 rctx->context.bind_fs_state = r600_bind_ps_shader;
1672 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1673 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1674 rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
1675 rctx->context.bind_vs_state = r600_bind_vs_shader;
1676 rctx->context.delete_blend_state = r600_delete_state;
1677 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1678 rctx->context.delete_fs_state = r600_delete_ps_shader;
1679 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1680 rctx->context.delete_sampler_state = r600_delete_state;
1681 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1682 rctx->context.delete_vs_state = r600_delete_vs_shader;
1683 rctx->context.set_blend_color = r600_set_blend_color;
1684 rctx->context.set_clip_state = r600_set_clip_state;
1685 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1686 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1687 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1688 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1689 rctx->context.set_sample_mask = r600_set_sample_mask;
1690 rctx->context.set_scissor_state = r600_set_scissor_state;
1691 rctx->context.set_stencil_ref = r600_set_stencil_ref;
1692 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1693 rctx->context.set_index_buffer = r600_set_index_buffer;
1694 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1695 rctx->context.set_viewport_state = r600_set_viewport_state;
1696 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1697 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1698 rctx->context.texture_barrier = r600_texture_barrier;
1699 }
1700
1701 void r600_adjust_gprs(struct r600_pipe_context *rctx)
1702 {
1703 struct r600_pipe_state rstate;
1704 unsigned num_ps_gprs = rctx->default_ps_gprs;
1705 unsigned num_vs_gprs = rctx->default_vs_gprs;
1706 unsigned tmp;
1707 int diff;
1708
1709 if (rctx->chip_class >= EVERGREEN)
1710 return;
1711
1712 if (!rctx->ps_shader || !rctx->vs_shader)
1713 return;
1714
1715 if (rctx->ps_shader->shader.bc.ngpr > rctx->default_ps_gprs)
1716 {
1717 diff = rctx->ps_shader->shader.bc.ngpr - rctx->default_ps_gprs;
1718 num_vs_gprs -= diff;
1719 num_ps_gprs += diff;
1720 }
1721
1722 if (rctx->vs_shader->shader.bc.ngpr > rctx->default_vs_gprs)
1723 {
1724 diff = rctx->vs_shader->shader.bc.ngpr - rctx->default_vs_gprs;
1725 num_ps_gprs -= diff;
1726 num_vs_gprs += diff;
1727 }
1728
1729 tmp = 0;
1730 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1731 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1732 rstate.nregs = 0;
1733 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0x0FFFFFFF, NULL, 0);
1734
1735 r600_context_pipe_state_set(&rctx->ctx, &rstate);
1736 }
1737
1738 void r600_init_config(struct r600_pipe_context *rctx)
1739 {
1740 int ps_prio;
1741 int vs_prio;
1742 int gs_prio;
1743 int es_prio;
1744 int num_ps_gprs;
1745 int num_vs_gprs;
1746 int num_gs_gprs;
1747 int num_es_gprs;
1748 int num_temp_gprs;
1749 int num_ps_threads;
1750 int num_vs_threads;
1751 int num_gs_threads;
1752 int num_es_threads;
1753 int num_ps_stack_entries;
1754 int num_vs_stack_entries;
1755 int num_gs_stack_entries;
1756 int num_es_stack_entries;
1757 enum radeon_family family;
1758 struct r600_pipe_state *rstate = &rctx->config;
1759 u32 tmp;
1760
1761 family = rctx->family;
1762 ps_prio = 0;
1763 vs_prio = 1;
1764 gs_prio = 2;
1765 es_prio = 3;
1766 switch (family) {
1767 case CHIP_R600:
1768 num_ps_gprs = 192;
1769 num_vs_gprs = 56;
1770 num_temp_gprs = 4;
1771 num_gs_gprs = 0;
1772 num_es_gprs = 0;
1773 num_ps_threads = 136;
1774 num_vs_threads = 48;
1775 num_gs_threads = 4;
1776 num_es_threads = 4;
1777 num_ps_stack_entries = 128;
1778 num_vs_stack_entries = 128;
1779 num_gs_stack_entries = 0;
1780 num_es_stack_entries = 0;
1781 break;
1782 case CHIP_RV630:
1783 case CHIP_RV635:
1784 num_ps_gprs = 84;
1785 num_vs_gprs = 36;
1786 num_temp_gprs = 4;
1787 num_gs_gprs = 0;
1788 num_es_gprs = 0;
1789 num_ps_threads = 144;
1790 num_vs_threads = 40;
1791 num_gs_threads = 4;
1792 num_es_threads = 4;
1793 num_ps_stack_entries = 40;
1794 num_vs_stack_entries = 40;
1795 num_gs_stack_entries = 32;
1796 num_es_stack_entries = 16;
1797 break;
1798 case CHIP_RV610:
1799 case CHIP_RV620:
1800 case CHIP_RS780:
1801 case CHIP_RS880:
1802 default:
1803 num_ps_gprs = 84;
1804 num_vs_gprs = 36;
1805 num_temp_gprs = 4;
1806 num_gs_gprs = 0;
1807 num_es_gprs = 0;
1808 num_ps_threads = 136;
1809 num_vs_threads = 48;
1810 num_gs_threads = 4;
1811 num_es_threads = 4;
1812 num_ps_stack_entries = 40;
1813 num_vs_stack_entries = 40;
1814 num_gs_stack_entries = 32;
1815 num_es_stack_entries = 16;
1816 break;
1817 case CHIP_RV670:
1818 num_ps_gprs = 144;
1819 num_vs_gprs = 40;
1820 num_temp_gprs = 4;
1821 num_gs_gprs = 0;
1822 num_es_gprs = 0;
1823 num_ps_threads = 136;
1824 num_vs_threads = 48;
1825 num_gs_threads = 4;
1826 num_es_threads = 4;
1827 num_ps_stack_entries = 40;
1828 num_vs_stack_entries = 40;
1829 num_gs_stack_entries = 32;
1830 num_es_stack_entries = 16;
1831 break;
1832 case CHIP_RV770:
1833 num_ps_gprs = 192;
1834 num_vs_gprs = 56;
1835 num_temp_gprs = 4;
1836 num_gs_gprs = 0;
1837 num_es_gprs = 0;
1838 num_ps_threads = 188;
1839 num_vs_threads = 60;
1840 num_gs_threads = 0;
1841 num_es_threads = 0;
1842 num_ps_stack_entries = 256;
1843 num_vs_stack_entries = 256;
1844 num_gs_stack_entries = 0;
1845 num_es_stack_entries = 0;
1846 break;
1847 case CHIP_RV730:
1848 case CHIP_RV740:
1849 num_ps_gprs = 84;
1850 num_vs_gprs = 36;
1851 num_temp_gprs = 4;
1852 num_gs_gprs = 0;
1853 num_es_gprs = 0;
1854 num_ps_threads = 188;
1855 num_vs_threads = 60;
1856 num_gs_threads = 0;
1857 num_es_threads = 0;
1858 num_ps_stack_entries = 128;
1859 num_vs_stack_entries = 128;
1860 num_gs_stack_entries = 0;
1861 num_es_stack_entries = 0;
1862 break;
1863 case CHIP_RV710:
1864 num_ps_gprs = 192;
1865 num_vs_gprs = 56;
1866 num_temp_gprs = 4;
1867 num_gs_gprs = 0;
1868 num_es_gprs = 0;
1869 num_ps_threads = 144;
1870 num_vs_threads = 48;
1871 num_gs_threads = 0;
1872 num_es_threads = 0;
1873 num_ps_stack_entries = 128;
1874 num_vs_stack_entries = 128;
1875 num_gs_stack_entries = 0;
1876 num_es_stack_entries = 0;
1877 break;
1878 }
1879
1880 rctx->default_ps_gprs = num_ps_gprs;
1881 rctx->default_vs_gprs = num_vs_gprs;
1882
1883 rstate->id = R600_PIPE_STATE_CONFIG;
1884
1885 /* SQ_CONFIG */
1886 tmp = 0;
1887 switch (family) {
1888 case CHIP_RV610:
1889 case CHIP_RV620:
1890 case CHIP_RS780:
1891 case CHIP_RS880:
1892 case CHIP_RV710:
1893 break;
1894 default:
1895 tmp |= S_008C00_VC_ENABLE(1);
1896 break;
1897 }
1898 tmp |= S_008C00_DX9_CONSTS(0);
1899 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1900 tmp |= S_008C00_PS_PRIO(ps_prio);
1901 tmp |= S_008C00_VS_PRIO(vs_prio);
1902 tmp |= S_008C00_GS_PRIO(gs_prio);
1903 tmp |= S_008C00_ES_PRIO(es_prio);
1904 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL, 0);
1905
1906 /* SQ_GPR_RESOURCE_MGMT_1 */
1907 tmp = 0;
1908 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1909 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1910 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1911 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
1912
1913 /* SQ_GPR_RESOURCE_MGMT_2 */
1914 tmp = 0;
1915 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1916 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1917 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
1918
1919 /* SQ_THREAD_RESOURCE_MGMT */
1920 tmp = 0;
1921 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1922 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1923 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1924 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1925 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL, 0);
1926
1927 /* SQ_STACK_RESOURCE_MGMT_1 */
1928 tmp = 0;
1929 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1930 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1931 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL, 0);
1932
1933 /* SQ_STACK_RESOURCE_MGMT_2 */
1934 tmp = 0;
1935 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1936 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1937 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL, 0);
1938
1939 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1940 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL, 0);
1941
1942 if (rctx->chip_class >= R700) {
1943 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL, 0);
1944 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1945 S_009508_DISABLE_CUBE_ANISO(1) |
1946 S_009508_SYNC_GRADIENT(1) |
1947 S_009508_SYNC_WALKER(1) |
1948 S_009508_SYNC_ALIGNER(1), 0xFFFFFFFF, NULL, 0);
1949 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL, 0);
1950 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL, 0);
1951 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL, 0);
1952 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL, 0);
1953 } else {
1954 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL, 0);
1955 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1956 S_009508_DISABLE_CUBE_ANISO(1) |
1957 S_009508_SYNC_GRADIENT(1) |
1958 S_009508_SYNC_WALKER(1) |
1959 S_009508_SYNC_ALIGNER(1), 0xFFFFFFFF, NULL, 0);
1960 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL, 0);
1961 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL, 0);
1962 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL, 0);
1963 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL, 0);
1964 }
1965 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1966 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1967 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1968 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1969 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1970 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1971 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1972 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1973 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1974 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
1975 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
1976 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL, 0);
1977 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL, 0);
1978 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL, 0);
1979 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1980 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL, 0);
1981 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL, 0);
1982 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
1983 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
1984 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
1985 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL, 0);
1986 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL, 0);
1987 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
1988 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL, 0);
1989 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
1990 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
1991
1992 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL, 0);
1993 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
1994 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL, 0);
1995 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL, 0);
1996 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL, 0);
1997 r600_context_pipe_state_set(&rctx->ctx, rstate);
1998 }
1999
2000 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2001 {
2002 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2003 struct r600_pipe_state *rstate = &shader->rstate;
2004 struct r600_shader *rshader = &shader->shader;
2005 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2006 int pos_index = -1, face_index = -1;
2007
2008 rstate->nregs = 0;
2009
2010 for (i = 0; i < rshader->ninput; i++) {
2011 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2012 pos_index = i;
2013 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2014 face_index = i;
2015 }
2016
2017 db_shader_control = 0;
2018 for (i = 0; i < rshader->noutput; i++) {
2019 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2020 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2021 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2022 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1);
2023 }
2024 if (rshader->uses_kill)
2025 db_shader_control |= S_02880C_KILL_ENABLE(1);
2026
2027 exports_ps = 0;
2028 num_cout = 0;
2029 for (i = 0; i < rshader->noutput; i++) {
2030 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2031 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2032 exports_ps |= 1;
2033 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2034 num_cout++;
2035 }
2036 }
2037 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2038 if (!exports_ps) {
2039 /* always at least export 1 component per pixel */
2040 exports_ps = 2;
2041 }
2042
2043 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2044 S_0286CC_PERSP_GRADIENT_ENA(1);
2045 spi_input_z = 0;
2046 if (pos_index != -1) {
2047 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2048 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2049 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2050 S_0286CC_BARYC_SAMPLE_CNTL(1));
2051 spi_input_z |= 1;
2052 }
2053
2054 spi_ps_in_control_1 = 0;
2055 if (face_index != -1) {
2056 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2057 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2058 }
2059
2060 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL, 0);
2061 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL, 0);
2062 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL, 0);
2063 r600_pipe_state_add_reg(rstate,
2064 R_028840_SQ_PGM_START_PS,
2065 0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2066 r600_pipe_state_add_reg(rstate,
2067 R_028850_SQ_PGM_RESOURCES_PS,
2068 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2069 S_028868_STACK_SIZE(rshader->bc.nstack),
2070 0xFFFFFFFF, NULL, 0);
2071 r600_pipe_state_add_reg(rstate,
2072 R_028854_SQ_PGM_EXPORTS_PS,
2073 exports_ps, 0xFFFFFFFF, NULL, 0);
2074 r600_pipe_state_add_reg(rstate,
2075 R_0288CC_SQ_PGM_CF_OFFSET_PS,
2076 0x00000000, 0xFFFFFFFF, NULL, 0);
2077 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
2078 S_028808_MULTIWRITE_ENABLE(!!rshader->fs_write_all),
2079 S_028808_MULTIWRITE_ENABLE(1),
2080 NULL, 0);
2081 /* only set some bits here, the other bits are set in the dsa state */
2082 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2083 db_shader_control,
2084 S_02880C_Z_EXPORT_ENABLE(1) |
2085 S_02880C_STENCIL_REF_EXPORT_ENABLE(1) |
2086 S_02880C_KILL_ENABLE(1),
2087 NULL, 0);
2088
2089 r600_pipe_state_add_reg(rstate,
2090 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
2091 0xFFFFFFFF, NULL, 0);
2092 }
2093
2094 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2095 {
2096 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2097 struct r600_pipe_state *rstate = &shader->rstate;
2098 struct r600_shader *rshader = &shader->shader;
2099 unsigned spi_vs_out_id[10];
2100 unsigned i, tmp, nparams;
2101
2102 /* clear previous register */
2103 rstate->nregs = 0;
2104
2105 /* so far never got proper semantic id from tgsi */
2106 /* FIXME better to move this in config things so they get emited
2107 * only one time per cs
2108 */
2109 for (i = 0; i < 10; i++) {
2110 spi_vs_out_id[i] = 0;
2111 }
2112 for (i = 0; i < 32; i++) {
2113 tmp = i << ((i & 3) * 8);
2114 spi_vs_out_id[i / 4] |= tmp;
2115 }
2116 for (i = 0; i < 10; i++) {
2117 r600_pipe_state_add_reg(rstate,
2118 R_028614_SPI_VS_OUT_ID_0 + i * 4,
2119 spi_vs_out_id[i], 0xFFFFFFFF, NULL, 0);
2120 }
2121
2122 /* Certain attributes (position, psize, etc.) don't count as params.
2123 * VS is required to export at least one param and r600_shader_from_tgsi()
2124 * takes care of adding a dummy export.
2125 */
2126 nparams = rshader->noutput - rshader->npos;
2127 if (nparams < 1)
2128 nparams = 1;
2129
2130 r600_pipe_state_add_reg(rstate,
2131 R_0286C4_SPI_VS_OUT_CONFIG,
2132 S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2133 0xFFFFFFFF, NULL, 0);
2134 r600_pipe_state_add_reg(rstate,
2135 R_028868_SQ_PGM_RESOURCES_VS,
2136 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2137 S_028868_STACK_SIZE(rshader->bc.nstack),
2138 0xFFFFFFFF, NULL, 0);
2139 r600_pipe_state_add_reg(rstate,
2140 R_0288D0_SQ_PGM_CF_OFFSET_VS,
2141 0x00000000, 0xFFFFFFFF, NULL, 0);
2142 r600_pipe_state_add_reg(rstate,
2143 R_028858_SQ_PGM_START_VS,
2144 0, 0xFFFFFFFF, shader->bo, RADEON_USAGE_READ);
2145
2146 r600_pipe_state_add_reg(rstate,
2147 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2148 0xFFFFFFFF, NULL, 0);
2149 }
2150
2151 void r600_fetch_shader(struct pipe_context *ctx,
2152 struct r600_vertex_element *ve)
2153 {
2154 struct r600_pipe_state *rstate;
2155 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2156
2157 rstate = &ve->rstate;
2158 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2159 rstate->nregs = 0;
2160 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
2161 0x00000000, 0xFFFFFFFF, NULL, 0);
2162 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
2163 0x00000000, 0xFFFFFFFF, NULL, 0);
2164 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
2165 0,
2166 0xFFFFFFFF, ve->fetch_shader, RADEON_USAGE_READ);
2167 }
2168
2169 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
2170 {
2171 struct pipe_depth_stencil_alpha_state dsa;
2172 struct r600_pipe_state *rstate;
2173 boolean quirk = false;
2174
2175 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2176 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2177 quirk = true;
2178
2179 memset(&dsa, 0, sizeof(dsa));
2180
2181 if (quirk) {
2182 dsa.depth.enabled = 1;
2183 dsa.depth.func = PIPE_FUNC_LEQUAL;
2184 dsa.stencil[0].enabled = 1;
2185 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2186 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2187 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2188 dsa.stencil[0].writemask = 0xff;
2189 }
2190
2191 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2192 r600_pipe_state_add_reg(rstate,
2193 R_02880C_DB_SHADER_CONTROL,
2194 0x0,
2195 S_02880C_DUAL_EXPORT_ENABLE(1), NULL, 0);
2196 r600_pipe_state_add_reg(rstate,
2197 R_028D0C_DB_RENDER_CONTROL,
2198 S_028D0C_DEPTH_COPY_ENABLE(1) |
2199 S_028D0C_STENCIL_COPY_ENABLE(1) |
2200 S_028D0C_COPY_CENTROID(1),
2201 S_028D0C_DEPTH_COPY_ENABLE(1) |
2202 S_028D0C_STENCIL_COPY_ENABLE(1) |
2203 S_028D0C_COPY_CENTROID(1), NULL, 0);
2204 return rstate;
2205 }
2206
2207 void r600_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
2208 struct r600_pipe_resource_state *rstate)
2209 {
2210 rstate->id = R600_PIPE_STATE_RESOURCE;
2211
2212 rstate->bo[0] = NULL;
2213 rstate->val[0] = 0;
2214 rstate->val[1] = 0;
2215 rstate->val[2] = 0;
2216 rstate->val[3] = 0;
2217 rstate->val[4] = 0;
2218 rstate->val[5] = 0;
2219 rstate->val[6] = 0xc0000000;
2220 }
2221
2222 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
2223 struct r600_resource *rbuffer,
2224 unsigned offset, unsigned stride,
2225 enum radeon_bo_usage usage)
2226 {
2227 rstate->val[0] = offset;
2228 rstate->bo[0] = rbuffer->bo;
2229 rstate->bo_usage[0] = usage;
2230 rstate->val[1] = rbuffer->bo_size - offset - 1;
2231 rstate->val[2] = S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
2232 S_038008_STRIDE(stride);
2233 }