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radeon: rearrange r600_texture and related code a bit.
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static uint32_t r600_translate_colorswap(enum pipe_format format)
145 {
146 switch (format) {
147 /* 8-bit buffers. */
148 case PIPE_FORMAT_A8_UNORM:
149 case PIPE_FORMAT_A8_SNORM:
150 case PIPE_FORMAT_A8_UINT:
151 case PIPE_FORMAT_A8_SINT:
152 case PIPE_FORMAT_A16_UNORM:
153 case PIPE_FORMAT_A16_SNORM:
154 case PIPE_FORMAT_A16_UINT:
155 case PIPE_FORMAT_A16_SINT:
156 case PIPE_FORMAT_A16_FLOAT:
157 case PIPE_FORMAT_A32_UINT:
158 case PIPE_FORMAT_A32_SINT:
159 case PIPE_FORMAT_A32_FLOAT:
160 case PIPE_FORMAT_R4A4_UNORM:
161 return V_0280A0_SWAP_ALT_REV;
162 case PIPE_FORMAT_I8_UNORM:
163 case PIPE_FORMAT_I8_SNORM:
164 case PIPE_FORMAT_I8_UINT:
165 case PIPE_FORMAT_I8_SINT:
166 case PIPE_FORMAT_L8_UNORM:
167 case PIPE_FORMAT_L8_SNORM:
168 case PIPE_FORMAT_L8_UINT:
169 case PIPE_FORMAT_L8_SINT:
170 case PIPE_FORMAT_L8_SRGB:
171 case PIPE_FORMAT_L16_UNORM:
172 case PIPE_FORMAT_L16_SNORM:
173 case PIPE_FORMAT_L16_UINT:
174 case PIPE_FORMAT_L16_SINT:
175 case PIPE_FORMAT_L16_FLOAT:
176 case PIPE_FORMAT_L32_UINT:
177 case PIPE_FORMAT_L32_SINT:
178 case PIPE_FORMAT_L32_FLOAT:
179 case PIPE_FORMAT_I16_UNORM:
180 case PIPE_FORMAT_I16_SNORM:
181 case PIPE_FORMAT_I16_UINT:
182 case PIPE_FORMAT_I16_SINT:
183 case PIPE_FORMAT_I16_FLOAT:
184 case PIPE_FORMAT_I32_UINT:
185 case PIPE_FORMAT_I32_SINT:
186 case PIPE_FORMAT_I32_FLOAT:
187 case PIPE_FORMAT_R8_UNORM:
188 case PIPE_FORMAT_R8_SNORM:
189 case PIPE_FORMAT_R8_UINT:
190 case PIPE_FORMAT_R8_SINT:
191 return V_0280A0_SWAP_STD;
192
193 case PIPE_FORMAT_L4A4_UNORM:
194 case PIPE_FORMAT_A4R4_UNORM:
195 return V_0280A0_SWAP_ALT;
196
197 /* 16-bit buffers. */
198 case PIPE_FORMAT_B5G6R5_UNORM:
199 return V_0280A0_SWAP_STD_REV;
200
201 case PIPE_FORMAT_B5G5R5A1_UNORM:
202 case PIPE_FORMAT_B5G5R5X1_UNORM:
203 return V_0280A0_SWAP_ALT;
204
205 case PIPE_FORMAT_B4G4R4A4_UNORM:
206 case PIPE_FORMAT_B4G4R4X4_UNORM:
207 return V_0280A0_SWAP_ALT;
208
209 case PIPE_FORMAT_Z16_UNORM:
210 return V_0280A0_SWAP_STD;
211
212 case PIPE_FORMAT_L8A8_UNORM:
213 case PIPE_FORMAT_L8A8_SNORM:
214 case PIPE_FORMAT_L8A8_UINT:
215 case PIPE_FORMAT_L8A8_SINT:
216 case PIPE_FORMAT_L8A8_SRGB:
217 case PIPE_FORMAT_L16A16_UNORM:
218 case PIPE_FORMAT_L16A16_SNORM:
219 case PIPE_FORMAT_L16A16_UINT:
220 case PIPE_FORMAT_L16A16_SINT:
221 case PIPE_FORMAT_L16A16_FLOAT:
222 case PIPE_FORMAT_L32A32_UINT:
223 case PIPE_FORMAT_L32A32_SINT:
224 case PIPE_FORMAT_L32A32_FLOAT:
225 case PIPE_FORMAT_R8A8_UNORM:
226 case PIPE_FORMAT_R8A8_SNORM:
227 case PIPE_FORMAT_R8A8_UINT:
228 case PIPE_FORMAT_R8A8_SINT:
229 case PIPE_FORMAT_R16A16_UNORM:
230 case PIPE_FORMAT_R16A16_SNORM:
231 case PIPE_FORMAT_R16A16_UINT:
232 case PIPE_FORMAT_R16A16_SINT:
233 case PIPE_FORMAT_R16A16_FLOAT:
234 case PIPE_FORMAT_R32A32_UINT:
235 case PIPE_FORMAT_R32A32_SINT:
236 case PIPE_FORMAT_R32A32_FLOAT:
237 return V_0280A0_SWAP_ALT;
238 case PIPE_FORMAT_R8G8_UNORM:
239 case PIPE_FORMAT_R8G8_SNORM:
240 case PIPE_FORMAT_R8G8_UINT:
241 case PIPE_FORMAT_R8G8_SINT:
242 return V_0280A0_SWAP_STD;
243
244 case PIPE_FORMAT_R16_UNORM:
245 case PIPE_FORMAT_R16_SNORM:
246 case PIPE_FORMAT_R16_UINT:
247 case PIPE_FORMAT_R16_SINT:
248 case PIPE_FORMAT_R16_FLOAT:
249 return V_0280A0_SWAP_STD;
250
251 /* 32-bit buffers. */
252
253 case PIPE_FORMAT_A8B8G8R8_SRGB:
254 return V_0280A0_SWAP_STD_REV;
255 case PIPE_FORMAT_B8G8R8A8_SRGB:
256 return V_0280A0_SWAP_ALT;
257
258 case PIPE_FORMAT_B8G8R8A8_UNORM:
259 case PIPE_FORMAT_B8G8R8X8_UNORM:
260 return V_0280A0_SWAP_ALT;
261
262 case PIPE_FORMAT_A8R8G8B8_UNORM:
263 case PIPE_FORMAT_X8R8G8B8_UNORM:
264 return V_0280A0_SWAP_ALT_REV;
265 case PIPE_FORMAT_R8G8B8A8_SNORM:
266 case PIPE_FORMAT_R8G8B8A8_UNORM:
267 case PIPE_FORMAT_R8G8B8X8_UNORM:
268 case PIPE_FORMAT_R8G8B8X8_SNORM:
269 case PIPE_FORMAT_R8G8B8X8_SRGB:
270 case PIPE_FORMAT_R8G8B8X8_UINT:
271 case PIPE_FORMAT_R8G8B8X8_SINT:
272 case PIPE_FORMAT_R8G8B8A8_SINT:
273 case PIPE_FORMAT_R8G8B8A8_UINT:
274 return V_0280A0_SWAP_STD;
275
276 case PIPE_FORMAT_A8B8G8R8_UNORM:
277 case PIPE_FORMAT_X8B8G8R8_UNORM:
278 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
279 return V_0280A0_SWAP_STD_REV;
280
281 case PIPE_FORMAT_Z24X8_UNORM:
282 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
283 return V_0280A0_SWAP_STD;
284
285 case PIPE_FORMAT_R10G10B10A2_UNORM:
286 case PIPE_FORMAT_R10G10B10X2_SNORM:
287 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
288 return V_0280A0_SWAP_STD;
289
290 case PIPE_FORMAT_B10G10R10A2_UNORM:
291 case PIPE_FORMAT_B10G10R10A2_UINT:
292 case PIPE_FORMAT_B10G10R10X2_UNORM:
293 return V_0280A0_SWAP_ALT;
294
295 case PIPE_FORMAT_R11G11B10_FLOAT:
296 case PIPE_FORMAT_R16G16_UNORM:
297 case PIPE_FORMAT_R16G16_SNORM:
298 case PIPE_FORMAT_R16G16_FLOAT:
299 case PIPE_FORMAT_R16G16_UINT:
300 case PIPE_FORMAT_R16G16_SINT:
301 case PIPE_FORMAT_R32_UINT:
302 case PIPE_FORMAT_R32_SINT:
303 case PIPE_FORMAT_R32_FLOAT:
304 case PIPE_FORMAT_Z32_FLOAT:
305 return V_0280A0_SWAP_STD;
306
307 /* 64-bit buffers. */
308 case PIPE_FORMAT_R32G32_FLOAT:
309 case PIPE_FORMAT_R32G32_UINT:
310 case PIPE_FORMAT_R32G32_SINT:
311 case PIPE_FORMAT_R16G16B16A16_UNORM:
312 case PIPE_FORMAT_R16G16B16A16_SNORM:
313 case PIPE_FORMAT_R16G16B16A16_UINT:
314 case PIPE_FORMAT_R16G16B16A16_SINT:
315 case PIPE_FORMAT_R16G16B16A16_FLOAT:
316 case PIPE_FORMAT_R16G16B16X16_UNORM:
317 case PIPE_FORMAT_R16G16B16X16_SNORM:
318 case PIPE_FORMAT_R16G16B16X16_FLOAT:
319 case PIPE_FORMAT_R16G16B16X16_UINT:
320 case PIPE_FORMAT_R16G16B16X16_SINT:
321 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
322
323 /* 128-bit buffers. */
324 case PIPE_FORMAT_R32G32B32A32_FLOAT:
325 case PIPE_FORMAT_R32G32B32A32_SNORM:
326 case PIPE_FORMAT_R32G32B32A32_UNORM:
327 case PIPE_FORMAT_R32G32B32A32_SINT:
328 case PIPE_FORMAT_R32G32B32A32_UINT:
329 case PIPE_FORMAT_R32G32B32X32_FLOAT:
330 case PIPE_FORMAT_R32G32B32X32_UINT:
331 case PIPE_FORMAT_R32G32B32X32_SINT:
332 return V_0280A0_SWAP_STD;
333 default:
334 R600_ERR("unsupported colorswap format %d\n", format);
335 return ~0U;
336 }
337 return ~0U;
338 }
339
340 static uint32_t r600_translate_colorformat(enum pipe_format format)
341 {
342 switch (format) {
343 case PIPE_FORMAT_L4A4_UNORM:
344 case PIPE_FORMAT_R4A4_UNORM:
345 case PIPE_FORMAT_A4R4_UNORM:
346 return V_0280A0_COLOR_4_4;
347
348 /* 8-bit buffers. */
349 case PIPE_FORMAT_A8_UNORM:
350 case PIPE_FORMAT_A8_SNORM:
351 case PIPE_FORMAT_A8_UINT:
352 case PIPE_FORMAT_A8_SINT:
353 case PIPE_FORMAT_I8_UNORM:
354 case PIPE_FORMAT_I8_SNORM:
355 case PIPE_FORMAT_I8_UINT:
356 case PIPE_FORMAT_I8_SINT:
357 case PIPE_FORMAT_L8_UNORM:
358 case PIPE_FORMAT_L8_SNORM:
359 case PIPE_FORMAT_L8_UINT:
360 case PIPE_FORMAT_L8_SINT:
361 case PIPE_FORMAT_L8_SRGB:
362 case PIPE_FORMAT_R8_UNORM:
363 case PIPE_FORMAT_R8_SNORM:
364 case PIPE_FORMAT_R8_UINT:
365 case PIPE_FORMAT_R8_SINT:
366 return V_0280A0_COLOR_8;
367
368 /* 16-bit buffers. */
369 case PIPE_FORMAT_B5G6R5_UNORM:
370 return V_0280A0_COLOR_5_6_5;
371
372 case PIPE_FORMAT_B5G5R5A1_UNORM:
373 case PIPE_FORMAT_B5G5R5X1_UNORM:
374 return V_0280A0_COLOR_1_5_5_5;
375
376 case PIPE_FORMAT_B4G4R4A4_UNORM:
377 case PIPE_FORMAT_B4G4R4X4_UNORM:
378 return V_0280A0_COLOR_4_4_4_4;
379
380 case PIPE_FORMAT_Z16_UNORM:
381 return V_0280A0_COLOR_16;
382
383 case PIPE_FORMAT_L8A8_UNORM:
384 case PIPE_FORMAT_L8A8_SNORM:
385 case PIPE_FORMAT_L8A8_UINT:
386 case PIPE_FORMAT_L8A8_SINT:
387 case PIPE_FORMAT_L8A8_SRGB:
388 case PIPE_FORMAT_R8G8_UNORM:
389 case PIPE_FORMAT_R8G8_SNORM:
390 case PIPE_FORMAT_R8G8_UINT:
391 case PIPE_FORMAT_R8G8_SINT:
392 case PIPE_FORMAT_R8A8_UNORM:
393 case PIPE_FORMAT_R8A8_SNORM:
394 case PIPE_FORMAT_R8A8_UINT:
395 case PIPE_FORMAT_R8A8_SINT:
396 return V_0280A0_COLOR_8_8;
397
398 case PIPE_FORMAT_R16_UNORM:
399 case PIPE_FORMAT_R16_SNORM:
400 case PIPE_FORMAT_R16_UINT:
401 case PIPE_FORMAT_R16_SINT:
402 case PIPE_FORMAT_A16_UNORM:
403 case PIPE_FORMAT_A16_SNORM:
404 case PIPE_FORMAT_A16_UINT:
405 case PIPE_FORMAT_A16_SINT:
406 case PIPE_FORMAT_L16_UNORM:
407 case PIPE_FORMAT_L16_SNORM:
408 case PIPE_FORMAT_L16_UINT:
409 case PIPE_FORMAT_L16_SINT:
410 case PIPE_FORMAT_I16_UNORM:
411 case PIPE_FORMAT_I16_SNORM:
412 case PIPE_FORMAT_I16_UINT:
413 case PIPE_FORMAT_I16_SINT:
414 return V_0280A0_COLOR_16;
415
416 case PIPE_FORMAT_R16_FLOAT:
417 case PIPE_FORMAT_A16_FLOAT:
418 case PIPE_FORMAT_L16_FLOAT:
419 case PIPE_FORMAT_I16_FLOAT:
420 return V_0280A0_COLOR_16_FLOAT;
421
422 /* 32-bit buffers. */
423 case PIPE_FORMAT_A8B8G8R8_SRGB:
424 case PIPE_FORMAT_A8B8G8R8_UNORM:
425 case PIPE_FORMAT_A8R8G8B8_UNORM:
426 case PIPE_FORMAT_B8G8R8A8_SRGB:
427 case PIPE_FORMAT_B8G8R8A8_UNORM:
428 case PIPE_FORMAT_B8G8R8X8_UNORM:
429 case PIPE_FORMAT_R8G8B8A8_SNORM:
430 case PIPE_FORMAT_R8G8B8A8_UNORM:
431 case PIPE_FORMAT_R8G8B8X8_UNORM:
432 case PIPE_FORMAT_R8G8B8X8_SNORM:
433 case PIPE_FORMAT_R8G8B8X8_SRGB:
434 case PIPE_FORMAT_R8G8B8X8_UINT:
435 case PIPE_FORMAT_R8G8B8X8_SINT:
436 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
437 case PIPE_FORMAT_X8B8G8R8_UNORM:
438 case PIPE_FORMAT_X8R8G8B8_UNORM:
439 case PIPE_FORMAT_R8G8B8A8_SINT:
440 case PIPE_FORMAT_R8G8B8A8_UINT:
441 return V_0280A0_COLOR_8_8_8_8;
442
443 case PIPE_FORMAT_R10G10B10A2_UNORM:
444 case PIPE_FORMAT_R10G10B10X2_SNORM:
445 case PIPE_FORMAT_B10G10R10A2_UNORM:
446 case PIPE_FORMAT_B10G10R10A2_UINT:
447 case PIPE_FORMAT_B10G10R10X2_UNORM:
448 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
449 return V_0280A0_COLOR_2_10_10_10;
450
451 case PIPE_FORMAT_Z24X8_UNORM:
452 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
453 return V_0280A0_COLOR_8_24;
454
455 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
456 return V_0280A0_COLOR_X24_8_32_FLOAT;
457
458 case PIPE_FORMAT_R32_UINT:
459 case PIPE_FORMAT_R32_SINT:
460 case PIPE_FORMAT_A32_UINT:
461 case PIPE_FORMAT_A32_SINT:
462 case PIPE_FORMAT_L32_UINT:
463 case PIPE_FORMAT_L32_SINT:
464 case PIPE_FORMAT_I32_UINT:
465 case PIPE_FORMAT_I32_SINT:
466 return V_0280A0_COLOR_32;
467
468 case PIPE_FORMAT_R32_FLOAT:
469 case PIPE_FORMAT_A32_FLOAT:
470 case PIPE_FORMAT_L32_FLOAT:
471 case PIPE_FORMAT_I32_FLOAT:
472 case PIPE_FORMAT_Z32_FLOAT:
473 return V_0280A0_COLOR_32_FLOAT;
474
475 case PIPE_FORMAT_R16G16_FLOAT:
476 case PIPE_FORMAT_L16A16_FLOAT:
477 case PIPE_FORMAT_R16A16_FLOAT:
478 return V_0280A0_COLOR_16_16_FLOAT;
479
480 case PIPE_FORMAT_R16G16_UNORM:
481 case PIPE_FORMAT_R16G16_SNORM:
482 case PIPE_FORMAT_R16G16_UINT:
483 case PIPE_FORMAT_R16G16_SINT:
484 case PIPE_FORMAT_L16A16_UNORM:
485 case PIPE_FORMAT_L16A16_SNORM:
486 case PIPE_FORMAT_L16A16_UINT:
487 case PIPE_FORMAT_L16A16_SINT:
488 case PIPE_FORMAT_R16A16_UNORM:
489 case PIPE_FORMAT_R16A16_SNORM:
490 case PIPE_FORMAT_R16A16_UINT:
491 case PIPE_FORMAT_R16A16_SINT:
492 return V_0280A0_COLOR_16_16;
493
494 case PIPE_FORMAT_R11G11B10_FLOAT:
495 return V_0280A0_COLOR_10_11_11_FLOAT;
496
497 /* 64-bit buffers. */
498 case PIPE_FORMAT_R16G16B16A16_UINT:
499 case PIPE_FORMAT_R16G16B16A16_SINT:
500 case PIPE_FORMAT_R16G16B16A16_UNORM:
501 case PIPE_FORMAT_R16G16B16A16_SNORM:
502 case PIPE_FORMAT_R16G16B16X16_UNORM:
503 case PIPE_FORMAT_R16G16B16X16_SNORM:
504 case PIPE_FORMAT_R16G16B16X16_UINT:
505 case PIPE_FORMAT_R16G16B16X16_SINT:
506 return V_0280A0_COLOR_16_16_16_16;
507
508 case PIPE_FORMAT_R16G16B16A16_FLOAT:
509 case PIPE_FORMAT_R16G16B16X16_FLOAT:
510 return V_0280A0_COLOR_16_16_16_16_FLOAT;
511
512 case PIPE_FORMAT_R32G32_FLOAT:
513 case PIPE_FORMAT_L32A32_FLOAT:
514 case PIPE_FORMAT_R32A32_FLOAT:
515 return V_0280A0_COLOR_32_32_FLOAT;
516
517 case PIPE_FORMAT_R32G32_SINT:
518 case PIPE_FORMAT_R32G32_UINT:
519 case PIPE_FORMAT_L32A32_UINT:
520 case PIPE_FORMAT_L32A32_SINT:
521 return V_0280A0_COLOR_32_32;
522
523 /* 128-bit buffers. */
524 case PIPE_FORMAT_R32G32B32A32_FLOAT:
525 case PIPE_FORMAT_R32G32B32X32_FLOAT:
526 return V_0280A0_COLOR_32_32_32_32_FLOAT;
527 case PIPE_FORMAT_R32G32B32A32_SNORM:
528 case PIPE_FORMAT_R32G32B32A32_UNORM:
529 case PIPE_FORMAT_R32G32B32A32_SINT:
530 case PIPE_FORMAT_R32G32B32A32_UINT:
531 case PIPE_FORMAT_R32G32B32X32_UINT:
532 case PIPE_FORMAT_R32G32B32X32_SINT:
533 return V_0280A0_COLOR_32_32_32_32;
534
535 /* YUV buffers. */
536 case PIPE_FORMAT_UYVY:
537 case PIPE_FORMAT_YUYV:
538 default:
539 return ~0U; /* Unsupported. */
540 }
541 }
542
543 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
544 {
545 if (R600_BIG_ENDIAN) {
546 switch(colorformat) {
547 case V_0280A0_COLOR_4_4:
548 return ENDIAN_NONE;
549
550 /* 8-bit buffers. */
551 case V_0280A0_COLOR_8:
552 return ENDIAN_NONE;
553
554 /* 16-bit buffers. */
555 case V_0280A0_COLOR_5_6_5:
556 case V_0280A0_COLOR_1_5_5_5:
557 case V_0280A0_COLOR_4_4_4_4:
558 case V_0280A0_COLOR_16:
559 case V_0280A0_COLOR_8_8:
560 return ENDIAN_8IN16;
561
562 /* 32-bit buffers. */
563 case V_0280A0_COLOR_8_8_8_8:
564 case V_0280A0_COLOR_2_10_10_10:
565 case V_0280A0_COLOR_8_24:
566 case V_0280A0_COLOR_24_8:
567 case V_0280A0_COLOR_32_FLOAT:
568 case V_0280A0_COLOR_16_16_FLOAT:
569 case V_0280A0_COLOR_16_16:
570 return ENDIAN_8IN32;
571
572 /* 64-bit buffers. */
573 case V_0280A0_COLOR_16_16_16_16:
574 case V_0280A0_COLOR_16_16_16_16_FLOAT:
575 return ENDIAN_8IN16;
576
577 case V_0280A0_COLOR_32_32_FLOAT:
578 case V_0280A0_COLOR_32_32:
579 case V_0280A0_COLOR_X24_8_32_FLOAT:
580 return ENDIAN_8IN32;
581
582 /* 128-bit buffers. */
583 case V_0280A0_COLOR_32_32_32_FLOAT:
584 case V_0280A0_COLOR_32_32_32_32_FLOAT:
585 case V_0280A0_COLOR_32_32_32_32:
586 return ENDIAN_8IN32;
587 default:
588 return ENDIAN_NONE; /* Unsupported. */
589 }
590 } else {
591 return ENDIAN_NONE;
592 }
593 }
594
595 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
596 {
597 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
598 }
599
600 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
601 {
602 return r600_translate_colorformat(format) != ~0U &&
603 r600_translate_colorswap(format) != ~0U;
604 }
605
606 static bool r600_is_zs_format_supported(enum pipe_format format)
607 {
608 return r600_translate_dbformat(format) != ~0U;
609 }
610
611 boolean r600_is_format_supported(struct pipe_screen *screen,
612 enum pipe_format format,
613 enum pipe_texture_target target,
614 unsigned sample_count,
615 unsigned usage)
616 {
617 struct r600_screen *rscreen = (struct r600_screen*)screen;
618 unsigned retval = 0;
619
620 if (target >= PIPE_MAX_TEXTURE_TYPES) {
621 R600_ERR("r600: unsupported texture type %d\n", target);
622 return FALSE;
623 }
624
625 if (!util_format_is_supported(format, usage))
626 return FALSE;
627
628 if (sample_count > 1) {
629 if (!rscreen->has_msaa)
630 return FALSE;
631
632 /* R11G11B10 is broken on R6xx. */
633 if (rscreen->b.chip_class == R600 &&
634 format == PIPE_FORMAT_R11G11B10_FLOAT)
635 return FALSE;
636
637 /* MSAA integer colorbuffers hang. */
638 if (util_format_is_pure_integer(format) &&
639 !util_format_is_depth_or_stencil(format))
640 return FALSE;
641
642 switch (sample_count) {
643 case 2:
644 case 4:
645 case 8:
646 break;
647 default:
648 return FALSE;
649 }
650 }
651
652 if (usage & PIPE_BIND_SAMPLER_VIEW) {
653 if (target == PIPE_BUFFER) {
654 if (r600_is_vertex_format_supported(format))
655 retval |= PIPE_BIND_SAMPLER_VIEW;
656 } else {
657 if (r600_is_sampler_format_supported(screen, format))
658 retval |= PIPE_BIND_SAMPLER_VIEW;
659 }
660 }
661
662 if ((usage & (PIPE_BIND_RENDER_TARGET |
663 PIPE_BIND_DISPLAY_TARGET |
664 PIPE_BIND_SCANOUT |
665 PIPE_BIND_SHARED)) &&
666 r600_is_colorbuffer_format_supported(format)) {
667 retval |= usage &
668 (PIPE_BIND_RENDER_TARGET |
669 PIPE_BIND_DISPLAY_TARGET |
670 PIPE_BIND_SCANOUT |
671 PIPE_BIND_SHARED);
672 }
673
674 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
675 r600_is_zs_format_supported(format)) {
676 retval |= PIPE_BIND_DEPTH_STENCIL;
677 }
678
679 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
680 r600_is_vertex_format_supported(format)) {
681 retval |= PIPE_BIND_VERTEX_BUFFER;
682 }
683
684 if (usage & PIPE_BIND_TRANSFER_READ)
685 retval |= PIPE_BIND_TRANSFER_READ;
686 if (usage & PIPE_BIND_TRANSFER_WRITE)
687 retval |= PIPE_BIND_TRANSFER_WRITE;
688
689 return retval == usage;
690 }
691
692 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
693 {
694 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
695 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
696 float offset_units = state->offset_units;
697 float offset_scale = state->offset_scale;
698
699 switch (state->zs_format) {
700 case PIPE_FORMAT_Z24X8_UNORM:
701 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
702 offset_units *= 2.0f;
703 break;
704 case PIPE_FORMAT_Z16_UNORM:
705 offset_units *= 4.0f;
706 break;
707 default:;
708 }
709
710 r600_write_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
711 radeon_emit(cs, fui(offset_scale));
712 radeon_emit(cs, fui(offset_units));
713 radeon_emit(cs, fui(offset_scale));
714 radeon_emit(cs, fui(offset_units));
715 }
716
717 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
718 {
719 int j = state->independent_blend_enable ? i : 0;
720
721 unsigned eqRGB = state->rt[j].rgb_func;
722 unsigned srcRGB = state->rt[j].rgb_src_factor;
723 unsigned dstRGB = state->rt[j].rgb_dst_factor;
724
725 unsigned eqA = state->rt[j].alpha_func;
726 unsigned srcA = state->rt[j].alpha_src_factor;
727 unsigned dstA = state->rt[j].alpha_dst_factor;
728 uint32_t bc = 0;
729
730 if (!state->rt[j].blend_enable)
731 return 0;
732
733 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
734 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
735 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
736
737 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
738 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
739 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
740 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
741 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
742 }
743 return bc;
744 }
745
746 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
747 const struct pipe_blend_state *state,
748 int mode)
749 {
750 struct r600_context *rctx = (struct r600_context *)ctx;
751 uint32_t color_control = 0, target_mask = 0;
752 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
753
754 if (!blend) {
755 return NULL;
756 }
757
758 r600_init_command_buffer(&blend->buffer, 20);
759 r600_init_command_buffer(&blend->buffer_no_blend, 20);
760
761 /* R600 does not support per-MRT blends */
762 if (rctx->b.family > CHIP_R600)
763 color_control |= S_028808_PER_MRT_BLEND(1);
764
765 if (state->logicop_enable) {
766 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
767 } else {
768 color_control |= (0xcc << 16);
769 }
770 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
771 if (state->independent_blend_enable) {
772 for (int i = 0; i < 8; i++) {
773 if (state->rt[i].blend_enable) {
774 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
775 }
776 target_mask |= (state->rt[i].colormask << (4 * i));
777 }
778 } else {
779 for (int i = 0; i < 8; i++) {
780 if (state->rt[0].blend_enable) {
781 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
782 }
783 target_mask |= (state->rt[0].colormask << (4 * i));
784 }
785 }
786
787 if (target_mask)
788 color_control |= S_028808_SPECIAL_OP(mode);
789 else
790 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
791
792 /* only MRT0 has dual src blend */
793 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
794 blend->cb_target_mask = target_mask;
795 blend->cb_color_control = color_control;
796 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
797 blend->alpha_to_one = state->alpha_to_one;
798
799 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
800 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
801 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
802 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
803 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
804 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
805
806 /* Copy over the registers set so far into buffer_no_blend. */
807 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
808 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
809
810 /* Only add blend registers if blending is enabled. */
811 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
812 return blend;
813 }
814
815 /* The first R600 does not support per-MRT blends */
816 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
817 r600_get_blend_control(state, 0));
818
819 if (rctx->b.family > CHIP_R600) {
820 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
821 for (int i = 0; i < 8; i++) {
822 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
823 }
824 }
825 return blend;
826 }
827
828 static void *r600_create_blend_state(struct pipe_context *ctx,
829 const struct pipe_blend_state *state)
830 {
831 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
832 }
833
834 static void *r600_create_dsa_state(struct pipe_context *ctx,
835 const struct pipe_depth_stencil_alpha_state *state)
836 {
837 unsigned db_depth_control, alpha_test_control, alpha_ref;
838 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
839
840 if (dsa == NULL) {
841 return NULL;
842 }
843
844 r600_init_command_buffer(&dsa->buffer, 3);
845
846 dsa->valuemask[0] = state->stencil[0].valuemask;
847 dsa->valuemask[1] = state->stencil[1].valuemask;
848 dsa->writemask[0] = state->stencil[0].writemask;
849 dsa->writemask[1] = state->stencil[1].writemask;
850 dsa->zwritemask = state->depth.writemask;
851
852 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
853 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
854 S_028800_ZFUNC(state->depth.func);
855
856 /* stencil */
857 if (state->stencil[0].enabled) {
858 db_depth_control |= S_028800_STENCIL_ENABLE(1);
859 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
860 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
861 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
862 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
863
864 if (state->stencil[1].enabled) {
865 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
866 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
867 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
868 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
869 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
870 }
871 }
872
873 /* alpha */
874 alpha_test_control = 0;
875 alpha_ref = 0;
876 if (state->alpha.enabled) {
877 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
878 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
879 alpha_ref = fui(state->alpha.ref_value);
880 }
881 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
882 dsa->alpha_ref = alpha_ref;
883
884 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
885 return dsa;
886 }
887
888 static void *r600_create_rs_state(struct pipe_context *ctx,
889 const struct pipe_rasterizer_state *state)
890 {
891 struct r600_context *rctx = (struct r600_context *)ctx;
892 unsigned tmp, sc_mode_cntl, spi_interp;
893 float psize_min, psize_max;
894 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
895
896 if (rs == NULL) {
897 return NULL;
898 }
899
900 r600_init_command_buffer(&rs->buffer, 30);
901
902 rs->flatshade = state->flatshade;
903 rs->sprite_coord_enable = state->sprite_coord_enable;
904 rs->two_side = state->light_twoside;
905 rs->clip_plane_enable = state->clip_plane_enable;
906 rs->pa_sc_line_stipple = state->line_stipple_enable ?
907 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
908 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
909 rs->pa_cl_clip_cntl =
910 S_028810_PS_UCP_MODE(3) |
911 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
912 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
913 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
914 rs->multisample_enable = state->multisample;
915
916 /* offset */
917 rs->offset_units = state->offset_units;
918 rs->offset_scale = state->offset_scale * 12.0f;
919 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
920
921 if (state->point_size_per_vertex) {
922 psize_min = util_get_min_point_size(state);
923 psize_max = 8192;
924 } else {
925 /* Force the point size to be as if the vertex output was disabled. */
926 psize_min = state->point_size;
927 psize_max = state->point_size;
928 }
929
930 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
931 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
932 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
933 if (rctx->b.chip_class >= R700) {
934 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
935 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
936 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
937 } else {
938 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
939 rs->scissor_enable = state->scissor;
940 }
941
942 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
943 if (state->sprite_coord_enable) {
944 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
945 S_0286D4_PNT_SPRITE_OVRD_X(2) |
946 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
947 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
948 S_0286D4_PNT_SPRITE_OVRD_W(1);
949 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
950 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
951 }
952 }
953
954 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
955 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
956 tmp = r600_pack_float_12p4(state->point_size/2);
957 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
958 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
959 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
960 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
961 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
962 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
963 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
964
965 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
966 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
967 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
968 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
969 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
970 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
971 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
972 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
973 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
974 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
975 S_028814_FACE(!state->front_ccw) |
976 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
977 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
978 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
979 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
980 state->fill_back != PIPE_POLYGON_MODE_FILL) |
981 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
982 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
983 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
984 return rs;
985 }
986
987 static void *r600_create_sampler_state(struct pipe_context *ctx,
988 const struct pipe_sampler_state *state)
989 {
990 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
991 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
992
993 if (ss == NULL) {
994 return NULL;
995 }
996
997 ss->seamless_cube_map = state->seamless_cube_map;
998 ss->border_color_use = sampler_state_needs_border_color(state);
999
1000 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
1001 ss->tex_sampler_words[0] =
1002 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1003 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1004 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1005 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
1006 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
1007 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1008 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
1009 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1010 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
1011 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
1012 ss->tex_sampler_words[1] =
1013 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1014 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1015 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
1016 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
1017 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
1018
1019 if (ss->border_color_use) {
1020 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
1021 }
1022 return ss;
1023 }
1024
1025 static struct pipe_sampler_view *
1026 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
1027 unsigned width0, unsigned height0)
1028
1029 {
1030 struct pipe_context *ctx = view->base.context;
1031 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
1032 uint64_t va;
1033 int stride = util_format_get_blocksize(view->base.format);
1034 unsigned format, num_format, format_comp, endian;
1035 unsigned offset = view->base.u.buf.first_element * stride;
1036 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
1037
1038 r600_vertex_data_type(view->base.format,
1039 &format, &num_format, &format_comp,
1040 &endian);
1041
1042 va = r600_resource_va(ctx->screen, view->base.texture) + offset;
1043 view->tex_resource = &tmp->resource;
1044
1045 view->skip_mip_address_reloc = true;
1046 view->tex_resource_words[0] = va;
1047 view->tex_resource_words[1] = size - 1;
1048 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(va >> 32UL) |
1049 S_038008_STRIDE(stride) |
1050 S_038008_DATA_FORMAT(format) |
1051 S_038008_NUM_FORMAT_ALL(num_format) |
1052 S_038008_FORMAT_COMP_ALL(format_comp) |
1053 S_038008_SRF_MODE_ALL(1) |
1054 S_038008_ENDIAN_SWAP(endian);
1055 view->tex_resource_words[3] = 0;
1056 /*
1057 * in theory dword 4 is for number of elements, for use with resinfo,
1058 * but it seems to utterly fail to work, the amd gpu shader analyser
1059 * uses a const buffer to store the element sizes for buffer txq
1060 */
1061 view->tex_resource_words[4] = 0;
1062 view->tex_resource_words[5] = 0;
1063 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
1064 return &view->base;
1065 }
1066
1067 struct pipe_sampler_view *
1068 r600_create_sampler_view_custom(struct pipe_context *ctx,
1069 struct pipe_resource *texture,
1070 const struct pipe_sampler_view *state,
1071 unsigned width_first_level, unsigned height_first_level)
1072 {
1073 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1074 struct r600_texture *tmp = (struct r600_texture*)texture;
1075 unsigned format, endian;
1076 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1077 unsigned char swizzle[4], array_mode = 0;
1078 unsigned width, height, depth, offset_level, last_level;
1079
1080 if (view == NULL)
1081 return NULL;
1082
1083 /* initialize base object */
1084 view->base = *state;
1085 view->base.texture = NULL;
1086 pipe_reference(NULL, &texture->reference);
1087 view->base.texture = texture;
1088 view->base.reference.count = 1;
1089 view->base.context = ctx;
1090
1091 if (texture->target == PIPE_BUFFER)
1092 return texture_buffer_sampler_view(view, texture->width0, 1);
1093
1094 swizzle[0] = state->swizzle_r;
1095 swizzle[1] = state->swizzle_g;
1096 swizzle[2] = state->swizzle_b;
1097 swizzle[3] = state->swizzle_a;
1098
1099 format = r600_translate_texformat(ctx->screen, state->format,
1100 swizzle,
1101 &word4, &yuv_format);
1102 assert(format != ~0);
1103 if (format == ~0) {
1104 FREE(view);
1105 return NULL;
1106 }
1107
1108 if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) {
1109 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1110 FREE(view);
1111 return NULL;
1112 }
1113 tmp = tmp->flushed_depth_texture;
1114 }
1115
1116 endian = r600_colorformat_endian_swap(format);
1117
1118 offset_level = state->u.tex.first_level;
1119 last_level = state->u.tex.last_level - offset_level;
1120 width = width_first_level;
1121 height = height_first_level;
1122 depth = u_minify(texture->depth0, offset_level);
1123 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1124
1125 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1126 height = 1;
1127 depth = texture->array_size;
1128 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1129 depth = texture->array_size;
1130 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
1131 depth = texture->array_size / 6;
1132 switch (tmp->surface.level[offset_level].mode) {
1133 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1134 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1135 break;
1136 case RADEON_SURF_MODE_1D:
1137 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1138 break;
1139 case RADEON_SURF_MODE_2D:
1140 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1141 break;
1142 case RADEON_SURF_MODE_LINEAR:
1143 default:
1144 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1145 break;
1146 }
1147
1148 view->tex_resource = &tmp->resource;
1149 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1150 S_038000_TILE_MODE(array_mode) |
1151 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
1152 S_038000_PITCH((pitch / 8) - 1) |
1153 S_038000_TEX_WIDTH(width - 1));
1154 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
1155 S_038004_TEX_DEPTH(depth - 1) |
1156 S_038004_DATA_FORMAT(format));
1157 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
1158 if (offset_level >= tmp->surface.last_level) {
1159 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
1160 } else {
1161 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1162 }
1163 view->tex_resource_words[4] = (word4 |
1164 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1165 S_038010_REQUEST_SIZE(1) |
1166 S_038010_ENDIAN_SWAP(endian) |
1167 S_038010_BASE_LEVEL(0));
1168 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1169 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1170 if (texture->nr_samples > 1) {
1171 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1172 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
1173 } else {
1174 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
1175 }
1176 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1177 S_038018_MAX_ANISO(4 /* max 16 samples */));
1178 return &view->base;
1179 }
1180
1181 static struct pipe_sampler_view *
1182 r600_create_sampler_view(struct pipe_context *ctx,
1183 struct pipe_resource *tex,
1184 const struct pipe_sampler_view *state)
1185 {
1186 return r600_create_sampler_view_custom(ctx, tex, state,
1187 u_minify(tex->width0, state->u.tex.first_level),
1188 u_minify(tex->height0, state->u.tex.first_level));
1189 }
1190
1191 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1192 {
1193 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1194 struct pipe_clip_state *state = &rctx->clip_state.state;
1195
1196 r600_write_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
1197 radeon_emit_array(cs, (unsigned*)state, 6*4);
1198 }
1199
1200 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1201 const struct pipe_poly_stipple *state)
1202 {
1203 }
1204
1205 static void r600_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
1206 {
1207 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1208 struct pipe_scissor_state *state = &rctx->scissor.scissor;
1209
1210 if (rctx->b.chip_class != R600 || rctx->scissor.enable) {
1211 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1212 radeon_emit(cs, S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) |
1213 S_028240_WINDOW_OFFSET_DISABLE(1));
1214 radeon_emit(cs, S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy));
1215 } else {
1216 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1217 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1218 S_028240_WINDOW_OFFSET_DISABLE(1));
1219 radeon_emit(cs, S_028244_BR_X(8192) | S_028244_BR_Y(8192));
1220 }
1221 }
1222
1223 static void r600_set_scissor_states(struct pipe_context *ctx,
1224 unsigned start_slot,
1225 unsigned num_scissors,
1226 const struct pipe_scissor_state *state)
1227 {
1228 struct r600_context *rctx = (struct r600_context *)ctx;
1229
1230 rctx->scissor.scissor = *state;
1231
1232 if (rctx->b.chip_class == R600 && !rctx->scissor.enable)
1233 return;
1234
1235 rctx->scissor.atom.dirty = true;
1236 }
1237
1238 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
1239 unsigned size, unsigned alignment)
1240 {
1241 struct pipe_resource buffer;
1242
1243 memset(&buffer, 0, sizeof buffer);
1244 buffer.target = PIPE_BUFFER;
1245 buffer.format = PIPE_FORMAT_R8_UNORM;
1246 buffer.bind = PIPE_BIND_CUSTOM;
1247 buffer.usage = PIPE_USAGE_STATIC;
1248 buffer.flags = 0;
1249 buffer.width0 = size;
1250 buffer.height0 = 1;
1251 buffer.depth0 = 1;
1252 buffer.array_size = 1;
1253
1254 return (struct r600_resource*)
1255 r600_buffer_create(&rscreen->b.b, &buffer, alignment);
1256 }
1257
1258 static void r600_init_color_surface(struct r600_context *rctx,
1259 struct r600_surface *surf,
1260 bool force_cmask_fmask)
1261 {
1262 struct r600_screen *rscreen = rctx->screen;
1263 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1264 unsigned level = surf->base.u.tex.level;
1265 unsigned pitch, slice;
1266 unsigned color_info;
1267 unsigned format, swap, ntype, endian;
1268 unsigned offset;
1269 const struct util_format_description *desc;
1270 int i;
1271 bool blend_bypass = 0, blend_clamp = 1;
1272
1273 if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
1274 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
1275 rtex = rtex->flushed_depth_texture;
1276 assert(rtex);
1277 }
1278
1279 offset = rtex->surface.level[level].offset;
1280 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1281 offset += rtex->surface.level[level].slice_size *
1282 surf->base.u.tex.first_layer;
1283 }
1284 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1285 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1286 if (slice) {
1287 slice = slice - 1;
1288 }
1289 color_info = 0;
1290 switch (rtex->surface.level[level].mode) {
1291 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1292 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1293 break;
1294 case RADEON_SURF_MODE_1D:
1295 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1296 break;
1297 case RADEON_SURF_MODE_2D:
1298 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1299 break;
1300 case RADEON_SURF_MODE_LINEAR:
1301 default:
1302 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1303 break;
1304 }
1305
1306 desc = util_format_description(surf->base.format);
1307
1308 for (i = 0; i < 4; i++) {
1309 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1310 break;
1311 }
1312 }
1313
1314 ntype = V_0280A0_NUMBER_UNORM;
1315 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1316 ntype = V_0280A0_NUMBER_SRGB;
1317 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1318 if (desc->channel[i].normalized)
1319 ntype = V_0280A0_NUMBER_SNORM;
1320 else if (desc->channel[i].pure_integer)
1321 ntype = V_0280A0_NUMBER_SINT;
1322 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1323 if (desc->channel[i].normalized)
1324 ntype = V_0280A0_NUMBER_UNORM;
1325 else if (desc->channel[i].pure_integer)
1326 ntype = V_0280A0_NUMBER_UINT;
1327 }
1328
1329 format = r600_translate_colorformat(surf->base.format);
1330 assert(format != ~0);
1331
1332 swap = r600_translate_colorswap(surf->base.format);
1333 assert(swap != ~0);
1334
1335 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1336 endian = ENDIAN_NONE;
1337 } else {
1338 endian = r600_colorformat_endian_swap(format);
1339 }
1340
1341 /* set blend bypass according to docs if SINT/UINT or
1342 8/24 COLOR variants */
1343 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1344 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1345 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1346 blend_clamp = 0;
1347 blend_bypass = 1;
1348 }
1349
1350 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
1351
1352 color_info |= S_0280A0_FORMAT(format) |
1353 S_0280A0_COMP_SWAP(swap) |
1354 S_0280A0_BLEND_BYPASS(blend_bypass) |
1355 S_0280A0_BLEND_CLAMP(blend_clamp) |
1356 S_0280A0_NUMBER_TYPE(ntype) |
1357 S_0280A0_ENDIAN(endian);
1358
1359 /* EXPORT_NORM is an optimzation that can be enabled for better
1360 * performance in certain cases
1361 */
1362 if (rctx->b.chip_class == R600) {
1363 /* EXPORT_NORM can be enabled if:
1364 * - 11-bit or smaller UNORM/SNORM/SRGB
1365 * - BLEND_CLAMP is enabled
1366 * - BLEND_FLOAT32 is disabled
1367 */
1368 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1369 (desc->channel[i].size < 12 &&
1370 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1371 ntype != V_0280A0_NUMBER_UINT &&
1372 ntype != V_0280A0_NUMBER_SINT) &&
1373 G_0280A0_BLEND_CLAMP(color_info) &&
1374 !G_0280A0_BLEND_FLOAT32(color_info)) {
1375 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1376 surf->export_16bpc = true;
1377 }
1378 } else {
1379 /* EXPORT_NORM can be enabled if:
1380 * - 11-bit or smaller UNORM/SNORM/SRGB
1381 * - 16-bit or smaller FLOAT
1382 */
1383 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1384 ((desc->channel[i].size < 12 &&
1385 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1386 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1387 (desc->channel[i].size < 17 &&
1388 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1389 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1390 surf->export_16bpc = true;
1391 }
1392 }
1393
1394 /* These might not always be initialized to zero. */
1395 surf->cb_color_base = offset >> 8;
1396 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
1397 S_028060_SLICE_TILE_MAX(slice);
1398 surf->cb_color_fmask = surf->cb_color_base;
1399 surf->cb_color_cmask = surf->cb_color_base;
1400 surf->cb_color_mask = 0;
1401
1402 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1403 &rtex->resource.b.b);
1404 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1405 &rtex->resource.b.b);
1406
1407 if (rtex->cmask.size) {
1408 surf->cb_color_cmask = rtex->cmask.offset >> 8;
1409 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
1410
1411 if (rtex->fmask.size) {
1412 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1413 surf->cb_color_fmask = rtex->fmask.offset >> 8;
1414 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
1415 } else { /* cmask only */
1416 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
1417 }
1418 } else if (force_cmask_fmask) {
1419 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1420 *
1421 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1422 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1423 * because it's not an MSAA buffer.
1424 */
1425 struct r600_cmask_info cmask;
1426 struct r600_fmask_info fmask;
1427
1428 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
1429 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
1430
1431 /* CMASK. */
1432 if (!rctx->dummy_cmask ||
1433 rctx->dummy_cmask->buf->size < cmask.size ||
1434 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1435 struct pipe_transfer *transfer;
1436 void *ptr;
1437
1438 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1439 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1440
1441 /* Set the contents to 0xCC. */
1442 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1443 memset(ptr, 0xCC, cmask.size);
1444 pipe_buffer_unmap(&rctx->b.b, transfer);
1445 }
1446 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1447 &rctx->dummy_cmask->b.b);
1448
1449 /* FMASK. */
1450 if (!rctx->dummy_fmask ||
1451 rctx->dummy_fmask->buf->size < fmask.size ||
1452 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1453 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1454 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1455
1456 }
1457 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1458 &rctx->dummy_fmask->b.b);
1459
1460 /* Init the registers. */
1461 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1462 surf->cb_color_cmask = 0;
1463 surf->cb_color_fmask = 0;
1464 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1465 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1466 }
1467
1468 surf->cb_color_info = color_info;
1469
1470 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1471 surf->cb_color_view = 0;
1472 } else {
1473 surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
1474 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
1475 }
1476
1477 surf->color_initialized = true;
1478 }
1479
1480 static void r600_init_depth_surface(struct r600_context *rctx,
1481 struct r600_surface *surf)
1482 {
1483 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1484 unsigned level, pitch, slice, format, offset, array_mode;
1485
1486 level = surf->base.u.tex.level;
1487 offset = rtex->surface.level[level].offset;
1488 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1489 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1490 if (slice) {
1491 slice = slice - 1;
1492 }
1493 switch (rtex->surface.level[level].mode) {
1494 case RADEON_SURF_MODE_2D:
1495 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1496 break;
1497 case RADEON_SURF_MODE_1D:
1498 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1499 case RADEON_SURF_MODE_LINEAR:
1500 default:
1501 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1502 break;
1503 }
1504
1505 format = r600_translate_dbformat(surf->base.format);
1506 assert(format != ~0);
1507
1508 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1509 surf->db_depth_base = offset >> 8;
1510 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1511 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1512 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1513 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1514
1515 switch (surf->base.format) {
1516 case PIPE_FORMAT_Z24X8_UNORM:
1517 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1518 surf->pa_su_poly_offset_db_fmt_cntl =
1519 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1520 break;
1521 case PIPE_FORMAT_Z32_FLOAT:
1522 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1523 surf->pa_su_poly_offset_db_fmt_cntl =
1524 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1525 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1526 break;
1527 case PIPE_FORMAT_Z16_UNORM:
1528 surf->pa_su_poly_offset_db_fmt_cntl =
1529 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1530 break;
1531 default:;
1532 }
1533
1534 surf->htile_enabled = 0;
1535 /* use htile only for first level */
1536 if (rtex->htile_buffer && !level) {
1537 uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile_buffer->b.b);
1538 surf->htile_enabled = 1;
1539 surf->db_htile_data_base = va >> 8;
1540 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1541 S_028D24_HTILE_HEIGHT(1) |
1542 S_028D24_FULL_CACHE(1) |
1543 S_028D24_LINEAR(1);
1544 /* preload is not working properly on r6xx/r7xx */
1545 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1546 }
1547
1548 surf->depth_initialized = true;
1549 }
1550
1551 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1552 const struct pipe_framebuffer_state *state)
1553 {
1554 struct r600_context *rctx = (struct r600_context *)ctx;
1555 struct r600_surface *surf;
1556 struct r600_texture *rtex;
1557 unsigned i;
1558
1559 if (rctx->framebuffer.state.nr_cbufs) {
1560 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1561 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB;
1562
1563 if (rctx->b.chip_class >= R700 &&
1564 rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
1565 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
1566 }
1567 }
1568 if (rctx->framebuffer.state.zsbuf) {
1569 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1570 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1571
1572 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1573 if (rctx->b.chip_class >= R700 && rtex->htile_buffer) {
1574 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1575 }
1576 }
1577
1578 /* Set the new state. */
1579 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1580
1581 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1582 rctx->framebuffer.cb0_is_integer = state->nr_cbufs &&
1583 util_format_is_pure_integer(state->cbufs[0]->format);
1584 rctx->framebuffer.compressed_cb_mask = 0;
1585 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1586 state->cbufs[0]->texture->nr_samples > 1 &&
1587 state->cbufs[1]->texture->nr_samples <= 1;
1588
1589 if (state->nr_cbufs)
1590 rctx->framebuffer.nr_samples = state->cbufs[0]->texture->nr_samples;
1591 else if (state->zsbuf)
1592 rctx->framebuffer.nr_samples = state->zsbuf->texture->nr_samples;
1593 else
1594 rctx->framebuffer.nr_samples = 0;
1595
1596 /* Colorbuffers. */
1597 for (i = 0; i < state->nr_cbufs; i++) {
1598 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1599 bool force_cmask_fmask = rctx->b.chip_class == R600 &&
1600 rctx->framebuffer.is_msaa_resolve &&
1601 i == 1;
1602
1603 surf = (struct r600_surface*)state->cbufs[i];
1604 rtex = (struct r600_texture*)surf->base.texture;
1605 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1606
1607 if (!surf->color_initialized || force_cmask_fmask) {
1608 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1609 if (force_cmask_fmask) {
1610 /* re-initialize later without compression */
1611 surf->color_initialized = false;
1612 }
1613 }
1614
1615 if (!surf->export_16bpc) {
1616 rctx->framebuffer.export_16bpc = false;
1617 }
1618
1619 if (rtex->fmask.size && rtex->cmask.size) {
1620 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1621 }
1622 }
1623
1624 /* Update alpha-test state dependencies.
1625 * Alpha-test is done on the first colorbuffer only. */
1626 if (state->nr_cbufs) {
1627 surf = (struct r600_surface*)state->cbufs[0];
1628 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1629 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1630 rctx->alphatest_state.atom.dirty = true;
1631 }
1632 }
1633
1634 /* ZS buffer. */
1635 if (state->zsbuf) {
1636 surf = (struct r600_surface*)state->zsbuf;
1637
1638 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1639
1640 if (!surf->depth_initialized) {
1641 r600_init_depth_surface(rctx, surf);
1642 }
1643
1644 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1645 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1646 rctx->poly_offset_state.atom.dirty = true;
1647 }
1648
1649 if (rctx->db_state.rsurf != surf) {
1650 rctx->db_state.rsurf = surf;
1651 rctx->db_state.atom.dirty = true;
1652 rctx->db_misc_state.atom.dirty = true;
1653 }
1654 } else if (rctx->db_state.rsurf) {
1655 rctx->db_state.rsurf = NULL;
1656 rctx->db_state.atom.dirty = true;
1657 rctx->db_misc_state.atom.dirty = true;
1658 }
1659
1660 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1661 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1662 rctx->cb_misc_state.atom.dirty = true;
1663 }
1664
1665 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1666 rctx->alphatest_state.bypass = false;
1667 rctx->alphatest_state.atom.dirty = true;
1668 }
1669
1670 r600_update_db_shader_control(rctx);
1671
1672 /* Calculate the CS size. */
1673 rctx->framebuffer.atom.num_dw =
1674 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1675
1676 if (rctx->framebuffer.state.nr_cbufs) {
1677 rctx->framebuffer.atom.num_dw += 6 * (2 + rctx->framebuffer.state.nr_cbufs);
1678 rctx->framebuffer.atom.num_dw += 6 * rctx->framebuffer.state.nr_cbufs; /* relocs */
1679
1680 }
1681 if (rctx->framebuffer.state.zsbuf) {
1682 rctx->framebuffer.atom.num_dw += 18;
1683 } else if (rctx->screen->b.info.drm_minor >= 18) {
1684 rctx->framebuffer.atom.num_dw += 3;
1685 }
1686 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1687 rctx->framebuffer.atom.num_dw += 2;
1688 }
1689
1690 rctx->framebuffer.atom.dirty = true;
1691 }
1692
1693 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1694 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1695 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1696 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1697 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1698
1699
1700 static uint32_t sample_locs_2x[] = {
1701 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1702 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1703 };
1704 static unsigned max_dist_2x = 4;
1705
1706 static uint32_t sample_locs_4x[] = {
1707 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1708 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1709 };
1710 static unsigned max_dist_4x = 6;
1711 static uint32_t sample_locs_8x[] = {
1712 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1713 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1714 };
1715 static unsigned max_dist_8x = 7;
1716
1717 static void r600_get_sample_position(struct pipe_context *ctx,
1718 unsigned sample_count,
1719 unsigned sample_index,
1720 float *out_value)
1721 {
1722 int offset, index;
1723 struct {
1724 int idx:4;
1725 } val;
1726 switch (sample_count) {
1727 case 1:
1728 default:
1729 out_value[0] = out_value[1] = 0.5;
1730 break;
1731 case 2:
1732 offset = 4 * (sample_index * 2);
1733 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1734 out_value[0] = (float)(val.idx + 8) / 16.0f;
1735 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1736 out_value[1] = (float)(val.idx + 8) / 16.0f;
1737 break;
1738 case 4:
1739 offset = 4 * (sample_index * 2);
1740 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1741 out_value[0] = (float)(val.idx + 8) / 16.0f;
1742 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1743 out_value[1] = (float)(val.idx + 8) / 16.0f;
1744 break;
1745 case 8:
1746 offset = 4 * (sample_index % 4 * 2);
1747 index = (sample_index / 4);
1748 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1749 out_value[0] = (float)(val.idx + 8) / 16.0f;
1750 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1751 out_value[1] = (float)(val.idx + 8) / 16.0f;
1752 break;
1753 }
1754 }
1755
1756 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1757 {
1758 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1759 unsigned max_dist = 0;
1760
1761 if (rctx->b.family == CHIP_R600) {
1762 switch (nr_samples) {
1763 default:
1764 nr_samples = 0;
1765 break;
1766 case 2:
1767 r600_write_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1768 max_dist = max_dist_2x;
1769 break;
1770 case 4:
1771 r600_write_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1772 max_dist = max_dist_4x;
1773 break;
1774 case 8:
1775 r600_write_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1776 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1777 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1778 max_dist = max_dist_8x;
1779 break;
1780 }
1781 } else {
1782 switch (nr_samples) {
1783 default:
1784 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1785 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1786 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1787 nr_samples = 0;
1788 break;
1789 case 2:
1790 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1791 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1792 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1793 max_dist = max_dist_2x;
1794 break;
1795 case 4:
1796 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1797 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1798 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1799 max_dist = max_dist_4x;
1800 break;
1801 case 8:
1802 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1803 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1804 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1805 max_dist = max_dist_8x;
1806 break;
1807 }
1808 }
1809
1810 if (nr_samples > 1) {
1811 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1812 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1813 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1814 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1815 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1816 } else {
1817 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1818 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1819 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1820 }
1821 }
1822
1823 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1824 {
1825 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1826 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1827 unsigned nr_cbufs = state->nr_cbufs;
1828 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1829 unsigned i, sbu = 0;
1830
1831 /* Colorbuffers. */
1832 r600_write_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1833 for (i = 0; i < nr_cbufs; i++) {
1834 radeon_emit(cs, cb[i]->cb_color_info);
1835 }
1836 /* set CB_COLOR1_INFO for possible dual-src blending */
1837 if (i == 1) {
1838 radeon_emit(cs, cb[0]->cb_color_info);
1839 i++;
1840 }
1841 for (; i < 8; i++) {
1842 radeon_emit(cs, 0);
1843 }
1844
1845 if (nr_cbufs) {
1846 /* COLOR_BASE */
1847 r600_write_context_reg_seq(cs, R_028040_CB_COLOR0_BASE, nr_cbufs);
1848 for (i = 0; i < nr_cbufs; i++) {
1849 radeon_emit(cs, cb[i]->cb_color_base);
1850 }
1851
1852 /* relocations */
1853 for (i = 0; i < nr_cbufs; i++) {
1854 unsigned reloc = r600_context_bo_reloc(&rctx->b,
1855 &rctx->b.rings.gfx,
1856 (struct r600_resource*)cb[i]->base.texture,
1857 RADEON_USAGE_READWRITE);
1858 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1859 radeon_emit(cs, reloc);
1860 }
1861
1862 r600_write_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1863 for (i = 0; i < nr_cbufs; i++) {
1864 radeon_emit(cs, cb[i]->cb_color_size);
1865 }
1866
1867 r600_write_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1868 for (i = 0; i < nr_cbufs; i++) {
1869 radeon_emit(cs, cb[i]->cb_color_view);
1870 }
1871
1872 r600_write_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1873 for (i = 0; i < nr_cbufs; i++) {
1874 radeon_emit(cs, cb[i]->cb_color_mask);
1875 }
1876
1877 /* FMASK. */
1878 r600_write_context_reg_seq(cs, R_0280E0_CB_COLOR0_FRAG, nr_cbufs);
1879 for (i = 0; i < nr_cbufs; i++) {
1880 radeon_emit(cs, cb[i]->cb_color_fmask);
1881 }
1882 /* relocations */
1883 for (i = 0; i < nr_cbufs; i++) {
1884 unsigned reloc = r600_context_bo_reloc(&rctx->b,
1885 &rctx->b.rings.gfx,
1886 cb[i]->cb_buffer_fmask,
1887 RADEON_USAGE_READWRITE);
1888 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1889 radeon_emit(cs, reloc);
1890 }
1891
1892 /* CMASK. */
1893 r600_write_context_reg_seq(cs, R_0280C0_CB_COLOR0_TILE, nr_cbufs);
1894 for (i = 0; i < nr_cbufs; i++) {
1895 radeon_emit(cs, cb[i]->cb_color_cmask);
1896 }
1897 /* relocations */
1898 for (i = 0; i < nr_cbufs; i++) {
1899 unsigned reloc = r600_context_bo_reloc(&rctx->b,
1900 &rctx->b.rings.gfx,
1901 cb[i]->cb_buffer_cmask,
1902 RADEON_USAGE_READWRITE);
1903 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1904 radeon_emit(cs, reloc);
1905 }
1906
1907 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1908 }
1909
1910 /* SURFACE_BASE_UPDATE */
1911 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1912 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1913 radeon_emit(cs, sbu);
1914 sbu = 0;
1915 }
1916
1917 /* Zbuffer. */
1918 if (state->zsbuf) {
1919 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1920 unsigned reloc = r600_context_bo_reloc(&rctx->b,
1921 &rctx->b.rings.gfx,
1922 (struct r600_resource*)state->zsbuf->texture,
1923 RADEON_USAGE_READWRITE);
1924
1925 r600_write_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1926 surf->pa_su_poly_offset_db_fmt_cntl);
1927
1928 r600_write_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1929 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1930 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1931 r600_write_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1932 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1933 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1934
1935 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1936 radeon_emit(cs, reloc);
1937
1938 r600_write_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1939
1940 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1941 } else if (rctx->screen->b.info.drm_minor >= 18) {
1942 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1943 * Older kernels are out of luck. */
1944 r600_write_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1945 }
1946
1947 /* SURFACE_BASE_UPDATE */
1948 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1949 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1950 radeon_emit(cs, sbu);
1951 sbu = 0;
1952 }
1953
1954 /* Framebuffer dimensions. */
1955 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1956 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1957 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1958 radeon_emit(cs, S_028244_BR_X(state->width) |
1959 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1960
1961 if (rctx->framebuffer.is_msaa_resolve) {
1962 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1963 } else {
1964 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1965 * will assure that the alpha-test will work even if there is
1966 * no colorbuffer bound. */
1967 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1968 (1ull << MAX2(nr_cbufs, 1)) - 1);
1969 }
1970
1971 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1972 }
1973
1974 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1975 {
1976 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1977 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1978
1979 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1980 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1981 if (rctx->b.chip_class == R600) {
1982 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1983 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1984 } else {
1985 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1986 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1987 }
1988 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1989 } else {
1990 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1991 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1992 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1993
1994 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1995 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1996 /* Always enable the first color output to make sure alpha-test works even without one. */
1997 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1998 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1999 a->cb_color_control |
2000 S_028808_MULTIWRITE_ENABLE(multiwrite));
2001 }
2002 }
2003
2004 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
2005 {
2006 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2007 struct r600_db_state *a = (struct r600_db_state*)atom;
2008
2009 if (a->rsurf && a->rsurf->htile_enabled) {
2010 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
2011 unsigned reloc_idx;
2012
2013 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2014 r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
2015 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
2016 reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer, RADEON_USAGE_READWRITE);
2017 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
2018 cs->buf[cs->cdw++] = reloc_idx;
2019 } else {
2020 r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
2021 }
2022 }
2023
2024 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2025 {
2026 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2027 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
2028 unsigned db_render_control = 0;
2029 unsigned db_render_override =
2030 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
2031 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
2032
2033 if (a->occlusion_query_enabled) {
2034 if (rctx->b.chip_class >= R700) {
2035 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
2036 }
2037 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
2038 }
2039 if (rctx->db_state.rsurf && rctx->db_state.rsurf->htile_enabled) {
2040 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
2041 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
2042 /* This is to fix a lockup when hyperz and alpha test are enabled at
2043 * the same time somehow GPU get confuse on which order to pick for
2044 * z test
2045 */
2046 if (rctx->alphatest_state.sx_alpha_test_control) {
2047 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
2048 }
2049 } else {
2050 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
2051 }
2052 if (a->flush_depthstencil_through_cb) {
2053 assert(a->copy_depth || a->copy_stencil);
2054
2055 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
2056 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
2057 S_028D0C_COPY_CENTROID(1) |
2058 S_028D0C_COPY_SAMPLE(a->copy_sample);
2059 } else if (a->flush_depthstencil_in_place) {
2060 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(1) |
2061 S_028D0C_STENCIL_COMPRESS_DISABLE(1);
2062 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
2063 }
2064 if (a->htile_clear) {
2065 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
2066 }
2067
2068 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
2069 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
2070 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
2071 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
2072 }
2073
2074 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
2075 {
2076 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2077 struct r600_config_state *a = (struct r600_config_state*)atom;
2078
2079 r600_write_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
2080 }
2081
2082 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
2083 {
2084 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2085 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
2086
2087 while (dirty_mask) {
2088 struct pipe_vertex_buffer *vb;
2089 struct r600_resource *rbuffer;
2090 unsigned offset;
2091 unsigned buffer_index = u_bit_scan(&dirty_mask);
2092
2093 vb = &rctx->vertex_buffer_state.vb[buffer_index];
2094 rbuffer = (struct r600_resource*)vb->buffer;
2095 assert(rbuffer);
2096
2097 offset = vb->buffer_offset;
2098
2099 /* fetch resources start at index 320 */
2100 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
2101 radeon_emit(cs, (320 + buffer_index) * 7);
2102 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
2103 radeon_emit(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
2104 radeon_emit(cs, /* RESOURCEi_WORD2 */
2105 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
2106 S_038008_STRIDE(vb->stride));
2107 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
2108 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2109 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2110 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
2111
2112 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2113 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ));
2114 }
2115 }
2116
2117 static void r600_emit_constant_buffers(struct r600_context *rctx,
2118 struct r600_constbuf_state *state,
2119 unsigned buffer_id_base,
2120 unsigned reg_alu_constbuf_size,
2121 unsigned reg_alu_const_cache)
2122 {
2123 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2124 uint32_t dirty_mask = state->dirty_mask;
2125
2126 while (dirty_mask) {
2127 struct pipe_constant_buffer *cb;
2128 struct r600_resource *rbuffer;
2129 unsigned offset;
2130 unsigned buffer_index = ffs(dirty_mask) - 1;
2131
2132 cb = &state->cb[buffer_index];
2133 rbuffer = (struct r600_resource*)cb->buffer;
2134 assert(rbuffer);
2135
2136 offset = cb->buffer_offset;
2137
2138 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
2139 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
2140 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
2141
2142 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2143 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ));
2144
2145 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
2146 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
2147 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
2148 radeon_emit(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
2149 radeon_emit(cs, /* RESOURCEi_WORD2 */
2150 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
2151 S_038008_STRIDE(16));
2152 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
2153 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2154 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2155 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
2156
2157 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2158 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ));
2159
2160 dirty_mask &= ~(1 << buffer_index);
2161 }
2162 state->dirty_mask = 0;
2163 }
2164
2165 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2166 {
2167 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 160,
2168 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2169 R_028980_ALU_CONST_CACHE_VS_0);
2170 }
2171
2172 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2173 {
2174 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
2175 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2176 R_0289C0_ALU_CONST_CACHE_GS_0);
2177 }
2178
2179 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2180 {
2181 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
2182 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2183 R_028940_ALU_CONST_CACHE_PS_0);
2184 }
2185
2186 static void r600_emit_sampler_views(struct r600_context *rctx,
2187 struct r600_samplerview_state *state,
2188 unsigned resource_id_base)
2189 {
2190 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2191 uint32_t dirty_mask = state->dirty_mask;
2192
2193 while (dirty_mask) {
2194 struct r600_pipe_sampler_view *rview;
2195 unsigned resource_index = u_bit_scan(&dirty_mask);
2196 unsigned reloc;
2197
2198 rview = state->views[resource_index];
2199 assert(rview);
2200
2201 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
2202 radeon_emit(cs, (resource_id_base + resource_index) * 7);
2203 radeon_emit_array(cs, rview->tex_resource_words, 7);
2204
2205 reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->tex_resource,
2206 RADEON_USAGE_READ);
2207 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2208 radeon_emit(cs, reloc);
2209 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2210 radeon_emit(cs, reloc);
2211 }
2212 state->dirty_mask = 0;
2213 }
2214
2215 /* Resource IDs:
2216 * PS: 0 .. +160
2217 * VS: 160 .. +160
2218 * FS: 320 .. +16
2219 * GS: 336 .. +160
2220 */
2221
2222 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2223 {
2224 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 160 + R600_MAX_CONST_BUFFERS);
2225 }
2226
2227 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2228 {
2229 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
2230 }
2231
2232 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2233 {
2234 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
2235 }
2236
2237 static void r600_emit_sampler_states(struct r600_context *rctx,
2238 struct r600_textures_info *texinfo,
2239 unsigned resource_id_base,
2240 unsigned border_color_reg)
2241 {
2242 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2243 uint32_t dirty_mask = texinfo->states.dirty_mask;
2244
2245 while (dirty_mask) {
2246 struct r600_pipe_sampler_state *rstate;
2247 struct r600_pipe_sampler_view *rview;
2248 unsigned i = u_bit_scan(&dirty_mask);
2249
2250 rstate = texinfo->states.states[i];
2251 assert(rstate);
2252 rview = texinfo->views.views[i];
2253
2254 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
2255 * filtering between layers.
2256 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
2257 */
2258 if (rview) {
2259 enum pipe_texture_target target = rview->base.texture->target;
2260 if (target == PIPE_TEXTURE_1D_ARRAY ||
2261 target == PIPE_TEXTURE_2D_ARRAY) {
2262 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
2263 texinfo->is_array_sampler[i] = true;
2264 } else {
2265 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
2266 texinfo->is_array_sampler[i] = false;
2267 }
2268 }
2269
2270 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2271 radeon_emit(cs, (resource_id_base + i) * 3);
2272 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2273
2274 if (rstate->border_color_use) {
2275 unsigned offset;
2276
2277 offset = border_color_reg;
2278 offset += i * 16;
2279 r600_write_config_reg_seq(cs, offset, 4);
2280 radeon_emit_array(cs, rstate->border_color.ui, 4);
2281 }
2282 }
2283 texinfo->states.dirty_mask = 0;
2284 }
2285
2286 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2287 {
2288 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
2289 }
2290
2291 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2292 {
2293 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
2294 }
2295
2296 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2297 {
2298 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
2299 }
2300
2301 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
2302 {
2303 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2304 unsigned tmp;
2305
2306 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
2307 S_009508_SYNC_GRADIENT(1) |
2308 S_009508_SYNC_WALKER(1) |
2309 S_009508_SYNC_ALIGNER(1);
2310 if (!rctx->seamless_cube_map.enabled) {
2311 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
2312 }
2313 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
2314 }
2315
2316 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2317 {
2318 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2319 uint8_t mask = s->sample_mask;
2320
2321 r600_write_context_reg(rctx->b.rings.gfx.cs, R_028C48_PA_SC_AA_MASK,
2322 mask | (mask << 8) | (mask << 16) | (mask << 24));
2323 }
2324
2325 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2326 {
2327 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2328 struct r600_cso_state *state = (struct r600_cso_state*)a;
2329 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2330
2331 r600_write_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
2332 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2333 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->buffer, RADEON_USAGE_READ));
2334 }
2335
2336 /* Adjust GPR allocation on R6xx/R7xx */
2337 bool r600_adjust_gprs(struct r600_context *rctx)
2338 {
2339 unsigned num_ps_gprs = rctx->ps_shader->current->shader.bc.ngpr;
2340 unsigned num_vs_gprs = rctx->vs_shader->current->shader.bc.ngpr;
2341 unsigned new_num_ps_gprs = num_ps_gprs;
2342 unsigned new_num_vs_gprs = num_vs_gprs;
2343 unsigned cur_num_ps_gprs = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2344 unsigned cur_num_vs_gprs = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2345 unsigned def_num_ps_gprs = rctx->default_ps_gprs;
2346 unsigned def_num_vs_gprs = rctx->default_vs_gprs;
2347 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
2348 /* hardware will reserve twice num_clause_temp_gprs */
2349 unsigned max_gprs = def_num_ps_gprs + def_num_vs_gprs + def_num_clause_temp_gprs * 2;
2350 unsigned tmp;
2351
2352 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2353 if (new_num_ps_gprs > cur_num_ps_gprs || new_num_vs_gprs > cur_num_vs_gprs) {
2354 /* try to use switch back to default */
2355 if (new_num_ps_gprs > def_num_ps_gprs || new_num_vs_gprs > def_num_vs_gprs) {
2356 /* always privilege vs stage so that at worst we have the
2357 * pixel stage producing wrong output (not the vertex
2358 * stage) */
2359 new_num_ps_gprs = max_gprs - (new_num_vs_gprs + def_num_clause_temp_gprs * 2);
2360 new_num_vs_gprs = num_vs_gprs;
2361 } else {
2362 new_num_ps_gprs = def_num_ps_gprs;
2363 new_num_vs_gprs = def_num_vs_gprs;
2364 }
2365 } else {
2366 return true;
2367 }
2368
2369 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2370 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2371 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2372 * it will lockup. So in this case just discard the draw command
2373 * and don't change the current gprs repartitions.
2374 */
2375 if (num_ps_gprs > new_num_ps_gprs || num_vs_gprs > new_num_vs_gprs) {
2376 R600_ERR("ps & vs shader require too many register (%d + %d) "
2377 "for a combined maximum of %d\n",
2378 num_ps_gprs, num_vs_gprs, max_gprs);
2379 return false;
2380 }
2381
2382 /* in some case we endup recomputing the current value */
2383 tmp = S_008C04_NUM_PS_GPRS(new_num_ps_gprs) |
2384 S_008C04_NUM_VS_GPRS(new_num_vs_gprs) |
2385 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2386 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp) {
2387 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2388 rctx->config_state.atom.dirty = true;
2389 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2390 }
2391 return true;
2392 }
2393
2394 void r600_init_atom_start_cs(struct r600_context *rctx)
2395 {
2396 int ps_prio;
2397 int vs_prio;
2398 int gs_prio;
2399 int es_prio;
2400 int num_ps_gprs;
2401 int num_vs_gprs;
2402 int num_gs_gprs;
2403 int num_es_gprs;
2404 int num_temp_gprs;
2405 int num_ps_threads;
2406 int num_vs_threads;
2407 int num_gs_threads;
2408 int num_es_threads;
2409 int num_ps_stack_entries;
2410 int num_vs_stack_entries;
2411 int num_gs_stack_entries;
2412 int num_es_stack_entries;
2413 enum radeon_family family;
2414 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2415 uint32_t tmp;
2416
2417 r600_init_command_buffer(cb, 256);
2418
2419 /* R6xx requires this packet at the start of each command buffer */
2420 if (rctx->b.chip_class == R600) {
2421 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2422 r600_store_value(cb, 0);
2423 }
2424 /* All asics require this one */
2425 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2426 r600_store_value(cb, 0x80000000);
2427 r600_store_value(cb, 0x80000000);
2428
2429 /* We're setting config registers here. */
2430 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2431 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2432
2433 family = rctx->b.family;
2434 ps_prio = 0;
2435 vs_prio = 1;
2436 gs_prio = 2;
2437 es_prio = 3;
2438 switch (family) {
2439 case CHIP_R600:
2440 num_ps_gprs = 192;
2441 num_vs_gprs = 56;
2442 num_temp_gprs = 4;
2443 num_gs_gprs = 0;
2444 num_es_gprs = 0;
2445 num_ps_threads = 136;
2446 num_vs_threads = 48;
2447 num_gs_threads = 4;
2448 num_es_threads = 4;
2449 num_ps_stack_entries = 128;
2450 num_vs_stack_entries = 128;
2451 num_gs_stack_entries = 0;
2452 num_es_stack_entries = 0;
2453 break;
2454 case CHIP_RV630:
2455 case CHIP_RV635:
2456 num_ps_gprs = 84;
2457 num_vs_gprs = 36;
2458 num_temp_gprs = 4;
2459 num_gs_gprs = 0;
2460 num_es_gprs = 0;
2461 num_ps_threads = 144;
2462 num_vs_threads = 40;
2463 num_gs_threads = 4;
2464 num_es_threads = 4;
2465 num_ps_stack_entries = 40;
2466 num_vs_stack_entries = 40;
2467 num_gs_stack_entries = 32;
2468 num_es_stack_entries = 16;
2469 break;
2470 case CHIP_RV610:
2471 case CHIP_RV620:
2472 case CHIP_RS780:
2473 case CHIP_RS880:
2474 default:
2475 num_ps_gprs = 84;
2476 num_vs_gprs = 36;
2477 num_temp_gprs = 4;
2478 num_gs_gprs = 0;
2479 num_es_gprs = 0;
2480 num_ps_threads = 136;
2481 num_vs_threads = 48;
2482 num_gs_threads = 4;
2483 num_es_threads = 4;
2484 num_ps_stack_entries = 40;
2485 num_vs_stack_entries = 40;
2486 num_gs_stack_entries = 32;
2487 num_es_stack_entries = 16;
2488 break;
2489 case CHIP_RV670:
2490 num_ps_gprs = 144;
2491 num_vs_gprs = 40;
2492 num_temp_gprs = 4;
2493 num_gs_gprs = 0;
2494 num_es_gprs = 0;
2495 num_ps_threads = 136;
2496 num_vs_threads = 48;
2497 num_gs_threads = 4;
2498 num_es_threads = 4;
2499 num_ps_stack_entries = 40;
2500 num_vs_stack_entries = 40;
2501 num_gs_stack_entries = 32;
2502 num_es_stack_entries = 16;
2503 break;
2504 case CHIP_RV770:
2505 num_ps_gprs = 192;
2506 num_vs_gprs = 56;
2507 num_temp_gprs = 4;
2508 num_gs_gprs = 0;
2509 num_es_gprs = 0;
2510 num_ps_threads = 188;
2511 num_vs_threads = 60;
2512 num_gs_threads = 0;
2513 num_es_threads = 0;
2514 num_ps_stack_entries = 256;
2515 num_vs_stack_entries = 256;
2516 num_gs_stack_entries = 0;
2517 num_es_stack_entries = 0;
2518 break;
2519 case CHIP_RV730:
2520 case CHIP_RV740:
2521 num_ps_gprs = 84;
2522 num_vs_gprs = 36;
2523 num_temp_gprs = 4;
2524 num_gs_gprs = 0;
2525 num_es_gprs = 0;
2526 num_ps_threads = 188;
2527 num_vs_threads = 60;
2528 num_gs_threads = 0;
2529 num_es_threads = 0;
2530 num_ps_stack_entries = 128;
2531 num_vs_stack_entries = 128;
2532 num_gs_stack_entries = 0;
2533 num_es_stack_entries = 0;
2534 break;
2535 case CHIP_RV710:
2536 num_ps_gprs = 192;
2537 num_vs_gprs = 56;
2538 num_temp_gprs = 4;
2539 num_gs_gprs = 0;
2540 num_es_gprs = 0;
2541 num_ps_threads = 144;
2542 num_vs_threads = 48;
2543 num_gs_threads = 0;
2544 num_es_threads = 0;
2545 num_ps_stack_entries = 128;
2546 num_vs_stack_entries = 128;
2547 num_gs_stack_entries = 0;
2548 num_es_stack_entries = 0;
2549 break;
2550 }
2551
2552 rctx->default_ps_gprs = num_ps_gprs;
2553 rctx->default_vs_gprs = num_vs_gprs;
2554 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2555
2556 /* SQ_CONFIG */
2557 tmp = 0;
2558 switch (family) {
2559 case CHIP_RV610:
2560 case CHIP_RV620:
2561 case CHIP_RS780:
2562 case CHIP_RS880:
2563 case CHIP_RV710:
2564 break;
2565 default:
2566 tmp |= S_008C00_VC_ENABLE(1);
2567 break;
2568 }
2569 tmp |= S_008C00_DX9_CONSTS(0);
2570 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2571 tmp |= S_008C00_PS_PRIO(ps_prio);
2572 tmp |= S_008C00_VS_PRIO(vs_prio);
2573 tmp |= S_008C00_GS_PRIO(gs_prio);
2574 tmp |= S_008C00_ES_PRIO(es_prio);
2575 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2576
2577 /* SQ_GPR_RESOURCE_MGMT_2 */
2578 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2579 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2580 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2581 r600_store_value(cb, tmp);
2582
2583 /* SQ_THREAD_RESOURCE_MGMT */
2584 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2585 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2586 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2587 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2588 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2589
2590 /* SQ_STACK_RESOURCE_MGMT_1 */
2591 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2592 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2593 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2594
2595 /* SQ_STACK_RESOURCE_MGMT_2 */
2596 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2597 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2598 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2599
2600 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2601
2602 if (rctx->b.chip_class >= R700) {
2603 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2604 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2605 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2606 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2607 } else {
2608 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2609 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2610 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2611 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2612 }
2613 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2614 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2615 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2616 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2617 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2618 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2619 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2620 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2621 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2622 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2623
2624 /* to avoid GPU doing any preloading of constant from random address */
2625 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2626 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2627 r600_store_value(cb, 0);
2628 r600_store_value(cb, 0);
2629 r600_store_value(cb, 0);
2630 r600_store_value(cb, 0);
2631 r600_store_value(cb, 0);
2632 r600_store_value(cb, 0);
2633 r600_store_value(cb, 0);
2634 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2635 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2636 r600_store_value(cb, 0);
2637 r600_store_value(cb, 0);
2638 r600_store_value(cb, 0);
2639 r600_store_value(cb, 0);
2640 r600_store_value(cb, 0);
2641 r600_store_value(cb, 0);
2642 r600_store_value(cb, 0);
2643
2644 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2645 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2646 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2647 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2648 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2649 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2650 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2651 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2652 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2653 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2654 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2655 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2656 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2657 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2658
2659 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2660 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2661 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2662
2663 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2664 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2665 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2666 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2667
2668 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2669
2670 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2671
2672 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2673
2674 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2675 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2676 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2677 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2678
2679 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2680 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2681 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2682 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2683
2684 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2685 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2686
2687 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2688 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2689 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2690 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2691 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2692
2693 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2694 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2695 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2696
2697 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2698
2699 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2700 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2701
2702 if (rctx->b.chip_class >= R700) {
2703 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2704 }
2705
2706 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2707 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2708 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2709 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2710 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2711
2712 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2713 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2714 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2715
2716 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2717 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2718 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2719
2720 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2721 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2722 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2723
2724 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2725
2726 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2727 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2728 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2729
2730 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2731 r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2732
2733 if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
2734 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2735 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2736 if (rctx->screen->b.has_streamout) {
2737 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2738 }
2739
2740 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2741 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2742 }
2743
2744 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2745 {
2746 struct r600_context *rctx = (struct r600_context *)ctx;
2747 struct r600_command_buffer *cb = &shader->command_buffer;
2748 struct r600_shader *rshader = &shader->shader;
2749 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2750 int pos_index = -1, face_index = -1;
2751 unsigned tmp, sid, ufi = 0;
2752 int need_linear = 0;
2753 unsigned z_export = 0, stencil_export = 0;
2754 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2755
2756 if (!cb->buf) {
2757 r600_init_command_buffer(cb, 64);
2758 } else {
2759 cb->num_dw = 0;
2760 }
2761
2762 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2763 for (i = 0; i < rshader->ninput; i++) {
2764 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2765 pos_index = i;
2766 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2767 face_index = i;
2768
2769 sid = rshader->input[i].spi_sid;
2770
2771 tmp = S_028644_SEMANTIC(sid);
2772
2773 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2774 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2775 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2776 rctx->rasterizer && rctx->rasterizer->flatshade))
2777 tmp |= S_028644_FLAT_SHADE(1);
2778
2779 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2780 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2781 tmp |= S_028644_PT_SPRITE_TEX(1);
2782 }
2783
2784 if (rshader->input[i].centroid)
2785 tmp |= S_028644_SEL_CENTROID(1);
2786
2787 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2788 need_linear = 1;
2789 tmp |= S_028644_SEL_LINEAR(1);
2790 }
2791
2792 r600_store_value(cb, tmp);
2793 }
2794
2795 db_shader_control = 0;
2796 for (i = 0; i < rshader->noutput; i++) {
2797 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2798 z_export = 1;
2799 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2800 stencil_export = 1;
2801 }
2802 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2803 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2804 if (rshader->uses_kill)
2805 db_shader_control |= S_02880C_KILL_ENABLE(1);
2806
2807 exports_ps = 0;
2808 for (i = 0; i < rshader->noutput; i++) {
2809 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2810 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2811 exports_ps |= 1;
2812 }
2813 }
2814 num_cout = rshader->nr_ps_color_exports;
2815 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2816 if (!exports_ps) {
2817 /* always at least export 1 component per pixel */
2818 exports_ps = 2;
2819 }
2820
2821 shader->nr_ps_color_outputs = num_cout;
2822
2823 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2824 S_0286CC_PERSP_GRADIENT_ENA(1)|
2825 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2826 spi_input_z = 0;
2827 if (pos_index != -1) {
2828 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2829 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2830 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2831 S_0286CC_BARYC_SAMPLE_CNTL(1));
2832 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2833 }
2834
2835 spi_ps_in_control_1 = 0;
2836 if (face_index != -1) {
2837 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2838 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2839 }
2840
2841 /* HW bug in original R600 */
2842 if (rctx->b.family == CHIP_R600)
2843 ufi = 1;
2844
2845 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2846 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2847 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2848
2849 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2850
2851 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2852 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2853 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2854 S_028850_STACK_SIZE(rshader->bc.nstack) |
2855 S_028850_UNCACHED_FIRST_INST(ufi));
2856 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2857
2858 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2859 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2860
2861 /* only set some bits here, the other bits are set in the dsa state */
2862 shader->db_shader_control = db_shader_control;
2863 shader->ps_depth_export = z_export | stencil_export;
2864
2865 shader->sprite_coord_enable = sprite_coord_enable;
2866 if (rctx->rasterizer)
2867 shader->flatshade = rctx->rasterizer->flatshade;
2868 }
2869
2870 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2871 {
2872 struct r600_command_buffer *cb = &shader->command_buffer;
2873 struct r600_shader *rshader = &shader->shader;
2874 unsigned spi_vs_out_id[10] = {};
2875 unsigned i, tmp, nparams = 0;
2876
2877 for (i = 0; i < rshader->noutput; i++) {
2878 if (rshader->output[i].spi_sid) {
2879 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2880 spi_vs_out_id[nparams / 4] |= tmp;
2881 nparams++;
2882 }
2883 }
2884
2885 r600_init_command_buffer(cb, 32);
2886
2887 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2888 for (i = 0; i < 10; i++) {
2889 r600_store_value(cb, spi_vs_out_id[i]);
2890 }
2891
2892 /* Certain attributes (position, psize, etc.) don't count as params.
2893 * VS is required to export at least one param and r600_shader_from_tgsi()
2894 * takes care of adding a dummy export.
2895 */
2896 if (nparams < 1)
2897 nparams = 1;
2898
2899 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2900 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2901 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2902 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2903 S_028868_STACK_SIZE(rshader->bc.nstack));
2904 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2905 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2906
2907 shader->pa_cl_vs_out_cntl =
2908 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2909 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2910 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2911 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2912 }
2913
2914 void *r600_create_resolve_blend(struct r600_context *rctx)
2915 {
2916 struct pipe_blend_state blend;
2917 unsigned i;
2918
2919 memset(&blend, 0, sizeof(blend));
2920 blend.independent_blend_enable = true;
2921 for (i = 0; i < 2; i++) {
2922 blend.rt[i].colormask = 0xf;
2923 blend.rt[i].blend_enable = 1;
2924 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2925 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2926 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2927 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2928 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2929 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2930 }
2931 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2932 }
2933
2934 void *r700_create_resolve_blend(struct r600_context *rctx)
2935 {
2936 struct pipe_blend_state blend;
2937
2938 memset(&blend, 0, sizeof(blend));
2939 blend.independent_blend_enable = true;
2940 blend.rt[0].colormask = 0xf;
2941 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2942 }
2943
2944 void *r600_create_decompress_blend(struct r600_context *rctx)
2945 {
2946 struct pipe_blend_state blend;
2947
2948 memset(&blend, 0, sizeof(blend));
2949 blend.independent_blend_enable = true;
2950 blend.rt[0].colormask = 0xf;
2951 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2952 }
2953
2954 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2955 {
2956 struct pipe_depth_stencil_alpha_state dsa;
2957 boolean quirk = false;
2958
2959 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2960 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2961 quirk = true;
2962
2963 memset(&dsa, 0, sizeof(dsa));
2964
2965 if (quirk) {
2966 dsa.depth.enabled = 1;
2967 dsa.depth.func = PIPE_FUNC_LEQUAL;
2968 dsa.stencil[0].enabled = 1;
2969 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2970 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2971 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2972 dsa.stencil[0].writemask = 0xff;
2973 }
2974
2975 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2976 }
2977
2978 void r600_update_db_shader_control(struct r600_context * rctx)
2979 {
2980 bool dual_export;
2981 unsigned db_shader_control;
2982
2983 if (!rctx->ps_shader) {
2984 return;
2985 }
2986
2987 dual_export = rctx->framebuffer.export_16bpc &&
2988 !rctx->ps_shader->current->ps_depth_export;
2989
2990 db_shader_control = rctx->ps_shader->current->db_shader_control |
2991 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2992
2993 /* When alpha test is enabled we can't trust the hw to make the proper
2994 * decision on the order in which ztest should be run related to fragment
2995 * shader execution.
2996 *
2997 * If alpha test is enabled perform z test after fragment. RE_Z (early
2998 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2999 */
3000 if (rctx->alphatest_state.sx_alpha_test_control) {
3001 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3002 } else {
3003 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3004 }
3005
3006 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3007 rctx->db_misc_state.db_shader_control = db_shader_control;
3008 rctx->db_misc_state.atom.dirty = true;
3009 }
3010 }
3011
3012 static INLINE unsigned r600_array_mode(unsigned mode)
3013 {
3014 switch (mode) {
3015 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
3016 break;
3017 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
3018 break;
3019 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
3020 default:
3021 case RADEON_SURF_MODE_LINEAR: return V_0280A0_ARRAY_LINEAR_GENERAL;
3022 }
3023 }
3024
3025 static boolean r600_dma_copy_tile(struct r600_context *rctx,
3026 struct pipe_resource *dst,
3027 unsigned dst_level,
3028 unsigned dst_x,
3029 unsigned dst_y,
3030 unsigned dst_z,
3031 struct pipe_resource *src,
3032 unsigned src_level,
3033 unsigned src_x,
3034 unsigned src_y,
3035 unsigned src_z,
3036 unsigned copy_height,
3037 unsigned pitch,
3038 unsigned bpp)
3039 {
3040 struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs;
3041 struct r600_texture *rsrc = (struct r600_texture*)src;
3042 struct r600_texture *rdst = (struct r600_texture*)dst;
3043 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3044 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3045 uint64_t base, addr;
3046
3047 /* make sure that the dma ring is only one active */
3048 rctx->b.rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
3049
3050 dst_mode = rdst->surface.level[dst_level].mode;
3051 src_mode = rsrc->surface.level[src_level].mode;
3052 /* downcast linear aligned to linear to simplify test */
3053 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3054 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3055 assert(dst_mode != src_mode);
3056
3057 y = 0;
3058 lbpp = util_logbase2(bpp);
3059 pitch_tile_max = ((pitch / bpp) >> 3) - 1;
3060
3061 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
3062 /* T2L */
3063 array_mode = r600_array_mode(src_mode);
3064 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) >> 6;
3065 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3066 /* linear height must be the same as the slice tile max height, it's ok even
3067 * if the linear destination/source have smaller heigh as the size of the
3068 * dma packet will be using the copy_height which is always smaller or equal
3069 * to the linear height
3070 */
3071 height = rsrc->surface.level[src_level].npix_y;
3072 detile = 1;
3073 x = src_x;
3074 y = src_y;
3075 z = src_z;
3076 base = rsrc->surface.level[src_level].offset;
3077 addr = rdst->surface.level[dst_level].offset;
3078 addr += rdst->surface.level[dst_level].slice_size * dst_z;
3079 addr += dst_y * pitch + dst_x * bpp;
3080 } else {
3081 /* L2T */
3082 array_mode = r600_array_mode(dst_mode);
3083 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) >> 6;
3084 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3085 /* linear height must be the same as the slice tile max height, it's ok even
3086 * if the linear destination/source have smaller heigh as the size of the
3087 * dma packet will be using the copy_height which is always smaller or equal
3088 * to the linear height
3089 */
3090 height = rdst->surface.level[dst_level].npix_y;
3091 detile = 0;
3092 x = dst_x;
3093 y = dst_y;
3094 z = dst_z;
3095 base = rdst->surface.level[dst_level].offset;
3096 addr = rsrc->surface.level[src_level].offset;
3097 addr += rsrc->surface.level[src_level].slice_size * src_z;
3098 addr += src_y * pitch + src_x * bpp;
3099 }
3100 /* check that we are in dw/base alignment constraint */
3101 if ((addr & 0x3) || (base & 0xff)) {
3102 return FALSE;
3103 }
3104
3105 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
3106 * line in the blit. Compute max 8 line we can copy in the size limit
3107 */
3108 cheight = ((0x0000ffff << 2) / pitch) & 0xfffffff8;
3109 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
3110 r600_need_dma_space(rctx, ncopy * 7);
3111
3112 for (i = 0; i < ncopy; i++) {
3113 cheight = cheight > copy_height ? copy_height : cheight;
3114 size = (cheight * pitch) >> 2;
3115 /* emit reloc before writting cs so that cs is always in consistent state */
3116 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rsrc->resource, RADEON_USAGE_READ);
3117 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rdst->resource, RADEON_USAGE_WRITE);
3118 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 1, 0, size);
3119 cs->buf[cs->cdw++] = base >> 8;
3120 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
3121 (lbpp << 24) | ((height - 1) << 10) |
3122 pitch_tile_max;
3123 cs->buf[cs->cdw++] = (slice_tile_max << 12) | (z << 0);
3124 cs->buf[cs->cdw++] = (x << 3) | (y << 17);
3125 cs->buf[cs->cdw++] = addr & 0xfffffffc;
3126 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
3127 copy_height -= cheight;
3128 addr += cheight * pitch;
3129 y += cheight;
3130 }
3131 return TRUE;
3132 }
3133
3134 static boolean r600_dma_blit(struct pipe_context *ctx,
3135 struct pipe_resource *dst,
3136 unsigned dst_level,
3137 unsigned dst_x, unsigned dst_y, unsigned dst_z,
3138 struct pipe_resource *src,
3139 unsigned src_level,
3140 const struct pipe_box *src_box)
3141 {
3142 struct r600_context *rctx = (struct r600_context *)ctx;
3143 struct r600_texture *rsrc = (struct r600_texture*)src;
3144 struct r600_texture *rdst = (struct r600_texture*)dst;
3145 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3146 unsigned src_w, dst_w;
3147 unsigned src_x, src_y;
3148
3149 if (rctx->b.rings.dma.cs == NULL) {
3150 return FALSE;
3151 }
3152
3153 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3154 r600_dma_copy(rctx, dst, src, dst_x, src_box->x, src_box->width);
3155 return TRUE;
3156 }
3157
3158 if (src->format != dst->format) {
3159 return FALSE;
3160 }
3161
3162 src_x = util_format_get_nblocksx(src->format, src_box->x);
3163 dst_x = util_format_get_nblocksx(src->format, dst_x);
3164 src_y = util_format_get_nblocksy(src->format, src_box->y);
3165 dst_y = util_format_get_nblocksy(src->format, dst_y);
3166
3167 bpp = rdst->surface.bpe;
3168 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
3169 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
3170 src_w = rsrc->surface.level[src_level].npix_x;
3171 dst_w = rdst->surface.level[dst_level].npix_x;
3172 copy_height = src_box->height / rsrc->surface.blk_h;
3173
3174 dst_mode = rdst->surface.level[dst_level].mode;
3175 src_mode = rsrc->surface.level[src_level].mode;
3176 /* downcast linear aligned to linear to simplify test */
3177 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3178 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3179
3180 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3181 /* strick requirement on r6xx/r7xx */
3182 return FALSE;
3183 }
3184 /* lot of constraint on alignment this should capture them all */
3185 if ((src_pitch & 0x7) || (src_box->y & 0x7) || (dst_y & 0x7)) {
3186 return FALSE;
3187 }
3188
3189 if (src_mode == dst_mode) {
3190 uint64_t dst_offset, src_offset, size;
3191
3192 /* simple dma blit would do NOTE code here assume :
3193 * src_box.x/y == 0
3194 * dst_x/y == 0
3195 * dst_pitch == src_pitch
3196 */
3197 src_offset= rsrc->surface.level[src_level].offset;
3198 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3199 src_offset += src_y * src_pitch + src_x * bpp;
3200 dst_offset = rdst->surface.level[dst_level].offset;
3201 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3202 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3203 size = src_box->height * src_pitch;
3204 /* must be dw aligned */
3205 if ((dst_offset & 0x3) || (src_offset & 0x3) || (size & 0x3)) {
3206 return FALSE;
3207 }
3208 r600_dma_copy(rctx, dst, src, dst_offset, src_offset, size);
3209 } else {
3210 return r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3211 src, src_level, src_x, src_y, src_box->z,
3212 copy_height, dst_pitch, bpp);
3213 }
3214 return TRUE;
3215 }
3216
3217 void r600_init_state_functions(struct r600_context *rctx)
3218 {
3219 unsigned id = 4;
3220
3221 /* !!!
3222 * To avoid GPU lockup registers must be emited in a specific order
3223 * (no kidding ...). The order below is important and have been
3224 * partialy infered from analyzing fglrx command stream.
3225 *
3226 * Don't reorder atom without carefully checking the effect (GPU lockup
3227 * or piglit regression).
3228 * !!!
3229 */
3230
3231 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
3232
3233 /* shader const */
3234 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
3235 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
3236 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
3237
3238 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3239 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
3240 */
3241 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
3242 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
3243 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
3244 /* resource */
3245 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
3246 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
3247 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
3248 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
3249
3250 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 7);
3251
3252 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3253 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3254 rctx->sample_mask.sample_mask = ~0;
3255
3256 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3257 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3258 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3259 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3260 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3261 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3262 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3263 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3264 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3265 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
3266 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3267 r600_init_atom(rctx, &rctx->scissor.atom, id++, r600_emit_scissor_state, 4);
3268 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3269 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3270 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
3271 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3272 rctx->atoms[id++] = &rctx->b.streamout.begin_atom;
3273 r600_init_atom(rctx, &rctx->vertex_shader.atom, id++, r600_emit_shader, 23);
3274 r600_init_atom(rctx, &rctx->pixel_shader.atom, id++, r600_emit_shader, 0);
3275
3276 rctx->b.b.create_blend_state = r600_create_blend_state;
3277 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3278 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3279 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3280 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3281 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3282 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3283 rctx->b.b.set_scissor_states = r600_set_scissor_states;
3284 rctx->b.b.get_sample_position = r600_get_sample_position;
3285 rctx->b.dma_copy = r600_dma_blit;
3286 }
3287 /* this function must be last */