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r600g: texture buffer object + glsl 1.40 enable support (v2)
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static uint32_t r600_translate_colorswap(enum pipe_format format)
145 {
146 switch (format) {
147 /* 8-bit buffers. */
148 case PIPE_FORMAT_A8_UNORM:
149 case PIPE_FORMAT_A8_SNORM:
150 case PIPE_FORMAT_A8_UINT:
151 case PIPE_FORMAT_A8_SINT:
152 case PIPE_FORMAT_A16_UNORM:
153 case PIPE_FORMAT_A16_SNORM:
154 case PIPE_FORMAT_A16_UINT:
155 case PIPE_FORMAT_A16_SINT:
156 case PIPE_FORMAT_A16_FLOAT:
157 case PIPE_FORMAT_A32_UINT:
158 case PIPE_FORMAT_A32_SINT:
159 case PIPE_FORMAT_A32_FLOAT:
160 case PIPE_FORMAT_R4A4_UNORM:
161 return V_0280A0_SWAP_ALT_REV;
162 case PIPE_FORMAT_I8_UNORM:
163 case PIPE_FORMAT_I8_SNORM:
164 case PIPE_FORMAT_I8_UINT:
165 case PIPE_FORMAT_I8_SINT:
166 case PIPE_FORMAT_L8_UNORM:
167 case PIPE_FORMAT_L8_SNORM:
168 case PIPE_FORMAT_L8_UINT:
169 case PIPE_FORMAT_L8_SINT:
170 case PIPE_FORMAT_L8_SRGB:
171 case PIPE_FORMAT_L16_UNORM:
172 case PIPE_FORMAT_L16_SNORM:
173 case PIPE_FORMAT_L16_UINT:
174 case PIPE_FORMAT_L16_SINT:
175 case PIPE_FORMAT_L16_FLOAT:
176 case PIPE_FORMAT_L32_UINT:
177 case PIPE_FORMAT_L32_SINT:
178 case PIPE_FORMAT_L32_FLOAT:
179 case PIPE_FORMAT_I16_UNORM:
180 case PIPE_FORMAT_I16_SNORM:
181 case PIPE_FORMAT_I16_UINT:
182 case PIPE_FORMAT_I16_SINT:
183 case PIPE_FORMAT_I16_FLOAT:
184 case PIPE_FORMAT_I32_UINT:
185 case PIPE_FORMAT_I32_SINT:
186 case PIPE_FORMAT_I32_FLOAT:
187 case PIPE_FORMAT_R8_UNORM:
188 case PIPE_FORMAT_R8_SNORM:
189 case PIPE_FORMAT_R8_UINT:
190 case PIPE_FORMAT_R8_SINT:
191 return V_0280A0_SWAP_STD;
192
193 case PIPE_FORMAT_L4A4_UNORM:
194 case PIPE_FORMAT_A4R4_UNORM:
195 return V_0280A0_SWAP_ALT;
196
197 /* 16-bit buffers. */
198 case PIPE_FORMAT_B5G6R5_UNORM:
199 return V_0280A0_SWAP_STD_REV;
200
201 case PIPE_FORMAT_B5G5R5A1_UNORM:
202 case PIPE_FORMAT_B5G5R5X1_UNORM:
203 return V_0280A0_SWAP_ALT;
204
205 case PIPE_FORMAT_B4G4R4A4_UNORM:
206 case PIPE_FORMAT_B4G4R4X4_UNORM:
207 return V_0280A0_SWAP_ALT;
208
209 case PIPE_FORMAT_Z16_UNORM:
210 return V_0280A0_SWAP_STD;
211
212 case PIPE_FORMAT_L8A8_UNORM:
213 case PIPE_FORMAT_L8A8_SNORM:
214 case PIPE_FORMAT_L8A8_UINT:
215 case PIPE_FORMAT_L8A8_SINT:
216 case PIPE_FORMAT_L8A8_SRGB:
217 case PIPE_FORMAT_L16A16_UNORM:
218 case PIPE_FORMAT_L16A16_SNORM:
219 case PIPE_FORMAT_L16A16_UINT:
220 case PIPE_FORMAT_L16A16_SINT:
221 case PIPE_FORMAT_L16A16_FLOAT:
222 case PIPE_FORMAT_L32A32_UINT:
223 case PIPE_FORMAT_L32A32_SINT:
224 case PIPE_FORMAT_L32A32_FLOAT:
225 return V_0280A0_SWAP_ALT;
226 case PIPE_FORMAT_R8G8_UNORM:
227 case PIPE_FORMAT_R8G8_SNORM:
228 case PIPE_FORMAT_R8G8_UINT:
229 case PIPE_FORMAT_R8G8_SINT:
230 return V_0280A0_SWAP_STD;
231
232 case PIPE_FORMAT_R16_UNORM:
233 case PIPE_FORMAT_R16_SNORM:
234 case PIPE_FORMAT_R16_UINT:
235 case PIPE_FORMAT_R16_SINT:
236 case PIPE_FORMAT_R16_FLOAT:
237 return V_0280A0_SWAP_STD;
238
239 /* 32-bit buffers. */
240
241 case PIPE_FORMAT_A8B8G8R8_SRGB:
242 return V_0280A0_SWAP_STD_REV;
243 case PIPE_FORMAT_B8G8R8A8_SRGB:
244 return V_0280A0_SWAP_ALT;
245
246 case PIPE_FORMAT_B8G8R8A8_UNORM:
247 case PIPE_FORMAT_B8G8R8X8_UNORM:
248 return V_0280A0_SWAP_ALT;
249
250 case PIPE_FORMAT_A8R8G8B8_UNORM:
251 case PIPE_FORMAT_X8R8G8B8_UNORM:
252 return V_0280A0_SWAP_ALT_REV;
253 case PIPE_FORMAT_R8G8B8A8_SNORM:
254 case PIPE_FORMAT_R8G8B8A8_UNORM:
255 case PIPE_FORMAT_R8G8B8X8_UNORM:
256 case PIPE_FORMAT_R8G8B8A8_SINT:
257 case PIPE_FORMAT_R8G8B8A8_UINT:
258 return V_0280A0_SWAP_STD;
259
260 case PIPE_FORMAT_A8B8G8R8_UNORM:
261 case PIPE_FORMAT_X8B8G8R8_UNORM:
262 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
263 return V_0280A0_SWAP_STD_REV;
264
265 case PIPE_FORMAT_Z24X8_UNORM:
266 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
267 return V_0280A0_SWAP_STD;
268
269 case PIPE_FORMAT_X8Z24_UNORM:
270 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
271 return V_0280A0_SWAP_STD;
272
273 case PIPE_FORMAT_R10G10B10A2_UNORM:
274 case PIPE_FORMAT_R10G10B10X2_SNORM:
275 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
276 return V_0280A0_SWAP_STD;
277
278 case PIPE_FORMAT_B10G10R10A2_UNORM:
279 case PIPE_FORMAT_B10G10R10A2_UINT:
280 return V_0280A0_SWAP_ALT;
281
282 case PIPE_FORMAT_R11G11B10_FLOAT:
283 case PIPE_FORMAT_R16G16_UNORM:
284 case PIPE_FORMAT_R16G16_SNORM:
285 case PIPE_FORMAT_R16G16_FLOAT:
286 case PIPE_FORMAT_R16G16_UINT:
287 case PIPE_FORMAT_R16G16_SINT:
288 case PIPE_FORMAT_R32_UINT:
289 case PIPE_FORMAT_R32_SINT:
290 case PIPE_FORMAT_R32_FLOAT:
291 case PIPE_FORMAT_Z32_FLOAT:
292 return V_0280A0_SWAP_STD;
293
294 /* 64-bit buffers. */
295 case PIPE_FORMAT_R32G32_FLOAT:
296 case PIPE_FORMAT_R32G32_UINT:
297 case PIPE_FORMAT_R32G32_SINT:
298 case PIPE_FORMAT_R16G16B16A16_UNORM:
299 case PIPE_FORMAT_R16G16B16A16_SNORM:
300 case PIPE_FORMAT_R16G16B16A16_UINT:
301 case PIPE_FORMAT_R16G16B16A16_SINT:
302 case PIPE_FORMAT_R16G16B16A16_FLOAT:
303 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
304
305 /* 128-bit buffers. */
306 case PIPE_FORMAT_R32G32B32A32_FLOAT:
307 case PIPE_FORMAT_R32G32B32A32_SNORM:
308 case PIPE_FORMAT_R32G32B32A32_UNORM:
309 case PIPE_FORMAT_R32G32B32A32_SINT:
310 case PIPE_FORMAT_R32G32B32A32_UINT:
311 return V_0280A0_SWAP_STD;
312 default:
313 R600_ERR("unsupported colorswap format %d\n", format);
314 return ~0U;
315 }
316 return ~0U;
317 }
318
319 static uint32_t r600_translate_colorformat(enum pipe_format format)
320 {
321 switch (format) {
322 case PIPE_FORMAT_L4A4_UNORM:
323 case PIPE_FORMAT_R4A4_UNORM:
324 case PIPE_FORMAT_A4R4_UNORM:
325 return V_0280A0_COLOR_4_4;
326
327 /* 8-bit buffers. */
328 case PIPE_FORMAT_A8_UNORM:
329 case PIPE_FORMAT_A8_SNORM:
330 case PIPE_FORMAT_A8_UINT:
331 case PIPE_FORMAT_A8_SINT:
332 case PIPE_FORMAT_I8_UNORM:
333 case PIPE_FORMAT_I8_SNORM:
334 case PIPE_FORMAT_I8_UINT:
335 case PIPE_FORMAT_I8_SINT:
336 case PIPE_FORMAT_L8_UNORM:
337 case PIPE_FORMAT_L8_SNORM:
338 case PIPE_FORMAT_L8_UINT:
339 case PIPE_FORMAT_L8_SINT:
340 case PIPE_FORMAT_L8_SRGB:
341 case PIPE_FORMAT_R8_UNORM:
342 case PIPE_FORMAT_R8_SNORM:
343 case PIPE_FORMAT_R8_UINT:
344 case PIPE_FORMAT_R8_SINT:
345 return V_0280A0_COLOR_8;
346
347 /* 16-bit buffers. */
348 case PIPE_FORMAT_B5G6R5_UNORM:
349 return V_0280A0_COLOR_5_6_5;
350
351 case PIPE_FORMAT_B5G5R5A1_UNORM:
352 case PIPE_FORMAT_B5G5R5X1_UNORM:
353 return V_0280A0_COLOR_1_5_5_5;
354
355 case PIPE_FORMAT_B4G4R4A4_UNORM:
356 case PIPE_FORMAT_B4G4R4X4_UNORM:
357 return V_0280A0_COLOR_4_4_4_4;
358
359 case PIPE_FORMAT_Z16_UNORM:
360 return V_0280A0_COLOR_16;
361
362 case PIPE_FORMAT_L8A8_UNORM:
363 case PIPE_FORMAT_L8A8_SNORM:
364 case PIPE_FORMAT_L8A8_UINT:
365 case PIPE_FORMAT_L8A8_SINT:
366 case PIPE_FORMAT_L8A8_SRGB:
367 case PIPE_FORMAT_R8G8_UNORM:
368 case PIPE_FORMAT_R8G8_SNORM:
369 case PIPE_FORMAT_R8G8_UINT:
370 case PIPE_FORMAT_R8G8_SINT:
371 return V_0280A0_COLOR_8_8;
372
373 case PIPE_FORMAT_R16_UNORM:
374 case PIPE_FORMAT_R16_SNORM:
375 case PIPE_FORMAT_R16_UINT:
376 case PIPE_FORMAT_R16_SINT:
377 case PIPE_FORMAT_A16_UNORM:
378 case PIPE_FORMAT_A16_SNORM:
379 case PIPE_FORMAT_A16_UINT:
380 case PIPE_FORMAT_A16_SINT:
381 case PIPE_FORMAT_L16_UNORM:
382 case PIPE_FORMAT_L16_SNORM:
383 case PIPE_FORMAT_L16_UINT:
384 case PIPE_FORMAT_L16_SINT:
385 case PIPE_FORMAT_I16_UNORM:
386 case PIPE_FORMAT_I16_SNORM:
387 case PIPE_FORMAT_I16_UINT:
388 case PIPE_FORMAT_I16_SINT:
389 return V_0280A0_COLOR_16;
390
391 case PIPE_FORMAT_R16_FLOAT:
392 case PIPE_FORMAT_A16_FLOAT:
393 case PIPE_FORMAT_L16_FLOAT:
394 case PIPE_FORMAT_I16_FLOAT:
395 return V_0280A0_COLOR_16_FLOAT;
396
397 /* 32-bit buffers. */
398 case PIPE_FORMAT_A8B8G8R8_SRGB:
399 case PIPE_FORMAT_A8B8G8R8_UNORM:
400 case PIPE_FORMAT_A8R8G8B8_UNORM:
401 case PIPE_FORMAT_B8G8R8A8_SRGB:
402 case PIPE_FORMAT_B8G8R8A8_UNORM:
403 case PIPE_FORMAT_B8G8R8X8_UNORM:
404 case PIPE_FORMAT_R8G8B8A8_SNORM:
405 case PIPE_FORMAT_R8G8B8A8_UNORM:
406 case PIPE_FORMAT_R8G8B8X8_UNORM:
407 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
408 case PIPE_FORMAT_X8B8G8R8_UNORM:
409 case PIPE_FORMAT_X8R8G8B8_UNORM:
410 case PIPE_FORMAT_R8G8B8A8_SINT:
411 case PIPE_FORMAT_R8G8B8A8_UINT:
412 return V_0280A0_COLOR_8_8_8_8;
413
414 case PIPE_FORMAT_R10G10B10A2_UNORM:
415 case PIPE_FORMAT_R10G10B10X2_SNORM:
416 case PIPE_FORMAT_B10G10R10A2_UNORM:
417 case PIPE_FORMAT_B10G10R10A2_UINT:
418 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
419 return V_0280A0_COLOR_2_10_10_10;
420
421 case PIPE_FORMAT_Z24X8_UNORM:
422 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
423 return V_0280A0_COLOR_8_24;
424
425 case PIPE_FORMAT_X8Z24_UNORM:
426 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
427 return V_0280A0_COLOR_24_8;
428
429 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
430 return V_0280A0_COLOR_X24_8_32_FLOAT;
431
432 case PIPE_FORMAT_R32_UINT:
433 case PIPE_FORMAT_R32_SINT:
434 case PIPE_FORMAT_A32_UINT:
435 case PIPE_FORMAT_A32_SINT:
436 case PIPE_FORMAT_L32_UINT:
437 case PIPE_FORMAT_L32_SINT:
438 case PIPE_FORMAT_I32_UINT:
439 case PIPE_FORMAT_I32_SINT:
440 return V_0280A0_COLOR_32;
441
442 case PIPE_FORMAT_R32_FLOAT:
443 case PIPE_FORMAT_A32_FLOAT:
444 case PIPE_FORMAT_L32_FLOAT:
445 case PIPE_FORMAT_I32_FLOAT:
446 case PIPE_FORMAT_Z32_FLOAT:
447 return V_0280A0_COLOR_32_FLOAT;
448
449 case PIPE_FORMAT_R16G16_FLOAT:
450 case PIPE_FORMAT_L16A16_FLOAT:
451 return V_0280A0_COLOR_16_16_FLOAT;
452
453 case PIPE_FORMAT_R16G16_UNORM:
454 case PIPE_FORMAT_R16G16_SNORM:
455 case PIPE_FORMAT_R16G16_UINT:
456 case PIPE_FORMAT_R16G16_SINT:
457 case PIPE_FORMAT_L16A16_UNORM:
458 case PIPE_FORMAT_L16A16_SNORM:
459 case PIPE_FORMAT_L16A16_UINT:
460 case PIPE_FORMAT_L16A16_SINT:
461 return V_0280A0_COLOR_16_16;
462
463 case PIPE_FORMAT_R11G11B10_FLOAT:
464 return V_0280A0_COLOR_10_11_11_FLOAT;
465
466 /* 64-bit buffers. */
467 case PIPE_FORMAT_R16G16B16A16_UINT:
468 case PIPE_FORMAT_R16G16B16A16_SINT:
469 case PIPE_FORMAT_R16G16B16A16_UNORM:
470 case PIPE_FORMAT_R16G16B16A16_SNORM:
471 return V_0280A0_COLOR_16_16_16_16;
472
473 case PIPE_FORMAT_R16G16B16A16_FLOAT:
474 return V_0280A0_COLOR_16_16_16_16_FLOAT;
475
476 case PIPE_FORMAT_R32G32_FLOAT:
477 case PIPE_FORMAT_L32A32_FLOAT:
478 return V_0280A0_COLOR_32_32_FLOAT;
479
480 case PIPE_FORMAT_R32G32_SINT:
481 case PIPE_FORMAT_R32G32_UINT:
482 case PIPE_FORMAT_L32A32_UINT:
483 case PIPE_FORMAT_L32A32_SINT:
484 return V_0280A0_COLOR_32_32;
485
486 /* 128-bit buffers. */
487 case PIPE_FORMAT_R32G32B32A32_FLOAT:
488 return V_0280A0_COLOR_32_32_32_32_FLOAT;
489 case PIPE_FORMAT_R32G32B32A32_SNORM:
490 case PIPE_FORMAT_R32G32B32A32_UNORM:
491 case PIPE_FORMAT_R32G32B32A32_SINT:
492 case PIPE_FORMAT_R32G32B32A32_UINT:
493 return V_0280A0_COLOR_32_32_32_32;
494
495 /* YUV buffers. */
496 case PIPE_FORMAT_UYVY:
497 case PIPE_FORMAT_YUYV:
498 default:
499 return ~0U; /* Unsupported. */
500 }
501 }
502
503 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
504 {
505 if (R600_BIG_ENDIAN) {
506 switch(colorformat) {
507 case V_0280A0_COLOR_4_4:
508 return ENDIAN_NONE;
509
510 /* 8-bit buffers. */
511 case V_0280A0_COLOR_8:
512 return ENDIAN_NONE;
513
514 /* 16-bit buffers. */
515 case V_0280A0_COLOR_5_6_5:
516 case V_0280A0_COLOR_1_5_5_5:
517 case V_0280A0_COLOR_4_4_4_4:
518 case V_0280A0_COLOR_16:
519 case V_0280A0_COLOR_8_8:
520 return ENDIAN_8IN16;
521
522 /* 32-bit buffers. */
523 case V_0280A0_COLOR_8_8_8_8:
524 case V_0280A0_COLOR_2_10_10_10:
525 case V_0280A0_COLOR_8_24:
526 case V_0280A0_COLOR_24_8:
527 case V_0280A0_COLOR_32_FLOAT:
528 case V_0280A0_COLOR_16_16_FLOAT:
529 case V_0280A0_COLOR_16_16:
530 return ENDIAN_8IN32;
531
532 /* 64-bit buffers. */
533 case V_0280A0_COLOR_16_16_16_16:
534 case V_0280A0_COLOR_16_16_16_16_FLOAT:
535 return ENDIAN_8IN16;
536
537 case V_0280A0_COLOR_32_32_FLOAT:
538 case V_0280A0_COLOR_32_32:
539 case V_0280A0_COLOR_X24_8_32_FLOAT:
540 return ENDIAN_8IN32;
541
542 /* 128-bit buffers. */
543 case V_0280A0_COLOR_32_32_32_FLOAT:
544 case V_0280A0_COLOR_32_32_32_32_FLOAT:
545 case V_0280A0_COLOR_32_32_32_32:
546 return ENDIAN_8IN32;
547 default:
548 return ENDIAN_NONE; /* Unsupported. */
549 }
550 } else {
551 return ENDIAN_NONE;
552 }
553 }
554
555 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
556 {
557 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
558 }
559
560 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
561 {
562 return r600_translate_colorformat(format) != ~0U &&
563 r600_translate_colorswap(format) != ~0U;
564 }
565
566 static bool r600_is_zs_format_supported(enum pipe_format format)
567 {
568 return r600_translate_dbformat(format) != ~0U;
569 }
570
571 boolean r600_is_format_supported(struct pipe_screen *screen,
572 enum pipe_format format,
573 enum pipe_texture_target target,
574 unsigned sample_count,
575 unsigned usage)
576 {
577 struct r600_screen *rscreen = (struct r600_screen*)screen;
578 unsigned retval = 0;
579
580 if (target >= PIPE_MAX_TEXTURE_TYPES) {
581 R600_ERR("r600: unsupported texture type %d\n", target);
582 return FALSE;
583 }
584
585 if (!util_format_is_supported(format, usage))
586 return FALSE;
587
588 if (sample_count > 1) {
589 if (!rscreen->has_msaa)
590 return FALSE;
591
592 /* R11G11B10 is broken on R6xx. */
593 if (rscreen->chip_class == R600 &&
594 format == PIPE_FORMAT_R11G11B10_FLOAT)
595 return FALSE;
596
597 /* MSAA integer colorbuffers hang. */
598 if (util_format_is_pure_integer(format) &&
599 !util_format_is_depth_or_stencil(format))
600 return FALSE;
601
602 switch (sample_count) {
603 case 2:
604 case 4:
605 case 8:
606 break;
607 default:
608 return FALSE;
609 }
610 }
611
612 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
613 r600_is_sampler_format_supported(screen, format)) {
614 retval |= PIPE_BIND_SAMPLER_VIEW;
615 }
616
617 if ((usage & (PIPE_BIND_RENDER_TARGET |
618 PIPE_BIND_DISPLAY_TARGET |
619 PIPE_BIND_SCANOUT |
620 PIPE_BIND_SHARED)) &&
621 r600_is_colorbuffer_format_supported(format)) {
622 retval |= usage &
623 (PIPE_BIND_RENDER_TARGET |
624 PIPE_BIND_DISPLAY_TARGET |
625 PIPE_BIND_SCANOUT |
626 PIPE_BIND_SHARED);
627 }
628
629 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
630 r600_is_zs_format_supported(format)) {
631 retval |= PIPE_BIND_DEPTH_STENCIL;
632 }
633
634 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
635 r600_is_vertex_format_supported(format)) {
636 retval |= PIPE_BIND_VERTEX_BUFFER;
637 }
638
639 if (usage & PIPE_BIND_TRANSFER_READ)
640 retval |= PIPE_BIND_TRANSFER_READ;
641 if (usage & PIPE_BIND_TRANSFER_WRITE)
642 retval |= PIPE_BIND_TRANSFER_WRITE;
643
644 return retval == usage;
645 }
646
647 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
648 {
649 struct radeon_winsys_cs *cs = rctx->cs;
650 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
651 float offset_units = state->offset_units;
652 float offset_scale = state->offset_scale;
653
654 switch (state->zs_format) {
655 case PIPE_FORMAT_Z24X8_UNORM:
656 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
657 offset_units *= 2.0f;
658 break;
659 case PIPE_FORMAT_Z16_UNORM:
660 offset_units *= 4.0f;
661 break;
662 default:;
663 }
664
665 r600_write_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
666 r600_write_value(cs, fui(offset_scale));
667 r600_write_value(cs, fui(offset_units));
668 r600_write_value(cs, fui(offset_scale));
669 r600_write_value(cs, fui(offset_units));
670 }
671
672 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
673 {
674 int j = state->independent_blend_enable ? i : 0;
675
676 unsigned eqRGB = state->rt[j].rgb_func;
677 unsigned srcRGB = state->rt[j].rgb_src_factor;
678 unsigned dstRGB = state->rt[j].rgb_dst_factor;
679
680 unsigned eqA = state->rt[j].alpha_func;
681 unsigned srcA = state->rt[j].alpha_src_factor;
682 unsigned dstA = state->rt[j].alpha_dst_factor;
683 uint32_t bc = 0;
684
685 if (!state->rt[j].blend_enable)
686 return 0;
687
688 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
689 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
690 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
691
692 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
693 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
694 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
695 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
696 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
697 }
698 return bc;
699 }
700
701 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
702 const struct pipe_blend_state *state,
703 int mode)
704 {
705 struct r600_context *rctx = (struct r600_context *)ctx;
706 uint32_t color_control = 0, target_mask = 0;
707 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
708
709 if (!blend) {
710 return NULL;
711 }
712
713 r600_init_command_buffer(&blend->buffer, 20);
714 r600_init_command_buffer(&blend->buffer_no_blend, 20);
715
716 /* R600 does not support per-MRT blends */
717 if (rctx->family > CHIP_R600)
718 color_control |= S_028808_PER_MRT_BLEND(1);
719
720 if (state->logicop_enable) {
721 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
722 } else {
723 color_control |= (0xcc << 16);
724 }
725 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
726 if (state->independent_blend_enable) {
727 for (int i = 0; i < 8; i++) {
728 if (state->rt[i].blend_enable) {
729 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
730 }
731 target_mask |= (state->rt[i].colormask << (4 * i));
732 }
733 } else {
734 for (int i = 0; i < 8; i++) {
735 if (state->rt[0].blend_enable) {
736 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
737 }
738 target_mask |= (state->rt[0].colormask << (4 * i));
739 }
740 }
741
742 if (target_mask)
743 color_control |= S_028808_SPECIAL_OP(mode);
744 else
745 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
746
747 /* only MRT0 has dual src blend */
748 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
749 blend->cb_target_mask = target_mask;
750 blend->cb_color_control = color_control;
751 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
752 blend->alpha_to_one = state->alpha_to_one;
753
754 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
755 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
756 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
757 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
758 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
759 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
760
761 /* Copy over the registers set so far into buffer_no_blend. */
762 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
763 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
764
765 /* Only add blend registers if blending is enabled. */
766 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
767 return blend;
768 }
769
770 /* The first R600 does not support per-MRT blends */
771 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
772 r600_get_blend_control(state, 0));
773
774 if (rctx->family > CHIP_R600) {
775 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
776 for (int i = 0; i < 8; i++) {
777 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
778 }
779 }
780 return blend;
781 }
782
783 static void *r600_create_blend_state(struct pipe_context *ctx,
784 const struct pipe_blend_state *state)
785 {
786 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
787 }
788
789 static void *r600_create_dsa_state(struct pipe_context *ctx,
790 const struct pipe_depth_stencil_alpha_state *state)
791 {
792 unsigned db_depth_control, alpha_test_control, alpha_ref;
793 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
794
795 if (dsa == NULL) {
796 return NULL;
797 }
798
799 r600_init_command_buffer(&dsa->buffer, 3);
800
801 dsa->valuemask[0] = state->stencil[0].valuemask;
802 dsa->valuemask[1] = state->stencil[1].valuemask;
803 dsa->writemask[0] = state->stencil[0].writemask;
804 dsa->writemask[1] = state->stencil[1].writemask;
805
806 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
807 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
808 S_028800_ZFUNC(state->depth.func);
809
810 /* stencil */
811 if (state->stencil[0].enabled) {
812 db_depth_control |= S_028800_STENCIL_ENABLE(1);
813 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
814 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
815 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
816 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
817
818 if (state->stencil[1].enabled) {
819 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
820 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
821 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
822 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
823 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
824 }
825 }
826
827 /* alpha */
828 alpha_test_control = 0;
829 alpha_ref = 0;
830 if (state->alpha.enabled) {
831 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
832 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
833 alpha_ref = fui(state->alpha.ref_value);
834 }
835 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
836 dsa->alpha_ref = alpha_ref;
837
838 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
839 return dsa;
840 }
841
842 static void *r600_create_rs_state(struct pipe_context *ctx,
843 const struct pipe_rasterizer_state *state)
844 {
845 struct r600_context *rctx = (struct r600_context *)ctx;
846 unsigned tmp, sc_mode_cntl, spi_interp;
847 float psize_min, psize_max;
848 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
849
850 if (rs == NULL) {
851 return NULL;
852 }
853
854 r600_init_command_buffer(&rs->buffer, 30);
855
856 rs->flatshade = state->flatshade;
857 rs->sprite_coord_enable = state->sprite_coord_enable;
858 rs->two_side = state->light_twoside;
859 rs->clip_plane_enable = state->clip_plane_enable;
860 rs->pa_sc_line_stipple = state->line_stipple_enable ?
861 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
862 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
863 rs->pa_cl_clip_cntl =
864 S_028810_PS_UCP_MODE(3) |
865 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
866 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
867 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
868 rs->multisample_enable = state->multisample;
869
870 /* offset */
871 rs->offset_units = state->offset_units;
872 rs->offset_scale = state->offset_scale * 12.0f;
873 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
874
875 if (state->point_size_per_vertex) {
876 psize_min = util_get_min_point_size(state);
877 psize_max = 8192;
878 } else {
879 /* Force the point size to be as if the vertex output was disabled. */
880 psize_min = state->point_size;
881 psize_max = state->point_size;
882 }
883
884 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
885 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
886 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
887 if (rctx->chip_class >= R700) {
888 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
889 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
890 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
891 } else {
892 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
893 rs->scissor_enable = state->scissor;
894 }
895
896 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
897 if (state->sprite_coord_enable) {
898 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
899 S_0286D4_PNT_SPRITE_OVRD_X(2) |
900 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
901 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
902 S_0286D4_PNT_SPRITE_OVRD_W(1);
903 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
904 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
905 }
906 }
907
908 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
909 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
910 tmp = r600_pack_float_12p4(state->point_size/2);
911 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
912 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
913 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
914 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
915 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
916 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
917 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
918
919 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
920 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
921 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
922 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
923 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
924 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
925 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
926 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
927 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
928 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
929 S_028814_FACE(!state->front_ccw) |
930 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
931 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
932 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
933 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
934 state->fill_back != PIPE_POLYGON_MODE_FILL) |
935 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
936 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
937 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
938 return rs;
939 }
940
941 static void *r600_create_sampler_state(struct pipe_context *ctx,
942 const struct pipe_sampler_state *state)
943 {
944 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
945 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
946
947 if (ss == NULL) {
948 return NULL;
949 }
950
951 ss->seamless_cube_map = state->seamless_cube_map;
952 ss->border_color_use = sampler_state_needs_border_color(state);
953
954 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
955 ss->tex_sampler_words[0] =
956 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
957 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
958 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
959 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
960 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
961 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
962 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
963 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
964 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
965 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
966 ss->tex_sampler_words[1] =
967 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
968 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
969 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
970 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
971 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
972
973 if (ss->border_color_use) {
974 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
975 }
976 return ss;
977 }
978
979 static struct pipe_sampler_view *
980 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
981 unsigned width0, unsigned height0)
982
983 {
984 struct pipe_context *ctx = view->base.context;
985 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
986 uint64_t va;
987 int stride = util_format_get_blocksize(view->base.format);
988 unsigned format, num_format, format_comp, endian;
989
990 r600_vertex_data_type(view->base.format,
991 &format, &num_format, &format_comp,
992 &endian);
993
994 va = r600_resource_va(ctx->screen, view->base.texture);
995 view->tex_resource = &tmp->resource;
996
997 view->skip_mip_address_reloc = true;
998 view->tex_resource_words[0] = va;
999 view->tex_resource_words[1] = width0 - 1;
1000 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(va >> 32UL) |
1001 S_038008_STRIDE(stride) |
1002 S_038008_DATA_FORMAT(format) |
1003 S_038008_NUM_FORMAT_ALL(num_format) |
1004 S_038008_FORMAT_COMP_ALL(format_comp) |
1005 S_038008_SRF_MODE_ALL(1) |
1006 S_038008_ENDIAN_SWAP(endian);
1007 view->tex_resource_words[3] = 0;
1008 /*
1009 * in theory dword 4 is for number of elements, for use with resinfo,
1010 * but it seems to utterly fail to work, the amd gpu shader analyser
1011 * uses a const buffer to store the element sizes for buffer txq
1012 */
1013 view->tex_resource_words[4] = 0;
1014 view->tex_resource_words[5] = 0;
1015 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
1016 return &view->base;
1017 }
1018
1019 struct pipe_sampler_view *
1020 r600_create_sampler_view_custom(struct pipe_context *ctx,
1021 struct pipe_resource *texture,
1022 const struct pipe_sampler_view *state,
1023 unsigned width_first_level, unsigned height_first_level)
1024 {
1025 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1026 struct r600_texture *tmp = (struct r600_texture*)texture;
1027 unsigned format, endian;
1028 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1029 unsigned char swizzle[4], array_mode = 0;
1030 unsigned width, height, depth, offset_level, last_level;
1031
1032 if (view == NULL)
1033 return NULL;
1034
1035 /* initialize base object */
1036 view->base = *state;
1037 view->base.texture = NULL;
1038 pipe_reference(NULL, &texture->reference);
1039 view->base.texture = texture;
1040 view->base.reference.count = 1;
1041 view->base.context = ctx;
1042
1043 if (texture->target == PIPE_BUFFER)
1044 return texture_buffer_sampler_view(view, texture->width0, 1);
1045
1046 swizzle[0] = state->swizzle_r;
1047 swizzle[1] = state->swizzle_g;
1048 swizzle[2] = state->swizzle_b;
1049 swizzle[3] = state->swizzle_a;
1050
1051 format = r600_translate_texformat(ctx->screen, state->format,
1052 swizzle,
1053 &word4, &yuv_format);
1054 assert(format != ~0);
1055 if (format == ~0) {
1056 FREE(view);
1057 return NULL;
1058 }
1059
1060 if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) {
1061 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1062 FREE(view);
1063 return NULL;
1064 }
1065 tmp = tmp->flushed_depth_texture;
1066 }
1067
1068 endian = r600_colorformat_endian_swap(format);
1069
1070 offset_level = state->u.tex.first_level;
1071 last_level = state->u.tex.last_level - offset_level;
1072 width = width_first_level;
1073 height = height_first_level;
1074 depth = tmp->surface.level[offset_level].npix_z;
1075 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1076
1077 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1078 height = 1;
1079 depth = texture->array_size;
1080 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1081 depth = texture->array_size;
1082 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
1083 depth = texture->array_size / 6;
1084 switch (tmp->surface.level[offset_level].mode) {
1085 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1086 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1087 break;
1088 case RADEON_SURF_MODE_1D:
1089 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1090 break;
1091 case RADEON_SURF_MODE_2D:
1092 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1093 break;
1094 case RADEON_SURF_MODE_LINEAR:
1095 default:
1096 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1097 break;
1098 }
1099
1100 view->tex_resource = &tmp->resource;
1101 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1102 S_038000_TILE_MODE(array_mode) |
1103 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
1104 S_038000_PITCH((pitch / 8) - 1) |
1105 S_038000_TEX_WIDTH(width - 1));
1106 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
1107 S_038004_TEX_DEPTH(depth - 1) |
1108 S_038004_DATA_FORMAT(format));
1109 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
1110 if (offset_level >= tmp->surface.last_level) {
1111 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
1112 } else {
1113 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1114 }
1115 view->tex_resource_words[4] = (word4 |
1116 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1117 S_038010_REQUEST_SIZE(1) |
1118 S_038010_ENDIAN_SWAP(endian) |
1119 S_038010_BASE_LEVEL(0));
1120 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1121 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1122 if (texture->nr_samples > 1) {
1123 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1124 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
1125 } else {
1126 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
1127 }
1128 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1129 S_038018_MAX_ANISO(4 /* max 16 samples */));
1130 return &view->base;
1131 }
1132
1133 static struct pipe_sampler_view *
1134 r600_create_sampler_view(struct pipe_context *ctx,
1135 struct pipe_resource *tex,
1136 const struct pipe_sampler_view *state)
1137 {
1138 struct r600_texture *rtex = (struct r600_texture*)tex;
1139
1140 return r600_create_sampler_view_custom(ctx, tex, state,
1141 rtex->surface.level[state->u.tex.first_level].npix_x,
1142 rtex->surface.level[state->u.tex.first_level].npix_y);
1143 }
1144
1145 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1146 {
1147 struct radeon_winsys_cs *cs = rctx->cs;
1148 struct pipe_clip_state *state = &rctx->clip_state.state;
1149
1150 r600_write_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
1151 r600_write_array(cs, 6*4, (unsigned*)state);
1152 }
1153
1154 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1155 const struct pipe_poly_stipple *state)
1156 {
1157 }
1158
1159 static void r600_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
1160 {
1161 struct radeon_winsys_cs *cs = rctx->cs;
1162 struct pipe_scissor_state *state = &rctx->scissor.scissor;
1163
1164 if (rctx->chip_class != R600 || rctx->scissor.enable) {
1165 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1166 r600_write_value(cs, S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) |
1167 S_028240_WINDOW_OFFSET_DISABLE(1));
1168 r600_write_value(cs, S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy));
1169 } else {
1170 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1171 r600_write_value(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1172 S_028240_WINDOW_OFFSET_DISABLE(1));
1173 r600_write_value(cs, S_028244_BR_X(8192) | S_028244_BR_Y(8192));
1174 }
1175 }
1176
1177 static void r600_set_scissor_state(struct pipe_context *ctx,
1178 const struct pipe_scissor_state *state)
1179 {
1180 struct r600_context *rctx = (struct r600_context *)ctx;
1181
1182 rctx->scissor.scissor = *state;
1183
1184 if (rctx->chip_class == R600 && !rctx->scissor.enable)
1185 return;
1186
1187 rctx->scissor.atom.dirty = true;
1188 }
1189
1190 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
1191 unsigned size, unsigned alignment)
1192 {
1193 struct pipe_resource buffer;
1194
1195 memset(&buffer, 0, sizeof buffer);
1196 buffer.target = PIPE_BUFFER;
1197 buffer.format = PIPE_FORMAT_R8_UNORM;
1198 buffer.bind = PIPE_BIND_CUSTOM;
1199 buffer.usage = PIPE_USAGE_STATIC;
1200 buffer.flags = 0;
1201 buffer.width0 = size;
1202 buffer.height0 = 1;
1203 buffer.depth0 = 1;
1204 buffer.array_size = 1;
1205
1206 return (struct r600_resource*)
1207 r600_buffer_create(&rscreen->screen, &buffer, alignment);
1208 }
1209
1210 static void r600_init_color_surface(struct r600_context *rctx,
1211 struct r600_surface *surf,
1212 bool force_cmask_fmask)
1213 {
1214 struct r600_screen *rscreen = rctx->screen;
1215 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1216 unsigned level = surf->base.u.tex.level;
1217 unsigned pitch, slice;
1218 unsigned color_info;
1219 unsigned format, swap, ntype, endian;
1220 unsigned offset;
1221 const struct util_format_description *desc;
1222 int i;
1223 bool blend_bypass = 0, blend_clamp = 1;
1224
1225 if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
1226 r600_init_flushed_depth_texture(&rctx->context, surf->base.texture, NULL);
1227 rtex = rtex->flushed_depth_texture;
1228 assert(rtex);
1229 }
1230
1231 offset = rtex->surface.level[level].offset;
1232 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1233 offset += rtex->surface.level[level].slice_size *
1234 surf->base.u.tex.first_layer;
1235 }
1236 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1237 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1238 if (slice) {
1239 slice = slice - 1;
1240 }
1241 color_info = 0;
1242 switch (rtex->surface.level[level].mode) {
1243 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1244 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1245 break;
1246 case RADEON_SURF_MODE_1D:
1247 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1248 break;
1249 case RADEON_SURF_MODE_2D:
1250 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1251 break;
1252 case RADEON_SURF_MODE_LINEAR:
1253 default:
1254 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1255 break;
1256 }
1257
1258 desc = util_format_description(surf->base.format);
1259
1260 for (i = 0; i < 4; i++) {
1261 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1262 break;
1263 }
1264 }
1265
1266 ntype = V_0280A0_NUMBER_UNORM;
1267 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1268 ntype = V_0280A0_NUMBER_SRGB;
1269 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1270 if (desc->channel[i].normalized)
1271 ntype = V_0280A0_NUMBER_SNORM;
1272 else if (desc->channel[i].pure_integer)
1273 ntype = V_0280A0_NUMBER_SINT;
1274 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1275 if (desc->channel[i].normalized)
1276 ntype = V_0280A0_NUMBER_UNORM;
1277 else if (desc->channel[i].pure_integer)
1278 ntype = V_0280A0_NUMBER_UINT;
1279 }
1280
1281 format = r600_translate_colorformat(surf->base.format);
1282 assert(format != ~0);
1283
1284 swap = r600_translate_colorswap(surf->base.format);
1285 assert(swap != ~0);
1286
1287 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1288 endian = ENDIAN_NONE;
1289 } else {
1290 endian = r600_colorformat_endian_swap(format);
1291 }
1292
1293 /* set blend bypass according to docs if SINT/UINT or
1294 8/24 COLOR variants */
1295 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1296 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1297 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1298 blend_clamp = 0;
1299 blend_bypass = 1;
1300 }
1301
1302 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
1303
1304 color_info |= S_0280A0_FORMAT(format) |
1305 S_0280A0_COMP_SWAP(swap) |
1306 S_0280A0_BLEND_BYPASS(blend_bypass) |
1307 S_0280A0_BLEND_CLAMP(blend_clamp) |
1308 S_0280A0_NUMBER_TYPE(ntype) |
1309 S_0280A0_ENDIAN(endian);
1310
1311 /* EXPORT_NORM is an optimzation that can be enabled for better
1312 * performance in certain cases
1313 */
1314 if (rctx->chip_class == R600) {
1315 /* EXPORT_NORM can be enabled if:
1316 * - 11-bit or smaller UNORM/SNORM/SRGB
1317 * - BLEND_CLAMP is enabled
1318 * - BLEND_FLOAT32 is disabled
1319 */
1320 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1321 (desc->channel[i].size < 12 &&
1322 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1323 ntype != V_0280A0_NUMBER_UINT &&
1324 ntype != V_0280A0_NUMBER_SINT) &&
1325 G_0280A0_BLEND_CLAMP(color_info) &&
1326 !G_0280A0_BLEND_FLOAT32(color_info)) {
1327 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1328 surf->export_16bpc = true;
1329 }
1330 } else {
1331 /* EXPORT_NORM can be enabled if:
1332 * - 11-bit or smaller UNORM/SNORM/SRGB
1333 * - 16-bit or smaller FLOAT
1334 */
1335 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1336 ((desc->channel[i].size < 12 &&
1337 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1338 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1339 (desc->channel[i].size < 17 &&
1340 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1341 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1342 surf->export_16bpc = true;
1343 }
1344 }
1345
1346 /* These might not always be initialized to zero. */
1347 surf->cb_color_base = offset >> 8;
1348 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
1349 S_028060_SLICE_TILE_MAX(slice);
1350 surf->cb_color_fmask = surf->cb_color_base;
1351 surf->cb_color_cmask = surf->cb_color_base;
1352 surf->cb_color_mask = 0;
1353
1354 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1355 &rtex->resource.b.b);
1356 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1357 &rtex->resource.b.b);
1358
1359 if (rtex->cmask_size) {
1360 surf->cb_color_cmask = rtex->cmask_offset >> 8;
1361 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask_slice_tile_max);
1362
1363 if (rtex->fmask_size) {
1364 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1365 surf->cb_color_fmask = rtex->fmask_offset >> 8;
1366 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(slice);
1367 } else { /* cmask only */
1368 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
1369 }
1370 } else if (force_cmask_fmask) {
1371 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1372 *
1373 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1374 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1375 * because it's not an MSAA buffer.
1376 */
1377 struct r600_cmask_info cmask;
1378 struct r600_fmask_info fmask;
1379
1380 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
1381 r600_texture_get_fmask_info(rscreen, rtex, 8, &fmask);
1382
1383 /* CMASK. */
1384 if (!rctx->dummy_cmask ||
1385 rctx->dummy_cmask->buf->size < cmask.size ||
1386 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1387 struct pipe_transfer *transfer;
1388 void *ptr;
1389
1390 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1391 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1392
1393 /* Set the contents to 0xCC. */
1394 ptr = pipe_buffer_map(&rctx->context, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1395 memset(ptr, 0xCC, cmask.size);
1396 pipe_buffer_unmap(&rctx->context, transfer);
1397 }
1398 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1399 &rctx->dummy_cmask->b.b);
1400
1401 /* FMASK. */
1402 if (!rctx->dummy_fmask ||
1403 rctx->dummy_fmask->buf->size < fmask.size ||
1404 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1405 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1406 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1407
1408 }
1409 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1410 &rctx->dummy_fmask->b.b);
1411
1412 /* Init the registers. */
1413 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1414 surf->cb_color_cmask = 0;
1415 surf->cb_color_fmask = 0;
1416 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1417 S_028100_FMASK_TILE_MAX(slice);
1418 }
1419
1420 surf->cb_color_info = color_info;
1421
1422 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1423 surf->cb_color_view = 0;
1424 } else {
1425 surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
1426 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
1427 }
1428
1429 surf->color_initialized = true;
1430 }
1431
1432 static void r600_init_depth_surface(struct r600_context *rctx,
1433 struct r600_surface *surf)
1434 {
1435 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1436 unsigned level, pitch, slice, format, offset, array_mode;
1437
1438 level = surf->base.u.tex.level;
1439 offset = rtex->surface.level[level].offset;
1440 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1441 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1442 if (slice) {
1443 slice = slice - 1;
1444 }
1445 switch (rtex->surface.level[level].mode) {
1446 case RADEON_SURF_MODE_2D:
1447 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1448 break;
1449 case RADEON_SURF_MODE_1D:
1450 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1451 case RADEON_SURF_MODE_LINEAR:
1452 default:
1453 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1454 break;
1455 }
1456
1457 format = r600_translate_dbformat(surf->base.format);
1458 assert(format != ~0);
1459
1460 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1461 surf->db_depth_base = offset >> 8;
1462 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1463 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1464 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1465 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1466
1467 switch (surf->base.format) {
1468 case PIPE_FORMAT_Z24X8_UNORM:
1469 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1470 surf->pa_su_poly_offset_db_fmt_cntl =
1471 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1472 break;
1473 case PIPE_FORMAT_Z32_FLOAT:
1474 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1475 surf->pa_su_poly_offset_db_fmt_cntl =
1476 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1477 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1478 break;
1479 case PIPE_FORMAT_Z16_UNORM:
1480 surf->pa_su_poly_offset_db_fmt_cntl =
1481 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1482 break;
1483 default:;
1484 }
1485
1486 surf->htile_enabled = 0;
1487 /* use htile only for first level */
1488 if (rtex->htile && !level) {
1489 uint64_t va = r600_resource_va(rctx->screen, rtex->htile);
1490 surf->htile_enabled = 1;
1491 surf->db_htile_data_base = va >> 8;
1492 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1493 S_028D24_HTILE_HEIGHT(1) |
1494 S_028D24_LINEAR(1);
1495 /* preload is not working properly on r6xx/r7xx */
1496 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1497 }
1498
1499 surf->depth_initialized = true;
1500 }
1501
1502 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1503 const struct pipe_framebuffer_state *state)
1504 {
1505 struct r600_context *rctx = (struct r600_context *)ctx;
1506 struct r600_surface *surf;
1507 struct r600_texture *rtex;
1508 unsigned i;
1509
1510 if (rctx->framebuffer.state.nr_cbufs) {
1511 rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1512
1513 if (rctx->chip_class >= R700 &&
1514 rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
1515 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
1516 }
1517 }
1518 if (rctx->framebuffer.state.zsbuf) {
1519 rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1520 }
1521
1522 /* Set the new state. */
1523 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1524
1525 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1526 rctx->framebuffer.cb0_is_integer = state->nr_cbufs &&
1527 util_format_is_pure_integer(state->cbufs[0]->format);
1528 rctx->framebuffer.compressed_cb_mask = 0;
1529 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1530 state->cbufs[0]->texture->nr_samples > 1 &&
1531 state->cbufs[1]->texture->nr_samples <= 1;
1532
1533 if (state->nr_cbufs)
1534 rctx->framebuffer.nr_samples = state->cbufs[0]->texture->nr_samples;
1535 else if (state->zsbuf)
1536 rctx->framebuffer.nr_samples = state->zsbuf->texture->nr_samples;
1537 else
1538 rctx->framebuffer.nr_samples = 0;
1539
1540 /* Colorbuffers. */
1541 for (i = 0; i < state->nr_cbufs; i++) {
1542 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1543 bool force_cmask_fmask = rctx->chip_class == R600 &&
1544 rctx->framebuffer.is_msaa_resolve &&
1545 i == 1;
1546
1547 surf = (struct r600_surface*)state->cbufs[i];
1548 rtex = (struct r600_texture*)surf->base.texture;
1549
1550 if (!surf->color_initialized || force_cmask_fmask) {
1551 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1552 if (force_cmask_fmask) {
1553 /* re-initialize later without compression */
1554 surf->color_initialized = false;
1555 }
1556 }
1557
1558 if (!surf->export_16bpc) {
1559 rctx->framebuffer.export_16bpc = false;
1560 }
1561
1562 if (rtex->fmask_size && rtex->cmask_size) {
1563 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1564 }
1565 }
1566
1567 /* Update alpha-test state dependencies.
1568 * Alpha-test is done on the first colorbuffer only. */
1569 if (state->nr_cbufs) {
1570 surf = (struct r600_surface*)state->cbufs[0];
1571 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1572 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1573 rctx->alphatest_state.atom.dirty = true;
1574 }
1575 }
1576
1577 /* ZS buffer. */
1578 if (state->zsbuf) {
1579 surf = (struct r600_surface*)state->zsbuf;
1580
1581 if (!surf->depth_initialized) {
1582 r600_init_depth_surface(rctx, surf);
1583 }
1584
1585 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1586 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1587 rctx->poly_offset_state.atom.dirty = true;
1588 }
1589
1590 if (rctx->db_state.rsurf != surf) {
1591 rctx->db_state.rsurf = surf;
1592 rctx->db_state.atom.dirty = true;
1593 rctx->db_misc_state.atom.dirty = true;
1594 }
1595 } else if (rctx->db_state.rsurf) {
1596 rctx->db_state.rsurf = NULL;
1597 rctx->db_state.atom.dirty = true;
1598 rctx->db_misc_state.atom.dirty = true;
1599 }
1600
1601 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1602 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1603 rctx->cb_misc_state.atom.dirty = true;
1604 }
1605
1606 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1607 rctx->alphatest_state.bypass = false;
1608 rctx->alphatest_state.atom.dirty = true;
1609 }
1610
1611 r600_update_db_shader_control(rctx);
1612
1613 /* Calculate the CS size. */
1614 rctx->framebuffer.atom.num_dw =
1615 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1616
1617 if (rctx->framebuffer.state.nr_cbufs) {
1618 rctx->framebuffer.atom.num_dw += 6 * (2 + rctx->framebuffer.state.nr_cbufs);
1619 rctx->framebuffer.atom.num_dw += 6 * rctx->framebuffer.state.nr_cbufs; /* relocs */
1620
1621 }
1622 if (rctx->framebuffer.state.zsbuf) {
1623 rctx->framebuffer.atom.num_dw += 18;
1624 } else if (rctx->screen->info.drm_minor >= 18) {
1625 rctx->framebuffer.atom.num_dw += 3;
1626 }
1627 if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770) {
1628 rctx->framebuffer.atom.num_dw += 2;
1629 }
1630
1631 rctx->framebuffer.atom.dirty = true;
1632 }
1633
1634 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1635 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1636 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1637 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1638 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1639
1640 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1641 {
1642 static uint32_t sample_locs_2x[] = {
1643 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1644 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1645 };
1646 static unsigned max_dist_2x = 4;
1647 static uint32_t sample_locs_4x[] = {
1648 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1649 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1650 };
1651 static unsigned max_dist_4x = 6;
1652 static uint32_t sample_locs_8x[] = {
1653 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1654 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1655 };
1656 static unsigned max_dist_8x = 7;
1657
1658 struct radeon_winsys_cs *cs = rctx->cs;
1659 unsigned max_dist = 0;
1660
1661 if (rctx->family == CHIP_R600) {
1662 switch (nr_samples) {
1663 default:
1664 nr_samples = 0;
1665 break;
1666 case 2:
1667 r600_write_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1668 max_dist = max_dist_2x;
1669 break;
1670 case 4:
1671 r600_write_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1672 max_dist = max_dist_4x;
1673 break;
1674 case 8:
1675 r600_write_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1676 r600_write_value(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1677 r600_write_value(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1678 max_dist = max_dist_8x;
1679 break;
1680 }
1681 } else {
1682 switch (nr_samples) {
1683 default:
1684 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1685 r600_write_value(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1686 r600_write_value(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1687 nr_samples = 0;
1688 break;
1689 case 2:
1690 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1691 r600_write_value(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1692 r600_write_value(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1693 max_dist = max_dist_2x;
1694 break;
1695 case 4:
1696 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1697 r600_write_value(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1698 r600_write_value(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1699 max_dist = max_dist_4x;
1700 break;
1701 case 8:
1702 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1703 r600_write_value(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1704 r600_write_value(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1705 max_dist = max_dist_8x;
1706 break;
1707 }
1708 }
1709
1710 if (nr_samples > 1) {
1711 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1712 r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
1713 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1714 r600_write_value(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1715 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1716 } else {
1717 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1718 r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1719 r600_write_value(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1720 }
1721 }
1722
1723 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1724 {
1725 struct radeon_winsys_cs *cs = rctx->cs;
1726 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1727 unsigned nr_cbufs = state->nr_cbufs;
1728 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1729 unsigned i, sbu = 0;
1730
1731 /* Colorbuffers. */
1732 r600_write_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1733 for (i = 0; i < nr_cbufs; i++) {
1734 r600_write_value(cs, cb[i]->cb_color_info);
1735 }
1736 /* set CB_COLOR1_INFO for possible dual-src blending */
1737 if (i == 1) {
1738 r600_write_value(cs, cb[0]->cb_color_info);
1739 i++;
1740 }
1741 for (; i < 8; i++) {
1742 r600_write_value(cs, 0);
1743 }
1744
1745 if (nr_cbufs) {
1746 /* COLOR_BASE */
1747 r600_write_context_reg_seq(cs, R_028040_CB_COLOR0_BASE, nr_cbufs);
1748 for (i = 0; i < nr_cbufs; i++) {
1749 r600_write_value(cs, cb[i]->cb_color_base);
1750 }
1751
1752 /* relocations */
1753 for (i = 0; i < nr_cbufs; i++) {
1754 unsigned reloc = r600_context_bo_reloc(rctx,
1755 (struct r600_resource*)cb[i]->base.texture,
1756 RADEON_USAGE_READWRITE);
1757 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1758 r600_write_value(cs, reloc);
1759 }
1760
1761 r600_write_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1762 for (i = 0; i < nr_cbufs; i++) {
1763 r600_write_value(cs, cb[i]->cb_color_size);
1764 }
1765
1766 r600_write_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1767 for (i = 0; i < nr_cbufs; i++) {
1768 r600_write_value(cs, cb[i]->cb_color_view);
1769 }
1770
1771 r600_write_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1772 for (i = 0; i < nr_cbufs; i++) {
1773 r600_write_value(cs, cb[i]->cb_color_mask);
1774 }
1775
1776 /* FMASK. */
1777 r600_write_context_reg_seq(cs, R_0280E0_CB_COLOR0_FRAG, nr_cbufs);
1778 for (i = 0; i < nr_cbufs; i++) {
1779 r600_write_value(cs, cb[i]->cb_color_fmask);
1780 }
1781 /* relocations */
1782 for (i = 0; i < nr_cbufs; i++) {
1783 unsigned reloc = r600_context_bo_reloc(rctx,
1784 cb[i]->cb_buffer_fmask,
1785 RADEON_USAGE_READWRITE);
1786 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1787 r600_write_value(cs, reloc);
1788 }
1789
1790 /* CMASK. */
1791 r600_write_context_reg_seq(cs, R_0280C0_CB_COLOR0_TILE, nr_cbufs);
1792 for (i = 0; i < nr_cbufs; i++) {
1793 r600_write_value(cs, cb[i]->cb_color_cmask);
1794 }
1795 /* relocations */
1796 for (i = 0; i < nr_cbufs; i++) {
1797 unsigned reloc = r600_context_bo_reloc(rctx,
1798 cb[i]->cb_buffer_cmask,
1799 RADEON_USAGE_READWRITE);
1800 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1801 r600_write_value(cs, reloc);
1802 }
1803
1804 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1805 }
1806
1807 /* SURFACE_BASE_UPDATE */
1808 if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770 && sbu) {
1809 r600_write_value(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1810 r600_write_value(cs, sbu);
1811 sbu = 0;
1812 }
1813
1814 /* Zbuffer. */
1815 if (state->zsbuf) {
1816 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1817 unsigned reloc = r600_context_bo_reloc(rctx,
1818 (struct r600_resource*)state->zsbuf->texture,
1819 RADEON_USAGE_READWRITE);
1820
1821 r600_write_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1822 surf->pa_su_poly_offset_db_fmt_cntl);
1823
1824 r600_write_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1825 r600_write_value(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1826 r600_write_value(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1827 r600_write_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1828 r600_write_value(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1829 r600_write_value(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1830
1831 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1832 r600_write_value(cs, reloc);
1833
1834 r600_write_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1835
1836 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1837 } else if (rctx->screen->info.drm_minor >= 18) {
1838 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1839 * Older kernels are out of luck. */
1840 r600_write_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1841 }
1842
1843 /* SURFACE_BASE_UPDATE */
1844 if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770 && sbu) {
1845 r600_write_value(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1846 r600_write_value(cs, sbu);
1847 sbu = 0;
1848 }
1849
1850 /* Framebuffer dimensions. */
1851 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1852 r600_write_value(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1853 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1854 r600_write_value(cs, S_028244_BR_X(state->width) |
1855 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1856
1857 if (rctx->framebuffer.is_msaa_resolve) {
1858 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1859 } else {
1860 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1861 * will assure that the alpha-test will work even if there is
1862 * no colorbuffer bound. */
1863 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1864 (1ull << MAX2(nr_cbufs, 1)) - 1);
1865 }
1866
1867 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1868 }
1869
1870 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1871 {
1872 struct radeon_winsys_cs *cs = rctx->cs;
1873 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1874
1875 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1876 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1877 if (rctx->chip_class == R600) {
1878 r600_write_value(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1879 r600_write_value(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1880 } else {
1881 r600_write_value(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1882 r600_write_value(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1883 }
1884 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1885 } else {
1886 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1887 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1888 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1889
1890 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1891 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1892 /* Always enable the first color output to make sure alpha-test works even without one. */
1893 r600_write_value(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1894 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1895 a->cb_color_control |
1896 S_028808_MULTIWRITE_ENABLE(multiwrite));
1897 }
1898 }
1899
1900 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1901 {
1902 struct radeon_winsys_cs *cs = rctx->cs;
1903 struct r600_db_state *a = (struct r600_db_state*)atom;
1904
1905 if (a->rsurf && a->rsurf->htile_enabled) {
1906 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1907 unsigned reloc_idx;
1908
1909 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear));
1910 r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1911 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1912 reloc_idx = r600_context_bo_reloc(rctx, rtex->htile, RADEON_USAGE_READWRITE);
1913 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1914 cs->buf[cs->cdw++] = reloc_idx;
1915 } else {
1916 r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1917 }
1918 }
1919
1920 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1921 {
1922 struct radeon_winsys_cs *cs = rctx->cs;
1923 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1924 unsigned db_render_control = 0;
1925 unsigned db_render_override =
1926 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1927 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1928
1929 if (a->occlusion_query_enabled) {
1930 if (rctx->chip_class >= R700) {
1931 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1932 }
1933 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1934 }
1935 if (rctx->db_state.rsurf && rctx->db_state.rsurf->htile_enabled) {
1936 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1937 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1938 } else {
1939 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1940 }
1941 if (a->flush_depthstencil_through_cb) {
1942 assert(a->copy_depth || a->copy_stencil);
1943
1944 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1945 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1946 S_028D0C_COPY_CENTROID(1) |
1947 S_028D0C_COPY_SAMPLE(a->copy_sample);
1948 } else if (a->flush_depthstencil_in_place) {
1949 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(1) |
1950 S_028D0C_STENCIL_COMPRESS_DISABLE(1);
1951 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1952 }
1953 if (a->htile_clear) {
1954 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1955 }
1956
1957 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1958 r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1959 r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1960 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1961 }
1962
1963 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1964 {
1965 struct radeon_winsys_cs *cs = rctx->cs;
1966 struct r600_config_state *a = (struct r600_config_state*)atom;
1967
1968 r600_write_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1969 }
1970
1971 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1972 {
1973 struct radeon_winsys_cs *cs = rctx->cs;
1974 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1975
1976 while (dirty_mask) {
1977 struct pipe_vertex_buffer *vb;
1978 struct r600_resource *rbuffer;
1979 unsigned offset;
1980 unsigned buffer_index = u_bit_scan(&dirty_mask);
1981
1982 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1983 rbuffer = (struct r600_resource*)vb->buffer;
1984 assert(rbuffer);
1985
1986 offset = vb->buffer_offset;
1987
1988 /* fetch resources start at index 320 */
1989 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1990 r600_write_value(cs, (320 + buffer_index) * 7);
1991 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1992 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1993 r600_write_value(cs, /* RESOURCEi_WORD2 */
1994 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1995 S_038008_STRIDE(vb->stride));
1996 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1997 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1998 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1999 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
2000
2001 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2002 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2003 }
2004 }
2005
2006 static void r600_emit_constant_buffers(struct r600_context *rctx,
2007 struct r600_constbuf_state *state,
2008 unsigned buffer_id_base,
2009 unsigned reg_alu_constbuf_size,
2010 unsigned reg_alu_const_cache)
2011 {
2012 struct radeon_winsys_cs *cs = rctx->cs;
2013 uint32_t dirty_mask = state->dirty_mask;
2014
2015 while (dirty_mask) {
2016 struct pipe_constant_buffer *cb;
2017 struct r600_resource *rbuffer;
2018 unsigned offset;
2019 unsigned buffer_index = ffs(dirty_mask) - 1;
2020
2021 cb = &state->cb[buffer_index];
2022 rbuffer = (struct r600_resource*)cb->buffer;
2023 assert(rbuffer);
2024
2025 offset = cb->buffer_offset;
2026
2027 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
2028 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
2029 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
2030
2031 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2032 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2033
2034 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
2035 r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
2036 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
2037 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
2038 r600_write_value(cs, /* RESOURCEi_WORD2 */
2039 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
2040 S_038008_STRIDE(16));
2041 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
2042 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
2043 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
2044 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
2045
2046 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2047 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2048
2049 dirty_mask &= ~(1 << buffer_index);
2050 }
2051 state->dirty_mask = 0;
2052 }
2053
2054 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2055 {
2056 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 160,
2057 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2058 R_028980_ALU_CONST_CACHE_VS_0);
2059 }
2060
2061 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2062 {
2063 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
2064 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2065 R_0289C0_ALU_CONST_CACHE_GS_0);
2066 }
2067
2068 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2069 {
2070 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
2071 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2072 R_028940_ALU_CONST_CACHE_PS_0);
2073 }
2074
2075 static void r600_emit_sampler_views(struct r600_context *rctx,
2076 struct r600_samplerview_state *state,
2077 unsigned resource_id_base)
2078 {
2079 struct radeon_winsys_cs *cs = rctx->cs;
2080 uint32_t dirty_mask = state->dirty_mask;
2081
2082 while (dirty_mask) {
2083 struct r600_pipe_sampler_view *rview;
2084 unsigned resource_index = u_bit_scan(&dirty_mask);
2085 unsigned reloc;
2086
2087 rview = state->views[resource_index];
2088 assert(rview);
2089
2090 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
2091 r600_write_value(cs, (resource_id_base + resource_index) * 7);
2092 r600_write_array(cs, 7, rview->tex_resource_words);
2093
2094 reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
2095 RADEON_USAGE_READ);
2096 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2097 r600_write_value(cs, reloc);
2098 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2099 r600_write_value(cs, reloc);
2100 }
2101 state->dirty_mask = 0;
2102 }
2103
2104 /* Resource IDs:
2105 * PS: 0 .. +160
2106 * VS: 160 .. +160
2107 * FS: 320 .. +16
2108 * GS: 336 .. +160
2109 */
2110
2111 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2112 {
2113 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 160 + R600_MAX_CONST_BUFFERS);
2114 }
2115
2116 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2117 {
2118 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
2119 }
2120
2121 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2122 {
2123 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
2124 }
2125
2126 static void r600_emit_sampler_states(struct r600_context *rctx,
2127 struct r600_textures_info *texinfo,
2128 unsigned resource_id_base,
2129 unsigned border_color_reg)
2130 {
2131 struct radeon_winsys_cs *cs = rctx->cs;
2132 uint32_t dirty_mask = texinfo->states.dirty_mask;
2133
2134 while (dirty_mask) {
2135 struct r600_pipe_sampler_state *rstate;
2136 struct r600_pipe_sampler_view *rview;
2137 unsigned i = u_bit_scan(&dirty_mask);
2138
2139 rstate = texinfo->states.states[i];
2140 assert(rstate);
2141 rview = texinfo->views.views[i];
2142
2143 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
2144 * filtering between layers.
2145 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
2146 */
2147 if (rview) {
2148 enum pipe_texture_target target = rview->base.texture->target;
2149 if (target == PIPE_TEXTURE_1D_ARRAY ||
2150 target == PIPE_TEXTURE_2D_ARRAY) {
2151 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
2152 texinfo->is_array_sampler[i] = true;
2153 } else {
2154 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
2155 texinfo->is_array_sampler[i] = false;
2156 }
2157 }
2158
2159 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2160 r600_write_value(cs, (resource_id_base + i) * 3);
2161 r600_write_array(cs, 3, rstate->tex_sampler_words);
2162
2163 if (rstate->border_color_use) {
2164 unsigned offset;
2165
2166 offset = border_color_reg;
2167 offset += i * 16;
2168 r600_write_config_reg_seq(cs, offset, 4);
2169 r600_write_array(cs, 4, rstate->border_color.ui);
2170 }
2171 }
2172 texinfo->states.dirty_mask = 0;
2173 }
2174
2175 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2176 {
2177 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
2178 }
2179
2180 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2181 {
2182 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
2183 }
2184
2185 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2186 {
2187 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
2188 }
2189
2190 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
2191 {
2192 struct radeon_winsys_cs *cs = rctx->cs;
2193 unsigned tmp;
2194
2195 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
2196 S_009508_SYNC_GRADIENT(1) |
2197 S_009508_SYNC_WALKER(1) |
2198 S_009508_SYNC_ALIGNER(1);
2199 if (!rctx->seamless_cube_map.enabled) {
2200 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
2201 }
2202 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
2203 }
2204
2205 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2206 {
2207 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2208 uint8_t mask = s->sample_mask;
2209
2210 r600_write_context_reg(rctx->cs, R_028C48_PA_SC_AA_MASK,
2211 mask | (mask << 8) | (mask << 16) | (mask << 24));
2212 }
2213
2214 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2215 {
2216 struct radeon_winsys_cs *cs = rctx->cs;
2217 struct r600_cso_state *state = (struct r600_cso_state*)a;
2218 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2219
2220 r600_write_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
2221 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2222 r600_write_value(cs, r600_context_bo_reloc(rctx, shader->buffer, RADEON_USAGE_READ));
2223 }
2224
2225 void r600_init_state_functions(struct r600_context *rctx)
2226 {
2227 unsigned id = 4;
2228
2229 /* !!!
2230 * To avoid GPU lockup registers must be emited in a specific order
2231 * (no kidding ...). The order below is important and have been
2232 * partialy infered from analyzing fglrx command stream.
2233 *
2234 * Don't reorder atom without carefully checking the effect (GPU lockup
2235 * or piglit regression).
2236 * !!!
2237 */
2238
2239 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
2240
2241 /* shader const */
2242 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
2243 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
2244 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
2245
2246 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2247 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
2248 */
2249 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
2250 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
2251 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
2252 /* resource */
2253 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
2254 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
2255 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
2256 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
2257
2258 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 6);
2259 r600_init_atom(rctx, &rctx->vgt2_state.atom, id++, r600_emit_vgt2_state, 3);
2260
2261 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
2262 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
2263 rctx->sample_mask.sample_mask = ~0;
2264
2265 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
2266 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
2267 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
2268 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
2269 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
2270 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
2271 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
2272 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
2273 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
2274 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
2275 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
2276 r600_init_atom(rctx, &rctx->scissor.atom, id++, r600_emit_scissor_state, 4);
2277 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
2278 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
2279 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
2280 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
2281
2282 rctx->context.create_blend_state = r600_create_blend_state;
2283 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
2284 rctx->context.create_rasterizer_state = r600_create_rs_state;
2285 rctx->context.create_sampler_state = r600_create_sampler_state;
2286 rctx->context.create_sampler_view = r600_create_sampler_view;
2287 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
2288 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
2289 rctx->context.set_scissor_state = r600_set_scissor_state;
2290 }
2291
2292 /* Adjust GPR allocation on R6xx/R7xx */
2293 bool r600_adjust_gprs(struct r600_context *rctx)
2294 {
2295 unsigned num_ps_gprs = rctx->ps_shader->current->shader.bc.ngpr;
2296 unsigned num_vs_gprs = rctx->vs_shader->current->shader.bc.ngpr;
2297 unsigned new_num_ps_gprs = num_ps_gprs;
2298 unsigned new_num_vs_gprs = num_vs_gprs;
2299 unsigned cur_num_ps_gprs = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2300 unsigned cur_num_vs_gprs = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2301 unsigned def_num_ps_gprs = rctx->default_ps_gprs;
2302 unsigned def_num_vs_gprs = rctx->default_vs_gprs;
2303 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
2304 /* hardware will reserve twice num_clause_temp_gprs */
2305 unsigned max_gprs = def_num_ps_gprs + def_num_vs_gprs + def_num_clause_temp_gprs * 2;
2306 unsigned tmp;
2307
2308 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2309 if (new_num_ps_gprs > cur_num_ps_gprs || new_num_vs_gprs > cur_num_vs_gprs) {
2310 /* try to use switch back to default */
2311 if (new_num_ps_gprs > def_num_ps_gprs || new_num_vs_gprs > def_num_vs_gprs) {
2312 /* always privilege vs stage so that at worst we have the
2313 * pixel stage producing wrong output (not the vertex
2314 * stage) */
2315 new_num_ps_gprs = max_gprs - (new_num_vs_gprs + def_num_clause_temp_gprs * 2);
2316 new_num_vs_gprs = num_vs_gprs;
2317 } else {
2318 new_num_ps_gprs = def_num_ps_gprs;
2319 new_num_vs_gprs = def_num_vs_gprs;
2320 }
2321 } else {
2322 return true;
2323 }
2324
2325 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2326 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2327 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2328 * it will lockup. So in this case just discard the draw command
2329 * and don't change the current gprs repartitions.
2330 */
2331 if (num_ps_gprs > new_num_ps_gprs || num_vs_gprs > new_num_vs_gprs) {
2332 R600_ERR("ps & vs shader require too many register (%d + %d) "
2333 "for a combined maximum of %d\n",
2334 num_ps_gprs, num_vs_gprs, max_gprs);
2335 return false;
2336 }
2337
2338 /* in some case we endup recomputing the current value */
2339 tmp = S_008C04_NUM_PS_GPRS(new_num_ps_gprs) |
2340 S_008C04_NUM_VS_GPRS(new_num_vs_gprs) |
2341 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2342 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp) {
2343 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2344 rctx->config_state.atom.dirty = true;
2345 rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
2346 }
2347 return true;
2348 }
2349
2350 void r600_init_atom_start_cs(struct r600_context *rctx)
2351 {
2352 int ps_prio;
2353 int vs_prio;
2354 int gs_prio;
2355 int es_prio;
2356 int num_ps_gprs;
2357 int num_vs_gprs;
2358 int num_gs_gprs;
2359 int num_es_gprs;
2360 int num_temp_gprs;
2361 int num_ps_threads;
2362 int num_vs_threads;
2363 int num_gs_threads;
2364 int num_es_threads;
2365 int num_ps_stack_entries;
2366 int num_vs_stack_entries;
2367 int num_gs_stack_entries;
2368 int num_es_stack_entries;
2369 enum radeon_family family;
2370 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2371 uint32_t tmp;
2372
2373 r600_init_command_buffer(cb, 256);
2374
2375 /* R6xx requires this packet at the start of each command buffer */
2376 if (rctx->chip_class == R600) {
2377 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2378 r600_store_value(cb, 0);
2379 }
2380 /* All asics require this one */
2381 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2382 r600_store_value(cb, 0x80000000);
2383 r600_store_value(cb, 0x80000000);
2384
2385 /* We're setting config registers here. */
2386 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2387 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2388
2389 family = rctx->family;
2390 ps_prio = 0;
2391 vs_prio = 1;
2392 gs_prio = 2;
2393 es_prio = 3;
2394 switch (family) {
2395 case CHIP_R600:
2396 num_ps_gprs = 192;
2397 num_vs_gprs = 56;
2398 num_temp_gprs = 4;
2399 num_gs_gprs = 0;
2400 num_es_gprs = 0;
2401 num_ps_threads = 136;
2402 num_vs_threads = 48;
2403 num_gs_threads = 4;
2404 num_es_threads = 4;
2405 num_ps_stack_entries = 128;
2406 num_vs_stack_entries = 128;
2407 num_gs_stack_entries = 0;
2408 num_es_stack_entries = 0;
2409 break;
2410 case CHIP_RV630:
2411 case CHIP_RV635:
2412 num_ps_gprs = 84;
2413 num_vs_gprs = 36;
2414 num_temp_gprs = 4;
2415 num_gs_gprs = 0;
2416 num_es_gprs = 0;
2417 num_ps_threads = 144;
2418 num_vs_threads = 40;
2419 num_gs_threads = 4;
2420 num_es_threads = 4;
2421 num_ps_stack_entries = 40;
2422 num_vs_stack_entries = 40;
2423 num_gs_stack_entries = 32;
2424 num_es_stack_entries = 16;
2425 break;
2426 case CHIP_RV610:
2427 case CHIP_RV620:
2428 case CHIP_RS780:
2429 case CHIP_RS880:
2430 default:
2431 num_ps_gprs = 84;
2432 num_vs_gprs = 36;
2433 num_temp_gprs = 4;
2434 num_gs_gprs = 0;
2435 num_es_gprs = 0;
2436 num_ps_threads = 136;
2437 num_vs_threads = 48;
2438 num_gs_threads = 4;
2439 num_es_threads = 4;
2440 num_ps_stack_entries = 40;
2441 num_vs_stack_entries = 40;
2442 num_gs_stack_entries = 32;
2443 num_es_stack_entries = 16;
2444 break;
2445 case CHIP_RV670:
2446 num_ps_gprs = 144;
2447 num_vs_gprs = 40;
2448 num_temp_gprs = 4;
2449 num_gs_gprs = 0;
2450 num_es_gprs = 0;
2451 num_ps_threads = 136;
2452 num_vs_threads = 48;
2453 num_gs_threads = 4;
2454 num_es_threads = 4;
2455 num_ps_stack_entries = 40;
2456 num_vs_stack_entries = 40;
2457 num_gs_stack_entries = 32;
2458 num_es_stack_entries = 16;
2459 break;
2460 case CHIP_RV770:
2461 num_ps_gprs = 192;
2462 num_vs_gprs = 56;
2463 num_temp_gprs = 4;
2464 num_gs_gprs = 0;
2465 num_es_gprs = 0;
2466 num_ps_threads = 188;
2467 num_vs_threads = 60;
2468 num_gs_threads = 0;
2469 num_es_threads = 0;
2470 num_ps_stack_entries = 256;
2471 num_vs_stack_entries = 256;
2472 num_gs_stack_entries = 0;
2473 num_es_stack_entries = 0;
2474 break;
2475 case CHIP_RV730:
2476 case CHIP_RV740:
2477 num_ps_gprs = 84;
2478 num_vs_gprs = 36;
2479 num_temp_gprs = 4;
2480 num_gs_gprs = 0;
2481 num_es_gprs = 0;
2482 num_ps_threads = 188;
2483 num_vs_threads = 60;
2484 num_gs_threads = 0;
2485 num_es_threads = 0;
2486 num_ps_stack_entries = 128;
2487 num_vs_stack_entries = 128;
2488 num_gs_stack_entries = 0;
2489 num_es_stack_entries = 0;
2490 break;
2491 case CHIP_RV710:
2492 num_ps_gprs = 192;
2493 num_vs_gprs = 56;
2494 num_temp_gprs = 4;
2495 num_gs_gprs = 0;
2496 num_es_gprs = 0;
2497 num_ps_threads = 144;
2498 num_vs_threads = 48;
2499 num_gs_threads = 0;
2500 num_es_threads = 0;
2501 num_ps_stack_entries = 128;
2502 num_vs_stack_entries = 128;
2503 num_gs_stack_entries = 0;
2504 num_es_stack_entries = 0;
2505 break;
2506 }
2507
2508 rctx->default_ps_gprs = num_ps_gprs;
2509 rctx->default_vs_gprs = num_vs_gprs;
2510 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2511
2512 /* SQ_CONFIG */
2513 tmp = 0;
2514 switch (family) {
2515 case CHIP_RV610:
2516 case CHIP_RV620:
2517 case CHIP_RS780:
2518 case CHIP_RS880:
2519 case CHIP_RV710:
2520 break;
2521 default:
2522 tmp |= S_008C00_VC_ENABLE(1);
2523 break;
2524 }
2525 tmp |= S_008C00_DX9_CONSTS(0);
2526 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2527 tmp |= S_008C00_PS_PRIO(ps_prio);
2528 tmp |= S_008C00_VS_PRIO(vs_prio);
2529 tmp |= S_008C00_GS_PRIO(gs_prio);
2530 tmp |= S_008C00_ES_PRIO(es_prio);
2531 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2532
2533 /* SQ_GPR_RESOURCE_MGMT_2 */
2534 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2535 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2536 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2537 r600_store_value(cb, tmp);
2538
2539 /* SQ_THREAD_RESOURCE_MGMT */
2540 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2541 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2542 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2543 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2544 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2545
2546 /* SQ_STACK_RESOURCE_MGMT_1 */
2547 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2548 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2549 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2550
2551 /* SQ_STACK_RESOURCE_MGMT_2 */
2552 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2553 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2554 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2555
2556 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2557
2558 if (rctx->chip_class >= R700) {
2559 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2560 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2561 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2562 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2563 } else {
2564 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2565 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2566 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2567 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2568 }
2569 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2570 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2571 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2572 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2573 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2574 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2575 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2576 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2577 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2578 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2579
2580 /* to avoid GPU doing any preloading of constant from random address */
2581 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2582 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2583 r600_store_value(cb, 0);
2584 r600_store_value(cb, 0);
2585 r600_store_value(cb, 0);
2586 r600_store_value(cb, 0);
2587 r600_store_value(cb, 0);
2588 r600_store_value(cb, 0);
2589 r600_store_value(cb, 0);
2590 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2591 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2592 r600_store_value(cb, 0);
2593 r600_store_value(cb, 0);
2594 r600_store_value(cb, 0);
2595 r600_store_value(cb, 0);
2596 r600_store_value(cb, 0);
2597 r600_store_value(cb, 0);
2598 r600_store_value(cb, 0);
2599
2600 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2601 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2602 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2603 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2604 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2605 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2606 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2607 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2608 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2609 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2610 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2611 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2612 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2613 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2614
2615 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2616 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2617 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2618
2619 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2620 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2621 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2622 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2623
2624 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2625
2626 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2627
2628 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2629
2630 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2631 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2632 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2633 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2634
2635 r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2636 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2637 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2638
2639 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2640 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2641
2642 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2643 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2644 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2645 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2646 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2647
2648 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2649 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2650 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2651
2652 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2653
2654 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2655 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2656
2657 if (rctx->chip_class >= R700) {
2658 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2659 }
2660
2661 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2662 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2663 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2664 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2665 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2666
2667 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2668 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2669 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2670
2671 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2672 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2673 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2674
2675 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2676 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2677 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2678
2679 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2680
2681 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2682 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2683 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2684
2685 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2686 r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2687
2688 if (rctx->chip_class == R700 && rctx->screen->has_streamout)
2689 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2690 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2691 if (rctx->screen->has_streamout) {
2692 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2693 }
2694
2695 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2696 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2697 }
2698
2699 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2700 {
2701 struct r600_context *rctx = (struct r600_context *)ctx;
2702 struct r600_pipe_state *rstate = &shader->rstate;
2703 struct r600_shader *rshader = &shader->shader;
2704 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2705 int pos_index = -1, face_index = -1;
2706 unsigned tmp, sid, ufi = 0;
2707 int need_linear = 0;
2708 unsigned z_export = 0, stencil_export = 0;
2709 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2710
2711 rstate->nregs = 0;
2712
2713 for (i = 0; i < rshader->ninput; i++) {
2714 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2715 pos_index = i;
2716 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2717 face_index = i;
2718
2719 sid = rshader->input[i].spi_sid;
2720
2721 tmp = S_028644_SEMANTIC(sid);
2722
2723 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2724 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2725 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2726 rctx->rasterizer && rctx->rasterizer->flatshade))
2727 tmp |= S_028644_FLAT_SHADE(1);
2728
2729 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2730 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2731 tmp |= S_028644_PT_SPRITE_TEX(1);
2732 }
2733
2734 if (rshader->input[i].centroid)
2735 tmp |= S_028644_SEL_CENTROID(1);
2736
2737 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2738 need_linear = 1;
2739 tmp |= S_028644_SEL_LINEAR(1);
2740 }
2741
2742 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2743 tmp);
2744 }
2745
2746 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2747 for (i = 0; i < rshader->noutput; i++) {
2748 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2749 z_export = 1;
2750 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2751 stencil_export = 1;
2752 }
2753 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2754 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2755 if (rshader->uses_kill)
2756 db_shader_control |= S_02880C_KILL_ENABLE(1);
2757
2758 exports_ps = 0;
2759 for (i = 0; i < rshader->noutput; i++) {
2760 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2761 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2762 exports_ps |= 1;
2763 }
2764 }
2765 num_cout = rshader->nr_ps_color_exports;
2766 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2767 if (!exports_ps) {
2768 /* always at least export 1 component per pixel */
2769 exports_ps = 2;
2770 }
2771
2772 shader->nr_ps_color_outputs = num_cout;
2773
2774 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2775 S_0286CC_PERSP_GRADIENT_ENA(1)|
2776 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2777 spi_input_z = 0;
2778 if (pos_index != -1) {
2779 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2780 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2781 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2782 S_0286CC_BARYC_SAMPLE_CNTL(1));
2783 spi_input_z |= 1;
2784 }
2785
2786 spi_ps_in_control_1 = 0;
2787 if (face_index != -1) {
2788 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2789 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2790 }
2791
2792 /* HW bug in original R600 */
2793 if (rctx->family == CHIP_R600)
2794 ufi = 1;
2795
2796 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2797 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2798 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2799 r600_pipe_state_add_reg_bo(rstate,
2800 R_028840_SQ_PGM_START_PS,
2801 0, shader->bo, RADEON_USAGE_READ);
2802 r600_pipe_state_add_reg(rstate,
2803 R_028850_SQ_PGM_RESOURCES_PS,
2804 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2805 S_028850_STACK_SIZE(rshader->bc.nstack) |
2806 S_028850_UNCACHED_FIRST_INST(ufi));
2807 r600_pipe_state_add_reg(rstate,
2808 R_028854_SQ_PGM_EXPORTS_PS,
2809 exports_ps);
2810 /* only set some bits here, the other bits are set in the dsa state */
2811 shader->db_shader_control = db_shader_control;
2812 shader->ps_depth_export = z_export | stencil_export;
2813
2814 shader->sprite_coord_enable = sprite_coord_enable;
2815 if (rctx->rasterizer)
2816 shader->flatshade = rctx->rasterizer->flatshade;
2817 }
2818
2819 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2820 {
2821 struct r600_context *rctx = (struct r600_context *)ctx;
2822 struct r600_pipe_state *rstate = &shader->rstate;
2823 struct r600_shader *rshader = &shader->shader;
2824 unsigned spi_vs_out_id[10] = {};
2825 unsigned i, tmp, nparams = 0;
2826
2827 /* clear previous register */
2828 rstate->nregs = 0;
2829
2830 for (i = 0; i < rshader->noutput; i++) {
2831 if (rshader->output[i].spi_sid) {
2832 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2833 spi_vs_out_id[nparams / 4] |= tmp;
2834 nparams++;
2835 }
2836 }
2837
2838 for (i = 0; i < 10; i++) {
2839 r600_pipe_state_add_reg(rstate,
2840 R_028614_SPI_VS_OUT_ID_0 + i * 4,
2841 spi_vs_out_id[i]);
2842 }
2843
2844 /* Certain attributes (position, psize, etc.) don't count as params.
2845 * VS is required to export at least one param and r600_shader_from_tgsi()
2846 * takes care of adding a dummy export.
2847 */
2848 if (nparams < 1)
2849 nparams = 1;
2850
2851 r600_pipe_state_add_reg(rstate,
2852 R_0286C4_SPI_VS_OUT_CONFIG,
2853 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2854 r600_pipe_state_add_reg(rstate,
2855 R_028868_SQ_PGM_RESOURCES_VS,
2856 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2857 S_028868_STACK_SIZE(rshader->bc.nstack));
2858 r600_pipe_state_add_reg_bo(rstate,
2859 R_028858_SQ_PGM_START_VS,
2860 0, shader->bo, RADEON_USAGE_READ);
2861
2862 shader->pa_cl_vs_out_cntl =
2863 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2864 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2865 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2866 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2867 }
2868
2869 void *r600_create_resolve_blend(struct r600_context *rctx)
2870 {
2871 struct pipe_blend_state blend;
2872 unsigned i;
2873
2874 memset(&blend, 0, sizeof(blend));
2875 blend.independent_blend_enable = true;
2876 for (i = 0; i < 2; i++) {
2877 blend.rt[i].colormask = 0xf;
2878 blend.rt[i].blend_enable = 1;
2879 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2880 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2881 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2882 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2883 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2884 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2885 }
2886 return r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2887 }
2888
2889 void *r700_create_resolve_blend(struct r600_context *rctx)
2890 {
2891 struct pipe_blend_state blend;
2892
2893 memset(&blend, 0, sizeof(blend));
2894 blend.independent_blend_enable = true;
2895 blend.rt[0].colormask = 0xf;
2896 return r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2897 }
2898
2899 void *r600_create_decompress_blend(struct r600_context *rctx)
2900 {
2901 struct pipe_blend_state blend;
2902
2903 memset(&blend, 0, sizeof(blend));
2904 blend.independent_blend_enable = true;
2905 blend.rt[0].colormask = 0xf;
2906 return r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2907 }
2908
2909 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2910 {
2911 struct pipe_depth_stencil_alpha_state dsa;
2912 boolean quirk = false;
2913
2914 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2915 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2916 quirk = true;
2917
2918 memset(&dsa, 0, sizeof(dsa));
2919
2920 if (quirk) {
2921 dsa.depth.enabled = 1;
2922 dsa.depth.func = PIPE_FUNC_LEQUAL;
2923 dsa.stencil[0].enabled = 1;
2924 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2925 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2926 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2927 dsa.stencil[0].writemask = 0xff;
2928 }
2929
2930 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2931 }
2932
2933 void r600_update_db_shader_control(struct r600_context * rctx)
2934 {
2935 bool dual_export = rctx->framebuffer.export_16bpc &&
2936 !rctx->ps_shader->current->ps_depth_export;
2937
2938 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2939 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2940
2941 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
2942 rctx->db_misc_state.db_shader_control = db_shader_control;
2943 rctx->db_misc_state.atom.dirty = true;
2944 }
2945 }