2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
24 #include "r600_shader.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
33 static uint32_t r600_translate_blend_function(int blend_func
)
37 return V_028804_COMB_DST_PLUS_SRC
;
38 case PIPE_BLEND_SUBTRACT
:
39 return V_028804_COMB_SRC_MINUS_DST
;
40 case PIPE_BLEND_REVERSE_SUBTRACT
:
41 return V_028804_COMB_DST_MINUS_SRC
;
43 return V_028804_COMB_MIN_DST_SRC
;
45 return V_028804_COMB_MAX_DST_SRC
;
47 R600_ERR("Unknown blend function %d\n", blend_func
);
54 static uint32_t r600_translate_blend_factor(int blend_fact
)
57 case PIPE_BLENDFACTOR_ONE
:
58 return V_028804_BLEND_ONE
;
59 case PIPE_BLENDFACTOR_SRC_COLOR
:
60 return V_028804_BLEND_SRC_COLOR
;
61 case PIPE_BLENDFACTOR_SRC_ALPHA
:
62 return V_028804_BLEND_SRC_ALPHA
;
63 case PIPE_BLENDFACTOR_DST_ALPHA
:
64 return V_028804_BLEND_DST_ALPHA
;
65 case PIPE_BLENDFACTOR_DST_COLOR
:
66 return V_028804_BLEND_DST_COLOR
;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE
;
69 case PIPE_BLENDFACTOR_CONST_COLOR
:
70 return V_028804_BLEND_CONST_COLOR
;
71 case PIPE_BLENDFACTOR_CONST_ALPHA
:
72 return V_028804_BLEND_CONST_ALPHA
;
73 case PIPE_BLENDFACTOR_ZERO
:
74 return V_028804_BLEND_ZERO
;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR
;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA
;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA
;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR
;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR
;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA
;
87 case PIPE_BLENDFACTOR_SRC1_COLOR
:
88 return V_028804_BLEND_SRC1_COLOR
;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
90 return V_028804_BLEND_SRC1_ALPHA
;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
92 return V_028804_BLEND_INV_SRC1_COLOR
;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
94 return V_028804_BLEND_INV_SRC1_ALPHA
;
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
103 static unsigned r600_tex_dim(unsigned dim
, unsigned nr_samples
)
107 case PIPE_TEXTURE_1D
:
108 return V_038000_SQ_TEX_DIM_1D
;
109 case PIPE_TEXTURE_1D_ARRAY
:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY
;
111 case PIPE_TEXTURE_2D
:
112 case PIPE_TEXTURE_RECT
:
113 return nr_samples
> 1 ? V_038000_SQ_TEX_DIM_2D_MSAA
:
114 V_038000_SQ_TEX_DIM_2D
;
115 case PIPE_TEXTURE_2D_ARRAY
:
116 return nr_samples
> 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
117 V_038000_SQ_TEX_DIM_2D_ARRAY
;
118 case PIPE_TEXTURE_3D
:
119 return V_038000_SQ_TEX_DIM_3D
;
120 case PIPE_TEXTURE_CUBE
:
121 case PIPE_TEXTURE_CUBE_ARRAY
:
122 return V_038000_SQ_TEX_DIM_CUBEMAP
;
126 static uint32_t r600_translate_dbformat(enum pipe_format format
)
129 case PIPE_FORMAT_Z16_UNORM
:
130 return V_028010_DEPTH_16
;
131 case PIPE_FORMAT_Z24X8_UNORM
:
132 return V_028010_DEPTH_X8_24
;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
134 return V_028010_DEPTH_8_24
;
135 case PIPE_FORMAT_Z32_FLOAT
:
136 return V_028010_DEPTH_32_FLOAT
;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
138 return V_028010_DEPTH_X24_8_32_FLOAT
;
144 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
146 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
) != ~0U;
149 static bool r600_is_colorbuffer_format_supported(enum chip_class chip
, enum pipe_format format
)
151 return r600_translate_colorformat(chip
, format
) != ~0U &&
152 r600_translate_colorswap(format
) != ~0U;
155 static bool r600_is_zs_format_supported(enum pipe_format format
)
157 return r600_translate_dbformat(format
) != ~0U;
160 static inline bool r600_is_blending_supported(enum pipe_format format
)
162 return !(util_format_is_pure_integer(format
) || util_format_is_depth_or_stencil(format
));
165 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
166 enum pipe_format format
,
167 enum pipe_texture_target target
,
168 unsigned sample_count
,
171 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
174 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
175 R600_ERR("r600: unsupported texture type %d\n", target
);
179 if (!util_format_is_supported(format
, usage
))
182 if (sample_count
> 1) {
183 if (!rscreen
->has_msaa
)
186 /* R11G11B10 is broken on R6xx. */
187 if (rscreen
->b
.chip_class
== R600
&&
188 format
== PIPE_FORMAT_R11G11B10_FLOAT
)
191 /* MSAA integer colorbuffers hang. */
192 if (util_format_is_pure_integer(format
) &&
193 !util_format_is_depth_or_stencil(format
))
196 switch (sample_count
) {
206 if (usage
& PIPE_BIND_SAMPLER_VIEW
) {
207 if (target
== PIPE_BUFFER
) {
208 if (r600_is_vertex_format_supported(format
))
209 retval
|= PIPE_BIND_SAMPLER_VIEW
;
211 if (r600_is_sampler_format_supported(screen
, format
))
212 retval
|= PIPE_BIND_SAMPLER_VIEW
;
216 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
217 PIPE_BIND_DISPLAY_TARGET
|
219 PIPE_BIND_SHARED
)) &&
220 r600_is_colorbuffer_format_supported(rscreen
->b
.chip_class
, format
)) {
222 (PIPE_BIND_RENDER_TARGET
|
223 PIPE_BIND_DISPLAY_TARGET
|
228 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
229 r600_is_zs_format_supported(format
)) {
230 retval
|= PIPE_BIND_DEPTH_STENCIL
;
233 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
234 r600_is_vertex_format_supported(format
)) {
235 retval
|= PIPE_BIND_VERTEX_BUFFER
;
238 if (usage
& PIPE_BIND_TRANSFER_READ
)
239 retval
|= PIPE_BIND_TRANSFER_READ
;
240 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
241 retval
|= PIPE_BIND_TRANSFER_WRITE
;
243 if ((usage
& PIPE_BIND_BLENDABLE
) &&
244 r600_is_blending_supported(format
))
245 retval
|= PIPE_BIND_BLENDABLE
;
247 return retval
== usage
;
250 static void r600_emit_polygon_offset(struct r600_context
*rctx
, struct r600_atom
*a
)
252 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
253 struct r600_poly_offset_state
*state
= (struct r600_poly_offset_state
*)a
;
254 float offset_units
= state
->offset_units
;
255 float offset_scale
= state
->offset_scale
;
257 switch (state
->zs_format
) {
258 case PIPE_FORMAT_Z24X8_UNORM
:
259 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
260 offset_units
*= 2.0f
;
262 case PIPE_FORMAT_Z16_UNORM
:
263 offset_units
*= 4.0f
;
268 r600_write_context_reg_seq(cs
, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE
, 4);
269 radeon_emit(cs
, fui(offset_scale
));
270 radeon_emit(cs
, fui(offset_units
));
271 radeon_emit(cs
, fui(offset_scale
));
272 radeon_emit(cs
, fui(offset_units
));
275 static uint32_t r600_get_blend_control(const struct pipe_blend_state
*state
, unsigned i
)
277 int j
= state
->independent_blend_enable
? i
: 0;
279 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
280 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
281 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
283 unsigned eqA
= state
->rt
[j
].alpha_func
;
284 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
285 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
288 if (!state
->rt
[j
].blend_enable
)
291 bc
|= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
292 bc
|= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
293 bc
|= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
295 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
296 bc
|= S_028804_SEPARATE_ALPHA_BLEND(1);
297 bc
|= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
298 bc
|= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
299 bc
|= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
304 static void *r600_create_blend_state_mode(struct pipe_context
*ctx
,
305 const struct pipe_blend_state
*state
,
308 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
309 uint32_t color_control
= 0, target_mask
= 0;
310 struct r600_blend_state
*blend
= CALLOC_STRUCT(r600_blend_state
);
316 r600_init_command_buffer(&blend
->buffer
, 20);
317 r600_init_command_buffer(&blend
->buffer_no_blend
, 20);
319 /* R600 does not support per-MRT blends */
320 if (rctx
->b
.family
> CHIP_R600
)
321 color_control
|= S_028808_PER_MRT_BLEND(1);
323 if (state
->logicop_enable
) {
324 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
326 color_control
|= (0xcc << 16);
328 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
329 if (state
->independent_blend_enable
) {
330 for (int i
= 0; i
< 8; i
++) {
331 if (state
->rt
[i
].blend_enable
) {
332 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
334 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
337 for (int i
= 0; i
< 8; i
++) {
338 if (state
->rt
[0].blend_enable
) {
339 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
341 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
346 color_control
|= S_028808_SPECIAL_OP(mode
);
348 color_control
|= S_028808_SPECIAL_OP(V_028808_DISABLE
);
350 /* only MRT0 has dual src blend */
351 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
352 blend
->cb_target_mask
= target_mask
;
353 blend
->cb_color_control
= color_control
;
354 blend
->cb_color_control_no_blend
= color_control
& C_028808_TARGET_BLEND_ENABLE
;
355 blend
->alpha_to_one
= state
->alpha_to_one
;
357 r600_store_context_reg(&blend
->buffer
, R_028D44_DB_ALPHA_TO_MASK
,
358 S_028D44_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
359 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
360 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
361 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
362 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
364 /* Copy over the registers set so far into buffer_no_blend. */
365 memcpy(blend
->buffer_no_blend
.buf
, blend
->buffer
.buf
, blend
->buffer
.num_dw
* 4);
366 blend
->buffer_no_blend
.num_dw
= blend
->buffer
.num_dw
;
368 /* Only add blend registers if blending is enabled. */
369 if (!G_028808_TARGET_BLEND_ENABLE(color_control
)) {
373 /* The first R600 does not support per-MRT blends */
374 r600_store_context_reg(&blend
->buffer
, R_028804_CB_BLEND_CONTROL
,
375 r600_get_blend_control(state
, 0));
377 if (rctx
->b
.family
> CHIP_R600
) {
378 r600_store_context_reg_seq(&blend
->buffer
, R_028780_CB_BLEND0_CONTROL
, 8);
379 for (int i
= 0; i
< 8; i
++) {
380 r600_store_value(&blend
->buffer
, r600_get_blend_control(state
, i
));
386 static void *r600_create_blend_state(struct pipe_context
*ctx
,
387 const struct pipe_blend_state
*state
)
389 return r600_create_blend_state_mode(ctx
, state
, V_028808_SPECIAL_NORMAL
);
392 static void *r600_create_dsa_state(struct pipe_context
*ctx
,
393 const struct pipe_depth_stencil_alpha_state
*state
)
395 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
396 struct r600_dsa_state
*dsa
= CALLOC_STRUCT(r600_dsa_state
);
402 r600_init_command_buffer(&dsa
->buffer
, 3);
404 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
405 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
406 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
407 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
408 dsa
->zwritemask
= state
->depth
.writemask
;
410 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
411 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
412 S_028800_ZFUNC(state
->depth
.func
);
415 if (state
->stencil
[0].enabled
) {
416 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
417 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
418 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
419 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
420 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
422 if (state
->stencil
[1].enabled
) {
423 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
424 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
425 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
426 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
427 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
432 alpha_test_control
= 0;
434 if (state
->alpha
.enabled
) {
435 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
436 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
437 alpha_ref
= fui(state
->alpha
.ref_value
);
439 dsa
->sx_alpha_test_control
= alpha_test_control
& 0xff;
440 dsa
->alpha_ref
= alpha_ref
;
442 r600_store_context_reg(&dsa
->buffer
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
446 static void *r600_create_rs_state(struct pipe_context
*ctx
,
447 const struct pipe_rasterizer_state
*state
)
449 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
450 unsigned tmp
, sc_mode_cntl
, spi_interp
;
451 float psize_min
, psize_max
;
452 struct r600_rasterizer_state
*rs
= CALLOC_STRUCT(r600_rasterizer_state
);
458 r600_init_command_buffer(&rs
->buffer
, 30);
460 rs
->flatshade
= state
->flatshade
;
461 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
462 rs
->two_side
= state
->light_twoside
;
463 rs
->clip_plane_enable
= state
->clip_plane_enable
;
464 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
465 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
466 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
467 rs
->pa_cl_clip_cntl
=
468 S_028810_PS_UCP_MODE(3) |
469 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
470 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
471 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
472 if (rctx
->b
.chip_class
== R700
) {
473 rs
->pa_cl_clip_cntl
|=
474 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
);
476 rs
->multisample_enable
= state
->multisample
;
479 rs
->offset_units
= state
->offset_units
;
480 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
481 rs
->offset_enable
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
483 if (state
->point_size_per_vertex
) {
484 psize_min
= util_get_min_point_size(state
);
487 /* Force the point size to be as if the vertex output was disabled. */
488 psize_min
= state
->point_size
;
489 psize_max
= state
->point_size
;
492 sc_mode_cntl
= S_028A4C_MSAA_ENABLE(state
->multisample
) |
493 S_028A4C_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
494 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
495 if (rctx
->b
.chip_class
>= R700
) {
496 sc_mode_cntl
|= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
497 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
498 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state
->scissor
);
500 sc_mode_cntl
|= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
501 rs
->scissor_enable
= state
->scissor
;
504 spi_interp
= S_0286D4_FLAT_SHADE_ENA(1);
505 if (state
->sprite_coord_enable
) {
506 spi_interp
|= S_0286D4_PNT_SPRITE_ENA(1) |
507 S_0286D4_PNT_SPRITE_OVRD_X(2) |
508 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
509 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
510 S_0286D4_PNT_SPRITE_OVRD_W(1);
511 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
512 spi_interp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
516 r600_store_context_reg_seq(&rs
->buffer
, R_028A00_PA_SU_POINT_SIZE
, 3);
517 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
518 tmp
= r600_pack_float_12p4(state
->point_size
/2);
519 r600_store_value(&rs
->buffer
, /* R_028A00_PA_SU_POINT_SIZE */
520 S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
521 r600_store_value(&rs
->buffer
, /* R_028A04_PA_SU_POINT_MINMAX */
522 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
523 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
524 r600_store_value(&rs
->buffer
, /* R_028A08_PA_SU_LINE_CNTL */
525 S_028A08_WIDTH(r600_pack_float_12p4(state
->line_width
/2)));
527 r600_store_context_reg(&rs
->buffer
, R_0286D4_SPI_INTERP_CONTROL_0
, spi_interp
);
528 r600_store_context_reg(&rs
->buffer
, R_028A4C_PA_SC_MODE_CNTL
, sc_mode_cntl
);
529 r600_store_context_reg(&rs
->buffer
, R_028C08_PA_SU_VTX_CNTL
,
530 S_028C08_PIX_CENTER_HALF(state
->half_pixel_center
) |
531 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
532 r600_store_context_reg(&rs
->buffer
, R_028DFC_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
534 rs
->pa_su_sc_mode_cntl
= S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
535 S_028814_CULL_FRONT(state
->cull_face
& PIPE_FACE_FRONT
? 1 : 0) |
536 S_028814_CULL_BACK(state
->cull_face
& PIPE_FACE_BACK
? 1 : 0) |
537 S_028814_FACE(!state
->front_ccw
) |
538 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
539 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
540 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
541 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
542 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
543 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
544 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
));
545 if (rctx
->b
.chip_class
== R700
) {
546 r600_store_context_reg(&rs
->buffer
, R_028814_PA_SU_SC_MODE_CNTL
, rs
->pa_su_sc_mode_cntl
);
548 if (rctx
->b
.chip_class
== R600
) {
549 r600_store_context_reg(&rs
->buffer
, R_028350_SX_MISC
,
550 S_028350_MULTIPASS(state
->rasterizer_discard
));
555 static void *r600_create_sampler_state(struct pipe_context
*ctx
,
556 const struct pipe_sampler_state
*state
)
558 struct r600_pipe_sampler_state
*ss
= CALLOC_STRUCT(r600_pipe_sampler_state
);
559 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 4 : 0;
565 ss
->seamless_cube_map
= state
->seamless_cube_map
;
566 ss
->border_color_use
= sampler_state_needs_border_color(state
);
568 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
569 ss
->tex_sampler_words
[0] =
570 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
571 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
572 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
573 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
574 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
575 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
576 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
577 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
578 S_03C000_BORDER_COLOR_TYPE(ss
->border_color_use
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0);
579 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
580 ss
->tex_sampler_words
[1] =
581 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 6)) |
582 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 6)) |
583 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 6));
584 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
585 ss
->tex_sampler_words
[2] = S_03C008_TYPE(1);
587 if (ss
->border_color_use
) {
588 memcpy(&ss
->border_color
, &state
->border_color
, sizeof(state
->border_color
));
593 static struct pipe_sampler_view
*
594 texture_buffer_sampler_view(struct r600_pipe_sampler_view
*view
,
595 unsigned width0
, unsigned height0
)
598 struct pipe_context
*ctx
= view
->base
.context
;
599 struct r600_texture
*tmp
= (struct r600_texture
*)view
->base
.texture
;
601 int stride
= util_format_get_blocksize(view
->base
.format
);
602 unsigned format
, num_format
, format_comp
, endian
;
603 unsigned offset
= view
->base
.u
.buf
.first_element
* stride
;
604 unsigned size
= (view
->base
.u
.buf
.last_element
- view
->base
.u
.buf
.first_element
+ 1) * stride
;
606 r600_vertex_data_type(view
->base
.format
,
607 &format
, &num_format
, &format_comp
,
610 va
= r600_resource_va(ctx
->screen
, view
->base
.texture
) + offset
;
611 view
->tex_resource
= &tmp
->resource
;
613 view
->skip_mip_address_reloc
= true;
614 view
->tex_resource_words
[0] = va
;
615 view
->tex_resource_words
[1] = size
- 1;
616 view
->tex_resource_words
[2] = S_038008_BASE_ADDRESS_HI(va
>> 32UL) |
617 S_038008_STRIDE(stride
) |
618 S_038008_DATA_FORMAT(format
) |
619 S_038008_NUM_FORMAT_ALL(num_format
) |
620 S_038008_FORMAT_COMP_ALL(format_comp
) |
621 S_038008_ENDIAN_SWAP(endian
);
622 view
->tex_resource_words
[3] = 0;
624 * in theory dword 4 is for number of elements, for use with resinfo,
625 * but it seems to utterly fail to work, the amd gpu shader analyser
626 * uses a const buffer to store the element sizes for buffer txq
628 view
->tex_resource_words
[4] = 0;
629 view
->tex_resource_words
[5] = 0;
630 view
->tex_resource_words
[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER
);
634 struct pipe_sampler_view
*
635 r600_create_sampler_view_custom(struct pipe_context
*ctx
,
636 struct pipe_resource
*texture
,
637 const struct pipe_sampler_view
*state
,
638 unsigned width_first_level
, unsigned height_first_level
)
640 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
641 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
642 unsigned format
, endian
;
643 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
644 unsigned char swizzle
[4], array_mode
= 0;
645 unsigned width
, height
, depth
, offset_level
, last_level
;
650 /* initialize base object */
652 view
->base
.texture
= NULL
;
653 pipe_reference(NULL
, &texture
->reference
);
654 view
->base
.texture
= texture
;
655 view
->base
.reference
.count
= 1;
656 view
->base
.context
= ctx
;
658 if (texture
->target
== PIPE_BUFFER
)
659 return texture_buffer_sampler_view(view
, texture
->width0
, 1);
661 swizzle
[0] = state
->swizzle_r
;
662 swizzle
[1] = state
->swizzle_g
;
663 swizzle
[2] = state
->swizzle_b
;
664 swizzle
[3] = state
->swizzle_a
;
666 format
= r600_translate_texformat(ctx
->screen
, state
->format
,
668 &word4
, &yuv_format
);
669 assert(format
!= ~0);
675 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
&& !r600_can_read_depth(tmp
)) {
676 if (!r600_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
680 tmp
= tmp
->flushed_depth_texture
;
683 endian
= r600_colorformat_endian_swap(format
);
685 offset_level
= state
->u
.tex
.first_level
;
686 last_level
= state
->u
.tex
.last_level
- offset_level
;
687 width
= width_first_level
;
688 height
= height_first_level
;
689 depth
= u_minify(texture
->depth0
, offset_level
);
690 pitch
= tmp
->surface
.level
[offset_level
].nblk_x
* util_format_get_blockwidth(state
->format
);
692 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
694 depth
= texture
->array_size
;
695 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
696 depth
= texture
->array_size
;
697 } else if (texture
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
698 depth
= texture
->array_size
/ 6;
699 switch (tmp
->surface
.level
[offset_level
].mode
) {
700 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
701 array_mode
= V_038000_ARRAY_LINEAR_ALIGNED
;
703 case RADEON_SURF_MODE_1D
:
704 array_mode
= V_038000_ARRAY_1D_TILED_THIN1
;
706 case RADEON_SURF_MODE_2D
:
707 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
709 case RADEON_SURF_MODE_LINEAR
:
711 array_mode
= V_038000_ARRAY_LINEAR_GENERAL
;
715 view
->tex_resource
= &tmp
->resource
;
716 view
->tex_resource_words
[0] = (S_038000_DIM(r600_tex_dim(texture
->target
, texture
->nr_samples
)) |
717 S_038000_TILE_MODE(array_mode
) |
718 S_038000_TILE_TYPE(tmp
->non_disp_tiling
) |
719 S_038000_PITCH((pitch
/ 8) - 1) |
720 S_038000_TEX_WIDTH(width
- 1));
721 view
->tex_resource_words
[1] = (S_038004_TEX_HEIGHT(height
- 1) |
722 S_038004_TEX_DEPTH(depth
- 1) |
723 S_038004_DATA_FORMAT(format
));
724 view
->tex_resource_words
[2] = tmp
->surface
.level
[offset_level
].offset
>> 8;
725 if (offset_level
>= tmp
->surface
.last_level
) {
726 view
->tex_resource_words
[3] = tmp
->surface
.level
[offset_level
].offset
>> 8;
728 view
->tex_resource_words
[3] = tmp
->surface
.level
[offset_level
+ 1].offset
>> 8;
730 view
->tex_resource_words
[4] = (word4
|
731 S_038010_REQUEST_SIZE(1) |
732 S_038010_ENDIAN_SWAP(endian
) |
733 S_038010_BASE_LEVEL(0));
734 view
->tex_resource_words
[5] = (S_038014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
735 S_038014_LAST_ARRAY(state
->u
.tex
.last_layer
));
736 if (texture
->nr_samples
> 1) {
737 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
738 view
->tex_resource_words
[5] |= S_038014_LAST_LEVEL(util_logbase2(texture
->nr_samples
));
740 view
->tex_resource_words
[5] |= S_038014_LAST_LEVEL(last_level
);
742 view
->tex_resource_words
[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE
) |
743 S_038018_MAX_ANISO(4 /* max 16 samples */));
747 static struct pipe_sampler_view
*
748 r600_create_sampler_view(struct pipe_context
*ctx
,
749 struct pipe_resource
*tex
,
750 const struct pipe_sampler_view
*state
)
752 return r600_create_sampler_view_custom(ctx
, tex
, state
,
753 u_minify(tex
->width0
, state
->u
.tex
.first_level
),
754 u_minify(tex
->height0
, state
->u
.tex
.first_level
));
757 static void r600_emit_clip_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
759 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
760 struct pipe_clip_state
*state
= &rctx
->clip_state
.state
;
762 r600_write_context_reg_seq(cs
, R_028E20_PA_CL_UCP0_X
, 6*4);
763 radeon_emit_array(cs
, (unsigned*)state
, 6*4);
766 static void r600_set_polygon_stipple(struct pipe_context
*ctx
,
767 const struct pipe_poly_stipple
*state
)
771 static void r600_emit_scissor_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
773 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
774 struct r600_scissor_state
*rstate
= (struct r600_scissor_state
*)atom
;
775 struct pipe_scissor_state
*state
= &rstate
->scissor
;
776 unsigned offset
= rstate
->idx
* 4 * 2;
778 if (rctx
->b
.chip_class
!= R600
|| rctx
->scissor
[0].enable
) {
779 r600_write_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
+ offset
, 2);
780 radeon_emit(cs
, S_028240_TL_X(state
->minx
) | S_028240_TL_Y(state
->miny
) |
781 S_028240_WINDOW_OFFSET_DISABLE(1));
782 radeon_emit(cs
, S_028244_BR_X(state
->maxx
) | S_028244_BR_Y(state
->maxy
));
784 r600_write_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 2);
785 radeon_emit(cs
, S_028240_TL_X(0) | S_028240_TL_Y(0) |
786 S_028240_WINDOW_OFFSET_DISABLE(1));
787 radeon_emit(cs
, S_028244_BR_X(8192) | S_028244_BR_Y(8192));
791 static void r600_set_scissor_states(struct pipe_context
*ctx
,
793 unsigned num_scissors
,
794 const struct pipe_scissor_state
*state
)
796 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
799 for (i
= start_slot
; i
< start_slot
+ num_scissors
; i
++) {
800 rctx
->scissor
[i
].scissor
= state
[i
- start_slot
];
803 if (rctx
->b
.chip_class
== R600
&& !rctx
->scissor
[0].enable
)
806 for (i
= start_slot
; i
< start_slot
+ num_scissors
; i
++) {
807 rctx
->scissor
[i
].atom
.dirty
= true;
811 static struct r600_resource
*r600_buffer_create_helper(struct r600_screen
*rscreen
,
812 unsigned size
, unsigned alignment
)
814 struct pipe_resource buffer
;
816 memset(&buffer
, 0, sizeof buffer
);
817 buffer
.target
= PIPE_BUFFER
;
818 buffer
.format
= PIPE_FORMAT_R8_UNORM
;
819 buffer
.bind
= PIPE_BIND_CUSTOM
;
820 buffer
.usage
= PIPE_USAGE_DEFAULT
;
822 buffer
.width0
= size
;
825 buffer
.array_size
= 1;
827 return (struct r600_resource
*)
828 r600_buffer_create(&rscreen
->b
.b
, &buffer
, alignment
);
831 static void r600_init_color_surface(struct r600_context
*rctx
,
832 struct r600_surface
*surf
,
833 bool force_cmask_fmask
)
835 struct r600_screen
*rscreen
= rctx
->screen
;
836 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
837 unsigned level
= surf
->base
.u
.tex
.level
;
838 unsigned pitch
, slice
;
841 unsigned format
, swap
, ntype
, endian
;
843 const struct util_format_description
*desc
;
845 bool blend_bypass
= 0, blend_clamp
= 1;
847 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
&& !r600_can_read_depth(rtex
)) {
848 r600_init_flushed_depth_texture(&rctx
->b
.b
, surf
->base
.texture
, NULL
);
849 rtex
= rtex
->flushed_depth_texture
;
853 offset
= rtex
->surface
.level
[level
].offset
;
854 if (rtex
->surface
.level
[level
].mode
== RADEON_SURF_MODE_LINEAR
) {
855 assert(surf
->base
.u
.tex
.first_layer
== surf
->base
.u
.tex
.last_layer
);
856 offset
+= rtex
->surface
.level
[level
].slice_size
*
857 surf
->base
.u
.tex
.first_layer
;
860 color_view
= S_028080_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
861 S_028080_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
863 pitch
= rtex
->surface
.level
[level
].nblk_x
/ 8 - 1;
864 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
869 switch (rtex
->surface
.level
[level
].mode
) {
870 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
871 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED
);
873 case RADEON_SURF_MODE_1D
:
874 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1
);
876 case RADEON_SURF_MODE_2D
:
877 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1
);
879 case RADEON_SURF_MODE_LINEAR
:
881 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL
);
885 desc
= util_format_description(surf
->base
.format
);
887 for (i
= 0; i
< 4; i
++) {
888 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
893 ntype
= V_0280A0_NUMBER_UNORM
;
894 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
895 ntype
= V_0280A0_NUMBER_SRGB
;
896 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
897 if (desc
->channel
[i
].normalized
)
898 ntype
= V_0280A0_NUMBER_SNORM
;
899 else if (desc
->channel
[i
].pure_integer
)
900 ntype
= V_0280A0_NUMBER_SINT
;
901 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
902 if (desc
->channel
[i
].normalized
)
903 ntype
= V_0280A0_NUMBER_UNORM
;
904 else if (desc
->channel
[i
].pure_integer
)
905 ntype
= V_0280A0_NUMBER_UINT
;
908 format
= r600_translate_colorformat(rctx
->b
.chip_class
, surf
->base
.format
);
909 assert(format
!= ~0);
911 swap
= r600_translate_colorswap(surf
->base
.format
);
914 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
915 endian
= ENDIAN_NONE
;
917 endian
= r600_colorformat_endian_swap(format
);
920 /* set blend bypass according to docs if SINT/UINT or
921 8/24 COLOR variants */
922 if (ntype
== V_0280A0_NUMBER_UINT
|| ntype
== V_0280A0_NUMBER_SINT
||
923 format
== V_0280A0_COLOR_8_24
|| format
== V_0280A0_COLOR_24_8
||
924 format
== V_0280A0_COLOR_X24_8_32_FLOAT
) {
929 surf
->alphatest_bypass
= ntype
== V_0280A0_NUMBER_UINT
|| ntype
== V_0280A0_NUMBER_SINT
;
931 color_info
|= S_0280A0_FORMAT(format
) |
932 S_0280A0_COMP_SWAP(swap
) |
933 S_0280A0_BLEND_BYPASS(blend_bypass
) |
934 S_0280A0_BLEND_CLAMP(blend_clamp
) |
935 S_0280A0_NUMBER_TYPE(ntype
) |
936 S_0280A0_ENDIAN(endian
);
938 /* EXPORT_NORM is an optimzation that can be enabled for better
939 * performance in certain cases
941 if (rctx
->b
.chip_class
== R600
) {
942 /* EXPORT_NORM can be enabled if:
943 * - 11-bit or smaller UNORM/SNORM/SRGB
944 * - BLEND_CLAMP is enabled
945 * - BLEND_FLOAT32 is disabled
947 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
948 (desc
->channel
[i
].size
< 12 &&
949 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
950 ntype
!= V_0280A0_NUMBER_UINT
&&
951 ntype
!= V_0280A0_NUMBER_SINT
) &&
952 G_0280A0_BLEND_CLAMP(color_info
) &&
953 !G_0280A0_BLEND_FLOAT32(color_info
)) {
954 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
955 surf
->export_16bpc
= true;
958 /* EXPORT_NORM can be enabled if:
959 * - 11-bit or smaller UNORM/SNORM/SRGB
960 * - 16-bit or smaller FLOAT
962 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
963 ((desc
->channel
[i
].size
< 12 &&
964 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
965 ntype
!= V_0280A0_NUMBER_UINT
&& ntype
!= V_0280A0_NUMBER_SINT
) ||
966 (desc
->channel
[i
].size
< 17 &&
967 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
968 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
969 surf
->export_16bpc
= true;
973 /* These might not always be initialized to zero. */
974 surf
->cb_color_base
= offset
>> 8;
975 surf
->cb_color_size
= S_028060_PITCH_TILE_MAX(pitch
) |
976 S_028060_SLICE_TILE_MAX(slice
);
977 surf
->cb_color_fmask
= surf
->cb_color_base
;
978 surf
->cb_color_cmask
= surf
->cb_color_base
;
979 surf
->cb_color_mask
= 0;
981 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
,
982 &rtex
->resource
.b
.b
);
983 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
,
984 &rtex
->resource
.b
.b
);
986 if (rtex
->cmask
.size
) {
987 surf
->cb_color_cmask
= rtex
->cmask
.offset
>> 8;
988 surf
->cb_color_mask
|= S_028100_CMASK_BLOCK_MAX(rtex
->cmask
.slice_tile_max
);
990 if (rtex
->fmask
.size
) {
991 color_info
|= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE
);
992 surf
->cb_color_fmask
= rtex
->fmask
.offset
>> 8;
993 surf
->cb_color_mask
|= S_028100_FMASK_TILE_MAX(rtex
->fmask
.slice_tile_max
);
994 } else { /* cmask only */
995 color_info
|= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE
);
997 } else if (force_cmask_fmask
) {
998 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1000 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1001 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1002 * because it's not an MSAA buffer.
1004 struct r600_cmask_info cmask
;
1005 struct r600_fmask_info fmask
;
1007 r600_texture_get_cmask_info(&rscreen
->b
, rtex
, &cmask
);
1008 r600_texture_get_fmask_info(&rscreen
->b
, rtex
, 8, &fmask
);
1011 if (!rctx
->dummy_cmask
||
1012 rctx
->dummy_cmask
->buf
->size
< cmask
.size
||
1013 rctx
->dummy_cmask
->buf
->alignment
% cmask
.alignment
!= 0) {
1014 struct pipe_transfer
*transfer
;
1017 pipe_resource_reference((struct pipe_resource
**)&rctx
->dummy_cmask
, NULL
);
1018 rctx
->dummy_cmask
= r600_buffer_create_helper(rscreen
, cmask
.size
, cmask
.alignment
);
1020 /* Set the contents to 0xCC. */
1021 ptr
= pipe_buffer_map(&rctx
->b
.b
, &rctx
->dummy_cmask
->b
.b
, PIPE_TRANSFER_WRITE
, &transfer
);
1022 memset(ptr
, 0xCC, cmask
.size
);
1023 pipe_buffer_unmap(&rctx
->b
.b
, transfer
);
1025 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
,
1026 &rctx
->dummy_cmask
->b
.b
);
1029 if (!rctx
->dummy_fmask
||
1030 rctx
->dummy_fmask
->buf
->size
< fmask
.size
||
1031 rctx
->dummy_fmask
->buf
->alignment
% fmask
.alignment
!= 0) {
1032 pipe_resource_reference((struct pipe_resource
**)&rctx
->dummy_fmask
, NULL
);
1033 rctx
->dummy_fmask
= r600_buffer_create_helper(rscreen
, fmask
.size
, fmask
.alignment
);
1036 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
,
1037 &rctx
->dummy_fmask
->b
.b
);
1039 /* Init the registers. */
1040 color_info
|= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE
);
1041 surf
->cb_color_cmask
= 0;
1042 surf
->cb_color_fmask
= 0;
1043 surf
->cb_color_mask
= S_028100_CMASK_BLOCK_MAX(cmask
.slice_tile_max
) |
1044 S_028100_FMASK_TILE_MAX(fmask
.slice_tile_max
);
1047 surf
->cb_color_info
= color_info
;
1048 surf
->cb_color_view
= color_view
;
1049 surf
->color_initialized
= true;
1052 static void r600_init_depth_surface(struct r600_context
*rctx
,
1053 struct r600_surface
*surf
)
1055 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1056 unsigned level
, pitch
, slice
, format
, offset
, array_mode
;
1058 level
= surf
->base
.u
.tex
.level
;
1059 offset
= rtex
->surface
.level
[level
].offset
;
1060 pitch
= rtex
->surface
.level
[level
].nblk_x
/ 8 - 1;
1061 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1065 switch (rtex
->surface
.level
[level
].mode
) {
1066 case RADEON_SURF_MODE_2D
:
1067 array_mode
= V_0280A0_ARRAY_2D_TILED_THIN1
;
1069 case RADEON_SURF_MODE_1D
:
1070 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1071 case RADEON_SURF_MODE_LINEAR
:
1073 array_mode
= V_0280A0_ARRAY_1D_TILED_THIN1
;
1077 format
= r600_translate_dbformat(surf
->base
.format
);
1078 assert(format
!= ~0);
1080 surf
->db_depth_info
= S_028010_ARRAY_MODE(array_mode
) | S_028010_FORMAT(format
);
1081 surf
->db_depth_base
= offset
>> 8;
1082 surf
->db_depth_view
= S_028004_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1083 S_028004_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1084 surf
->db_depth_size
= S_028000_PITCH_TILE_MAX(pitch
) | S_028000_SLICE_TILE_MAX(slice
);
1085 surf
->db_prefetch_limit
= (rtex
->surface
.level
[level
].nblk_y
/ 8) - 1;
1087 switch (surf
->base
.format
) {
1088 case PIPE_FORMAT_Z24X8_UNORM
:
1089 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1090 surf
->pa_su_poly_offset_db_fmt_cntl
=
1091 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1093 case PIPE_FORMAT_Z32_FLOAT
:
1094 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1095 surf
->pa_su_poly_offset_db_fmt_cntl
=
1096 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1097 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1099 case PIPE_FORMAT_Z16_UNORM
:
1100 surf
->pa_su_poly_offset_db_fmt_cntl
=
1101 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1106 /* use htile only for first level */
1107 if (rtex
->htile_buffer
&& !level
) {
1108 uint64_t va
= r600_resource_va(&rctx
->screen
->b
.b
, &rtex
->htile_buffer
->b
.b
);
1109 surf
->db_htile_data_base
= va
>> 8;
1110 surf
->db_htile_surface
= S_028D24_HTILE_WIDTH(1) |
1111 S_028D24_HTILE_HEIGHT(1) |
1112 S_028D24_FULL_CACHE(1) |
1114 /* preload is not working properly on r6xx/r7xx */
1115 surf
->db_depth_info
|= S_028010_TILE_SURFACE_ENABLE(1);
1118 surf
->depth_initialized
= true;
1121 static void r600_set_framebuffer_state(struct pipe_context
*ctx
,
1122 const struct pipe_framebuffer_state
*state
)
1124 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1125 struct r600_surface
*surf
;
1126 struct r600_texture
*rtex
;
1129 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1130 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
1131 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_CB
|
1132 R600_CONTEXT_FLUSH_AND_INV_CB_META
;
1134 if (rctx
->framebuffer
.state
.zsbuf
) {
1135 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
1136 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_DB
;
1138 rtex
= (struct r600_texture
*)rctx
->framebuffer
.state
.zsbuf
->texture
;
1139 if (rctx
->b
.chip_class
>= R700
&& rtex
->htile_buffer
) {
1140 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_DB_META
;
1144 /* Set the new state. */
1145 util_copy_framebuffer_state(&rctx
->framebuffer
.state
, state
);
1147 rctx
->framebuffer
.export_16bpc
= state
->nr_cbufs
!= 0;
1148 rctx
->framebuffer
.cb0_is_integer
= state
->nr_cbufs
&& state
->cbufs
[0] &&
1149 util_format_is_pure_integer(state
->cbufs
[0]->format
);
1150 rctx
->framebuffer
.compressed_cb_mask
= 0;
1151 rctx
->framebuffer
.is_msaa_resolve
= state
->nr_cbufs
== 2 &&
1152 state
->cbufs
[0] && state
->cbufs
[1] &&
1153 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
1154 state
->cbufs
[1]->texture
->nr_samples
<= 1;
1155 rctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
1158 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
1159 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1160 bool force_cmask_fmask
= rctx
->b
.chip_class
== R600
&&
1161 rctx
->framebuffer
.is_msaa_resolve
&&
1164 surf
= (struct r600_surface
*)state
->cbufs
[i
];
1168 rtex
= (struct r600_texture
*)surf
->base
.texture
;
1169 r600_context_add_resource_size(ctx
, state
->cbufs
[i
]->texture
);
1171 if (!surf
->color_initialized
|| force_cmask_fmask
) {
1172 r600_init_color_surface(rctx
, surf
, force_cmask_fmask
);
1173 if (force_cmask_fmask
) {
1174 /* re-initialize later without compression */
1175 surf
->color_initialized
= false;
1179 if (!surf
->export_16bpc
) {
1180 rctx
->framebuffer
.export_16bpc
= false;
1183 if (rtex
->fmask
.size
&& rtex
->cmask
.size
) {
1184 rctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
1188 /* Update alpha-test state dependencies.
1189 * Alpha-test is done on the first colorbuffer only. */
1190 if (state
->nr_cbufs
) {
1191 bool alphatest_bypass
= false;
1193 surf
= (struct r600_surface
*)state
->cbufs
[0];
1195 alphatest_bypass
= surf
->alphatest_bypass
;
1198 if (rctx
->alphatest_state
.bypass
!= alphatest_bypass
) {
1199 rctx
->alphatest_state
.bypass
= alphatest_bypass
;
1200 rctx
->alphatest_state
.atom
.dirty
= true;
1206 surf
= (struct r600_surface
*)state
->zsbuf
;
1208 r600_context_add_resource_size(ctx
, state
->zsbuf
->texture
);
1210 if (!surf
->depth_initialized
) {
1211 r600_init_depth_surface(rctx
, surf
);
1214 if (state
->zsbuf
->format
!= rctx
->poly_offset_state
.zs_format
) {
1215 rctx
->poly_offset_state
.zs_format
= state
->zsbuf
->format
;
1216 rctx
->poly_offset_state
.atom
.dirty
= true;
1219 if (rctx
->db_state
.rsurf
!= surf
) {
1220 rctx
->db_state
.rsurf
= surf
;
1221 rctx
->db_state
.atom
.dirty
= true;
1222 rctx
->db_misc_state
.atom
.dirty
= true;
1224 } else if (rctx
->db_state
.rsurf
) {
1225 rctx
->db_state
.rsurf
= NULL
;
1226 rctx
->db_state
.atom
.dirty
= true;
1227 rctx
->db_misc_state
.atom
.dirty
= true;
1230 if (rctx
->cb_misc_state
.nr_cbufs
!= state
->nr_cbufs
) {
1231 rctx
->cb_misc_state
.nr_cbufs
= state
->nr_cbufs
;
1232 rctx
->cb_misc_state
.atom
.dirty
= true;
1235 if (state
->nr_cbufs
== 0 && rctx
->alphatest_state
.bypass
) {
1236 rctx
->alphatest_state
.bypass
= false;
1237 rctx
->alphatest_state
.atom
.dirty
= true;
1240 /* Calculate the CS size. */
1241 rctx
->framebuffer
.atom
.num_dw
=
1242 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1244 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1245 rctx
->framebuffer
.atom
.num_dw
+= 15 * rctx
->framebuffer
.state
.nr_cbufs
;
1246 rctx
->framebuffer
.atom
.num_dw
+= 3 * (2 + rctx
->framebuffer
.state
.nr_cbufs
);
1248 if (rctx
->framebuffer
.state
.zsbuf
) {
1249 rctx
->framebuffer
.atom
.num_dw
+= 16;
1250 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1251 rctx
->framebuffer
.atom
.num_dw
+= 3;
1253 if (rctx
->b
.family
> CHIP_R600
&& rctx
->b
.family
< CHIP_RV770
) {
1254 rctx
->framebuffer
.atom
.num_dw
+= 2;
1257 rctx
->framebuffer
.atom
.dirty
= true;
1260 static uint32_t sample_locs_2x
[] = {
1261 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1262 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1264 static unsigned max_dist_2x
= 4;
1266 static uint32_t sample_locs_4x
[] = {
1267 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1268 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1270 static unsigned max_dist_4x
= 6;
1271 static uint32_t sample_locs_8x
[] = {
1272 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1273 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1275 static unsigned max_dist_8x
= 7;
1277 static void r600_get_sample_position(struct pipe_context
*ctx
,
1278 unsigned sample_count
,
1279 unsigned sample_index
,
1286 switch (sample_count
) {
1289 out_value
[0] = out_value
[1] = 0.5;
1292 offset
= 4 * (sample_index
* 2);
1293 val
.idx
= (sample_locs_2x
[0] >> offset
) & 0xf;
1294 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1295 val
.idx
= (sample_locs_2x
[0] >> (offset
+ 4)) & 0xf;
1296 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1299 offset
= 4 * (sample_index
* 2);
1300 val
.idx
= (sample_locs_4x
[0] >> offset
) & 0xf;
1301 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1302 val
.idx
= (sample_locs_4x
[0] >> (offset
+ 4)) & 0xf;
1303 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1306 offset
= 4 * (sample_index
% 4 * 2);
1307 index
= (sample_index
/ 4);
1308 val
.idx
= (sample_locs_8x
[index
] >> offset
) & 0xf;
1309 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1310 val
.idx
= (sample_locs_8x
[index
] >> (offset
+ 4)) & 0xf;
1311 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1316 static void r600_emit_msaa_state(struct r600_context
*rctx
, int nr_samples
)
1318 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1319 unsigned max_dist
= 0;
1321 if (rctx
->b
.family
== CHIP_R600
) {
1322 switch (nr_samples
) {
1327 r600_write_config_reg(cs
, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S
, sample_locs_2x
[0]);
1328 max_dist
= max_dist_2x
;
1331 r600_write_config_reg(cs
, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S
, sample_locs_4x
[0]);
1332 max_dist
= max_dist_4x
;
1335 r600_write_config_reg_seq(cs
, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0
, 2);
1336 radeon_emit(cs
, sample_locs_8x
[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1337 radeon_emit(cs
, sample_locs_8x
[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1338 max_dist
= max_dist_8x
;
1342 switch (nr_samples
) {
1344 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1345 radeon_emit(cs
, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1346 radeon_emit(cs
, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1350 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1351 radeon_emit(cs
, sample_locs_2x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1352 radeon_emit(cs
, sample_locs_2x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1353 max_dist
= max_dist_2x
;
1356 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1357 radeon_emit(cs
, sample_locs_4x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1358 radeon_emit(cs
, sample_locs_4x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1359 max_dist
= max_dist_4x
;
1362 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1363 radeon_emit(cs
, sample_locs_8x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1364 radeon_emit(cs
, sample_locs_8x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1365 max_dist
= max_dist_8x
;
1370 if (nr_samples
> 1) {
1371 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1372 radeon_emit(cs
, S_028C00_LAST_PIXEL(1) |
1373 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1374 radeon_emit(cs
, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples
)) |
1375 S_028C04_MAX_SAMPLE_DIST(max_dist
)); /* R_028C04_PA_SC_AA_CONFIG */
1377 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1378 radeon_emit(cs
, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1379 radeon_emit(cs
, 0); /* R_028C04_PA_SC_AA_CONFIG */
1383 static void r600_emit_framebuffer_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1385 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1386 struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
.state
;
1387 unsigned nr_cbufs
= state
->nr_cbufs
;
1388 struct r600_surface
**cb
= (struct r600_surface
**)&state
->cbufs
[0];
1389 unsigned i
, sbu
= 0;
1392 r600_write_context_reg_seq(cs
, R_0280A0_CB_COLOR0_INFO
, 8);
1393 for (i
= 0; i
< nr_cbufs
; i
++) {
1394 radeon_emit(cs
, cb
[i
] ? cb
[i
]->cb_color_info
: 0);
1396 /* set CB_COLOR1_INFO for possible dual-src blending */
1397 if (i
== 1 && cb
[0]) {
1398 radeon_emit(cs
, cb
[0]->cb_color_info
);
1401 for (; i
< 8; i
++) {
1406 for (i
= 0; i
< nr_cbufs
; i
++) {
1413 r600_write_context_reg(cs
, R_028040_CB_COLOR0_BASE
+ i
*4, cb
[i
]->cb_color_base
);
1415 reloc
= r600_context_bo_reloc(&rctx
->b
,
1417 (struct r600_resource
*)cb
[i
]->base
.texture
,
1418 RADEON_USAGE_READWRITE
,
1419 cb
[i
]->base
.texture
->nr_samples
> 1 ?
1420 RADEON_PRIO_COLOR_BUFFER_MSAA
:
1421 RADEON_PRIO_COLOR_BUFFER
);
1422 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1423 radeon_emit(cs
, reloc
);
1426 r600_write_context_reg(cs
, R_0280E0_CB_COLOR0_FRAG
+ i
*4, cb
[i
]->cb_color_fmask
);
1428 reloc
= r600_context_bo_reloc(&rctx
->b
,
1430 cb
[i
]->cb_buffer_fmask
,
1431 RADEON_USAGE_READWRITE
,
1432 cb
[i
]->base
.texture
->nr_samples
> 1 ?
1433 RADEON_PRIO_COLOR_BUFFER_MSAA
:
1434 RADEON_PRIO_COLOR_BUFFER
);
1435 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1436 radeon_emit(cs
, reloc
);
1439 r600_write_context_reg(cs
, R_0280C0_CB_COLOR0_TILE
+ i
*4, cb
[i
]->cb_color_cmask
);
1441 reloc
= r600_context_bo_reloc(&rctx
->b
,
1443 cb
[i
]->cb_buffer_cmask
,
1444 RADEON_USAGE_READWRITE
,
1445 cb
[i
]->base
.texture
->nr_samples
> 1 ?
1446 RADEON_PRIO_COLOR_BUFFER_MSAA
:
1447 RADEON_PRIO_COLOR_BUFFER
);
1448 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1449 radeon_emit(cs
, reloc
);
1452 r600_write_context_reg_seq(cs
, R_028060_CB_COLOR0_SIZE
, nr_cbufs
);
1453 for (i
= 0; i
< nr_cbufs
; i
++) {
1454 radeon_emit(cs
, cb
[i
] ? cb
[i
]->cb_color_size
: 0);
1457 r600_write_context_reg_seq(cs
, R_028080_CB_COLOR0_VIEW
, nr_cbufs
);
1458 for (i
= 0; i
< nr_cbufs
; i
++) {
1459 radeon_emit(cs
, cb
[i
] ? cb
[i
]->cb_color_view
: 0);
1462 r600_write_context_reg_seq(cs
, R_028100_CB_COLOR0_MASK
, nr_cbufs
);
1463 for (i
= 0; i
< nr_cbufs
; i
++) {
1464 radeon_emit(cs
, cb
[i
] ? cb
[i
]->cb_color_mask
: 0);
1467 sbu
|= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs
);
1470 /* SURFACE_BASE_UPDATE */
1471 if (rctx
->b
.family
> CHIP_R600
&& rctx
->b
.family
< CHIP_RV770
&& sbu
) {
1472 radeon_emit(cs
, PKT3(PKT3_SURFACE_BASE_UPDATE
, 0, 0));
1473 radeon_emit(cs
, sbu
);
1479 struct r600_surface
*surf
= (struct r600_surface
*)state
->zsbuf
;
1480 unsigned reloc
= r600_context_bo_reloc(&rctx
->b
,
1482 (struct r600_resource
*)state
->zsbuf
->texture
,
1483 RADEON_USAGE_READWRITE
,
1484 surf
->base
.texture
->nr_samples
> 1 ?
1485 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
1486 RADEON_PRIO_DEPTH_BUFFER
);
1488 r600_write_context_reg(cs
, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1489 surf
->pa_su_poly_offset_db_fmt_cntl
);
1491 r600_write_context_reg_seq(cs
, R_028000_DB_DEPTH_SIZE
, 2);
1492 radeon_emit(cs
, surf
->db_depth_size
); /* R_028000_DB_DEPTH_SIZE */
1493 radeon_emit(cs
, surf
->db_depth_view
); /* R_028004_DB_DEPTH_VIEW */
1494 r600_write_context_reg_seq(cs
, R_02800C_DB_DEPTH_BASE
, 2);
1495 radeon_emit(cs
, surf
->db_depth_base
); /* R_02800C_DB_DEPTH_BASE */
1496 radeon_emit(cs
, surf
->db_depth_info
); /* R_028010_DB_DEPTH_INFO */
1498 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1499 radeon_emit(cs
, reloc
);
1501 r600_write_context_reg(cs
, R_028D34_DB_PREFETCH_LIMIT
, surf
->db_prefetch_limit
);
1503 sbu
|= SURFACE_BASE_UPDATE_DEPTH
;
1504 } else if (rctx
->screen
->b
.info
.drm_minor
>= 18) {
1505 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1506 * Older kernels are out of luck. */
1507 r600_write_context_reg(cs
, R_028010_DB_DEPTH_INFO
, S_028010_FORMAT(V_028010_DEPTH_INVALID
));
1510 /* SURFACE_BASE_UPDATE */
1511 if (rctx
->b
.family
> CHIP_R600
&& rctx
->b
.family
< CHIP_RV770
&& sbu
) {
1512 radeon_emit(cs
, PKT3(PKT3_SURFACE_BASE_UPDATE
, 0, 0));
1513 radeon_emit(cs
, sbu
);
1517 /* Framebuffer dimensions. */
1518 r600_write_context_reg_seq(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, 2);
1519 radeon_emit(cs
, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1520 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1521 radeon_emit(cs
, S_028244_BR_X(state
->width
) |
1522 S_028244_BR_Y(state
->height
)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1524 if (rctx
->framebuffer
.is_msaa_resolve
) {
1525 r600_write_context_reg(cs
, R_0287A0_CB_SHADER_CONTROL
, 1);
1527 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1528 * will assure that the alpha-test will work even if there is
1529 * no colorbuffer bound. */
1530 r600_write_context_reg(cs
, R_0287A0_CB_SHADER_CONTROL
,
1531 (1ull << MAX2(nr_cbufs
, 1)) - 1);
1534 r600_emit_msaa_state(rctx
, rctx
->framebuffer
.nr_samples
);
1537 static void r600_emit_cb_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1539 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1540 struct r600_cb_misc_state
*a
= (struct r600_cb_misc_state
*)atom
;
1542 if (G_028808_SPECIAL_OP(a
->cb_color_control
) == V_028808_SPECIAL_RESOLVE_BOX
) {
1543 r600_write_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1544 if (rctx
->b
.chip_class
== R600
) {
1545 radeon_emit(cs
, 0xff); /* R_028238_CB_TARGET_MASK */
1546 radeon_emit(cs
, 0xff); /* R_02823C_CB_SHADER_MASK */
1548 radeon_emit(cs
, 0xf); /* R_028238_CB_TARGET_MASK */
1549 radeon_emit(cs
, 0xf); /* R_02823C_CB_SHADER_MASK */
1551 r600_write_context_reg(cs
, R_028808_CB_COLOR_CONTROL
, a
->cb_color_control
);
1553 unsigned fb_colormask
= (1ULL << ((unsigned)a
->nr_cbufs
* 4)) - 1;
1554 unsigned ps_colormask
= (1ULL << ((unsigned)a
->nr_ps_color_outputs
* 4)) - 1;
1555 unsigned multiwrite
= a
->multiwrite
&& a
->nr_cbufs
> 1;
1557 r600_write_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1558 radeon_emit(cs
, a
->blend_colormask
& fb_colormask
); /* R_028238_CB_TARGET_MASK */
1559 /* Always enable the first color output to make sure alpha-test works even without one. */
1560 radeon_emit(cs
, 0xf | (multiwrite
? fb_colormask
: ps_colormask
)); /* R_02823C_CB_SHADER_MASK */
1561 r600_write_context_reg(cs
, R_028808_CB_COLOR_CONTROL
,
1562 a
->cb_color_control
|
1563 S_028808_MULTIWRITE_ENABLE(multiwrite
));
1567 static void r600_emit_db_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1569 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1570 struct r600_db_state
*a
= (struct r600_db_state
*)atom
;
1572 if (a
->rsurf
&& a
->rsurf
->db_htile_surface
) {
1573 struct r600_texture
*rtex
= (struct r600_texture
*)a
->rsurf
->base
.texture
;
1576 r600_write_context_reg(cs
, R_02802C_DB_DEPTH_CLEAR
, fui(rtex
->depth_clear_value
));
1577 r600_write_context_reg(cs
, R_028D24_DB_HTILE_SURFACE
, a
->rsurf
->db_htile_surface
);
1578 r600_write_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, a
->rsurf
->db_htile_data_base
);
1579 reloc_idx
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rtex
->htile_buffer
,
1580 RADEON_USAGE_READWRITE
, RADEON_PRIO_DEPTH_META
);
1581 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1582 cs
->buf
[cs
->cdw
++] = reloc_idx
;
1584 r600_write_context_reg(cs
, R_028D24_DB_HTILE_SURFACE
, 0);
1588 static void r600_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1590 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1591 struct r600_db_misc_state
*a
= (struct r600_db_misc_state
*)atom
;
1592 unsigned db_render_control
= 0;
1593 unsigned db_render_override
=
1594 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE
) |
1595 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE
);
1597 if (a
->occlusion_query_enabled
) {
1598 if (rctx
->b
.chip_class
>= R700
) {
1599 db_render_control
|= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1601 db_render_override
|= S_028D10_NOOP_CULL_DISABLE(1);
1603 if (rctx
->db_state
.rsurf
&& rctx
->db_state
.rsurf
->db_htile_surface
) {
1604 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1605 db_render_override
|= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF
);
1606 /* This is to fix a lockup when hyperz and alpha test are enabled at
1607 * the same time somehow GPU get confuse on which order to pick for
1610 if (rctx
->alphatest_state
.sx_alpha_test_control
) {
1611 db_render_override
|= S_028D10_FORCE_SHADER_Z_ORDER(1);
1614 db_render_override
|= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE
);
1616 if (a
->flush_depthstencil_through_cb
) {
1617 assert(a
->copy_depth
|| a
->copy_stencil
);
1619 db_render_control
|= S_028D0C_DEPTH_COPY_ENABLE(a
->copy_depth
) |
1620 S_028D0C_STENCIL_COPY_ENABLE(a
->copy_stencil
) |
1621 S_028D0C_COPY_CENTROID(1) |
1622 S_028D0C_COPY_SAMPLE(a
->copy_sample
);
1623 } else if (a
->flush_depthstencil_in_place
) {
1624 db_render_control
|= S_028D0C_DEPTH_COMPRESS_DISABLE(1) |
1625 S_028D0C_STENCIL_COMPRESS_DISABLE(1);
1626 db_render_override
|= S_028D10_NOOP_CULL_DISABLE(1);
1628 if (a
->htile_clear
) {
1629 db_render_control
|= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1632 /* RV770 workaround for a hang with 8x MSAA. */
1633 if (rctx
->b
.family
== CHIP_RV770
&& a
->log_samples
== 3) {
1634 db_render_override
|= S_028D10_MAX_TILES_IN_DTT(6);
1637 r600_write_context_reg_seq(cs
, R_028D0C_DB_RENDER_CONTROL
, 2);
1638 radeon_emit(cs
, db_render_control
); /* R_028D0C_DB_RENDER_CONTROL */
1639 radeon_emit(cs
, db_render_override
); /* R_028D10_DB_RENDER_OVERRIDE */
1640 r600_write_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
, a
->db_shader_control
);
1643 static void r600_emit_config_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1645 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1646 struct r600_config_state
*a
= (struct r600_config_state
*)atom
;
1648 r600_write_config_reg(cs
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, a
->sq_gpr_resource_mgmt_1
);
1649 r600_write_config_reg(cs
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, a
->sq_gpr_resource_mgmt_2
);
1652 static void r600_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1654 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1655 uint32_t dirty_mask
= rctx
->vertex_buffer_state
.dirty_mask
;
1657 while (dirty_mask
) {
1658 struct pipe_vertex_buffer
*vb
;
1659 struct r600_resource
*rbuffer
;
1661 unsigned buffer_index
= u_bit_scan(&dirty_mask
);
1663 vb
= &rctx
->vertex_buffer_state
.vb
[buffer_index
];
1664 rbuffer
= (struct r600_resource
*)vb
->buffer
;
1667 offset
= vb
->buffer_offset
;
1669 /* fetch resources start at index 320 */
1670 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1671 radeon_emit(cs
, (320 + buffer_index
) * 7);
1672 radeon_emit(cs
, offset
); /* RESOURCEi_WORD0 */
1673 radeon_emit(cs
, rbuffer
->buf
->size
- offset
- 1); /* RESOURCEi_WORD1 */
1674 radeon_emit(cs
, /* RESOURCEi_WORD2 */
1675 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1676 S_038008_STRIDE(vb
->stride
));
1677 radeon_emit(cs
, 0); /* RESOURCEi_WORD3 */
1678 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
1679 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
1680 radeon_emit(cs
, 0xc0000000); /* RESOURCEi_WORD6 */
1682 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1683 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
1684 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BUFFER_RO
));
1688 static void r600_emit_constant_buffers(struct r600_context
*rctx
,
1689 struct r600_constbuf_state
*state
,
1690 unsigned buffer_id_base
,
1691 unsigned reg_alu_constbuf_size
,
1692 unsigned reg_alu_const_cache
)
1694 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1695 uint32_t dirty_mask
= state
->dirty_mask
;
1697 while (dirty_mask
) {
1698 struct pipe_constant_buffer
*cb
;
1699 struct r600_resource
*rbuffer
;
1701 unsigned buffer_index
= ffs(dirty_mask
) - 1;
1702 unsigned gs_ring_buffer
= (buffer_index
== R600_GS_RING_CONST_BUFFER
);
1703 cb
= &state
->cb
[buffer_index
];
1704 rbuffer
= (struct r600_resource
*)cb
->buffer
;
1707 offset
= cb
->buffer_offset
;
1709 if (!gs_ring_buffer
) {
1710 r600_write_context_reg(cs
, reg_alu_constbuf_size
+ buffer_index
* 4,
1711 ALIGN_DIVUP(cb
->buffer_size
>> 4, 16));
1712 r600_write_context_reg(cs
, reg_alu_const_cache
+ buffer_index
* 4, offset
>> 8);
1715 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1716 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
1717 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BUFFER_RO
));
1719 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1720 radeon_emit(cs
, (buffer_id_base
+ buffer_index
) * 7);
1721 radeon_emit(cs
, offset
); /* RESOURCEi_WORD0 */
1722 radeon_emit(cs
, rbuffer
->buf
->size
- offset
- 1); /* RESOURCEi_WORD1 */
1723 radeon_emit(cs
, /* RESOURCEi_WORD2 */
1724 S_038008_ENDIAN_SWAP(gs_ring_buffer
? ENDIAN_NONE
: r600_endian_swap(32)) |
1725 S_038008_STRIDE(gs_ring_buffer
? 4 : 16));
1726 radeon_emit(cs
, 0); /* RESOURCEi_WORD3 */
1727 radeon_emit(cs
, 0); /* RESOURCEi_WORD4 */
1728 radeon_emit(cs
, 0); /* RESOURCEi_WORD5 */
1729 radeon_emit(cs
, 0xc0000000); /* RESOURCEi_WORD6 */
1731 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1732 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
1733 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BUFFER_RO
));
1735 dirty_mask
&= ~(1 << buffer_index
);
1737 state
->dirty_mask
= 0;
1740 static void r600_emit_vs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1742 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
], 160,
1743 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
1744 R_028980_ALU_CONST_CACHE_VS_0
);
1747 static void r600_emit_gs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1749 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
], 336,
1750 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
,
1751 R_0289C0_ALU_CONST_CACHE_GS_0
);
1754 static void r600_emit_ps_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1756 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
], 0,
1757 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
1758 R_028940_ALU_CONST_CACHE_PS_0
);
1761 static void r600_emit_sampler_views(struct r600_context
*rctx
,
1762 struct r600_samplerview_state
*state
,
1763 unsigned resource_id_base
)
1765 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1766 uint32_t dirty_mask
= state
->dirty_mask
;
1768 while (dirty_mask
) {
1769 struct r600_pipe_sampler_view
*rview
;
1770 unsigned resource_index
= u_bit_scan(&dirty_mask
);
1773 rview
= state
->views
[resource_index
];
1776 radeon_emit(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1777 radeon_emit(cs
, (resource_id_base
+ resource_index
) * 7);
1778 radeon_emit_array(cs
, rview
->tex_resource_words
, 7);
1780 reloc
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rview
->tex_resource
,
1782 rview
->tex_resource
->b
.b
.nr_samples
> 1 ?
1783 RADEON_PRIO_SHADER_TEXTURE_MSAA
:
1784 RADEON_PRIO_SHADER_TEXTURE_RO
);
1785 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1786 radeon_emit(cs
, reloc
);
1787 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1788 radeon_emit(cs
, reloc
);
1790 state
->dirty_mask
= 0;
1800 static void r600_emit_vs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
1802 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
, 160 + R600_MAX_CONST_BUFFERS
);
1805 static void r600_emit_gs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
1807 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
, 336 + R600_MAX_CONST_BUFFERS
);
1810 static void r600_emit_ps_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
1812 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
, R600_MAX_CONST_BUFFERS
);
1815 static void r600_emit_sampler_states(struct r600_context
*rctx
,
1816 struct r600_textures_info
*texinfo
,
1817 unsigned resource_id_base
,
1818 unsigned border_color_reg
)
1820 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1821 uint32_t dirty_mask
= texinfo
->states
.dirty_mask
;
1823 while (dirty_mask
) {
1824 struct r600_pipe_sampler_state
*rstate
;
1825 struct r600_pipe_sampler_view
*rview
;
1826 unsigned i
= u_bit_scan(&dirty_mask
);
1828 rstate
= texinfo
->states
.states
[i
];
1830 rview
= texinfo
->views
.views
[i
];
1832 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1833 * filtering between layers.
1834 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1837 enum pipe_texture_target target
= rview
->base
.texture
->target
;
1838 if (target
== PIPE_TEXTURE_1D_ARRAY
||
1839 target
== PIPE_TEXTURE_2D_ARRAY
) {
1840 rstate
->tex_sampler_words
[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1841 texinfo
->is_array_sampler
[i
] = true;
1843 rstate
->tex_sampler_words
[0] &= C_03C000_TEX_ARRAY_OVERRIDE
;
1844 texinfo
->is_array_sampler
[i
] = false;
1848 radeon_emit(cs
, PKT3(PKT3_SET_SAMPLER
, 3, 0));
1849 radeon_emit(cs
, (resource_id_base
+ i
) * 3);
1850 radeon_emit_array(cs
, rstate
->tex_sampler_words
, 3);
1852 if (rstate
->border_color_use
) {
1855 offset
= border_color_reg
;
1857 r600_write_config_reg_seq(cs
, offset
, 4);
1858 radeon_emit_array(cs
, rstate
->border_color
.ui
, 4);
1861 texinfo
->states
.dirty_mask
= 0;
1864 static void r600_emit_vs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
1866 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED
);
1869 static void r600_emit_gs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
1871 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED
);
1874 static void r600_emit_ps_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
1876 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED
);
1879 static void r600_emit_seamless_cube_map(struct r600_context
*rctx
, struct r600_atom
*atom
)
1881 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1884 tmp
= S_009508_DISABLE_CUBE_ANISO(1) |
1885 S_009508_SYNC_GRADIENT(1) |
1886 S_009508_SYNC_WALKER(1) |
1887 S_009508_SYNC_ALIGNER(1);
1888 if (!rctx
->seamless_cube_map
.enabled
) {
1889 tmp
|= S_009508_DISABLE_CUBE_WRAP(1);
1891 r600_write_config_reg(cs
, R_009508_TA_CNTL_AUX
, tmp
);
1894 static void r600_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
1896 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
1897 uint8_t mask
= s
->sample_mask
;
1899 r600_write_context_reg(rctx
->b
.rings
.gfx
.cs
, R_028C48_PA_SC_AA_MASK
,
1900 mask
| (mask
<< 8) | (mask
<< 16) | (mask
<< 24));
1903 static void r600_emit_vertex_fetch_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
1905 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1906 struct r600_cso_state
*state
= (struct r600_cso_state
*)a
;
1907 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
->cso
;
1909 r600_write_context_reg(cs
, R_028894_SQ_PGM_START_FS
, shader
->offset
>> 8);
1910 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1911 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, shader
->buffer
,
1912 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_DATA
));
1915 static void r600_emit_shader_stages(struct r600_context
*rctx
, struct r600_atom
*a
)
1917 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1918 struct r600_shader_stages_state
*state
= (struct r600_shader_stages_state
*)a
;
1920 uint32_t v2
= 0, primid
= 0;
1922 if (state
->geom_enable
) {
1925 if (rctx
->gs_shader
->current
->shader
.gs_max_out_vertices
<= 128)
1926 cut_val
= V_028A40_GS_CUT_128
;
1927 else if (rctx
->gs_shader
->current
->shader
.gs_max_out_vertices
<= 256)
1928 cut_val
= V_028A40_GS_CUT_256
;
1929 else if (rctx
->gs_shader
->current
->shader
.gs_max_out_vertices
<= 512)
1930 cut_val
= V_028A40_GS_CUT_512
;
1932 cut_val
= V_028A40_GS_CUT_1024
;
1934 v2
= S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
1935 S_028A40_CUT_MODE(cut_val
);
1937 if (rctx
->gs_shader
->current
->shader
.gs_prim_id_input
)
1941 r600_write_context_reg(cs
, R_028A40_VGT_GS_MODE
, v2
);
1942 r600_write_context_reg(cs
, R_028A84_VGT_PRIMITIVEID_EN
, primid
);
1945 static void r600_emit_gs_rings(struct r600_context
*rctx
, struct r600_atom
*a
)
1947 struct pipe_screen
*screen
= rctx
->b
.b
.screen
;
1948 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1949 struct r600_gs_rings_state
*state
= (struct r600_gs_rings_state
*)a
;
1950 struct r600_resource
*rbuffer
;
1952 r600_write_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
1953 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1954 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
1956 if (state
->enable
) {
1957 rbuffer
=(struct r600_resource
*)state
->esgs_ring
.buffer
;
1958 r600_write_config_reg(cs
, R_008C40_SQ_ESGS_RING_BASE
,
1959 (r600_resource_va(screen
, &rbuffer
->b
.b
)) >> 8);
1960 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1961 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
1962 RADEON_USAGE_READWRITE
,
1963 RADEON_PRIO_SHADER_RESOURCE_RW
));
1964 r600_write_config_reg(cs
, R_008C44_SQ_ESGS_RING_SIZE
,
1965 state
->esgs_ring
.buffer_size
>> 8);
1967 rbuffer
=(struct r600_resource
*)state
->gsvs_ring
.buffer
;
1968 r600_write_config_reg(cs
, R_008C48_SQ_GSVS_RING_BASE
,
1969 (r600_resource_va(screen
, &rbuffer
->b
.b
)) >> 8);
1970 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1971 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rbuffer
,
1972 RADEON_USAGE_READWRITE
,
1973 RADEON_PRIO_SHADER_RESOURCE_RW
));
1974 r600_write_config_reg(cs
, R_008C4C_SQ_GSVS_RING_SIZE
,
1975 state
->gsvs_ring
.buffer_size
>> 8);
1977 r600_write_config_reg(cs
, R_008C44_SQ_ESGS_RING_SIZE
, 0);
1978 r600_write_config_reg(cs
, R_008C4C_SQ_GSVS_RING_SIZE
, 0);
1981 r600_write_config_reg(cs
, R_008040_WAIT_UNTIL
, S_008040_WAIT_3D_IDLE(1));
1982 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1983 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH
));
1986 /* Adjust GPR allocation on R6xx/R7xx */
1987 bool r600_adjust_gprs(struct r600_context
*rctx
)
1989 unsigned num_ps_gprs
= rctx
->ps_shader
->current
->shader
.bc
.ngpr
;
1990 unsigned num_vs_gprs
, num_es_gprs
, num_gs_gprs
;
1991 unsigned new_num_ps_gprs
= num_ps_gprs
;
1992 unsigned new_num_vs_gprs
, new_num_es_gprs
, new_num_gs_gprs
;
1993 unsigned cur_num_ps_gprs
= G_008C04_NUM_PS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_1
);
1994 unsigned cur_num_vs_gprs
= G_008C04_NUM_VS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_1
);
1995 unsigned cur_num_gs_gprs
= G_008C08_NUM_GS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_2
);
1996 unsigned cur_num_es_gprs
= G_008C08_NUM_ES_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_2
);
1997 unsigned def_num_ps_gprs
= rctx
->default_ps_gprs
;
1998 unsigned def_num_vs_gprs
= rctx
->default_vs_gprs
;
1999 unsigned def_num_gs_gprs
= 0;
2000 unsigned def_num_es_gprs
= 0;
2001 unsigned def_num_clause_temp_gprs
= rctx
->r6xx_num_clause_temp_gprs
;
2002 /* hardware will reserve twice num_clause_temp_gprs */
2003 unsigned max_gprs
= def_num_gs_gprs
+ def_num_es_gprs
+ def_num_ps_gprs
+ def_num_vs_gprs
+ def_num_clause_temp_gprs
* 2;
2006 if (rctx
->gs_shader
) {
2007 num_es_gprs
= rctx
->vs_shader
->current
->shader
.bc
.ngpr
;
2008 num_gs_gprs
= rctx
->gs_shader
->current
->shader
.bc
.ngpr
;
2009 num_vs_gprs
= rctx
->gs_shader
->current
->gs_copy_shader
->shader
.bc
.ngpr
;
2013 num_vs_gprs
= rctx
->vs_shader
->current
->shader
.bc
.ngpr
;
2015 new_num_vs_gprs
= num_vs_gprs
;
2016 new_num_es_gprs
= num_es_gprs
;
2017 new_num_gs_gprs
= num_gs_gprs
;
2019 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2020 if (new_num_ps_gprs
> cur_num_ps_gprs
|| new_num_vs_gprs
> cur_num_vs_gprs
||
2021 new_num_es_gprs
> cur_num_es_gprs
|| new_num_gs_gprs
> cur_num_gs_gprs
) {
2022 /* try to use switch back to default */
2023 if (new_num_ps_gprs
> def_num_ps_gprs
|| new_num_vs_gprs
> def_num_vs_gprs
||
2024 new_num_gs_gprs
> def_num_gs_gprs
|| new_num_es_gprs
> def_num_es_gprs
) {
2025 /* always privilege vs stage so that at worst we have the
2026 * pixel stage producing wrong output (not the vertex
2028 new_num_ps_gprs
= max_gprs
- ((new_num_vs_gprs
- new_num_es_gprs
- new_num_gs_gprs
) + def_num_clause_temp_gprs
* 2);
2029 new_num_vs_gprs
= num_vs_gprs
;
2030 new_num_gs_gprs
= num_gs_gprs
;
2031 new_num_es_gprs
= num_es_gprs
;
2033 new_num_ps_gprs
= def_num_ps_gprs
;
2034 new_num_vs_gprs
= def_num_vs_gprs
;
2035 new_num_es_gprs
= def_num_es_gprs
;
2036 new_num_gs_gprs
= def_num_gs_gprs
;
2042 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2043 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2044 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2045 * it will lockup. So in this case just discard the draw command
2046 * and don't change the current gprs repartitions.
2048 if (num_ps_gprs
> new_num_ps_gprs
|| num_vs_gprs
> new_num_vs_gprs
||
2049 num_gs_gprs
> new_num_gs_gprs
|| num_es_gprs
> new_num_es_gprs
) {
2050 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2051 "for a combined maximum of %d\n",
2052 num_ps_gprs
, num_vs_gprs
, num_es_gprs
, num_gs_gprs
, max_gprs
);
2056 /* in some case we endup recomputing the current value */
2057 tmp
= S_008C04_NUM_PS_GPRS(new_num_ps_gprs
) |
2058 S_008C04_NUM_VS_GPRS(new_num_vs_gprs
) |
2059 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs
);
2061 tmp2
= S_008C08_NUM_ES_GPRS(new_num_es_gprs
) |
2062 S_008C08_NUM_GS_GPRS(new_num_gs_gprs
);
2063 if (rctx
->config_state
.sq_gpr_resource_mgmt_1
!= tmp
|| rctx
->config_state
.sq_gpr_resource_mgmt_2
!= tmp2
) {
2064 rctx
->config_state
.sq_gpr_resource_mgmt_1
= tmp
;
2065 rctx
->config_state
.sq_gpr_resource_mgmt_2
= tmp2
;
2066 rctx
->config_state
.atom
.dirty
= true;
2067 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
2072 void r600_init_atom_start_cs(struct r600_context
*rctx
)
2087 int num_ps_stack_entries
;
2088 int num_vs_stack_entries
;
2089 int num_gs_stack_entries
;
2090 int num_es_stack_entries
;
2091 enum radeon_family family
;
2092 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2095 r600_init_command_buffer(cb
, 256);
2097 /* R6xx requires this packet at the start of each command buffer */
2098 if (rctx
->b
.chip_class
== R600
) {
2099 r600_store_value(cb
, PKT3(PKT3_START_3D_CMDBUF
, 0, 0));
2100 r600_store_value(cb
, 0);
2102 /* All asics require this one */
2103 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2104 r600_store_value(cb
, 0x80000000);
2105 r600_store_value(cb
, 0x80000000);
2107 /* We're setting config registers here. */
2108 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2109 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2111 family
= rctx
->b
.family
;
2123 num_ps_threads
= 136;
2124 num_vs_threads
= 48;
2127 num_ps_stack_entries
= 128;
2128 num_vs_stack_entries
= 128;
2129 num_gs_stack_entries
= 0;
2130 num_es_stack_entries
= 0;
2139 num_ps_threads
= 144;
2140 num_vs_threads
= 40;
2143 num_ps_stack_entries
= 40;
2144 num_vs_stack_entries
= 40;
2145 num_gs_stack_entries
= 32;
2146 num_es_stack_entries
= 16;
2158 num_ps_threads
= 136;
2159 num_vs_threads
= 48;
2162 num_ps_stack_entries
= 40;
2163 num_vs_stack_entries
= 40;
2164 num_gs_stack_entries
= 32;
2165 num_es_stack_entries
= 16;
2173 num_ps_threads
= 136;
2174 num_vs_threads
= 48;
2177 num_ps_stack_entries
= 40;
2178 num_vs_stack_entries
= 40;
2179 num_gs_stack_entries
= 32;
2180 num_es_stack_entries
= 16;
2188 num_ps_threads
= 180;
2189 num_vs_threads
= 60;
2192 num_ps_stack_entries
= 128;
2193 num_vs_stack_entries
= 128;
2194 num_gs_stack_entries
= 128;
2195 num_es_stack_entries
= 128;
2204 num_ps_threads
= 180;
2205 num_vs_threads
= 60;
2208 num_ps_stack_entries
= 128;
2209 num_vs_stack_entries
= 128;
2210 num_gs_stack_entries
= 0;
2211 num_es_stack_entries
= 0;
2219 num_ps_threads
= 136;
2220 num_vs_threads
= 48;
2223 num_ps_stack_entries
= 128;
2224 num_vs_stack_entries
= 128;
2225 num_gs_stack_entries
= 0;
2226 num_es_stack_entries
= 0;
2230 rctx
->default_ps_gprs
= num_ps_gprs
;
2231 rctx
->default_vs_gprs
= num_vs_gprs
;
2232 rctx
->r6xx_num_clause_temp_gprs
= num_temp_gprs
;
2244 tmp
|= S_008C00_VC_ENABLE(1);
2247 tmp
|= S_008C00_DX9_CONSTS(0);
2248 tmp
|= S_008C00_ALU_INST_PREFER_VECTOR(1);
2249 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2250 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2251 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2252 tmp
|= S_008C00_ES_PRIO(es_prio
);
2253 r600_store_config_reg(cb
, R_008C00_SQ_CONFIG
, tmp
);
2255 /* SQ_GPR_RESOURCE_MGMT_2 */
2256 tmp
= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
2257 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
2258 r600_store_config_reg_seq(cb
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, 4);
2259 r600_store_value(cb
, tmp
);
2261 /* SQ_THREAD_RESOURCE_MGMT */
2262 tmp
= S_008C0C_NUM_PS_THREADS(num_ps_threads
);
2263 tmp
|= S_008C0C_NUM_VS_THREADS(num_vs_threads
);
2264 tmp
|= S_008C0C_NUM_GS_THREADS(num_gs_threads
);
2265 tmp
|= S_008C0C_NUM_ES_THREADS(num_es_threads
);
2266 r600_store_value(cb
, tmp
); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2268 /* SQ_STACK_RESOURCE_MGMT_1 */
2269 tmp
= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
2270 tmp
|= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
2271 r600_store_value(cb
, tmp
); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2273 /* SQ_STACK_RESOURCE_MGMT_2 */
2274 tmp
= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
2275 tmp
|= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
2276 r600_store_value(cb
, tmp
); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2278 r600_store_config_reg(cb
, R_009714_VC_ENHANCE
, 0);
2280 if (rctx
->b
.chip_class
>= R700
) {
2281 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0x00004000);
2282 r600_store_config_reg(cb
, R_009830_DB_DEBUG
, 0);
2283 r600_store_config_reg(cb
, R_009838_DB_WATERMARKS
, 0x00420204);
2284 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2286 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0);
2287 r600_store_config_reg(cb
, R_009830_DB_DEBUG
, 0x82000000);
2288 r600_store_config_reg(cb
, R_009838_DB_WATERMARKS
, 0x01020204);
2289 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 1);
2291 r600_store_context_reg_seq(cb
, R_0288A8_SQ_ESGS_RING_ITEMSIZE
, 9);
2292 r600_store_value(cb
, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2293 r600_store_value(cb
, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2294 r600_store_value(cb
, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2295 r600_store_value(cb
, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2296 r600_store_value(cb
, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2297 r600_store_value(cb
, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2298 r600_store_value(cb
, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2299 r600_store_value(cb
, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2300 r600_store_value(cb
, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2302 /* to avoid GPU doing any preloading of constant from random address */
2303 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 8);
2304 r600_store_value(cb
, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2305 r600_store_value(cb
, 0);
2306 r600_store_value(cb
, 0);
2307 r600_store_value(cb
, 0);
2308 r600_store_value(cb
, 0);
2309 r600_store_value(cb
, 0);
2310 r600_store_value(cb
, 0);
2311 r600_store_value(cb
, 0);
2312 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 8);
2313 r600_store_value(cb
, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2314 r600_store_value(cb
, 0);
2315 r600_store_value(cb
, 0);
2316 r600_store_value(cb
, 0);
2317 r600_store_value(cb
, 0);
2318 r600_store_value(cb
, 0);
2319 r600_store_value(cb
, 0);
2320 r600_store_value(cb
, 0);
2322 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2323 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2324 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2325 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2326 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2327 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2328 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2329 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2330 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2331 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2332 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2333 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2334 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2335 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE, 0); */
2337 r600_store_context_reg(cb
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
2338 r600_store_context_reg(cb
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 0);
2339 r600_store_context_reg(cb
, R_028AA4_VGT_INSTANCE_STEP_RATE_1
, 0);
2341 r600_store_context_reg_seq(cb
, R_028AB4_VGT_REUSE_OFF
, 2);
2342 r600_store_value(cb
, 1); /* R_028AB4_VGT_REUSE_OFF */
2343 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2345 r600_store_context_reg(cb
, R_028B20_VGT_STRMOUT_BUFFER_EN
, 0);
2347 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2349 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
2351 r600_store_context_reg_seq(cb
, R_0286DC_SPI_FOG_CNTL
, 3);
2352 r600_store_value(cb
, 0); /* R_0286DC_SPI_FOG_CNTL */
2353 r600_store_value(cb
, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2354 r600_store_value(cb
, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2356 r600_store_context_reg_seq(cb
, R_028D28_DB_SRESULTS_COMPARE_STATE0
, 3);
2357 r600_store_value(cb
, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2358 r600_store_value(cb
, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2359 r600_store_value(cb
, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2361 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2362 r600_store_context_reg(cb
, R_028A48_PA_SC_MPASS_PS_CNTL
, 0);
2364 r600_store_context_reg_seq(cb
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 4);
2365 r600_store_value(cb
, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2366 r600_store_value(cb
, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2367 r600_store_value(cb
, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2368 r600_store_value(cb
, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2370 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2 * 16);
2371 for (tmp
= 0; tmp
< 16; tmp
++) {
2372 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2373 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2376 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2377 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2379 if (rctx
->b
.chip_class
>= R700
) {
2380 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2383 r600_store_context_reg_seq(cb
, R_028C30_CB_CLRCMP_CONTROL
, 4);
2384 r600_store_value(cb
, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2385 r600_store_value(cb
, 0); /* R_028C34_CB_CLRCMP_SRC */
2386 r600_store_value(cb
, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2387 r600_store_value(cb
, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2389 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2390 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2391 r600_store_value(cb
, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2393 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2394 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2395 r600_store_value(cb
, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2397 r600_store_context_reg_seq(cb
, R_0288CC_SQ_PGM_CF_OFFSET_PS
, 5);
2398 r600_store_value(cb
, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2399 r600_store_value(cb
, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2400 r600_store_value(cb
, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2401 r600_store_value(cb
, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2402 r600_store_value(cb
, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2404 r600_store_context_reg(cb
, R_0288E0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
2406 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2407 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2408 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2410 r600_store_context_reg(cb
, R_0288A4_SQ_PGM_RESOURCES_FS
, 0);
2412 if (rctx
->b
.chip_class
== R700
)
2413 r600_store_context_reg(cb
, R_028350_SX_MISC
, 0);
2414 if (rctx
->b
.chip_class
== R700
&& rctx
->screen
->b
.has_streamout
)
2415 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
2417 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2418 if (rctx
->screen
->b
.has_streamout
) {
2419 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2422 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
, 0x1000FFF);
2423 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
+ (32 * 4), 0x1000FFF);
2424 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
+ (64 * 4), 0x1000FFF);
2427 void r600_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2429 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2430 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2431 struct r600_shader
*rshader
= &shader
->shader
;
2432 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
;
2433 int pos_index
= -1, face_index
= -1;
2434 unsigned tmp
, sid
, ufi
= 0;
2435 int need_linear
= 0;
2436 unsigned z_export
= 0, stencil_export
= 0;
2437 unsigned sprite_coord_enable
= rctx
->rasterizer
? rctx
->rasterizer
->sprite_coord_enable
: 0;
2440 r600_init_command_buffer(cb
, 64);
2445 r600_store_context_reg_seq(cb
, R_028644_SPI_PS_INPUT_CNTL_0
, rshader
->ninput
);
2446 for (i
= 0; i
< rshader
->ninput
; i
++) {
2447 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
2449 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
2452 sid
= rshader
->input
[i
].spi_sid
;
2454 tmp
= S_028644_SEMANTIC(sid
);
2456 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
2457 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2458 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
2459 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
))
2460 tmp
|= S_028644_FLAT_SHADE(1);
2462 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
2463 sprite_coord_enable
& (1 << rshader
->input
[i
].sid
)) {
2464 tmp
|= S_028644_PT_SPRITE_TEX(1);
2467 if (rshader
->input
[i
].centroid
)
2468 tmp
|= S_028644_SEL_CENTROID(1);
2470 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
) {
2472 tmp
|= S_028644_SEL_LINEAR(1);
2475 r600_store_value(cb
, tmp
);
2478 db_shader_control
= 0;
2479 for (i
= 0; i
< rshader
->noutput
; i
++) {
2480 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2482 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2485 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(z_export
);
2486 db_shader_control
|= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export
);
2487 if (rshader
->uses_kill
)
2488 db_shader_control
|= S_02880C_KILL_ENABLE(1);
2491 for (i
= 0; i
< rshader
->noutput
; i
++) {
2492 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
2493 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
) {
2497 num_cout
= rshader
->nr_ps_color_exports
;
2498 exports_ps
|= S_028854_EXPORT_COLORS(num_cout
);
2500 /* always at least export 1 component per pixel */
2504 shader
->nr_ps_color_outputs
= num_cout
;
2506 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(rshader
->ninput
) |
2507 S_0286CC_PERSP_GRADIENT_ENA(1)|
2508 S_0286CC_LINEAR_GRADIENT_ENA(need_linear
);
2510 if (pos_index
!= -1) {
2511 spi_ps_in_control_0
|= (S_0286CC_POSITION_ENA(1) |
2512 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
2513 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
) |
2514 S_0286CC_BARYC_SAMPLE_CNTL(1));
2515 spi_input_z
|= S_0286D8_PROVIDE_Z_TO_SPI(1);
2518 spi_ps_in_control_1
= 0;
2519 if (face_index
!= -1) {
2520 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
2521 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
2524 /* HW bug in original R600 */
2525 if (rctx
->b
.family
== CHIP_R600
)
2528 r600_store_context_reg_seq(cb
, R_0286CC_SPI_PS_IN_CONTROL_0
, 2);
2529 r600_store_value(cb
, spi_ps_in_control_0
); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2530 r600_store_value(cb
, spi_ps_in_control_1
); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2532 r600_store_context_reg(cb
, R_0286D8_SPI_INPUT_Z
, spi_input_z
);
2534 r600_store_context_reg_seq(cb
, R_028850_SQ_PGM_RESOURCES_PS
, 2);
2535 r600_store_value(cb
, /* R_028850_SQ_PGM_RESOURCES_PS*/
2536 S_028850_NUM_GPRS(rshader
->bc
.ngpr
) |
2537 S_028850_STACK_SIZE(rshader
->bc
.nstack
) |
2538 S_028850_UNCACHED_FIRST_INST(ufi
));
2539 r600_store_value(cb
, exports_ps
); /* R_028854_SQ_PGM_EXPORTS_PS */
2541 r600_store_context_reg(cb
, R_028840_SQ_PGM_START_PS
, 0);
2542 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2544 /* only set some bits here, the other bits are set in the dsa state */
2545 shader
->db_shader_control
= db_shader_control
;
2546 shader
->ps_depth_export
= z_export
| stencil_export
;
2548 shader
->sprite_coord_enable
= sprite_coord_enable
;
2549 if (rctx
->rasterizer
)
2550 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
2553 void r600_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2555 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2556 struct r600_shader
*rshader
= &shader
->shader
;
2557 unsigned spi_vs_out_id
[10] = {};
2558 unsigned i
, tmp
, nparams
= 0;
2560 for (i
= 0; i
< rshader
->noutput
; i
++) {
2561 if (rshader
->output
[i
].spi_sid
) {
2562 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
2563 spi_vs_out_id
[nparams
/ 4] |= tmp
;
2568 r600_init_command_buffer(cb
, 32);
2570 r600_store_context_reg_seq(cb
, R_028614_SPI_VS_OUT_ID_0
, 10);
2571 for (i
= 0; i
< 10; i
++) {
2572 r600_store_value(cb
, spi_vs_out_id
[i
]);
2575 /* Certain attributes (position, psize, etc.) don't count as params.
2576 * VS is required to export at least one param and r600_shader_from_tgsi()
2577 * takes care of adding a dummy export.
2582 r600_store_context_reg(cb
, R_0286C4_SPI_VS_OUT_CONFIG
,
2583 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
2584 r600_store_context_reg(cb
, R_028868_SQ_PGM_RESOURCES_VS
,
2585 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
2586 S_028868_STACK_SIZE(rshader
->bc
.nstack
));
2587 if (rshader
->vs_position_window_space
) {
2588 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
,
2589 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
2591 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
,
2592 S_028818_VTX_W0_FMT(1) |
2593 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2594 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2595 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2598 r600_store_context_reg(cb
, R_028858_SQ_PGM_START_VS
, 0);
2599 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2601 shader
->pa_cl_vs_out_cntl
=
2602 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
2603 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
2604 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
2605 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
) |
2606 S_02881C_USE_VTX_EDGE_FLAG(rshader
->vs_out_edgeflag
) |
2607 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader
->vs_out_layer
) |
2608 S_02881C_USE_VTX_VIEWPORT_INDX(rshader
->vs_out_viewport
);
2611 void r600_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2613 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2614 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2615 struct r600_shader
*rshader
= &shader
->shader
;
2616 struct r600_shader
*cp_shader
= &shader
->gs_copy_shader
->shader
;
2617 unsigned gsvs_itemsize
=
2618 (cp_shader
->ring_item_size
* rshader
->gs_max_out_vertices
) >> 2;
2620 r600_init_command_buffer(cb
, 64);
2622 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2623 r600_store_context_reg(cb
, R_028AB8_VGT_VTX_CNT_EN
, 1);
2625 if (rctx
->b
.chip_class
>= R700
) {
2626 r600_store_context_reg(cb
, R_028B38_VGT_GS_MAX_VERT_OUT
,
2627 S_028B38_MAX_VERT_OUT(rshader
->gs_max_out_vertices
));
2629 r600_store_context_reg(cb
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
,
2630 r600_conv_prim_to_gs_out(rshader
->gs_output_prim
));
2632 r600_store_context_reg_seq(cb
, R_0288C8_SQ_GS_VERT_ITEMSIZE
, 4);
2633 r600_store_value(cb
, cp_shader
->ring_item_size
>> 2);
2634 r600_store_value(cb
, 0);
2635 r600_store_value(cb
, 0);
2636 r600_store_value(cb
, 0);
2638 r600_store_context_reg(cb
, R_0288A8_SQ_ESGS_RING_ITEMSIZE
,
2639 (rshader
->ring_item_size
) >> 2);
2641 r600_store_context_reg(cb
, R_0288AC_SQ_GSVS_RING_ITEMSIZE
,
2644 /* FIXME calculate these values somehow ??? */
2645 r600_store_config_reg_seq(cb
, R_0088C8_VGT_GS_PER_ES
, 2);
2646 r600_store_value(cb
, 0x80); /* GS_PER_ES */
2647 r600_store_value(cb
, 0x100); /* ES_PER_GS */
2648 r600_store_config_reg_seq(cb
, R_0088E8_VGT_GS_PER_VS
, 1);
2649 r600_store_value(cb
, 0x2); /* GS_PER_VS */
2651 r600_store_context_reg(cb
, R_02887C_SQ_PGM_RESOURCES_GS
,
2652 S_02887C_NUM_GPRS(rshader
->bc
.ngpr
) |
2653 S_02887C_STACK_SIZE(rshader
->bc
.nstack
));
2654 r600_store_context_reg(cb
, R_02886C_SQ_PGM_START_GS
,
2655 r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8);
2656 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2659 void r600_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2661 struct r600_command_buffer
*cb
= &shader
->command_buffer
;
2662 struct r600_shader
*rshader
= &shader
->shader
;
2664 r600_init_command_buffer(cb
, 32);
2666 r600_store_context_reg(cb
, R_028890_SQ_PGM_RESOURCES_ES
,
2667 S_028890_NUM_GPRS(rshader
->bc
.ngpr
) |
2668 S_028890_STACK_SIZE(rshader
->bc
.nstack
));
2669 r600_store_context_reg(cb
, R_028880_SQ_PGM_START_ES
,
2670 r600_resource_va(ctx
->screen
, (void *)shader
->bo
) >> 8);
2671 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2675 void *r600_create_resolve_blend(struct r600_context
*rctx
)
2677 struct pipe_blend_state blend
;
2680 memset(&blend
, 0, sizeof(blend
));
2681 blend
.independent_blend_enable
= true;
2682 for (i
= 0; i
< 2; i
++) {
2683 blend
.rt
[i
].colormask
= 0xf;
2684 blend
.rt
[i
].blend_enable
= 1;
2685 blend
.rt
[i
].rgb_func
= PIPE_BLEND_ADD
;
2686 blend
.rt
[i
].alpha_func
= PIPE_BLEND_ADD
;
2687 blend
.rt
[i
].rgb_src_factor
= PIPE_BLENDFACTOR_ZERO
;
2688 blend
.rt
[i
].rgb_dst_factor
= PIPE_BLENDFACTOR_ZERO
;
2689 blend
.rt
[i
].alpha_src_factor
= PIPE_BLENDFACTOR_ZERO
;
2690 blend
.rt
[i
].alpha_dst_factor
= PIPE_BLENDFACTOR_ZERO
;
2692 return r600_create_blend_state_mode(&rctx
->b
.b
, &blend
, V_028808_SPECIAL_RESOLVE_BOX
);
2695 void *r700_create_resolve_blend(struct r600_context
*rctx
)
2697 struct pipe_blend_state blend
;
2699 memset(&blend
, 0, sizeof(blend
));
2700 blend
.independent_blend_enable
= true;
2701 blend
.rt
[0].colormask
= 0xf;
2702 return r600_create_blend_state_mode(&rctx
->b
.b
, &blend
, V_028808_SPECIAL_RESOLVE_BOX
);
2705 void *r600_create_decompress_blend(struct r600_context
*rctx
)
2707 struct pipe_blend_state blend
;
2709 memset(&blend
, 0, sizeof(blend
));
2710 blend
.independent_blend_enable
= true;
2711 blend
.rt
[0].colormask
= 0xf;
2712 return r600_create_blend_state_mode(&rctx
->b
.b
, &blend
, V_028808_SPECIAL_EXPAND_SAMPLES
);
2715 void *r600_create_db_flush_dsa(struct r600_context
*rctx
)
2717 struct pipe_depth_stencil_alpha_state dsa
;
2718 boolean quirk
= false;
2720 if (rctx
->b
.family
== CHIP_RV610
|| rctx
->b
.family
== CHIP_RV630
||
2721 rctx
->b
.family
== CHIP_RV620
|| rctx
->b
.family
== CHIP_RV635
)
2724 memset(&dsa
, 0, sizeof(dsa
));
2727 dsa
.depth
.enabled
= 1;
2728 dsa
.depth
.func
= PIPE_FUNC_LEQUAL
;
2729 dsa
.stencil
[0].enabled
= 1;
2730 dsa
.stencil
[0].func
= PIPE_FUNC_ALWAYS
;
2731 dsa
.stencil
[0].zpass_op
= PIPE_STENCIL_OP_KEEP
;
2732 dsa
.stencil
[0].zfail_op
= PIPE_STENCIL_OP_INCR
;
2733 dsa
.stencil
[0].writemask
= 0xff;
2736 return rctx
->b
.b
.create_depth_stencil_alpha_state(&rctx
->b
.b
, &dsa
);
2739 void r600_update_db_shader_control(struct r600_context
* rctx
)
2742 unsigned db_shader_control
;
2744 if (!rctx
->ps_shader
) {
2748 dual_export
= rctx
->framebuffer
.export_16bpc
&&
2749 !rctx
->ps_shader
->current
->ps_depth_export
;
2751 db_shader_control
= rctx
->ps_shader
->current
->db_shader_control
|
2752 S_02880C_DUAL_EXPORT_ENABLE(dual_export
);
2754 /* When alpha test is enabled we can't trust the hw to make the proper
2755 * decision on the order in which ztest should be run related to fragment
2758 * If alpha test is enabled perform z test after fragment. RE_Z (early
2759 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2761 if (rctx
->alphatest_state
.sx_alpha_test_control
) {
2762 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
2764 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2767 if (db_shader_control
!= rctx
->db_misc_state
.db_shader_control
) {
2768 rctx
->db_misc_state
.db_shader_control
= db_shader_control
;
2769 rctx
->db_misc_state
.atom
.dirty
= true;
2773 static INLINE
unsigned r600_array_mode(unsigned mode
)
2776 case RADEON_SURF_MODE_LINEAR_ALIGNED
: return V_0280A0_ARRAY_LINEAR_ALIGNED
;
2778 case RADEON_SURF_MODE_1D
: return V_0280A0_ARRAY_1D_TILED_THIN1
;
2780 case RADEON_SURF_MODE_2D
: return V_0280A0_ARRAY_2D_TILED_THIN1
;
2782 case RADEON_SURF_MODE_LINEAR
: return V_0280A0_ARRAY_LINEAR_GENERAL
;
2786 static boolean
r600_dma_copy_tile(struct r600_context
*rctx
,
2787 struct pipe_resource
*dst
,
2792 struct pipe_resource
*src
,
2797 unsigned copy_height
,
2801 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.dma
.cs
;
2802 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
2803 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
2804 unsigned array_mode
, lbpp
, pitch_tile_max
, slice_tile_max
, size
;
2805 unsigned ncopy
, height
, cheight
, detile
, i
, x
, y
, z
, src_mode
, dst_mode
;
2806 uint64_t base
, addr
;
2808 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
2809 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
2810 /* downcast linear aligned to linear to simplify test */
2811 src_mode
= src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: src_mode
;
2812 dst_mode
= dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: dst_mode
;
2813 assert(dst_mode
!= src_mode
);
2816 lbpp
= util_logbase2(bpp
);
2817 pitch_tile_max
= ((pitch
/ bpp
) / 8) - 1;
2819 if (dst_mode
== RADEON_SURF_MODE_LINEAR
) {
2821 array_mode
= r600_array_mode(src_mode
);
2822 slice_tile_max
= (rsrc
->surface
.level
[src_level
].nblk_x
* rsrc
->surface
.level
[src_level
].nblk_y
) / (8*8);
2823 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
2824 /* linear height must be the same as the slice tile max height, it's ok even
2825 * if the linear destination/source have smaller heigh as the size of the
2826 * dma packet will be using the copy_height which is always smaller or equal
2827 * to the linear height
2829 height
= rsrc
->surface
.level
[src_level
].npix_y
;
2834 base
= rsrc
->surface
.level
[src_level
].offset
;
2835 addr
= rdst
->surface
.level
[dst_level
].offset
;
2836 addr
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
2837 addr
+= dst_y
* pitch
+ dst_x
* bpp
;
2840 array_mode
= r600_array_mode(dst_mode
);
2841 slice_tile_max
= (rdst
->surface
.level
[dst_level
].nblk_x
* rdst
->surface
.level
[dst_level
].nblk_y
) / (8*8);
2842 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
2843 /* linear height must be the same as the slice tile max height, it's ok even
2844 * if the linear destination/source have smaller heigh as the size of the
2845 * dma packet will be using the copy_height which is always smaller or equal
2846 * to the linear height
2848 height
= rdst
->surface
.level
[dst_level
].npix_y
;
2853 base
= rdst
->surface
.level
[dst_level
].offset
;
2854 addr
= rsrc
->surface
.level
[src_level
].offset
;
2855 addr
+= rsrc
->surface
.level
[src_level
].slice_size
* src_z
;
2856 addr
+= src_y
* pitch
+ src_x
* bpp
;
2858 /* check that we are in dw/base alignment constraint */
2859 if (addr
% 4 || base
% 256) {
2863 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2864 * line in the blit. Compute max 8 line we can copy in the size limit
2866 cheight
= ((R600_DMA_COPY_MAX_SIZE_DW
* 4) / pitch
) & 0xfffffff8;
2867 ncopy
= (copy_height
/ cheight
) + !!(copy_height
% cheight
);
2868 r600_need_dma_space(&rctx
->b
, ncopy
* 7);
2870 for (i
= 0; i
< ncopy
; i
++) {
2871 cheight
= cheight
> copy_height
? copy_height
: cheight
;
2872 size
= (cheight
* pitch
) / 4;
2873 /* emit reloc before writting cs so that cs is always in consistent state */
2874 r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.dma
, &rsrc
->resource
, RADEON_USAGE_READ
,
2876 r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.dma
, &rdst
->resource
, RADEON_USAGE_WRITE
,
2878 cs
->buf
[cs
->cdw
++] = DMA_PACKET(DMA_PACKET_COPY
, 1, 0, size
);
2879 cs
->buf
[cs
->cdw
++] = base
>> 8;
2880 cs
->buf
[cs
->cdw
++] = (detile
<< 31) | (array_mode
<< 27) |
2881 (lbpp
<< 24) | ((height
- 1) << 10) |
2883 cs
->buf
[cs
->cdw
++] = (slice_tile_max
<< 12) | (z
<< 0);
2884 cs
->buf
[cs
->cdw
++] = (x
<< 3) | (y
<< 17);
2885 cs
->buf
[cs
->cdw
++] = addr
& 0xfffffffc;
2886 cs
->buf
[cs
->cdw
++] = (addr
>> 32UL) & 0xff;
2887 copy_height
-= cheight
;
2888 addr
+= cheight
* pitch
;
2894 static void r600_dma_copy(struct pipe_context
*ctx
,
2895 struct pipe_resource
*dst
,
2897 unsigned dstx
, unsigned dsty
, unsigned dstz
,
2898 struct pipe_resource
*src
,
2900 const struct pipe_box
*src_box
)
2902 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2903 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
2904 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
2905 unsigned dst_pitch
, src_pitch
, bpp
, dst_mode
, src_mode
, copy_height
;
2906 unsigned src_w
, dst_w
;
2907 unsigned src_x
, src_y
;
2908 unsigned dst_x
= dstx
, dst_y
= dsty
, dst_z
= dstz
;
2910 if (rctx
->b
.rings
.dma
.cs
== NULL
) {
2914 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
2915 if (dst_x
% 4 || src_box
->x
% 4 || src_box
->width
% 4)
2918 r600_dma_copy_buffer(rctx
, dst
, src
, dst_x
, src_box
->x
, src_box
->width
);
2922 if (src
->format
!= dst
->format
|| src_box
->depth
> 1) {
2926 src_x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
2927 dst_x
= util_format_get_nblocksx(src
->format
, dst_x
);
2928 src_y
= util_format_get_nblocksy(src
->format
, src_box
->y
);
2929 dst_y
= util_format_get_nblocksy(src
->format
, dst_y
);
2931 bpp
= rdst
->surface
.bpe
;
2932 dst_pitch
= rdst
->surface
.level
[dst_level
].pitch_bytes
;
2933 src_pitch
= rsrc
->surface
.level
[src_level
].pitch_bytes
;
2934 src_w
= rsrc
->surface
.level
[src_level
].npix_x
;
2935 dst_w
= rdst
->surface
.level
[dst_level
].npix_x
;
2936 copy_height
= src_box
->height
/ rsrc
->surface
.blk_h
;
2938 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
2939 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
2940 /* downcast linear aligned to linear to simplify test */
2941 src_mode
= src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: src_mode
;
2942 dst_mode
= dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: dst_mode
;
2944 if (src_pitch
!= dst_pitch
|| src_box
->x
|| dst_x
|| src_w
!= dst_w
) {
2945 /* strict requirement on r6xx/r7xx */
2948 /* lot of constraint on alignment this should capture them all */
2949 if (src_pitch
% 8 || src_box
->y
% 8 || dst_y
% 8) {
2953 if (src_mode
== dst_mode
) {
2954 uint64_t dst_offset
, src_offset
, size
;
2956 /* simple dma blit would do NOTE code here assume :
2959 * dst_pitch == src_pitch
2961 src_offset
= rsrc
->surface
.level
[src_level
].offset
;
2962 src_offset
+= rsrc
->surface
.level
[src_level
].slice_size
* src_box
->z
;
2963 src_offset
+= src_y
* src_pitch
+ src_x
* bpp
;
2964 dst_offset
= rdst
->surface
.level
[dst_level
].offset
;
2965 dst_offset
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
2966 dst_offset
+= dst_y
* dst_pitch
+ dst_x
* bpp
;
2967 size
= src_box
->height
* src_pitch
;
2968 /* must be dw aligned */
2969 if (dst_offset
% 4 || src_offset
% 4 || size
% 4) {
2972 r600_dma_copy_buffer(rctx
, dst
, src
, dst_offset
, src_offset
, size
);
2974 if (!r600_dma_copy_tile(rctx
, dst
, dst_level
, dst_x
, dst_y
, dst_z
,
2975 src
, src_level
, src_x
, src_y
, src_box
->z
,
2976 copy_height
, dst_pitch
, bpp
)) {
2983 ctx
->resource_copy_region(ctx
, dst
, dst_level
, dstx
, dsty
, dstz
,
2984 src
, src_level
, src_box
);
2987 void r600_init_state_functions(struct r600_context
*rctx
)
2993 * To avoid GPU lockup registers must be emited in a specific order
2994 * (no kidding ...). The order below is important and have been
2995 * partialy infered from analyzing fglrx command stream.
2997 * Don't reorder atom without carefully checking the effect (GPU lockup
2998 * or piglit regression).
3002 r600_init_atom(rctx
, &rctx
->framebuffer
.atom
, id
++, r600_emit_framebuffer_state
, 0);
3005 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
].atom
, id
++, r600_emit_vs_constant_buffers
, 0);
3006 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
].atom
, id
++, r600_emit_gs_constant_buffers
, 0);
3007 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
].atom
, id
++, r600_emit_ps_constant_buffers
, 0);
3009 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3010 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
3012 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].states
.atom
, id
++, r600_emit_vs_sampler_states
, 0);
3013 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].states
.atom
, id
++, r600_emit_gs_sampler_states
, 0);
3014 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].states
.atom
, id
++, r600_emit_ps_sampler_states
, 0);
3016 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
.atom
, id
++, r600_emit_vs_sampler_views
, 0);
3017 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
.atom
, id
++, r600_emit_gs_sampler_views
, 0);
3018 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.atom
, id
++, r600_emit_ps_sampler_views
, 0);
3019 r600_init_atom(rctx
, &rctx
->vertex_buffer_state
.atom
, id
++, r600_emit_vertex_buffers
, 0);
3021 r600_init_atom(rctx
, &rctx
->vgt_state
.atom
, id
++, r600_emit_vgt_state
, 7);
3023 r600_init_atom(rctx
, &rctx
->seamless_cube_map
.atom
, id
++, r600_emit_seamless_cube_map
, 3);
3024 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, r600_emit_sample_mask
, 3);
3025 rctx
->sample_mask
.sample_mask
= ~0;
3027 r600_init_atom(rctx
, &rctx
->alphatest_state
.atom
, id
++, r600_emit_alphatest_state
, 6);
3028 r600_init_atom(rctx
, &rctx
->blend_color
.atom
, id
++, r600_emit_blend_color
, 6);
3029 r600_init_atom(rctx
, &rctx
->blend_state
.atom
, id
++, r600_emit_cso_state
, 0);
3030 r600_init_atom(rctx
, &rctx
->cb_misc_state
.atom
, id
++, r600_emit_cb_misc_state
, 7);
3031 r600_init_atom(rctx
, &rctx
->clip_misc_state
.atom
, id
++, r600_emit_clip_misc_state
, 6);
3032 r600_init_atom(rctx
, &rctx
->clip_state
.atom
, id
++, r600_emit_clip_state
, 26);
3033 r600_init_atom(rctx
, &rctx
->db_misc_state
.atom
, id
++, r600_emit_db_misc_state
, 7);
3034 r600_init_atom(rctx
, &rctx
->db_state
.atom
, id
++, r600_emit_db_state
, 11);
3035 r600_init_atom(rctx
, &rctx
->dsa_state
.atom
, id
++, r600_emit_cso_state
, 0);
3036 r600_init_atom(rctx
, &rctx
->poly_offset_state
.atom
, id
++, r600_emit_polygon_offset
, 6);
3037 r600_init_atom(rctx
, &rctx
->rasterizer_state
.atom
, id
++, r600_emit_cso_state
, 0);
3038 for (i
= 0;i
< 16; i
++) {
3039 r600_init_atom(rctx
, &rctx
->scissor
[i
].atom
, id
++, r600_emit_scissor_state
, 4);
3040 r600_init_atom(rctx
, &rctx
->viewport
[i
].atom
, id
++, r600_emit_viewport_state
, 8);
3041 rctx
->scissor
[i
].idx
= i
;
3042 rctx
->viewport
[i
].idx
= i
;
3044 r600_init_atom(rctx
, &rctx
->config_state
.atom
, id
++, r600_emit_config_state
, 3);
3045 r600_init_atom(rctx
, &rctx
->stencil_ref
.atom
, id
++, r600_emit_stencil_ref
, 4);
3046 r600_init_atom(rctx
, &rctx
->vertex_fetch_shader
.atom
, id
++, r600_emit_vertex_fetch_shader
, 5);
3047 rctx
->atoms
[id
++] = &rctx
->b
.streamout
.begin_atom
;
3048 rctx
->atoms
[id
++] = &rctx
->b
.streamout
.enable_atom
;
3049 r600_init_atom(rctx
, &rctx
->vertex_shader
.atom
, id
++, r600_emit_shader
, 23);
3050 r600_init_atom(rctx
, &rctx
->pixel_shader
.atom
, id
++, r600_emit_shader
, 0);
3051 r600_init_atom(rctx
, &rctx
->geometry_shader
.atom
, id
++, r600_emit_shader
, 0);
3052 r600_init_atom(rctx
, &rctx
->export_shader
.atom
, id
++, r600_emit_shader
, 0);
3053 r600_init_atom(rctx
, &rctx
->shader_stages
.atom
, id
++, r600_emit_shader_stages
, 0);
3054 r600_init_atom(rctx
, &rctx
->gs_rings
.atom
, id
++, r600_emit_gs_rings
, 0);
3056 rctx
->b
.b
.create_blend_state
= r600_create_blend_state
;
3057 rctx
->b
.b
.create_depth_stencil_alpha_state
= r600_create_dsa_state
;
3058 rctx
->b
.b
.create_rasterizer_state
= r600_create_rs_state
;
3059 rctx
->b
.b
.create_sampler_state
= r600_create_sampler_state
;
3060 rctx
->b
.b
.create_sampler_view
= r600_create_sampler_view
;
3061 rctx
->b
.b
.set_framebuffer_state
= r600_set_framebuffer_state
;
3062 rctx
->b
.b
.set_polygon_stipple
= r600_set_polygon_stipple
;
3063 rctx
->b
.b
.set_scissor_states
= r600_set_scissor_states
;
3064 rctx
->b
.b
.get_sample_position
= r600_get_sample_position
;
3065 rctx
->b
.dma_copy
= r600_dma_copy
;
3067 /* this function must be last */