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r600g: do not require MSAA renderbuffer support if not asked for
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600d.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31
32 static uint32_t r600_translate_blend_function(int blend_func)
33 {
34 switch (blend_func) {
35 case PIPE_BLEND_ADD:
36 return V_028804_COMB_DST_PLUS_SRC;
37 case PIPE_BLEND_SUBTRACT:
38 return V_028804_COMB_SRC_MINUS_DST;
39 case PIPE_BLEND_REVERSE_SUBTRACT:
40 return V_028804_COMB_DST_MINUS_SRC;
41 case PIPE_BLEND_MIN:
42 return V_028804_COMB_MIN_DST_SRC;
43 case PIPE_BLEND_MAX:
44 return V_028804_COMB_MAX_DST_SRC;
45 default:
46 R600_ERR("Unknown blend function %d\n", blend_func);
47 assert(0);
48 break;
49 }
50 return 0;
51 }
52
53 static uint32_t r600_translate_blend_factor(int blend_fact)
54 {
55 switch (blend_fact) {
56 case PIPE_BLENDFACTOR_ONE:
57 return V_028804_BLEND_ONE;
58 case PIPE_BLENDFACTOR_SRC_COLOR:
59 return V_028804_BLEND_SRC_COLOR;
60 case PIPE_BLENDFACTOR_SRC_ALPHA:
61 return V_028804_BLEND_SRC_ALPHA;
62 case PIPE_BLENDFACTOR_DST_ALPHA:
63 return V_028804_BLEND_DST_ALPHA;
64 case PIPE_BLENDFACTOR_DST_COLOR:
65 return V_028804_BLEND_DST_COLOR;
66 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
67 return V_028804_BLEND_SRC_ALPHA_SATURATE;
68 case PIPE_BLENDFACTOR_CONST_COLOR:
69 return V_028804_BLEND_CONST_COLOR;
70 case PIPE_BLENDFACTOR_CONST_ALPHA:
71 return V_028804_BLEND_CONST_ALPHA;
72 case PIPE_BLENDFACTOR_ZERO:
73 return V_028804_BLEND_ZERO;
74 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
75 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
76 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
77 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
78 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
79 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
80 case PIPE_BLENDFACTOR_INV_DST_COLOR:
81 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
82 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
83 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
84 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
85 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
86 case PIPE_BLENDFACTOR_SRC1_COLOR:
87 return V_028804_BLEND_SRC1_COLOR;
88 case PIPE_BLENDFACTOR_SRC1_ALPHA:
89 return V_028804_BLEND_SRC1_ALPHA;
90 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
91 return V_028804_BLEND_INV_SRC1_COLOR;
92 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
93 return V_028804_BLEND_INV_SRC1_ALPHA;
94 default:
95 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
96 assert(0);
97 break;
98 }
99 return 0;
100 }
101
102 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
103 {
104 switch (dim) {
105 default:
106 case PIPE_TEXTURE_1D:
107 return V_038000_SQ_TEX_DIM_1D;
108 case PIPE_TEXTURE_1D_ARRAY:
109 return V_038000_SQ_TEX_DIM_1D_ARRAY;
110 case PIPE_TEXTURE_2D:
111 case PIPE_TEXTURE_RECT:
112 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
113 V_038000_SQ_TEX_DIM_2D;
114 case PIPE_TEXTURE_2D_ARRAY:
115 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
116 V_038000_SQ_TEX_DIM_2D_ARRAY;
117 case PIPE_TEXTURE_3D:
118 return V_038000_SQ_TEX_DIM_3D;
119 case PIPE_TEXTURE_CUBE:
120 return V_038000_SQ_TEX_DIM_CUBEMAP;
121 }
122 }
123
124 static uint32_t r600_translate_dbformat(enum pipe_format format)
125 {
126 switch (format) {
127 case PIPE_FORMAT_Z16_UNORM:
128 return V_028010_DEPTH_16;
129 case PIPE_FORMAT_Z24X8_UNORM:
130 return V_028010_DEPTH_X8_24;
131 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
132 return V_028010_DEPTH_8_24;
133 case PIPE_FORMAT_Z32_FLOAT:
134 return V_028010_DEPTH_32_FLOAT;
135 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
136 return V_028010_DEPTH_X24_8_32_FLOAT;
137 default:
138 return ~0U;
139 }
140 }
141
142 static uint32_t r600_translate_colorswap(enum pipe_format format)
143 {
144 switch (format) {
145 /* 8-bit buffers. */
146 case PIPE_FORMAT_A8_UNORM:
147 case PIPE_FORMAT_A8_SNORM:
148 case PIPE_FORMAT_A8_UINT:
149 case PIPE_FORMAT_A8_SINT:
150 case PIPE_FORMAT_A16_UNORM:
151 case PIPE_FORMAT_A16_SNORM:
152 case PIPE_FORMAT_A16_UINT:
153 case PIPE_FORMAT_A16_SINT:
154 case PIPE_FORMAT_A16_FLOAT:
155 case PIPE_FORMAT_A32_UINT:
156 case PIPE_FORMAT_A32_SINT:
157 case PIPE_FORMAT_A32_FLOAT:
158 case PIPE_FORMAT_R4A4_UNORM:
159 return V_0280A0_SWAP_ALT_REV;
160 case PIPE_FORMAT_I8_UNORM:
161 case PIPE_FORMAT_I8_SNORM:
162 case PIPE_FORMAT_I8_UINT:
163 case PIPE_FORMAT_I8_SINT:
164 case PIPE_FORMAT_L8_UNORM:
165 case PIPE_FORMAT_L8_SNORM:
166 case PIPE_FORMAT_L8_UINT:
167 case PIPE_FORMAT_L8_SINT:
168 case PIPE_FORMAT_L8_SRGB:
169 case PIPE_FORMAT_L16_UNORM:
170 case PIPE_FORMAT_L16_SNORM:
171 case PIPE_FORMAT_L16_UINT:
172 case PIPE_FORMAT_L16_SINT:
173 case PIPE_FORMAT_L16_FLOAT:
174 case PIPE_FORMAT_L32_UINT:
175 case PIPE_FORMAT_L32_SINT:
176 case PIPE_FORMAT_L32_FLOAT:
177 case PIPE_FORMAT_I16_UNORM:
178 case PIPE_FORMAT_I16_SNORM:
179 case PIPE_FORMAT_I16_UINT:
180 case PIPE_FORMAT_I16_SINT:
181 case PIPE_FORMAT_I16_FLOAT:
182 case PIPE_FORMAT_I32_UINT:
183 case PIPE_FORMAT_I32_SINT:
184 case PIPE_FORMAT_I32_FLOAT:
185 case PIPE_FORMAT_R8_UNORM:
186 case PIPE_FORMAT_R8_SNORM:
187 case PIPE_FORMAT_R8_UINT:
188 case PIPE_FORMAT_R8_SINT:
189 return V_0280A0_SWAP_STD;
190
191 case PIPE_FORMAT_L4A4_UNORM:
192 case PIPE_FORMAT_A4R4_UNORM:
193 return V_0280A0_SWAP_ALT;
194
195 /* 16-bit buffers. */
196 case PIPE_FORMAT_B5G6R5_UNORM:
197 return V_0280A0_SWAP_STD_REV;
198
199 case PIPE_FORMAT_B5G5R5A1_UNORM:
200 case PIPE_FORMAT_B5G5R5X1_UNORM:
201 return V_0280A0_SWAP_ALT;
202
203 case PIPE_FORMAT_B4G4R4A4_UNORM:
204 case PIPE_FORMAT_B4G4R4X4_UNORM:
205 return V_0280A0_SWAP_ALT;
206
207 case PIPE_FORMAT_Z16_UNORM:
208 return V_0280A0_SWAP_STD;
209
210 case PIPE_FORMAT_L8A8_UNORM:
211 case PIPE_FORMAT_L8A8_SNORM:
212 case PIPE_FORMAT_L8A8_UINT:
213 case PIPE_FORMAT_L8A8_SINT:
214 case PIPE_FORMAT_L8A8_SRGB:
215 case PIPE_FORMAT_L16A16_UNORM:
216 case PIPE_FORMAT_L16A16_SNORM:
217 case PIPE_FORMAT_L16A16_UINT:
218 case PIPE_FORMAT_L16A16_SINT:
219 case PIPE_FORMAT_L16A16_FLOAT:
220 case PIPE_FORMAT_L32A32_UINT:
221 case PIPE_FORMAT_L32A32_SINT:
222 case PIPE_FORMAT_L32A32_FLOAT:
223 return V_0280A0_SWAP_ALT;
224 case PIPE_FORMAT_R8G8_UNORM:
225 case PIPE_FORMAT_R8G8_SNORM:
226 case PIPE_FORMAT_R8G8_UINT:
227 case PIPE_FORMAT_R8G8_SINT:
228 return V_0280A0_SWAP_STD;
229
230 case PIPE_FORMAT_R16_UNORM:
231 case PIPE_FORMAT_R16_SNORM:
232 case PIPE_FORMAT_R16_UINT:
233 case PIPE_FORMAT_R16_SINT:
234 case PIPE_FORMAT_R16_FLOAT:
235 return V_0280A0_SWAP_STD;
236
237 /* 32-bit buffers. */
238
239 case PIPE_FORMAT_A8B8G8R8_SRGB:
240 return V_0280A0_SWAP_STD_REV;
241 case PIPE_FORMAT_B8G8R8A8_SRGB:
242 return V_0280A0_SWAP_ALT;
243
244 case PIPE_FORMAT_B8G8R8A8_UNORM:
245 case PIPE_FORMAT_B8G8R8X8_UNORM:
246 return V_0280A0_SWAP_ALT;
247
248 case PIPE_FORMAT_A8R8G8B8_UNORM:
249 case PIPE_FORMAT_X8R8G8B8_UNORM:
250 return V_0280A0_SWAP_ALT_REV;
251 case PIPE_FORMAT_R8G8B8A8_SNORM:
252 case PIPE_FORMAT_R8G8B8A8_UNORM:
253 case PIPE_FORMAT_R8G8B8X8_UNORM:
254 case PIPE_FORMAT_R8G8B8A8_SINT:
255 case PIPE_FORMAT_R8G8B8A8_UINT:
256 return V_0280A0_SWAP_STD;
257
258 case PIPE_FORMAT_A8B8G8R8_UNORM:
259 case PIPE_FORMAT_X8B8G8R8_UNORM:
260 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
261 return V_0280A0_SWAP_STD_REV;
262
263 case PIPE_FORMAT_Z24X8_UNORM:
264 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
265 return V_0280A0_SWAP_STD;
266
267 case PIPE_FORMAT_X8Z24_UNORM:
268 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
269 return V_0280A0_SWAP_STD;
270
271 case PIPE_FORMAT_R10G10B10A2_UNORM:
272 case PIPE_FORMAT_R10G10B10X2_SNORM:
273 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
274 return V_0280A0_SWAP_STD;
275
276 case PIPE_FORMAT_B10G10R10A2_UNORM:
277 case PIPE_FORMAT_B10G10R10A2_UINT:
278 return V_0280A0_SWAP_ALT;
279
280 case PIPE_FORMAT_R11G11B10_FLOAT:
281 case PIPE_FORMAT_R16G16_UNORM:
282 case PIPE_FORMAT_R16G16_SNORM:
283 case PIPE_FORMAT_R16G16_FLOAT:
284 case PIPE_FORMAT_R16G16_UINT:
285 case PIPE_FORMAT_R16G16_SINT:
286 case PIPE_FORMAT_R32_UINT:
287 case PIPE_FORMAT_R32_SINT:
288 case PIPE_FORMAT_R32_FLOAT:
289 case PIPE_FORMAT_Z32_FLOAT:
290 return V_0280A0_SWAP_STD;
291
292 /* 64-bit buffers. */
293 case PIPE_FORMAT_R32G32_FLOAT:
294 case PIPE_FORMAT_R32G32_UINT:
295 case PIPE_FORMAT_R32G32_SINT:
296 case PIPE_FORMAT_R16G16B16A16_UNORM:
297 case PIPE_FORMAT_R16G16B16A16_SNORM:
298 case PIPE_FORMAT_R16G16B16A16_UINT:
299 case PIPE_FORMAT_R16G16B16A16_SINT:
300 case PIPE_FORMAT_R16G16B16A16_FLOAT:
301 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
302
303 /* 128-bit buffers. */
304 case PIPE_FORMAT_R32G32B32A32_FLOAT:
305 case PIPE_FORMAT_R32G32B32A32_SNORM:
306 case PIPE_FORMAT_R32G32B32A32_UNORM:
307 case PIPE_FORMAT_R32G32B32A32_SINT:
308 case PIPE_FORMAT_R32G32B32A32_UINT:
309 return V_0280A0_SWAP_STD;
310 default:
311 R600_ERR("unsupported colorswap format %d\n", format);
312 return ~0U;
313 }
314 return ~0U;
315 }
316
317 static uint32_t r600_translate_colorformat(enum pipe_format format)
318 {
319 switch (format) {
320 case PIPE_FORMAT_L4A4_UNORM:
321 case PIPE_FORMAT_R4A4_UNORM:
322 case PIPE_FORMAT_A4R4_UNORM:
323 return V_0280A0_COLOR_4_4;
324
325 /* 8-bit buffers. */
326 case PIPE_FORMAT_A8_UNORM:
327 case PIPE_FORMAT_A8_SNORM:
328 case PIPE_FORMAT_A8_UINT:
329 case PIPE_FORMAT_A8_SINT:
330 case PIPE_FORMAT_I8_UNORM:
331 case PIPE_FORMAT_I8_SNORM:
332 case PIPE_FORMAT_I8_UINT:
333 case PIPE_FORMAT_I8_SINT:
334 case PIPE_FORMAT_L8_UNORM:
335 case PIPE_FORMAT_L8_SNORM:
336 case PIPE_FORMAT_L8_UINT:
337 case PIPE_FORMAT_L8_SINT:
338 case PIPE_FORMAT_L8_SRGB:
339 case PIPE_FORMAT_R8_UNORM:
340 case PIPE_FORMAT_R8_SNORM:
341 case PIPE_FORMAT_R8_UINT:
342 case PIPE_FORMAT_R8_SINT:
343 return V_0280A0_COLOR_8;
344
345 /* 16-bit buffers. */
346 case PIPE_FORMAT_B5G6R5_UNORM:
347 return V_0280A0_COLOR_5_6_5;
348
349 case PIPE_FORMAT_B5G5R5A1_UNORM:
350 case PIPE_FORMAT_B5G5R5X1_UNORM:
351 return V_0280A0_COLOR_1_5_5_5;
352
353 case PIPE_FORMAT_B4G4R4A4_UNORM:
354 case PIPE_FORMAT_B4G4R4X4_UNORM:
355 return V_0280A0_COLOR_4_4_4_4;
356
357 case PIPE_FORMAT_Z16_UNORM:
358 return V_0280A0_COLOR_16;
359
360 case PIPE_FORMAT_L8A8_UNORM:
361 case PIPE_FORMAT_L8A8_SNORM:
362 case PIPE_FORMAT_L8A8_UINT:
363 case PIPE_FORMAT_L8A8_SINT:
364 case PIPE_FORMAT_L8A8_SRGB:
365 case PIPE_FORMAT_R8G8_UNORM:
366 case PIPE_FORMAT_R8G8_SNORM:
367 case PIPE_FORMAT_R8G8_UINT:
368 case PIPE_FORMAT_R8G8_SINT:
369 return V_0280A0_COLOR_8_8;
370
371 case PIPE_FORMAT_R16_UNORM:
372 case PIPE_FORMAT_R16_SNORM:
373 case PIPE_FORMAT_R16_UINT:
374 case PIPE_FORMAT_R16_SINT:
375 case PIPE_FORMAT_A16_UNORM:
376 case PIPE_FORMAT_A16_SNORM:
377 case PIPE_FORMAT_A16_UINT:
378 case PIPE_FORMAT_A16_SINT:
379 case PIPE_FORMAT_L16_UNORM:
380 case PIPE_FORMAT_L16_SNORM:
381 case PIPE_FORMAT_L16_UINT:
382 case PIPE_FORMAT_L16_SINT:
383 case PIPE_FORMAT_I16_UNORM:
384 case PIPE_FORMAT_I16_SNORM:
385 case PIPE_FORMAT_I16_UINT:
386 case PIPE_FORMAT_I16_SINT:
387 return V_0280A0_COLOR_16;
388
389 case PIPE_FORMAT_R16_FLOAT:
390 case PIPE_FORMAT_A16_FLOAT:
391 case PIPE_FORMAT_L16_FLOAT:
392 case PIPE_FORMAT_I16_FLOAT:
393 return V_0280A0_COLOR_16_FLOAT;
394
395 /* 32-bit buffers. */
396 case PIPE_FORMAT_A8B8G8R8_SRGB:
397 case PIPE_FORMAT_A8B8G8R8_UNORM:
398 case PIPE_FORMAT_A8R8G8B8_UNORM:
399 case PIPE_FORMAT_B8G8R8A8_SRGB:
400 case PIPE_FORMAT_B8G8R8A8_UNORM:
401 case PIPE_FORMAT_B8G8R8X8_UNORM:
402 case PIPE_FORMAT_R8G8B8A8_SNORM:
403 case PIPE_FORMAT_R8G8B8A8_UNORM:
404 case PIPE_FORMAT_R8G8B8X8_UNORM:
405 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
406 case PIPE_FORMAT_X8B8G8R8_UNORM:
407 case PIPE_FORMAT_X8R8G8B8_UNORM:
408 case PIPE_FORMAT_R8G8B8A8_SINT:
409 case PIPE_FORMAT_R8G8B8A8_UINT:
410 return V_0280A0_COLOR_8_8_8_8;
411
412 case PIPE_FORMAT_R10G10B10A2_UNORM:
413 case PIPE_FORMAT_R10G10B10X2_SNORM:
414 case PIPE_FORMAT_B10G10R10A2_UNORM:
415 case PIPE_FORMAT_B10G10R10A2_UINT:
416 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
417 return V_0280A0_COLOR_2_10_10_10;
418
419 case PIPE_FORMAT_Z24X8_UNORM:
420 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
421 return V_0280A0_COLOR_8_24;
422
423 case PIPE_FORMAT_X8Z24_UNORM:
424 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
425 return V_0280A0_COLOR_24_8;
426
427 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
428 return V_0280A0_COLOR_X24_8_32_FLOAT;
429
430 case PIPE_FORMAT_R32_UINT:
431 case PIPE_FORMAT_R32_SINT:
432 case PIPE_FORMAT_A32_UINT:
433 case PIPE_FORMAT_A32_SINT:
434 case PIPE_FORMAT_L32_UINT:
435 case PIPE_FORMAT_L32_SINT:
436 case PIPE_FORMAT_I32_UINT:
437 case PIPE_FORMAT_I32_SINT:
438 return V_0280A0_COLOR_32;
439
440 case PIPE_FORMAT_R32_FLOAT:
441 case PIPE_FORMAT_A32_FLOAT:
442 case PIPE_FORMAT_L32_FLOAT:
443 case PIPE_FORMAT_I32_FLOAT:
444 case PIPE_FORMAT_Z32_FLOAT:
445 return V_0280A0_COLOR_32_FLOAT;
446
447 case PIPE_FORMAT_R16G16_FLOAT:
448 case PIPE_FORMAT_L16A16_FLOAT:
449 return V_0280A0_COLOR_16_16_FLOAT;
450
451 case PIPE_FORMAT_R16G16_UNORM:
452 case PIPE_FORMAT_R16G16_SNORM:
453 case PIPE_FORMAT_R16G16_UINT:
454 case PIPE_FORMAT_R16G16_SINT:
455 case PIPE_FORMAT_L16A16_UNORM:
456 case PIPE_FORMAT_L16A16_SNORM:
457 case PIPE_FORMAT_L16A16_UINT:
458 case PIPE_FORMAT_L16A16_SINT:
459 return V_0280A0_COLOR_16_16;
460
461 case PIPE_FORMAT_R11G11B10_FLOAT:
462 return V_0280A0_COLOR_10_11_11_FLOAT;
463
464 /* 64-bit buffers. */
465 case PIPE_FORMAT_R16G16B16A16_UINT:
466 case PIPE_FORMAT_R16G16B16A16_SINT:
467 case PIPE_FORMAT_R16G16B16A16_UNORM:
468 case PIPE_FORMAT_R16G16B16A16_SNORM:
469 return V_0280A0_COLOR_16_16_16_16;
470
471 case PIPE_FORMAT_R16G16B16A16_FLOAT:
472 return V_0280A0_COLOR_16_16_16_16_FLOAT;
473
474 case PIPE_FORMAT_R32G32_FLOAT:
475 case PIPE_FORMAT_L32A32_FLOAT:
476 return V_0280A0_COLOR_32_32_FLOAT;
477
478 case PIPE_FORMAT_R32G32_SINT:
479 case PIPE_FORMAT_R32G32_UINT:
480 case PIPE_FORMAT_L32A32_UINT:
481 case PIPE_FORMAT_L32A32_SINT:
482 return V_0280A0_COLOR_32_32;
483
484 /* 128-bit buffers. */
485 case PIPE_FORMAT_R32G32B32A32_FLOAT:
486 return V_0280A0_COLOR_32_32_32_32_FLOAT;
487 case PIPE_FORMAT_R32G32B32A32_SNORM:
488 case PIPE_FORMAT_R32G32B32A32_UNORM:
489 case PIPE_FORMAT_R32G32B32A32_SINT:
490 case PIPE_FORMAT_R32G32B32A32_UINT:
491 return V_0280A0_COLOR_32_32_32_32;
492
493 /* YUV buffers. */
494 case PIPE_FORMAT_UYVY:
495 case PIPE_FORMAT_YUYV:
496 default:
497 return ~0U; /* Unsupported. */
498 }
499 }
500
501 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
502 {
503 if (R600_BIG_ENDIAN) {
504 switch(colorformat) {
505 case V_0280A0_COLOR_4_4:
506 return ENDIAN_NONE;
507
508 /* 8-bit buffers. */
509 case V_0280A0_COLOR_8:
510 return ENDIAN_NONE;
511
512 /* 16-bit buffers. */
513 case V_0280A0_COLOR_5_6_5:
514 case V_0280A0_COLOR_1_5_5_5:
515 case V_0280A0_COLOR_4_4_4_4:
516 case V_0280A0_COLOR_16:
517 case V_0280A0_COLOR_8_8:
518 return ENDIAN_8IN16;
519
520 /* 32-bit buffers. */
521 case V_0280A0_COLOR_8_8_8_8:
522 case V_0280A0_COLOR_2_10_10_10:
523 case V_0280A0_COLOR_8_24:
524 case V_0280A0_COLOR_24_8:
525 case V_0280A0_COLOR_32_FLOAT:
526 case V_0280A0_COLOR_16_16_FLOAT:
527 case V_0280A0_COLOR_16_16:
528 return ENDIAN_8IN32;
529
530 /* 64-bit buffers. */
531 case V_0280A0_COLOR_16_16_16_16:
532 case V_0280A0_COLOR_16_16_16_16_FLOAT:
533 return ENDIAN_8IN16;
534
535 case V_0280A0_COLOR_32_32_FLOAT:
536 case V_0280A0_COLOR_32_32:
537 case V_0280A0_COLOR_X24_8_32_FLOAT:
538 return ENDIAN_8IN32;
539
540 /* 128-bit buffers. */
541 case V_0280A0_COLOR_32_32_32_FLOAT:
542 case V_0280A0_COLOR_32_32_32_32_FLOAT:
543 case V_0280A0_COLOR_32_32_32_32:
544 return ENDIAN_8IN32;
545 default:
546 return ENDIAN_NONE; /* Unsupported. */
547 }
548 } else {
549 return ENDIAN_NONE;
550 }
551 }
552
553 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
554 {
555 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
556 }
557
558 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
559 {
560 return r600_translate_colorformat(format) != ~0U &&
561 r600_translate_colorswap(format) != ~0U;
562 }
563
564 static bool r600_is_zs_format_supported(enum pipe_format format)
565 {
566 return r600_translate_dbformat(format) != ~0U;
567 }
568
569 boolean r600_is_format_supported(struct pipe_screen *screen,
570 enum pipe_format format,
571 enum pipe_texture_target target,
572 unsigned sample_count,
573 unsigned usage)
574 {
575 struct r600_screen *rscreen = (struct r600_screen*)screen;
576 unsigned retval = 0;
577
578 if (target >= PIPE_MAX_TEXTURE_TYPES) {
579 R600_ERR("r600: unsupported texture type %d\n", target);
580 return FALSE;
581 }
582
583 if (!util_format_is_supported(format, usage))
584 return FALSE;
585
586 if (sample_count > 1) {
587 if (rscreen->info.drm_minor < 22)
588 return FALSE;
589
590 /* R11G11B10 is broken on R6xx. */
591 if (rscreen->chip_class == R600 &&
592 format == PIPE_FORMAT_R11G11B10_FLOAT)
593 return FALSE;
594
595 /* MSAA integer colorbuffers hang. */
596 if (util_format_is_pure_integer(format))
597 return FALSE;
598
599 switch (sample_count) {
600 case 2:
601 case 4:
602 case 8:
603 break;
604 default:
605 return FALSE;
606 }
607 }
608
609 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
610 r600_is_sampler_format_supported(screen, format)) {
611 retval |= PIPE_BIND_SAMPLER_VIEW;
612 }
613
614 if ((usage & (PIPE_BIND_RENDER_TARGET |
615 PIPE_BIND_DISPLAY_TARGET |
616 PIPE_BIND_SCANOUT |
617 PIPE_BIND_SHARED)) &&
618 r600_is_colorbuffer_format_supported(format)) {
619 retval |= usage &
620 (PIPE_BIND_RENDER_TARGET |
621 PIPE_BIND_DISPLAY_TARGET |
622 PIPE_BIND_SCANOUT |
623 PIPE_BIND_SHARED);
624 }
625
626 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
627 r600_is_zs_format_supported(format)) {
628 retval |= PIPE_BIND_DEPTH_STENCIL;
629 }
630
631 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
632 r600_is_vertex_format_supported(format)) {
633 retval |= PIPE_BIND_VERTEX_BUFFER;
634 }
635
636 if (usage & PIPE_BIND_TRANSFER_READ)
637 retval |= PIPE_BIND_TRANSFER_READ;
638 if (usage & PIPE_BIND_TRANSFER_WRITE)
639 retval |= PIPE_BIND_TRANSFER_WRITE;
640
641 return retval == usage;
642 }
643
644 void r600_polygon_offset_update(struct r600_context *rctx)
645 {
646 struct r600_pipe_state state;
647
648 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
649 state.nregs = 0;
650 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
651 float offset_units = rctx->rasterizer->offset_units;
652 unsigned offset_db_fmt_cntl = 0, depth;
653
654 switch (rctx->framebuffer.zsbuf->format) {
655 case PIPE_FORMAT_Z24X8_UNORM:
656 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
657 depth = -24;
658 offset_units *= 2.0f;
659 break;
660 case PIPE_FORMAT_Z32_FLOAT:
661 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
662 depth = -23;
663 offset_units *= 1.0f;
664 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
665 break;
666 case PIPE_FORMAT_Z16_UNORM:
667 depth = -16;
668 offset_units *= 4.0f;
669 break;
670 default:
671 return;
672 }
673 /* XXX some of those reg can be computed with cso */
674 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
675 r600_pipe_state_add_reg(&state,
676 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
677 fui(rctx->rasterizer->offset_scale));
678 r600_pipe_state_add_reg(&state,
679 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
680 fui(offset_units));
681 r600_pipe_state_add_reg(&state,
682 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
683 fui(rctx->rasterizer->offset_scale));
684 r600_pipe_state_add_reg(&state,
685 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
686 fui(offset_units));
687 r600_pipe_state_add_reg(&state,
688 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
689 offset_db_fmt_cntl);
690 r600_context_pipe_state_set(rctx, &state);
691 }
692 }
693
694 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
695 const struct pipe_blend_state *state,
696 int mode)
697 {
698 struct r600_context *rctx = (struct r600_context *)ctx;
699 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
700 struct r600_pipe_state *rstate;
701 uint32_t color_control = 0, target_mask = 0;
702
703 if (blend == NULL) {
704 return NULL;
705 }
706 rstate = &blend->rstate;
707
708 rstate->id = R600_PIPE_STATE_BLEND;
709
710 /* R600 does not support per-MRT blends */
711 if (rctx->family > CHIP_R600)
712 color_control |= S_028808_PER_MRT_BLEND(1);
713
714 if (state->logicop_enable) {
715 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
716 } else {
717 color_control |= (0xcc << 16);
718 }
719 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
720 if (state->independent_blend_enable) {
721 for (int i = 0; i < 8; i++) {
722 if (state->rt[i].blend_enable) {
723 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
724 }
725 target_mask |= (state->rt[i].colormask << (4 * i));
726 }
727 } else {
728 for (int i = 0; i < 8; i++) {
729 if (state->rt[0].blend_enable) {
730 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
731 }
732 target_mask |= (state->rt[0].colormask << (4 * i));
733 }
734 }
735
736 if (target_mask)
737 color_control |= S_028808_SPECIAL_OP(mode);
738 else
739 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
740
741 blend->cb_target_mask = target_mask;
742 blend->cb_color_control = color_control;
743 /* only MRT0 has dual src blend */
744 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
745 for (int i = 0; i < 8; i++) {
746 /* state->rt entries > 0 only written if independent blending */
747 const int j = state->independent_blend_enable ? i : 0;
748
749 unsigned eqRGB = state->rt[j].rgb_func;
750 unsigned srcRGB = state->rt[j].rgb_src_factor;
751 unsigned dstRGB = state->rt[j].rgb_dst_factor;
752
753 unsigned eqA = state->rt[j].alpha_func;
754 unsigned srcA = state->rt[j].alpha_src_factor;
755 unsigned dstA = state->rt[j].alpha_dst_factor;
756 uint32_t bc = 0;
757
758 if (!state->rt[j].blend_enable)
759 continue;
760
761 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
762 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
763 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
764
765 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
766 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
767 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
768 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
769 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
770 }
771
772 /* R600 does not support per-MRT blends */
773 if (rctx->family > CHIP_R600)
774 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc);
775 if (i == 0)
776 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc);
777 }
778
779 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK,
780 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
781 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
782 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
783 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
784 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
785
786 blend->alpha_to_one = state->alpha_to_one;
787 return rstate;
788 }
789
790
791 static void *r600_create_blend_state(struct pipe_context *ctx,
792 const struct pipe_blend_state *state)
793 {
794 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
795 }
796
797 static void *r600_create_dsa_state(struct pipe_context *ctx,
798 const struct pipe_depth_stencil_alpha_state *state)
799 {
800 struct r600_context *rctx = (struct r600_context *)ctx;
801 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
802 unsigned db_depth_control, alpha_test_control, alpha_ref;
803 struct r600_pipe_state *rstate;
804
805 if (dsa == NULL) {
806 return NULL;
807 }
808
809 dsa->valuemask[0] = state->stencil[0].valuemask;
810 dsa->valuemask[1] = state->stencil[1].valuemask;
811 dsa->writemask[0] = state->stencil[0].writemask;
812 dsa->writemask[1] = state->stencil[1].writemask;
813
814 rstate = &dsa->rstate;
815
816 rstate->id = R600_PIPE_STATE_DSA;
817 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
818 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
819 S_028800_ZFUNC(state->depth.func);
820
821 /* stencil */
822 if (state->stencil[0].enabled) {
823 db_depth_control |= S_028800_STENCIL_ENABLE(1);
824 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
825 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
826 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
827 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
828
829 if (state->stencil[1].enabled) {
830 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
831 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
832 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
833 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
834 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
835 }
836 }
837
838 /* alpha */
839 alpha_test_control = 0;
840 alpha_ref = 0;
841 if (state->alpha.enabled) {
842 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
843 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
844 alpha_ref = fui(state->alpha.ref_value);
845 }
846 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
847 dsa->alpha_ref = alpha_ref;
848
849 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
850 return rstate;
851 }
852
853 static void *r600_create_rs_state(struct pipe_context *ctx,
854 const struct pipe_rasterizer_state *state)
855 {
856 struct r600_context *rctx = (struct r600_context *)ctx;
857 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
858 struct r600_pipe_state *rstate;
859 unsigned tmp;
860 unsigned prov_vtx = 1, polygon_dual_mode;
861 unsigned sc_mode_cntl;
862 float psize_min, psize_max;
863
864 if (rs == NULL) {
865 return NULL;
866 }
867
868 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
869 state->fill_back != PIPE_POLYGON_MODE_FILL);
870
871 if (state->flatshade_first)
872 prov_vtx = 0;
873
874 rstate = &rs->rstate;
875 rs->flatshade = state->flatshade;
876 rs->sprite_coord_enable = state->sprite_coord_enable;
877 rs->two_side = state->light_twoside;
878 rs->clip_plane_enable = state->clip_plane_enable;
879 rs->pa_sc_line_stipple = state->line_stipple_enable ?
880 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
881 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
882 rs->pa_cl_clip_cntl =
883 S_028810_PS_UCP_MODE(3) |
884 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
885 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
886 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
887 rs->multisample_enable = state->multisample;
888
889 /* offset */
890 rs->offset_units = state->offset_units;
891 rs->offset_scale = state->offset_scale * 12.0f;
892
893 rstate->id = R600_PIPE_STATE_RASTERIZER;
894 tmp = S_0286D4_FLAT_SHADE_ENA(1);
895 if (state->sprite_coord_enable) {
896 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
897 S_0286D4_PNT_SPRITE_OVRD_X(2) |
898 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
899 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
900 S_0286D4_PNT_SPRITE_OVRD_W(1);
901 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
902 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
903 }
904 }
905 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
906
907 /* point size 12.4 fixed point */
908 tmp = r600_pack_float_12p4(state->point_size/2);
909 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
910
911 if (state->point_size_per_vertex) {
912 psize_min = util_get_min_point_size(state);
913 psize_max = 8192;
914 } else {
915 /* Force the point size to be as if the vertex output was disabled. */
916 psize_min = state->point_size;
917 psize_max = state->point_size;
918 }
919 /* Divide by two, because 0.5 = 1 pixel. */
920 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
921 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
922 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
923
924 tmp = r600_pack_float_12p4(state->line_width/2);
925 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
926
927 if (rctx->chip_class >= R700) {
928 sc_mode_cntl =
929 S_028A4C_MSAA_ENABLE(state->multisample) |
930 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
931 S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
932 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
933 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
934 } else {
935 sc_mode_cntl =
936 S_028A4C_MSAA_ENABLE(state->multisample) |
937 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
938 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
939 rs->scissor_enable = state->scissor;
940 }
941 sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
942
943 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
944
945 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
946 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
947 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
948
949 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
950 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
951 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
952 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
953 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
954 S_028814_FACE(!state->front_ccw) |
955 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
956 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
957 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
958 S_028814_POLY_MODE(polygon_dual_mode) |
959 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
960 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
961 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
962 return rstate;
963 }
964
965 static void *r600_create_sampler_state(struct pipe_context *ctx,
966 const struct pipe_sampler_state *state)
967 {
968 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
969 union util_color uc;
970 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
971
972 if (ss == NULL) {
973 return NULL;
974 }
975
976 ss->seamless_cube_map = state->seamless_cube_map;
977 ss->border_color_use = false;
978 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
979 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
980 ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
981 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
982 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
983 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
984 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
985 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
986 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
987 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
988 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
989 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
990 ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
991 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
992 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
993 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
994 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
995 if (uc.ui) {
996 ss->border_color_use = true;
997 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
998 ss->border_color[0] = fui(state->border_color.f[0]);
999 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
1000 ss->border_color[1] = fui(state->border_color.f[1]);
1001 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
1002 ss->border_color[2] = fui(state->border_color.f[2]);
1003 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
1004 ss->border_color[3] = fui(state->border_color.f[3]);
1005 }
1006 return ss;
1007 }
1008
1009 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
1010 struct pipe_resource *texture,
1011 const struct pipe_sampler_view *state)
1012 {
1013 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1014 struct r600_texture *tmp = (struct r600_texture*)texture;
1015 unsigned format, endian;
1016 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1017 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1018 unsigned width, height, depth, offset_level, last_level;
1019
1020 if (view == NULL)
1021 return NULL;
1022
1023 /* initialize base object */
1024 view->base = *state;
1025 view->base.texture = NULL;
1026 pipe_reference(NULL, &texture->reference);
1027 view->base.texture = texture;
1028 view->base.reference.count = 1;
1029 view->base.context = ctx;
1030
1031 swizzle[0] = state->swizzle_r;
1032 swizzle[1] = state->swizzle_g;
1033 swizzle[2] = state->swizzle_b;
1034 swizzle[3] = state->swizzle_a;
1035
1036 format = r600_translate_texformat(ctx->screen, state->format,
1037 swizzle,
1038 &word4, &yuv_format);
1039 assert(format != ~0);
1040 if (format == ~0) {
1041 FREE(view);
1042 return NULL;
1043 }
1044
1045 if (tmp->is_depth && !tmp->is_flushing_texture) {
1046 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1047 FREE(view);
1048 return NULL;
1049 }
1050 tmp = tmp->flushed_depth_texture;
1051 }
1052
1053 endian = r600_colorformat_endian_swap(format);
1054
1055 offset_level = state->u.tex.first_level;
1056 last_level = state->u.tex.last_level - offset_level;
1057 width = tmp->surface.level[offset_level].npix_x;
1058 height = tmp->surface.level[offset_level].npix_y;
1059 depth = tmp->surface.level[offset_level].npix_z;
1060 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1061 tile_type = tmp->tile_type;
1062
1063 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1064 height = 1;
1065 depth = texture->array_size;
1066 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1067 depth = texture->array_size;
1068 }
1069 switch (tmp->surface.level[offset_level].mode) {
1070 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1071 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1072 break;
1073 case RADEON_SURF_MODE_1D:
1074 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1075 break;
1076 case RADEON_SURF_MODE_2D:
1077 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1078 break;
1079 case RADEON_SURF_MODE_LINEAR:
1080 default:
1081 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1082 break;
1083 }
1084
1085 view->tex_resource = &tmp->resource;
1086 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1087 S_038000_TILE_MODE(array_mode) |
1088 S_038000_TILE_TYPE(tile_type) |
1089 S_038000_PITCH((pitch / 8) - 1) |
1090 S_038000_TEX_WIDTH(width - 1));
1091 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
1092 S_038004_TEX_DEPTH(depth - 1) |
1093 S_038004_DATA_FORMAT(format));
1094 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
1095 if (offset_level >= tmp->surface.last_level) {
1096 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
1097 } else {
1098 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1099 }
1100 view->tex_resource_words[4] = (word4 |
1101 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1102 S_038010_REQUEST_SIZE(1) |
1103 S_038010_ENDIAN_SWAP(endian) |
1104 S_038010_BASE_LEVEL(0));
1105 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1106 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1107 if (texture->nr_samples > 1) {
1108 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1109 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
1110 } else {
1111 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
1112 }
1113 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1114 S_038018_MAX_ANISO(4 /* max 16 samples */));
1115 return &view->base;
1116 }
1117
1118 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1119 {
1120 struct radeon_winsys_cs *cs = rctx->cs;
1121 struct pipe_clip_state *state = &rctx->clip_state.state;
1122
1123 r600_write_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
1124 r600_write_array(cs, 6*4, (unsigned*)state);
1125 }
1126
1127 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1128 const struct pipe_poly_stipple *state)
1129 {
1130 }
1131
1132 void r600_set_scissor_state(struct r600_context *rctx,
1133 const struct pipe_scissor_state *state)
1134 {
1135 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1136 uint32_t tl, br;
1137
1138 if (rstate == NULL)
1139 return;
1140
1141 rstate->id = R600_PIPE_STATE_SCISSOR;
1142 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1143 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1144 r600_pipe_state_add_reg(rstate,
1145 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1146 r600_pipe_state_add_reg(rstate,
1147 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1148
1149 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1150 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1151 r600_context_pipe_state_set(rctx, rstate);
1152 }
1153
1154 static void r600_pipe_set_scissor_state(struct pipe_context *ctx,
1155 const struct pipe_scissor_state *state)
1156 {
1157 struct r600_context *rctx = (struct r600_context *)ctx;
1158
1159 if (rctx->chip_class == R600) {
1160 rctx->scissor_state = *state;
1161
1162 if (!rctx->scissor_enable)
1163 return;
1164 }
1165
1166 r600_set_scissor_state(rctx, state);
1167 }
1168
1169 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
1170 unsigned size, unsigned alignment)
1171 {
1172 struct pipe_resource buffer;
1173
1174 memset(&buffer, 0, sizeof buffer);
1175 buffer.target = PIPE_BUFFER;
1176 buffer.format = PIPE_FORMAT_R8_UNORM;
1177 buffer.bind = PIPE_BIND_CUSTOM;
1178 buffer.usage = PIPE_USAGE_STATIC;
1179 buffer.flags = 0;
1180 buffer.width0 = size;
1181 buffer.height0 = 1;
1182 buffer.depth0 = 1;
1183 buffer.array_size = 1;
1184
1185 return (struct r600_resource*)
1186 r600_buffer_create(&rscreen->screen, &buffer, alignment);
1187 }
1188
1189 static void r600_init_color_surface(struct r600_context *rctx,
1190 struct r600_surface *surf,
1191 bool force_cmask_fmask)
1192 {
1193 struct r600_screen *rscreen = rctx->screen;
1194 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1195 unsigned level = surf->base.u.tex.level;
1196 unsigned pitch, slice;
1197 unsigned color_info;
1198 unsigned format, swap, ntype, endian;
1199 unsigned offset;
1200 const struct util_format_description *desc;
1201 int i;
1202 bool blend_bypass = 0, blend_clamp = 1;
1203
1204 if (rtex->is_depth && !rtex->is_flushing_texture) {
1205 r600_init_flushed_depth_texture(&rctx->context, surf->base.texture, NULL);
1206 rtex = rtex->flushed_depth_texture;
1207 assert(rtex);
1208 }
1209
1210 offset = rtex->surface.level[level].offset;
1211 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1212 offset += rtex->surface.level[level].slice_size *
1213 surf->base.u.tex.first_layer;
1214 }
1215 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1216 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1217 if (slice) {
1218 slice = slice - 1;
1219 }
1220 color_info = 0;
1221 switch (rtex->surface.level[level].mode) {
1222 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1223 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1224 break;
1225 case RADEON_SURF_MODE_1D:
1226 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1227 break;
1228 case RADEON_SURF_MODE_2D:
1229 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1230 break;
1231 case RADEON_SURF_MODE_LINEAR:
1232 default:
1233 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1234 break;
1235 }
1236
1237 desc = util_format_description(surf->base.format);
1238
1239 for (i = 0; i < 4; i++) {
1240 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1241 break;
1242 }
1243 }
1244
1245 ntype = V_0280A0_NUMBER_UNORM;
1246 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1247 ntype = V_0280A0_NUMBER_SRGB;
1248 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1249 if (desc->channel[i].normalized)
1250 ntype = V_0280A0_NUMBER_SNORM;
1251 else if (desc->channel[i].pure_integer)
1252 ntype = V_0280A0_NUMBER_SINT;
1253 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1254 if (desc->channel[i].normalized)
1255 ntype = V_0280A0_NUMBER_UNORM;
1256 else if (desc->channel[i].pure_integer)
1257 ntype = V_0280A0_NUMBER_UINT;
1258 }
1259
1260 format = r600_translate_colorformat(surf->base.format);
1261 assert(format != ~0);
1262
1263 swap = r600_translate_colorswap(surf->base.format);
1264 assert(swap != ~0);
1265
1266 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1267 endian = ENDIAN_NONE;
1268 } else {
1269 endian = r600_colorformat_endian_swap(format);
1270 }
1271
1272 /* set blend bypass according to docs if SINT/UINT or
1273 8/24 COLOR variants */
1274 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1275 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1276 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1277 blend_clamp = 0;
1278 blend_bypass = 1;
1279 }
1280
1281 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
1282
1283 color_info |= S_0280A0_FORMAT(format) |
1284 S_0280A0_COMP_SWAP(swap) |
1285 S_0280A0_BLEND_BYPASS(blend_bypass) |
1286 S_0280A0_BLEND_CLAMP(blend_clamp) |
1287 S_0280A0_NUMBER_TYPE(ntype) |
1288 S_0280A0_ENDIAN(endian);
1289
1290 /* EXPORT_NORM is an optimzation that can be enabled for better
1291 * performance in certain cases
1292 */
1293 if (rctx->chip_class == R600) {
1294 /* EXPORT_NORM can be enabled if:
1295 * - 11-bit or smaller UNORM/SNORM/SRGB
1296 * - BLEND_CLAMP is enabled
1297 * - BLEND_FLOAT32 is disabled
1298 */
1299 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1300 (desc->channel[i].size < 12 &&
1301 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1302 ntype != V_0280A0_NUMBER_UINT &&
1303 ntype != V_0280A0_NUMBER_SINT) &&
1304 G_0280A0_BLEND_CLAMP(color_info) &&
1305 !G_0280A0_BLEND_FLOAT32(color_info)) {
1306 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1307 surf->export_16bpc = true;
1308 }
1309 } else {
1310 /* EXPORT_NORM can be enabled if:
1311 * - 11-bit or smaller UNORM/SNORM/SRGB
1312 * - 16-bit or smaller FLOAT
1313 */
1314 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1315 ((desc->channel[i].size < 12 &&
1316 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1317 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1318 (desc->channel[i].size < 17 &&
1319 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1320 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1321 surf->export_16bpc = true;
1322 }
1323 }
1324
1325 /* These might not always be initialized to zero. */
1326 surf->cb_color_base = offset >> 8;
1327 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
1328 S_028060_SLICE_TILE_MAX(slice);
1329 surf->cb_color_fmask = surf->cb_color_base;
1330 surf->cb_color_cmask = surf->cb_color_base;
1331 surf->cb_color_mask = 0;
1332
1333 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1334 &rtex->resource.b.b);
1335 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1336 &rtex->resource.b.b);
1337
1338 if (rtex->cmask_size) {
1339 surf->cb_color_cmask = rtex->cmask_offset >> 8;
1340 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask_slice_tile_max);
1341
1342 if (rtex->fmask_size) {
1343 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1344 surf->cb_color_fmask = rtex->fmask_offset >> 8;
1345 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(slice);
1346 } else { /* cmask only */
1347 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
1348 }
1349 } else if (force_cmask_fmask) {
1350 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1351 *
1352 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1353 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1354 * because it's not an MSAA buffer.
1355 */
1356 struct r600_cmask_info cmask;
1357 struct r600_fmask_info fmask;
1358
1359 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
1360 r600_texture_get_fmask_info(rscreen, rtex, 8, &fmask);
1361
1362 /* CMASK. */
1363 if (!rctx->dummy_cmask ||
1364 rctx->dummy_cmask->buf->size < cmask.size ||
1365 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1366 struct pipe_transfer *transfer;
1367 void *ptr;
1368
1369 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1370 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1371
1372 /* Set the contents to 0xCC. */
1373 ptr = pipe_buffer_map(&rctx->context, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1374 memset(ptr, 0xCC, cmask.size);
1375 pipe_buffer_unmap(&rctx->context, transfer);
1376 }
1377 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1378 &rctx->dummy_cmask->b.b);
1379
1380 /* FMASK. */
1381 if (!rctx->dummy_fmask ||
1382 rctx->dummy_fmask->buf->size < fmask.size ||
1383 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1384 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1385 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1386
1387 }
1388 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1389 &rctx->dummy_fmask->b.b);
1390
1391 /* Init the registers. */
1392 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1393 surf->cb_color_cmask = 0;
1394 surf->cb_color_fmask = 0;
1395 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1396 S_028100_FMASK_TILE_MAX(slice);
1397 }
1398
1399 surf->cb_color_info = color_info;
1400
1401 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1402 surf->cb_color_view = 0;
1403 } else {
1404 surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
1405 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
1406 }
1407
1408 surf->color_initialized = true;
1409 }
1410
1411 static void r600_init_depth_surface(struct r600_context *rctx,
1412 struct r600_surface *surf)
1413 {
1414 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1415 unsigned level, pitch, slice, format, offset, array_mode;
1416
1417 level = surf->base.u.tex.level;
1418 offset = rtex->surface.level[level].offset;
1419 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1420 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1421 if (slice) {
1422 slice = slice - 1;
1423 }
1424 switch (rtex->surface.level[level].mode) {
1425 case RADEON_SURF_MODE_2D:
1426 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1427 break;
1428 case RADEON_SURF_MODE_1D:
1429 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1430 case RADEON_SURF_MODE_LINEAR:
1431 default:
1432 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1433 break;
1434 }
1435
1436 format = r600_translate_dbformat(surf->base.format);
1437 assert(format != ~0);
1438
1439 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1440 surf->db_depth_base = offset >> 8;
1441 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1442 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1443 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1444 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1445
1446 surf->depth_initialized = true;
1447 }
1448
1449 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1450 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1451 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1452 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1453 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1454
1455 static uint32_t r600_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
1456 {
1457 static uint32_t sample_locs_2x[] = {
1458 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1459 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1460 };
1461 static unsigned max_dist_2x = 4;
1462 static uint32_t sample_locs_4x[] = {
1463 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1464 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1465 };
1466 static unsigned max_dist_4x = 6;
1467 static uint32_t sample_locs_8x[] = {
1468 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1469 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1470 };
1471 static unsigned max_dist_8x = 8;
1472 struct r600_context *rctx = (struct r600_context *)ctx;
1473
1474 if (rctx->family == CHIP_R600) {
1475 switch (nsample) {
1476 case 0:
1477 case 1:
1478 return 0;
1479 case 2:
1480 r600_pipe_state_add_reg(rstate, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1481 return max_dist_2x;
1482 case 4:
1483 r600_pipe_state_add_reg(rstate, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1484 return max_dist_4x;
1485 case 8:
1486 r600_pipe_state_add_reg(rstate, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, sample_locs_8x[0]);
1487 r600_pipe_state_add_reg(rstate, R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1, sample_locs_8x[1]);
1488 return max_dist_8x;
1489 }
1490 } else {
1491 switch (nsample) {
1492 case 0:
1493 case 1:
1494 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0);
1495 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, 0);
1496 return 0;
1497 case 2:
1498 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_2x[0]);
1499 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_2x[1]);
1500 return max_dist_2x;
1501 case 4:
1502 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_4x[0]);
1503 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_4x[1]);
1504 return max_dist_4x;
1505 case 8:
1506 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_8x[0]);
1507 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_8x[1]);
1508 return max_dist_8x;
1509 }
1510 }
1511 R600_ERR("Invalid nr_samples %i\n", nsample);
1512 return 0;
1513 }
1514
1515 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1516 const struct pipe_framebuffer_state *state)
1517 {
1518 struct r600_context *rctx = (struct r600_context *)ctx;
1519 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1520 struct r600_surface *surf;
1521 struct r600_resource *res;
1522 struct r600_texture *rtex;
1523 uint32_t tl, br, i, nr_samples, max_dist;
1524 bool is_resolve = state->nr_cbufs == 2 &&
1525 state->cbufs[0]->texture->nr_samples > 1 &&
1526 state->cbufs[1]->texture->nr_samples <= 1;
1527 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1528 bool cb1_force_cmask_fmask = rctx->chip_class == R600 && is_resolve;
1529
1530 if (rstate == NULL)
1531 return;
1532
1533 if (rctx->framebuffer.nr_cbufs) {
1534 rctx->flags |= R600_CONTEXT_CB_FLUSH;
1535 }
1536 if (rctx->framebuffer.zsbuf) {
1537 rctx->flags |= R600_CONTEXT_DB_FLUSH;
1538 }
1539 /* R6xx errata */
1540 if (rctx->chip_class == R600) {
1541 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
1542 }
1543
1544 /* unreference old buffer and reference new one */
1545 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1546
1547 util_copy_framebuffer_state(&rctx->framebuffer, state);
1548
1549
1550 /* Colorbuffers. */
1551 rctx->export_16bpc = true;
1552 rctx->nr_cbufs = state->nr_cbufs;
1553 rctx->cb0_is_integer = state->nr_cbufs &&
1554 util_format_is_pure_integer(state->cbufs[0]->format);
1555 rctx->compressed_cb_mask = 0;
1556
1557 for (i = 0; i < state->nr_cbufs; i++) {
1558 bool force_cmask_fmask = cb1_force_cmask_fmask && i == 1;
1559 surf = (struct r600_surface*)state->cbufs[i];
1560 res = (struct r600_resource*)surf->base.texture;
1561 rtex = (struct r600_texture*)res;
1562
1563 if (!surf->color_initialized || force_cmask_fmask) {
1564 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1565 if (force_cmask_fmask) {
1566 /* re-initialize later without compression */
1567 surf->color_initialized = false;
1568 }
1569 }
1570
1571 if (!surf->export_16bpc) {
1572 rctx->export_16bpc = false;
1573 }
1574
1575 r600_pipe_state_add_reg_bo(rstate, R_028040_CB_COLOR0_BASE + i * 4,
1576 surf->cb_color_base, res, RADEON_USAGE_READWRITE);
1577 r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + i * 4,
1578 surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1579 r600_pipe_state_add_reg(rstate, R_028060_CB_COLOR0_SIZE + i * 4,
1580 surf->cb_color_size);
1581 r600_pipe_state_add_reg(rstate, R_028080_CB_COLOR0_VIEW + i * 4,
1582 surf->cb_color_view);
1583 r600_pipe_state_add_reg_bo(rstate, R_0280E0_CB_COLOR0_FRAG + i * 4,
1584 surf->cb_color_fmask, surf->cb_buffer_fmask,
1585 RADEON_USAGE_READWRITE);
1586 r600_pipe_state_add_reg_bo(rstate, R_0280C0_CB_COLOR0_TILE + i * 4,
1587 surf->cb_color_cmask, surf->cb_buffer_cmask,
1588 RADEON_USAGE_READWRITE);
1589 r600_pipe_state_add_reg(rstate, R_028100_CB_COLOR0_MASK + i * 4,
1590 surf->cb_color_mask);
1591
1592 if (rtex->fmask_size && rtex->cmask_size) {
1593 rctx->compressed_cb_mask |= 1 << i;
1594 }
1595 }
1596 /* set CB_COLOR1_INFO for possible dual-src blending */
1597 if (i == 1) {
1598 r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + 1 * 4,
1599 surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1600 i++;
1601 }
1602 for (; i < 8 ; i++) {
1603 r600_pipe_state_add_reg(rstate, R_0280A0_CB_COLOR0_INFO + i * 4, 0);
1604 }
1605
1606 /* Update alpha-test state dependencies.
1607 * Alpha-test is done on the first colorbuffer only. */
1608 if (state->nr_cbufs) {
1609 surf = (struct r600_surface*)state->cbufs[0];
1610 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1611 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1612 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1613 }
1614 }
1615
1616 /* ZS buffer. */
1617 if (state->zsbuf) {
1618 surf = (struct r600_surface*)state->zsbuf;
1619 res = (struct r600_resource*)surf->base.texture;
1620
1621 if (!surf->depth_initialized) {
1622 r600_init_depth_surface(rctx, surf);
1623 }
1624
1625 r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE, surf->db_depth_base,
1626 res, RADEON_USAGE_READWRITE);
1627 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE, surf->db_depth_size);
1628 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, surf->db_depth_view);
1629 r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO, surf->db_depth_info,
1630 res, RADEON_USAGE_READWRITE);
1631 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1632 }
1633
1634 /* Framebuffer dimensions. */
1635 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1636 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1637
1638 r600_pipe_state_add_reg(rstate,
1639 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1640 r600_pipe_state_add_reg(rstate,
1641 R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1642
1643 /* If we're doing MSAA resolve... */
1644 if (is_resolve) {
1645 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL, 1);
1646 } else {
1647 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1648 * will assure that the alpha-test will work even if there is
1649 * no colorbuffer bound. */
1650 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1651 (1ull << MAX2(state->nr_cbufs, 1)) - 1);
1652 }
1653
1654 /* Multisampling */
1655 if (state->nr_cbufs)
1656 nr_samples = state->cbufs[0]->texture->nr_samples;
1657 else if (state->zsbuf)
1658 nr_samples = state->zsbuf->texture->nr_samples;
1659 else
1660 nr_samples = 0;
1661
1662 max_dist = r600_set_ms_pos(ctx, rstate, nr_samples);
1663
1664 if (nr_samples > 1) {
1665 unsigned log_samples = util_logbase2(nr_samples);
1666
1667 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL,
1668 S_028C00_LAST_PIXEL(1) |
1669 S_028C00_EXPAND_LINE_WIDTH(1));
1670 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1671 S_028C04_MSAA_NUM_SAMPLES(log_samples) |
1672 S_028C04_MAX_SAMPLE_DIST(max_dist));
1673 } else {
1674 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
1675 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 0);
1676 }
1677
1678 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1679 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1680 r600_context_pipe_state_set(rctx, rstate);
1681
1682 if (state->zsbuf) {
1683 r600_polygon_offset_update(rctx);
1684 }
1685
1686 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1687 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1688 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1689 }
1690
1691 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1692 rctx->alphatest_state.bypass = false;
1693 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1694 }
1695 }
1696
1697 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1698 {
1699 struct radeon_winsys_cs *cs = rctx->cs;
1700 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1701
1702 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1703 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1704 if (rctx->chip_class == R600) {
1705 r600_write_value(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1706 r600_write_value(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1707 } else {
1708 r600_write_value(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1709 r600_write_value(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1710 }
1711 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1712 } else {
1713 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1714 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1715 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1716
1717 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1718 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1719 /* Always enable the first color output to make sure alpha-test works even without one. */
1720 r600_write_value(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1721 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1722 a->cb_color_control |
1723 S_028808_MULTIWRITE_ENABLE(multiwrite));
1724 }
1725 }
1726
1727 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1728 {
1729 struct radeon_winsys_cs *cs = rctx->cs;
1730 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1731 unsigned db_render_control = 0;
1732 unsigned db_render_override =
1733 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
1734 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1735 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1736
1737 if (a->occlusion_query_enabled) {
1738 if (rctx->chip_class >= R700) {
1739 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1740 }
1741 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1742 }
1743 if (a->flush_depthstencil_through_cb) {
1744 assert(a->copy_depth || a->copy_stencil);
1745
1746 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1747 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1748 S_028D0C_COPY_CENTROID(1) |
1749 S_028D0C_COPY_SAMPLE(a->copy_sample);
1750 }
1751
1752 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1753 r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1754 r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1755 }
1756
1757 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1758 {
1759 struct radeon_winsys_cs *cs = rctx->cs;
1760 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1761
1762 while (dirty_mask) {
1763 struct pipe_vertex_buffer *vb;
1764 struct r600_resource *rbuffer;
1765 unsigned offset;
1766 unsigned buffer_index = u_bit_scan(&dirty_mask);
1767
1768 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1769 rbuffer = (struct r600_resource*)vb->buffer;
1770 assert(rbuffer);
1771
1772 offset = vb->buffer_offset;
1773
1774 /* fetch resources start at index 320 */
1775 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1776 r600_write_value(cs, (320 + buffer_index) * 7);
1777 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1778 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1779 r600_write_value(cs, /* RESOURCEi_WORD2 */
1780 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1781 S_038008_STRIDE(vb->stride));
1782 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1783 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1784 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1785 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1786
1787 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1788 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1789 }
1790 }
1791
1792 static void r600_emit_constant_buffers(struct r600_context *rctx,
1793 struct r600_constbuf_state *state,
1794 unsigned buffer_id_base,
1795 unsigned reg_alu_constbuf_size,
1796 unsigned reg_alu_const_cache)
1797 {
1798 struct radeon_winsys_cs *cs = rctx->cs;
1799 uint32_t dirty_mask = state->dirty_mask;
1800
1801 while (dirty_mask) {
1802 struct pipe_constant_buffer *cb;
1803 struct r600_resource *rbuffer;
1804 unsigned offset;
1805 unsigned buffer_index = ffs(dirty_mask) - 1;
1806
1807 cb = &state->cb[buffer_index];
1808 rbuffer = (struct r600_resource*)cb->buffer;
1809 assert(rbuffer);
1810
1811 offset = cb->buffer_offset;
1812
1813 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1814 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1815 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1816
1817 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1818 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1819
1820 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1821 r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
1822 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1823 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1824 r600_write_value(cs, /* RESOURCEi_WORD2 */
1825 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1826 S_038008_STRIDE(16));
1827 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1828 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1829 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1830 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1831
1832 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1833 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1834
1835 dirty_mask &= ~(1 << buffer_index);
1836 }
1837 state->dirty_mask = 0;
1838 }
1839
1840 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1841 {
1842 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 160,
1843 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1844 R_028980_ALU_CONST_CACHE_VS_0);
1845 }
1846
1847 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1848 {
1849 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
1850 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1851 R_0289C0_ALU_CONST_CACHE_GS_0);
1852 }
1853
1854 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1855 {
1856 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
1857 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1858 R_028940_ALU_CONST_CACHE_PS_0);
1859 }
1860
1861 static void r600_emit_sampler_views(struct r600_context *rctx,
1862 struct r600_samplerview_state *state,
1863 unsigned resource_id_base)
1864 {
1865 struct radeon_winsys_cs *cs = rctx->cs;
1866 uint32_t dirty_mask = state->dirty_mask;
1867
1868 while (dirty_mask) {
1869 struct r600_pipe_sampler_view *rview;
1870 unsigned resource_index = u_bit_scan(&dirty_mask);
1871 unsigned reloc;
1872
1873 rview = state->views[resource_index];
1874 assert(rview);
1875
1876 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1877 r600_write_value(cs, (resource_id_base + resource_index) * 7);
1878 r600_write_array(cs, 7, rview->tex_resource_words);
1879
1880 /* XXX The kernel needs two relocations. This is stupid. */
1881 reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
1882 RADEON_USAGE_READ);
1883 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1884 r600_write_value(cs, reloc);
1885 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1886 r600_write_value(cs, reloc);
1887 }
1888 state->dirty_mask = 0;
1889 }
1890
1891 /* Resource IDs:
1892 * PS: 0 .. +160
1893 * VS: 160 .. +160
1894 * FS: 320 .. +16
1895 * GS: 336 .. +160
1896 */
1897
1898 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1899 {
1900 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 160 + R600_MAX_CONST_BUFFERS);
1901 }
1902
1903 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1904 {
1905 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
1906 }
1907
1908 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1909 {
1910 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
1911 }
1912
1913 static void r600_emit_sampler_states(struct r600_context *rctx,
1914 struct r600_textures_info *texinfo,
1915 unsigned resource_id_base,
1916 unsigned border_color_reg)
1917 {
1918 struct radeon_winsys_cs *cs = rctx->cs;
1919 uint32_t dirty_mask = texinfo->states.dirty_mask;
1920
1921 while (dirty_mask) {
1922 struct r600_pipe_sampler_state *rstate;
1923 struct r600_pipe_sampler_view *rview;
1924 unsigned i = u_bit_scan(&dirty_mask);
1925
1926 rstate = texinfo->states.states[i];
1927 assert(rstate);
1928 rview = texinfo->views.views[i];
1929
1930 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1931 * filtering between layers.
1932 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1933 */
1934 if (rview) {
1935 enum pipe_texture_target target = rview->base.texture->target;
1936 if (target == PIPE_TEXTURE_1D_ARRAY ||
1937 target == PIPE_TEXTURE_2D_ARRAY) {
1938 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1939 texinfo->is_array_sampler[i] = true;
1940 } else {
1941 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1942 texinfo->is_array_sampler[i] = false;
1943 }
1944 }
1945
1946 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1947 r600_write_value(cs, (resource_id_base + i) * 3);
1948 r600_write_array(cs, 3, rstate->tex_sampler_words);
1949
1950 if (rstate->border_color_use) {
1951 unsigned offset;
1952
1953 offset = border_color_reg;
1954 offset += i * 16;
1955 r600_write_config_reg_seq(cs, offset, 4);
1956 r600_write_array(cs, 4, rstate->border_color);
1957 }
1958 }
1959 texinfo->states.dirty_mask = 0;
1960 }
1961
1962 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1963 {
1964 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1965 }
1966
1967 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1968 {
1969 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1970 }
1971
1972 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1973 {
1974 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1975 }
1976
1977 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1978 {
1979 struct radeon_winsys_cs *cs = rctx->cs;
1980 unsigned tmp;
1981
1982 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1983 S_009508_SYNC_GRADIENT(1) |
1984 S_009508_SYNC_WALKER(1) |
1985 S_009508_SYNC_ALIGNER(1);
1986 if (!rctx->seamless_cube_map.enabled) {
1987 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1988 }
1989 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1990 }
1991
1992 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1993 {
1994 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1995 uint8_t mask = s->sample_mask;
1996
1997 r600_write_context_reg(rctx->cs, R_028C48_PA_SC_AA_MASK,
1998 mask | (mask << 8) | (mask << 16) | (mask << 24));
1999 }
2000
2001 void r600_init_state_functions(struct r600_context *rctx)
2002 {
2003 unsigned id = 4;
2004
2005 /* !!!
2006 * To avoid GPU lockup registers must be emited in a specific order
2007 * (no kidding ...). The order below is important and have been
2008 * partialy infered from analyzing fglrx command stream.
2009 *
2010 * Don't reorder atom without carefully checking the effect (GPU lockup
2011 * or piglit regression).
2012 * !!!
2013 */
2014
2015 /* shader const */
2016 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
2017 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
2018 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
2019
2020 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2021 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
2022 */
2023 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
2024 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
2025 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
2026 /* resource */
2027 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
2028 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
2029 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
2030 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
2031
2032 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 6);
2033 r600_init_atom(rctx, &rctx->vgt2_state.atom, id++, r600_emit_vgt2_state, 3);
2034
2035 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
2036 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
2037 rctx->sample_mask.sample_mask = ~0;
2038
2039 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
2040 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
2041 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
2042 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
2043 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
2044 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 4);
2045 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
2046 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
2047
2048 rctx->context.create_blend_state = r600_create_blend_state;
2049 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
2050 rctx->context.create_rasterizer_state = r600_create_rs_state;
2051 rctx->context.create_sampler_state = r600_create_sampler_state;
2052 rctx->context.create_sampler_view = r600_create_sampler_view;
2053 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
2054 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
2055 rctx->context.set_scissor_state = r600_pipe_set_scissor_state;
2056 }
2057
2058 /* Adjust GPR allocation on R6xx/R7xx */
2059 void r600_adjust_gprs(struct r600_context *rctx)
2060 {
2061 struct r600_pipe_state rstate;
2062 unsigned num_ps_gprs = rctx->default_ps_gprs;
2063 unsigned num_vs_gprs = rctx->default_vs_gprs;
2064 unsigned tmp;
2065 int diff;
2066
2067 if (rctx->ps_shader->current->shader.bc.ngpr > rctx->default_ps_gprs) {
2068 diff = rctx->ps_shader->current->shader.bc.ngpr - rctx->default_ps_gprs;
2069 num_vs_gprs -= diff;
2070 num_ps_gprs += diff;
2071 }
2072
2073 if (rctx->vs_shader->current->shader.bc.ngpr > rctx->default_vs_gprs)
2074 {
2075 diff = rctx->vs_shader->current->shader.bc.ngpr - rctx->default_vs_gprs;
2076 num_ps_gprs -= diff;
2077 num_vs_gprs += diff;
2078 }
2079
2080 tmp = 0;
2081 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2082 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2083 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
2084 rstate.nregs = 0;
2085 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp);
2086
2087 r600_context_pipe_state_set(rctx, &rstate);
2088 }
2089
2090 void r600_init_atom_start_cs(struct r600_context *rctx)
2091 {
2092 int ps_prio;
2093 int vs_prio;
2094 int gs_prio;
2095 int es_prio;
2096 int num_ps_gprs;
2097 int num_vs_gprs;
2098 int num_gs_gprs;
2099 int num_es_gprs;
2100 int num_temp_gprs;
2101 int num_ps_threads;
2102 int num_vs_threads;
2103 int num_gs_threads;
2104 int num_es_threads;
2105 int num_ps_stack_entries;
2106 int num_vs_stack_entries;
2107 int num_gs_stack_entries;
2108 int num_es_stack_entries;
2109 enum radeon_family family;
2110 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2111 uint32_t tmp;
2112
2113 r600_init_command_buffer(rctx, cb, 0, 256);
2114
2115 /* R6xx requires this packet at the start of each command buffer */
2116 if (rctx->chip_class == R600) {
2117 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2118 r600_store_value(cb, 0);
2119 }
2120 /* All asics require this one */
2121 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2122 r600_store_value(cb, 0x80000000);
2123 r600_store_value(cb, 0x80000000);
2124
2125 family = rctx->family;
2126 ps_prio = 0;
2127 vs_prio = 1;
2128 gs_prio = 2;
2129 es_prio = 3;
2130 switch (family) {
2131 case CHIP_R600:
2132 num_ps_gprs = 192;
2133 num_vs_gprs = 56;
2134 num_temp_gprs = 4;
2135 num_gs_gprs = 0;
2136 num_es_gprs = 0;
2137 num_ps_threads = 136;
2138 num_vs_threads = 48;
2139 num_gs_threads = 4;
2140 num_es_threads = 4;
2141 num_ps_stack_entries = 128;
2142 num_vs_stack_entries = 128;
2143 num_gs_stack_entries = 0;
2144 num_es_stack_entries = 0;
2145 break;
2146 case CHIP_RV630:
2147 case CHIP_RV635:
2148 num_ps_gprs = 84;
2149 num_vs_gprs = 36;
2150 num_temp_gprs = 4;
2151 num_gs_gprs = 0;
2152 num_es_gprs = 0;
2153 num_ps_threads = 144;
2154 num_vs_threads = 40;
2155 num_gs_threads = 4;
2156 num_es_threads = 4;
2157 num_ps_stack_entries = 40;
2158 num_vs_stack_entries = 40;
2159 num_gs_stack_entries = 32;
2160 num_es_stack_entries = 16;
2161 break;
2162 case CHIP_RV610:
2163 case CHIP_RV620:
2164 case CHIP_RS780:
2165 case CHIP_RS880:
2166 default:
2167 num_ps_gprs = 84;
2168 num_vs_gprs = 36;
2169 num_temp_gprs = 4;
2170 num_gs_gprs = 0;
2171 num_es_gprs = 0;
2172 num_ps_threads = 136;
2173 num_vs_threads = 48;
2174 num_gs_threads = 4;
2175 num_es_threads = 4;
2176 num_ps_stack_entries = 40;
2177 num_vs_stack_entries = 40;
2178 num_gs_stack_entries = 32;
2179 num_es_stack_entries = 16;
2180 break;
2181 case CHIP_RV670:
2182 num_ps_gprs = 144;
2183 num_vs_gprs = 40;
2184 num_temp_gprs = 4;
2185 num_gs_gprs = 0;
2186 num_es_gprs = 0;
2187 num_ps_threads = 136;
2188 num_vs_threads = 48;
2189 num_gs_threads = 4;
2190 num_es_threads = 4;
2191 num_ps_stack_entries = 40;
2192 num_vs_stack_entries = 40;
2193 num_gs_stack_entries = 32;
2194 num_es_stack_entries = 16;
2195 break;
2196 case CHIP_RV770:
2197 num_ps_gprs = 192;
2198 num_vs_gprs = 56;
2199 num_temp_gprs = 4;
2200 num_gs_gprs = 0;
2201 num_es_gprs = 0;
2202 num_ps_threads = 188;
2203 num_vs_threads = 60;
2204 num_gs_threads = 0;
2205 num_es_threads = 0;
2206 num_ps_stack_entries = 256;
2207 num_vs_stack_entries = 256;
2208 num_gs_stack_entries = 0;
2209 num_es_stack_entries = 0;
2210 break;
2211 case CHIP_RV730:
2212 case CHIP_RV740:
2213 num_ps_gprs = 84;
2214 num_vs_gprs = 36;
2215 num_temp_gprs = 4;
2216 num_gs_gprs = 0;
2217 num_es_gprs = 0;
2218 num_ps_threads = 188;
2219 num_vs_threads = 60;
2220 num_gs_threads = 0;
2221 num_es_threads = 0;
2222 num_ps_stack_entries = 128;
2223 num_vs_stack_entries = 128;
2224 num_gs_stack_entries = 0;
2225 num_es_stack_entries = 0;
2226 break;
2227 case CHIP_RV710:
2228 num_ps_gprs = 192;
2229 num_vs_gprs = 56;
2230 num_temp_gprs = 4;
2231 num_gs_gprs = 0;
2232 num_es_gprs = 0;
2233 num_ps_threads = 144;
2234 num_vs_threads = 48;
2235 num_gs_threads = 0;
2236 num_es_threads = 0;
2237 num_ps_stack_entries = 128;
2238 num_vs_stack_entries = 128;
2239 num_gs_stack_entries = 0;
2240 num_es_stack_entries = 0;
2241 break;
2242 }
2243
2244 rctx->default_ps_gprs = num_ps_gprs;
2245 rctx->default_vs_gprs = num_vs_gprs;
2246 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2247
2248 /* SQ_CONFIG */
2249 tmp = 0;
2250 switch (family) {
2251 case CHIP_RV610:
2252 case CHIP_RV620:
2253 case CHIP_RS780:
2254 case CHIP_RS880:
2255 case CHIP_RV710:
2256 break;
2257 default:
2258 tmp |= S_008C00_VC_ENABLE(1);
2259 break;
2260 }
2261 tmp |= S_008C00_DX9_CONSTS(0);
2262 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2263 tmp |= S_008C00_PS_PRIO(ps_prio);
2264 tmp |= S_008C00_VS_PRIO(vs_prio);
2265 tmp |= S_008C00_GS_PRIO(gs_prio);
2266 tmp |= S_008C00_ES_PRIO(es_prio);
2267 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2268
2269 /* SQ_GPR_RESOURCE_MGMT_2 */
2270 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2271 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2272 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2273 r600_store_value(cb, tmp);
2274
2275 /* SQ_THREAD_RESOURCE_MGMT */
2276 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2277 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2278 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2279 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2280 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2281
2282 /* SQ_STACK_RESOURCE_MGMT_1 */
2283 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2284 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2285 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2286
2287 /* SQ_STACK_RESOURCE_MGMT_2 */
2288 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2289 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2290 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2291
2292 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2293
2294 if (rctx->chip_class >= R700) {
2295 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2296 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2297 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2298 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2299 } else {
2300 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2301 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2302 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2303 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2304 }
2305 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2306 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2307 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2308 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2309 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2310 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2311 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2312 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2313 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2314 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2315
2316 /* to avoid GPU doing any preloading of constant from random address */
2317 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2318 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2319 r600_store_value(cb, 0);
2320 r600_store_value(cb, 0);
2321 r600_store_value(cb, 0);
2322 r600_store_value(cb, 0);
2323 r600_store_value(cb, 0);
2324 r600_store_value(cb, 0);
2325 r600_store_value(cb, 0);
2326 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2327 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2328 r600_store_value(cb, 0);
2329 r600_store_value(cb, 0);
2330 r600_store_value(cb, 0);
2331 r600_store_value(cb, 0);
2332 r600_store_value(cb, 0);
2333 r600_store_value(cb, 0);
2334 r600_store_value(cb, 0);
2335
2336 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2337 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2338 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2339 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2340 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2341 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2342 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2343 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2344 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2345 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2346 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2347 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2348 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2349 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2350
2351 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2352 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2353 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2354
2355 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2356 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2357 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2358 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2359
2360 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2361
2362 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2363 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2364 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2365
2366 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2367
2368 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2369 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2370 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2371
2372 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2373 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2374 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2375 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2376
2377 r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2378 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2379 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2380
2381 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2382 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2383
2384 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2385 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2386 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2387 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2388 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2389
2390 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2391 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2392 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2393
2394 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2395
2396 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2397 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2398
2399 if (rctx->chip_class >= R700) {
2400 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2401 }
2402
2403 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2404 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2405 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2406 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2407 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2408
2409 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2410 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2411 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2412
2413 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2414 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2415 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2416
2417 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2418 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2419 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2420
2421 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2422 r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2423
2424 if (rctx->chip_class == R700 && rctx->screen->has_streamout)
2425 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2426 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2427 if (rctx->screen->has_streamout) {
2428 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2429 }
2430
2431 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2432 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2433 }
2434
2435 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2436 {
2437 struct r600_context *rctx = (struct r600_context *)ctx;
2438 struct r600_pipe_state *rstate = &shader->rstate;
2439 struct r600_shader *rshader = &shader->shader;
2440 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2441 int pos_index = -1, face_index = -1;
2442 unsigned tmp, sid, ufi = 0;
2443 int need_linear = 0;
2444 unsigned z_export = 0, stencil_export = 0;
2445
2446 rstate->nregs = 0;
2447
2448 for (i = 0; i < rshader->ninput; i++) {
2449 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2450 pos_index = i;
2451 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2452 face_index = i;
2453
2454 sid = rshader->input[i].spi_sid;
2455
2456 tmp = S_028644_SEMANTIC(sid);
2457
2458 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2459 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2460 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2461 rctx->rasterizer && rctx->rasterizer->flatshade))
2462 tmp |= S_028644_FLAT_SHADE(1);
2463
2464 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2465 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2466 tmp |= S_028644_PT_SPRITE_TEX(1);
2467 }
2468
2469 if (rshader->input[i].centroid)
2470 tmp |= S_028644_SEL_CENTROID(1);
2471
2472 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2473 need_linear = 1;
2474 tmp |= S_028644_SEL_LINEAR(1);
2475 }
2476
2477 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2478 tmp);
2479 }
2480
2481 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2482 for (i = 0; i < rshader->noutput; i++) {
2483 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2484 z_export = 1;
2485 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2486 stencil_export = 1;
2487 }
2488 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2489 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2490 if (rshader->uses_kill)
2491 db_shader_control |= S_02880C_KILL_ENABLE(1);
2492
2493 exports_ps = 0;
2494 for (i = 0; i < rshader->noutput; i++) {
2495 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2496 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2497 exports_ps |= 1;
2498 }
2499 }
2500 num_cout = rshader->nr_ps_color_exports;
2501 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2502 if (!exports_ps) {
2503 /* always at least export 1 component per pixel */
2504 exports_ps = 2;
2505 }
2506
2507 shader->nr_ps_color_outputs = num_cout;
2508
2509 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2510 S_0286CC_PERSP_GRADIENT_ENA(1)|
2511 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2512 spi_input_z = 0;
2513 if (pos_index != -1) {
2514 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2515 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2516 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2517 S_0286CC_BARYC_SAMPLE_CNTL(1));
2518 spi_input_z |= 1;
2519 }
2520
2521 spi_ps_in_control_1 = 0;
2522 if (face_index != -1) {
2523 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2524 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2525 }
2526
2527 /* HW bug in original R600 */
2528 if (rctx->family == CHIP_R600)
2529 ufi = 1;
2530
2531 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2532 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2533 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2534 r600_pipe_state_add_reg_bo(rstate,
2535 R_028840_SQ_PGM_START_PS,
2536 0, shader->bo, RADEON_USAGE_READ);
2537 r600_pipe_state_add_reg(rstate,
2538 R_028850_SQ_PGM_RESOURCES_PS,
2539 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2540 S_028850_STACK_SIZE(rshader->bc.nstack) |
2541 S_028850_UNCACHED_FIRST_INST(ufi));
2542 r600_pipe_state_add_reg(rstate,
2543 R_028854_SQ_PGM_EXPORTS_PS,
2544 exports_ps);
2545 /* only set some bits here, the other bits are set in the dsa state */
2546 shader->db_shader_control = db_shader_control;
2547 shader->ps_depth_export = z_export | stencil_export;
2548
2549 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2550 if (rctx->rasterizer)
2551 shader->flatshade = rctx->rasterizer->flatshade;
2552 }
2553
2554 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2555 {
2556 struct r600_context *rctx = (struct r600_context *)ctx;
2557 struct r600_pipe_state *rstate = &shader->rstate;
2558 struct r600_shader *rshader = &shader->shader;
2559 unsigned spi_vs_out_id[10] = {};
2560 unsigned i, tmp, nparams = 0;
2561
2562 /* clear previous register */
2563 rstate->nregs = 0;
2564
2565 for (i = 0; i < rshader->noutput; i++) {
2566 if (rshader->output[i].spi_sid) {
2567 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2568 spi_vs_out_id[nparams / 4] |= tmp;
2569 nparams++;
2570 }
2571 }
2572
2573 for (i = 0; i < 10; i++) {
2574 r600_pipe_state_add_reg(rstate,
2575 R_028614_SPI_VS_OUT_ID_0 + i * 4,
2576 spi_vs_out_id[i]);
2577 }
2578
2579 /* Certain attributes (position, psize, etc.) don't count as params.
2580 * VS is required to export at least one param and r600_shader_from_tgsi()
2581 * takes care of adding a dummy export.
2582 */
2583 if (nparams < 1)
2584 nparams = 1;
2585
2586 r600_pipe_state_add_reg(rstate,
2587 R_0286C4_SPI_VS_OUT_CONFIG,
2588 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2589 r600_pipe_state_add_reg(rstate,
2590 R_028868_SQ_PGM_RESOURCES_VS,
2591 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2592 S_028868_STACK_SIZE(rshader->bc.nstack));
2593 r600_pipe_state_add_reg_bo(rstate,
2594 R_028858_SQ_PGM_START_VS,
2595 0, shader->bo, RADEON_USAGE_READ);
2596
2597 shader->pa_cl_vs_out_cntl =
2598 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2599 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2600 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2601 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2602 }
2603
2604 void r600_fetch_shader(struct pipe_context *ctx,
2605 struct r600_vertex_element *ve)
2606 {
2607 struct r600_pipe_state *rstate;
2608 struct r600_context *rctx = (struct r600_context *)ctx;
2609
2610 rstate = &ve->rstate;
2611 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2612 rstate->nregs = 0;
2613 r600_pipe_state_add_reg_bo(rstate, R_028894_SQ_PGM_START_FS,
2614 0,
2615 ve->fetch_shader, RADEON_USAGE_READ);
2616 }
2617
2618 void *r600_create_resolve_blend(struct r600_context *rctx)
2619 {
2620 struct pipe_blend_state blend;
2621 struct r600_pipe_state *rstate;
2622 unsigned i;
2623
2624 memset(&blend, 0, sizeof(blend));
2625 blend.independent_blend_enable = true;
2626 for (i = 0; i < 2; i++) {
2627 blend.rt[i].colormask = 0xf;
2628 blend.rt[i].blend_enable = 1;
2629 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2630 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2631 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2632 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2633 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2634 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2635 }
2636 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2637 return rstate;
2638 }
2639
2640 void *r700_create_resolve_blend(struct r600_context *rctx)
2641 {
2642 struct pipe_blend_state blend;
2643 struct r600_pipe_state *rstate;
2644
2645 memset(&blend, 0, sizeof(blend));
2646 blend.independent_blend_enable = true;
2647 blend.rt[0].colormask = 0xf;
2648 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2649 return rstate;
2650 }
2651
2652 void *r600_create_decompress_blend(struct r600_context *rctx)
2653 {
2654 struct pipe_blend_state blend;
2655 struct r600_pipe_state *rstate;
2656
2657 memset(&blend, 0, sizeof(blend));
2658 blend.independent_blend_enable = true;
2659 blend.rt[0].colormask = 0xf;
2660 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2661 return rstate;
2662 }
2663
2664 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2665 {
2666 struct pipe_depth_stencil_alpha_state dsa;
2667 boolean quirk = false;
2668
2669 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2670 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2671 quirk = true;
2672
2673 memset(&dsa, 0, sizeof(dsa));
2674
2675 if (quirk) {
2676 dsa.depth.enabled = 1;
2677 dsa.depth.func = PIPE_FUNC_LEQUAL;
2678 dsa.stencil[0].enabled = 1;
2679 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2680 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2681 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2682 dsa.stencil[0].writemask = 0xff;
2683 }
2684
2685 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2686 }
2687
2688 void r600_update_dual_export_state(struct r600_context * rctx)
2689 {
2690 unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
2691 !rctx->ps_shader->current->ps_depth_export;
2692 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2693 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2694
2695 if (db_shader_control != rctx->db_shader_control) {
2696 struct r600_pipe_state rstate;
2697
2698 rctx->db_shader_control = db_shader_control;
2699 rstate.nregs = 0;
2700 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2701 r600_context_pipe_state_set(rctx, &rstate);
2702 }
2703 }