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r600g: use uint64_t instead of unsigned long for proper 32bits cpu support
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static uint32_t r600_translate_colorswap(enum pipe_format format)
145 {
146 switch (format) {
147 /* 8-bit buffers. */
148 case PIPE_FORMAT_A8_UNORM:
149 case PIPE_FORMAT_A8_SNORM:
150 case PIPE_FORMAT_A8_UINT:
151 case PIPE_FORMAT_A8_SINT:
152 case PIPE_FORMAT_A16_UNORM:
153 case PIPE_FORMAT_A16_SNORM:
154 case PIPE_FORMAT_A16_UINT:
155 case PIPE_FORMAT_A16_SINT:
156 case PIPE_FORMAT_A16_FLOAT:
157 case PIPE_FORMAT_A32_UINT:
158 case PIPE_FORMAT_A32_SINT:
159 case PIPE_FORMAT_A32_FLOAT:
160 case PIPE_FORMAT_R4A4_UNORM:
161 return V_0280A0_SWAP_ALT_REV;
162 case PIPE_FORMAT_I8_UNORM:
163 case PIPE_FORMAT_I8_SNORM:
164 case PIPE_FORMAT_I8_UINT:
165 case PIPE_FORMAT_I8_SINT:
166 case PIPE_FORMAT_L8_UNORM:
167 case PIPE_FORMAT_L8_SNORM:
168 case PIPE_FORMAT_L8_UINT:
169 case PIPE_FORMAT_L8_SINT:
170 case PIPE_FORMAT_L8_SRGB:
171 case PIPE_FORMAT_L16_UNORM:
172 case PIPE_FORMAT_L16_SNORM:
173 case PIPE_FORMAT_L16_UINT:
174 case PIPE_FORMAT_L16_SINT:
175 case PIPE_FORMAT_L16_FLOAT:
176 case PIPE_FORMAT_L32_UINT:
177 case PIPE_FORMAT_L32_SINT:
178 case PIPE_FORMAT_L32_FLOAT:
179 case PIPE_FORMAT_I16_UNORM:
180 case PIPE_FORMAT_I16_SNORM:
181 case PIPE_FORMAT_I16_UINT:
182 case PIPE_FORMAT_I16_SINT:
183 case PIPE_FORMAT_I16_FLOAT:
184 case PIPE_FORMAT_I32_UINT:
185 case PIPE_FORMAT_I32_SINT:
186 case PIPE_FORMAT_I32_FLOAT:
187 case PIPE_FORMAT_R8_UNORM:
188 case PIPE_FORMAT_R8_SNORM:
189 case PIPE_FORMAT_R8_UINT:
190 case PIPE_FORMAT_R8_SINT:
191 return V_0280A0_SWAP_STD;
192
193 case PIPE_FORMAT_L4A4_UNORM:
194 case PIPE_FORMAT_A4R4_UNORM:
195 return V_0280A0_SWAP_ALT;
196
197 /* 16-bit buffers. */
198 case PIPE_FORMAT_B5G6R5_UNORM:
199 return V_0280A0_SWAP_STD_REV;
200
201 case PIPE_FORMAT_B5G5R5A1_UNORM:
202 case PIPE_FORMAT_B5G5R5X1_UNORM:
203 return V_0280A0_SWAP_ALT;
204
205 case PIPE_FORMAT_B4G4R4A4_UNORM:
206 case PIPE_FORMAT_B4G4R4X4_UNORM:
207 return V_0280A0_SWAP_ALT;
208
209 case PIPE_FORMAT_Z16_UNORM:
210 return V_0280A0_SWAP_STD;
211
212 case PIPE_FORMAT_L8A8_UNORM:
213 case PIPE_FORMAT_L8A8_SNORM:
214 case PIPE_FORMAT_L8A8_UINT:
215 case PIPE_FORMAT_L8A8_SINT:
216 case PIPE_FORMAT_L8A8_SRGB:
217 case PIPE_FORMAT_L16A16_UNORM:
218 case PIPE_FORMAT_L16A16_SNORM:
219 case PIPE_FORMAT_L16A16_UINT:
220 case PIPE_FORMAT_L16A16_SINT:
221 case PIPE_FORMAT_L16A16_FLOAT:
222 case PIPE_FORMAT_L32A32_UINT:
223 case PIPE_FORMAT_L32A32_SINT:
224 case PIPE_FORMAT_L32A32_FLOAT:
225 return V_0280A0_SWAP_ALT;
226 case PIPE_FORMAT_R8G8_UNORM:
227 case PIPE_FORMAT_R8G8_SNORM:
228 case PIPE_FORMAT_R8G8_UINT:
229 case PIPE_FORMAT_R8G8_SINT:
230 return V_0280A0_SWAP_STD;
231
232 case PIPE_FORMAT_R16_UNORM:
233 case PIPE_FORMAT_R16_SNORM:
234 case PIPE_FORMAT_R16_UINT:
235 case PIPE_FORMAT_R16_SINT:
236 case PIPE_FORMAT_R16_FLOAT:
237 return V_0280A0_SWAP_STD;
238
239 /* 32-bit buffers. */
240
241 case PIPE_FORMAT_A8B8G8R8_SRGB:
242 return V_0280A0_SWAP_STD_REV;
243 case PIPE_FORMAT_B8G8R8A8_SRGB:
244 return V_0280A0_SWAP_ALT;
245
246 case PIPE_FORMAT_B8G8R8A8_UNORM:
247 case PIPE_FORMAT_B8G8R8X8_UNORM:
248 return V_0280A0_SWAP_ALT;
249
250 case PIPE_FORMAT_A8R8G8B8_UNORM:
251 case PIPE_FORMAT_X8R8G8B8_UNORM:
252 return V_0280A0_SWAP_ALT_REV;
253 case PIPE_FORMAT_R8G8B8A8_SNORM:
254 case PIPE_FORMAT_R8G8B8A8_UNORM:
255 case PIPE_FORMAT_R8G8B8X8_UNORM:
256 case PIPE_FORMAT_R8G8B8A8_SINT:
257 case PIPE_FORMAT_R8G8B8A8_UINT:
258 return V_0280A0_SWAP_STD;
259
260 case PIPE_FORMAT_A8B8G8R8_UNORM:
261 case PIPE_FORMAT_X8B8G8R8_UNORM:
262 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
263 return V_0280A0_SWAP_STD_REV;
264
265 case PIPE_FORMAT_Z24X8_UNORM:
266 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
267 return V_0280A0_SWAP_STD;
268
269 case PIPE_FORMAT_X8Z24_UNORM:
270 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
271 return V_0280A0_SWAP_STD;
272
273 case PIPE_FORMAT_R10G10B10A2_UNORM:
274 case PIPE_FORMAT_R10G10B10X2_SNORM:
275 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
276 return V_0280A0_SWAP_STD;
277
278 case PIPE_FORMAT_B10G10R10A2_UNORM:
279 case PIPE_FORMAT_B10G10R10A2_UINT:
280 return V_0280A0_SWAP_ALT;
281
282 case PIPE_FORMAT_R11G11B10_FLOAT:
283 case PIPE_FORMAT_R16G16_UNORM:
284 case PIPE_FORMAT_R16G16_SNORM:
285 case PIPE_FORMAT_R16G16_FLOAT:
286 case PIPE_FORMAT_R16G16_UINT:
287 case PIPE_FORMAT_R16G16_SINT:
288 case PIPE_FORMAT_R32_UINT:
289 case PIPE_FORMAT_R32_SINT:
290 case PIPE_FORMAT_R32_FLOAT:
291 case PIPE_FORMAT_Z32_FLOAT:
292 return V_0280A0_SWAP_STD;
293
294 /* 64-bit buffers. */
295 case PIPE_FORMAT_R32G32_FLOAT:
296 case PIPE_FORMAT_R32G32_UINT:
297 case PIPE_FORMAT_R32G32_SINT:
298 case PIPE_FORMAT_R16G16B16A16_UNORM:
299 case PIPE_FORMAT_R16G16B16A16_SNORM:
300 case PIPE_FORMAT_R16G16B16A16_UINT:
301 case PIPE_FORMAT_R16G16B16A16_SINT:
302 case PIPE_FORMAT_R16G16B16A16_FLOAT:
303 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
304
305 /* 128-bit buffers. */
306 case PIPE_FORMAT_R32G32B32A32_FLOAT:
307 case PIPE_FORMAT_R32G32B32A32_SNORM:
308 case PIPE_FORMAT_R32G32B32A32_UNORM:
309 case PIPE_FORMAT_R32G32B32A32_SINT:
310 case PIPE_FORMAT_R32G32B32A32_UINT:
311 return V_0280A0_SWAP_STD;
312 default:
313 R600_ERR("unsupported colorswap format %d\n", format);
314 return ~0U;
315 }
316 return ~0U;
317 }
318
319 static uint32_t r600_translate_colorformat(enum pipe_format format)
320 {
321 switch (format) {
322 case PIPE_FORMAT_L4A4_UNORM:
323 case PIPE_FORMAT_R4A4_UNORM:
324 case PIPE_FORMAT_A4R4_UNORM:
325 return V_0280A0_COLOR_4_4;
326
327 /* 8-bit buffers. */
328 case PIPE_FORMAT_A8_UNORM:
329 case PIPE_FORMAT_A8_SNORM:
330 case PIPE_FORMAT_A8_UINT:
331 case PIPE_FORMAT_A8_SINT:
332 case PIPE_FORMAT_I8_UNORM:
333 case PIPE_FORMAT_I8_SNORM:
334 case PIPE_FORMAT_I8_UINT:
335 case PIPE_FORMAT_I8_SINT:
336 case PIPE_FORMAT_L8_UNORM:
337 case PIPE_FORMAT_L8_SNORM:
338 case PIPE_FORMAT_L8_UINT:
339 case PIPE_FORMAT_L8_SINT:
340 case PIPE_FORMAT_L8_SRGB:
341 case PIPE_FORMAT_R8_UNORM:
342 case PIPE_FORMAT_R8_SNORM:
343 case PIPE_FORMAT_R8_UINT:
344 case PIPE_FORMAT_R8_SINT:
345 return V_0280A0_COLOR_8;
346
347 /* 16-bit buffers. */
348 case PIPE_FORMAT_B5G6R5_UNORM:
349 return V_0280A0_COLOR_5_6_5;
350
351 case PIPE_FORMAT_B5G5R5A1_UNORM:
352 case PIPE_FORMAT_B5G5R5X1_UNORM:
353 return V_0280A0_COLOR_1_5_5_5;
354
355 case PIPE_FORMAT_B4G4R4A4_UNORM:
356 case PIPE_FORMAT_B4G4R4X4_UNORM:
357 return V_0280A0_COLOR_4_4_4_4;
358
359 case PIPE_FORMAT_Z16_UNORM:
360 return V_0280A0_COLOR_16;
361
362 case PIPE_FORMAT_L8A8_UNORM:
363 case PIPE_FORMAT_L8A8_SNORM:
364 case PIPE_FORMAT_L8A8_UINT:
365 case PIPE_FORMAT_L8A8_SINT:
366 case PIPE_FORMAT_L8A8_SRGB:
367 case PIPE_FORMAT_R8G8_UNORM:
368 case PIPE_FORMAT_R8G8_SNORM:
369 case PIPE_FORMAT_R8G8_UINT:
370 case PIPE_FORMAT_R8G8_SINT:
371 return V_0280A0_COLOR_8_8;
372
373 case PIPE_FORMAT_R16_UNORM:
374 case PIPE_FORMAT_R16_SNORM:
375 case PIPE_FORMAT_R16_UINT:
376 case PIPE_FORMAT_R16_SINT:
377 case PIPE_FORMAT_A16_UNORM:
378 case PIPE_FORMAT_A16_SNORM:
379 case PIPE_FORMAT_A16_UINT:
380 case PIPE_FORMAT_A16_SINT:
381 case PIPE_FORMAT_L16_UNORM:
382 case PIPE_FORMAT_L16_SNORM:
383 case PIPE_FORMAT_L16_UINT:
384 case PIPE_FORMAT_L16_SINT:
385 case PIPE_FORMAT_I16_UNORM:
386 case PIPE_FORMAT_I16_SNORM:
387 case PIPE_FORMAT_I16_UINT:
388 case PIPE_FORMAT_I16_SINT:
389 return V_0280A0_COLOR_16;
390
391 case PIPE_FORMAT_R16_FLOAT:
392 case PIPE_FORMAT_A16_FLOAT:
393 case PIPE_FORMAT_L16_FLOAT:
394 case PIPE_FORMAT_I16_FLOAT:
395 return V_0280A0_COLOR_16_FLOAT;
396
397 /* 32-bit buffers. */
398 case PIPE_FORMAT_A8B8G8R8_SRGB:
399 case PIPE_FORMAT_A8B8G8R8_UNORM:
400 case PIPE_FORMAT_A8R8G8B8_UNORM:
401 case PIPE_FORMAT_B8G8R8A8_SRGB:
402 case PIPE_FORMAT_B8G8R8A8_UNORM:
403 case PIPE_FORMAT_B8G8R8X8_UNORM:
404 case PIPE_FORMAT_R8G8B8A8_SNORM:
405 case PIPE_FORMAT_R8G8B8A8_UNORM:
406 case PIPE_FORMAT_R8G8B8X8_UNORM:
407 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
408 case PIPE_FORMAT_X8B8G8R8_UNORM:
409 case PIPE_FORMAT_X8R8G8B8_UNORM:
410 case PIPE_FORMAT_R8G8B8A8_SINT:
411 case PIPE_FORMAT_R8G8B8A8_UINT:
412 return V_0280A0_COLOR_8_8_8_8;
413
414 case PIPE_FORMAT_R10G10B10A2_UNORM:
415 case PIPE_FORMAT_R10G10B10X2_SNORM:
416 case PIPE_FORMAT_B10G10R10A2_UNORM:
417 case PIPE_FORMAT_B10G10R10A2_UINT:
418 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
419 return V_0280A0_COLOR_2_10_10_10;
420
421 case PIPE_FORMAT_Z24X8_UNORM:
422 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
423 return V_0280A0_COLOR_8_24;
424
425 case PIPE_FORMAT_X8Z24_UNORM:
426 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
427 return V_0280A0_COLOR_24_8;
428
429 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
430 return V_0280A0_COLOR_X24_8_32_FLOAT;
431
432 case PIPE_FORMAT_R32_UINT:
433 case PIPE_FORMAT_R32_SINT:
434 case PIPE_FORMAT_A32_UINT:
435 case PIPE_FORMAT_A32_SINT:
436 case PIPE_FORMAT_L32_UINT:
437 case PIPE_FORMAT_L32_SINT:
438 case PIPE_FORMAT_I32_UINT:
439 case PIPE_FORMAT_I32_SINT:
440 return V_0280A0_COLOR_32;
441
442 case PIPE_FORMAT_R32_FLOAT:
443 case PIPE_FORMAT_A32_FLOAT:
444 case PIPE_FORMAT_L32_FLOAT:
445 case PIPE_FORMAT_I32_FLOAT:
446 case PIPE_FORMAT_Z32_FLOAT:
447 return V_0280A0_COLOR_32_FLOAT;
448
449 case PIPE_FORMAT_R16G16_FLOAT:
450 case PIPE_FORMAT_L16A16_FLOAT:
451 return V_0280A0_COLOR_16_16_FLOAT;
452
453 case PIPE_FORMAT_R16G16_UNORM:
454 case PIPE_FORMAT_R16G16_SNORM:
455 case PIPE_FORMAT_R16G16_UINT:
456 case PIPE_FORMAT_R16G16_SINT:
457 case PIPE_FORMAT_L16A16_UNORM:
458 case PIPE_FORMAT_L16A16_SNORM:
459 case PIPE_FORMAT_L16A16_UINT:
460 case PIPE_FORMAT_L16A16_SINT:
461 return V_0280A0_COLOR_16_16;
462
463 case PIPE_FORMAT_R11G11B10_FLOAT:
464 return V_0280A0_COLOR_10_11_11_FLOAT;
465
466 /* 64-bit buffers. */
467 case PIPE_FORMAT_R16G16B16A16_UINT:
468 case PIPE_FORMAT_R16G16B16A16_SINT:
469 case PIPE_FORMAT_R16G16B16A16_UNORM:
470 case PIPE_FORMAT_R16G16B16A16_SNORM:
471 return V_0280A0_COLOR_16_16_16_16;
472
473 case PIPE_FORMAT_R16G16B16A16_FLOAT:
474 return V_0280A0_COLOR_16_16_16_16_FLOAT;
475
476 case PIPE_FORMAT_R32G32_FLOAT:
477 case PIPE_FORMAT_L32A32_FLOAT:
478 return V_0280A0_COLOR_32_32_FLOAT;
479
480 case PIPE_FORMAT_R32G32_SINT:
481 case PIPE_FORMAT_R32G32_UINT:
482 case PIPE_FORMAT_L32A32_UINT:
483 case PIPE_FORMAT_L32A32_SINT:
484 return V_0280A0_COLOR_32_32;
485
486 /* 128-bit buffers. */
487 case PIPE_FORMAT_R32G32B32A32_FLOAT:
488 return V_0280A0_COLOR_32_32_32_32_FLOAT;
489 case PIPE_FORMAT_R32G32B32A32_SNORM:
490 case PIPE_FORMAT_R32G32B32A32_UNORM:
491 case PIPE_FORMAT_R32G32B32A32_SINT:
492 case PIPE_FORMAT_R32G32B32A32_UINT:
493 return V_0280A0_COLOR_32_32_32_32;
494
495 /* YUV buffers. */
496 case PIPE_FORMAT_UYVY:
497 case PIPE_FORMAT_YUYV:
498 default:
499 return ~0U; /* Unsupported. */
500 }
501 }
502
503 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
504 {
505 if (R600_BIG_ENDIAN) {
506 switch(colorformat) {
507 case V_0280A0_COLOR_4_4:
508 return ENDIAN_NONE;
509
510 /* 8-bit buffers. */
511 case V_0280A0_COLOR_8:
512 return ENDIAN_NONE;
513
514 /* 16-bit buffers. */
515 case V_0280A0_COLOR_5_6_5:
516 case V_0280A0_COLOR_1_5_5_5:
517 case V_0280A0_COLOR_4_4_4_4:
518 case V_0280A0_COLOR_16:
519 case V_0280A0_COLOR_8_8:
520 return ENDIAN_8IN16;
521
522 /* 32-bit buffers. */
523 case V_0280A0_COLOR_8_8_8_8:
524 case V_0280A0_COLOR_2_10_10_10:
525 case V_0280A0_COLOR_8_24:
526 case V_0280A0_COLOR_24_8:
527 case V_0280A0_COLOR_32_FLOAT:
528 case V_0280A0_COLOR_16_16_FLOAT:
529 case V_0280A0_COLOR_16_16:
530 return ENDIAN_8IN32;
531
532 /* 64-bit buffers. */
533 case V_0280A0_COLOR_16_16_16_16:
534 case V_0280A0_COLOR_16_16_16_16_FLOAT:
535 return ENDIAN_8IN16;
536
537 case V_0280A0_COLOR_32_32_FLOAT:
538 case V_0280A0_COLOR_32_32:
539 case V_0280A0_COLOR_X24_8_32_FLOAT:
540 return ENDIAN_8IN32;
541
542 /* 128-bit buffers. */
543 case V_0280A0_COLOR_32_32_32_FLOAT:
544 case V_0280A0_COLOR_32_32_32_32_FLOAT:
545 case V_0280A0_COLOR_32_32_32_32:
546 return ENDIAN_8IN32;
547 default:
548 return ENDIAN_NONE; /* Unsupported. */
549 }
550 } else {
551 return ENDIAN_NONE;
552 }
553 }
554
555 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
556 {
557 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
558 }
559
560 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
561 {
562 return r600_translate_colorformat(format) != ~0U &&
563 r600_translate_colorswap(format) != ~0U;
564 }
565
566 static bool r600_is_zs_format_supported(enum pipe_format format)
567 {
568 return r600_translate_dbformat(format) != ~0U;
569 }
570
571 boolean r600_is_format_supported(struct pipe_screen *screen,
572 enum pipe_format format,
573 enum pipe_texture_target target,
574 unsigned sample_count,
575 unsigned usage)
576 {
577 struct r600_screen *rscreen = (struct r600_screen*)screen;
578 unsigned retval = 0;
579
580 if (target >= PIPE_MAX_TEXTURE_TYPES) {
581 R600_ERR("r600: unsupported texture type %d\n", target);
582 return FALSE;
583 }
584
585 if (!util_format_is_supported(format, usage))
586 return FALSE;
587
588 if (sample_count > 1) {
589 if (!rscreen->has_msaa)
590 return FALSE;
591
592 /* R11G11B10 is broken on R6xx. */
593 if (rscreen->chip_class == R600 &&
594 format == PIPE_FORMAT_R11G11B10_FLOAT)
595 return FALSE;
596
597 /* MSAA integer colorbuffers hang. */
598 if (util_format_is_pure_integer(format) &&
599 !util_format_is_depth_or_stencil(format))
600 return FALSE;
601
602 switch (sample_count) {
603 case 2:
604 case 4:
605 case 8:
606 break;
607 default:
608 return FALSE;
609 }
610 }
611
612 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
613 r600_is_sampler_format_supported(screen, format)) {
614 retval |= PIPE_BIND_SAMPLER_VIEW;
615 }
616
617 if ((usage & (PIPE_BIND_RENDER_TARGET |
618 PIPE_BIND_DISPLAY_TARGET |
619 PIPE_BIND_SCANOUT |
620 PIPE_BIND_SHARED)) &&
621 r600_is_colorbuffer_format_supported(format)) {
622 retval |= usage &
623 (PIPE_BIND_RENDER_TARGET |
624 PIPE_BIND_DISPLAY_TARGET |
625 PIPE_BIND_SCANOUT |
626 PIPE_BIND_SHARED);
627 }
628
629 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
630 r600_is_zs_format_supported(format)) {
631 retval |= PIPE_BIND_DEPTH_STENCIL;
632 }
633
634 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
635 r600_is_vertex_format_supported(format)) {
636 retval |= PIPE_BIND_VERTEX_BUFFER;
637 }
638
639 if (usage & PIPE_BIND_TRANSFER_READ)
640 retval |= PIPE_BIND_TRANSFER_READ;
641 if (usage & PIPE_BIND_TRANSFER_WRITE)
642 retval |= PIPE_BIND_TRANSFER_WRITE;
643
644 return retval == usage;
645 }
646
647 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
648 {
649 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
650 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
651 float offset_units = state->offset_units;
652 float offset_scale = state->offset_scale;
653
654 switch (state->zs_format) {
655 case PIPE_FORMAT_Z24X8_UNORM:
656 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
657 offset_units *= 2.0f;
658 break;
659 case PIPE_FORMAT_Z16_UNORM:
660 offset_units *= 4.0f;
661 break;
662 default:;
663 }
664
665 r600_write_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
666 r600_write_value(cs, fui(offset_scale));
667 r600_write_value(cs, fui(offset_units));
668 r600_write_value(cs, fui(offset_scale));
669 r600_write_value(cs, fui(offset_units));
670 }
671
672 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
673 {
674 int j = state->independent_blend_enable ? i : 0;
675
676 unsigned eqRGB = state->rt[j].rgb_func;
677 unsigned srcRGB = state->rt[j].rgb_src_factor;
678 unsigned dstRGB = state->rt[j].rgb_dst_factor;
679
680 unsigned eqA = state->rt[j].alpha_func;
681 unsigned srcA = state->rt[j].alpha_src_factor;
682 unsigned dstA = state->rt[j].alpha_dst_factor;
683 uint32_t bc = 0;
684
685 if (!state->rt[j].blend_enable)
686 return 0;
687
688 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
689 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
690 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
691
692 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
693 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
694 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
695 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
696 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
697 }
698 return bc;
699 }
700
701 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
702 const struct pipe_blend_state *state,
703 int mode)
704 {
705 struct r600_context *rctx = (struct r600_context *)ctx;
706 uint32_t color_control = 0, target_mask = 0;
707 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
708
709 if (!blend) {
710 return NULL;
711 }
712
713 r600_init_command_buffer(&blend->buffer, 20);
714 r600_init_command_buffer(&blend->buffer_no_blend, 20);
715
716 /* R600 does not support per-MRT blends */
717 if (rctx->family > CHIP_R600)
718 color_control |= S_028808_PER_MRT_BLEND(1);
719
720 if (state->logicop_enable) {
721 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
722 } else {
723 color_control |= (0xcc << 16);
724 }
725 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
726 if (state->independent_blend_enable) {
727 for (int i = 0; i < 8; i++) {
728 if (state->rt[i].blend_enable) {
729 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
730 }
731 target_mask |= (state->rt[i].colormask << (4 * i));
732 }
733 } else {
734 for (int i = 0; i < 8; i++) {
735 if (state->rt[0].blend_enable) {
736 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
737 }
738 target_mask |= (state->rt[0].colormask << (4 * i));
739 }
740 }
741
742 if (target_mask)
743 color_control |= S_028808_SPECIAL_OP(mode);
744 else
745 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
746
747 /* only MRT0 has dual src blend */
748 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
749 blend->cb_target_mask = target_mask;
750 blend->cb_color_control = color_control;
751 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
752 blend->alpha_to_one = state->alpha_to_one;
753
754 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
755 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
756 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
757 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
758 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
759 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
760
761 /* Copy over the registers set so far into buffer_no_blend. */
762 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
763 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
764
765 /* Only add blend registers if blending is enabled. */
766 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
767 return blend;
768 }
769
770 /* The first R600 does not support per-MRT blends */
771 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
772 r600_get_blend_control(state, 0));
773
774 if (rctx->family > CHIP_R600) {
775 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
776 for (int i = 0; i < 8; i++) {
777 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
778 }
779 }
780 return blend;
781 }
782
783 static void *r600_create_blend_state(struct pipe_context *ctx,
784 const struct pipe_blend_state *state)
785 {
786 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
787 }
788
789 static void *r600_create_dsa_state(struct pipe_context *ctx,
790 const struct pipe_depth_stencil_alpha_state *state)
791 {
792 unsigned db_depth_control, alpha_test_control, alpha_ref;
793 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
794
795 if (dsa == NULL) {
796 return NULL;
797 }
798
799 r600_init_command_buffer(&dsa->buffer, 3);
800
801 dsa->valuemask[0] = state->stencil[0].valuemask;
802 dsa->valuemask[1] = state->stencil[1].valuemask;
803 dsa->writemask[0] = state->stencil[0].writemask;
804 dsa->writemask[1] = state->stencil[1].writemask;
805
806 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
807 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
808 S_028800_ZFUNC(state->depth.func);
809
810 /* stencil */
811 if (state->stencil[0].enabled) {
812 db_depth_control |= S_028800_STENCIL_ENABLE(1);
813 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
814 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
815 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
816 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
817
818 if (state->stencil[1].enabled) {
819 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
820 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
821 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
822 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
823 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
824 }
825 }
826
827 /* alpha */
828 alpha_test_control = 0;
829 alpha_ref = 0;
830 if (state->alpha.enabled) {
831 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
832 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
833 alpha_ref = fui(state->alpha.ref_value);
834 }
835 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
836 dsa->alpha_ref = alpha_ref;
837
838 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
839 return dsa;
840 }
841
842 static void *r600_create_rs_state(struct pipe_context *ctx,
843 const struct pipe_rasterizer_state *state)
844 {
845 struct r600_context *rctx = (struct r600_context *)ctx;
846 unsigned tmp, sc_mode_cntl, spi_interp;
847 float psize_min, psize_max;
848 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
849
850 if (rs == NULL) {
851 return NULL;
852 }
853
854 r600_init_command_buffer(&rs->buffer, 30);
855
856 rs->flatshade = state->flatshade;
857 rs->sprite_coord_enable = state->sprite_coord_enable;
858 rs->two_side = state->light_twoside;
859 rs->clip_plane_enable = state->clip_plane_enable;
860 rs->pa_sc_line_stipple = state->line_stipple_enable ?
861 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
862 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
863 rs->pa_cl_clip_cntl =
864 S_028810_PS_UCP_MODE(3) |
865 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
866 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
867 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
868 rs->multisample_enable = state->multisample;
869
870 /* offset */
871 rs->offset_units = state->offset_units;
872 rs->offset_scale = state->offset_scale * 12.0f;
873 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
874
875 if (state->point_size_per_vertex) {
876 psize_min = util_get_min_point_size(state);
877 psize_max = 8192;
878 } else {
879 /* Force the point size to be as if the vertex output was disabled. */
880 psize_min = state->point_size;
881 psize_max = state->point_size;
882 }
883
884 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
885 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
886 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
887 if (rctx->chip_class >= R700) {
888 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
889 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
890 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
891 } else {
892 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
893 rs->scissor_enable = state->scissor;
894 }
895
896 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
897 if (state->sprite_coord_enable) {
898 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
899 S_0286D4_PNT_SPRITE_OVRD_X(2) |
900 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
901 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
902 S_0286D4_PNT_SPRITE_OVRD_W(1);
903 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
904 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
905 }
906 }
907
908 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
909 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
910 tmp = r600_pack_float_12p4(state->point_size/2);
911 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
912 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
913 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
914 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
915 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
916 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
917 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
918
919 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
920 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
921 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
922 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
923 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
924 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
925 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
926 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
927 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
928 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
929 S_028814_FACE(!state->front_ccw) |
930 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
931 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
932 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
933 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
934 state->fill_back != PIPE_POLYGON_MODE_FILL) |
935 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
936 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
937 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
938 return rs;
939 }
940
941 static void *r600_create_sampler_state(struct pipe_context *ctx,
942 const struct pipe_sampler_state *state)
943 {
944 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
945 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
946
947 if (ss == NULL) {
948 return NULL;
949 }
950
951 ss->seamless_cube_map = state->seamless_cube_map;
952 ss->border_color_use = sampler_state_needs_border_color(state);
953
954 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
955 ss->tex_sampler_words[0] =
956 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
957 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
958 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
959 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
960 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
961 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
962 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
963 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
964 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
965 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
966 ss->tex_sampler_words[1] =
967 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
968 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
969 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
970 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
971 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
972
973 if (ss->border_color_use) {
974 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
975 }
976 return ss;
977 }
978
979 static struct pipe_sampler_view *
980 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
981 unsigned width0, unsigned height0)
982
983 {
984 struct pipe_context *ctx = view->base.context;
985 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
986 uint64_t va;
987 int stride = util_format_get_blocksize(view->base.format);
988 unsigned format, num_format, format_comp, endian;
989
990 r600_vertex_data_type(view->base.format,
991 &format, &num_format, &format_comp,
992 &endian);
993
994 va = r600_resource_va(ctx->screen, view->base.texture);
995 view->tex_resource = &tmp->resource;
996
997 view->skip_mip_address_reloc = true;
998 view->tex_resource_words[0] = va;
999 view->tex_resource_words[1] = width0 - 1;
1000 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(va >> 32UL) |
1001 S_038008_STRIDE(stride) |
1002 S_038008_DATA_FORMAT(format) |
1003 S_038008_NUM_FORMAT_ALL(num_format) |
1004 S_038008_FORMAT_COMP_ALL(format_comp) |
1005 S_038008_SRF_MODE_ALL(1) |
1006 S_038008_ENDIAN_SWAP(endian);
1007 view->tex_resource_words[3] = 0;
1008 /*
1009 * in theory dword 4 is for number of elements, for use with resinfo,
1010 * but it seems to utterly fail to work, the amd gpu shader analyser
1011 * uses a const buffer to store the element sizes for buffer txq
1012 */
1013 view->tex_resource_words[4] = 0;
1014 view->tex_resource_words[5] = 0;
1015 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
1016 return &view->base;
1017 }
1018
1019 struct pipe_sampler_view *
1020 r600_create_sampler_view_custom(struct pipe_context *ctx,
1021 struct pipe_resource *texture,
1022 const struct pipe_sampler_view *state,
1023 unsigned width_first_level, unsigned height_first_level)
1024 {
1025 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1026 struct r600_texture *tmp = (struct r600_texture*)texture;
1027 unsigned format, endian;
1028 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1029 unsigned char swizzle[4], array_mode = 0;
1030 unsigned width, height, depth, offset_level, last_level;
1031
1032 if (view == NULL)
1033 return NULL;
1034
1035 /* initialize base object */
1036 view->base = *state;
1037 view->base.texture = NULL;
1038 pipe_reference(NULL, &texture->reference);
1039 view->base.texture = texture;
1040 view->base.reference.count = 1;
1041 view->base.context = ctx;
1042
1043 if (texture->target == PIPE_BUFFER)
1044 return texture_buffer_sampler_view(view, texture->width0, 1);
1045
1046 swizzle[0] = state->swizzle_r;
1047 swizzle[1] = state->swizzle_g;
1048 swizzle[2] = state->swizzle_b;
1049 swizzle[3] = state->swizzle_a;
1050
1051 format = r600_translate_texformat(ctx->screen, state->format,
1052 swizzle,
1053 &word4, &yuv_format);
1054 assert(format != ~0);
1055 if (format == ~0) {
1056 FREE(view);
1057 return NULL;
1058 }
1059
1060 if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) {
1061 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1062 FREE(view);
1063 return NULL;
1064 }
1065 tmp = tmp->flushed_depth_texture;
1066 }
1067
1068 endian = r600_colorformat_endian_swap(format);
1069
1070 offset_level = state->u.tex.first_level;
1071 last_level = state->u.tex.last_level - offset_level;
1072 width = width_first_level;
1073 height = height_first_level;
1074 depth = u_minify(texture->depth0, offset_level);
1075 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1076
1077 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1078 height = 1;
1079 depth = texture->array_size;
1080 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1081 depth = texture->array_size;
1082 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
1083 depth = texture->array_size / 6;
1084 switch (tmp->surface.level[offset_level].mode) {
1085 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1086 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1087 break;
1088 case RADEON_SURF_MODE_1D:
1089 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1090 break;
1091 case RADEON_SURF_MODE_2D:
1092 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1093 break;
1094 case RADEON_SURF_MODE_LINEAR:
1095 default:
1096 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1097 break;
1098 }
1099
1100 view->tex_resource = &tmp->resource;
1101 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1102 S_038000_TILE_MODE(array_mode) |
1103 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
1104 S_038000_PITCH((pitch / 8) - 1) |
1105 S_038000_TEX_WIDTH(width - 1));
1106 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
1107 S_038004_TEX_DEPTH(depth - 1) |
1108 S_038004_DATA_FORMAT(format));
1109 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
1110 if (offset_level >= tmp->surface.last_level) {
1111 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
1112 } else {
1113 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1114 }
1115 view->tex_resource_words[4] = (word4 |
1116 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1117 S_038010_REQUEST_SIZE(1) |
1118 S_038010_ENDIAN_SWAP(endian) |
1119 S_038010_BASE_LEVEL(0));
1120 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1121 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1122 if (texture->nr_samples > 1) {
1123 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1124 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
1125 } else {
1126 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
1127 }
1128 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1129 S_038018_MAX_ANISO(4 /* max 16 samples */));
1130 return &view->base;
1131 }
1132
1133 static struct pipe_sampler_view *
1134 r600_create_sampler_view(struct pipe_context *ctx,
1135 struct pipe_resource *tex,
1136 const struct pipe_sampler_view *state)
1137 {
1138 return r600_create_sampler_view_custom(ctx, tex, state,
1139 u_minify(tex->width0, state->u.tex.first_level),
1140 u_minify(tex->height0, state->u.tex.first_level));
1141 }
1142
1143 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1144 {
1145 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1146 struct pipe_clip_state *state = &rctx->clip_state.state;
1147
1148 r600_write_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
1149 r600_write_array(cs, 6*4, (unsigned*)state);
1150 }
1151
1152 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1153 const struct pipe_poly_stipple *state)
1154 {
1155 }
1156
1157 static void r600_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
1158 {
1159 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1160 struct pipe_scissor_state *state = &rctx->scissor.scissor;
1161
1162 if (rctx->chip_class != R600 || rctx->scissor.enable) {
1163 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1164 r600_write_value(cs, S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) |
1165 S_028240_WINDOW_OFFSET_DISABLE(1));
1166 r600_write_value(cs, S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy));
1167 } else {
1168 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1169 r600_write_value(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1170 S_028240_WINDOW_OFFSET_DISABLE(1));
1171 r600_write_value(cs, S_028244_BR_X(8192) | S_028244_BR_Y(8192));
1172 }
1173 }
1174
1175 static void r600_set_scissor_state(struct pipe_context *ctx,
1176 const struct pipe_scissor_state *state)
1177 {
1178 struct r600_context *rctx = (struct r600_context *)ctx;
1179
1180 rctx->scissor.scissor = *state;
1181
1182 if (rctx->chip_class == R600 && !rctx->scissor.enable)
1183 return;
1184
1185 rctx->scissor.atom.dirty = true;
1186 }
1187
1188 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
1189 unsigned size, unsigned alignment)
1190 {
1191 struct pipe_resource buffer;
1192
1193 memset(&buffer, 0, sizeof buffer);
1194 buffer.target = PIPE_BUFFER;
1195 buffer.format = PIPE_FORMAT_R8_UNORM;
1196 buffer.bind = PIPE_BIND_CUSTOM;
1197 buffer.usage = PIPE_USAGE_STATIC;
1198 buffer.flags = 0;
1199 buffer.width0 = size;
1200 buffer.height0 = 1;
1201 buffer.depth0 = 1;
1202 buffer.array_size = 1;
1203
1204 return (struct r600_resource*)
1205 r600_buffer_create(&rscreen->screen, &buffer, alignment);
1206 }
1207
1208 static void r600_init_color_surface(struct r600_context *rctx,
1209 struct r600_surface *surf,
1210 bool force_cmask_fmask)
1211 {
1212 struct r600_screen *rscreen = rctx->screen;
1213 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1214 unsigned level = surf->base.u.tex.level;
1215 unsigned pitch, slice;
1216 unsigned color_info;
1217 unsigned format, swap, ntype, endian;
1218 unsigned offset;
1219 const struct util_format_description *desc;
1220 int i;
1221 bool blend_bypass = 0, blend_clamp = 1;
1222
1223 if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
1224 r600_init_flushed_depth_texture(&rctx->context, surf->base.texture, NULL);
1225 rtex = rtex->flushed_depth_texture;
1226 assert(rtex);
1227 }
1228
1229 offset = rtex->surface.level[level].offset;
1230 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1231 offset += rtex->surface.level[level].slice_size *
1232 surf->base.u.tex.first_layer;
1233 }
1234 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1235 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1236 if (slice) {
1237 slice = slice - 1;
1238 }
1239 color_info = 0;
1240 switch (rtex->surface.level[level].mode) {
1241 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1242 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1243 break;
1244 case RADEON_SURF_MODE_1D:
1245 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1246 break;
1247 case RADEON_SURF_MODE_2D:
1248 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1249 break;
1250 case RADEON_SURF_MODE_LINEAR:
1251 default:
1252 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1253 break;
1254 }
1255
1256 desc = util_format_description(surf->base.format);
1257
1258 for (i = 0; i < 4; i++) {
1259 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1260 break;
1261 }
1262 }
1263
1264 ntype = V_0280A0_NUMBER_UNORM;
1265 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1266 ntype = V_0280A0_NUMBER_SRGB;
1267 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1268 if (desc->channel[i].normalized)
1269 ntype = V_0280A0_NUMBER_SNORM;
1270 else if (desc->channel[i].pure_integer)
1271 ntype = V_0280A0_NUMBER_SINT;
1272 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1273 if (desc->channel[i].normalized)
1274 ntype = V_0280A0_NUMBER_UNORM;
1275 else if (desc->channel[i].pure_integer)
1276 ntype = V_0280A0_NUMBER_UINT;
1277 }
1278
1279 format = r600_translate_colorformat(surf->base.format);
1280 assert(format != ~0);
1281
1282 swap = r600_translate_colorswap(surf->base.format);
1283 assert(swap != ~0);
1284
1285 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1286 endian = ENDIAN_NONE;
1287 } else {
1288 endian = r600_colorformat_endian_swap(format);
1289 }
1290
1291 /* set blend bypass according to docs if SINT/UINT or
1292 8/24 COLOR variants */
1293 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1294 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1295 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1296 blend_clamp = 0;
1297 blend_bypass = 1;
1298 }
1299
1300 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
1301
1302 color_info |= S_0280A0_FORMAT(format) |
1303 S_0280A0_COMP_SWAP(swap) |
1304 S_0280A0_BLEND_BYPASS(blend_bypass) |
1305 S_0280A0_BLEND_CLAMP(blend_clamp) |
1306 S_0280A0_NUMBER_TYPE(ntype) |
1307 S_0280A0_ENDIAN(endian);
1308
1309 /* EXPORT_NORM is an optimzation that can be enabled for better
1310 * performance in certain cases
1311 */
1312 if (rctx->chip_class == R600) {
1313 /* EXPORT_NORM can be enabled if:
1314 * - 11-bit or smaller UNORM/SNORM/SRGB
1315 * - BLEND_CLAMP is enabled
1316 * - BLEND_FLOAT32 is disabled
1317 */
1318 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1319 (desc->channel[i].size < 12 &&
1320 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1321 ntype != V_0280A0_NUMBER_UINT &&
1322 ntype != V_0280A0_NUMBER_SINT) &&
1323 G_0280A0_BLEND_CLAMP(color_info) &&
1324 !G_0280A0_BLEND_FLOAT32(color_info)) {
1325 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1326 surf->export_16bpc = true;
1327 }
1328 } else {
1329 /* EXPORT_NORM can be enabled if:
1330 * - 11-bit or smaller UNORM/SNORM/SRGB
1331 * - 16-bit or smaller FLOAT
1332 */
1333 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1334 ((desc->channel[i].size < 12 &&
1335 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1336 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1337 (desc->channel[i].size < 17 &&
1338 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1339 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1340 surf->export_16bpc = true;
1341 }
1342 }
1343
1344 /* These might not always be initialized to zero. */
1345 surf->cb_color_base = offset >> 8;
1346 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
1347 S_028060_SLICE_TILE_MAX(slice);
1348 surf->cb_color_fmask = surf->cb_color_base;
1349 surf->cb_color_cmask = surf->cb_color_base;
1350 surf->cb_color_mask = 0;
1351
1352 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1353 &rtex->resource.b.b);
1354 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1355 &rtex->resource.b.b);
1356
1357 if (rtex->cmask_size) {
1358 surf->cb_color_cmask = rtex->cmask_offset >> 8;
1359 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask_slice_tile_max);
1360
1361 if (rtex->fmask_size) {
1362 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1363 surf->cb_color_fmask = rtex->fmask_offset >> 8;
1364 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(slice);
1365 } else { /* cmask only */
1366 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
1367 }
1368 } else if (force_cmask_fmask) {
1369 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1370 *
1371 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1372 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1373 * because it's not an MSAA buffer.
1374 */
1375 struct r600_cmask_info cmask;
1376 struct r600_fmask_info fmask;
1377
1378 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
1379 r600_texture_get_fmask_info(rscreen, rtex, 8, &fmask);
1380
1381 /* CMASK. */
1382 if (!rctx->dummy_cmask ||
1383 rctx->dummy_cmask->buf->size < cmask.size ||
1384 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1385 struct pipe_transfer *transfer;
1386 void *ptr;
1387
1388 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1389 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1390
1391 /* Set the contents to 0xCC. */
1392 ptr = pipe_buffer_map(&rctx->context, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1393 memset(ptr, 0xCC, cmask.size);
1394 pipe_buffer_unmap(&rctx->context, transfer);
1395 }
1396 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1397 &rctx->dummy_cmask->b.b);
1398
1399 /* FMASK. */
1400 if (!rctx->dummy_fmask ||
1401 rctx->dummy_fmask->buf->size < fmask.size ||
1402 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1403 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1404 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1405
1406 }
1407 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1408 &rctx->dummy_fmask->b.b);
1409
1410 /* Init the registers. */
1411 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1412 surf->cb_color_cmask = 0;
1413 surf->cb_color_fmask = 0;
1414 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1415 S_028100_FMASK_TILE_MAX(slice);
1416 }
1417
1418 surf->cb_color_info = color_info;
1419
1420 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1421 surf->cb_color_view = 0;
1422 } else {
1423 surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
1424 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
1425 }
1426
1427 surf->color_initialized = true;
1428 }
1429
1430 static void r600_init_depth_surface(struct r600_context *rctx,
1431 struct r600_surface *surf)
1432 {
1433 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1434 unsigned level, pitch, slice, format, offset, array_mode;
1435
1436 level = surf->base.u.tex.level;
1437 offset = rtex->surface.level[level].offset;
1438 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1439 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1440 if (slice) {
1441 slice = slice - 1;
1442 }
1443 switch (rtex->surface.level[level].mode) {
1444 case RADEON_SURF_MODE_2D:
1445 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1446 break;
1447 case RADEON_SURF_MODE_1D:
1448 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1449 case RADEON_SURF_MODE_LINEAR:
1450 default:
1451 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1452 break;
1453 }
1454
1455 format = r600_translate_dbformat(surf->base.format);
1456 assert(format != ~0);
1457
1458 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1459 surf->db_depth_base = offset >> 8;
1460 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1461 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1462 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1463 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1464
1465 switch (surf->base.format) {
1466 case PIPE_FORMAT_Z24X8_UNORM:
1467 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1468 surf->pa_su_poly_offset_db_fmt_cntl =
1469 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1470 break;
1471 case PIPE_FORMAT_Z32_FLOAT:
1472 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1473 surf->pa_su_poly_offset_db_fmt_cntl =
1474 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1475 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1476 break;
1477 case PIPE_FORMAT_Z16_UNORM:
1478 surf->pa_su_poly_offset_db_fmt_cntl =
1479 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1480 break;
1481 default:;
1482 }
1483
1484 surf->htile_enabled = 0;
1485 /* use htile only for first level */
1486 if (rtex->htile && !level) {
1487 uint64_t va = r600_resource_va(&rctx->screen->screen, &rtex->htile->b.b);
1488 surf->htile_enabled = 1;
1489 surf->db_htile_data_base = va >> 8;
1490 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1491 S_028D24_HTILE_HEIGHT(1) |
1492 S_028D24_LINEAR(1);
1493 /* preload is not working properly on r6xx/r7xx */
1494 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1495 }
1496
1497 surf->depth_initialized = true;
1498 }
1499
1500 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1501 const struct pipe_framebuffer_state *state)
1502 {
1503 struct r600_context *rctx = (struct r600_context *)ctx;
1504 struct r600_surface *surf;
1505 struct r600_texture *rtex;
1506 unsigned i;
1507
1508 if (rctx->framebuffer.state.nr_cbufs) {
1509 rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1510
1511 if (rctx->chip_class >= R700 &&
1512 rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
1513 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
1514 }
1515 }
1516 if (rctx->framebuffer.state.zsbuf) {
1517 rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1518 }
1519
1520 /* Set the new state. */
1521 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1522
1523 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1524 rctx->framebuffer.cb0_is_integer = state->nr_cbufs &&
1525 util_format_is_pure_integer(state->cbufs[0]->format);
1526 rctx->framebuffer.compressed_cb_mask = 0;
1527 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1528 state->cbufs[0]->texture->nr_samples > 1 &&
1529 state->cbufs[1]->texture->nr_samples <= 1;
1530
1531 if (state->nr_cbufs)
1532 rctx->framebuffer.nr_samples = state->cbufs[0]->texture->nr_samples;
1533 else if (state->zsbuf)
1534 rctx->framebuffer.nr_samples = state->zsbuf->texture->nr_samples;
1535 else
1536 rctx->framebuffer.nr_samples = 0;
1537
1538 /* Colorbuffers. */
1539 for (i = 0; i < state->nr_cbufs; i++) {
1540 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1541 bool force_cmask_fmask = rctx->chip_class == R600 &&
1542 rctx->framebuffer.is_msaa_resolve &&
1543 i == 1;
1544
1545 surf = (struct r600_surface*)state->cbufs[i];
1546 rtex = (struct r600_texture*)surf->base.texture;
1547
1548 if (!surf->color_initialized || force_cmask_fmask) {
1549 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1550 if (force_cmask_fmask) {
1551 /* re-initialize later without compression */
1552 surf->color_initialized = false;
1553 }
1554 }
1555
1556 if (!surf->export_16bpc) {
1557 rctx->framebuffer.export_16bpc = false;
1558 }
1559
1560 if (rtex->fmask_size && rtex->cmask_size) {
1561 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1562 }
1563 }
1564
1565 /* Update alpha-test state dependencies.
1566 * Alpha-test is done on the first colorbuffer only. */
1567 if (state->nr_cbufs) {
1568 surf = (struct r600_surface*)state->cbufs[0];
1569 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1570 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1571 rctx->alphatest_state.atom.dirty = true;
1572 }
1573 }
1574
1575 /* ZS buffer. */
1576 if (state->zsbuf) {
1577 surf = (struct r600_surface*)state->zsbuf;
1578
1579 if (!surf->depth_initialized) {
1580 r600_init_depth_surface(rctx, surf);
1581 }
1582
1583 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1584 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1585 rctx->poly_offset_state.atom.dirty = true;
1586 }
1587
1588 if (rctx->db_state.rsurf != surf) {
1589 rctx->db_state.rsurf = surf;
1590 rctx->db_state.atom.dirty = true;
1591 rctx->db_misc_state.atom.dirty = true;
1592 }
1593 } else if (rctx->db_state.rsurf) {
1594 rctx->db_state.rsurf = NULL;
1595 rctx->db_state.atom.dirty = true;
1596 rctx->db_misc_state.atom.dirty = true;
1597 }
1598
1599 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1600 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1601 rctx->cb_misc_state.atom.dirty = true;
1602 }
1603
1604 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1605 rctx->alphatest_state.bypass = false;
1606 rctx->alphatest_state.atom.dirty = true;
1607 }
1608
1609 r600_update_db_shader_control(rctx);
1610
1611 /* Calculate the CS size. */
1612 rctx->framebuffer.atom.num_dw =
1613 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1614
1615 if (rctx->framebuffer.state.nr_cbufs) {
1616 rctx->framebuffer.atom.num_dw += 6 * (2 + rctx->framebuffer.state.nr_cbufs);
1617 rctx->framebuffer.atom.num_dw += 6 * rctx->framebuffer.state.nr_cbufs; /* relocs */
1618
1619 }
1620 if (rctx->framebuffer.state.zsbuf) {
1621 rctx->framebuffer.atom.num_dw += 18;
1622 } else if (rctx->screen->info.drm_minor >= 18) {
1623 rctx->framebuffer.atom.num_dw += 3;
1624 }
1625 if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770) {
1626 rctx->framebuffer.atom.num_dw += 2;
1627 }
1628
1629 rctx->framebuffer.atom.dirty = true;
1630 }
1631
1632 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1633 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1634 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1635 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1636 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1637
1638 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1639 {
1640 static uint32_t sample_locs_2x[] = {
1641 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1642 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1643 };
1644 static unsigned max_dist_2x = 4;
1645 static uint32_t sample_locs_4x[] = {
1646 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1647 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1648 };
1649 static unsigned max_dist_4x = 6;
1650 static uint32_t sample_locs_8x[] = {
1651 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1652 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1653 };
1654 static unsigned max_dist_8x = 7;
1655
1656 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1657 unsigned max_dist = 0;
1658
1659 if (rctx->family == CHIP_R600) {
1660 switch (nr_samples) {
1661 default:
1662 nr_samples = 0;
1663 break;
1664 case 2:
1665 r600_write_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1666 max_dist = max_dist_2x;
1667 break;
1668 case 4:
1669 r600_write_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1670 max_dist = max_dist_4x;
1671 break;
1672 case 8:
1673 r600_write_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1674 r600_write_value(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1675 r600_write_value(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1676 max_dist = max_dist_8x;
1677 break;
1678 }
1679 } else {
1680 switch (nr_samples) {
1681 default:
1682 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1683 r600_write_value(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1684 r600_write_value(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1685 nr_samples = 0;
1686 break;
1687 case 2:
1688 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1689 r600_write_value(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1690 r600_write_value(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1691 max_dist = max_dist_2x;
1692 break;
1693 case 4:
1694 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1695 r600_write_value(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1696 r600_write_value(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1697 max_dist = max_dist_4x;
1698 break;
1699 case 8:
1700 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1701 r600_write_value(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1702 r600_write_value(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1703 max_dist = max_dist_8x;
1704 break;
1705 }
1706 }
1707
1708 if (nr_samples > 1) {
1709 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1710 r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
1711 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1712 r600_write_value(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1713 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1714 } else {
1715 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1716 r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1717 r600_write_value(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1718 }
1719 }
1720
1721 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1722 {
1723 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1724 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1725 unsigned nr_cbufs = state->nr_cbufs;
1726 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1727 unsigned i, sbu = 0;
1728
1729 /* Colorbuffers. */
1730 r600_write_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1731 for (i = 0; i < nr_cbufs; i++) {
1732 r600_write_value(cs, cb[i]->cb_color_info);
1733 }
1734 /* set CB_COLOR1_INFO for possible dual-src blending */
1735 if (i == 1) {
1736 r600_write_value(cs, cb[0]->cb_color_info);
1737 i++;
1738 }
1739 for (; i < 8; i++) {
1740 r600_write_value(cs, 0);
1741 }
1742
1743 if (nr_cbufs) {
1744 /* COLOR_BASE */
1745 r600_write_context_reg_seq(cs, R_028040_CB_COLOR0_BASE, nr_cbufs);
1746 for (i = 0; i < nr_cbufs; i++) {
1747 r600_write_value(cs, cb[i]->cb_color_base);
1748 }
1749
1750 /* relocations */
1751 for (i = 0; i < nr_cbufs; i++) {
1752 unsigned reloc = r600_context_bo_reloc(rctx,
1753 &rctx->rings.gfx,
1754 (struct r600_resource*)cb[i]->base.texture,
1755 RADEON_USAGE_READWRITE);
1756 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1757 r600_write_value(cs, reloc);
1758 }
1759
1760 r600_write_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1761 for (i = 0; i < nr_cbufs; i++) {
1762 r600_write_value(cs, cb[i]->cb_color_size);
1763 }
1764
1765 r600_write_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1766 for (i = 0; i < nr_cbufs; i++) {
1767 r600_write_value(cs, cb[i]->cb_color_view);
1768 }
1769
1770 r600_write_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1771 for (i = 0; i < nr_cbufs; i++) {
1772 r600_write_value(cs, cb[i]->cb_color_mask);
1773 }
1774
1775 /* FMASK. */
1776 r600_write_context_reg_seq(cs, R_0280E0_CB_COLOR0_FRAG, nr_cbufs);
1777 for (i = 0; i < nr_cbufs; i++) {
1778 r600_write_value(cs, cb[i]->cb_color_fmask);
1779 }
1780 /* relocations */
1781 for (i = 0; i < nr_cbufs; i++) {
1782 unsigned reloc = r600_context_bo_reloc(rctx,
1783 &rctx->rings.gfx,
1784 cb[i]->cb_buffer_fmask,
1785 RADEON_USAGE_READWRITE);
1786 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1787 r600_write_value(cs, reloc);
1788 }
1789
1790 /* CMASK. */
1791 r600_write_context_reg_seq(cs, R_0280C0_CB_COLOR0_TILE, nr_cbufs);
1792 for (i = 0; i < nr_cbufs; i++) {
1793 r600_write_value(cs, cb[i]->cb_color_cmask);
1794 }
1795 /* relocations */
1796 for (i = 0; i < nr_cbufs; i++) {
1797 unsigned reloc = r600_context_bo_reloc(rctx,
1798 &rctx->rings.gfx,
1799 cb[i]->cb_buffer_cmask,
1800 RADEON_USAGE_READWRITE);
1801 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1802 r600_write_value(cs, reloc);
1803 }
1804
1805 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1806 }
1807
1808 /* SURFACE_BASE_UPDATE */
1809 if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770 && sbu) {
1810 r600_write_value(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1811 r600_write_value(cs, sbu);
1812 sbu = 0;
1813 }
1814
1815 /* Zbuffer. */
1816 if (state->zsbuf) {
1817 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1818 unsigned reloc = r600_context_bo_reloc(rctx,
1819 &rctx->rings.gfx,
1820 (struct r600_resource*)state->zsbuf->texture,
1821 RADEON_USAGE_READWRITE);
1822
1823 r600_write_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1824 surf->pa_su_poly_offset_db_fmt_cntl);
1825
1826 r600_write_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1827 r600_write_value(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1828 r600_write_value(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1829 r600_write_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1830 r600_write_value(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1831 r600_write_value(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1832
1833 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1834 r600_write_value(cs, reloc);
1835
1836 r600_write_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1837
1838 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1839 } else if (rctx->screen->info.drm_minor >= 18) {
1840 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1841 * Older kernels are out of luck. */
1842 r600_write_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1843 }
1844
1845 /* SURFACE_BASE_UPDATE */
1846 if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770 && sbu) {
1847 r600_write_value(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1848 r600_write_value(cs, sbu);
1849 sbu = 0;
1850 }
1851
1852 /* Framebuffer dimensions. */
1853 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1854 r600_write_value(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1855 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1856 r600_write_value(cs, S_028244_BR_X(state->width) |
1857 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1858
1859 if (rctx->framebuffer.is_msaa_resolve) {
1860 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1861 } else {
1862 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1863 * will assure that the alpha-test will work even if there is
1864 * no colorbuffer bound. */
1865 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1866 (1ull << MAX2(nr_cbufs, 1)) - 1);
1867 }
1868
1869 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1870 }
1871
1872 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1873 {
1874 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1875 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1876
1877 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1878 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1879 if (rctx->chip_class == R600) {
1880 r600_write_value(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1881 r600_write_value(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1882 } else {
1883 r600_write_value(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1884 r600_write_value(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1885 }
1886 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1887 } else {
1888 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1889 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1890 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1891
1892 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1893 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1894 /* Always enable the first color output to make sure alpha-test works even without one. */
1895 r600_write_value(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1896 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1897 a->cb_color_control |
1898 S_028808_MULTIWRITE_ENABLE(multiwrite));
1899 }
1900 }
1901
1902 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1903 {
1904 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1905 struct r600_db_state *a = (struct r600_db_state*)atom;
1906
1907 if (a->rsurf && a->rsurf->htile_enabled) {
1908 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1909 unsigned reloc_idx;
1910
1911 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear));
1912 r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1913 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1914 reloc_idx = r600_context_bo_reloc(rctx, &rctx->rings.gfx, rtex->htile, RADEON_USAGE_READWRITE);
1915 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1916 cs->buf[cs->cdw++] = reloc_idx;
1917 } else {
1918 r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1919 }
1920 }
1921
1922 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1923 {
1924 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1925 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1926 unsigned db_render_control = 0;
1927 unsigned db_render_override =
1928 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1929 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1930
1931 if (a->occlusion_query_enabled) {
1932 if (rctx->chip_class >= R700) {
1933 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1934 }
1935 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1936 }
1937 if (rctx->db_state.rsurf && rctx->db_state.rsurf->htile_enabled) {
1938 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1939 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1940 } else {
1941 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1942 }
1943 if (a->flush_depthstencil_through_cb) {
1944 assert(a->copy_depth || a->copy_stencil);
1945
1946 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1947 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1948 S_028D0C_COPY_CENTROID(1) |
1949 S_028D0C_COPY_SAMPLE(a->copy_sample);
1950 } else if (a->flush_depthstencil_in_place) {
1951 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(1) |
1952 S_028D0C_STENCIL_COMPRESS_DISABLE(1);
1953 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1954 }
1955 if (a->htile_clear) {
1956 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1957 }
1958
1959 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1960 r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1961 r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1962 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1963 }
1964
1965 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1966 {
1967 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1968 struct r600_config_state *a = (struct r600_config_state*)atom;
1969
1970 r600_write_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1971 }
1972
1973 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1974 {
1975 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
1976 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1977
1978 while (dirty_mask) {
1979 struct pipe_vertex_buffer *vb;
1980 struct r600_resource *rbuffer;
1981 unsigned offset;
1982 unsigned buffer_index = u_bit_scan(&dirty_mask);
1983
1984 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1985 rbuffer = (struct r600_resource*)vb->buffer;
1986 assert(rbuffer);
1987
1988 offset = vb->buffer_offset;
1989
1990 /* fetch resources start at index 320 */
1991 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1992 r600_write_value(cs, (320 + buffer_index) * 7);
1993 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1994 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1995 r600_write_value(cs, /* RESOURCEi_WORD2 */
1996 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1997 S_038008_STRIDE(vb->stride));
1998 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1999 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
2000 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
2001 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
2002
2003 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2004 r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, rbuffer, RADEON_USAGE_READ));
2005 }
2006 }
2007
2008 static void r600_emit_constant_buffers(struct r600_context *rctx,
2009 struct r600_constbuf_state *state,
2010 unsigned buffer_id_base,
2011 unsigned reg_alu_constbuf_size,
2012 unsigned reg_alu_const_cache)
2013 {
2014 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2015 uint32_t dirty_mask = state->dirty_mask;
2016
2017 while (dirty_mask) {
2018 struct pipe_constant_buffer *cb;
2019 struct r600_resource *rbuffer;
2020 unsigned offset;
2021 unsigned buffer_index = ffs(dirty_mask) - 1;
2022
2023 cb = &state->cb[buffer_index];
2024 rbuffer = (struct r600_resource*)cb->buffer;
2025 assert(rbuffer);
2026
2027 offset = cb->buffer_offset;
2028
2029 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
2030 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
2031 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
2032
2033 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2034 r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, rbuffer, RADEON_USAGE_READ));
2035
2036 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
2037 r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
2038 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
2039 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
2040 r600_write_value(cs, /* RESOURCEi_WORD2 */
2041 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
2042 S_038008_STRIDE(16));
2043 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
2044 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
2045 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
2046 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
2047
2048 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2049 r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, rbuffer, RADEON_USAGE_READ));
2050
2051 dirty_mask &= ~(1 << buffer_index);
2052 }
2053 state->dirty_mask = 0;
2054 }
2055
2056 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2057 {
2058 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 160,
2059 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2060 R_028980_ALU_CONST_CACHE_VS_0);
2061 }
2062
2063 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2064 {
2065 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
2066 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2067 R_0289C0_ALU_CONST_CACHE_GS_0);
2068 }
2069
2070 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2071 {
2072 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
2073 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2074 R_028940_ALU_CONST_CACHE_PS_0);
2075 }
2076
2077 static void r600_emit_sampler_views(struct r600_context *rctx,
2078 struct r600_samplerview_state *state,
2079 unsigned resource_id_base)
2080 {
2081 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2082 uint32_t dirty_mask = state->dirty_mask;
2083
2084 while (dirty_mask) {
2085 struct r600_pipe_sampler_view *rview;
2086 unsigned resource_index = u_bit_scan(&dirty_mask);
2087 unsigned reloc;
2088
2089 rview = state->views[resource_index];
2090 assert(rview);
2091
2092 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
2093 r600_write_value(cs, (resource_id_base + resource_index) * 7);
2094 r600_write_array(cs, 7, rview->tex_resource_words);
2095
2096 reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, rview->tex_resource,
2097 RADEON_USAGE_READ);
2098 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2099 r600_write_value(cs, reloc);
2100 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2101 r600_write_value(cs, reloc);
2102 }
2103 state->dirty_mask = 0;
2104 }
2105
2106 /* Resource IDs:
2107 * PS: 0 .. +160
2108 * VS: 160 .. +160
2109 * FS: 320 .. +16
2110 * GS: 336 .. +160
2111 */
2112
2113 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2114 {
2115 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 160 + R600_MAX_CONST_BUFFERS);
2116 }
2117
2118 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2119 {
2120 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
2121 }
2122
2123 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2124 {
2125 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
2126 }
2127
2128 static void r600_emit_sampler_states(struct r600_context *rctx,
2129 struct r600_textures_info *texinfo,
2130 unsigned resource_id_base,
2131 unsigned border_color_reg)
2132 {
2133 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2134 uint32_t dirty_mask = texinfo->states.dirty_mask;
2135
2136 while (dirty_mask) {
2137 struct r600_pipe_sampler_state *rstate;
2138 struct r600_pipe_sampler_view *rview;
2139 unsigned i = u_bit_scan(&dirty_mask);
2140
2141 rstate = texinfo->states.states[i];
2142 assert(rstate);
2143 rview = texinfo->views.views[i];
2144
2145 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
2146 * filtering between layers.
2147 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
2148 */
2149 if (rview) {
2150 enum pipe_texture_target target = rview->base.texture->target;
2151 if (target == PIPE_TEXTURE_1D_ARRAY ||
2152 target == PIPE_TEXTURE_2D_ARRAY) {
2153 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
2154 texinfo->is_array_sampler[i] = true;
2155 } else {
2156 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
2157 texinfo->is_array_sampler[i] = false;
2158 }
2159 }
2160
2161 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2162 r600_write_value(cs, (resource_id_base + i) * 3);
2163 r600_write_array(cs, 3, rstate->tex_sampler_words);
2164
2165 if (rstate->border_color_use) {
2166 unsigned offset;
2167
2168 offset = border_color_reg;
2169 offset += i * 16;
2170 r600_write_config_reg_seq(cs, offset, 4);
2171 r600_write_array(cs, 4, rstate->border_color.ui);
2172 }
2173 }
2174 texinfo->states.dirty_mask = 0;
2175 }
2176
2177 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2178 {
2179 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
2180 }
2181
2182 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2183 {
2184 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
2185 }
2186
2187 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2188 {
2189 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
2190 }
2191
2192 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
2193 {
2194 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2195 unsigned tmp;
2196
2197 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
2198 S_009508_SYNC_GRADIENT(1) |
2199 S_009508_SYNC_WALKER(1) |
2200 S_009508_SYNC_ALIGNER(1);
2201 if (!rctx->seamless_cube_map.enabled) {
2202 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
2203 }
2204 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
2205 }
2206
2207 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2208 {
2209 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2210 uint8_t mask = s->sample_mask;
2211
2212 r600_write_context_reg(rctx->rings.gfx.cs, R_028C48_PA_SC_AA_MASK,
2213 mask | (mask << 8) | (mask << 16) | (mask << 24));
2214 }
2215
2216 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2217 {
2218 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
2219 struct r600_cso_state *state = (struct r600_cso_state*)a;
2220 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2221
2222 r600_write_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
2223 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2224 r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, shader->buffer, RADEON_USAGE_READ));
2225 }
2226
2227 void r600_init_state_functions(struct r600_context *rctx)
2228 {
2229 unsigned id = 4;
2230
2231 /* !!!
2232 * To avoid GPU lockup registers must be emited in a specific order
2233 * (no kidding ...). The order below is important and have been
2234 * partialy infered from analyzing fglrx command stream.
2235 *
2236 * Don't reorder atom without carefully checking the effect (GPU lockup
2237 * or piglit regression).
2238 * !!!
2239 */
2240
2241 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
2242
2243 /* shader const */
2244 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
2245 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
2246 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
2247
2248 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2249 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
2250 */
2251 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
2252 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
2253 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
2254 /* resource */
2255 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
2256 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
2257 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
2258 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
2259
2260 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 6);
2261 r600_init_atom(rctx, &rctx->vgt2_state.atom, id++, r600_emit_vgt2_state, 3);
2262
2263 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
2264 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
2265 rctx->sample_mask.sample_mask = ~0;
2266
2267 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
2268 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
2269 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
2270 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
2271 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
2272 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
2273 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
2274 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
2275 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
2276 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
2277 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
2278 r600_init_atom(rctx, &rctx->scissor.atom, id++, r600_emit_scissor_state, 4);
2279 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
2280 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
2281 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
2282 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
2283
2284 rctx->context.create_blend_state = r600_create_blend_state;
2285 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
2286 rctx->context.create_rasterizer_state = r600_create_rs_state;
2287 rctx->context.create_sampler_state = r600_create_sampler_state;
2288 rctx->context.create_sampler_view = r600_create_sampler_view;
2289 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
2290 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
2291 rctx->context.set_scissor_state = r600_set_scissor_state;
2292 }
2293
2294 /* Adjust GPR allocation on R6xx/R7xx */
2295 bool r600_adjust_gprs(struct r600_context *rctx)
2296 {
2297 unsigned num_ps_gprs = rctx->ps_shader->current->shader.bc.ngpr;
2298 unsigned num_vs_gprs = rctx->vs_shader->current->shader.bc.ngpr;
2299 unsigned new_num_ps_gprs = num_ps_gprs;
2300 unsigned new_num_vs_gprs = num_vs_gprs;
2301 unsigned cur_num_ps_gprs = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2302 unsigned cur_num_vs_gprs = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2303 unsigned def_num_ps_gprs = rctx->default_ps_gprs;
2304 unsigned def_num_vs_gprs = rctx->default_vs_gprs;
2305 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
2306 /* hardware will reserve twice num_clause_temp_gprs */
2307 unsigned max_gprs = def_num_ps_gprs + def_num_vs_gprs + def_num_clause_temp_gprs * 2;
2308 unsigned tmp;
2309
2310 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2311 if (new_num_ps_gprs > cur_num_ps_gprs || new_num_vs_gprs > cur_num_vs_gprs) {
2312 /* try to use switch back to default */
2313 if (new_num_ps_gprs > def_num_ps_gprs || new_num_vs_gprs > def_num_vs_gprs) {
2314 /* always privilege vs stage so that at worst we have the
2315 * pixel stage producing wrong output (not the vertex
2316 * stage) */
2317 new_num_ps_gprs = max_gprs - (new_num_vs_gprs + def_num_clause_temp_gprs * 2);
2318 new_num_vs_gprs = num_vs_gprs;
2319 } else {
2320 new_num_ps_gprs = def_num_ps_gprs;
2321 new_num_vs_gprs = def_num_vs_gprs;
2322 }
2323 } else {
2324 return true;
2325 }
2326
2327 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2328 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2329 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2330 * it will lockup. So in this case just discard the draw command
2331 * and don't change the current gprs repartitions.
2332 */
2333 if (num_ps_gprs > new_num_ps_gprs || num_vs_gprs > new_num_vs_gprs) {
2334 R600_ERR("ps & vs shader require too many register (%d + %d) "
2335 "for a combined maximum of %d\n",
2336 num_ps_gprs, num_vs_gprs, max_gprs);
2337 return false;
2338 }
2339
2340 /* in some case we endup recomputing the current value */
2341 tmp = S_008C04_NUM_PS_GPRS(new_num_ps_gprs) |
2342 S_008C04_NUM_VS_GPRS(new_num_vs_gprs) |
2343 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2344 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp) {
2345 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2346 rctx->config_state.atom.dirty = true;
2347 rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
2348 }
2349 return true;
2350 }
2351
2352 void r600_init_atom_start_cs(struct r600_context *rctx)
2353 {
2354 int ps_prio;
2355 int vs_prio;
2356 int gs_prio;
2357 int es_prio;
2358 int num_ps_gprs;
2359 int num_vs_gprs;
2360 int num_gs_gprs;
2361 int num_es_gprs;
2362 int num_temp_gprs;
2363 int num_ps_threads;
2364 int num_vs_threads;
2365 int num_gs_threads;
2366 int num_es_threads;
2367 int num_ps_stack_entries;
2368 int num_vs_stack_entries;
2369 int num_gs_stack_entries;
2370 int num_es_stack_entries;
2371 enum radeon_family family;
2372 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2373 uint32_t tmp;
2374
2375 r600_init_command_buffer(cb, 256);
2376
2377 /* R6xx requires this packet at the start of each command buffer */
2378 if (rctx->chip_class == R600) {
2379 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2380 r600_store_value(cb, 0);
2381 }
2382 /* All asics require this one */
2383 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2384 r600_store_value(cb, 0x80000000);
2385 r600_store_value(cb, 0x80000000);
2386
2387 /* We're setting config registers here. */
2388 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2389 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2390
2391 family = rctx->family;
2392 ps_prio = 0;
2393 vs_prio = 1;
2394 gs_prio = 2;
2395 es_prio = 3;
2396 switch (family) {
2397 case CHIP_R600:
2398 num_ps_gprs = 192;
2399 num_vs_gprs = 56;
2400 num_temp_gprs = 4;
2401 num_gs_gprs = 0;
2402 num_es_gprs = 0;
2403 num_ps_threads = 136;
2404 num_vs_threads = 48;
2405 num_gs_threads = 4;
2406 num_es_threads = 4;
2407 num_ps_stack_entries = 128;
2408 num_vs_stack_entries = 128;
2409 num_gs_stack_entries = 0;
2410 num_es_stack_entries = 0;
2411 break;
2412 case CHIP_RV630:
2413 case CHIP_RV635:
2414 num_ps_gprs = 84;
2415 num_vs_gprs = 36;
2416 num_temp_gprs = 4;
2417 num_gs_gprs = 0;
2418 num_es_gprs = 0;
2419 num_ps_threads = 144;
2420 num_vs_threads = 40;
2421 num_gs_threads = 4;
2422 num_es_threads = 4;
2423 num_ps_stack_entries = 40;
2424 num_vs_stack_entries = 40;
2425 num_gs_stack_entries = 32;
2426 num_es_stack_entries = 16;
2427 break;
2428 case CHIP_RV610:
2429 case CHIP_RV620:
2430 case CHIP_RS780:
2431 case CHIP_RS880:
2432 default:
2433 num_ps_gprs = 84;
2434 num_vs_gprs = 36;
2435 num_temp_gprs = 4;
2436 num_gs_gprs = 0;
2437 num_es_gprs = 0;
2438 num_ps_threads = 136;
2439 num_vs_threads = 48;
2440 num_gs_threads = 4;
2441 num_es_threads = 4;
2442 num_ps_stack_entries = 40;
2443 num_vs_stack_entries = 40;
2444 num_gs_stack_entries = 32;
2445 num_es_stack_entries = 16;
2446 break;
2447 case CHIP_RV670:
2448 num_ps_gprs = 144;
2449 num_vs_gprs = 40;
2450 num_temp_gprs = 4;
2451 num_gs_gprs = 0;
2452 num_es_gprs = 0;
2453 num_ps_threads = 136;
2454 num_vs_threads = 48;
2455 num_gs_threads = 4;
2456 num_es_threads = 4;
2457 num_ps_stack_entries = 40;
2458 num_vs_stack_entries = 40;
2459 num_gs_stack_entries = 32;
2460 num_es_stack_entries = 16;
2461 break;
2462 case CHIP_RV770:
2463 num_ps_gprs = 192;
2464 num_vs_gprs = 56;
2465 num_temp_gprs = 4;
2466 num_gs_gprs = 0;
2467 num_es_gprs = 0;
2468 num_ps_threads = 188;
2469 num_vs_threads = 60;
2470 num_gs_threads = 0;
2471 num_es_threads = 0;
2472 num_ps_stack_entries = 256;
2473 num_vs_stack_entries = 256;
2474 num_gs_stack_entries = 0;
2475 num_es_stack_entries = 0;
2476 break;
2477 case CHIP_RV730:
2478 case CHIP_RV740:
2479 num_ps_gprs = 84;
2480 num_vs_gprs = 36;
2481 num_temp_gprs = 4;
2482 num_gs_gprs = 0;
2483 num_es_gprs = 0;
2484 num_ps_threads = 188;
2485 num_vs_threads = 60;
2486 num_gs_threads = 0;
2487 num_es_threads = 0;
2488 num_ps_stack_entries = 128;
2489 num_vs_stack_entries = 128;
2490 num_gs_stack_entries = 0;
2491 num_es_stack_entries = 0;
2492 break;
2493 case CHIP_RV710:
2494 num_ps_gprs = 192;
2495 num_vs_gprs = 56;
2496 num_temp_gprs = 4;
2497 num_gs_gprs = 0;
2498 num_es_gprs = 0;
2499 num_ps_threads = 144;
2500 num_vs_threads = 48;
2501 num_gs_threads = 0;
2502 num_es_threads = 0;
2503 num_ps_stack_entries = 128;
2504 num_vs_stack_entries = 128;
2505 num_gs_stack_entries = 0;
2506 num_es_stack_entries = 0;
2507 break;
2508 }
2509
2510 rctx->default_ps_gprs = num_ps_gprs;
2511 rctx->default_vs_gprs = num_vs_gprs;
2512 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2513
2514 /* SQ_CONFIG */
2515 tmp = 0;
2516 switch (family) {
2517 case CHIP_RV610:
2518 case CHIP_RV620:
2519 case CHIP_RS780:
2520 case CHIP_RS880:
2521 case CHIP_RV710:
2522 break;
2523 default:
2524 tmp |= S_008C00_VC_ENABLE(1);
2525 break;
2526 }
2527 tmp |= S_008C00_DX9_CONSTS(0);
2528 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2529 tmp |= S_008C00_PS_PRIO(ps_prio);
2530 tmp |= S_008C00_VS_PRIO(vs_prio);
2531 tmp |= S_008C00_GS_PRIO(gs_prio);
2532 tmp |= S_008C00_ES_PRIO(es_prio);
2533 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2534
2535 /* SQ_GPR_RESOURCE_MGMT_2 */
2536 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2537 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2538 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2539 r600_store_value(cb, tmp);
2540
2541 /* SQ_THREAD_RESOURCE_MGMT */
2542 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2543 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2544 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2545 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2546 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2547
2548 /* SQ_STACK_RESOURCE_MGMT_1 */
2549 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2550 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2551 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2552
2553 /* SQ_STACK_RESOURCE_MGMT_2 */
2554 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2555 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2556 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2557
2558 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2559
2560 if (rctx->chip_class >= R700) {
2561 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2562 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2563 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2564 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2565 } else {
2566 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2567 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2568 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2569 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2570 }
2571 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2572 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2573 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2574 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2575 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2576 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2577 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2578 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2579 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2580 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2581
2582 /* to avoid GPU doing any preloading of constant from random address */
2583 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2584 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2585 r600_store_value(cb, 0);
2586 r600_store_value(cb, 0);
2587 r600_store_value(cb, 0);
2588 r600_store_value(cb, 0);
2589 r600_store_value(cb, 0);
2590 r600_store_value(cb, 0);
2591 r600_store_value(cb, 0);
2592 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2593 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2594 r600_store_value(cb, 0);
2595 r600_store_value(cb, 0);
2596 r600_store_value(cb, 0);
2597 r600_store_value(cb, 0);
2598 r600_store_value(cb, 0);
2599 r600_store_value(cb, 0);
2600 r600_store_value(cb, 0);
2601
2602 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2603 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2604 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2605 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2606 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2607 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2608 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2609 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2610 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2611 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2612 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2613 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2614 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2615 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2616
2617 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2618 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2619 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2620
2621 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2622 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2623 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2624 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2625
2626 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2627
2628 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2629
2630 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2631
2632 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2633 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2634 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2635 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2636
2637 r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2638 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2639 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2640
2641 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2642 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2643
2644 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2645 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2646 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2647 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2648 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2649
2650 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2651 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2652 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2653
2654 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2655
2656 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2657 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2658
2659 if (rctx->chip_class >= R700) {
2660 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2661 }
2662
2663 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2664 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2665 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2666 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2667 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2668
2669 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2670 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2671 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2672
2673 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2674 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2675 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2676
2677 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2678 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2679 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2680
2681 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2682
2683 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2684 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2685 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2686
2687 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2688 r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2689
2690 if (rctx->chip_class == R700 && rctx->screen->has_streamout)
2691 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2692 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2693 if (rctx->screen->has_streamout) {
2694 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2695 }
2696
2697 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2698 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2699 }
2700
2701 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2702 {
2703 struct r600_context *rctx = (struct r600_context *)ctx;
2704 struct r600_pipe_state *rstate = &shader->rstate;
2705 struct r600_shader *rshader = &shader->shader;
2706 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2707 int pos_index = -1, face_index = -1;
2708 unsigned tmp, sid, ufi = 0;
2709 int need_linear = 0;
2710 unsigned z_export = 0, stencil_export = 0;
2711 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2712
2713 rstate->nregs = 0;
2714
2715 for (i = 0; i < rshader->ninput; i++) {
2716 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2717 pos_index = i;
2718 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2719 face_index = i;
2720
2721 sid = rshader->input[i].spi_sid;
2722
2723 tmp = S_028644_SEMANTIC(sid);
2724
2725 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2726 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2727 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2728 rctx->rasterizer && rctx->rasterizer->flatshade))
2729 tmp |= S_028644_FLAT_SHADE(1);
2730
2731 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2732 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2733 tmp |= S_028644_PT_SPRITE_TEX(1);
2734 }
2735
2736 if (rshader->input[i].centroid)
2737 tmp |= S_028644_SEL_CENTROID(1);
2738
2739 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2740 need_linear = 1;
2741 tmp |= S_028644_SEL_LINEAR(1);
2742 }
2743
2744 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2745 tmp);
2746 }
2747
2748 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2749 for (i = 0; i < rshader->noutput; i++) {
2750 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2751 z_export = 1;
2752 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2753 stencil_export = 1;
2754 }
2755 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2756 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2757 if (rshader->uses_kill)
2758 db_shader_control |= S_02880C_KILL_ENABLE(1);
2759
2760 exports_ps = 0;
2761 for (i = 0; i < rshader->noutput; i++) {
2762 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2763 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2764 exports_ps |= 1;
2765 }
2766 }
2767 num_cout = rshader->nr_ps_color_exports;
2768 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2769 if (!exports_ps) {
2770 /* always at least export 1 component per pixel */
2771 exports_ps = 2;
2772 }
2773
2774 shader->nr_ps_color_outputs = num_cout;
2775
2776 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2777 S_0286CC_PERSP_GRADIENT_ENA(1)|
2778 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2779 spi_input_z = 0;
2780 if (pos_index != -1) {
2781 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2782 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2783 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2784 S_0286CC_BARYC_SAMPLE_CNTL(1));
2785 spi_input_z |= 1;
2786 }
2787
2788 spi_ps_in_control_1 = 0;
2789 if (face_index != -1) {
2790 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2791 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2792 }
2793
2794 /* HW bug in original R600 */
2795 if (rctx->family == CHIP_R600)
2796 ufi = 1;
2797
2798 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2799 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2800 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2801 r600_pipe_state_add_reg_bo(rstate,
2802 R_028840_SQ_PGM_START_PS,
2803 0, shader->bo, RADEON_USAGE_READ);
2804 r600_pipe_state_add_reg(rstate,
2805 R_028850_SQ_PGM_RESOURCES_PS,
2806 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2807 S_028850_STACK_SIZE(rshader->bc.nstack) |
2808 S_028850_UNCACHED_FIRST_INST(ufi));
2809 r600_pipe_state_add_reg(rstate,
2810 R_028854_SQ_PGM_EXPORTS_PS,
2811 exports_ps);
2812 /* only set some bits here, the other bits are set in the dsa state */
2813 shader->db_shader_control = db_shader_control;
2814 shader->ps_depth_export = z_export | stencil_export;
2815
2816 shader->sprite_coord_enable = sprite_coord_enable;
2817 if (rctx->rasterizer)
2818 shader->flatshade = rctx->rasterizer->flatshade;
2819 }
2820
2821 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2822 {
2823 struct r600_context *rctx = (struct r600_context *)ctx;
2824 struct r600_pipe_state *rstate = &shader->rstate;
2825 struct r600_shader *rshader = &shader->shader;
2826 unsigned spi_vs_out_id[10] = {};
2827 unsigned i, tmp, nparams = 0;
2828
2829 /* clear previous register */
2830 rstate->nregs = 0;
2831
2832 for (i = 0; i < rshader->noutput; i++) {
2833 if (rshader->output[i].spi_sid) {
2834 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2835 spi_vs_out_id[nparams / 4] |= tmp;
2836 nparams++;
2837 }
2838 }
2839
2840 for (i = 0; i < 10; i++) {
2841 r600_pipe_state_add_reg(rstate,
2842 R_028614_SPI_VS_OUT_ID_0 + i * 4,
2843 spi_vs_out_id[i]);
2844 }
2845
2846 /* Certain attributes (position, psize, etc.) don't count as params.
2847 * VS is required to export at least one param and r600_shader_from_tgsi()
2848 * takes care of adding a dummy export.
2849 */
2850 if (nparams < 1)
2851 nparams = 1;
2852
2853 r600_pipe_state_add_reg(rstate,
2854 R_0286C4_SPI_VS_OUT_CONFIG,
2855 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2856 r600_pipe_state_add_reg(rstate,
2857 R_028868_SQ_PGM_RESOURCES_VS,
2858 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2859 S_028868_STACK_SIZE(rshader->bc.nstack));
2860 r600_pipe_state_add_reg_bo(rstate,
2861 R_028858_SQ_PGM_START_VS,
2862 0, shader->bo, RADEON_USAGE_READ);
2863
2864 shader->pa_cl_vs_out_cntl =
2865 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2866 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2867 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2868 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2869 }
2870
2871 void *r600_create_resolve_blend(struct r600_context *rctx)
2872 {
2873 struct pipe_blend_state blend;
2874 unsigned i;
2875
2876 memset(&blend, 0, sizeof(blend));
2877 blend.independent_blend_enable = true;
2878 for (i = 0; i < 2; i++) {
2879 blend.rt[i].colormask = 0xf;
2880 blend.rt[i].blend_enable = 1;
2881 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2882 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2883 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2884 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2885 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2886 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2887 }
2888 return r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2889 }
2890
2891 void *r700_create_resolve_blend(struct r600_context *rctx)
2892 {
2893 struct pipe_blend_state blend;
2894
2895 memset(&blend, 0, sizeof(blend));
2896 blend.independent_blend_enable = true;
2897 blend.rt[0].colormask = 0xf;
2898 return r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2899 }
2900
2901 void *r600_create_decompress_blend(struct r600_context *rctx)
2902 {
2903 struct pipe_blend_state blend;
2904
2905 memset(&blend, 0, sizeof(blend));
2906 blend.independent_blend_enable = true;
2907 blend.rt[0].colormask = 0xf;
2908 return r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2909 }
2910
2911 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2912 {
2913 struct pipe_depth_stencil_alpha_state dsa;
2914 boolean quirk = false;
2915
2916 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2917 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2918 quirk = true;
2919
2920 memset(&dsa, 0, sizeof(dsa));
2921
2922 if (quirk) {
2923 dsa.depth.enabled = 1;
2924 dsa.depth.func = PIPE_FUNC_LEQUAL;
2925 dsa.stencil[0].enabled = 1;
2926 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2927 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2928 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2929 dsa.stencil[0].writemask = 0xff;
2930 }
2931
2932 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2933 }
2934
2935 void r600_update_db_shader_control(struct r600_context * rctx)
2936 {
2937 bool dual_export = rctx->framebuffer.export_16bpc &&
2938 !rctx->ps_shader->current->ps_depth_export;
2939
2940 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2941 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2942
2943 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
2944 rctx->db_misc_state.db_shader_control = db_shader_control;
2945 rctx->db_misc_state.atom.dirty = true;
2946 }
2947 }
2948
2949 static INLINE unsigned r600_array_mode(unsigned mode)
2950 {
2951 switch (mode) {
2952 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
2953 break;
2954 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
2955 break;
2956 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
2957 default:
2958 case RADEON_SURF_MODE_LINEAR: return V_0280A0_ARRAY_LINEAR_GENERAL;
2959 }
2960 }
2961
2962 static boolean r600_dma_copy_tile(struct r600_context *rctx,
2963 struct pipe_resource *dst,
2964 unsigned dst_level,
2965 unsigned dst_x,
2966 unsigned dst_y,
2967 unsigned dst_z,
2968 struct pipe_resource *src,
2969 unsigned src_level,
2970 unsigned src_x,
2971 unsigned src_y,
2972 unsigned src_z,
2973 unsigned copy_height,
2974 unsigned pitch,
2975 unsigned bpp)
2976 {
2977 struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
2978 struct r600_texture *rsrc = (struct r600_texture*)src;
2979 struct r600_texture *rdst = (struct r600_texture*)dst;
2980 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
2981 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
2982 uint64_t base, addr;
2983
2984 /* make sure that the dma ring is only one active */
2985 rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
2986
2987 dst_mode = rdst->surface.level[dst_level].mode;
2988 src_mode = rsrc->surface.level[src_level].mode;
2989 /* downcast linear aligned to linear to simplify test */
2990 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
2991 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
2992 assert(dst_mode != src_mode);
2993
2994 y = 0;
2995 lbpp = util_logbase2(bpp);
2996 pitch_tile_max = ((pitch / bpp) >> 3) - 1;
2997
2998 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
2999 /* T2L */
3000 array_mode = r600_array_mode(src_mode);
3001 slice_tile_max = (((pitch * rsrc->surface.level[src_level].npix_y) >> 6) / bpp) - 1;
3002 /* linear height must be the same as the slice tile max height, it's ok even
3003 * if the linear destination/source have smaller heigh as the size of the
3004 * dma packet will be using the copy_height which is always smaller or equal
3005 * to the linear height
3006 */
3007 height = rsrc->surface.level[src_level].npix_y;
3008 detile = 1;
3009 x = src_x;
3010 y = src_y;
3011 z = src_z;
3012 base = rsrc->surface.level[src_level].offset;
3013 addr = rdst->surface.level[dst_level].offset;
3014 addr += rdst->surface.level[dst_level].slice_size * dst_z;
3015 addr += dst_y * pitch + dst_x * bpp;
3016 } else {
3017 /* L2T */
3018 array_mode = r600_array_mode(dst_mode);
3019 slice_tile_max = (((pitch * rdst->surface.level[dst_level].npix_y) >> 6) / bpp) - 1;
3020 /* linear height must be the same as the slice tile max height, it's ok even
3021 * if the linear destination/source have smaller heigh as the size of the
3022 * dma packet will be using the copy_height which is always smaller or equal
3023 * to the linear height
3024 */
3025 height = rdst->surface.level[dst_level].npix_y;
3026 detile = 0;
3027 x = dst_x;
3028 y = dst_y;
3029 z = dst_z;
3030 base = rdst->surface.level[dst_level].offset;
3031 addr = rsrc->surface.level[src_level].offset;
3032 addr += rsrc->surface.level[src_level].slice_size * src_z;
3033 addr += src_y * pitch + src_x * bpp;
3034 }
3035 /* check that we are in dw/base alignment constraint */
3036 if ((addr & 0x3) || (base & 0xff)) {
3037 return FALSE;
3038 }
3039
3040 size = (copy_height * pitch) >> 2;
3041 ncopy = (size / 0x0000ffff) + !!(size % 0x0000ffff);
3042 r600_need_dma_space(rctx, ncopy * 7);
3043 for (i = 0; i < ncopy; i++) {
3044 cheight = copy_height;
3045 if (((cheight * pitch) >> 2) > 0x0000ffff) {
3046 cheight = (0x0000ffff << 2) / pitch;
3047 }
3048 size = (cheight * pitch) >> 2;
3049 /* emit reloc before writting cs so that cs is always in consistent state */
3050 r600_context_bo_reloc(rctx, &rctx->rings.dma, &rsrc->resource, RADEON_USAGE_READ);
3051 r600_context_bo_reloc(rctx, &rctx->rings.dma, &rdst->resource, RADEON_USAGE_WRITE);
3052 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 1, 0, size);
3053 cs->buf[cs->cdw++] = base >> 8;
3054 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
3055 (lbpp << 24) | ((height - 1) << 10) |
3056 pitch_tile_max;
3057 cs->buf[cs->cdw++] = (slice_tile_max << 12) | (z << 0);
3058 cs->buf[cs->cdw++] = (x << 3) | (y << 17);
3059 cs->buf[cs->cdw++] = addr & 0xfffffffc;
3060 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
3061 copy_height -= cheight;
3062 addr += cheight * pitch;
3063 y += cheight;
3064 }
3065 return TRUE;
3066 }
3067
3068 boolean r600_dma_blit(struct pipe_context *ctx,
3069 struct pipe_resource *dst,
3070 unsigned dst_level,
3071 unsigned dst_x, unsigned dst_y, unsigned dst_z,
3072 struct pipe_resource *src,
3073 unsigned src_level,
3074 const struct pipe_box *src_box)
3075 {
3076 struct r600_context *rctx = (struct r600_context *)ctx;
3077 struct r600_texture *rsrc = (struct r600_texture*)src;
3078 struct r600_texture *rdst = (struct r600_texture*)dst;
3079 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3080 unsigned src_w, dst_w;
3081
3082 if (rctx->rings.dma.cs == NULL) {
3083 return FALSE;
3084 }
3085 if (src->format != dst->format) {
3086 return FALSE;
3087 }
3088
3089 bpp = rdst->surface.bpe;
3090 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
3091 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
3092 src_w = rsrc->surface.level[src_level].npix_x;
3093 dst_w = rdst->surface.level[dst_level].npix_x;
3094 copy_height = src_box->height / rsrc->surface.blk_h;
3095
3096 dst_mode = rdst->surface.level[dst_level].mode;
3097 src_mode = rsrc->surface.level[src_level].mode;
3098 /* downcast linear aligned to linear to simplify test */
3099 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3100 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3101
3102 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3103 /* strick requirement on r6xx/r7xx */
3104 return FALSE;
3105 }
3106 /* lot of constraint on alignment this should capture them all */
3107 if ((src_pitch & 0x7) || (src_box->y & 0x7) || (dst_y & 0x7)) {
3108 return FALSE;
3109 }
3110
3111 if (src_mode == dst_mode) {
3112 uint64_t dst_offset, src_offset, size;
3113
3114 /* simple dma blit would do NOTE code here assume :
3115 * src_box.x/y == 0
3116 * dst_x/y == 0
3117 * dst_pitch == src_pitch
3118 */
3119 src_offset= rsrc->surface.level[src_level].offset;
3120 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3121 src_offset += src_box->y * src_pitch + src_box->x * bpp;
3122 dst_offset = rdst->surface.level[dst_level].offset;
3123 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3124 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3125 size = src_box->height * src_pitch;
3126 /* must be dw aligned */
3127 if ((dst_offset & 0x3) || (src_offset & 0x3) || (size & 0x3)) {
3128 return FALSE;
3129 }
3130 r600_dma_copy(rctx, dst, src, dst_offset, src_offset, size);
3131 } else {
3132 return r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3133 src, src_level, src_box->x, src_box->y, src_box->z,
3134 copy_height, dst_pitch, bpp);
3135 }
3136 return TRUE;
3137 }