2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
24 #include "r600_shader.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
33 static uint32_t r600_translate_blend_function(int blend_func
)
37 return V_028804_COMB_DST_PLUS_SRC
;
38 case PIPE_BLEND_SUBTRACT
:
39 return V_028804_COMB_SRC_MINUS_DST
;
40 case PIPE_BLEND_REVERSE_SUBTRACT
:
41 return V_028804_COMB_DST_MINUS_SRC
;
43 return V_028804_COMB_MIN_DST_SRC
;
45 return V_028804_COMB_MAX_DST_SRC
;
47 R600_ERR("Unknown blend function %d\n", blend_func
);
54 static uint32_t r600_translate_blend_factor(int blend_fact
)
57 case PIPE_BLENDFACTOR_ONE
:
58 return V_028804_BLEND_ONE
;
59 case PIPE_BLENDFACTOR_SRC_COLOR
:
60 return V_028804_BLEND_SRC_COLOR
;
61 case PIPE_BLENDFACTOR_SRC_ALPHA
:
62 return V_028804_BLEND_SRC_ALPHA
;
63 case PIPE_BLENDFACTOR_DST_ALPHA
:
64 return V_028804_BLEND_DST_ALPHA
;
65 case PIPE_BLENDFACTOR_DST_COLOR
:
66 return V_028804_BLEND_DST_COLOR
;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE
;
69 case PIPE_BLENDFACTOR_CONST_COLOR
:
70 return V_028804_BLEND_CONST_COLOR
;
71 case PIPE_BLENDFACTOR_CONST_ALPHA
:
72 return V_028804_BLEND_CONST_ALPHA
;
73 case PIPE_BLENDFACTOR_ZERO
:
74 return V_028804_BLEND_ZERO
;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR
;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA
;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA
;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR
;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR
;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA
;
87 case PIPE_BLENDFACTOR_SRC1_COLOR
:
88 return V_028804_BLEND_SRC1_COLOR
;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
90 return V_028804_BLEND_SRC1_ALPHA
;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
92 return V_028804_BLEND_INV_SRC1_COLOR
;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
94 return V_028804_BLEND_INV_SRC1_ALPHA
;
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
103 static unsigned r600_tex_dim(unsigned dim
, unsigned nr_samples
)
107 case PIPE_TEXTURE_1D
:
108 return V_038000_SQ_TEX_DIM_1D
;
109 case PIPE_TEXTURE_1D_ARRAY
:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY
;
111 case PIPE_TEXTURE_2D
:
112 case PIPE_TEXTURE_RECT
:
113 return nr_samples
> 1 ? V_038000_SQ_TEX_DIM_2D_MSAA
:
114 V_038000_SQ_TEX_DIM_2D
;
115 case PIPE_TEXTURE_2D_ARRAY
:
116 return nr_samples
> 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
117 V_038000_SQ_TEX_DIM_2D_ARRAY
;
118 case PIPE_TEXTURE_3D
:
119 return V_038000_SQ_TEX_DIM_3D
;
120 case PIPE_TEXTURE_CUBE
:
121 case PIPE_TEXTURE_CUBE_ARRAY
:
122 return V_038000_SQ_TEX_DIM_CUBEMAP
;
126 static uint32_t r600_translate_dbformat(enum pipe_format format
)
129 case PIPE_FORMAT_Z16_UNORM
:
130 return V_028010_DEPTH_16
;
131 case PIPE_FORMAT_Z24X8_UNORM
:
132 return V_028010_DEPTH_X8_24
;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
134 return V_028010_DEPTH_8_24
;
135 case PIPE_FORMAT_Z32_FLOAT
:
136 return V_028010_DEPTH_32_FLOAT
;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
138 return V_028010_DEPTH_X24_8_32_FLOAT
;
144 static uint32_t r600_translate_colorswap(enum pipe_format format
)
148 case PIPE_FORMAT_A8_UNORM
:
149 case PIPE_FORMAT_A8_SNORM
:
150 case PIPE_FORMAT_A8_UINT
:
151 case PIPE_FORMAT_A8_SINT
:
152 case PIPE_FORMAT_A16_UNORM
:
153 case PIPE_FORMAT_A16_SNORM
:
154 case PIPE_FORMAT_A16_UINT
:
155 case PIPE_FORMAT_A16_SINT
:
156 case PIPE_FORMAT_A16_FLOAT
:
157 case PIPE_FORMAT_A32_UINT
:
158 case PIPE_FORMAT_A32_SINT
:
159 case PIPE_FORMAT_A32_FLOAT
:
160 case PIPE_FORMAT_R4A4_UNORM
:
161 return V_0280A0_SWAP_ALT_REV
;
162 case PIPE_FORMAT_I8_UNORM
:
163 case PIPE_FORMAT_I8_SNORM
:
164 case PIPE_FORMAT_I8_UINT
:
165 case PIPE_FORMAT_I8_SINT
:
166 case PIPE_FORMAT_L8_UNORM
:
167 case PIPE_FORMAT_L8_SNORM
:
168 case PIPE_FORMAT_L8_UINT
:
169 case PIPE_FORMAT_L8_SINT
:
170 case PIPE_FORMAT_L8_SRGB
:
171 case PIPE_FORMAT_L16_UNORM
:
172 case PIPE_FORMAT_L16_SNORM
:
173 case PIPE_FORMAT_L16_UINT
:
174 case PIPE_FORMAT_L16_SINT
:
175 case PIPE_FORMAT_L16_FLOAT
:
176 case PIPE_FORMAT_L32_UINT
:
177 case PIPE_FORMAT_L32_SINT
:
178 case PIPE_FORMAT_L32_FLOAT
:
179 case PIPE_FORMAT_I16_UNORM
:
180 case PIPE_FORMAT_I16_SNORM
:
181 case PIPE_FORMAT_I16_UINT
:
182 case PIPE_FORMAT_I16_SINT
:
183 case PIPE_FORMAT_I16_FLOAT
:
184 case PIPE_FORMAT_I32_UINT
:
185 case PIPE_FORMAT_I32_SINT
:
186 case PIPE_FORMAT_I32_FLOAT
:
187 case PIPE_FORMAT_R8_UNORM
:
188 case PIPE_FORMAT_R8_SNORM
:
189 case PIPE_FORMAT_R8_UINT
:
190 case PIPE_FORMAT_R8_SINT
:
191 return V_0280A0_SWAP_STD
;
193 case PIPE_FORMAT_L4A4_UNORM
:
194 case PIPE_FORMAT_A4R4_UNORM
:
195 return V_0280A0_SWAP_ALT
;
197 /* 16-bit buffers. */
198 case PIPE_FORMAT_B5G6R5_UNORM
:
199 return V_0280A0_SWAP_STD_REV
;
201 case PIPE_FORMAT_B5G5R5A1_UNORM
:
202 case PIPE_FORMAT_B5G5R5X1_UNORM
:
203 return V_0280A0_SWAP_ALT
;
205 case PIPE_FORMAT_B4G4R4A4_UNORM
:
206 case PIPE_FORMAT_B4G4R4X4_UNORM
:
207 return V_0280A0_SWAP_ALT
;
209 case PIPE_FORMAT_Z16_UNORM
:
210 return V_0280A0_SWAP_STD
;
212 case PIPE_FORMAT_L8A8_UNORM
:
213 case PIPE_FORMAT_L8A8_SNORM
:
214 case PIPE_FORMAT_L8A8_UINT
:
215 case PIPE_FORMAT_L8A8_SINT
:
216 case PIPE_FORMAT_L8A8_SRGB
:
217 case PIPE_FORMAT_L16A16_UNORM
:
218 case PIPE_FORMAT_L16A16_SNORM
:
219 case PIPE_FORMAT_L16A16_UINT
:
220 case PIPE_FORMAT_L16A16_SINT
:
221 case PIPE_FORMAT_L16A16_FLOAT
:
222 case PIPE_FORMAT_L32A32_UINT
:
223 case PIPE_FORMAT_L32A32_SINT
:
224 case PIPE_FORMAT_L32A32_FLOAT
:
225 case PIPE_FORMAT_R8A8_UNORM
:
226 case PIPE_FORMAT_R8A8_SNORM
:
227 case PIPE_FORMAT_R8A8_UINT
:
228 case PIPE_FORMAT_R8A8_SINT
:
229 case PIPE_FORMAT_R16A16_UNORM
:
230 case PIPE_FORMAT_R16A16_SNORM
:
231 case PIPE_FORMAT_R16A16_UINT
:
232 case PIPE_FORMAT_R16A16_SINT
:
233 case PIPE_FORMAT_R16A16_FLOAT
:
234 case PIPE_FORMAT_R32A32_UINT
:
235 case PIPE_FORMAT_R32A32_SINT
:
236 case PIPE_FORMAT_R32A32_FLOAT
:
237 return V_0280A0_SWAP_ALT
;
238 case PIPE_FORMAT_R8G8_UNORM
:
239 case PIPE_FORMAT_R8G8_SNORM
:
240 case PIPE_FORMAT_R8G8_UINT
:
241 case PIPE_FORMAT_R8G8_SINT
:
242 return V_0280A0_SWAP_STD
;
244 case PIPE_FORMAT_R16_UNORM
:
245 case PIPE_FORMAT_R16_SNORM
:
246 case PIPE_FORMAT_R16_UINT
:
247 case PIPE_FORMAT_R16_SINT
:
248 case PIPE_FORMAT_R16_FLOAT
:
249 return V_0280A0_SWAP_STD
;
251 /* 32-bit buffers. */
253 case PIPE_FORMAT_A8B8G8R8_SRGB
:
254 return V_0280A0_SWAP_STD_REV
;
255 case PIPE_FORMAT_B8G8R8A8_SRGB
:
256 return V_0280A0_SWAP_ALT
;
258 case PIPE_FORMAT_B8G8R8A8_UNORM
:
259 case PIPE_FORMAT_B8G8R8X8_UNORM
:
260 return V_0280A0_SWAP_ALT
;
262 case PIPE_FORMAT_A8R8G8B8_UNORM
:
263 case PIPE_FORMAT_X8R8G8B8_UNORM
:
264 return V_0280A0_SWAP_ALT_REV
;
265 case PIPE_FORMAT_R8G8B8A8_SNORM
:
266 case PIPE_FORMAT_R8G8B8A8_UNORM
:
267 case PIPE_FORMAT_R8G8B8X8_UNORM
:
268 case PIPE_FORMAT_R8G8B8X8_SNORM
:
269 case PIPE_FORMAT_R8G8B8X8_SRGB
:
270 case PIPE_FORMAT_R8G8B8X8_UINT
:
271 case PIPE_FORMAT_R8G8B8X8_SINT
:
272 case PIPE_FORMAT_R8G8B8A8_SINT
:
273 case PIPE_FORMAT_R8G8B8A8_UINT
:
274 return V_0280A0_SWAP_STD
;
276 case PIPE_FORMAT_A8B8G8R8_UNORM
:
277 case PIPE_FORMAT_X8B8G8R8_UNORM
:
278 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
279 return V_0280A0_SWAP_STD_REV
;
281 case PIPE_FORMAT_Z24X8_UNORM
:
282 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
283 return V_0280A0_SWAP_STD
;
285 case PIPE_FORMAT_R10G10B10A2_UNORM
:
286 case PIPE_FORMAT_R10G10B10X2_SNORM
:
287 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
288 return V_0280A0_SWAP_STD
;
290 case PIPE_FORMAT_B10G10R10A2_UNORM
:
291 case PIPE_FORMAT_B10G10R10A2_UINT
:
292 case PIPE_FORMAT_B10G10R10X2_UNORM
:
293 return V_0280A0_SWAP_ALT
;
295 case PIPE_FORMAT_R11G11B10_FLOAT
:
296 case PIPE_FORMAT_R16G16_UNORM
:
297 case PIPE_FORMAT_R16G16_SNORM
:
298 case PIPE_FORMAT_R16G16_FLOAT
:
299 case PIPE_FORMAT_R16G16_UINT
:
300 case PIPE_FORMAT_R16G16_SINT
:
301 case PIPE_FORMAT_R32_UINT
:
302 case PIPE_FORMAT_R32_SINT
:
303 case PIPE_FORMAT_R32_FLOAT
:
304 case PIPE_FORMAT_Z32_FLOAT
:
305 return V_0280A0_SWAP_STD
;
307 /* 64-bit buffers. */
308 case PIPE_FORMAT_R32G32_FLOAT
:
309 case PIPE_FORMAT_R32G32_UINT
:
310 case PIPE_FORMAT_R32G32_SINT
:
311 case PIPE_FORMAT_R16G16B16A16_UNORM
:
312 case PIPE_FORMAT_R16G16B16A16_SNORM
:
313 case PIPE_FORMAT_R16G16B16A16_UINT
:
314 case PIPE_FORMAT_R16G16B16A16_SINT
:
315 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
316 case PIPE_FORMAT_R16G16B16X16_UNORM
:
317 case PIPE_FORMAT_R16G16B16X16_SNORM
:
318 case PIPE_FORMAT_R16G16B16X16_FLOAT
:
319 case PIPE_FORMAT_R16G16B16X16_UINT
:
320 case PIPE_FORMAT_R16G16B16X16_SINT
:
321 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
323 /* 128-bit buffers. */
324 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
325 case PIPE_FORMAT_R32G32B32A32_SNORM
:
326 case PIPE_FORMAT_R32G32B32A32_UNORM
:
327 case PIPE_FORMAT_R32G32B32A32_SINT
:
328 case PIPE_FORMAT_R32G32B32A32_UINT
:
329 case PIPE_FORMAT_R32G32B32X32_FLOAT
:
330 case PIPE_FORMAT_R32G32B32X32_UINT
:
331 case PIPE_FORMAT_R32G32B32X32_SINT
:
332 return V_0280A0_SWAP_STD
;
334 R600_ERR("unsupported colorswap format %d\n", format
);
340 static uint32_t r600_translate_colorformat(enum pipe_format format
)
343 case PIPE_FORMAT_L4A4_UNORM
:
344 case PIPE_FORMAT_R4A4_UNORM
:
345 case PIPE_FORMAT_A4R4_UNORM
:
346 return V_0280A0_COLOR_4_4
;
349 case PIPE_FORMAT_A8_UNORM
:
350 case PIPE_FORMAT_A8_SNORM
:
351 case PIPE_FORMAT_A8_UINT
:
352 case PIPE_FORMAT_A8_SINT
:
353 case PIPE_FORMAT_I8_UNORM
:
354 case PIPE_FORMAT_I8_SNORM
:
355 case PIPE_FORMAT_I8_UINT
:
356 case PIPE_FORMAT_I8_SINT
:
357 case PIPE_FORMAT_L8_UNORM
:
358 case PIPE_FORMAT_L8_SNORM
:
359 case PIPE_FORMAT_L8_UINT
:
360 case PIPE_FORMAT_L8_SINT
:
361 case PIPE_FORMAT_L8_SRGB
:
362 case PIPE_FORMAT_R8_UNORM
:
363 case PIPE_FORMAT_R8_SNORM
:
364 case PIPE_FORMAT_R8_UINT
:
365 case PIPE_FORMAT_R8_SINT
:
366 return V_0280A0_COLOR_8
;
368 /* 16-bit buffers. */
369 case PIPE_FORMAT_B5G6R5_UNORM
:
370 return V_0280A0_COLOR_5_6_5
;
372 case PIPE_FORMAT_B5G5R5A1_UNORM
:
373 case PIPE_FORMAT_B5G5R5X1_UNORM
:
374 return V_0280A0_COLOR_1_5_5_5
;
376 case PIPE_FORMAT_B4G4R4A4_UNORM
:
377 case PIPE_FORMAT_B4G4R4X4_UNORM
:
378 return V_0280A0_COLOR_4_4_4_4
;
380 case PIPE_FORMAT_Z16_UNORM
:
381 return V_0280A0_COLOR_16
;
383 case PIPE_FORMAT_L8A8_UNORM
:
384 case PIPE_FORMAT_L8A8_SNORM
:
385 case PIPE_FORMAT_L8A8_UINT
:
386 case PIPE_FORMAT_L8A8_SINT
:
387 case PIPE_FORMAT_L8A8_SRGB
:
388 case PIPE_FORMAT_R8G8_UNORM
:
389 case PIPE_FORMAT_R8G8_SNORM
:
390 case PIPE_FORMAT_R8G8_UINT
:
391 case PIPE_FORMAT_R8G8_SINT
:
392 case PIPE_FORMAT_R8A8_UNORM
:
393 case PIPE_FORMAT_R8A8_SNORM
:
394 case PIPE_FORMAT_R8A8_UINT
:
395 case PIPE_FORMAT_R8A8_SINT
:
396 return V_0280A0_COLOR_8_8
;
398 case PIPE_FORMAT_R16_UNORM
:
399 case PIPE_FORMAT_R16_SNORM
:
400 case PIPE_FORMAT_R16_UINT
:
401 case PIPE_FORMAT_R16_SINT
:
402 case PIPE_FORMAT_A16_UNORM
:
403 case PIPE_FORMAT_A16_SNORM
:
404 case PIPE_FORMAT_A16_UINT
:
405 case PIPE_FORMAT_A16_SINT
:
406 case PIPE_FORMAT_L16_UNORM
:
407 case PIPE_FORMAT_L16_SNORM
:
408 case PIPE_FORMAT_L16_UINT
:
409 case PIPE_FORMAT_L16_SINT
:
410 case PIPE_FORMAT_I16_UNORM
:
411 case PIPE_FORMAT_I16_SNORM
:
412 case PIPE_FORMAT_I16_UINT
:
413 case PIPE_FORMAT_I16_SINT
:
414 return V_0280A0_COLOR_16
;
416 case PIPE_FORMAT_R16_FLOAT
:
417 case PIPE_FORMAT_A16_FLOAT
:
418 case PIPE_FORMAT_L16_FLOAT
:
419 case PIPE_FORMAT_I16_FLOAT
:
420 return V_0280A0_COLOR_16_FLOAT
;
422 /* 32-bit buffers. */
423 case PIPE_FORMAT_A8B8G8R8_SRGB
:
424 case PIPE_FORMAT_A8B8G8R8_UNORM
:
425 case PIPE_FORMAT_A8R8G8B8_UNORM
:
426 case PIPE_FORMAT_B8G8R8A8_SRGB
:
427 case PIPE_FORMAT_B8G8R8A8_UNORM
:
428 case PIPE_FORMAT_B8G8R8X8_UNORM
:
429 case PIPE_FORMAT_R8G8B8A8_SNORM
:
430 case PIPE_FORMAT_R8G8B8A8_UNORM
:
431 case PIPE_FORMAT_R8G8B8X8_UNORM
:
432 case PIPE_FORMAT_R8G8B8X8_SNORM
:
433 case PIPE_FORMAT_R8G8B8X8_SRGB
:
434 case PIPE_FORMAT_R8G8B8X8_UINT
:
435 case PIPE_FORMAT_R8G8B8X8_SINT
:
436 case PIPE_FORMAT_R8SG8SB8UX8U_NORM
:
437 case PIPE_FORMAT_X8B8G8R8_UNORM
:
438 case PIPE_FORMAT_X8R8G8B8_UNORM
:
439 case PIPE_FORMAT_R8G8B8A8_SINT
:
440 case PIPE_FORMAT_R8G8B8A8_UINT
:
441 return V_0280A0_COLOR_8_8_8_8
;
443 case PIPE_FORMAT_R10G10B10A2_UNORM
:
444 case PIPE_FORMAT_R10G10B10X2_SNORM
:
445 case PIPE_FORMAT_B10G10R10A2_UNORM
:
446 case PIPE_FORMAT_B10G10R10A2_UINT
:
447 case PIPE_FORMAT_B10G10R10X2_UNORM
:
448 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
449 return V_0280A0_COLOR_2_10_10_10
;
451 case PIPE_FORMAT_Z24X8_UNORM
:
452 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
453 return V_0280A0_COLOR_8_24
;
455 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
456 return V_0280A0_COLOR_X24_8_32_FLOAT
;
458 case PIPE_FORMAT_R32_UINT
:
459 case PIPE_FORMAT_R32_SINT
:
460 case PIPE_FORMAT_A32_UINT
:
461 case PIPE_FORMAT_A32_SINT
:
462 case PIPE_FORMAT_L32_UINT
:
463 case PIPE_FORMAT_L32_SINT
:
464 case PIPE_FORMAT_I32_UINT
:
465 case PIPE_FORMAT_I32_SINT
:
466 return V_0280A0_COLOR_32
;
468 case PIPE_FORMAT_R32_FLOAT
:
469 case PIPE_FORMAT_A32_FLOAT
:
470 case PIPE_FORMAT_L32_FLOAT
:
471 case PIPE_FORMAT_I32_FLOAT
:
472 case PIPE_FORMAT_Z32_FLOAT
:
473 return V_0280A0_COLOR_32_FLOAT
;
475 case PIPE_FORMAT_R16G16_FLOAT
:
476 case PIPE_FORMAT_L16A16_FLOAT
:
477 case PIPE_FORMAT_R16A16_FLOAT
:
478 return V_0280A0_COLOR_16_16_FLOAT
;
480 case PIPE_FORMAT_R16G16_UNORM
:
481 case PIPE_FORMAT_R16G16_SNORM
:
482 case PIPE_FORMAT_R16G16_UINT
:
483 case PIPE_FORMAT_R16G16_SINT
:
484 case PIPE_FORMAT_L16A16_UNORM
:
485 case PIPE_FORMAT_L16A16_SNORM
:
486 case PIPE_FORMAT_L16A16_UINT
:
487 case PIPE_FORMAT_L16A16_SINT
:
488 case PIPE_FORMAT_R16A16_UNORM
:
489 case PIPE_FORMAT_R16A16_SNORM
:
490 case PIPE_FORMAT_R16A16_UINT
:
491 case PIPE_FORMAT_R16A16_SINT
:
492 return V_0280A0_COLOR_16_16
;
494 case PIPE_FORMAT_R11G11B10_FLOAT
:
495 return V_0280A0_COLOR_10_11_11_FLOAT
;
497 /* 64-bit buffers. */
498 case PIPE_FORMAT_R16G16B16A16_UINT
:
499 case PIPE_FORMAT_R16G16B16A16_SINT
:
500 case PIPE_FORMAT_R16G16B16A16_UNORM
:
501 case PIPE_FORMAT_R16G16B16A16_SNORM
:
502 case PIPE_FORMAT_R16G16B16X16_UNORM
:
503 case PIPE_FORMAT_R16G16B16X16_SNORM
:
504 case PIPE_FORMAT_R16G16B16X16_UINT
:
505 case PIPE_FORMAT_R16G16B16X16_SINT
:
506 return V_0280A0_COLOR_16_16_16_16
;
508 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
509 case PIPE_FORMAT_R16G16B16X16_FLOAT
:
510 return V_0280A0_COLOR_16_16_16_16_FLOAT
;
512 case PIPE_FORMAT_R32G32_FLOAT
:
513 case PIPE_FORMAT_L32A32_FLOAT
:
514 case PIPE_FORMAT_R32A32_FLOAT
:
515 return V_0280A0_COLOR_32_32_FLOAT
;
517 case PIPE_FORMAT_R32G32_SINT
:
518 case PIPE_FORMAT_R32G32_UINT
:
519 case PIPE_FORMAT_L32A32_UINT
:
520 case PIPE_FORMAT_L32A32_SINT
:
521 return V_0280A0_COLOR_32_32
;
523 /* 128-bit buffers. */
524 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
525 case PIPE_FORMAT_R32G32B32X32_FLOAT
:
526 return V_0280A0_COLOR_32_32_32_32_FLOAT
;
527 case PIPE_FORMAT_R32G32B32A32_SNORM
:
528 case PIPE_FORMAT_R32G32B32A32_UNORM
:
529 case PIPE_FORMAT_R32G32B32A32_SINT
:
530 case PIPE_FORMAT_R32G32B32A32_UINT
:
531 case PIPE_FORMAT_R32G32B32X32_UINT
:
532 case PIPE_FORMAT_R32G32B32X32_SINT
:
533 return V_0280A0_COLOR_32_32_32_32
;
536 case PIPE_FORMAT_UYVY
:
537 case PIPE_FORMAT_YUYV
:
539 return ~0U; /* Unsupported. */
543 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat
)
545 if (R600_BIG_ENDIAN
) {
546 switch(colorformat
) {
547 case V_0280A0_COLOR_4_4
:
551 case V_0280A0_COLOR_8
:
554 /* 16-bit buffers. */
555 case V_0280A0_COLOR_5_6_5
:
556 case V_0280A0_COLOR_1_5_5_5
:
557 case V_0280A0_COLOR_4_4_4_4
:
558 case V_0280A0_COLOR_16
:
559 case V_0280A0_COLOR_8_8
:
562 /* 32-bit buffers. */
563 case V_0280A0_COLOR_8_8_8_8
:
564 case V_0280A0_COLOR_2_10_10_10
:
565 case V_0280A0_COLOR_8_24
:
566 case V_0280A0_COLOR_24_8
:
567 case V_0280A0_COLOR_32_FLOAT
:
568 case V_0280A0_COLOR_16_16_FLOAT
:
569 case V_0280A0_COLOR_16_16
:
572 /* 64-bit buffers. */
573 case V_0280A0_COLOR_16_16_16_16
:
574 case V_0280A0_COLOR_16_16_16_16_FLOAT
:
577 case V_0280A0_COLOR_32_32_FLOAT
:
578 case V_0280A0_COLOR_32_32
:
579 case V_0280A0_COLOR_X24_8_32_FLOAT
:
582 /* 128-bit buffers. */
583 case V_0280A0_COLOR_32_32_32_FLOAT
:
584 case V_0280A0_COLOR_32_32_32_32_FLOAT
:
585 case V_0280A0_COLOR_32_32_32_32
:
588 return ENDIAN_NONE
; /* Unsupported. */
595 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
597 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
) != ~0U;
600 static bool r600_is_colorbuffer_format_supported(enum pipe_format format
)
602 return r600_translate_colorformat(format
) != ~0U &&
603 r600_translate_colorswap(format
) != ~0U;
606 static bool r600_is_zs_format_supported(enum pipe_format format
)
608 return r600_translate_dbformat(format
) != ~0U;
611 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
612 enum pipe_format format
,
613 enum pipe_texture_target target
,
614 unsigned sample_count
,
617 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
620 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
621 R600_ERR("r600: unsupported texture type %d\n", target
);
625 if (!util_format_is_supported(format
, usage
))
628 if (sample_count
> 1) {
629 if (!rscreen
->has_msaa
)
632 /* R11G11B10 is broken on R6xx. */
633 if (rscreen
->chip_class
== R600
&&
634 format
== PIPE_FORMAT_R11G11B10_FLOAT
)
637 /* MSAA integer colorbuffers hang. */
638 if (util_format_is_pure_integer(format
) &&
639 !util_format_is_depth_or_stencil(format
))
642 switch (sample_count
) {
652 if ((usage
& PIPE_BIND_SAMPLER_VIEW
) &&
653 r600_is_sampler_format_supported(screen
, format
)) {
654 retval
|= PIPE_BIND_SAMPLER_VIEW
;
657 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
658 PIPE_BIND_DISPLAY_TARGET
|
660 PIPE_BIND_SHARED
)) &&
661 r600_is_colorbuffer_format_supported(format
)) {
663 (PIPE_BIND_RENDER_TARGET
|
664 PIPE_BIND_DISPLAY_TARGET
|
669 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
670 r600_is_zs_format_supported(format
)) {
671 retval
|= PIPE_BIND_DEPTH_STENCIL
;
674 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
675 r600_is_vertex_format_supported(format
)) {
676 retval
|= PIPE_BIND_VERTEX_BUFFER
;
679 if (usage
& PIPE_BIND_TRANSFER_READ
)
680 retval
|= PIPE_BIND_TRANSFER_READ
;
681 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
682 retval
|= PIPE_BIND_TRANSFER_WRITE
;
684 return retval
== usage
;
687 static void r600_emit_polygon_offset(struct r600_context
*rctx
, struct r600_atom
*a
)
689 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
690 struct r600_poly_offset_state
*state
= (struct r600_poly_offset_state
*)a
;
691 float offset_units
= state
->offset_units
;
692 float offset_scale
= state
->offset_scale
;
694 switch (state
->zs_format
) {
695 case PIPE_FORMAT_Z24X8_UNORM
:
696 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
697 offset_units
*= 2.0f
;
699 case PIPE_FORMAT_Z16_UNORM
:
700 offset_units
*= 4.0f
;
705 r600_write_context_reg_seq(cs
, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE
, 4);
706 r600_write_value(cs
, fui(offset_scale
));
707 r600_write_value(cs
, fui(offset_units
));
708 r600_write_value(cs
, fui(offset_scale
));
709 r600_write_value(cs
, fui(offset_units
));
712 static uint32_t r600_get_blend_control(const struct pipe_blend_state
*state
, unsigned i
)
714 int j
= state
->independent_blend_enable
? i
: 0;
716 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
717 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
718 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
720 unsigned eqA
= state
->rt
[j
].alpha_func
;
721 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
722 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
725 if (!state
->rt
[j
].blend_enable
)
728 bc
|= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
729 bc
|= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
730 bc
|= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
732 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
733 bc
|= S_028804_SEPARATE_ALPHA_BLEND(1);
734 bc
|= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
735 bc
|= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
736 bc
|= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
741 static void *r600_create_blend_state_mode(struct pipe_context
*ctx
,
742 const struct pipe_blend_state
*state
,
745 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
746 uint32_t color_control
= 0, target_mask
= 0;
747 struct r600_blend_state
*blend
= CALLOC_STRUCT(r600_blend_state
);
753 r600_init_command_buffer(&blend
->buffer
, 20);
754 r600_init_command_buffer(&blend
->buffer_no_blend
, 20);
756 /* R600 does not support per-MRT blends */
757 if (rctx
->family
> CHIP_R600
)
758 color_control
|= S_028808_PER_MRT_BLEND(1);
760 if (state
->logicop_enable
) {
761 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
763 color_control
|= (0xcc << 16);
765 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
766 if (state
->independent_blend_enable
) {
767 for (int i
= 0; i
< 8; i
++) {
768 if (state
->rt
[i
].blend_enable
) {
769 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
771 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
774 for (int i
= 0; i
< 8; i
++) {
775 if (state
->rt
[0].blend_enable
) {
776 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
778 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
783 color_control
|= S_028808_SPECIAL_OP(mode
);
785 color_control
|= S_028808_SPECIAL_OP(V_028808_DISABLE
);
787 /* only MRT0 has dual src blend */
788 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
789 blend
->cb_target_mask
= target_mask
;
790 blend
->cb_color_control
= color_control
;
791 blend
->cb_color_control_no_blend
= color_control
& C_028808_TARGET_BLEND_ENABLE
;
792 blend
->alpha_to_one
= state
->alpha_to_one
;
794 r600_store_context_reg(&blend
->buffer
, R_028D44_DB_ALPHA_TO_MASK
,
795 S_028D44_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
796 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
797 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
798 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
799 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
801 /* Copy over the registers set so far into buffer_no_blend. */
802 memcpy(blend
->buffer_no_blend
.buf
, blend
->buffer
.buf
, blend
->buffer
.num_dw
* 4);
803 blend
->buffer_no_blend
.num_dw
= blend
->buffer
.num_dw
;
805 /* Only add blend registers if blending is enabled. */
806 if (!G_028808_TARGET_BLEND_ENABLE(color_control
)) {
810 /* The first R600 does not support per-MRT blends */
811 r600_store_context_reg(&blend
->buffer
, R_028804_CB_BLEND_CONTROL
,
812 r600_get_blend_control(state
, 0));
814 if (rctx
->family
> CHIP_R600
) {
815 r600_store_context_reg_seq(&blend
->buffer
, R_028780_CB_BLEND0_CONTROL
, 8);
816 for (int i
= 0; i
< 8; i
++) {
817 r600_store_value(&blend
->buffer
, r600_get_blend_control(state
, i
));
823 static void *r600_create_blend_state(struct pipe_context
*ctx
,
824 const struct pipe_blend_state
*state
)
826 return r600_create_blend_state_mode(ctx
, state
, V_028808_SPECIAL_NORMAL
);
829 static void *r600_create_dsa_state(struct pipe_context
*ctx
,
830 const struct pipe_depth_stencil_alpha_state
*state
)
832 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
833 struct r600_dsa_state
*dsa
= CALLOC_STRUCT(r600_dsa_state
);
839 r600_init_command_buffer(&dsa
->buffer
, 3);
841 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
842 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
843 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
844 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
845 dsa
->zwritemask
= state
->depth
.writemask
;
847 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
848 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
849 S_028800_ZFUNC(state
->depth
.func
);
852 if (state
->stencil
[0].enabled
) {
853 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
854 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
855 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
856 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
857 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
859 if (state
->stencil
[1].enabled
) {
860 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
861 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
862 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
863 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
864 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
869 alpha_test_control
= 0;
871 if (state
->alpha
.enabled
) {
872 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
873 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
874 alpha_ref
= fui(state
->alpha
.ref_value
);
876 dsa
->sx_alpha_test_control
= alpha_test_control
& 0xff;
877 dsa
->alpha_ref
= alpha_ref
;
879 r600_store_context_reg(&dsa
->buffer
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
883 static void *r600_create_rs_state(struct pipe_context
*ctx
,
884 const struct pipe_rasterizer_state
*state
)
886 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
887 unsigned tmp
, sc_mode_cntl
, spi_interp
;
888 float psize_min
, psize_max
;
889 struct r600_rasterizer_state
*rs
= CALLOC_STRUCT(r600_rasterizer_state
);
895 r600_init_command_buffer(&rs
->buffer
, 30);
897 rs
->flatshade
= state
->flatshade
;
898 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
899 rs
->two_side
= state
->light_twoside
;
900 rs
->clip_plane_enable
= state
->clip_plane_enable
;
901 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
902 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
903 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
904 rs
->pa_cl_clip_cntl
=
905 S_028810_PS_UCP_MODE(3) |
906 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
907 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
908 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
909 rs
->multisample_enable
= state
->multisample
;
912 rs
->offset_units
= state
->offset_units
;
913 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
914 rs
->offset_enable
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
916 if (state
->point_size_per_vertex
) {
917 psize_min
= util_get_min_point_size(state
);
920 /* Force the point size to be as if the vertex output was disabled. */
921 psize_min
= state
->point_size
;
922 psize_max
= state
->point_size
;
925 sc_mode_cntl
= S_028A4C_MSAA_ENABLE(state
->multisample
) |
926 S_028A4C_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
927 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
928 if (rctx
->chip_class
>= R700
) {
929 sc_mode_cntl
|= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
930 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
931 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state
->scissor
);
933 sc_mode_cntl
|= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
934 rs
->scissor_enable
= state
->scissor
;
937 spi_interp
= S_0286D4_FLAT_SHADE_ENA(1);
938 if (state
->sprite_coord_enable
) {
939 spi_interp
|= S_0286D4_PNT_SPRITE_ENA(1) |
940 S_0286D4_PNT_SPRITE_OVRD_X(2) |
941 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
942 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
943 S_0286D4_PNT_SPRITE_OVRD_W(1);
944 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
945 spi_interp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
949 r600_store_context_reg_seq(&rs
->buffer
, R_028A00_PA_SU_POINT_SIZE
, 3);
950 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
951 tmp
= r600_pack_float_12p4(state
->point_size
/2);
952 r600_store_value(&rs
->buffer
, /* R_028A00_PA_SU_POINT_SIZE */
953 S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
954 r600_store_value(&rs
->buffer
, /* R_028A04_PA_SU_POINT_MINMAX */
955 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
956 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
957 r600_store_value(&rs
->buffer
, /* R_028A08_PA_SU_LINE_CNTL */
958 S_028A08_WIDTH(r600_pack_float_12p4(state
->line_width
/2)));
960 r600_store_context_reg(&rs
->buffer
, R_0286D4_SPI_INTERP_CONTROL_0
, spi_interp
);
961 r600_store_context_reg(&rs
->buffer
, R_028A4C_PA_SC_MODE_CNTL
, sc_mode_cntl
);
962 r600_store_context_reg(&rs
->buffer
, R_028C08_PA_SU_VTX_CNTL
,
963 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
) |
964 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
965 r600_store_context_reg(&rs
->buffer
, R_028DFC_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
966 r600_store_context_reg(&rs
->buffer
, R_028814_PA_SU_SC_MODE_CNTL
,
967 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
968 S_028814_CULL_FRONT(state
->cull_face
& PIPE_FACE_FRONT
? 1 : 0) |
969 S_028814_CULL_BACK(state
->cull_face
& PIPE_FACE_BACK
? 1 : 0) |
970 S_028814_FACE(!state
->front_ccw
) |
971 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
972 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
973 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
974 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
975 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
976 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
977 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)));
978 r600_store_context_reg(&rs
->buffer
, R_028350_SX_MISC
, S_028350_MULTIPASS(state
->rasterizer_discard
));
982 static void *r600_create_sampler_state(struct pipe_context
*ctx
,
983 const struct pipe_sampler_state
*state
)
985 struct r600_pipe_sampler_state
*ss
= CALLOC_STRUCT(r600_pipe_sampler_state
);
986 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 4 : 0;
992 ss
->seamless_cube_map
= state
->seamless_cube_map
;
993 ss
->border_color_use
= sampler_state_needs_border_color(state
);
995 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
996 ss
->tex_sampler_words
[0] =
997 S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
998 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
999 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
1000 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
1001 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
1002 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
1003 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
1004 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
1005 S_03C000_BORDER_COLOR_TYPE(ss
->border_color_use
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0);
1006 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
1007 ss
->tex_sampler_words
[1] =
1008 S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 6)) |
1009 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 6)) |
1010 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 6));
1011 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
1012 ss
->tex_sampler_words
[2] = S_03C008_TYPE(1);
1014 if (ss
->border_color_use
) {
1015 memcpy(&ss
->border_color
, &state
->border_color
, sizeof(state
->border_color
));
1020 static struct pipe_sampler_view
*
1021 texture_buffer_sampler_view(struct r600_pipe_sampler_view
*view
,
1022 unsigned width0
, unsigned height0
)
1025 struct pipe_context
*ctx
= view
->base
.context
;
1026 struct r600_texture
*tmp
= (struct r600_texture
*)view
->base
.texture
;
1028 int stride
= util_format_get_blocksize(view
->base
.format
);
1029 unsigned format
, num_format
, format_comp
, endian
;
1031 r600_vertex_data_type(view
->base
.format
,
1032 &format
, &num_format
, &format_comp
,
1035 va
= r600_resource_va(ctx
->screen
, view
->base
.texture
);
1036 view
->tex_resource
= &tmp
->resource
;
1038 view
->skip_mip_address_reloc
= true;
1039 view
->tex_resource_words
[0] = va
;
1040 view
->tex_resource_words
[1] = width0
- 1;
1041 view
->tex_resource_words
[2] = S_038008_BASE_ADDRESS_HI(va
>> 32UL) |
1042 S_038008_STRIDE(stride
) |
1043 S_038008_DATA_FORMAT(format
) |
1044 S_038008_NUM_FORMAT_ALL(num_format
) |
1045 S_038008_FORMAT_COMP_ALL(format_comp
) |
1046 S_038008_SRF_MODE_ALL(1) |
1047 S_038008_ENDIAN_SWAP(endian
);
1048 view
->tex_resource_words
[3] = 0;
1050 * in theory dword 4 is for number of elements, for use with resinfo,
1051 * but it seems to utterly fail to work, the amd gpu shader analyser
1052 * uses a const buffer to store the element sizes for buffer txq
1054 view
->tex_resource_words
[4] = 0;
1055 view
->tex_resource_words
[5] = 0;
1056 view
->tex_resource_words
[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER
);
1060 struct pipe_sampler_view
*
1061 r600_create_sampler_view_custom(struct pipe_context
*ctx
,
1062 struct pipe_resource
*texture
,
1063 const struct pipe_sampler_view
*state
,
1064 unsigned width_first_level
, unsigned height_first_level
)
1066 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
1067 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
1068 unsigned format
, endian
;
1069 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
1070 unsigned char swizzle
[4], array_mode
= 0;
1071 unsigned width
, height
, depth
, offset_level
, last_level
;
1076 /* initialize base object */
1077 view
->base
= *state
;
1078 view
->base
.texture
= NULL
;
1079 pipe_reference(NULL
, &texture
->reference
);
1080 view
->base
.texture
= texture
;
1081 view
->base
.reference
.count
= 1;
1082 view
->base
.context
= ctx
;
1084 if (texture
->target
== PIPE_BUFFER
)
1085 return texture_buffer_sampler_view(view
, texture
->width0
, 1);
1087 swizzle
[0] = state
->swizzle_r
;
1088 swizzle
[1] = state
->swizzle_g
;
1089 swizzle
[2] = state
->swizzle_b
;
1090 swizzle
[3] = state
->swizzle_a
;
1092 format
= r600_translate_texformat(ctx
->screen
, state
->format
,
1094 &word4
, &yuv_format
);
1095 assert(format
!= ~0);
1101 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
&& !r600_can_read_depth(tmp
)) {
1102 if (!r600_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
1106 tmp
= tmp
->flushed_depth_texture
;
1109 endian
= r600_colorformat_endian_swap(format
);
1111 offset_level
= state
->u
.tex
.first_level
;
1112 last_level
= state
->u
.tex
.last_level
- offset_level
;
1113 width
= width_first_level
;
1114 height
= height_first_level
;
1115 depth
= u_minify(texture
->depth0
, offset_level
);
1116 pitch
= tmp
->surface
.level
[offset_level
].nblk_x
* util_format_get_blockwidth(state
->format
);
1118 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
1120 depth
= texture
->array_size
;
1121 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
1122 depth
= texture
->array_size
;
1123 } else if (texture
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
1124 depth
= texture
->array_size
/ 6;
1125 switch (tmp
->surface
.level
[offset_level
].mode
) {
1126 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1127 array_mode
= V_038000_ARRAY_LINEAR_ALIGNED
;
1129 case RADEON_SURF_MODE_1D
:
1130 array_mode
= V_038000_ARRAY_1D_TILED_THIN1
;
1132 case RADEON_SURF_MODE_2D
:
1133 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
1135 case RADEON_SURF_MODE_LINEAR
:
1137 array_mode
= V_038000_ARRAY_LINEAR_GENERAL
;
1141 view
->tex_resource
= &tmp
->resource
;
1142 view
->tex_resource_words
[0] = (S_038000_DIM(r600_tex_dim(texture
->target
, texture
->nr_samples
)) |
1143 S_038000_TILE_MODE(array_mode
) |
1144 S_038000_TILE_TYPE(tmp
->non_disp_tiling
) |
1145 S_038000_PITCH((pitch
/ 8) - 1) |
1146 S_038000_TEX_WIDTH(width
- 1));
1147 view
->tex_resource_words
[1] = (S_038004_TEX_HEIGHT(height
- 1) |
1148 S_038004_TEX_DEPTH(depth
- 1) |
1149 S_038004_DATA_FORMAT(format
));
1150 view
->tex_resource_words
[2] = tmp
->surface
.level
[offset_level
].offset
>> 8;
1151 if (offset_level
>= tmp
->surface
.last_level
) {
1152 view
->tex_resource_words
[3] = tmp
->surface
.level
[offset_level
].offset
>> 8;
1154 view
->tex_resource_words
[3] = tmp
->surface
.level
[offset_level
+ 1].offset
>> 8;
1156 view
->tex_resource_words
[4] = (word4
|
1157 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE
) |
1158 S_038010_REQUEST_SIZE(1) |
1159 S_038010_ENDIAN_SWAP(endian
) |
1160 S_038010_BASE_LEVEL(0));
1161 view
->tex_resource_words
[5] = (S_038014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
1162 S_038014_LAST_ARRAY(state
->u
.tex
.last_layer
));
1163 if (texture
->nr_samples
> 1) {
1164 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1165 view
->tex_resource_words
[5] |= S_038014_LAST_LEVEL(util_logbase2(texture
->nr_samples
));
1167 view
->tex_resource_words
[5] |= S_038014_LAST_LEVEL(last_level
);
1169 view
->tex_resource_words
[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE
) |
1170 S_038018_MAX_ANISO(4 /* max 16 samples */));
1174 static struct pipe_sampler_view
*
1175 r600_create_sampler_view(struct pipe_context
*ctx
,
1176 struct pipe_resource
*tex
,
1177 const struct pipe_sampler_view
*state
)
1179 return r600_create_sampler_view_custom(ctx
, tex
, state
,
1180 u_minify(tex
->width0
, state
->u
.tex
.first_level
),
1181 u_minify(tex
->height0
, state
->u
.tex
.first_level
));
1184 static void r600_emit_clip_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1186 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
1187 struct pipe_clip_state
*state
= &rctx
->clip_state
.state
;
1189 r600_write_context_reg_seq(cs
, R_028E20_PA_CL_UCP0_X
, 6*4);
1190 r600_write_array(cs
, 6*4, (unsigned*)state
);
1193 static void r600_set_polygon_stipple(struct pipe_context
*ctx
,
1194 const struct pipe_poly_stipple
*state
)
1198 static void r600_emit_scissor_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1200 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
1201 struct pipe_scissor_state
*state
= &rctx
->scissor
.scissor
;
1203 if (rctx
->chip_class
!= R600
|| rctx
->scissor
.enable
) {
1204 r600_write_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 2);
1205 r600_write_value(cs
, S_028240_TL_X(state
->minx
) | S_028240_TL_Y(state
->miny
) |
1206 S_028240_WINDOW_OFFSET_DISABLE(1));
1207 r600_write_value(cs
, S_028244_BR_X(state
->maxx
) | S_028244_BR_Y(state
->maxy
));
1209 r600_write_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 2);
1210 r600_write_value(cs
, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1211 S_028240_WINDOW_OFFSET_DISABLE(1));
1212 r600_write_value(cs
, S_028244_BR_X(8192) | S_028244_BR_Y(8192));
1216 static void r600_set_scissor_state(struct pipe_context
*ctx
,
1217 const struct pipe_scissor_state
*state
)
1219 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1221 rctx
->scissor
.scissor
= *state
;
1223 if (rctx
->chip_class
== R600
&& !rctx
->scissor
.enable
)
1226 rctx
->scissor
.atom
.dirty
= true;
1229 static struct r600_resource
*r600_buffer_create_helper(struct r600_screen
*rscreen
,
1230 unsigned size
, unsigned alignment
)
1232 struct pipe_resource buffer
;
1234 memset(&buffer
, 0, sizeof buffer
);
1235 buffer
.target
= PIPE_BUFFER
;
1236 buffer
.format
= PIPE_FORMAT_R8_UNORM
;
1237 buffer
.bind
= PIPE_BIND_CUSTOM
;
1238 buffer
.usage
= PIPE_USAGE_STATIC
;
1240 buffer
.width0
= size
;
1243 buffer
.array_size
= 1;
1245 return (struct r600_resource
*)
1246 r600_buffer_create(&rscreen
->screen
, &buffer
, alignment
);
1249 static void r600_init_color_surface(struct r600_context
*rctx
,
1250 struct r600_surface
*surf
,
1251 bool force_cmask_fmask
)
1253 struct r600_screen
*rscreen
= rctx
->screen
;
1254 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1255 unsigned level
= surf
->base
.u
.tex
.level
;
1256 unsigned pitch
, slice
;
1257 unsigned color_info
;
1258 unsigned format
, swap
, ntype
, endian
;
1260 const struct util_format_description
*desc
;
1262 bool blend_bypass
= 0, blend_clamp
= 1;
1264 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
&& !r600_can_read_depth(rtex
)) {
1265 r600_init_flushed_depth_texture(&rctx
->context
, surf
->base
.texture
, NULL
);
1266 rtex
= rtex
->flushed_depth_texture
;
1270 offset
= rtex
->surface
.level
[level
].offset
;
1271 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1272 offset
+= rtex
->surface
.level
[level
].slice_size
*
1273 surf
->base
.u
.tex
.first_layer
;
1275 pitch
= rtex
->surface
.level
[level
].nblk_x
/ 8 - 1;
1276 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1281 switch (rtex
->surface
.level
[level
].mode
) {
1282 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1283 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED
);
1285 case RADEON_SURF_MODE_1D
:
1286 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1
);
1288 case RADEON_SURF_MODE_2D
:
1289 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1
);
1291 case RADEON_SURF_MODE_LINEAR
:
1293 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL
);
1297 desc
= util_format_description(surf
->base
.format
);
1299 for (i
= 0; i
< 4; i
++) {
1300 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1305 ntype
= V_0280A0_NUMBER_UNORM
;
1306 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1307 ntype
= V_0280A0_NUMBER_SRGB
;
1308 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1309 if (desc
->channel
[i
].normalized
)
1310 ntype
= V_0280A0_NUMBER_SNORM
;
1311 else if (desc
->channel
[i
].pure_integer
)
1312 ntype
= V_0280A0_NUMBER_SINT
;
1313 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1314 if (desc
->channel
[i
].normalized
)
1315 ntype
= V_0280A0_NUMBER_UNORM
;
1316 else if (desc
->channel
[i
].pure_integer
)
1317 ntype
= V_0280A0_NUMBER_UINT
;
1320 format
= r600_translate_colorformat(surf
->base
.format
);
1321 assert(format
!= ~0);
1323 swap
= r600_translate_colorswap(surf
->base
.format
);
1326 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1327 endian
= ENDIAN_NONE
;
1329 endian
= r600_colorformat_endian_swap(format
);
1332 /* set blend bypass according to docs if SINT/UINT or
1333 8/24 COLOR variants */
1334 if (ntype
== V_0280A0_NUMBER_UINT
|| ntype
== V_0280A0_NUMBER_SINT
||
1335 format
== V_0280A0_COLOR_8_24
|| format
== V_0280A0_COLOR_24_8
||
1336 format
== V_0280A0_COLOR_X24_8_32_FLOAT
) {
1341 surf
->alphatest_bypass
= ntype
== V_0280A0_NUMBER_UINT
|| ntype
== V_0280A0_NUMBER_SINT
;
1343 color_info
|= S_0280A0_FORMAT(format
) |
1344 S_0280A0_COMP_SWAP(swap
) |
1345 S_0280A0_BLEND_BYPASS(blend_bypass
) |
1346 S_0280A0_BLEND_CLAMP(blend_clamp
) |
1347 S_0280A0_NUMBER_TYPE(ntype
) |
1348 S_0280A0_ENDIAN(endian
);
1350 /* EXPORT_NORM is an optimzation that can be enabled for better
1351 * performance in certain cases
1353 if (rctx
->chip_class
== R600
) {
1354 /* EXPORT_NORM can be enabled if:
1355 * - 11-bit or smaller UNORM/SNORM/SRGB
1356 * - BLEND_CLAMP is enabled
1357 * - BLEND_FLOAT32 is disabled
1359 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1360 (desc
->channel
[i
].size
< 12 &&
1361 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1362 ntype
!= V_0280A0_NUMBER_UINT
&&
1363 ntype
!= V_0280A0_NUMBER_SINT
) &&
1364 G_0280A0_BLEND_CLAMP(color_info
) &&
1365 !G_0280A0_BLEND_FLOAT32(color_info
)) {
1366 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
1367 surf
->export_16bpc
= true;
1370 /* EXPORT_NORM can be enabled if:
1371 * - 11-bit or smaller UNORM/SNORM/SRGB
1372 * - 16-bit or smaller FLOAT
1374 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1375 ((desc
->channel
[i
].size
< 12 &&
1376 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1377 ntype
!= V_0280A0_NUMBER_UINT
&& ntype
!= V_0280A0_NUMBER_SINT
) ||
1378 (desc
->channel
[i
].size
< 17 &&
1379 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
1380 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
1381 surf
->export_16bpc
= true;
1385 /* These might not always be initialized to zero. */
1386 surf
->cb_color_base
= offset
>> 8;
1387 surf
->cb_color_size
= S_028060_PITCH_TILE_MAX(pitch
) |
1388 S_028060_SLICE_TILE_MAX(slice
);
1389 surf
->cb_color_fmask
= surf
->cb_color_base
;
1390 surf
->cb_color_cmask
= surf
->cb_color_base
;
1391 surf
->cb_color_mask
= 0;
1393 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
,
1394 &rtex
->resource
.b
.b
);
1395 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
,
1396 &rtex
->resource
.b
.b
);
1398 if (rtex
->cmask_size
) {
1399 surf
->cb_color_cmask
= rtex
->cmask_offset
>> 8;
1400 surf
->cb_color_mask
|= S_028100_CMASK_BLOCK_MAX(rtex
->cmask_slice_tile_max
);
1402 if (rtex
->fmask_size
) {
1403 color_info
|= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE
);
1404 surf
->cb_color_fmask
= rtex
->fmask_offset
>> 8;
1405 surf
->cb_color_mask
|= S_028100_FMASK_TILE_MAX(slice
);
1406 } else { /* cmask only */
1407 color_info
|= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE
);
1409 } else if (force_cmask_fmask
) {
1410 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1412 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1413 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1414 * because it's not an MSAA buffer.
1416 struct r600_cmask_info cmask
;
1417 struct r600_fmask_info fmask
;
1419 r600_texture_get_cmask_info(rscreen
, rtex
, &cmask
);
1420 r600_texture_get_fmask_info(rscreen
, rtex
, 8, &fmask
);
1423 if (!rctx
->dummy_cmask
||
1424 rctx
->dummy_cmask
->buf
->size
< cmask
.size
||
1425 rctx
->dummy_cmask
->buf
->alignment
% cmask
.alignment
!= 0) {
1426 struct pipe_transfer
*transfer
;
1429 pipe_resource_reference((struct pipe_resource
**)&rctx
->dummy_cmask
, NULL
);
1430 rctx
->dummy_cmask
= r600_buffer_create_helper(rscreen
, cmask
.size
, cmask
.alignment
);
1432 /* Set the contents to 0xCC. */
1433 ptr
= pipe_buffer_map(&rctx
->context
, &rctx
->dummy_cmask
->b
.b
, PIPE_TRANSFER_WRITE
, &transfer
);
1434 memset(ptr
, 0xCC, cmask
.size
);
1435 pipe_buffer_unmap(&rctx
->context
, transfer
);
1437 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
,
1438 &rctx
->dummy_cmask
->b
.b
);
1441 if (!rctx
->dummy_fmask
||
1442 rctx
->dummy_fmask
->buf
->size
< fmask
.size
||
1443 rctx
->dummy_fmask
->buf
->alignment
% fmask
.alignment
!= 0) {
1444 pipe_resource_reference((struct pipe_resource
**)&rctx
->dummy_fmask
, NULL
);
1445 rctx
->dummy_fmask
= r600_buffer_create_helper(rscreen
, fmask
.size
, fmask
.alignment
);
1448 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
,
1449 &rctx
->dummy_fmask
->b
.b
);
1451 /* Init the registers. */
1452 color_info
|= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE
);
1453 surf
->cb_color_cmask
= 0;
1454 surf
->cb_color_fmask
= 0;
1455 surf
->cb_color_mask
= S_028100_CMASK_BLOCK_MAX(cmask
.slice_tile_max
) |
1456 S_028100_FMASK_TILE_MAX(slice
);
1459 surf
->cb_color_info
= color_info
;
1461 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1462 surf
->cb_color_view
= 0;
1464 surf
->cb_color_view
= S_028080_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1465 S_028080_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1468 surf
->color_initialized
= true;
1471 static void r600_init_depth_surface(struct r600_context
*rctx
,
1472 struct r600_surface
*surf
)
1474 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1475 unsigned level
, pitch
, slice
, format
, offset
, array_mode
;
1477 level
= surf
->base
.u
.tex
.level
;
1478 offset
= rtex
->surface
.level
[level
].offset
;
1479 pitch
= rtex
->surface
.level
[level
].nblk_x
/ 8 - 1;
1480 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1484 switch (rtex
->surface
.level
[level
].mode
) {
1485 case RADEON_SURF_MODE_2D
:
1486 array_mode
= V_0280A0_ARRAY_2D_TILED_THIN1
;
1488 case RADEON_SURF_MODE_1D
:
1489 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1490 case RADEON_SURF_MODE_LINEAR
:
1492 array_mode
= V_0280A0_ARRAY_1D_TILED_THIN1
;
1496 format
= r600_translate_dbformat(surf
->base
.format
);
1497 assert(format
!= ~0);
1499 surf
->db_depth_info
= S_028010_ARRAY_MODE(array_mode
) | S_028010_FORMAT(format
);
1500 surf
->db_depth_base
= offset
>> 8;
1501 surf
->db_depth_view
= S_028004_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1502 S_028004_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1503 surf
->db_depth_size
= S_028000_PITCH_TILE_MAX(pitch
) | S_028000_SLICE_TILE_MAX(slice
);
1504 surf
->db_prefetch_limit
= (rtex
->surface
.level
[level
].nblk_y
/ 8) - 1;
1506 switch (surf
->base
.format
) {
1507 case PIPE_FORMAT_Z24X8_UNORM
:
1508 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1509 surf
->pa_su_poly_offset_db_fmt_cntl
=
1510 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1512 case PIPE_FORMAT_Z32_FLOAT
:
1513 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1514 surf
->pa_su_poly_offset_db_fmt_cntl
=
1515 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1516 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1518 case PIPE_FORMAT_Z16_UNORM
:
1519 surf
->pa_su_poly_offset_db_fmt_cntl
=
1520 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1525 surf
->htile_enabled
= 0;
1526 /* use htile only for first level */
1527 if (rtex
->htile
&& !level
) {
1528 uint64_t va
= r600_resource_va(&rctx
->screen
->screen
, &rtex
->htile
->b
.b
);
1529 surf
->htile_enabled
= 1;
1530 surf
->db_htile_data_base
= va
>> 8;
1531 surf
->db_htile_surface
= S_028D24_HTILE_WIDTH(1) |
1532 S_028D24_HTILE_HEIGHT(1) |
1534 /* preload is not working properly on r6xx/r7xx */
1535 surf
->db_depth_info
|= S_028010_TILE_SURFACE_ENABLE(1);
1538 surf
->depth_initialized
= true;
1541 static void r600_set_framebuffer_state(struct pipe_context
*ctx
,
1542 const struct pipe_framebuffer_state
*state
)
1544 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1545 struct r600_surface
*surf
;
1546 struct r600_texture
*rtex
;
1549 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1550 rctx
->flags
|= R600_CONTEXT_WAIT_3D_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
1552 if (rctx
->chip_class
>= R700
&&
1553 rctx
->framebuffer
.state
.cbufs
[0]->texture
->nr_samples
> 1) {
1554 rctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV_CB_META
;
1557 if (rctx
->framebuffer
.state
.zsbuf
) {
1558 rctx
->flags
|= R600_CONTEXT_WAIT_3D_IDLE
| R600_CONTEXT_FLUSH_AND_INV
;
1560 rtex
= (struct r600_texture
*)rctx
->framebuffer
.state
.zsbuf
->texture
;
1561 if (rctx
->chip_class
>= R700
&& rtex
->htile
) {
1562 rctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV_DB_META
;
1566 /* Set the new state. */
1567 util_copy_framebuffer_state(&rctx
->framebuffer
.state
, state
);
1569 rctx
->framebuffer
.export_16bpc
= state
->nr_cbufs
!= 0;
1570 rctx
->framebuffer
.cb0_is_integer
= state
->nr_cbufs
&&
1571 util_format_is_pure_integer(state
->cbufs
[0]->format
);
1572 rctx
->framebuffer
.compressed_cb_mask
= 0;
1573 rctx
->framebuffer
.is_msaa_resolve
= state
->nr_cbufs
== 2 &&
1574 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
1575 state
->cbufs
[1]->texture
->nr_samples
<= 1;
1577 if (state
->nr_cbufs
)
1578 rctx
->framebuffer
.nr_samples
= state
->cbufs
[0]->texture
->nr_samples
;
1579 else if (state
->zsbuf
)
1580 rctx
->framebuffer
.nr_samples
= state
->zsbuf
->texture
->nr_samples
;
1582 rctx
->framebuffer
.nr_samples
= 0;
1585 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
1586 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1587 bool force_cmask_fmask
= rctx
->chip_class
== R600
&&
1588 rctx
->framebuffer
.is_msaa_resolve
&&
1591 surf
= (struct r600_surface
*)state
->cbufs
[i
];
1592 rtex
= (struct r600_texture
*)surf
->base
.texture
;
1593 r600_context_add_resource_size(ctx
, state
->cbufs
[i
]->texture
);
1595 if (!surf
->color_initialized
|| force_cmask_fmask
) {
1596 r600_init_color_surface(rctx
, surf
, force_cmask_fmask
);
1597 if (force_cmask_fmask
) {
1598 /* re-initialize later without compression */
1599 surf
->color_initialized
= false;
1603 if (!surf
->export_16bpc
) {
1604 rctx
->framebuffer
.export_16bpc
= false;
1607 if (rtex
->fmask_size
&& rtex
->cmask_size
) {
1608 rctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
1612 /* Update alpha-test state dependencies.
1613 * Alpha-test is done on the first colorbuffer only. */
1614 if (state
->nr_cbufs
) {
1615 surf
= (struct r600_surface
*)state
->cbufs
[0];
1616 if (rctx
->alphatest_state
.bypass
!= surf
->alphatest_bypass
) {
1617 rctx
->alphatest_state
.bypass
= surf
->alphatest_bypass
;
1618 rctx
->alphatest_state
.atom
.dirty
= true;
1624 surf
= (struct r600_surface
*)state
->zsbuf
;
1626 r600_context_add_resource_size(ctx
, state
->zsbuf
->texture
);
1628 if (!surf
->depth_initialized
) {
1629 r600_init_depth_surface(rctx
, surf
);
1632 if (state
->zsbuf
->format
!= rctx
->poly_offset_state
.zs_format
) {
1633 rctx
->poly_offset_state
.zs_format
= state
->zsbuf
->format
;
1634 rctx
->poly_offset_state
.atom
.dirty
= true;
1637 if (rctx
->db_state
.rsurf
!= surf
) {
1638 rctx
->db_state
.rsurf
= surf
;
1639 rctx
->db_state
.atom
.dirty
= true;
1640 rctx
->db_misc_state
.atom
.dirty
= true;
1642 } else if (rctx
->db_state
.rsurf
) {
1643 rctx
->db_state
.rsurf
= NULL
;
1644 rctx
->db_state
.atom
.dirty
= true;
1645 rctx
->db_misc_state
.atom
.dirty
= true;
1648 if (rctx
->cb_misc_state
.nr_cbufs
!= state
->nr_cbufs
) {
1649 rctx
->cb_misc_state
.nr_cbufs
= state
->nr_cbufs
;
1650 rctx
->cb_misc_state
.atom
.dirty
= true;
1653 if (state
->nr_cbufs
== 0 && rctx
->alphatest_state
.bypass
) {
1654 rctx
->alphatest_state
.bypass
= false;
1655 rctx
->alphatest_state
.atom
.dirty
= true;
1658 r600_update_db_shader_control(rctx
);
1660 /* Calculate the CS size. */
1661 rctx
->framebuffer
.atom
.num_dw
=
1662 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1664 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1665 rctx
->framebuffer
.atom
.num_dw
+= 6 * (2 + rctx
->framebuffer
.state
.nr_cbufs
);
1666 rctx
->framebuffer
.atom
.num_dw
+= 6 * rctx
->framebuffer
.state
.nr_cbufs
; /* relocs */
1669 if (rctx
->framebuffer
.state
.zsbuf
) {
1670 rctx
->framebuffer
.atom
.num_dw
+= 18;
1671 } else if (rctx
->screen
->info
.drm_minor
>= 18) {
1672 rctx
->framebuffer
.atom
.num_dw
+= 3;
1674 if (rctx
->family
> CHIP_R600
&& rctx
->family
< CHIP_RV770
) {
1675 rctx
->framebuffer
.atom
.num_dw
+= 2;
1678 rctx
->framebuffer
.atom
.dirty
= true;
1681 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1682 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1683 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1684 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1685 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1687 static void r600_emit_msaa_state(struct r600_context
*rctx
, int nr_samples
)
1689 static uint32_t sample_locs_2x
[] = {
1690 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1691 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1693 static unsigned max_dist_2x
= 4;
1694 static uint32_t sample_locs_4x
[] = {
1695 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1696 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1698 static unsigned max_dist_4x
= 6;
1699 static uint32_t sample_locs_8x
[] = {
1700 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1701 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1703 static unsigned max_dist_8x
= 7;
1705 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
1706 unsigned max_dist
= 0;
1708 if (rctx
->family
== CHIP_R600
) {
1709 switch (nr_samples
) {
1714 r600_write_config_reg(cs
, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S
, sample_locs_2x
[0]);
1715 max_dist
= max_dist_2x
;
1718 r600_write_config_reg(cs
, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S
, sample_locs_4x
[0]);
1719 max_dist
= max_dist_4x
;
1722 r600_write_config_reg_seq(cs
, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0
, 2);
1723 r600_write_value(cs
, sample_locs_8x
[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1724 r600_write_value(cs
, sample_locs_8x
[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1725 max_dist
= max_dist_8x
;
1729 switch (nr_samples
) {
1731 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1732 r600_write_value(cs
, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1733 r600_write_value(cs
, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1737 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1738 r600_write_value(cs
, sample_locs_2x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1739 r600_write_value(cs
, sample_locs_2x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1740 max_dist
= max_dist_2x
;
1743 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1744 r600_write_value(cs
, sample_locs_4x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1745 r600_write_value(cs
, sample_locs_4x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1746 max_dist
= max_dist_4x
;
1749 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1750 r600_write_value(cs
, sample_locs_8x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1751 r600_write_value(cs
, sample_locs_8x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1752 max_dist
= max_dist_8x
;
1757 if (nr_samples
> 1) {
1758 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1759 r600_write_value(cs
, S_028C00_LAST_PIXEL(1) |
1760 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1761 r600_write_value(cs
, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples
)) |
1762 S_028C04_MAX_SAMPLE_DIST(max_dist
)); /* R_028C04_PA_SC_AA_CONFIG */
1764 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1765 r600_write_value(cs
, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1766 r600_write_value(cs
, 0); /* R_028C04_PA_SC_AA_CONFIG */
1770 static void r600_emit_framebuffer_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1772 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
1773 struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
.state
;
1774 unsigned nr_cbufs
= state
->nr_cbufs
;
1775 struct r600_surface
**cb
= (struct r600_surface
**)&state
->cbufs
[0];
1776 unsigned i
, sbu
= 0;
1779 r600_write_context_reg_seq(cs
, R_0280A0_CB_COLOR0_INFO
, 8);
1780 for (i
= 0; i
< nr_cbufs
; i
++) {
1781 r600_write_value(cs
, cb
[i
]->cb_color_info
);
1783 /* set CB_COLOR1_INFO for possible dual-src blending */
1785 r600_write_value(cs
, cb
[0]->cb_color_info
);
1788 for (; i
< 8; i
++) {
1789 r600_write_value(cs
, 0);
1794 r600_write_context_reg_seq(cs
, R_028040_CB_COLOR0_BASE
, nr_cbufs
);
1795 for (i
= 0; i
< nr_cbufs
; i
++) {
1796 r600_write_value(cs
, cb
[i
]->cb_color_base
);
1800 for (i
= 0; i
< nr_cbufs
; i
++) {
1801 unsigned reloc
= r600_context_bo_reloc(rctx
,
1803 (struct r600_resource
*)cb
[i
]->base
.texture
,
1804 RADEON_USAGE_READWRITE
);
1805 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1806 r600_write_value(cs
, reloc
);
1809 r600_write_context_reg_seq(cs
, R_028060_CB_COLOR0_SIZE
, nr_cbufs
);
1810 for (i
= 0; i
< nr_cbufs
; i
++) {
1811 r600_write_value(cs
, cb
[i
]->cb_color_size
);
1814 r600_write_context_reg_seq(cs
, R_028080_CB_COLOR0_VIEW
, nr_cbufs
);
1815 for (i
= 0; i
< nr_cbufs
; i
++) {
1816 r600_write_value(cs
, cb
[i
]->cb_color_view
);
1819 r600_write_context_reg_seq(cs
, R_028100_CB_COLOR0_MASK
, nr_cbufs
);
1820 for (i
= 0; i
< nr_cbufs
; i
++) {
1821 r600_write_value(cs
, cb
[i
]->cb_color_mask
);
1825 r600_write_context_reg_seq(cs
, R_0280E0_CB_COLOR0_FRAG
, nr_cbufs
);
1826 for (i
= 0; i
< nr_cbufs
; i
++) {
1827 r600_write_value(cs
, cb
[i
]->cb_color_fmask
);
1830 for (i
= 0; i
< nr_cbufs
; i
++) {
1831 unsigned reloc
= r600_context_bo_reloc(rctx
,
1833 cb
[i
]->cb_buffer_fmask
,
1834 RADEON_USAGE_READWRITE
);
1835 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1836 r600_write_value(cs
, reloc
);
1840 r600_write_context_reg_seq(cs
, R_0280C0_CB_COLOR0_TILE
, nr_cbufs
);
1841 for (i
= 0; i
< nr_cbufs
; i
++) {
1842 r600_write_value(cs
, cb
[i
]->cb_color_cmask
);
1845 for (i
= 0; i
< nr_cbufs
; i
++) {
1846 unsigned reloc
= r600_context_bo_reloc(rctx
,
1848 cb
[i
]->cb_buffer_cmask
,
1849 RADEON_USAGE_READWRITE
);
1850 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1851 r600_write_value(cs
, reloc
);
1854 sbu
|= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs
);
1857 /* SURFACE_BASE_UPDATE */
1858 if (rctx
->family
> CHIP_R600
&& rctx
->family
< CHIP_RV770
&& sbu
) {
1859 r600_write_value(cs
, PKT3(PKT3_SURFACE_BASE_UPDATE
, 0, 0));
1860 r600_write_value(cs
, sbu
);
1866 struct r600_surface
*surf
= (struct r600_surface
*)state
->zsbuf
;
1867 unsigned reloc
= r600_context_bo_reloc(rctx
,
1869 (struct r600_resource
*)state
->zsbuf
->texture
,
1870 RADEON_USAGE_READWRITE
);
1872 r600_write_context_reg(cs
, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1873 surf
->pa_su_poly_offset_db_fmt_cntl
);
1875 r600_write_context_reg_seq(cs
, R_028000_DB_DEPTH_SIZE
, 2);
1876 r600_write_value(cs
, surf
->db_depth_size
); /* R_028000_DB_DEPTH_SIZE */
1877 r600_write_value(cs
, surf
->db_depth_view
); /* R_028004_DB_DEPTH_VIEW */
1878 r600_write_context_reg_seq(cs
, R_02800C_DB_DEPTH_BASE
, 2);
1879 r600_write_value(cs
, surf
->db_depth_base
); /* R_02800C_DB_DEPTH_BASE */
1880 r600_write_value(cs
, surf
->db_depth_info
); /* R_028010_DB_DEPTH_INFO */
1882 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1883 r600_write_value(cs
, reloc
);
1885 r600_write_context_reg(cs
, R_028D34_DB_PREFETCH_LIMIT
, surf
->db_prefetch_limit
);
1887 sbu
|= SURFACE_BASE_UPDATE_DEPTH
;
1888 } else if (rctx
->screen
->info
.drm_minor
>= 18) {
1889 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1890 * Older kernels are out of luck. */
1891 r600_write_context_reg(cs
, R_028010_DB_DEPTH_INFO
, S_028010_FORMAT(V_028010_DEPTH_INVALID
));
1894 /* SURFACE_BASE_UPDATE */
1895 if (rctx
->family
> CHIP_R600
&& rctx
->family
< CHIP_RV770
&& sbu
) {
1896 r600_write_value(cs
, PKT3(PKT3_SURFACE_BASE_UPDATE
, 0, 0));
1897 r600_write_value(cs
, sbu
);
1901 /* Framebuffer dimensions. */
1902 r600_write_context_reg_seq(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, 2);
1903 r600_write_value(cs
, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1904 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1905 r600_write_value(cs
, S_028244_BR_X(state
->width
) |
1906 S_028244_BR_Y(state
->height
)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1908 if (rctx
->framebuffer
.is_msaa_resolve
) {
1909 r600_write_context_reg(cs
, R_0287A0_CB_SHADER_CONTROL
, 1);
1911 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1912 * will assure that the alpha-test will work even if there is
1913 * no colorbuffer bound. */
1914 r600_write_context_reg(cs
, R_0287A0_CB_SHADER_CONTROL
,
1915 (1ull << MAX2(nr_cbufs
, 1)) - 1);
1918 r600_emit_msaa_state(rctx
, rctx
->framebuffer
.nr_samples
);
1921 static void r600_emit_cb_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1923 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
1924 struct r600_cb_misc_state
*a
= (struct r600_cb_misc_state
*)atom
;
1926 if (G_028808_SPECIAL_OP(a
->cb_color_control
) == V_028808_SPECIAL_RESOLVE_BOX
) {
1927 r600_write_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1928 if (rctx
->chip_class
== R600
) {
1929 r600_write_value(cs
, 0xff); /* R_028238_CB_TARGET_MASK */
1930 r600_write_value(cs
, 0xff); /* R_02823C_CB_SHADER_MASK */
1932 r600_write_value(cs
, 0xf); /* R_028238_CB_TARGET_MASK */
1933 r600_write_value(cs
, 0xf); /* R_02823C_CB_SHADER_MASK */
1935 r600_write_context_reg(cs
, R_028808_CB_COLOR_CONTROL
, a
->cb_color_control
);
1937 unsigned fb_colormask
= (1ULL << ((unsigned)a
->nr_cbufs
* 4)) - 1;
1938 unsigned ps_colormask
= (1ULL << ((unsigned)a
->nr_ps_color_outputs
* 4)) - 1;
1939 unsigned multiwrite
= a
->multiwrite
&& a
->nr_cbufs
> 1;
1941 r600_write_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1942 r600_write_value(cs
, a
->blend_colormask
& fb_colormask
); /* R_028238_CB_TARGET_MASK */
1943 /* Always enable the first color output to make sure alpha-test works even without one. */
1944 r600_write_value(cs
, 0xf | (multiwrite
? fb_colormask
: ps_colormask
)); /* R_02823C_CB_SHADER_MASK */
1945 r600_write_context_reg(cs
, R_028808_CB_COLOR_CONTROL
,
1946 a
->cb_color_control
|
1947 S_028808_MULTIWRITE_ENABLE(multiwrite
));
1951 static void r600_emit_db_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1953 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
1954 struct r600_db_state
*a
= (struct r600_db_state
*)atom
;
1956 if (a
->rsurf
&& a
->rsurf
->htile_enabled
) {
1957 struct r600_texture
*rtex
= (struct r600_texture
*)a
->rsurf
->base
.texture
;
1960 r600_write_context_reg(cs
, R_02802C_DB_DEPTH_CLEAR
, fui(rtex
->depth_clear
));
1961 r600_write_context_reg(cs
, R_028D24_DB_HTILE_SURFACE
, a
->rsurf
->db_htile_surface
);
1962 r600_write_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, a
->rsurf
->db_htile_data_base
);
1963 reloc_idx
= r600_context_bo_reloc(rctx
, &rctx
->rings
.gfx
, rtex
->htile
, RADEON_USAGE_READWRITE
);
1964 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1965 cs
->buf
[cs
->cdw
++] = reloc_idx
;
1967 r600_write_context_reg(cs
, R_028D24_DB_HTILE_SURFACE
, 0);
1971 static void r600_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1973 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
1974 struct r600_db_misc_state
*a
= (struct r600_db_misc_state
*)atom
;
1975 unsigned db_render_control
= 0;
1976 unsigned db_render_override
=
1977 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE
) |
1978 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE
);
1980 if (a
->occlusion_query_enabled
) {
1981 if (rctx
->chip_class
>= R700
) {
1982 db_render_control
|= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1984 db_render_override
|= S_028D10_NOOP_CULL_DISABLE(1);
1986 if (rctx
->db_state
.rsurf
&& rctx
->db_state
.rsurf
->htile_enabled
) {
1987 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1988 db_render_override
|= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF
);
1989 /* This is to fix a lockup when hyperz and alpha test are enabled at
1990 * the same time somehow GPU get confuse on which order to pick for
1993 if (rctx
->alphatest_state
.sx_alpha_test_control
) {
1994 db_render_override
|= S_028D10_FORCE_SHADER_Z_ORDER(1);
1997 db_render_override
|= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE
);
1999 if (a
->flush_depthstencil_through_cb
) {
2000 assert(a
->copy_depth
|| a
->copy_stencil
);
2002 db_render_control
|= S_028D0C_DEPTH_COPY_ENABLE(a
->copy_depth
) |
2003 S_028D0C_STENCIL_COPY_ENABLE(a
->copy_stencil
) |
2004 S_028D0C_COPY_CENTROID(1) |
2005 S_028D0C_COPY_SAMPLE(a
->copy_sample
);
2006 } else if (a
->flush_depthstencil_in_place
) {
2007 db_render_control
|= S_028D0C_DEPTH_COMPRESS_DISABLE(1) |
2008 S_028D0C_STENCIL_COMPRESS_DISABLE(1);
2009 db_render_override
|= S_028D10_NOOP_CULL_DISABLE(1);
2011 if (a
->htile_clear
) {
2012 db_render_control
|= S_028D0C_DEPTH_CLEAR_ENABLE(1);
2015 r600_write_context_reg_seq(cs
, R_028D0C_DB_RENDER_CONTROL
, 2);
2016 r600_write_value(cs
, db_render_control
); /* R_028D0C_DB_RENDER_CONTROL */
2017 r600_write_value(cs
, db_render_override
); /* R_028D10_DB_RENDER_OVERRIDE */
2018 r600_write_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
, a
->db_shader_control
);
2021 static void r600_emit_config_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
2023 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
2024 struct r600_config_state
*a
= (struct r600_config_state
*)atom
;
2026 r600_write_config_reg(cs
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, a
->sq_gpr_resource_mgmt_1
);
2029 static void r600_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2031 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
2032 uint32_t dirty_mask
= rctx
->vertex_buffer_state
.dirty_mask
;
2034 while (dirty_mask
) {
2035 struct pipe_vertex_buffer
*vb
;
2036 struct r600_resource
*rbuffer
;
2038 unsigned buffer_index
= u_bit_scan(&dirty_mask
);
2040 vb
= &rctx
->vertex_buffer_state
.vb
[buffer_index
];
2041 rbuffer
= (struct r600_resource
*)vb
->buffer
;
2044 offset
= vb
->buffer_offset
;
2046 /* fetch resources start at index 320 */
2047 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
2048 r600_write_value(cs
, (320 + buffer_index
) * 7);
2049 r600_write_value(cs
, offset
); /* RESOURCEi_WORD0 */
2050 r600_write_value(cs
, rbuffer
->buf
->size
- offset
- 1); /* RESOURCEi_WORD1 */
2051 r600_write_value(cs
, /* RESOURCEi_WORD2 */
2052 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
2053 S_038008_STRIDE(vb
->stride
));
2054 r600_write_value(cs
, 0); /* RESOURCEi_WORD3 */
2055 r600_write_value(cs
, 0); /* RESOURCEi_WORD4 */
2056 r600_write_value(cs
, 0); /* RESOURCEi_WORD5 */
2057 r600_write_value(cs
, 0xc0000000); /* RESOURCEi_WORD6 */
2059 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2060 r600_write_value(cs
, r600_context_bo_reloc(rctx
, &rctx
->rings
.gfx
, rbuffer
, RADEON_USAGE_READ
));
2064 static void r600_emit_constant_buffers(struct r600_context
*rctx
,
2065 struct r600_constbuf_state
*state
,
2066 unsigned buffer_id_base
,
2067 unsigned reg_alu_constbuf_size
,
2068 unsigned reg_alu_const_cache
)
2070 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
2071 uint32_t dirty_mask
= state
->dirty_mask
;
2073 while (dirty_mask
) {
2074 struct pipe_constant_buffer
*cb
;
2075 struct r600_resource
*rbuffer
;
2077 unsigned buffer_index
= ffs(dirty_mask
) - 1;
2079 cb
= &state
->cb
[buffer_index
];
2080 rbuffer
= (struct r600_resource
*)cb
->buffer
;
2083 offset
= cb
->buffer_offset
;
2085 r600_write_context_reg(cs
, reg_alu_constbuf_size
+ buffer_index
* 4,
2086 ALIGN_DIVUP(cb
->buffer_size
>> 4, 16));
2087 r600_write_context_reg(cs
, reg_alu_const_cache
+ buffer_index
* 4, offset
>> 8);
2089 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2090 r600_write_value(cs
, r600_context_bo_reloc(rctx
, &rctx
->rings
.gfx
, rbuffer
, RADEON_USAGE_READ
));
2092 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
2093 r600_write_value(cs
, (buffer_id_base
+ buffer_index
) * 7);
2094 r600_write_value(cs
, offset
); /* RESOURCEi_WORD0 */
2095 r600_write_value(cs
, rbuffer
->buf
->size
- offset
- 1); /* RESOURCEi_WORD1 */
2096 r600_write_value(cs
, /* RESOURCEi_WORD2 */
2097 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
2098 S_038008_STRIDE(16));
2099 r600_write_value(cs
, 0); /* RESOURCEi_WORD3 */
2100 r600_write_value(cs
, 0); /* RESOURCEi_WORD4 */
2101 r600_write_value(cs
, 0); /* RESOURCEi_WORD5 */
2102 r600_write_value(cs
, 0xc0000000); /* RESOURCEi_WORD6 */
2104 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2105 r600_write_value(cs
, r600_context_bo_reloc(rctx
, &rctx
->rings
.gfx
, rbuffer
, RADEON_USAGE_READ
));
2107 dirty_mask
&= ~(1 << buffer_index
);
2109 state
->dirty_mask
= 0;
2112 static void r600_emit_vs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2114 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
], 160,
2115 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
2116 R_028980_ALU_CONST_CACHE_VS_0
);
2119 static void r600_emit_gs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2121 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
], 336,
2122 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
,
2123 R_0289C0_ALU_CONST_CACHE_GS_0
);
2126 static void r600_emit_ps_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
2128 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
], 0,
2129 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
2130 R_028940_ALU_CONST_CACHE_PS_0
);
2133 static void r600_emit_sampler_views(struct r600_context
*rctx
,
2134 struct r600_samplerview_state
*state
,
2135 unsigned resource_id_base
)
2137 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
2138 uint32_t dirty_mask
= state
->dirty_mask
;
2140 while (dirty_mask
) {
2141 struct r600_pipe_sampler_view
*rview
;
2142 unsigned resource_index
= u_bit_scan(&dirty_mask
);
2145 rview
= state
->views
[resource_index
];
2148 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
2149 r600_write_value(cs
, (resource_id_base
+ resource_index
) * 7);
2150 r600_write_array(cs
, 7, rview
->tex_resource_words
);
2152 reloc
= r600_context_bo_reloc(rctx
, &rctx
->rings
.gfx
, rview
->tex_resource
,
2154 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2155 r600_write_value(cs
, reloc
);
2156 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2157 r600_write_value(cs
, reloc
);
2159 state
->dirty_mask
= 0;
2169 static void r600_emit_vs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2171 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
, 160 + R600_MAX_CONST_BUFFERS
);
2174 static void r600_emit_gs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2176 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
, 336 + R600_MAX_CONST_BUFFERS
);
2179 static void r600_emit_ps_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2181 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
, R600_MAX_CONST_BUFFERS
);
2184 static void r600_emit_sampler_states(struct r600_context
*rctx
,
2185 struct r600_textures_info
*texinfo
,
2186 unsigned resource_id_base
,
2187 unsigned border_color_reg
)
2189 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
2190 uint32_t dirty_mask
= texinfo
->states
.dirty_mask
;
2192 while (dirty_mask
) {
2193 struct r600_pipe_sampler_state
*rstate
;
2194 struct r600_pipe_sampler_view
*rview
;
2195 unsigned i
= u_bit_scan(&dirty_mask
);
2197 rstate
= texinfo
->states
.states
[i
];
2199 rview
= texinfo
->views
.views
[i
];
2201 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
2202 * filtering between layers.
2203 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
2206 enum pipe_texture_target target
= rview
->base
.texture
->target
;
2207 if (target
== PIPE_TEXTURE_1D_ARRAY
||
2208 target
== PIPE_TEXTURE_2D_ARRAY
) {
2209 rstate
->tex_sampler_words
[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
2210 texinfo
->is_array_sampler
[i
] = true;
2212 rstate
->tex_sampler_words
[0] &= C_03C000_TEX_ARRAY_OVERRIDE
;
2213 texinfo
->is_array_sampler
[i
] = false;
2217 r600_write_value(cs
, PKT3(PKT3_SET_SAMPLER
, 3, 0));
2218 r600_write_value(cs
, (resource_id_base
+ i
) * 3);
2219 r600_write_array(cs
, 3, rstate
->tex_sampler_words
);
2221 if (rstate
->border_color_use
) {
2224 offset
= border_color_reg
;
2226 r600_write_config_reg_seq(cs
, offset
, 4);
2227 r600_write_array(cs
, 4, rstate
->border_color
.ui
);
2230 texinfo
->states
.dirty_mask
= 0;
2233 static void r600_emit_vs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2235 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED
);
2238 static void r600_emit_gs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2240 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED
);
2243 static void r600_emit_ps_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2245 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED
);
2248 static void r600_emit_seamless_cube_map(struct r600_context
*rctx
, struct r600_atom
*atom
)
2250 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
2253 tmp
= S_009508_DISABLE_CUBE_ANISO(1) |
2254 S_009508_SYNC_GRADIENT(1) |
2255 S_009508_SYNC_WALKER(1) |
2256 S_009508_SYNC_ALIGNER(1);
2257 if (!rctx
->seamless_cube_map
.enabled
) {
2258 tmp
|= S_009508_DISABLE_CUBE_WRAP(1);
2260 r600_write_config_reg(cs
, R_009508_TA_CNTL_AUX
, tmp
);
2263 static void r600_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2265 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2266 uint8_t mask
= s
->sample_mask
;
2268 r600_write_context_reg(rctx
->rings
.gfx
.cs
, R_028C48_PA_SC_AA_MASK
,
2269 mask
| (mask
<< 8) | (mask
<< 16) | (mask
<< 24));
2272 static void r600_emit_vertex_fetch_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2274 struct radeon_winsys_cs
*cs
= rctx
->rings
.gfx
.cs
;
2275 struct r600_cso_state
*state
= (struct r600_cso_state
*)a
;
2276 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
->cso
;
2278 r600_write_context_reg(cs
, R_028894_SQ_PGM_START_FS
, shader
->offset
>> 8);
2279 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2280 r600_write_value(cs
, r600_context_bo_reloc(rctx
, &rctx
->rings
.gfx
, shader
->buffer
, RADEON_USAGE_READ
));
2283 void r600_init_state_functions(struct r600_context
*rctx
)
2288 * To avoid GPU lockup registers must be emited in a specific order
2289 * (no kidding ...). The order below is important and have been
2290 * partialy infered from analyzing fglrx command stream.
2292 * Don't reorder atom without carefully checking the effect (GPU lockup
2293 * or piglit regression).
2297 r600_init_atom(rctx
, &rctx
->framebuffer
.atom
, id
++, r600_emit_framebuffer_state
, 0);
2300 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
].atom
, id
++, r600_emit_vs_constant_buffers
, 0);
2301 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
].atom
, id
++, r600_emit_gs_constant_buffers
, 0);
2302 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
].atom
, id
++, r600_emit_ps_constant_buffers
, 0);
2304 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2305 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
2307 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].states
.atom
, id
++, r600_emit_vs_sampler_states
, 0);
2308 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].states
.atom
, id
++, r600_emit_gs_sampler_states
, 0);
2309 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].states
.atom
, id
++, r600_emit_ps_sampler_states
, 0);
2311 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
.atom
, id
++, r600_emit_vs_sampler_views
, 0);
2312 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
.atom
, id
++, r600_emit_gs_sampler_views
, 0);
2313 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.atom
, id
++, r600_emit_ps_sampler_views
, 0);
2314 r600_init_atom(rctx
, &rctx
->vertex_buffer_state
.atom
, id
++, r600_emit_vertex_buffers
, 0);
2316 r600_init_atom(rctx
, &rctx
->vgt_state
.atom
, id
++, r600_emit_vgt_state
, 6);
2317 r600_init_atom(rctx
, &rctx
->vgt2_state
.atom
, id
++, r600_emit_vgt2_state
, 3);
2319 r600_init_atom(rctx
, &rctx
->seamless_cube_map
.atom
, id
++, r600_emit_seamless_cube_map
, 3);
2320 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, r600_emit_sample_mask
, 3);
2321 rctx
->sample_mask
.sample_mask
= ~0;
2323 r600_init_atom(rctx
, &rctx
->alphatest_state
.atom
, id
++, r600_emit_alphatest_state
, 6);
2324 r600_init_atom(rctx
, &rctx
->blend_color
.atom
, id
++, r600_emit_blend_color
, 6);
2325 r600_init_atom(rctx
, &rctx
->blend_state
.atom
, id
++, r600_emit_cso_state
, 0);
2326 r600_init_atom(rctx
, &rctx
->cb_misc_state
.atom
, id
++, r600_emit_cb_misc_state
, 7);
2327 r600_init_atom(rctx
, &rctx
->clip_misc_state
.atom
, id
++, r600_emit_clip_misc_state
, 6);
2328 r600_init_atom(rctx
, &rctx
->clip_state
.atom
, id
++, r600_emit_clip_state
, 26);
2329 r600_init_atom(rctx
, &rctx
->db_misc_state
.atom
, id
++, r600_emit_db_misc_state
, 7);
2330 r600_init_atom(rctx
, &rctx
->db_state
.atom
, id
++, r600_emit_db_state
, 11);
2331 r600_init_atom(rctx
, &rctx
->dsa_state
.atom
, id
++, r600_emit_cso_state
, 0);
2332 r600_init_atom(rctx
, &rctx
->poly_offset_state
.atom
, id
++, r600_emit_polygon_offset
, 6);
2333 r600_init_atom(rctx
, &rctx
->rasterizer_state
.atom
, id
++, r600_emit_cso_state
, 0);
2334 r600_init_atom(rctx
, &rctx
->scissor
.atom
, id
++, r600_emit_scissor_state
, 4);
2335 r600_init_atom(rctx
, &rctx
->config_state
.atom
, id
++, r600_emit_config_state
, 3);
2336 r600_init_atom(rctx
, &rctx
->stencil_ref
.atom
, id
++, r600_emit_stencil_ref
, 4);
2337 r600_init_atom(rctx
, &rctx
->viewport
.atom
, id
++, r600_emit_viewport_state
, 8);
2338 r600_init_atom(rctx
, &rctx
->vertex_fetch_shader
.atom
, id
++, r600_emit_vertex_fetch_shader
, 5);
2339 r600_init_atom(rctx
, &rctx
->streamout
.begin_atom
, id
++, r600_emit_streamout_begin
, 0);
2341 rctx
->context
.create_blend_state
= r600_create_blend_state
;
2342 rctx
->context
.create_depth_stencil_alpha_state
= r600_create_dsa_state
;
2343 rctx
->context
.create_rasterizer_state
= r600_create_rs_state
;
2344 rctx
->context
.create_sampler_state
= r600_create_sampler_state
;
2345 rctx
->context
.create_sampler_view
= r600_create_sampler_view
;
2346 rctx
->context
.set_framebuffer_state
= r600_set_framebuffer_state
;
2347 rctx
->context
.set_polygon_stipple
= r600_set_polygon_stipple
;
2348 rctx
->context
.set_scissor_state
= r600_set_scissor_state
;
2351 /* Adjust GPR allocation on R6xx/R7xx */
2352 bool r600_adjust_gprs(struct r600_context
*rctx
)
2354 unsigned num_ps_gprs
= rctx
->ps_shader
->current
->shader
.bc
.ngpr
;
2355 unsigned num_vs_gprs
= rctx
->vs_shader
->current
->shader
.bc
.ngpr
;
2356 unsigned new_num_ps_gprs
= num_ps_gprs
;
2357 unsigned new_num_vs_gprs
= num_vs_gprs
;
2358 unsigned cur_num_ps_gprs
= G_008C04_NUM_PS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_1
);
2359 unsigned cur_num_vs_gprs
= G_008C04_NUM_VS_GPRS(rctx
->config_state
.sq_gpr_resource_mgmt_1
);
2360 unsigned def_num_ps_gprs
= rctx
->default_ps_gprs
;
2361 unsigned def_num_vs_gprs
= rctx
->default_vs_gprs
;
2362 unsigned def_num_clause_temp_gprs
= rctx
->r6xx_num_clause_temp_gprs
;
2363 /* hardware will reserve twice num_clause_temp_gprs */
2364 unsigned max_gprs
= def_num_ps_gprs
+ def_num_vs_gprs
+ def_num_clause_temp_gprs
* 2;
2367 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2368 if (new_num_ps_gprs
> cur_num_ps_gprs
|| new_num_vs_gprs
> cur_num_vs_gprs
) {
2369 /* try to use switch back to default */
2370 if (new_num_ps_gprs
> def_num_ps_gprs
|| new_num_vs_gprs
> def_num_vs_gprs
) {
2371 /* always privilege vs stage so that at worst we have the
2372 * pixel stage producing wrong output (not the vertex
2374 new_num_ps_gprs
= max_gprs
- (new_num_vs_gprs
+ def_num_clause_temp_gprs
* 2);
2375 new_num_vs_gprs
= num_vs_gprs
;
2377 new_num_ps_gprs
= def_num_ps_gprs
;
2378 new_num_vs_gprs
= def_num_vs_gprs
;
2384 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2385 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2386 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2387 * it will lockup. So in this case just discard the draw command
2388 * and don't change the current gprs repartitions.
2390 if (num_ps_gprs
> new_num_ps_gprs
|| num_vs_gprs
> new_num_vs_gprs
) {
2391 R600_ERR("ps & vs shader require too many register (%d + %d) "
2392 "for a combined maximum of %d\n",
2393 num_ps_gprs
, num_vs_gprs
, max_gprs
);
2397 /* in some case we endup recomputing the current value */
2398 tmp
= S_008C04_NUM_PS_GPRS(new_num_ps_gprs
) |
2399 S_008C04_NUM_VS_GPRS(new_num_vs_gprs
) |
2400 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs
);
2401 if (rctx
->config_state
.sq_gpr_resource_mgmt_1
!= tmp
) {
2402 rctx
->config_state
.sq_gpr_resource_mgmt_1
= tmp
;
2403 rctx
->config_state
.atom
.dirty
= true;
2404 rctx
->flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
2409 void r600_init_atom_start_cs(struct r600_context
*rctx
)
2424 int num_ps_stack_entries
;
2425 int num_vs_stack_entries
;
2426 int num_gs_stack_entries
;
2427 int num_es_stack_entries
;
2428 enum radeon_family family
;
2429 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2432 r600_init_command_buffer(cb
, 256);
2434 /* R6xx requires this packet at the start of each command buffer */
2435 if (rctx
->chip_class
== R600
) {
2436 r600_store_value(cb
, PKT3(PKT3_START_3D_CMDBUF
, 0, 0));
2437 r600_store_value(cb
, 0);
2439 /* All asics require this one */
2440 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2441 r600_store_value(cb
, 0x80000000);
2442 r600_store_value(cb
, 0x80000000);
2444 /* We're setting config registers here. */
2445 r600_store_value(cb
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2446 r600_store_value(cb
, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2448 family
= rctx
->family
;
2460 num_ps_threads
= 136;
2461 num_vs_threads
= 48;
2464 num_ps_stack_entries
= 128;
2465 num_vs_stack_entries
= 128;
2466 num_gs_stack_entries
= 0;
2467 num_es_stack_entries
= 0;
2476 num_ps_threads
= 144;
2477 num_vs_threads
= 40;
2480 num_ps_stack_entries
= 40;
2481 num_vs_stack_entries
= 40;
2482 num_gs_stack_entries
= 32;
2483 num_es_stack_entries
= 16;
2495 num_ps_threads
= 136;
2496 num_vs_threads
= 48;
2499 num_ps_stack_entries
= 40;
2500 num_vs_stack_entries
= 40;
2501 num_gs_stack_entries
= 32;
2502 num_es_stack_entries
= 16;
2510 num_ps_threads
= 136;
2511 num_vs_threads
= 48;
2514 num_ps_stack_entries
= 40;
2515 num_vs_stack_entries
= 40;
2516 num_gs_stack_entries
= 32;
2517 num_es_stack_entries
= 16;
2525 num_ps_threads
= 188;
2526 num_vs_threads
= 60;
2529 num_ps_stack_entries
= 256;
2530 num_vs_stack_entries
= 256;
2531 num_gs_stack_entries
= 0;
2532 num_es_stack_entries
= 0;
2541 num_ps_threads
= 188;
2542 num_vs_threads
= 60;
2545 num_ps_stack_entries
= 128;
2546 num_vs_stack_entries
= 128;
2547 num_gs_stack_entries
= 0;
2548 num_es_stack_entries
= 0;
2556 num_ps_threads
= 144;
2557 num_vs_threads
= 48;
2560 num_ps_stack_entries
= 128;
2561 num_vs_stack_entries
= 128;
2562 num_gs_stack_entries
= 0;
2563 num_es_stack_entries
= 0;
2567 rctx
->default_ps_gprs
= num_ps_gprs
;
2568 rctx
->default_vs_gprs
= num_vs_gprs
;
2569 rctx
->r6xx_num_clause_temp_gprs
= num_temp_gprs
;
2581 tmp
|= S_008C00_VC_ENABLE(1);
2584 tmp
|= S_008C00_DX9_CONSTS(0);
2585 tmp
|= S_008C00_ALU_INST_PREFER_VECTOR(1);
2586 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2587 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2588 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2589 tmp
|= S_008C00_ES_PRIO(es_prio
);
2590 r600_store_config_reg(cb
, R_008C00_SQ_CONFIG
, tmp
);
2592 /* SQ_GPR_RESOURCE_MGMT_2 */
2593 tmp
= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
2594 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
2595 r600_store_config_reg_seq(cb
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, 4);
2596 r600_store_value(cb
, tmp
);
2598 /* SQ_THREAD_RESOURCE_MGMT */
2599 tmp
= S_008C0C_NUM_PS_THREADS(num_ps_threads
);
2600 tmp
|= S_008C0C_NUM_VS_THREADS(num_vs_threads
);
2601 tmp
|= S_008C0C_NUM_GS_THREADS(num_gs_threads
);
2602 tmp
|= S_008C0C_NUM_ES_THREADS(num_es_threads
);
2603 r600_store_value(cb
, tmp
); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2605 /* SQ_STACK_RESOURCE_MGMT_1 */
2606 tmp
= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
2607 tmp
|= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
2608 r600_store_value(cb
, tmp
); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2610 /* SQ_STACK_RESOURCE_MGMT_2 */
2611 tmp
= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
2612 tmp
|= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
2613 r600_store_value(cb
, tmp
); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2615 r600_store_config_reg(cb
, R_009714_VC_ENHANCE
, 0);
2617 if (rctx
->chip_class
>= R700
) {
2618 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0x00004000);
2619 r600_store_config_reg(cb
, R_009830_DB_DEBUG
, 0);
2620 r600_store_config_reg(cb
, R_009838_DB_WATERMARKS
, 0x00420204);
2621 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2623 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0);
2624 r600_store_config_reg(cb
, R_009830_DB_DEBUG
, 0x82000000);
2625 r600_store_config_reg(cb
, R_009838_DB_WATERMARKS
, 0x01020204);
2626 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 1);
2628 r600_store_context_reg_seq(cb
, R_0288A8_SQ_ESGS_RING_ITEMSIZE
, 9);
2629 r600_store_value(cb
, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2630 r600_store_value(cb
, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2631 r600_store_value(cb
, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2632 r600_store_value(cb
, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2633 r600_store_value(cb
, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2634 r600_store_value(cb
, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2635 r600_store_value(cb
, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2636 r600_store_value(cb
, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2637 r600_store_value(cb
, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2639 /* to avoid GPU doing any preloading of constant from random address */
2640 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 8);
2641 r600_store_value(cb
, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2642 r600_store_value(cb
, 0);
2643 r600_store_value(cb
, 0);
2644 r600_store_value(cb
, 0);
2645 r600_store_value(cb
, 0);
2646 r600_store_value(cb
, 0);
2647 r600_store_value(cb
, 0);
2648 r600_store_value(cb
, 0);
2649 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 8);
2650 r600_store_value(cb
, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2651 r600_store_value(cb
, 0);
2652 r600_store_value(cb
, 0);
2653 r600_store_value(cb
, 0);
2654 r600_store_value(cb
, 0);
2655 r600_store_value(cb
, 0);
2656 r600_store_value(cb
, 0);
2657 r600_store_value(cb
, 0);
2659 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2660 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2661 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2662 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2663 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2664 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2665 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2666 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2667 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2668 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2669 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2670 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2671 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2672 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE, 0); */
2674 r600_store_context_reg(cb
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
2675 r600_store_context_reg(cb
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 0);
2676 r600_store_context_reg(cb
, R_028AA4_VGT_INSTANCE_STEP_RATE_1
, 0);
2678 r600_store_context_reg_seq(cb
, R_028AB0_VGT_STRMOUT_EN
, 3);
2679 r600_store_value(cb
, 0); /* R_028AB0_VGT_STRMOUT_EN */
2680 r600_store_value(cb
, 1); /* R_028AB4_VGT_REUSE_OFF */
2681 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2683 r600_store_context_reg(cb
, R_028B20_VGT_STRMOUT_BUFFER_EN
, 0);
2685 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2687 r600_store_context_reg(cb
, R_028028_DB_STENCIL_CLEAR
, 0);
2689 r600_store_context_reg_seq(cb
, R_0286DC_SPI_FOG_CNTL
, 3);
2690 r600_store_value(cb
, 0); /* R_0286DC_SPI_FOG_CNTL */
2691 r600_store_value(cb
, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2692 r600_store_value(cb
, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2694 r600_store_context_reg_seq(cb
, R_028D2C_DB_SRESULTS_COMPARE_STATE1
, 2);
2695 r600_store_value(cb
, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2696 r600_store_value(cb
, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2698 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2699 r600_store_context_reg(cb
, R_028A48_PA_SC_MPASS_PS_CNTL
, 0);
2701 r600_store_context_reg_seq(cb
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 4);
2702 r600_store_value(cb
, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2703 r600_store_value(cb
, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2704 r600_store_value(cb
, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2705 r600_store_value(cb
, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2707 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
2708 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2709 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2711 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x43F);
2713 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2714 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2716 if (rctx
->chip_class
>= R700
) {
2717 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2720 r600_store_context_reg_seq(cb
, R_028C30_CB_CLRCMP_CONTROL
, 4);
2721 r600_store_value(cb
, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2722 r600_store_value(cb
, 0); /* R_028C34_CB_CLRCMP_SRC */
2723 r600_store_value(cb
, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2724 r600_store_value(cb
, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2726 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2727 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2728 r600_store_value(cb
, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2730 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2731 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2732 r600_store_value(cb
, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2734 r600_store_context_reg_seq(cb
, R_0288CC_SQ_PGM_CF_OFFSET_PS
, 2);
2735 r600_store_value(cb
, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2736 r600_store_value(cb
, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2738 r600_store_context_reg(cb
, R_0288E0_SQ_VTX_SEMANTIC_CLEAR
, ~0);
2740 r600_store_context_reg_seq(cb
, R_028400_VGT_MAX_VTX_INDX
, 2);
2741 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2742 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2744 r600_store_context_reg(cb
, R_0288A4_SQ_PGM_RESOURCES_FS
, 0);
2745 r600_store_context_reg(cb
, R_0288DC_SQ_PGM_CF_OFFSET_FS
, 0);
2747 if (rctx
->chip_class
== R700
&& rctx
->screen
->has_streamout
)
2748 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
2749 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2750 if (rctx
->screen
->has_streamout
) {
2751 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2754 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
, 0x1000FFF);
2755 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
+ (32 * 4), 0x1000FFF);
2758 void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2760 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2761 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2762 struct r600_shader
*rshader
= &shader
->shader
;
2763 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
;
2764 int pos_index
= -1, face_index
= -1;
2765 unsigned tmp
, sid
, ufi
= 0;
2766 int need_linear
= 0;
2767 unsigned z_export
= 0, stencil_export
= 0;
2768 unsigned sprite_coord_enable
= rctx
->rasterizer
? rctx
->rasterizer
->sprite_coord_enable
: 0;
2772 for (i
= 0; i
< rshader
->ninput
; i
++) {
2773 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
2775 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
2778 sid
= rshader
->input
[i
].spi_sid
;
2780 tmp
= S_028644_SEMANTIC(sid
);
2782 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
2783 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2784 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
2785 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
))
2786 tmp
|= S_028644_FLAT_SHADE(1);
2788 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
2789 sprite_coord_enable
& (1 << rshader
->input
[i
].sid
)) {
2790 tmp
|= S_028644_PT_SPRITE_TEX(1);
2793 if (rshader
->input
[i
].centroid
)
2794 tmp
|= S_028644_SEL_CENTROID(1);
2796 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
) {
2798 tmp
|= S_028644_SEL_LINEAR(1);
2801 r600_pipe_state_add_reg(rstate
, R_028644_SPI_PS_INPUT_CNTL_0
+ i
* 4,
2805 db_shader_control
= 0;
2806 for (i
= 0; i
< rshader
->noutput
; i
++) {
2807 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2809 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2812 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(z_export
);
2813 db_shader_control
|= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export
);
2814 if (rshader
->uses_kill
)
2815 db_shader_control
|= S_02880C_KILL_ENABLE(1);
2818 for (i
= 0; i
< rshader
->noutput
; i
++) {
2819 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
2820 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
) {
2824 num_cout
= rshader
->nr_ps_color_exports
;
2825 exports_ps
|= S_028854_EXPORT_COLORS(num_cout
);
2827 /* always at least export 1 component per pixel */
2831 shader
->nr_ps_color_outputs
= num_cout
;
2833 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(rshader
->ninput
) |
2834 S_0286CC_PERSP_GRADIENT_ENA(1)|
2835 S_0286CC_LINEAR_GRADIENT_ENA(need_linear
);
2837 if (pos_index
!= -1) {
2838 spi_ps_in_control_0
|= (S_0286CC_POSITION_ENA(1) |
2839 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
2840 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
) |
2841 S_0286CC_BARYC_SAMPLE_CNTL(1));
2845 spi_ps_in_control_1
= 0;
2846 if (face_index
!= -1) {
2847 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
2848 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
2851 /* HW bug in original R600 */
2852 if (rctx
->family
== CHIP_R600
)
2855 r600_pipe_state_add_reg(rstate
, R_0286CC_SPI_PS_IN_CONTROL_0
, spi_ps_in_control_0
);
2856 r600_pipe_state_add_reg(rstate
, R_0286D0_SPI_PS_IN_CONTROL_1
, spi_ps_in_control_1
);
2857 r600_pipe_state_add_reg(rstate
, R_0286D8_SPI_INPUT_Z
, spi_input_z
);
2858 r600_pipe_state_add_reg_bo(rstate
,
2859 R_028840_SQ_PGM_START_PS
,
2860 0, shader
->bo
, RADEON_USAGE_READ
);
2861 r600_pipe_state_add_reg(rstate
,
2862 R_028850_SQ_PGM_RESOURCES_PS
,
2863 S_028850_NUM_GPRS(rshader
->bc
.ngpr
) |
2864 S_028850_STACK_SIZE(rshader
->bc
.nstack
) |
2865 S_028850_UNCACHED_FIRST_INST(ufi
));
2866 r600_pipe_state_add_reg(rstate
,
2867 R_028854_SQ_PGM_EXPORTS_PS
,
2869 /* only set some bits here, the other bits are set in the dsa state */
2870 shader
->db_shader_control
= db_shader_control
;
2871 shader
->ps_depth_export
= z_export
| stencil_export
;
2873 shader
->sprite_coord_enable
= sprite_coord_enable
;
2874 if (rctx
->rasterizer
)
2875 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
2878 void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2880 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2881 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2882 struct r600_shader
*rshader
= &shader
->shader
;
2883 unsigned spi_vs_out_id
[10] = {};
2884 unsigned i
, tmp
, nparams
= 0;
2886 /* clear previous register */
2889 for (i
= 0; i
< rshader
->noutput
; i
++) {
2890 if (rshader
->output
[i
].spi_sid
) {
2891 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
2892 spi_vs_out_id
[nparams
/ 4] |= tmp
;
2897 for (i
= 0; i
< 10; i
++) {
2898 r600_pipe_state_add_reg(rstate
,
2899 R_028614_SPI_VS_OUT_ID_0
+ i
* 4,
2903 /* Certain attributes (position, psize, etc.) don't count as params.
2904 * VS is required to export at least one param and r600_shader_from_tgsi()
2905 * takes care of adding a dummy export.
2910 r600_pipe_state_add_reg(rstate
,
2911 R_0286C4_SPI_VS_OUT_CONFIG
,
2912 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
2913 r600_pipe_state_add_reg(rstate
,
2914 R_028868_SQ_PGM_RESOURCES_VS
,
2915 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
2916 S_028868_STACK_SIZE(rshader
->bc
.nstack
));
2917 r600_pipe_state_add_reg_bo(rstate
,
2918 R_028858_SQ_PGM_START_VS
,
2919 0, shader
->bo
, RADEON_USAGE_READ
);
2921 shader
->pa_cl_vs_out_cntl
=
2922 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
2923 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
2924 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
2925 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
);
2928 void *r600_create_resolve_blend(struct r600_context
*rctx
)
2930 struct pipe_blend_state blend
;
2933 memset(&blend
, 0, sizeof(blend
));
2934 blend
.independent_blend_enable
= true;
2935 for (i
= 0; i
< 2; i
++) {
2936 blend
.rt
[i
].colormask
= 0xf;
2937 blend
.rt
[i
].blend_enable
= 1;
2938 blend
.rt
[i
].rgb_func
= PIPE_BLEND_ADD
;
2939 blend
.rt
[i
].alpha_func
= PIPE_BLEND_ADD
;
2940 blend
.rt
[i
].rgb_src_factor
= PIPE_BLENDFACTOR_ZERO
;
2941 blend
.rt
[i
].rgb_dst_factor
= PIPE_BLENDFACTOR_ZERO
;
2942 blend
.rt
[i
].alpha_src_factor
= PIPE_BLENDFACTOR_ZERO
;
2943 blend
.rt
[i
].alpha_dst_factor
= PIPE_BLENDFACTOR_ZERO
;
2945 return r600_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_SPECIAL_RESOLVE_BOX
);
2948 void *r700_create_resolve_blend(struct r600_context
*rctx
)
2950 struct pipe_blend_state blend
;
2952 memset(&blend
, 0, sizeof(blend
));
2953 blend
.independent_blend_enable
= true;
2954 blend
.rt
[0].colormask
= 0xf;
2955 return r600_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_SPECIAL_RESOLVE_BOX
);
2958 void *r600_create_decompress_blend(struct r600_context
*rctx
)
2960 struct pipe_blend_state blend
;
2962 memset(&blend
, 0, sizeof(blend
));
2963 blend
.independent_blend_enable
= true;
2964 blend
.rt
[0].colormask
= 0xf;
2965 return r600_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_SPECIAL_EXPAND_SAMPLES
);
2968 void *r600_create_db_flush_dsa(struct r600_context
*rctx
)
2970 struct pipe_depth_stencil_alpha_state dsa
;
2971 boolean quirk
= false;
2973 if (rctx
->family
== CHIP_RV610
|| rctx
->family
== CHIP_RV630
||
2974 rctx
->family
== CHIP_RV620
|| rctx
->family
== CHIP_RV635
)
2977 memset(&dsa
, 0, sizeof(dsa
));
2980 dsa
.depth
.enabled
= 1;
2981 dsa
.depth
.func
= PIPE_FUNC_LEQUAL
;
2982 dsa
.stencil
[0].enabled
= 1;
2983 dsa
.stencil
[0].func
= PIPE_FUNC_ALWAYS
;
2984 dsa
.stencil
[0].zpass_op
= PIPE_STENCIL_OP_KEEP
;
2985 dsa
.stencil
[0].zfail_op
= PIPE_STENCIL_OP_INCR
;
2986 dsa
.stencil
[0].writemask
= 0xff;
2989 return rctx
->context
.create_depth_stencil_alpha_state(&rctx
->context
, &dsa
);
2992 void r600_update_db_shader_control(struct r600_context
* rctx
)
2994 bool dual_export
= rctx
->framebuffer
.export_16bpc
&&
2995 !rctx
->ps_shader
->current
->ps_depth_export
;
2997 unsigned db_shader_control
= rctx
->ps_shader
->current
->db_shader_control
|
2998 S_02880C_DUAL_EXPORT_ENABLE(dual_export
);
3000 /* When alpha test is enabled we can't trust the hw to make the proper
3001 * decision on the order in which ztest should be run related to fragment
3004 * If alpha test is enabled perform z test after fragment. RE_Z (early
3005 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
3007 if (rctx
->alphatest_state
.sx_alpha_test_control
) {
3008 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
3010 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
3013 if (db_shader_control
!= rctx
->db_misc_state
.db_shader_control
) {
3014 rctx
->db_misc_state
.db_shader_control
= db_shader_control
;
3015 rctx
->db_misc_state
.atom
.dirty
= true;
3019 static INLINE
unsigned r600_array_mode(unsigned mode
)
3022 case RADEON_SURF_MODE_LINEAR_ALIGNED
: return V_0280A0_ARRAY_LINEAR_ALIGNED
;
3024 case RADEON_SURF_MODE_1D
: return V_0280A0_ARRAY_1D_TILED_THIN1
;
3026 case RADEON_SURF_MODE_2D
: return V_0280A0_ARRAY_2D_TILED_THIN1
;
3028 case RADEON_SURF_MODE_LINEAR
: return V_0280A0_ARRAY_LINEAR_GENERAL
;
3032 static boolean
r600_dma_copy_tile(struct r600_context
*rctx
,
3033 struct pipe_resource
*dst
,
3038 struct pipe_resource
*src
,
3043 unsigned copy_height
,
3047 struct radeon_winsys_cs
*cs
= rctx
->rings
.dma
.cs
;
3048 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
3049 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
3050 unsigned array_mode
, lbpp
, pitch_tile_max
, slice_tile_max
, size
;
3051 unsigned ncopy
, height
, cheight
, detile
, i
, x
, y
, z
, src_mode
, dst_mode
;
3052 uint64_t base
, addr
;
3054 /* make sure that the dma ring is only one active */
3055 rctx
->rings
.gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
);
3057 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
3058 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
3059 /* downcast linear aligned to linear to simplify test */
3060 src_mode
= src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: src_mode
;
3061 dst_mode
= dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: dst_mode
;
3062 assert(dst_mode
!= src_mode
);
3065 lbpp
= util_logbase2(bpp
);
3066 pitch_tile_max
= ((pitch
/ bpp
) >> 3) - 1;
3068 if (dst_mode
== RADEON_SURF_MODE_LINEAR
) {
3070 array_mode
= r600_array_mode(src_mode
);
3071 slice_tile_max
= (rsrc
->surface
.level
[src_level
].nblk_x
* rsrc
->surface
.level
[src_level
].nblk_y
) >> 6;
3072 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
3073 /* linear height must be the same as the slice tile max height, it's ok even
3074 * if the linear destination/source have smaller heigh as the size of the
3075 * dma packet will be using the copy_height which is always smaller or equal
3076 * to the linear height
3078 height
= rsrc
->surface
.level
[src_level
].npix_y
;
3083 base
= rsrc
->surface
.level
[src_level
].offset
;
3084 addr
= rdst
->surface
.level
[dst_level
].offset
;
3085 addr
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
3086 addr
+= dst_y
* pitch
+ dst_x
* bpp
;
3089 array_mode
= r600_array_mode(dst_mode
);
3090 slice_tile_max
= (rdst
->surface
.level
[dst_level
].nblk_x
* rdst
->surface
.level
[dst_level
].nblk_y
) >> 6;
3091 slice_tile_max
= slice_tile_max
? slice_tile_max
- 1 : 0;
3092 /* linear height must be the same as the slice tile max height, it's ok even
3093 * if the linear destination/source have smaller heigh as the size of the
3094 * dma packet will be using the copy_height which is always smaller or equal
3095 * to the linear height
3097 height
= rdst
->surface
.level
[dst_level
].npix_y
;
3102 base
= rdst
->surface
.level
[dst_level
].offset
;
3103 addr
= rsrc
->surface
.level
[src_level
].offset
;
3104 addr
+= rsrc
->surface
.level
[src_level
].slice_size
* src_z
;
3105 addr
+= src_y
* pitch
+ src_x
* bpp
;
3107 /* check that we are in dw/base alignment constraint */
3108 if ((addr
& 0x3) || (base
& 0xff)) {
3112 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
3113 * line in the blit. Compute max 8 line we can copy in the size limit
3115 cheight
= ((0x0000ffff << 2) / pitch
) & 0xfffffff8;
3116 ncopy
= (copy_height
/ cheight
) + !!(copy_height
% cheight
);
3117 r600_need_dma_space(rctx
, ncopy
* 7);
3119 for (i
= 0; i
< ncopy
; i
++) {
3120 cheight
= cheight
> copy_height
? copy_height
: cheight
;
3121 size
= (cheight
* pitch
) >> 2;
3122 /* emit reloc before writting cs so that cs is always in consistent state */
3123 r600_context_bo_reloc(rctx
, &rctx
->rings
.dma
, &rsrc
->resource
, RADEON_USAGE_READ
);
3124 r600_context_bo_reloc(rctx
, &rctx
->rings
.dma
, &rdst
->resource
, RADEON_USAGE_WRITE
);
3125 cs
->buf
[cs
->cdw
++] = DMA_PACKET(DMA_PACKET_COPY
, 1, 0, size
);
3126 cs
->buf
[cs
->cdw
++] = base
>> 8;
3127 cs
->buf
[cs
->cdw
++] = (detile
<< 31) | (array_mode
<< 27) |
3128 (lbpp
<< 24) | ((height
- 1) << 10) |
3130 cs
->buf
[cs
->cdw
++] = (slice_tile_max
<< 12) | (z
<< 0);
3131 cs
->buf
[cs
->cdw
++] = (x
<< 3) | (y
<< 17);
3132 cs
->buf
[cs
->cdw
++] = addr
& 0xfffffffc;
3133 cs
->buf
[cs
->cdw
++] = (addr
>> 32UL) & 0xff;
3134 copy_height
-= cheight
;
3135 addr
+= cheight
* pitch
;
3141 boolean
r600_dma_blit(struct pipe_context
*ctx
,
3142 struct pipe_resource
*dst
,
3144 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
3145 struct pipe_resource
*src
,
3147 const struct pipe_box
*src_box
)
3149 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3150 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
3151 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
3152 unsigned dst_pitch
, src_pitch
, bpp
, dst_mode
, src_mode
, copy_height
;
3153 unsigned src_w
, dst_w
;
3155 if (rctx
->rings
.dma
.cs
== NULL
) {
3158 if (src
->format
!= dst
->format
) {
3162 bpp
= rdst
->surface
.bpe
;
3163 dst_pitch
= rdst
->surface
.level
[dst_level
].pitch_bytes
;
3164 src_pitch
= rsrc
->surface
.level
[src_level
].pitch_bytes
;
3165 src_w
= rsrc
->surface
.level
[src_level
].npix_x
;
3166 dst_w
= rdst
->surface
.level
[dst_level
].npix_x
;
3167 copy_height
= src_box
->height
/ rsrc
->surface
.blk_h
;
3169 dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
3170 src_mode
= rsrc
->surface
.level
[src_level
].mode
;
3171 /* downcast linear aligned to linear to simplify test */
3172 src_mode
= src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: src_mode
;
3173 dst_mode
= dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
? RADEON_SURF_MODE_LINEAR
: dst_mode
;
3175 if (src_pitch
!= dst_pitch
|| src_box
->x
|| dst_x
|| src_w
!= dst_w
) {
3176 /* strick requirement on r6xx/r7xx */
3179 /* lot of constraint on alignment this should capture them all */
3180 if ((src_pitch
& 0x7) || (src_box
->y
& 0x7) || (dst_y
& 0x7)) {
3184 if (src_mode
== dst_mode
) {
3185 uint64_t dst_offset
, src_offset
, size
;
3187 /* simple dma blit would do NOTE code here assume :
3190 * dst_pitch == src_pitch
3192 src_offset
= rsrc
->surface
.level
[src_level
].offset
;
3193 src_offset
+= rsrc
->surface
.level
[src_level
].slice_size
* src_box
->z
;
3194 src_offset
+= src_box
->y
* src_pitch
+ src_box
->x
* bpp
;
3195 dst_offset
= rdst
->surface
.level
[dst_level
].offset
;
3196 dst_offset
+= rdst
->surface
.level
[dst_level
].slice_size
* dst_z
;
3197 dst_offset
+= dst_y
* dst_pitch
+ dst_x
* bpp
;
3198 size
= src_box
->height
* src_pitch
;
3199 /* must be dw aligned */
3200 if ((dst_offset
& 0x3) || (src_offset
& 0x3) || (size
& 0x3)) {
3203 r600_dma_copy(rctx
, dst
, src
, dst_offset
, src_offset
, size
);
3205 return r600_dma_copy_tile(rctx
, dst
, dst_level
, dst_x
, dst_y
, dst_z
,
3206 src
, src_level
, src_box
->x
, src_box
->y
, src_box
->z
,
3207 copy_height
, dst_pitch
, bpp
);