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r600g,radeonsi: share r600_texture.c
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static uint32_t r600_translate_colorswap(enum pipe_format format)
145 {
146 switch (format) {
147 /* 8-bit buffers. */
148 case PIPE_FORMAT_A8_UNORM:
149 case PIPE_FORMAT_A8_SNORM:
150 case PIPE_FORMAT_A8_UINT:
151 case PIPE_FORMAT_A8_SINT:
152 case PIPE_FORMAT_A16_UNORM:
153 case PIPE_FORMAT_A16_SNORM:
154 case PIPE_FORMAT_A16_UINT:
155 case PIPE_FORMAT_A16_SINT:
156 case PIPE_FORMAT_A16_FLOAT:
157 case PIPE_FORMAT_A32_UINT:
158 case PIPE_FORMAT_A32_SINT:
159 case PIPE_FORMAT_A32_FLOAT:
160 case PIPE_FORMAT_R4A4_UNORM:
161 return V_0280A0_SWAP_ALT_REV;
162 case PIPE_FORMAT_I8_UNORM:
163 case PIPE_FORMAT_I8_SNORM:
164 case PIPE_FORMAT_I8_UINT:
165 case PIPE_FORMAT_I8_SINT:
166 case PIPE_FORMAT_L8_UNORM:
167 case PIPE_FORMAT_L8_SNORM:
168 case PIPE_FORMAT_L8_UINT:
169 case PIPE_FORMAT_L8_SINT:
170 case PIPE_FORMAT_L8_SRGB:
171 case PIPE_FORMAT_L16_UNORM:
172 case PIPE_FORMAT_L16_SNORM:
173 case PIPE_FORMAT_L16_UINT:
174 case PIPE_FORMAT_L16_SINT:
175 case PIPE_FORMAT_L16_FLOAT:
176 case PIPE_FORMAT_L32_UINT:
177 case PIPE_FORMAT_L32_SINT:
178 case PIPE_FORMAT_L32_FLOAT:
179 case PIPE_FORMAT_I16_UNORM:
180 case PIPE_FORMAT_I16_SNORM:
181 case PIPE_FORMAT_I16_UINT:
182 case PIPE_FORMAT_I16_SINT:
183 case PIPE_FORMAT_I16_FLOAT:
184 case PIPE_FORMAT_I32_UINT:
185 case PIPE_FORMAT_I32_SINT:
186 case PIPE_FORMAT_I32_FLOAT:
187 case PIPE_FORMAT_R8_UNORM:
188 case PIPE_FORMAT_R8_SNORM:
189 case PIPE_FORMAT_R8_UINT:
190 case PIPE_FORMAT_R8_SINT:
191 return V_0280A0_SWAP_STD;
192
193 case PIPE_FORMAT_L4A4_UNORM:
194 case PIPE_FORMAT_A4R4_UNORM:
195 return V_0280A0_SWAP_ALT;
196
197 /* 16-bit buffers. */
198 case PIPE_FORMAT_B5G6R5_UNORM:
199 return V_0280A0_SWAP_STD_REV;
200
201 case PIPE_FORMAT_B5G5R5A1_UNORM:
202 case PIPE_FORMAT_B5G5R5X1_UNORM:
203 return V_0280A0_SWAP_ALT;
204
205 case PIPE_FORMAT_B4G4R4A4_UNORM:
206 case PIPE_FORMAT_B4G4R4X4_UNORM:
207 return V_0280A0_SWAP_ALT;
208
209 case PIPE_FORMAT_Z16_UNORM:
210 return V_0280A0_SWAP_STD;
211
212 case PIPE_FORMAT_L8A8_UNORM:
213 case PIPE_FORMAT_L8A8_SNORM:
214 case PIPE_FORMAT_L8A8_UINT:
215 case PIPE_FORMAT_L8A8_SINT:
216 case PIPE_FORMAT_L8A8_SRGB:
217 case PIPE_FORMAT_L16A16_UNORM:
218 case PIPE_FORMAT_L16A16_SNORM:
219 case PIPE_FORMAT_L16A16_UINT:
220 case PIPE_FORMAT_L16A16_SINT:
221 case PIPE_FORMAT_L16A16_FLOAT:
222 case PIPE_FORMAT_L32A32_UINT:
223 case PIPE_FORMAT_L32A32_SINT:
224 case PIPE_FORMAT_L32A32_FLOAT:
225 case PIPE_FORMAT_R8A8_UNORM:
226 case PIPE_FORMAT_R8A8_SNORM:
227 case PIPE_FORMAT_R8A8_UINT:
228 case PIPE_FORMAT_R8A8_SINT:
229 case PIPE_FORMAT_R16A16_UNORM:
230 case PIPE_FORMAT_R16A16_SNORM:
231 case PIPE_FORMAT_R16A16_UINT:
232 case PIPE_FORMAT_R16A16_SINT:
233 case PIPE_FORMAT_R16A16_FLOAT:
234 case PIPE_FORMAT_R32A32_UINT:
235 case PIPE_FORMAT_R32A32_SINT:
236 case PIPE_FORMAT_R32A32_FLOAT:
237 return V_0280A0_SWAP_ALT;
238 case PIPE_FORMAT_R8G8_UNORM:
239 case PIPE_FORMAT_R8G8_SNORM:
240 case PIPE_FORMAT_R8G8_UINT:
241 case PIPE_FORMAT_R8G8_SINT:
242 return V_0280A0_SWAP_STD;
243
244 case PIPE_FORMAT_R16_UNORM:
245 case PIPE_FORMAT_R16_SNORM:
246 case PIPE_FORMAT_R16_UINT:
247 case PIPE_FORMAT_R16_SINT:
248 case PIPE_FORMAT_R16_FLOAT:
249 return V_0280A0_SWAP_STD;
250
251 /* 32-bit buffers. */
252
253 case PIPE_FORMAT_A8B8G8R8_SRGB:
254 return V_0280A0_SWAP_STD_REV;
255 case PIPE_FORMAT_B8G8R8A8_SRGB:
256 return V_0280A0_SWAP_ALT;
257
258 case PIPE_FORMAT_B8G8R8A8_UNORM:
259 case PIPE_FORMAT_B8G8R8X8_UNORM:
260 return V_0280A0_SWAP_ALT;
261
262 case PIPE_FORMAT_A8R8G8B8_UNORM:
263 case PIPE_FORMAT_X8R8G8B8_UNORM:
264 return V_0280A0_SWAP_ALT_REV;
265 case PIPE_FORMAT_R8G8B8A8_SNORM:
266 case PIPE_FORMAT_R8G8B8A8_UNORM:
267 case PIPE_FORMAT_R8G8B8X8_UNORM:
268 case PIPE_FORMAT_R8G8B8X8_SNORM:
269 case PIPE_FORMAT_R8G8B8X8_SRGB:
270 case PIPE_FORMAT_R8G8B8X8_UINT:
271 case PIPE_FORMAT_R8G8B8X8_SINT:
272 case PIPE_FORMAT_R8G8B8A8_SINT:
273 case PIPE_FORMAT_R8G8B8A8_UINT:
274 return V_0280A0_SWAP_STD;
275
276 case PIPE_FORMAT_A8B8G8R8_UNORM:
277 case PIPE_FORMAT_X8B8G8R8_UNORM:
278 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
279 return V_0280A0_SWAP_STD_REV;
280
281 case PIPE_FORMAT_Z24X8_UNORM:
282 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
283 return V_0280A0_SWAP_STD;
284
285 case PIPE_FORMAT_R10G10B10A2_UNORM:
286 case PIPE_FORMAT_R10G10B10X2_SNORM:
287 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
288 return V_0280A0_SWAP_STD;
289
290 case PIPE_FORMAT_B10G10R10A2_UNORM:
291 case PIPE_FORMAT_B10G10R10A2_UINT:
292 case PIPE_FORMAT_B10G10R10X2_UNORM:
293 return V_0280A0_SWAP_ALT;
294
295 case PIPE_FORMAT_R11G11B10_FLOAT:
296 case PIPE_FORMAT_R16G16_UNORM:
297 case PIPE_FORMAT_R16G16_SNORM:
298 case PIPE_FORMAT_R16G16_FLOAT:
299 case PIPE_FORMAT_R16G16_UINT:
300 case PIPE_FORMAT_R16G16_SINT:
301 case PIPE_FORMAT_R32_UINT:
302 case PIPE_FORMAT_R32_SINT:
303 case PIPE_FORMAT_R32_FLOAT:
304 case PIPE_FORMAT_Z32_FLOAT:
305 return V_0280A0_SWAP_STD;
306
307 /* 64-bit buffers. */
308 case PIPE_FORMAT_R32G32_FLOAT:
309 case PIPE_FORMAT_R32G32_UINT:
310 case PIPE_FORMAT_R32G32_SINT:
311 case PIPE_FORMAT_R16G16B16A16_UNORM:
312 case PIPE_FORMAT_R16G16B16A16_SNORM:
313 case PIPE_FORMAT_R16G16B16A16_UINT:
314 case PIPE_FORMAT_R16G16B16A16_SINT:
315 case PIPE_FORMAT_R16G16B16A16_FLOAT:
316 case PIPE_FORMAT_R16G16B16X16_UNORM:
317 case PIPE_FORMAT_R16G16B16X16_SNORM:
318 case PIPE_FORMAT_R16G16B16X16_FLOAT:
319 case PIPE_FORMAT_R16G16B16X16_UINT:
320 case PIPE_FORMAT_R16G16B16X16_SINT:
321 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
322
323 /* 128-bit buffers. */
324 case PIPE_FORMAT_R32G32B32A32_FLOAT:
325 case PIPE_FORMAT_R32G32B32A32_SNORM:
326 case PIPE_FORMAT_R32G32B32A32_UNORM:
327 case PIPE_FORMAT_R32G32B32A32_SINT:
328 case PIPE_FORMAT_R32G32B32A32_UINT:
329 case PIPE_FORMAT_R32G32B32X32_FLOAT:
330 case PIPE_FORMAT_R32G32B32X32_UINT:
331 case PIPE_FORMAT_R32G32B32X32_SINT:
332 return V_0280A0_SWAP_STD;
333 default:
334 R600_ERR("unsupported colorswap format %d\n", format);
335 return ~0U;
336 }
337 return ~0U;
338 }
339
340 static uint32_t r600_translate_colorformat(enum pipe_format format)
341 {
342 switch (format) {
343 case PIPE_FORMAT_L4A4_UNORM:
344 case PIPE_FORMAT_R4A4_UNORM:
345 case PIPE_FORMAT_A4R4_UNORM:
346 return V_0280A0_COLOR_4_4;
347
348 /* 8-bit buffers. */
349 case PIPE_FORMAT_A8_UNORM:
350 case PIPE_FORMAT_A8_SNORM:
351 case PIPE_FORMAT_A8_UINT:
352 case PIPE_FORMAT_A8_SINT:
353 case PIPE_FORMAT_I8_UNORM:
354 case PIPE_FORMAT_I8_SNORM:
355 case PIPE_FORMAT_I8_UINT:
356 case PIPE_FORMAT_I8_SINT:
357 case PIPE_FORMAT_L8_UNORM:
358 case PIPE_FORMAT_L8_SNORM:
359 case PIPE_FORMAT_L8_UINT:
360 case PIPE_FORMAT_L8_SINT:
361 case PIPE_FORMAT_L8_SRGB:
362 case PIPE_FORMAT_R8_UNORM:
363 case PIPE_FORMAT_R8_SNORM:
364 case PIPE_FORMAT_R8_UINT:
365 case PIPE_FORMAT_R8_SINT:
366 return V_0280A0_COLOR_8;
367
368 /* 16-bit buffers. */
369 case PIPE_FORMAT_B5G6R5_UNORM:
370 return V_0280A0_COLOR_5_6_5;
371
372 case PIPE_FORMAT_B5G5R5A1_UNORM:
373 case PIPE_FORMAT_B5G5R5X1_UNORM:
374 return V_0280A0_COLOR_1_5_5_5;
375
376 case PIPE_FORMAT_B4G4R4A4_UNORM:
377 case PIPE_FORMAT_B4G4R4X4_UNORM:
378 return V_0280A0_COLOR_4_4_4_4;
379
380 case PIPE_FORMAT_Z16_UNORM:
381 return V_0280A0_COLOR_16;
382
383 case PIPE_FORMAT_L8A8_UNORM:
384 case PIPE_FORMAT_L8A8_SNORM:
385 case PIPE_FORMAT_L8A8_UINT:
386 case PIPE_FORMAT_L8A8_SINT:
387 case PIPE_FORMAT_L8A8_SRGB:
388 case PIPE_FORMAT_R8G8_UNORM:
389 case PIPE_FORMAT_R8G8_SNORM:
390 case PIPE_FORMAT_R8G8_UINT:
391 case PIPE_FORMAT_R8G8_SINT:
392 case PIPE_FORMAT_R8A8_UNORM:
393 case PIPE_FORMAT_R8A8_SNORM:
394 case PIPE_FORMAT_R8A8_UINT:
395 case PIPE_FORMAT_R8A8_SINT:
396 return V_0280A0_COLOR_8_8;
397
398 case PIPE_FORMAT_R16_UNORM:
399 case PIPE_FORMAT_R16_SNORM:
400 case PIPE_FORMAT_R16_UINT:
401 case PIPE_FORMAT_R16_SINT:
402 case PIPE_FORMAT_A16_UNORM:
403 case PIPE_FORMAT_A16_SNORM:
404 case PIPE_FORMAT_A16_UINT:
405 case PIPE_FORMAT_A16_SINT:
406 case PIPE_FORMAT_L16_UNORM:
407 case PIPE_FORMAT_L16_SNORM:
408 case PIPE_FORMAT_L16_UINT:
409 case PIPE_FORMAT_L16_SINT:
410 case PIPE_FORMAT_I16_UNORM:
411 case PIPE_FORMAT_I16_SNORM:
412 case PIPE_FORMAT_I16_UINT:
413 case PIPE_FORMAT_I16_SINT:
414 return V_0280A0_COLOR_16;
415
416 case PIPE_FORMAT_R16_FLOAT:
417 case PIPE_FORMAT_A16_FLOAT:
418 case PIPE_FORMAT_L16_FLOAT:
419 case PIPE_FORMAT_I16_FLOAT:
420 return V_0280A0_COLOR_16_FLOAT;
421
422 /* 32-bit buffers. */
423 case PIPE_FORMAT_A8B8G8R8_SRGB:
424 case PIPE_FORMAT_A8B8G8R8_UNORM:
425 case PIPE_FORMAT_A8R8G8B8_UNORM:
426 case PIPE_FORMAT_B8G8R8A8_SRGB:
427 case PIPE_FORMAT_B8G8R8A8_UNORM:
428 case PIPE_FORMAT_B8G8R8X8_UNORM:
429 case PIPE_FORMAT_R8G8B8A8_SNORM:
430 case PIPE_FORMAT_R8G8B8A8_UNORM:
431 case PIPE_FORMAT_R8G8B8X8_UNORM:
432 case PIPE_FORMAT_R8G8B8X8_SNORM:
433 case PIPE_FORMAT_R8G8B8X8_SRGB:
434 case PIPE_FORMAT_R8G8B8X8_UINT:
435 case PIPE_FORMAT_R8G8B8X8_SINT:
436 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
437 case PIPE_FORMAT_X8B8G8R8_UNORM:
438 case PIPE_FORMAT_X8R8G8B8_UNORM:
439 case PIPE_FORMAT_R8G8B8A8_SINT:
440 case PIPE_FORMAT_R8G8B8A8_UINT:
441 return V_0280A0_COLOR_8_8_8_8;
442
443 case PIPE_FORMAT_R10G10B10A2_UNORM:
444 case PIPE_FORMAT_R10G10B10X2_SNORM:
445 case PIPE_FORMAT_B10G10R10A2_UNORM:
446 case PIPE_FORMAT_B10G10R10A2_UINT:
447 case PIPE_FORMAT_B10G10R10X2_UNORM:
448 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
449 return V_0280A0_COLOR_2_10_10_10;
450
451 case PIPE_FORMAT_Z24X8_UNORM:
452 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
453 return V_0280A0_COLOR_8_24;
454
455 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
456 return V_0280A0_COLOR_X24_8_32_FLOAT;
457
458 case PIPE_FORMAT_R32_UINT:
459 case PIPE_FORMAT_R32_SINT:
460 case PIPE_FORMAT_A32_UINT:
461 case PIPE_FORMAT_A32_SINT:
462 case PIPE_FORMAT_L32_UINT:
463 case PIPE_FORMAT_L32_SINT:
464 case PIPE_FORMAT_I32_UINT:
465 case PIPE_FORMAT_I32_SINT:
466 return V_0280A0_COLOR_32;
467
468 case PIPE_FORMAT_R32_FLOAT:
469 case PIPE_FORMAT_A32_FLOAT:
470 case PIPE_FORMAT_L32_FLOAT:
471 case PIPE_FORMAT_I32_FLOAT:
472 case PIPE_FORMAT_Z32_FLOAT:
473 return V_0280A0_COLOR_32_FLOAT;
474
475 case PIPE_FORMAT_R16G16_FLOAT:
476 case PIPE_FORMAT_L16A16_FLOAT:
477 case PIPE_FORMAT_R16A16_FLOAT:
478 return V_0280A0_COLOR_16_16_FLOAT;
479
480 case PIPE_FORMAT_R16G16_UNORM:
481 case PIPE_FORMAT_R16G16_SNORM:
482 case PIPE_FORMAT_R16G16_UINT:
483 case PIPE_FORMAT_R16G16_SINT:
484 case PIPE_FORMAT_L16A16_UNORM:
485 case PIPE_FORMAT_L16A16_SNORM:
486 case PIPE_FORMAT_L16A16_UINT:
487 case PIPE_FORMAT_L16A16_SINT:
488 case PIPE_FORMAT_R16A16_UNORM:
489 case PIPE_FORMAT_R16A16_SNORM:
490 case PIPE_FORMAT_R16A16_UINT:
491 case PIPE_FORMAT_R16A16_SINT:
492 return V_0280A0_COLOR_16_16;
493
494 case PIPE_FORMAT_R11G11B10_FLOAT:
495 return V_0280A0_COLOR_10_11_11_FLOAT;
496
497 /* 64-bit buffers. */
498 case PIPE_FORMAT_R16G16B16A16_UINT:
499 case PIPE_FORMAT_R16G16B16A16_SINT:
500 case PIPE_FORMAT_R16G16B16A16_UNORM:
501 case PIPE_FORMAT_R16G16B16A16_SNORM:
502 case PIPE_FORMAT_R16G16B16X16_UNORM:
503 case PIPE_FORMAT_R16G16B16X16_SNORM:
504 case PIPE_FORMAT_R16G16B16X16_UINT:
505 case PIPE_FORMAT_R16G16B16X16_SINT:
506 return V_0280A0_COLOR_16_16_16_16;
507
508 case PIPE_FORMAT_R16G16B16A16_FLOAT:
509 case PIPE_FORMAT_R16G16B16X16_FLOAT:
510 return V_0280A0_COLOR_16_16_16_16_FLOAT;
511
512 case PIPE_FORMAT_R32G32_FLOAT:
513 case PIPE_FORMAT_L32A32_FLOAT:
514 case PIPE_FORMAT_R32A32_FLOAT:
515 return V_0280A0_COLOR_32_32_FLOAT;
516
517 case PIPE_FORMAT_R32G32_SINT:
518 case PIPE_FORMAT_R32G32_UINT:
519 case PIPE_FORMAT_L32A32_UINT:
520 case PIPE_FORMAT_L32A32_SINT:
521 return V_0280A0_COLOR_32_32;
522
523 /* 128-bit buffers. */
524 case PIPE_FORMAT_R32G32B32A32_FLOAT:
525 case PIPE_FORMAT_R32G32B32X32_FLOAT:
526 return V_0280A0_COLOR_32_32_32_32_FLOAT;
527 case PIPE_FORMAT_R32G32B32A32_SNORM:
528 case PIPE_FORMAT_R32G32B32A32_UNORM:
529 case PIPE_FORMAT_R32G32B32A32_SINT:
530 case PIPE_FORMAT_R32G32B32A32_UINT:
531 case PIPE_FORMAT_R32G32B32X32_UINT:
532 case PIPE_FORMAT_R32G32B32X32_SINT:
533 return V_0280A0_COLOR_32_32_32_32;
534
535 /* YUV buffers. */
536 case PIPE_FORMAT_UYVY:
537 case PIPE_FORMAT_YUYV:
538 default:
539 return ~0U; /* Unsupported. */
540 }
541 }
542
543 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
544 {
545 if (R600_BIG_ENDIAN) {
546 switch(colorformat) {
547 case V_0280A0_COLOR_4_4:
548 return ENDIAN_NONE;
549
550 /* 8-bit buffers. */
551 case V_0280A0_COLOR_8:
552 return ENDIAN_NONE;
553
554 /* 16-bit buffers. */
555 case V_0280A0_COLOR_5_6_5:
556 case V_0280A0_COLOR_1_5_5_5:
557 case V_0280A0_COLOR_4_4_4_4:
558 case V_0280A0_COLOR_16:
559 case V_0280A0_COLOR_8_8:
560 return ENDIAN_8IN16;
561
562 /* 32-bit buffers. */
563 case V_0280A0_COLOR_8_8_8_8:
564 case V_0280A0_COLOR_2_10_10_10:
565 case V_0280A0_COLOR_8_24:
566 case V_0280A0_COLOR_24_8:
567 case V_0280A0_COLOR_32_FLOAT:
568 case V_0280A0_COLOR_16_16_FLOAT:
569 case V_0280A0_COLOR_16_16:
570 return ENDIAN_8IN32;
571
572 /* 64-bit buffers. */
573 case V_0280A0_COLOR_16_16_16_16:
574 case V_0280A0_COLOR_16_16_16_16_FLOAT:
575 return ENDIAN_8IN16;
576
577 case V_0280A0_COLOR_32_32_FLOAT:
578 case V_0280A0_COLOR_32_32:
579 case V_0280A0_COLOR_X24_8_32_FLOAT:
580 return ENDIAN_8IN32;
581
582 /* 128-bit buffers. */
583 case V_0280A0_COLOR_32_32_32_FLOAT:
584 case V_0280A0_COLOR_32_32_32_32_FLOAT:
585 case V_0280A0_COLOR_32_32_32_32:
586 return ENDIAN_8IN32;
587 default:
588 return ENDIAN_NONE; /* Unsupported. */
589 }
590 } else {
591 return ENDIAN_NONE;
592 }
593 }
594
595 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
596 {
597 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
598 }
599
600 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
601 {
602 return r600_translate_colorformat(format) != ~0U &&
603 r600_translate_colorswap(format) != ~0U;
604 }
605
606 static bool r600_is_zs_format_supported(enum pipe_format format)
607 {
608 return r600_translate_dbformat(format) != ~0U;
609 }
610
611 boolean r600_is_format_supported(struct pipe_screen *screen,
612 enum pipe_format format,
613 enum pipe_texture_target target,
614 unsigned sample_count,
615 unsigned usage)
616 {
617 struct r600_screen *rscreen = (struct r600_screen*)screen;
618 unsigned retval = 0;
619
620 if (target >= PIPE_MAX_TEXTURE_TYPES) {
621 R600_ERR("r600: unsupported texture type %d\n", target);
622 return FALSE;
623 }
624
625 if (!util_format_is_supported(format, usage))
626 return FALSE;
627
628 if (sample_count > 1) {
629 if (!rscreen->has_msaa)
630 return FALSE;
631
632 /* R11G11B10 is broken on R6xx. */
633 if (rscreen->b.chip_class == R600 &&
634 format == PIPE_FORMAT_R11G11B10_FLOAT)
635 return FALSE;
636
637 /* MSAA integer colorbuffers hang. */
638 if (util_format_is_pure_integer(format) &&
639 !util_format_is_depth_or_stencil(format))
640 return FALSE;
641
642 switch (sample_count) {
643 case 2:
644 case 4:
645 case 8:
646 break;
647 default:
648 return FALSE;
649 }
650 }
651
652 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
653 r600_is_sampler_format_supported(screen, format)) {
654 retval |= PIPE_BIND_SAMPLER_VIEW;
655 }
656
657 if ((usage & (PIPE_BIND_RENDER_TARGET |
658 PIPE_BIND_DISPLAY_TARGET |
659 PIPE_BIND_SCANOUT |
660 PIPE_BIND_SHARED)) &&
661 r600_is_colorbuffer_format_supported(format)) {
662 retval |= usage &
663 (PIPE_BIND_RENDER_TARGET |
664 PIPE_BIND_DISPLAY_TARGET |
665 PIPE_BIND_SCANOUT |
666 PIPE_BIND_SHARED);
667 }
668
669 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
670 r600_is_zs_format_supported(format)) {
671 retval |= PIPE_BIND_DEPTH_STENCIL;
672 }
673
674 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
675 r600_is_vertex_format_supported(format)) {
676 retval |= PIPE_BIND_VERTEX_BUFFER;
677 }
678
679 if (usage & PIPE_BIND_TRANSFER_READ)
680 retval |= PIPE_BIND_TRANSFER_READ;
681 if (usage & PIPE_BIND_TRANSFER_WRITE)
682 retval |= PIPE_BIND_TRANSFER_WRITE;
683
684 return retval == usage;
685 }
686
687 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
688 {
689 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
690 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
691 float offset_units = state->offset_units;
692 float offset_scale = state->offset_scale;
693
694 switch (state->zs_format) {
695 case PIPE_FORMAT_Z24X8_UNORM:
696 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
697 offset_units *= 2.0f;
698 break;
699 case PIPE_FORMAT_Z16_UNORM:
700 offset_units *= 4.0f;
701 break;
702 default:;
703 }
704
705 r600_write_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
706 radeon_emit(cs, fui(offset_scale));
707 radeon_emit(cs, fui(offset_units));
708 radeon_emit(cs, fui(offset_scale));
709 radeon_emit(cs, fui(offset_units));
710 }
711
712 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
713 {
714 int j = state->independent_blend_enable ? i : 0;
715
716 unsigned eqRGB = state->rt[j].rgb_func;
717 unsigned srcRGB = state->rt[j].rgb_src_factor;
718 unsigned dstRGB = state->rt[j].rgb_dst_factor;
719
720 unsigned eqA = state->rt[j].alpha_func;
721 unsigned srcA = state->rt[j].alpha_src_factor;
722 unsigned dstA = state->rt[j].alpha_dst_factor;
723 uint32_t bc = 0;
724
725 if (!state->rt[j].blend_enable)
726 return 0;
727
728 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
729 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
730 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
731
732 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
733 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
734 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
735 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
736 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
737 }
738 return bc;
739 }
740
741 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
742 const struct pipe_blend_state *state,
743 int mode)
744 {
745 struct r600_context *rctx = (struct r600_context *)ctx;
746 uint32_t color_control = 0, target_mask = 0;
747 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
748
749 if (!blend) {
750 return NULL;
751 }
752
753 r600_init_command_buffer(&blend->buffer, 20);
754 r600_init_command_buffer(&blend->buffer_no_blend, 20);
755
756 /* R600 does not support per-MRT blends */
757 if (rctx->b.family > CHIP_R600)
758 color_control |= S_028808_PER_MRT_BLEND(1);
759
760 if (state->logicop_enable) {
761 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
762 } else {
763 color_control |= (0xcc << 16);
764 }
765 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
766 if (state->independent_blend_enable) {
767 for (int i = 0; i < 8; i++) {
768 if (state->rt[i].blend_enable) {
769 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
770 }
771 target_mask |= (state->rt[i].colormask << (4 * i));
772 }
773 } else {
774 for (int i = 0; i < 8; i++) {
775 if (state->rt[0].blend_enable) {
776 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
777 }
778 target_mask |= (state->rt[0].colormask << (4 * i));
779 }
780 }
781
782 if (target_mask)
783 color_control |= S_028808_SPECIAL_OP(mode);
784 else
785 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
786
787 /* only MRT0 has dual src blend */
788 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
789 blend->cb_target_mask = target_mask;
790 blend->cb_color_control = color_control;
791 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
792 blend->alpha_to_one = state->alpha_to_one;
793
794 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
795 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
796 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
797 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
798 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
799 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
800
801 /* Copy over the registers set so far into buffer_no_blend. */
802 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
803 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
804
805 /* Only add blend registers if blending is enabled. */
806 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
807 return blend;
808 }
809
810 /* The first R600 does not support per-MRT blends */
811 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
812 r600_get_blend_control(state, 0));
813
814 if (rctx->b.family > CHIP_R600) {
815 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
816 for (int i = 0; i < 8; i++) {
817 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
818 }
819 }
820 return blend;
821 }
822
823 static void *r600_create_blend_state(struct pipe_context *ctx,
824 const struct pipe_blend_state *state)
825 {
826 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
827 }
828
829 static void *r600_create_dsa_state(struct pipe_context *ctx,
830 const struct pipe_depth_stencil_alpha_state *state)
831 {
832 unsigned db_depth_control, alpha_test_control, alpha_ref;
833 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
834
835 if (dsa == NULL) {
836 return NULL;
837 }
838
839 r600_init_command_buffer(&dsa->buffer, 3);
840
841 dsa->valuemask[0] = state->stencil[0].valuemask;
842 dsa->valuemask[1] = state->stencil[1].valuemask;
843 dsa->writemask[0] = state->stencil[0].writemask;
844 dsa->writemask[1] = state->stencil[1].writemask;
845 dsa->zwritemask = state->depth.writemask;
846
847 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
848 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
849 S_028800_ZFUNC(state->depth.func);
850
851 /* stencil */
852 if (state->stencil[0].enabled) {
853 db_depth_control |= S_028800_STENCIL_ENABLE(1);
854 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
855 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
856 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
857 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
858
859 if (state->stencil[1].enabled) {
860 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
861 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
862 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
863 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
864 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
865 }
866 }
867
868 /* alpha */
869 alpha_test_control = 0;
870 alpha_ref = 0;
871 if (state->alpha.enabled) {
872 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
873 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
874 alpha_ref = fui(state->alpha.ref_value);
875 }
876 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
877 dsa->alpha_ref = alpha_ref;
878
879 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
880 return dsa;
881 }
882
883 static void *r600_create_rs_state(struct pipe_context *ctx,
884 const struct pipe_rasterizer_state *state)
885 {
886 struct r600_context *rctx = (struct r600_context *)ctx;
887 unsigned tmp, sc_mode_cntl, spi_interp;
888 float psize_min, psize_max;
889 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
890
891 if (rs == NULL) {
892 return NULL;
893 }
894
895 r600_init_command_buffer(&rs->buffer, 30);
896
897 rs->flatshade = state->flatshade;
898 rs->sprite_coord_enable = state->sprite_coord_enable;
899 rs->two_side = state->light_twoside;
900 rs->clip_plane_enable = state->clip_plane_enable;
901 rs->pa_sc_line_stipple = state->line_stipple_enable ?
902 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
903 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
904 rs->pa_cl_clip_cntl =
905 S_028810_PS_UCP_MODE(3) |
906 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
907 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
908 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
909 rs->multisample_enable = state->multisample;
910
911 /* offset */
912 rs->offset_units = state->offset_units;
913 rs->offset_scale = state->offset_scale * 12.0f;
914 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
915
916 if (state->point_size_per_vertex) {
917 psize_min = util_get_min_point_size(state);
918 psize_max = 8192;
919 } else {
920 /* Force the point size to be as if the vertex output was disabled. */
921 psize_min = state->point_size;
922 psize_max = state->point_size;
923 }
924
925 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
926 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
927 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
928 if (rctx->b.chip_class >= R700) {
929 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
930 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
931 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
932 } else {
933 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
934 rs->scissor_enable = state->scissor;
935 }
936
937 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
938 if (state->sprite_coord_enable) {
939 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
940 S_0286D4_PNT_SPRITE_OVRD_X(2) |
941 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
942 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
943 S_0286D4_PNT_SPRITE_OVRD_W(1);
944 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
945 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
946 }
947 }
948
949 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
950 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
951 tmp = r600_pack_float_12p4(state->point_size/2);
952 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
953 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
954 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
955 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
956 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
957 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
958 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
959
960 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
961 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
962 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
963 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
964 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
965 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
966 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
967 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
968 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
969 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
970 S_028814_FACE(!state->front_ccw) |
971 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
972 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
973 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
974 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
975 state->fill_back != PIPE_POLYGON_MODE_FILL) |
976 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
977 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
978 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
979 return rs;
980 }
981
982 static void *r600_create_sampler_state(struct pipe_context *ctx,
983 const struct pipe_sampler_state *state)
984 {
985 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
986 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
987
988 if (ss == NULL) {
989 return NULL;
990 }
991
992 ss->seamless_cube_map = state->seamless_cube_map;
993 ss->border_color_use = sampler_state_needs_border_color(state);
994
995 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
996 ss->tex_sampler_words[0] =
997 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
998 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
999 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1000 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
1001 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
1002 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1003 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
1004 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1005 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
1006 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
1007 ss->tex_sampler_words[1] =
1008 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1009 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1010 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
1011 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
1012 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
1013
1014 if (ss->border_color_use) {
1015 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
1016 }
1017 return ss;
1018 }
1019
1020 static struct pipe_sampler_view *
1021 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
1022 unsigned width0, unsigned height0)
1023
1024 {
1025 struct pipe_context *ctx = view->base.context;
1026 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
1027 uint64_t va;
1028 int stride = util_format_get_blocksize(view->base.format);
1029 unsigned format, num_format, format_comp, endian;
1030 unsigned offset = view->base.u.buf.first_element * stride;
1031 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
1032
1033 r600_vertex_data_type(view->base.format,
1034 &format, &num_format, &format_comp,
1035 &endian);
1036
1037 va = r600_resource_va(ctx->screen, view->base.texture) + offset;
1038 view->tex_resource = &tmp->resource;
1039
1040 view->skip_mip_address_reloc = true;
1041 view->tex_resource_words[0] = va;
1042 view->tex_resource_words[1] = size - 1;
1043 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(va >> 32UL) |
1044 S_038008_STRIDE(stride) |
1045 S_038008_DATA_FORMAT(format) |
1046 S_038008_NUM_FORMAT_ALL(num_format) |
1047 S_038008_FORMAT_COMP_ALL(format_comp) |
1048 S_038008_SRF_MODE_ALL(1) |
1049 S_038008_ENDIAN_SWAP(endian);
1050 view->tex_resource_words[3] = 0;
1051 /*
1052 * in theory dword 4 is for number of elements, for use with resinfo,
1053 * but it seems to utterly fail to work, the amd gpu shader analyser
1054 * uses a const buffer to store the element sizes for buffer txq
1055 */
1056 view->tex_resource_words[4] = 0;
1057 view->tex_resource_words[5] = 0;
1058 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
1059 return &view->base;
1060 }
1061
1062 struct pipe_sampler_view *
1063 r600_create_sampler_view_custom(struct pipe_context *ctx,
1064 struct pipe_resource *texture,
1065 const struct pipe_sampler_view *state,
1066 unsigned width_first_level, unsigned height_first_level)
1067 {
1068 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1069 struct r600_texture *tmp = (struct r600_texture*)texture;
1070 unsigned format, endian;
1071 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1072 unsigned char swizzle[4], array_mode = 0;
1073 unsigned width, height, depth, offset_level, last_level;
1074
1075 if (view == NULL)
1076 return NULL;
1077
1078 /* initialize base object */
1079 view->base = *state;
1080 view->base.texture = NULL;
1081 pipe_reference(NULL, &texture->reference);
1082 view->base.texture = texture;
1083 view->base.reference.count = 1;
1084 view->base.context = ctx;
1085
1086 if (texture->target == PIPE_BUFFER)
1087 return texture_buffer_sampler_view(view, texture->width0, 1);
1088
1089 swizzle[0] = state->swizzle_r;
1090 swizzle[1] = state->swizzle_g;
1091 swizzle[2] = state->swizzle_b;
1092 swizzle[3] = state->swizzle_a;
1093
1094 format = r600_translate_texformat(ctx->screen, state->format,
1095 swizzle,
1096 &word4, &yuv_format);
1097 assert(format != ~0);
1098 if (format == ~0) {
1099 FREE(view);
1100 return NULL;
1101 }
1102
1103 if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) {
1104 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1105 FREE(view);
1106 return NULL;
1107 }
1108 tmp = tmp->flushed_depth_texture;
1109 }
1110
1111 endian = r600_colorformat_endian_swap(format);
1112
1113 offset_level = state->u.tex.first_level;
1114 last_level = state->u.tex.last_level - offset_level;
1115 width = width_first_level;
1116 height = height_first_level;
1117 depth = u_minify(texture->depth0, offset_level);
1118 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1119
1120 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1121 height = 1;
1122 depth = texture->array_size;
1123 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1124 depth = texture->array_size;
1125 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
1126 depth = texture->array_size / 6;
1127 switch (tmp->surface.level[offset_level].mode) {
1128 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1129 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1130 break;
1131 case RADEON_SURF_MODE_1D:
1132 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1133 break;
1134 case RADEON_SURF_MODE_2D:
1135 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1136 break;
1137 case RADEON_SURF_MODE_LINEAR:
1138 default:
1139 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1140 break;
1141 }
1142
1143 view->tex_resource = &tmp->resource;
1144 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1145 S_038000_TILE_MODE(array_mode) |
1146 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
1147 S_038000_PITCH((pitch / 8) - 1) |
1148 S_038000_TEX_WIDTH(width - 1));
1149 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
1150 S_038004_TEX_DEPTH(depth - 1) |
1151 S_038004_DATA_FORMAT(format));
1152 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
1153 if (offset_level >= tmp->surface.last_level) {
1154 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
1155 } else {
1156 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1157 }
1158 view->tex_resource_words[4] = (word4 |
1159 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1160 S_038010_REQUEST_SIZE(1) |
1161 S_038010_ENDIAN_SWAP(endian) |
1162 S_038010_BASE_LEVEL(0));
1163 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1164 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1165 if (texture->nr_samples > 1) {
1166 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1167 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
1168 } else {
1169 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
1170 }
1171 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1172 S_038018_MAX_ANISO(4 /* max 16 samples */));
1173 return &view->base;
1174 }
1175
1176 static struct pipe_sampler_view *
1177 r600_create_sampler_view(struct pipe_context *ctx,
1178 struct pipe_resource *tex,
1179 const struct pipe_sampler_view *state)
1180 {
1181 return r600_create_sampler_view_custom(ctx, tex, state,
1182 u_minify(tex->width0, state->u.tex.first_level),
1183 u_minify(tex->height0, state->u.tex.first_level));
1184 }
1185
1186 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1187 {
1188 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1189 struct pipe_clip_state *state = &rctx->clip_state.state;
1190
1191 r600_write_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
1192 radeon_emit_array(cs, (unsigned*)state, 6*4);
1193 }
1194
1195 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1196 const struct pipe_poly_stipple *state)
1197 {
1198 }
1199
1200 static void r600_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
1201 {
1202 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1203 struct pipe_scissor_state *state = &rctx->scissor.scissor;
1204
1205 if (rctx->b.chip_class != R600 || rctx->scissor.enable) {
1206 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1207 radeon_emit(cs, S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) |
1208 S_028240_WINDOW_OFFSET_DISABLE(1));
1209 radeon_emit(cs, S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy));
1210 } else {
1211 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
1212 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1213 S_028240_WINDOW_OFFSET_DISABLE(1));
1214 radeon_emit(cs, S_028244_BR_X(8192) | S_028244_BR_Y(8192));
1215 }
1216 }
1217
1218 static void r600_set_scissor_states(struct pipe_context *ctx,
1219 unsigned start_slot,
1220 unsigned num_scissors,
1221 const struct pipe_scissor_state *state)
1222 {
1223 struct r600_context *rctx = (struct r600_context *)ctx;
1224
1225 rctx->scissor.scissor = *state;
1226
1227 if (rctx->b.chip_class == R600 && !rctx->scissor.enable)
1228 return;
1229
1230 rctx->scissor.atom.dirty = true;
1231 }
1232
1233 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
1234 unsigned size, unsigned alignment)
1235 {
1236 struct pipe_resource buffer;
1237
1238 memset(&buffer, 0, sizeof buffer);
1239 buffer.target = PIPE_BUFFER;
1240 buffer.format = PIPE_FORMAT_R8_UNORM;
1241 buffer.bind = PIPE_BIND_CUSTOM;
1242 buffer.usage = PIPE_USAGE_STATIC;
1243 buffer.flags = 0;
1244 buffer.width0 = size;
1245 buffer.height0 = 1;
1246 buffer.depth0 = 1;
1247 buffer.array_size = 1;
1248
1249 return (struct r600_resource*)
1250 r600_buffer_create(&rscreen->b.b, &buffer, alignment);
1251 }
1252
1253 static void r600_init_color_surface(struct r600_context *rctx,
1254 struct r600_surface *surf,
1255 bool force_cmask_fmask)
1256 {
1257 struct r600_screen *rscreen = rctx->screen;
1258 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1259 unsigned level = surf->base.u.tex.level;
1260 unsigned pitch, slice;
1261 unsigned color_info;
1262 unsigned format, swap, ntype, endian;
1263 unsigned offset;
1264 const struct util_format_description *desc;
1265 int i;
1266 bool blend_bypass = 0, blend_clamp = 1;
1267
1268 if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
1269 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
1270 rtex = rtex->flushed_depth_texture;
1271 assert(rtex);
1272 }
1273
1274 offset = rtex->surface.level[level].offset;
1275 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1276 offset += rtex->surface.level[level].slice_size *
1277 surf->base.u.tex.first_layer;
1278 }
1279 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1280 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1281 if (slice) {
1282 slice = slice - 1;
1283 }
1284 color_info = 0;
1285 switch (rtex->surface.level[level].mode) {
1286 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1287 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1288 break;
1289 case RADEON_SURF_MODE_1D:
1290 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1291 break;
1292 case RADEON_SURF_MODE_2D:
1293 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1294 break;
1295 case RADEON_SURF_MODE_LINEAR:
1296 default:
1297 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1298 break;
1299 }
1300
1301 desc = util_format_description(surf->base.format);
1302
1303 for (i = 0; i < 4; i++) {
1304 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1305 break;
1306 }
1307 }
1308
1309 ntype = V_0280A0_NUMBER_UNORM;
1310 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1311 ntype = V_0280A0_NUMBER_SRGB;
1312 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1313 if (desc->channel[i].normalized)
1314 ntype = V_0280A0_NUMBER_SNORM;
1315 else if (desc->channel[i].pure_integer)
1316 ntype = V_0280A0_NUMBER_SINT;
1317 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1318 if (desc->channel[i].normalized)
1319 ntype = V_0280A0_NUMBER_UNORM;
1320 else if (desc->channel[i].pure_integer)
1321 ntype = V_0280A0_NUMBER_UINT;
1322 }
1323
1324 format = r600_translate_colorformat(surf->base.format);
1325 assert(format != ~0);
1326
1327 swap = r600_translate_colorswap(surf->base.format);
1328 assert(swap != ~0);
1329
1330 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1331 endian = ENDIAN_NONE;
1332 } else {
1333 endian = r600_colorformat_endian_swap(format);
1334 }
1335
1336 /* set blend bypass according to docs if SINT/UINT or
1337 8/24 COLOR variants */
1338 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1339 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1340 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1341 blend_clamp = 0;
1342 blend_bypass = 1;
1343 }
1344
1345 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
1346
1347 color_info |= S_0280A0_FORMAT(format) |
1348 S_0280A0_COMP_SWAP(swap) |
1349 S_0280A0_BLEND_BYPASS(blend_bypass) |
1350 S_0280A0_BLEND_CLAMP(blend_clamp) |
1351 S_0280A0_NUMBER_TYPE(ntype) |
1352 S_0280A0_ENDIAN(endian);
1353
1354 /* EXPORT_NORM is an optimzation that can be enabled for better
1355 * performance in certain cases
1356 */
1357 if (rctx->b.chip_class == R600) {
1358 /* EXPORT_NORM can be enabled if:
1359 * - 11-bit or smaller UNORM/SNORM/SRGB
1360 * - BLEND_CLAMP is enabled
1361 * - BLEND_FLOAT32 is disabled
1362 */
1363 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1364 (desc->channel[i].size < 12 &&
1365 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1366 ntype != V_0280A0_NUMBER_UINT &&
1367 ntype != V_0280A0_NUMBER_SINT) &&
1368 G_0280A0_BLEND_CLAMP(color_info) &&
1369 !G_0280A0_BLEND_FLOAT32(color_info)) {
1370 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1371 surf->export_16bpc = true;
1372 }
1373 } else {
1374 /* EXPORT_NORM can be enabled if:
1375 * - 11-bit or smaller UNORM/SNORM/SRGB
1376 * - 16-bit or smaller FLOAT
1377 */
1378 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1379 ((desc->channel[i].size < 12 &&
1380 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1381 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1382 (desc->channel[i].size < 17 &&
1383 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1384 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1385 surf->export_16bpc = true;
1386 }
1387 }
1388
1389 /* These might not always be initialized to zero. */
1390 surf->cb_color_base = offset >> 8;
1391 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
1392 S_028060_SLICE_TILE_MAX(slice);
1393 surf->cb_color_fmask = surf->cb_color_base;
1394 surf->cb_color_cmask = surf->cb_color_base;
1395 surf->cb_color_mask = 0;
1396
1397 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1398 &rtex->resource.b.b);
1399 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1400 &rtex->resource.b.b);
1401
1402 if (rtex->cmask.size) {
1403 surf->cb_color_cmask = rtex->cmask.offset >> 8;
1404 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
1405
1406 if (rtex->fmask.size) {
1407 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1408 surf->cb_color_fmask = rtex->fmask.offset >> 8;
1409 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
1410 } else { /* cmask only */
1411 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
1412 }
1413 } else if (force_cmask_fmask) {
1414 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1415 *
1416 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1417 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1418 * because it's not an MSAA buffer.
1419 */
1420 struct r600_cmask_info cmask;
1421 struct r600_fmask_info fmask;
1422
1423 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
1424 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
1425
1426 /* CMASK. */
1427 if (!rctx->dummy_cmask ||
1428 rctx->dummy_cmask->buf->size < cmask.size ||
1429 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1430 struct pipe_transfer *transfer;
1431 void *ptr;
1432
1433 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1434 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1435
1436 /* Set the contents to 0xCC. */
1437 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1438 memset(ptr, 0xCC, cmask.size);
1439 pipe_buffer_unmap(&rctx->b.b, transfer);
1440 }
1441 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1442 &rctx->dummy_cmask->b.b);
1443
1444 /* FMASK. */
1445 if (!rctx->dummy_fmask ||
1446 rctx->dummy_fmask->buf->size < fmask.size ||
1447 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1448 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1449 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1450
1451 }
1452 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1453 &rctx->dummy_fmask->b.b);
1454
1455 /* Init the registers. */
1456 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1457 surf->cb_color_cmask = 0;
1458 surf->cb_color_fmask = 0;
1459 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1460 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1461 }
1462
1463 surf->cb_color_info = color_info;
1464
1465 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1466 surf->cb_color_view = 0;
1467 } else {
1468 surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
1469 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
1470 }
1471
1472 surf->color_initialized = true;
1473 }
1474
1475 static void r600_init_depth_surface(struct r600_context *rctx,
1476 struct r600_surface *surf)
1477 {
1478 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1479 unsigned level, pitch, slice, format, offset, array_mode;
1480
1481 level = surf->base.u.tex.level;
1482 offset = rtex->surface.level[level].offset;
1483 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1484 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1485 if (slice) {
1486 slice = slice - 1;
1487 }
1488 switch (rtex->surface.level[level].mode) {
1489 case RADEON_SURF_MODE_2D:
1490 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1491 break;
1492 case RADEON_SURF_MODE_1D:
1493 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1494 case RADEON_SURF_MODE_LINEAR:
1495 default:
1496 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1497 break;
1498 }
1499
1500 format = r600_translate_dbformat(surf->base.format);
1501 assert(format != ~0);
1502
1503 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1504 surf->db_depth_base = offset >> 8;
1505 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1506 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1507 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1508 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1509
1510 switch (surf->base.format) {
1511 case PIPE_FORMAT_Z24X8_UNORM:
1512 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1513 surf->pa_su_poly_offset_db_fmt_cntl =
1514 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1515 break;
1516 case PIPE_FORMAT_Z32_FLOAT:
1517 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1518 surf->pa_su_poly_offset_db_fmt_cntl =
1519 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1520 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1521 break;
1522 case PIPE_FORMAT_Z16_UNORM:
1523 surf->pa_su_poly_offset_db_fmt_cntl =
1524 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1525 break;
1526 default:;
1527 }
1528
1529 surf->htile_enabled = 0;
1530 /* use htile only for first level */
1531 if (rtex->htile && !level) {
1532 uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile->b.b);
1533 surf->htile_enabled = 1;
1534 surf->db_htile_data_base = va >> 8;
1535 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1536 S_028D24_HTILE_HEIGHT(1) |
1537 S_028D24_FULL_CACHE(1) |
1538 S_028D24_LINEAR(1);
1539 /* preload is not working properly on r6xx/r7xx */
1540 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1541 }
1542
1543 surf->depth_initialized = true;
1544 }
1545
1546 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1547 const struct pipe_framebuffer_state *state)
1548 {
1549 struct r600_context *rctx = (struct r600_context *)ctx;
1550 struct r600_surface *surf;
1551 struct r600_texture *rtex;
1552 unsigned i;
1553
1554 if (rctx->framebuffer.state.nr_cbufs) {
1555 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1556 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB;
1557
1558 if (rctx->b.chip_class >= R700 &&
1559 rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
1560 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
1561 }
1562 }
1563 if (rctx->framebuffer.state.zsbuf) {
1564 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1565 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1566
1567 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1568 if (rctx->b.chip_class >= R700 && rtex->htile) {
1569 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1570 }
1571 }
1572
1573 /* Set the new state. */
1574 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1575
1576 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1577 rctx->framebuffer.cb0_is_integer = state->nr_cbufs &&
1578 util_format_is_pure_integer(state->cbufs[0]->format);
1579 rctx->framebuffer.compressed_cb_mask = 0;
1580 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1581 state->cbufs[0]->texture->nr_samples > 1 &&
1582 state->cbufs[1]->texture->nr_samples <= 1;
1583
1584 if (state->nr_cbufs)
1585 rctx->framebuffer.nr_samples = state->cbufs[0]->texture->nr_samples;
1586 else if (state->zsbuf)
1587 rctx->framebuffer.nr_samples = state->zsbuf->texture->nr_samples;
1588 else
1589 rctx->framebuffer.nr_samples = 0;
1590
1591 /* Colorbuffers. */
1592 for (i = 0; i < state->nr_cbufs; i++) {
1593 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1594 bool force_cmask_fmask = rctx->b.chip_class == R600 &&
1595 rctx->framebuffer.is_msaa_resolve &&
1596 i == 1;
1597
1598 surf = (struct r600_surface*)state->cbufs[i];
1599 rtex = (struct r600_texture*)surf->base.texture;
1600 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1601
1602 if (!surf->color_initialized || force_cmask_fmask) {
1603 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1604 if (force_cmask_fmask) {
1605 /* re-initialize later without compression */
1606 surf->color_initialized = false;
1607 }
1608 }
1609
1610 if (!surf->export_16bpc) {
1611 rctx->framebuffer.export_16bpc = false;
1612 }
1613
1614 if (rtex->fmask.size && rtex->cmask.size) {
1615 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1616 }
1617 }
1618
1619 /* Update alpha-test state dependencies.
1620 * Alpha-test is done on the first colorbuffer only. */
1621 if (state->nr_cbufs) {
1622 surf = (struct r600_surface*)state->cbufs[0];
1623 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1624 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1625 rctx->alphatest_state.atom.dirty = true;
1626 }
1627 }
1628
1629 /* ZS buffer. */
1630 if (state->zsbuf) {
1631 surf = (struct r600_surface*)state->zsbuf;
1632
1633 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1634
1635 if (!surf->depth_initialized) {
1636 r600_init_depth_surface(rctx, surf);
1637 }
1638
1639 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1640 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1641 rctx->poly_offset_state.atom.dirty = true;
1642 }
1643
1644 if (rctx->db_state.rsurf != surf) {
1645 rctx->db_state.rsurf = surf;
1646 rctx->db_state.atom.dirty = true;
1647 rctx->db_misc_state.atom.dirty = true;
1648 }
1649 } else if (rctx->db_state.rsurf) {
1650 rctx->db_state.rsurf = NULL;
1651 rctx->db_state.atom.dirty = true;
1652 rctx->db_misc_state.atom.dirty = true;
1653 }
1654
1655 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1656 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1657 rctx->cb_misc_state.atom.dirty = true;
1658 }
1659
1660 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1661 rctx->alphatest_state.bypass = false;
1662 rctx->alphatest_state.atom.dirty = true;
1663 }
1664
1665 r600_update_db_shader_control(rctx);
1666
1667 /* Calculate the CS size. */
1668 rctx->framebuffer.atom.num_dw =
1669 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1670
1671 if (rctx->framebuffer.state.nr_cbufs) {
1672 rctx->framebuffer.atom.num_dw += 6 * (2 + rctx->framebuffer.state.nr_cbufs);
1673 rctx->framebuffer.atom.num_dw += 6 * rctx->framebuffer.state.nr_cbufs; /* relocs */
1674
1675 }
1676 if (rctx->framebuffer.state.zsbuf) {
1677 rctx->framebuffer.atom.num_dw += 18;
1678 } else if (rctx->screen->b.info.drm_minor >= 18) {
1679 rctx->framebuffer.atom.num_dw += 3;
1680 }
1681 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1682 rctx->framebuffer.atom.num_dw += 2;
1683 }
1684
1685 rctx->framebuffer.atom.dirty = true;
1686 }
1687
1688 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1689 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1690 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1691 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1692 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1693
1694
1695 static uint32_t sample_locs_2x[] = {
1696 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1697 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1698 };
1699 static unsigned max_dist_2x = 4;
1700
1701 static uint32_t sample_locs_4x[] = {
1702 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1703 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1704 };
1705 static unsigned max_dist_4x = 6;
1706 static uint32_t sample_locs_8x[] = {
1707 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1708 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1709 };
1710 static unsigned max_dist_8x = 7;
1711
1712 static void r600_get_sample_position(struct pipe_context *ctx,
1713 unsigned sample_count,
1714 unsigned sample_index,
1715 float *out_value)
1716 {
1717 int offset, index;
1718 struct {
1719 int idx:4;
1720 } val;
1721 switch (sample_count) {
1722 case 1:
1723 default:
1724 out_value[0] = out_value[1] = 0.5;
1725 break;
1726 case 2:
1727 offset = 4 * (sample_index * 2);
1728 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1729 out_value[0] = (float)(val.idx + 8) / 16.0f;
1730 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1731 out_value[1] = (float)(val.idx + 8) / 16.0f;
1732 break;
1733 case 4:
1734 offset = 4 * (sample_index * 2);
1735 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1736 out_value[0] = (float)(val.idx + 8) / 16.0f;
1737 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1738 out_value[1] = (float)(val.idx + 8) / 16.0f;
1739 break;
1740 case 8:
1741 offset = 4 * (sample_index % 4 * 2);
1742 index = (sample_index / 4);
1743 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1744 out_value[0] = (float)(val.idx + 8) / 16.0f;
1745 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1746 out_value[1] = (float)(val.idx + 8) / 16.0f;
1747 break;
1748 }
1749 }
1750
1751 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1752 {
1753 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1754 unsigned max_dist = 0;
1755
1756 if (rctx->b.family == CHIP_R600) {
1757 switch (nr_samples) {
1758 default:
1759 nr_samples = 0;
1760 break;
1761 case 2:
1762 r600_write_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1763 max_dist = max_dist_2x;
1764 break;
1765 case 4:
1766 r600_write_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1767 max_dist = max_dist_4x;
1768 break;
1769 case 8:
1770 r600_write_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1771 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1772 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1773 max_dist = max_dist_8x;
1774 break;
1775 }
1776 } else {
1777 switch (nr_samples) {
1778 default:
1779 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1780 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1781 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1782 nr_samples = 0;
1783 break;
1784 case 2:
1785 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1786 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1787 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1788 max_dist = max_dist_2x;
1789 break;
1790 case 4:
1791 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1792 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1793 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1794 max_dist = max_dist_4x;
1795 break;
1796 case 8:
1797 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1798 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1799 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1800 max_dist = max_dist_8x;
1801 break;
1802 }
1803 }
1804
1805 if (nr_samples > 1) {
1806 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1807 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1808 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1809 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1810 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1811 } else {
1812 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1813 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1814 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1815 }
1816 }
1817
1818 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1819 {
1820 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1821 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1822 unsigned nr_cbufs = state->nr_cbufs;
1823 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1824 unsigned i, sbu = 0;
1825
1826 /* Colorbuffers. */
1827 r600_write_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1828 for (i = 0; i < nr_cbufs; i++) {
1829 radeon_emit(cs, cb[i]->cb_color_info);
1830 }
1831 /* set CB_COLOR1_INFO for possible dual-src blending */
1832 if (i == 1) {
1833 radeon_emit(cs, cb[0]->cb_color_info);
1834 i++;
1835 }
1836 for (; i < 8; i++) {
1837 radeon_emit(cs, 0);
1838 }
1839
1840 if (nr_cbufs) {
1841 /* COLOR_BASE */
1842 r600_write_context_reg_seq(cs, R_028040_CB_COLOR0_BASE, nr_cbufs);
1843 for (i = 0; i < nr_cbufs; i++) {
1844 radeon_emit(cs, cb[i]->cb_color_base);
1845 }
1846
1847 /* relocations */
1848 for (i = 0; i < nr_cbufs; i++) {
1849 unsigned reloc = r600_context_bo_reloc(&rctx->b,
1850 &rctx->b.rings.gfx,
1851 (struct r600_resource*)cb[i]->base.texture,
1852 RADEON_USAGE_READWRITE);
1853 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1854 radeon_emit(cs, reloc);
1855 }
1856
1857 r600_write_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1858 for (i = 0; i < nr_cbufs; i++) {
1859 radeon_emit(cs, cb[i]->cb_color_size);
1860 }
1861
1862 r600_write_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1863 for (i = 0; i < nr_cbufs; i++) {
1864 radeon_emit(cs, cb[i]->cb_color_view);
1865 }
1866
1867 r600_write_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1868 for (i = 0; i < nr_cbufs; i++) {
1869 radeon_emit(cs, cb[i]->cb_color_mask);
1870 }
1871
1872 /* FMASK. */
1873 r600_write_context_reg_seq(cs, R_0280E0_CB_COLOR0_FRAG, nr_cbufs);
1874 for (i = 0; i < nr_cbufs; i++) {
1875 radeon_emit(cs, cb[i]->cb_color_fmask);
1876 }
1877 /* relocations */
1878 for (i = 0; i < nr_cbufs; i++) {
1879 unsigned reloc = r600_context_bo_reloc(&rctx->b,
1880 &rctx->b.rings.gfx,
1881 cb[i]->cb_buffer_fmask,
1882 RADEON_USAGE_READWRITE);
1883 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1884 radeon_emit(cs, reloc);
1885 }
1886
1887 /* CMASK. */
1888 r600_write_context_reg_seq(cs, R_0280C0_CB_COLOR0_TILE, nr_cbufs);
1889 for (i = 0; i < nr_cbufs; i++) {
1890 radeon_emit(cs, cb[i]->cb_color_cmask);
1891 }
1892 /* relocations */
1893 for (i = 0; i < nr_cbufs; i++) {
1894 unsigned reloc = r600_context_bo_reloc(&rctx->b,
1895 &rctx->b.rings.gfx,
1896 cb[i]->cb_buffer_cmask,
1897 RADEON_USAGE_READWRITE);
1898 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1899 radeon_emit(cs, reloc);
1900 }
1901
1902 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1903 }
1904
1905 /* SURFACE_BASE_UPDATE */
1906 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1907 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1908 radeon_emit(cs, sbu);
1909 sbu = 0;
1910 }
1911
1912 /* Zbuffer. */
1913 if (state->zsbuf) {
1914 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1915 unsigned reloc = r600_context_bo_reloc(&rctx->b,
1916 &rctx->b.rings.gfx,
1917 (struct r600_resource*)state->zsbuf->texture,
1918 RADEON_USAGE_READWRITE);
1919
1920 r600_write_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1921 surf->pa_su_poly_offset_db_fmt_cntl);
1922
1923 r600_write_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1924 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1925 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1926 r600_write_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1927 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1928 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1929
1930 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1931 radeon_emit(cs, reloc);
1932
1933 r600_write_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1934
1935 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1936 } else if (rctx->screen->b.info.drm_minor >= 18) {
1937 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1938 * Older kernels are out of luck. */
1939 r600_write_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1940 }
1941
1942 /* SURFACE_BASE_UPDATE */
1943 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1944 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1945 radeon_emit(cs, sbu);
1946 sbu = 0;
1947 }
1948
1949 /* Framebuffer dimensions. */
1950 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1951 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1952 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1953 radeon_emit(cs, S_028244_BR_X(state->width) |
1954 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1955
1956 if (rctx->framebuffer.is_msaa_resolve) {
1957 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1958 } else {
1959 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1960 * will assure that the alpha-test will work even if there is
1961 * no colorbuffer bound. */
1962 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1963 (1ull << MAX2(nr_cbufs, 1)) - 1);
1964 }
1965
1966 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1967 }
1968
1969 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1970 {
1971 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1972 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1973
1974 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1975 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1976 if (rctx->b.chip_class == R600) {
1977 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1978 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1979 } else {
1980 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1981 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1982 }
1983 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1984 } else {
1985 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1986 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1987 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1988
1989 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1990 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1991 /* Always enable the first color output to make sure alpha-test works even without one. */
1992 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1993 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1994 a->cb_color_control |
1995 S_028808_MULTIWRITE_ENABLE(multiwrite));
1996 }
1997 }
1998
1999 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
2000 {
2001 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2002 struct r600_db_state *a = (struct r600_db_state*)atom;
2003
2004 if (a->rsurf && a->rsurf->htile_enabled) {
2005 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
2006 unsigned reloc_idx;
2007
2008 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear));
2009 r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
2010 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
2011 reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile, RADEON_USAGE_READWRITE);
2012 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
2013 cs->buf[cs->cdw++] = reloc_idx;
2014 } else {
2015 r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
2016 }
2017 }
2018
2019 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2020 {
2021 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2022 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
2023 unsigned db_render_control = 0;
2024 unsigned db_render_override =
2025 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
2026 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
2027
2028 if (a->occlusion_query_enabled) {
2029 if (rctx->b.chip_class >= R700) {
2030 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
2031 }
2032 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
2033 }
2034 if (rctx->db_state.rsurf && rctx->db_state.rsurf->htile_enabled) {
2035 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
2036 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
2037 /* This is to fix a lockup when hyperz and alpha test are enabled at
2038 * the same time somehow GPU get confuse on which order to pick for
2039 * z test
2040 */
2041 if (rctx->alphatest_state.sx_alpha_test_control) {
2042 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
2043 }
2044 } else {
2045 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
2046 }
2047 if (a->flush_depthstencil_through_cb) {
2048 assert(a->copy_depth || a->copy_stencil);
2049
2050 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
2051 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
2052 S_028D0C_COPY_CENTROID(1) |
2053 S_028D0C_COPY_SAMPLE(a->copy_sample);
2054 } else if (a->flush_depthstencil_in_place) {
2055 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(1) |
2056 S_028D0C_STENCIL_COMPRESS_DISABLE(1);
2057 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
2058 }
2059 if (a->htile_clear) {
2060 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
2061 }
2062
2063 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
2064 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
2065 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
2066 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
2067 }
2068
2069 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
2070 {
2071 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2072 struct r600_config_state *a = (struct r600_config_state*)atom;
2073
2074 r600_write_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
2075 }
2076
2077 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
2078 {
2079 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2080 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
2081
2082 while (dirty_mask) {
2083 struct pipe_vertex_buffer *vb;
2084 struct r600_resource *rbuffer;
2085 unsigned offset;
2086 unsigned buffer_index = u_bit_scan(&dirty_mask);
2087
2088 vb = &rctx->vertex_buffer_state.vb[buffer_index];
2089 rbuffer = (struct r600_resource*)vb->buffer;
2090 assert(rbuffer);
2091
2092 offset = vb->buffer_offset;
2093
2094 /* fetch resources start at index 320 */
2095 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
2096 radeon_emit(cs, (320 + buffer_index) * 7);
2097 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
2098 radeon_emit(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
2099 radeon_emit(cs, /* RESOURCEi_WORD2 */
2100 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
2101 S_038008_STRIDE(vb->stride));
2102 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
2103 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2104 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2105 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
2106
2107 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2108 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ));
2109 }
2110 }
2111
2112 static void r600_emit_constant_buffers(struct r600_context *rctx,
2113 struct r600_constbuf_state *state,
2114 unsigned buffer_id_base,
2115 unsigned reg_alu_constbuf_size,
2116 unsigned reg_alu_const_cache)
2117 {
2118 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2119 uint32_t dirty_mask = state->dirty_mask;
2120
2121 while (dirty_mask) {
2122 struct pipe_constant_buffer *cb;
2123 struct r600_resource *rbuffer;
2124 unsigned offset;
2125 unsigned buffer_index = ffs(dirty_mask) - 1;
2126
2127 cb = &state->cb[buffer_index];
2128 rbuffer = (struct r600_resource*)cb->buffer;
2129 assert(rbuffer);
2130
2131 offset = cb->buffer_offset;
2132
2133 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
2134 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
2135 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
2136
2137 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2138 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ));
2139
2140 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
2141 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
2142 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
2143 radeon_emit(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
2144 radeon_emit(cs, /* RESOURCEi_WORD2 */
2145 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
2146 S_038008_STRIDE(16));
2147 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
2148 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2149 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2150 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
2151
2152 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2153 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer, RADEON_USAGE_READ));
2154
2155 dirty_mask &= ~(1 << buffer_index);
2156 }
2157 state->dirty_mask = 0;
2158 }
2159
2160 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2161 {
2162 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 160,
2163 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2164 R_028980_ALU_CONST_CACHE_VS_0);
2165 }
2166
2167 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2168 {
2169 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
2170 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2171 R_0289C0_ALU_CONST_CACHE_GS_0);
2172 }
2173
2174 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2175 {
2176 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
2177 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2178 R_028940_ALU_CONST_CACHE_PS_0);
2179 }
2180
2181 static void r600_emit_sampler_views(struct r600_context *rctx,
2182 struct r600_samplerview_state *state,
2183 unsigned resource_id_base)
2184 {
2185 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2186 uint32_t dirty_mask = state->dirty_mask;
2187
2188 while (dirty_mask) {
2189 struct r600_pipe_sampler_view *rview;
2190 unsigned resource_index = u_bit_scan(&dirty_mask);
2191 unsigned reloc;
2192
2193 rview = state->views[resource_index];
2194 assert(rview);
2195
2196 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
2197 radeon_emit(cs, (resource_id_base + resource_index) * 7);
2198 radeon_emit_array(cs, rview->tex_resource_words, 7);
2199
2200 reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->tex_resource,
2201 RADEON_USAGE_READ);
2202 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2203 radeon_emit(cs, reloc);
2204 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2205 radeon_emit(cs, reloc);
2206 }
2207 state->dirty_mask = 0;
2208 }
2209
2210 /* Resource IDs:
2211 * PS: 0 .. +160
2212 * VS: 160 .. +160
2213 * FS: 320 .. +16
2214 * GS: 336 .. +160
2215 */
2216
2217 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2218 {
2219 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 160 + R600_MAX_CONST_BUFFERS);
2220 }
2221
2222 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2223 {
2224 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
2225 }
2226
2227 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2228 {
2229 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
2230 }
2231
2232 static void r600_emit_sampler_states(struct r600_context *rctx,
2233 struct r600_textures_info *texinfo,
2234 unsigned resource_id_base,
2235 unsigned border_color_reg)
2236 {
2237 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2238 uint32_t dirty_mask = texinfo->states.dirty_mask;
2239
2240 while (dirty_mask) {
2241 struct r600_pipe_sampler_state *rstate;
2242 struct r600_pipe_sampler_view *rview;
2243 unsigned i = u_bit_scan(&dirty_mask);
2244
2245 rstate = texinfo->states.states[i];
2246 assert(rstate);
2247 rview = texinfo->views.views[i];
2248
2249 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
2250 * filtering between layers.
2251 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
2252 */
2253 if (rview) {
2254 enum pipe_texture_target target = rview->base.texture->target;
2255 if (target == PIPE_TEXTURE_1D_ARRAY ||
2256 target == PIPE_TEXTURE_2D_ARRAY) {
2257 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
2258 texinfo->is_array_sampler[i] = true;
2259 } else {
2260 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
2261 texinfo->is_array_sampler[i] = false;
2262 }
2263 }
2264
2265 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2266 radeon_emit(cs, (resource_id_base + i) * 3);
2267 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2268
2269 if (rstate->border_color_use) {
2270 unsigned offset;
2271
2272 offset = border_color_reg;
2273 offset += i * 16;
2274 r600_write_config_reg_seq(cs, offset, 4);
2275 radeon_emit_array(cs, rstate->border_color.ui, 4);
2276 }
2277 }
2278 texinfo->states.dirty_mask = 0;
2279 }
2280
2281 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2282 {
2283 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
2284 }
2285
2286 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2287 {
2288 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
2289 }
2290
2291 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2292 {
2293 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
2294 }
2295
2296 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
2297 {
2298 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2299 unsigned tmp;
2300
2301 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
2302 S_009508_SYNC_GRADIENT(1) |
2303 S_009508_SYNC_WALKER(1) |
2304 S_009508_SYNC_ALIGNER(1);
2305 if (!rctx->seamless_cube_map.enabled) {
2306 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
2307 }
2308 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
2309 }
2310
2311 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2312 {
2313 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2314 uint8_t mask = s->sample_mask;
2315
2316 r600_write_context_reg(rctx->b.rings.gfx.cs, R_028C48_PA_SC_AA_MASK,
2317 mask | (mask << 8) | (mask << 16) | (mask << 24));
2318 }
2319
2320 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2321 {
2322 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2323 struct r600_cso_state *state = (struct r600_cso_state*)a;
2324 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2325
2326 r600_write_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
2327 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2328 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->buffer, RADEON_USAGE_READ));
2329 }
2330
2331 /* Adjust GPR allocation on R6xx/R7xx */
2332 bool r600_adjust_gprs(struct r600_context *rctx)
2333 {
2334 unsigned num_ps_gprs = rctx->ps_shader->current->shader.bc.ngpr;
2335 unsigned num_vs_gprs = rctx->vs_shader->current->shader.bc.ngpr;
2336 unsigned new_num_ps_gprs = num_ps_gprs;
2337 unsigned new_num_vs_gprs = num_vs_gprs;
2338 unsigned cur_num_ps_gprs = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2339 unsigned cur_num_vs_gprs = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2340 unsigned def_num_ps_gprs = rctx->default_ps_gprs;
2341 unsigned def_num_vs_gprs = rctx->default_vs_gprs;
2342 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
2343 /* hardware will reserve twice num_clause_temp_gprs */
2344 unsigned max_gprs = def_num_ps_gprs + def_num_vs_gprs + def_num_clause_temp_gprs * 2;
2345 unsigned tmp;
2346
2347 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2348 if (new_num_ps_gprs > cur_num_ps_gprs || new_num_vs_gprs > cur_num_vs_gprs) {
2349 /* try to use switch back to default */
2350 if (new_num_ps_gprs > def_num_ps_gprs || new_num_vs_gprs > def_num_vs_gprs) {
2351 /* always privilege vs stage so that at worst we have the
2352 * pixel stage producing wrong output (not the vertex
2353 * stage) */
2354 new_num_ps_gprs = max_gprs - (new_num_vs_gprs + def_num_clause_temp_gprs * 2);
2355 new_num_vs_gprs = num_vs_gprs;
2356 } else {
2357 new_num_ps_gprs = def_num_ps_gprs;
2358 new_num_vs_gprs = def_num_vs_gprs;
2359 }
2360 } else {
2361 return true;
2362 }
2363
2364 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2365 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2366 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2367 * it will lockup. So in this case just discard the draw command
2368 * and don't change the current gprs repartitions.
2369 */
2370 if (num_ps_gprs > new_num_ps_gprs || num_vs_gprs > new_num_vs_gprs) {
2371 R600_ERR("ps & vs shader require too many register (%d + %d) "
2372 "for a combined maximum of %d\n",
2373 num_ps_gprs, num_vs_gprs, max_gprs);
2374 return false;
2375 }
2376
2377 /* in some case we endup recomputing the current value */
2378 tmp = S_008C04_NUM_PS_GPRS(new_num_ps_gprs) |
2379 S_008C04_NUM_VS_GPRS(new_num_vs_gprs) |
2380 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2381 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp) {
2382 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2383 rctx->config_state.atom.dirty = true;
2384 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2385 }
2386 return true;
2387 }
2388
2389 void r600_init_atom_start_cs(struct r600_context *rctx)
2390 {
2391 int ps_prio;
2392 int vs_prio;
2393 int gs_prio;
2394 int es_prio;
2395 int num_ps_gprs;
2396 int num_vs_gprs;
2397 int num_gs_gprs;
2398 int num_es_gprs;
2399 int num_temp_gprs;
2400 int num_ps_threads;
2401 int num_vs_threads;
2402 int num_gs_threads;
2403 int num_es_threads;
2404 int num_ps_stack_entries;
2405 int num_vs_stack_entries;
2406 int num_gs_stack_entries;
2407 int num_es_stack_entries;
2408 enum radeon_family family;
2409 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2410 uint32_t tmp;
2411
2412 r600_init_command_buffer(cb, 256);
2413
2414 /* R6xx requires this packet at the start of each command buffer */
2415 if (rctx->b.chip_class == R600) {
2416 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2417 r600_store_value(cb, 0);
2418 }
2419 /* All asics require this one */
2420 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2421 r600_store_value(cb, 0x80000000);
2422 r600_store_value(cb, 0x80000000);
2423
2424 /* We're setting config registers here. */
2425 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2426 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2427
2428 family = rctx->b.family;
2429 ps_prio = 0;
2430 vs_prio = 1;
2431 gs_prio = 2;
2432 es_prio = 3;
2433 switch (family) {
2434 case CHIP_R600:
2435 num_ps_gprs = 192;
2436 num_vs_gprs = 56;
2437 num_temp_gprs = 4;
2438 num_gs_gprs = 0;
2439 num_es_gprs = 0;
2440 num_ps_threads = 136;
2441 num_vs_threads = 48;
2442 num_gs_threads = 4;
2443 num_es_threads = 4;
2444 num_ps_stack_entries = 128;
2445 num_vs_stack_entries = 128;
2446 num_gs_stack_entries = 0;
2447 num_es_stack_entries = 0;
2448 break;
2449 case CHIP_RV630:
2450 case CHIP_RV635:
2451 num_ps_gprs = 84;
2452 num_vs_gprs = 36;
2453 num_temp_gprs = 4;
2454 num_gs_gprs = 0;
2455 num_es_gprs = 0;
2456 num_ps_threads = 144;
2457 num_vs_threads = 40;
2458 num_gs_threads = 4;
2459 num_es_threads = 4;
2460 num_ps_stack_entries = 40;
2461 num_vs_stack_entries = 40;
2462 num_gs_stack_entries = 32;
2463 num_es_stack_entries = 16;
2464 break;
2465 case CHIP_RV610:
2466 case CHIP_RV620:
2467 case CHIP_RS780:
2468 case CHIP_RS880:
2469 default:
2470 num_ps_gprs = 84;
2471 num_vs_gprs = 36;
2472 num_temp_gprs = 4;
2473 num_gs_gprs = 0;
2474 num_es_gprs = 0;
2475 num_ps_threads = 136;
2476 num_vs_threads = 48;
2477 num_gs_threads = 4;
2478 num_es_threads = 4;
2479 num_ps_stack_entries = 40;
2480 num_vs_stack_entries = 40;
2481 num_gs_stack_entries = 32;
2482 num_es_stack_entries = 16;
2483 break;
2484 case CHIP_RV670:
2485 num_ps_gprs = 144;
2486 num_vs_gprs = 40;
2487 num_temp_gprs = 4;
2488 num_gs_gprs = 0;
2489 num_es_gprs = 0;
2490 num_ps_threads = 136;
2491 num_vs_threads = 48;
2492 num_gs_threads = 4;
2493 num_es_threads = 4;
2494 num_ps_stack_entries = 40;
2495 num_vs_stack_entries = 40;
2496 num_gs_stack_entries = 32;
2497 num_es_stack_entries = 16;
2498 break;
2499 case CHIP_RV770:
2500 num_ps_gprs = 192;
2501 num_vs_gprs = 56;
2502 num_temp_gprs = 4;
2503 num_gs_gprs = 0;
2504 num_es_gprs = 0;
2505 num_ps_threads = 188;
2506 num_vs_threads = 60;
2507 num_gs_threads = 0;
2508 num_es_threads = 0;
2509 num_ps_stack_entries = 256;
2510 num_vs_stack_entries = 256;
2511 num_gs_stack_entries = 0;
2512 num_es_stack_entries = 0;
2513 break;
2514 case CHIP_RV730:
2515 case CHIP_RV740:
2516 num_ps_gprs = 84;
2517 num_vs_gprs = 36;
2518 num_temp_gprs = 4;
2519 num_gs_gprs = 0;
2520 num_es_gprs = 0;
2521 num_ps_threads = 188;
2522 num_vs_threads = 60;
2523 num_gs_threads = 0;
2524 num_es_threads = 0;
2525 num_ps_stack_entries = 128;
2526 num_vs_stack_entries = 128;
2527 num_gs_stack_entries = 0;
2528 num_es_stack_entries = 0;
2529 break;
2530 case CHIP_RV710:
2531 num_ps_gprs = 192;
2532 num_vs_gprs = 56;
2533 num_temp_gprs = 4;
2534 num_gs_gprs = 0;
2535 num_es_gprs = 0;
2536 num_ps_threads = 144;
2537 num_vs_threads = 48;
2538 num_gs_threads = 0;
2539 num_es_threads = 0;
2540 num_ps_stack_entries = 128;
2541 num_vs_stack_entries = 128;
2542 num_gs_stack_entries = 0;
2543 num_es_stack_entries = 0;
2544 break;
2545 }
2546
2547 rctx->default_ps_gprs = num_ps_gprs;
2548 rctx->default_vs_gprs = num_vs_gprs;
2549 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2550
2551 /* SQ_CONFIG */
2552 tmp = 0;
2553 switch (family) {
2554 case CHIP_RV610:
2555 case CHIP_RV620:
2556 case CHIP_RS780:
2557 case CHIP_RS880:
2558 case CHIP_RV710:
2559 break;
2560 default:
2561 tmp |= S_008C00_VC_ENABLE(1);
2562 break;
2563 }
2564 tmp |= S_008C00_DX9_CONSTS(0);
2565 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2566 tmp |= S_008C00_PS_PRIO(ps_prio);
2567 tmp |= S_008C00_VS_PRIO(vs_prio);
2568 tmp |= S_008C00_GS_PRIO(gs_prio);
2569 tmp |= S_008C00_ES_PRIO(es_prio);
2570 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2571
2572 /* SQ_GPR_RESOURCE_MGMT_2 */
2573 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2574 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2575 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2576 r600_store_value(cb, tmp);
2577
2578 /* SQ_THREAD_RESOURCE_MGMT */
2579 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2580 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2581 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2582 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2583 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2584
2585 /* SQ_STACK_RESOURCE_MGMT_1 */
2586 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2587 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2588 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2589
2590 /* SQ_STACK_RESOURCE_MGMT_2 */
2591 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2592 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2593 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2594
2595 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2596
2597 if (rctx->b.chip_class >= R700) {
2598 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2599 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2600 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2601 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2602 } else {
2603 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2604 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2605 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2606 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2607 }
2608 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2609 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2610 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2611 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2612 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2613 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2614 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2615 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2616 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2617 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2618
2619 /* to avoid GPU doing any preloading of constant from random address */
2620 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2621 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2622 r600_store_value(cb, 0);
2623 r600_store_value(cb, 0);
2624 r600_store_value(cb, 0);
2625 r600_store_value(cb, 0);
2626 r600_store_value(cb, 0);
2627 r600_store_value(cb, 0);
2628 r600_store_value(cb, 0);
2629 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2630 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2631 r600_store_value(cb, 0);
2632 r600_store_value(cb, 0);
2633 r600_store_value(cb, 0);
2634 r600_store_value(cb, 0);
2635 r600_store_value(cb, 0);
2636 r600_store_value(cb, 0);
2637 r600_store_value(cb, 0);
2638
2639 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2640 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2641 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2642 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2643 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2644 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2645 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2646 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2647 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2648 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2649 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2650 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2651 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2652 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2653
2654 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2655 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2656 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2657
2658 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2659 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2660 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2661 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2662
2663 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2664
2665 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2666
2667 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2668
2669 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2670 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2671 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2672 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2673
2674 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2675 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2676 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2677 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2678
2679 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2680 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2681
2682 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2683 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2684 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2685 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2686 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2687
2688 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2689 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2690 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2691
2692 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2693
2694 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2695 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2696
2697 if (rctx->b.chip_class >= R700) {
2698 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2699 }
2700
2701 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2702 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2703 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2704 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2705 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2706
2707 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2708 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2709 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2710
2711 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2712 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2713 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2714
2715 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2716 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2717 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2718
2719 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2720
2721 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2722 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2723 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2724
2725 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2726 r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2727
2728 if (rctx->b.chip_class == R700 && rctx->screen->has_streamout)
2729 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2730 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2731 if (rctx->screen->has_streamout) {
2732 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2733 }
2734
2735 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2736 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2737 }
2738
2739 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2740 {
2741 struct r600_context *rctx = (struct r600_context *)ctx;
2742 struct r600_command_buffer *cb = &shader->command_buffer;
2743 struct r600_shader *rshader = &shader->shader;
2744 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2745 int pos_index = -1, face_index = -1;
2746 unsigned tmp, sid, ufi = 0;
2747 int need_linear = 0;
2748 unsigned z_export = 0, stencil_export = 0;
2749 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2750
2751 if (!cb->buf) {
2752 r600_init_command_buffer(cb, 64);
2753 } else {
2754 cb->num_dw = 0;
2755 }
2756
2757 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2758 for (i = 0; i < rshader->ninput; i++) {
2759 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2760 pos_index = i;
2761 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2762 face_index = i;
2763
2764 sid = rshader->input[i].spi_sid;
2765
2766 tmp = S_028644_SEMANTIC(sid);
2767
2768 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2769 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2770 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2771 rctx->rasterizer && rctx->rasterizer->flatshade))
2772 tmp |= S_028644_FLAT_SHADE(1);
2773
2774 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2775 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2776 tmp |= S_028644_PT_SPRITE_TEX(1);
2777 }
2778
2779 if (rshader->input[i].centroid)
2780 tmp |= S_028644_SEL_CENTROID(1);
2781
2782 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2783 need_linear = 1;
2784 tmp |= S_028644_SEL_LINEAR(1);
2785 }
2786
2787 r600_store_value(cb, tmp);
2788 }
2789
2790 db_shader_control = 0;
2791 for (i = 0; i < rshader->noutput; i++) {
2792 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2793 z_export = 1;
2794 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2795 stencil_export = 1;
2796 }
2797 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2798 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2799 if (rshader->uses_kill)
2800 db_shader_control |= S_02880C_KILL_ENABLE(1);
2801
2802 exports_ps = 0;
2803 for (i = 0; i < rshader->noutput; i++) {
2804 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2805 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2806 exports_ps |= 1;
2807 }
2808 }
2809 num_cout = rshader->nr_ps_color_exports;
2810 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2811 if (!exports_ps) {
2812 /* always at least export 1 component per pixel */
2813 exports_ps = 2;
2814 }
2815
2816 shader->nr_ps_color_outputs = num_cout;
2817
2818 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2819 S_0286CC_PERSP_GRADIENT_ENA(1)|
2820 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2821 spi_input_z = 0;
2822 if (pos_index != -1) {
2823 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2824 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2825 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2826 S_0286CC_BARYC_SAMPLE_CNTL(1));
2827 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2828 }
2829
2830 spi_ps_in_control_1 = 0;
2831 if (face_index != -1) {
2832 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2833 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2834 }
2835
2836 /* HW bug in original R600 */
2837 if (rctx->b.family == CHIP_R600)
2838 ufi = 1;
2839
2840 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2841 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2842 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2843
2844 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2845
2846 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2847 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2848 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2849 S_028850_STACK_SIZE(rshader->bc.nstack) |
2850 S_028850_UNCACHED_FIRST_INST(ufi));
2851 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2852
2853 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2854 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2855
2856 /* only set some bits here, the other bits are set in the dsa state */
2857 shader->db_shader_control = db_shader_control;
2858 shader->ps_depth_export = z_export | stencil_export;
2859
2860 shader->sprite_coord_enable = sprite_coord_enable;
2861 if (rctx->rasterizer)
2862 shader->flatshade = rctx->rasterizer->flatshade;
2863 }
2864
2865 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2866 {
2867 struct r600_command_buffer *cb = &shader->command_buffer;
2868 struct r600_shader *rshader = &shader->shader;
2869 unsigned spi_vs_out_id[10] = {};
2870 unsigned i, tmp, nparams = 0;
2871
2872 for (i = 0; i < rshader->noutput; i++) {
2873 if (rshader->output[i].spi_sid) {
2874 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2875 spi_vs_out_id[nparams / 4] |= tmp;
2876 nparams++;
2877 }
2878 }
2879
2880 r600_init_command_buffer(cb, 32);
2881
2882 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2883 for (i = 0; i < 10; i++) {
2884 r600_store_value(cb, spi_vs_out_id[i]);
2885 }
2886
2887 /* Certain attributes (position, psize, etc.) don't count as params.
2888 * VS is required to export at least one param and r600_shader_from_tgsi()
2889 * takes care of adding a dummy export.
2890 */
2891 if (nparams < 1)
2892 nparams = 1;
2893
2894 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2895 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2896 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2897 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2898 S_028868_STACK_SIZE(rshader->bc.nstack));
2899 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2900 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2901
2902 shader->pa_cl_vs_out_cntl =
2903 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2904 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2905 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2906 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2907 }
2908
2909 void *r600_create_resolve_blend(struct r600_context *rctx)
2910 {
2911 struct pipe_blend_state blend;
2912 unsigned i;
2913
2914 memset(&blend, 0, sizeof(blend));
2915 blend.independent_blend_enable = true;
2916 for (i = 0; i < 2; i++) {
2917 blend.rt[i].colormask = 0xf;
2918 blend.rt[i].blend_enable = 1;
2919 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2920 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2921 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2922 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2923 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2924 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2925 }
2926 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2927 }
2928
2929 void *r700_create_resolve_blend(struct r600_context *rctx)
2930 {
2931 struct pipe_blend_state blend;
2932
2933 memset(&blend, 0, sizeof(blend));
2934 blend.independent_blend_enable = true;
2935 blend.rt[0].colormask = 0xf;
2936 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2937 }
2938
2939 void *r600_create_decompress_blend(struct r600_context *rctx)
2940 {
2941 struct pipe_blend_state blend;
2942
2943 memset(&blend, 0, sizeof(blend));
2944 blend.independent_blend_enable = true;
2945 blend.rt[0].colormask = 0xf;
2946 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2947 }
2948
2949 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2950 {
2951 struct pipe_depth_stencil_alpha_state dsa;
2952 boolean quirk = false;
2953
2954 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2955 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2956 quirk = true;
2957
2958 memset(&dsa, 0, sizeof(dsa));
2959
2960 if (quirk) {
2961 dsa.depth.enabled = 1;
2962 dsa.depth.func = PIPE_FUNC_LEQUAL;
2963 dsa.stencil[0].enabled = 1;
2964 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2965 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2966 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2967 dsa.stencil[0].writemask = 0xff;
2968 }
2969
2970 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2971 }
2972
2973 void r600_update_db_shader_control(struct r600_context * rctx)
2974 {
2975 bool dual_export = rctx->framebuffer.export_16bpc &&
2976 !rctx->ps_shader->current->ps_depth_export;
2977
2978 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2979 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2980
2981 /* When alpha test is enabled we can't trust the hw to make the proper
2982 * decision on the order in which ztest should be run related to fragment
2983 * shader execution.
2984 *
2985 * If alpha test is enabled perform z test after fragment. RE_Z (early
2986 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2987 */
2988 if (rctx->alphatest_state.sx_alpha_test_control) {
2989 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2990 } else {
2991 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2992 }
2993
2994 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
2995 rctx->db_misc_state.db_shader_control = db_shader_control;
2996 rctx->db_misc_state.atom.dirty = true;
2997 }
2998 }
2999
3000 static INLINE unsigned r600_array_mode(unsigned mode)
3001 {
3002 switch (mode) {
3003 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
3004 break;
3005 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
3006 break;
3007 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
3008 default:
3009 case RADEON_SURF_MODE_LINEAR: return V_0280A0_ARRAY_LINEAR_GENERAL;
3010 }
3011 }
3012
3013 static boolean r600_dma_copy_tile(struct r600_context *rctx,
3014 struct pipe_resource *dst,
3015 unsigned dst_level,
3016 unsigned dst_x,
3017 unsigned dst_y,
3018 unsigned dst_z,
3019 struct pipe_resource *src,
3020 unsigned src_level,
3021 unsigned src_x,
3022 unsigned src_y,
3023 unsigned src_z,
3024 unsigned copy_height,
3025 unsigned pitch,
3026 unsigned bpp)
3027 {
3028 struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs;
3029 struct r600_texture *rsrc = (struct r600_texture*)src;
3030 struct r600_texture *rdst = (struct r600_texture*)dst;
3031 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3032 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3033 uint64_t base, addr;
3034
3035 /* make sure that the dma ring is only one active */
3036 rctx->b.rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
3037
3038 dst_mode = rdst->surface.level[dst_level].mode;
3039 src_mode = rsrc->surface.level[src_level].mode;
3040 /* downcast linear aligned to linear to simplify test */
3041 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3042 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3043 assert(dst_mode != src_mode);
3044
3045 y = 0;
3046 lbpp = util_logbase2(bpp);
3047 pitch_tile_max = ((pitch / bpp) >> 3) - 1;
3048
3049 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
3050 /* T2L */
3051 array_mode = r600_array_mode(src_mode);
3052 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) >> 6;
3053 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3054 /* linear height must be the same as the slice tile max height, it's ok even
3055 * if the linear destination/source have smaller heigh as the size of the
3056 * dma packet will be using the copy_height which is always smaller or equal
3057 * to the linear height
3058 */
3059 height = rsrc->surface.level[src_level].npix_y;
3060 detile = 1;
3061 x = src_x;
3062 y = src_y;
3063 z = src_z;
3064 base = rsrc->surface.level[src_level].offset;
3065 addr = rdst->surface.level[dst_level].offset;
3066 addr += rdst->surface.level[dst_level].slice_size * dst_z;
3067 addr += dst_y * pitch + dst_x * bpp;
3068 } else {
3069 /* L2T */
3070 array_mode = r600_array_mode(dst_mode);
3071 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) >> 6;
3072 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3073 /* linear height must be the same as the slice tile max height, it's ok even
3074 * if the linear destination/source have smaller heigh as the size of the
3075 * dma packet will be using the copy_height which is always smaller or equal
3076 * to the linear height
3077 */
3078 height = rdst->surface.level[dst_level].npix_y;
3079 detile = 0;
3080 x = dst_x;
3081 y = dst_y;
3082 z = dst_z;
3083 base = rdst->surface.level[dst_level].offset;
3084 addr = rsrc->surface.level[src_level].offset;
3085 addr += rsrc->surface.level[src_level].slice_size * src_z;
3086 addr += src_y * pitch + src_x * bpp;
3087 }
3088 /* check that we are in dw/base alignment constraint */
3089 if ((addr & 0x3) || (base & 0xff)) {
3090 return FALSE;
3091 }
3092
3093 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
3094 * line in the blit. Compute max 8 line we can copy in the size limit
3095 */
3096 cheight = ((0x0000ffff << 2) / pitch) & 0xfffffff8;
3097 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
3098 r600_need_dma_space(rctx, ncopy * 7);
3099
3100 for (i = 0; i < ncopy; i++) {
3101 cheight = cheight > copy_height ? copy_height : cheight;
3102 size = (cheight * pitch) >> 2;
3103 /* emit reloc before writting cs so that cs is always in consistent state */
3104 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rsrc->resource, RADEON_USAGE_READ);
3105 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rdst->resource, RADEON_USAGE_WRITE);
3106 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 1, 0, size);
3107 cs->buf[cs->cdw++] = base >> 8;
3108 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
3109 (lbpp << 24) | ((height - 1) << 10) |
3110 pitch_tile_max;
3111 cs->buf[cs->cdw++] = (slice_tile_max << 12) | (z << 0);
3112 cs->buf[cs->cdw++] = (x << 3) | (y << 17);
3113 cs->buf[cs->cdw++] = addr & 0xfffffffc;
3114 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
3115 copy_height -= cheight;
3116 addr += cheight * pitch;
3117 y += cheight;
3118 }
3119 return TRUE;
3120 }
3121
3122 static boolean r600_dma_blit(struct pipe_context *ctx,
3123 struct pipe_resource *dst,
3124 unsigned dst_level,
3125 unsigned dst_x, unsigned dst_y, unsigned dst_z,
3126 struct pipe_resource *src,
3127 unsigned src_level,
3128 const struct pipe_box *src_box)
3129 {
3130 struct r600_context *rctx = (struct r600_context *)ctx;
3131 struct r600_texture *rsrc = (struct r600_texture*)src;
3132 struct r600_texture *rdst = (struct r600_texture*)dst;
3133 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3134 unsigned src_w, dst_w;
3135 unsigned src_x, src_y;
3136
3137 if (rctx->b.rings.dma.cs == NULL) {
3138 return FALSE;
3139 }
3140 if (src->format != dst->format) {
3141 return FALSE;
3142 }
3143
3144 src_x = util_format_get_nblocksx(src->format, src_box->x);
3145 dst_x = util_format_get_nblocksx(src->format, dst_x);
3146 src_y = util_format_get_nblocksy(src->format, src_box->y);
3147 dst_y = util_format_get_nblocksy(src->format, dst_y);
3148
3149 bpp = rdst->surface.bpe;
3150 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
3151 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
3152 src_w = rsrc->surface.level[src_level].npix_x;
3153 dst_w = rdst->surface.level[dst_level].npix_x;
3154 copy_height = src_box->height / rsrc->surface.blk_h;
3155
3156 dst_mode = rdst->surface.level[dst_level].mode;
3157 src_mode = rsrc->surface.level[src_level].mode;
3158 /* downcast linear aligned to linear to simplify test */
3159 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3160 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3161
3162 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3163 /* strick requirement on r6xx/r7xx */
3164 return FALSE;
3165 }
3166 /* lot of constraint on alignment this should capture them all */
3167 if ((src_pitch & 0x7) || (src_box->y & 0x7) || (dst_y & 0x7)) {
3168 return FALSE;
3169 }
3170
3171 if (src_mode == dst_mode) {
3172 uint64_t dst_offset, src_offset, size;
3173
3174 /* simple dma blit would do NOTE code here assume :
3175 * src_box.x/y == 0
3176 * dst_x/y == 0
3177 * dst_pitch == src_pitch
3178 */
3179 src_offset= rsrc->surface.level[src_level].offset;
3180 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3181 src_offset += src_y * src_pitch + src_x * bpp;
3182 dst_offset = rdst->surface.level[dst_level].offset;
3183 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3184 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3185 size = src_box->height * src_pitch;
3186 /* must be dw aligned */
3187 if ((dst_offset & 0x3) || (src_offset & 0x3) || (size & 0x3)) {
3188 return FALSE;
3189 }
3190 r600_dma_copy(rctx, dst, src, dst_offset, src_offset, size);
3191 } else {
3192 return r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3193 src, src_level, src_x, src_y, src_box->z,
3194 copy_height, dst_pitch, bpp);
3195 }
3196 return TRUE;
3197 }
3198
3199 void r600_init_state_functions(struct r600_context *rctx)
3200 {
3201 unsigned id = 4;
3202
3203 /* !!!
3204 * To avoid GPU lockup registers must be emited in a specific order
3205 * (no kidding ...). The order below is important and have been
3206 * partialy infered from analyzing fglrx command stream.
3207 *
3208 * Don't reorder atom without carefully checking the effect (GPU lockup
3209 * or piglit regression).
3210 * !!!
3211 */
3212
3213 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
3214
3215 /* shader const */
3216 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
3217 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
3218 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
3219
3220 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3221 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
3222 */
3223 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
3224 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
3225 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
3226 /* resource */
3227 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
3228 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
3229 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
3230 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
3231
3232 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 7);
3233
3234 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3235 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3236 rctx->sample_mask.sample_mask = ~0;
3237
3238 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3239 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3240 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3241 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3242 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3243 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3244 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3245 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3246 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3247 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
3248 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3249 r600_init_atom(rctx, &rctx->scissor.atom, id++, r600_emit_scissor_state, 4);
3250 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3251 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3252 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
3253 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3254 rctx->atoms[id++] = &rctx->b.streamout.begin_atom;
3255 r600_init_atom(rctx, &rctx->vertex_shader.atom, id++, r600_emit_shader, 23);
3256 r600_init_atom(rctx, &rctx->pixel_shader.atom, id++, r600_emit_shader, 0);
3257
3258 rctx->b.b.create_blend_state = r600_create_blend_state;
3259 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3260 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3261 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3262 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3263 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3264 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3265 rctx->b.b.set_scissor_states = r600_set_scissor_states;
3266 rctx->b.b.get_sample_position = r600_get_sample_position;
3267 rctx->b.dma_copy = r600_dma_blit;
3268 }
3269 /* this function must be last */