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r600g: fix for broken CULL_FRONT behavior on R6xx
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
145 {
146 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
147 }
148
149 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
150 {
151 return r600_translate_colorformat(chip, format) != ~0U &&
152 r600_translate_colorswap(format) != ~0U;
153 }
154
155 static bool r600_is_zs_format_supported(enum pipe_format format)
156 {
157 return r600_translate_dbformat(format) != ~0U;
158 }
159
160 boolean r600_is_format_supported(struct pipe_screen *screen,
161 enum pipe_format format,
162 enum pipe_texture_target target,
163 unsigned sample_count,
164 unsigned usage)
165 {
166 struct r600_screen *rscreen = (struct r600_screen*)screen;
167 unsigned retval = 0;
168
169 if (target >= PIPE_MAX_TEXTURE_TYPES) {
170 R600_ERR("r600: unsupported texture type %d\n", target);
171 return FALSE;
172 }
173
174 if (!util_format_is_supported(format, usage))
175 return FALSE;
176
177 if (sample_count > 1) {
178 if (!rscreen->has_msaa)
179 return FALSE;
180
181 /* R11G11B10 is broken on R6xx. */
182 if (rscreen->b.chip_class == R600 &&
183 format == PIPE_FORMAT_R11G11B10_FLOAT)
184 return FALSE;
185
186 /* MSAA integer colorbuffers hang. */
187 if (util_format_is_pure_integer(format) &&
188 !util_format_is_depth_or_stencil(format))
189 return FALSE;
190
191 switch (sample_count) {
192 case 2:
193 case 4:
194 case 8:
195 break;
196 default:
197 return FALSE;
198 }
199 }
200
201 if (usage & PIPE_BIND_SAMPLER_VIEW) {
202 if (target == PIPE_BUFFER) {
203 if (r600_is_vertex_format_supported(format))
204 retval |= PIPE_BIND_SAMPLER_VIEW;
205 } else {
206 if (r600_is_sampler_format_supported(screen, format))
207 retval |= PIPE_BIND_SAMPLER_VIEW;
208 }
209 }
210
211 if ((usage & (PIPE_BIND_RENDER_TARGET |
212 PIPE_BIND_DISPLAY_TARGET |
213 PIPE_BIND_SCANOUT |
214 PIPE_BIND_SHARED)) &&
215 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
216 retval |= usage &
217 (PIPE_BIND_RENDER_TARGET |
218 PIPE_BIND_DISPLAY_TARGET |
219 PIPE_BIND_SCANOUT |
220 PIPE_BIND_SHARED);
221 }
222
223 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
224 r600_is_zs_format_supported(format)) {
225 retval |= PIPE_BIND_DEPTH_STENCIL;
226 }
227
228 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
229 r600_is_vertex_format_supported(format)) {
230 retval |= PIPE_BIND_VERTEX_BUFFER;
231 }
232
233 if (usage & PIPE_BIND_TRANSFER_READ)
234 retval |= PIPE_BIND_TRANSFER_READ;
235 if (usage & PIPE_BIND_TRANSFER_WRITE)
236 retval |= PIPE_BIND_TRANSFER_WRITE;
237
238 return retval == usage;
239 }
240
241 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
242 {
243 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
244 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
245 float offset_units = state->offset_units;
246 float offset_scale = state->offset_scale;
247
248 switch (state->zs_format) {
249 case PIPE_FORMAT_Z24X8_UNORM:
250 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
251 offset_units *= 2.0f;
252 break;
253 case PIPE_FORMAT_Z16_UNORM:
254 offset_units *= 4.0f;
255 break;
256 default:;
257 }
258
259 r600_write_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
260 radeon_emit(cs, fui(offset_scale));
261 radeon_emit(cs, fui(offset_units));
262 radeon_emit(cs, fui(offset_scale));
263 radeon_emit(cs, fui(offset_units));
264 }
265
266 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
267 {
268 int j = state->independent_blend_enable ? i : 0;
269
270 unsigned eqRGB = state->rt[j].rgb_func;
271 unsigned srcRGB = state->rt[j].rgb_src_factor;
272 unsigned dstRGB = state->rt[j].rgb_dst_factor;
273
274 unsigned eqA = state->rt[j].alpha_func;
275 unsigned srcA = state->rt[j].alpha_src_factor;
276 unsigned dstA = state->rt[j].alpha_dst_factor;
277 uint32_t bc = 0;
278
279 if (!state->rt[j].blend_enable)
280 return 0;
281
282 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
283 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
284 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
285
286 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
287 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
288 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
289 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
290 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
291 }
292 return bc;
293 }
294
295 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
296 const struct pipe_blend_state *state,
297 int mode)
298 {
299 struct r600_context *rctx = (struct r600_context *)ctx;
300 uint32_t color_control = 0, target_mask = 0;
301 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
302
303 if (!blend) {
304 return NULL;
305 }
306
307 r600_init_command_buffer(&blend->buffer, 20);
308 r600_init_command_buffer(&blend->buffer_no_blend, 20);
309
310 /* R600 does not support per-MRT blends */
311 if (rctx->b.family > CHIP_R600)
312 color_control |= S_028808_PER_MRT_BLEND(1);
313
314 if (state->logicop_enable) {
315 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
316 } else {
317 color_control |= (0xcc << 16);
318 }
319 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
320 if (state->independent_blend_enable) {
321 for (int i = 0; i < 8; i++) {
322 if (state->rt[i].blend_enable) {
323 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
324 }
325 target_mask |= (state->rt[i].colormask << (4 * i));
326 }
327 } else {
328 for (int i = 0; i < 8; i++) {
329 if (state->rt[0].blend_enable) {
330 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
331 }
332 target_mask |= (state->rt[0].colormask << (4 * i));
333 }
334 }
335
336 if (target_mask)
337 color_control |= S_028808_SPECIAL_OP(mode);
338 else
339 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
340
341 /* only MRT0 has dual src blend */
342 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
343 blend->cb_target_mask = target_mask;
344 blend->cb_color_control = color_control;
345 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
346 blend->alpha_to_one = state->alpha_to_one;
347
348 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
349 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
350 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
351 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
352 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
353 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
354
355 /* Copy over the registers set so far into buffer_no_blend. */
356 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
357 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
358
359 /* Only add blend registers if blending is enabled. */
360 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
361 return blend;
362 }
363
364 /* The first R600 does not support per-MRT blends */
365 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
366 r600_get_blend_control(state, 0));
367
368 if (rctx->b.family > CHIP_R600) {
369 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
370 for (int i = 0; i < 8; i++) {
371 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
372 }
373 }
374 return blend;
375 }
376
377 static void *r600_create_blend_state(struct pipe_context *ctx,
378 const struct pipe_blend_state *state)
379 {
380 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
381 }
382
383 static void *r600_create_dsa_state(struct pipe_context *ctx,
384 const struct pipe_depth_stencil_alpha_state *state)
385 {
386 unsigned db_depth_control, alpha_test_control, alpha_ref;
387 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
388
389 if (dsa == NULL) {
390 return NULL;
391 }
392
393 r600_init_command_buffer(&dsa->buffer, 3);
394
395 dsa->valuemask[0] = state->stencil[0].valuemask;
396 dsa->valuemask[1] = state->stencil[1].valuemask;
397 dsa->writemask[0] = state->stencil[0].writemask;
398 dsa->writemask[1] = state->stencil[1].writemask;
399 dsa->zwritemask = state->depth.writemask;
400
401 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
402 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
403 S_028800_ZFUNC(state->depth.func);
404
405 /* stencil */
406 if (state->stencil[0].enabled) {
407 db_depth_control |= S_028800_STENCIL_ENABLE(1);
408 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
409 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
410 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
411 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
412
413 if (state->stencil[1].enabled) {
414 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
415 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
416 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
417 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
418 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
419 }
420 }
421
422 /* alpha */
423 alpha_test_control = 0;
424 alpha_ref = 0;
425 if (state->alpha.enabled) {
426 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
427 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
428 alpha_ref = fui(state->alpha.ref_value);
429 }
430 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
431 dsa->alpha_ref = alpha_ref;
432
433 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
434 return dsa;
435 }
436
437 static void *r600_create_rs_state(struct pipe_context *ctx,
438 const struct pipe_rasterizer_state *state)
439 {
440 struct r600_context *rctx = (struct r600_context *)ctx;
441 unsigned tmp, sc_mode_cntl, spi_interp;
442 float psize_min, psize_max;
443 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
444
445 if (rs == NULL) {
446 return NULL;
447 }
448
449 r600_init_command_buffer(&rs->buffer, 30);
450
451 rs->flatshade = state->flatshade;
452 rs->sprite_coord_enable = state->sprite_coord_enable;
453 rs->two_side = state->light_twoside;
454 rs->clip_plane_enable = state->clip_plane_enable;
455 rs->pa_sc_line_stipple = state->line_stipple_enable ?
456 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
457 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
458 rs->pa_cl_clip_cntl =
459 S_028810_PS_UCP_MODE(3) |
460 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
461 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
462 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
463 rs->multisample_enable = state->multisample;
464
465 /* offset */
466 rs->offset_units = state->offset_units;
467 rs->offset_scale = state->offset_scale * 12.0f;
468 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
469
470 if (state->point_size_per_vertex) {
471 psize_min = util_get_min_point_size(state);
472 psize_max = 8192;
473 } else {
474 /* Force the point size to be as if the vertex output was disabled. */
475 psize_min = state->point_size;
476 psize_max = state->point_size;
477 }
478
479 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
480 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
481 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
482 if (rctx->b.chip_class >= R700) {
483 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
484 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
485 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
486 } else {
487 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
488 rs->scissor_enable = state->scissor;
489 }
490
491 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
492 if (state->sprite_coord_enable) {
493 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
494 S_0286D4_PNT_SPRITE_OVRD_X(2) |
495 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
496 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
497 S_0286D4_PNT_SPRITE_OVRD_W(1);
498 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
499 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
500 }
501 }
502
503 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
504 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
505 tmp = r600_pack_float_12p4(state->point_size/2);
506 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
507 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
508 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
509 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
510 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
511 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
512 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
513
514 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
515 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
516 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
517 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
518 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
519 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
520
521 rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
522 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
523 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
524 S_028814_FACE(!state->front_ccw) |
525 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
526 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
527 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
528 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
529 state->fill_back != PIPE_POLYGON_MODE_FILL) |
530 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
531 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
532 if (rctx->b.chip_class == R700) {
533 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl);
534 }
535 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
536 return rs;
537 }
538
539 static void *r600_create_sampler_state(struct pipe_context *ctx,
540 const struct pipe_sampler_state *state)
541 {
542 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
543 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
544
545 if (ss == NULL) {
546 return NULL;
547 }
548
549 ss->seamless_cube_map = state->seamless_cube_map;
550 ss->border_color_use = sampler_state_needs_border_color(state);
551
552 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
553 ss->tex_sampler_words[0] =
554 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
555 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
556 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
557 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
558 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
559 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
560 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
561 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
562 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
563 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
564 ss->tex_sampler_words[1] =
565 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
566 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
567 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
568 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
569 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
570
571 if (ss->border_color_use) {
572 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
573 }
574 return ss;
575 }
576
577 static struct pipe_sampler_view *
578 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
579 unsigned width0, unsigned height0)
580
581 {
582 struct pipe_context *ctx = view->base.context;
583 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
584 uint64_t va;
585 int stride = util_format_get_blocksize(view->base.format);
586 unsigned format, num_format, format_comp, endian;
587 unsigned offset = view->base.u.buf.first_element * stride;
588 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
589
590 r600_vertex_data_type(view->base.format,
591 &format, &num_format, &format_comp,
592 &endian);
593
594 va = r600_resource_va(ctx->screen, view->base.texture) + offset;
595 view->tex_resource = &tmp->resource;
596
597 view->skip_mip_address_reloc = true;
598 view->tex_resource_words[0] = va;
599 view->tex_resource_words[1] = size - 1;
600 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(va >> 32UL) |
601 S_038008_STRIDE(stride) |
602 S_038008_DATA_FORMAT(format) |
603 S_038008_NUM_FORMAT_ALL(num_format) |
604 S_038008_FORMAT_COMP_ALL(format_comp) |
605 S_038008_SRF_MODE_ALL(1) |
606 S_038008_ENDIAN_SWAP(endian);
607 view->tex_resource_words[3] = 0;
608 /*
609 * in theory dword 4 is for number of elements, for use with resinfo,
610 * but it seems to utterly fail to work, the amd gpu shader analyser
611 * uses a const buffer to store the element sizes for buffer txq
612 */
613 view->tex_resource_words[4] = 0;
614 view->tex_resource_words[5] = 0;
615 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
616 return &view->base;
617 }
618
619 struct pipe_sampler_view *
620 r600_create_sampler_view_custom(struct pipe_context *ctx,
621 struct pipe_resource *texture,
622 const struct pipe_sampler_view *state,
623 unsigned width_first_level, unsigned height_first_level)
624 {
625 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
626 struct r600_texture *tmp = (struct r600_texture*)texture;
627 unsigned format, endian;
628 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
629 unsigned char swizzle[4], array_mode = 0;
630 unsigned width, height, depth, offset_level, last_level;
631
632 if (view == NULL)
633 return NULL;
634
635 /* initialize base object */
636 view->base = *state;
637 view->base.texture = NULL;
638 pipe_reference(NULL, &texture->reference);
639 view->base.texture = texture;
640 view->base.reference.count = 1;
641 view->base.context = ctx;
642
643 if (texture->target == PIPE_BUFFER)
644 return texture_buffer_sampler_view(view, texture->width0, 1);
645
646 swizzle[0] = state->swizzle_r;
647 swizzle[1] = state->swizzle_g;
648 swizzle[2] = state->swizzle_b;
649 swizzle[3] = state->swizzle_a;
650
651 format = r600_translate_texformat(ctx->screen, state->format,
652 swizzle,
653 &word4, &yuv_format);
654 assert(format != ~0);
655 if (format == ~0) {
656 FREE(view);
657 return NULL;
658 }
659
660 if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) {
661 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
662 FREE(view);
663 return NULL;
664 }
665 tmp = tmp->flushed_depth_texture;
666 }
667
668 endian = r600_colorformat_endian_swap(format);
669
670 offset_level = state->u.tex.first_level;
671 last_level = state->u.tex.last_level - offset_level;
672 width = width_first_level;
673 height = height_first_level;
674 depth = u_minify(texture->depth0, offset_level);
675 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
676
677 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
678 height = 1;
679 depth = texture->array_size;
680 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
681 depth = texture->array_size;
682 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
683 depth = texture->array_size / 6;
684 switch (tmp->surface.level[offset_level].mode) {
685 case RADEON_SURF_MODE_LINEAR_ALIGNED:
686 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
687 break;
688 case RADEON_SURF_MODE_1D:
689 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
690 break;
691 case RADEON_SURF_MODE_2D:
692 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
693 break;
694 case RADEON_SURF_MODE_LINEAR:
695 default:
696 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
697 break;
698 }
699
700 view->tex_resource = &tmp->resource;
701 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
702 S_038000_TILE_MODE(array_mode) |
703 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
704 S_038000_PITCH((pitch / 8) - 1) |
705 S_038000_TEX_WIDTH(width - 1));
706 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
707 S_038004_TEX_DEPTH(depth - 1) |
708 S_038004_DATA_FORMAT(format));
709 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
710 if (offset_level >= tmp->surface.last_level) {
711 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
712 } else {
713 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
714 }
715 view->tex_resource_words[4] = (word4 |
716 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
717 S_038010_REQUEST_SIZE(1) |
718 S_038010_ENDIAN_SWAP(endian) |
719 S_038010_BASE_LEVEL(0));
720 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
721 S_038014_LAST_ARRAY(state->u.tex.last_layer));
722 if (texture->nr_samples > 1) {
723 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
724 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
725 } else {
726 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
727 }
728 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
729 S_038018_MAX_ANISO(4 /* max 16 samples */));
730 return &view->base;
731 }
732
733 static struct pipe_sampler_view *
734 r600_create_sampler_view(struct pipe_context *ctx,
735 struct pipe_resource *tex,
736 const struct pipe_sampler_view *state)
737 {
738 return r600_create_sampler_view_custom(ctx, tex, state,
739 u_minify(tex->width0, state->u.tex.first_level),
740 u_minify(tex->height0, state->u.tex.first_level));
741 }
742
743 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
744 {
745 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
746 struct pipe_clip_state *state = &rctx->clip_state.state;
747
748 r600_write_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
749 radeon_emit_array(cs, (unsigned*)state, 6*4);
750 }
751
752 static void r600_set_polygon_stipple(struct pipe_context *ctx,
753 const struct pipe_poly_stipple *state)
754 {
755 }
756
757 static void r600_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
758 {
759 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
760 struct r600_scissor_state *rstate = (struct r600_scissor_state *)atom;
761 struct pipe_scissor_state *state = &rstate->scissor;
762 unsigned offset = rstate->idx * 4 * 2;
763
764 if (rctx->b.chip_class != R600 || rctx->scissor[0].enable) {
765 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + offset, 2);
766 radeon_emit(cs, S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) |
767 S_028240_WINDOW_OFFSET_DISABLE(1));
768 radeon_emit(cs, S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy));
769 } else {
770 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
771 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
772 S_028240_WINDOW_OFFSET_DISABLE(1));
773 radeon_emit(cs, S_028244_BR_X(8192) | S_028244_BR_Y(8192));
774 }
775 }
776
777 static void r600_set_scissor_states(struct pipe_context *ctx,
778 unsigned start_slot,
779 unsigned num_scissors,
780 const struct pipe_scissor_state *state)
781 {
782 struct r600_context *rctx = (struct r600_context *)ctx;
783 int i;
784
785 for (i = start_slot ; i < start_slot + num_scissors; i++) {
786 rctx->scissor[i].scissor = state[i - start_slot];
787 }
788
789 if (rctx->b.chip_class == R600 && !rctx->scissor[0].enable)
790 return;
791
792 for (i = start_slot ; i < start_slot + num_scissors; i++) {
793 rctx->scissor[i].atom.dirty = true;
794 }
795 }
796
797 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
798 unsigned size, unsigned alignment)
799 {
800 struct pipe_resource buffer;
801
802 memset(&buffer, 0, sizeof buffer);
803 buffer.target = PIPE_BUFFER;
804 buffer.format = PIPE_FORMAT_R8_UNORM;
805 buffer.bind = PIPE_BIND_CUSTOM;
806 buffer.usage = PIPE_USAGE_DEFAULT;
807 buffer.flags = 0;
808 buffer.width0 = size;
809 buffer.height0 = 1;
810 buffer.depth0 = 1;
811 buffer.array_size = 1;
812
813 return (struct r600_resource*)
814 r600_buffer_create(&rscreen->b.b, &buffer, alignment);
815 }
816
817 static void r600_init_color_surface(struct r600_context *rctx,
818 struct r600_surface *surf,
819 bool force_cmask_fmask)
820 {
821 struct r600_screen *rscreen = rctx->screen;
822 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
823 unsigned level = surf->base.u.tex.level;
824 unsigned pitch, slice;
825 unsigned color_info;
826 unsigned color_view;
827 unsigned format, swap, ntype, endian;
828 unsigned offset;
829 const struct util_format_description *desc;
830 int i;
831 bool blend_bypass = 0, blend_clamp = 1;
832
833 if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
834 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
835 rtex = rtex->flushed_depth_texture;
836 assert(rtex);
837 }
838
839 offset = rtex->surface.level[level].offset;
840 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
841 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
842 offset += rtex->surface.level[level].slice_size *
843 surf->base.u.tex.first_layer;
844 color_view = 0;
845 } else
846 color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
847 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
848
849 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
850 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
851 if (slice) {
852 slice = slice - 1;
853 }
854 color_info = 0;
855 switch (rtex->surface.level[level].mode) {
856 case RADEON_SURF_MODE_LINEAR_ALIGNED:
857 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
858 break;
859 case RADEON_SURF_MODE_1D:
860 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
861 break;
862 case RADEON_SURF_MODE_2D:
863 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
864 break;
865 case RADEON_SURF_MODE_LINEAR:
866 default:
867 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
868 break;
869 }
870
871 desc = util_format_description(surf->base.format);
872
873 for (i = 0; i < 4; i++) {
874 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
875 break;
876 }
877 }
878
879 ntype = V_0280A0_NUMBER_UNORM;
880 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
881 ntype = V_0280A0_NUMBER_SRGB;
882 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
883 if (desc->channel[i].normalized)
884 ntype = V_0280A0_NUMBER_SNORM;
885 else if (desc->channel[i].pure_integer)
886 ntype = V_0280A0_NUMBER_SINT;
887 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
888 if (desc->channel[i].normalized)
889 ntype = V_0280A0_NUMBER_UNORM;
890 else if (desc->channel[i].pure_integer)
891 ntype = V_0280A0_NUMBER_UINT;
892 }
893
894 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
895 assert(format != ~0);
896
897 swap = r600_translate_colorswap(surf->base.format);
898 assert(swap != ~0);
899
900 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
901 endian = ENDIAN_NONE;
902 } else {
903 endian = r600_colorformat_endian_swap(format);
904 }
905
906 /* set blend bypass according to docs if SINT/UINT or
907 8/24 COLOR variants */
908 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
909 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
910 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
911 blend_clamp = 0;
912 blend_bypass = 1;
913 }
914
915 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
916
917 color_info |= S_0280A0_FORMAT(format) |
918 S_0280A0_COMP_SWAP(swap) |
919 S_0280A0_BLEND_BYPASS(blend_bypass) |
920 S_0280A0_BLEND_CLAMP(blend_clamp) |
921 S_0280A0_NUMBER_TYPE(ntype) |
922 S_0280A0_ENDIAN(endian);
923
924 /* EXPORT_NORM is an optimzation that can be enabled for better
925 * performance in certain cases
926 */
927 if (rctx->b.chip_class == R600) {
928 /* EXPORT_NORM can be enabled if:
929 * - 11-bit or smaller UNORM/SNORM/SRGB
930 * - BLEND_CLAMP is enabled
931 * - BLEND_FLOAT32 is disabled
932 */
933 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
934 (desc->channel[i].size < 12 &&
935 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
936 ntype != V_0280A0_NUMBER_UINT &&
937 ntype != V_0280A0_NUMBER_SINT) &&
938 G_0280A0_BLEND_CLAMP(color_info) &&
939 !G_0280A0_BLEND_FLOAT32(color_info)) {
940 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
941 surf->export_16bpc = true;
942 }
943 } else {
944 /* EXPORT_NORM can be enabled if:
945 * - 11-bit or smaller UNORM/SNORM/SRGB
946 * - 16-bit or smaller FLOAT
947 */
948 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
949 ((desc->channel[i].size < 12 &&
950 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
951 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
952 (desc->channel[i].size < 17 &&
953 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
954 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
955 surf->export_16bpc = true;
956 }
957 }
958
959 /* These might not always be initialized to zero. */
960 surf->cb_color_base = offset >> 8;
961 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
962 S_028060_SLICE_TILE_MAX(slice);
963 surf->cb_color_fmask = surf->cb_color_base;
964 surf->cb_color_cmask = surf->cb_color_base;
965 surf->cb_color_mask = 0;
966
967 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
968 &rtex->resource.b.b);
969 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
970 &rtex->resource.b.b);
971
972 if (rtex->cmask.size) {
973 surf->cb_color_cmask = rtex->cmask.offset >> 8;
974 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
975
976 if (rtex->fmask.size) {
977 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
978 surf->cb_color_fmask = rtex->fmask.offset >> 8;
979 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
980 } else { /* cmask only */
981 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
982 }
983 } else if (force_cmask_fmask) {
984 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
985 *
986 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
987 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
988 * because it's not an MSAA buffer.
989 */
990 struct r600_cmask_info cmask;
991 struct r600_fmask_info fmask;
992
993 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
994 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
995
996 /* CMASK. */
997 if (!rctx->dummy_cmask ||
998 rctx->dummy_cmask->buf->size < cmask.size ||
999 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1000 struct pipe_transfer *transfer;
1001 void *ptr;
1002
1003 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1004 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1005
1006 /* Set the contents to 0xCC. */
1007 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1008 memset(ptr, 0xCC, cmask.size);
1009 pipe_buffer_unmap(&rctx->b.b, transfer);
1010 }
1011 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1012 &rctx->dummy_cmask->b.b);
1013
1014 /* FMASK. */
1015 if (!rctx->dummy_fmask ||
1016 rctx->dummy_fmask->buf->size < fmask.size ||
1017 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1018 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1019 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1020
1021 }
1022 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1023 &rctx->dummy_fmask->b.b);
1024
1025 /* Init the registers. */
1026 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1027 surf->cb_color_cmask = 0;
1028 surf->cb_color_fmask = 0;
1029 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1030 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1031 }
1032
1033 surf->cb_color_info = color_info;
1034 surf->cb_color_view = color_view;
1035 surf->color_initialized = true;
1036 }
1037
1038 static void r600_init_depth_surface(struct r600_context *rctx,
1039 struct r600_surface *surf)
1040 {
1041 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1042 unsigned level, pitch, slice, format, offset, array_mode;
1043
1044 level = surf->base.u.tex.level;
1045 offset = rtex->surface.level[level].offset;
1046 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1047 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1048 if (slice) {
1049 slice = slice - 1;
1050 }
1051 switch (rtex->surface.level[level].mode) {
1052 case RADEON_SURF_MODE_2D:
1053 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1054 break;
1055 case RADEON_SURF_MODE_1D:
1056 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1057 case RADEON_SURF_MODE_LINEAR:
1058 default:
1059 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1060 break;
1061 }
1062
1063 format = r600_translate_dbformat(surf->base.format);
1064 assert(format != ~0);
1065
1066 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1067 surf->db_depth_base = offset >> 8;
1068 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1069 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1070 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1071 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1072
1073 switch (surf->base.format) {
1074 case PIPE_FORMAT_Z24X8_UNORM:
1075 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1076 surf->pa_su_poly_offset_db_fmt_cntl =
1077 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1078 break;
1079 case PIPE_FORMAT_Z32_FLOAT:
1080 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1081 surf->pa_su_poly_offset_db_fmt_cntl =
1082 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1083 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1084 break;
1085 case PIPE_FORMAT_Z16_UNORM:
1086 surf->pa_su_poly_offset_db_fmt_cntl =
1087 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1088 break;
1089 default:;
1090 }
1091
1092 /* use htile only for first level */
1093 if (rtex->htile_buffer && !level) {
1094 uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile_buffer->b.b);
1095 surf->db_htile_data_base = va >> 8;
1096 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1097 S_028D24_HTILE_HEIGHT(1) |
1098 S_028D24_FULL_CACHE(1) |
1099 S_028D24_LINEAR(1);
1100 /* preload is not working properly on r6xx/r7xx */
1101 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1102 }
1103
1104 surf->depth_initialized = true;
1105 }
1106
1107 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1108 const struct pipe_framebuffer_state *state)
1109 {
1110 struct r600_context *rctx = (struct r600_context *)ctx;
1111 struct r600_surface *surf;
1112 struct r600_texture *rtex;
1113 unsigned i;
1114
1115 if (rctx->framebuffer.state.nr_cbufs) {
1116 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1117 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1118 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1119 }
1120 if (rctx->framebuffer.state.zsbuf) {
1121 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1122 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1123
1124 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1125 if (rctx->b.chip_class >= R700 && rtex->htile_buffer) {
1126 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1127 }
1128 }
1129
1130 /* Set the new state. */
1131 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1132
1133 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1134 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1135 util_format_is_pure_integer(state->cbufs[0]->format);
1136 rctx->framebuffer.compressed_cb_mask = 0;
1137 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1138 state->cbufs[0] && state->cbufs[1] &&
1139 state->cbufs[0]->texture->nr_samples > 1 &&
1140 state->cbufs[1]->texture->nr_samples <= 1;
1141 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1142
1143 /* Colorbuffers. */
1144 for (i = 0; i < state->nr_cbufs; i++) {
1145 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1146 bool force_cmask_fmask = rctx->b.chip_class == R600 &&
1147 rctx->framebuffer.is_msaa_resolve &&
1148 i == 1;
1149
1150 surf = (struct r600_surface*)state->cbufs[i];
1151 if (!surf)
1152 continue;
1153
1154 rtex = (struct r600_texture*)surf->base.texture;
1155 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1156
1157 if (!surf->color_initialized || force_cmask_fmask) {
1158 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1159 if (force_cmask_fmask) {
1160 /* re-initialize later without compression */
1161 surf->color_initialized = false;
1162 }
1163 }
1164
1165 if (!surf->export_16bpc) {
1166 rctx->framebuffer.export_16bpc = false;
1167 }
1168
1169 if (rtex->fmask.size && rtex->cmask.size) {
1170 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1171 }
1172 }
1173
1174 /* Update alpha-test state dependencies.
1175 * Alpha-test is done on the first colorbuffer only. */
1176 if (state->nr_cbufs) {
1177 bool alphatest_bypass = false;
1178
1179 surf = (struct r600_surface*)state->cbufs[0];
1180 if (surf) {
1181 alphatest_bypass = surf->alphatest_bypass;
1182 }
1183
1184 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1185 rctx->alphatest_state.bypass = alphatest_bypass;
1186 rctx->alphatest_state.atom.dirty = true;
1187 }
1188 }
1189
1190 /* ZS buffer. */
1191 if (state->zsbuf) {
1192 surf = (struct r600_surface*)state->zsbuf;
1193
1194 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1195
1196 if (!surf->depth_initialized) {
1197 r600_init_depth_surface(rctx, surf);
1198 }
1199
1200 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1201 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1202 rctx->poly_offset_state.atom.dirty = true;
1203 }
1204
1205 if (rctx->db_state.rsurf != surf) {
1206 rctx->db_state.rsurf = surf;
1207 rctx->db_state.atom.dirty = true;
1208 rctx->db_misc_state.atom.dirty = true;
1209 }
1210 } else if (rctx->db_state.rsurf) {
1211 rctx->db_state.rsurf = NULL;
1212 rctx->db_state.atom.dirty = true;
1213 rctx->db_misc_state.atom.dirty = true;
1214 }
1215
1216 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1217 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1218 rctx->cb_misc_state.atom.dirty = true;
1219 }
1220
1221 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1222 rctx->alphatest_state.bypass = false;
1223 rctx->alphatest_state.atom.dirty = true;
1224 }
1225
1226 /* Calculate the CS size. */
1227 rctx->framebuffer.atom.num_dw =
1228 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1229
1230 if (rctx->framebuffer.state.nr_cbufs) {
1231 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
1232 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
1233 }
1234 if (rctx->framebuffer.state.zsbuf) {
1235 rctx->framebuffer.atom.num_dw += 16;
1236 } else if (rctx->screen->b.info.drm_minor >= 18) {
1237 rctx->framebuffer.atom.num_dw += 3;
1238 }
1239 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1240 rctx->framebuffer.atom.num_dw += 2;
1241 }
1242
1243 rctx->framebuffer.atom.dirty = true;
1244 }
1245
1246 static uint32_t sample_locs_2x[] = {
1247 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1248 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1249 };
1250 static unsigned max_dist_2x = 4;
1251
1252 static uint32_t sample_locs_4x[] = {
1253 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1254 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1255 };
1256 static unsigned max_dist_4x = 6;
1257 static uint32_t sample_locs_8x[] = {
1258 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1259 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1260 };
1261 static unsigned max_dist_8x = 7;
1262
1263 static void r600_get_sample_position(struct pipe_context *ctx,
1264 unsigned sample_count,
1265 unsigned sample_index,
1266 float *out_value)
1267 {
1268 int offset, index;
1269 struct {
1270 int idx:4;
1271 } val;
1272 switch (sample_count) {
1273 case 1:
1274 default:
1275 out_value[0] = out_value[1] = 0.5;
1276 break;
1277 case 2:
1278 offset = 4 * (sample_index * 2);
1279 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1280 out_value[0] = (float)(val.idx + 8) / 16.0f;
1281 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1282 out_value[1] = (float)(val.idx + 8) / 16.0f;
1283 break;
1284 case 4:
1285 offset = 4 * (sample_index * 2);
1286 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1287 out_value[0] = (float)(val.idx + 8) / 16.0f;
1288 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1289 out_value[1] = (float)(val.idx + 8) / 16.0f;
1290 break;
1291 case 8:
1292 offset = 4 * (sample_index % 4 * 2);
1293 index = (sample_index / 4);
1294 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1295 out_value[0] = (float)(val.idx + 8) / 16.0f;
1296 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1297 out_value[1] = (float)(val.idx + 8) / 16.0f;
1298 break;
1299 }
1300 }
1301
1302 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1303 {
1304 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1305 unsigned max_dist = 0;
1306
1307 if (rctx->b.family == CHIP_R600) {
1308 switch (nr_samples) {
1309 default:
1310 nr_samples = 0;
1311 break;
1312 case 2:
1313 r600_write_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1314 max_dist = max_dist_2x;
1315 break;
1316 case 4:
1317 r600_write_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1318 max_dist = max_dist_4x;
1319 break;
1320 case 8:
1321 r600_write_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1322 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1323 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1324 max_dist = max_dist_8x;
1325 break;
1326 }
1327 } else {
1328 switch (nr_samples) {
1329 default:
1330 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1331 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1332 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1333 nr_samples = 0;
1334 break;
1335 case 2:
1336 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1337 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1338 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1339 max_dist = max_dist_2x;
1340 break;
1341 case 4:
1342 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1343 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1344 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1345 max_dist = max_dist_4x;
1346 break;
1347 case 8:
1348 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1349 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1350 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1351 max_dist = max_dist_8x;
1352 break;
1353 }
1354 }
1355
1356 if (nr_samples > 1) {
1357 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1358 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1359 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1360 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1361 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1362 } else {
1363 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1364 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1365 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1366 }
1367 }
1368
1369 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1370 {
1371 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1372 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1373 unsigned nr_cbufs = state->nr_cbufs;
1374 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1375 unsigned i, sbu = 0;
1376
1377 /* Colorbuffers. */
1378 r600_write_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1379 for (i = 0; i < nr_cbufs; i++) {
1380 radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0);
1381 }
1382 /* set CB_COLOR1_INFO for possible dual-src blending */
1383 if (i == 1 && cb[0]) {
1384 radeon_emit(cs, cb[0]->cb_color_info);
1385 i++;
1386 }
1387 for (; i < 8; i++) {
1388 radeon_emit(cs, 0);
1389 }
1390
1391 if (nr_cbufs) {
1392 for (i = 0; i < nr_cbufs; i++) {
1393 unsigned reloc;
1394
1395 if (!cb[i])
1396 continue;
1397
1398 /* COLOR_BASE */
1399 r600_write_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1400
1401 reloc = r600_context_bo_reloc(&rctx->b,
1402 &rctx->b.rings.gfx,
1403 (struct r600_resource*)cb[i]->base.texture,
1404 RADEON_USAGE_READWRITE,
1405 cb[i]->base.texture->nr_samples > 1 ?
1406 RADEON_PRIO_COLOR_BUFFER_MSAA :
1407 RADEON_PRIO_COLOR_BUFFER);
1408 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1409 radeon_emit(cs, reloc);
1410
1411 /* FMASK */
1412 r600_write_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1413
1414 reloc = r600_context_bo_reloc(&rctx->b,
1415 &rctx->b.rings.gfx,
1416 cb[i]->cb_buffer_fmask,
1417 RADEON_USAGE_READWRITE,
1418 cb[i]->base.texture->nr_samples > 1 ?
1419 RADEON_PRIO_COLOR_BUFFER_MSAA :
1420 RADEON_PRIO_COLOR_BUFFER);
1421 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1422 radeon_emit(cs, reloc);
1423
1424 /* CMASK */
1425 r600_write_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1426
1427 reloc = r600_context_bo_reloc(&rctx->b,
1428 &rctx->b.rings.gfx,
1429 cb[i]->cb_buffer_cmask,
1430 RADEON_USAGE_READWRITE,
1431 cb[i]->base.texture->nr_samples > 1 ?
1432 RADEON_PRIO_COLOR_BUFFER_MSAA :
1433 RADEON_PRIO_COLOR_BUFFER);
1434 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1435 radeon_emit(cs, reloc);
1436 }
1437
1438 r600_write_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1439 for (i = 0; i < nr_cbufs; i++) {
1440 radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0);
1441 }
1442
1443 r600_write_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1444 for (i = 0; i < nr_cbufs; i++) {
1445 radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0);
1446 }
1447
1448 r600_write_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1449 for (i = 0; i < nr_cbufs; i++) {
1450 radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0);
1451 }
1452
1453 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1454 }
1455
1456 /* SURFACE_BASE_UPDATE */
1457 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1458 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1459 radeon_emit(cs, sbu);
1460 sbu = 0;
1461 }
1462
1463 /* Zbuffer. */
1464 if (state->zsbuf) {
1465 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1466 unsigned reloc = r600_context_bo_reloc(&rctx->b,
1467 &rctx->b.rings.gfx,
1468 (struct r600_resource*)state->zsbuf->texture,
1469 RADEON_USAGE_READWRITE,
1470 surf->base.texture->nr_samples > 1 ?
1471 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1472 RADEON_PRIO_DEPTH_BUFFER);
1473
1474 r600_write_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1475 surf->pa_su_poly_offset_db_fmt_cntl);
1476
1477 r600_write_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1478 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1479 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1480 r600_write_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1481 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1482 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1483
1484 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1485 radeon_emit(cs, reloc);
1486
1487 r600_write_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1488
1489 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1490 } else if (rctx->screen->b.info.drm_minor >= 18) {
1491 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1492 * Older kernels are out of luck. */
1493 r600_write_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1494 }
1495
1496 /* SURFACE_BASE_UPDATE */
1497 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1498 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1499 radeon_emit(cs, sbu);
1500 sbu = 0;
1501 }
1502
1503 /* Framebuffer dimensions. */
1504 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1505 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1506 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1507 radeon_emit(cs, S_028244_BR_X(state->width) |
1508 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1509
1510 if (rctx->framebuffer.is_msaa_resolve) {
1511 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1512 } else {
1513 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1514 * will assure that the alpha-test will work even if there is
1515 * no colorbuffer bound. */
1516 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1517 (1ull << MAX2(nr_cbufs, 1)) - 1);
1518 }
1519
1520 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1521 }
1522
1523 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1524 {
1525 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1526 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1527
1528 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1529 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1530 if (rctx->b.chip_class == R600) {
1531 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1532 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1533 } else {
1534 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1535 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1536 }
1537 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1538 } else {
1539 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1540 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1541 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1542
1543 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1544 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1545 /* Always enable the first color output to make sure alpha-test works even without one. */
1546 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1547 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1548 a->cb_color_control |
1549 S_028808_MULTIWRITE_ENABLE(multiwrite));
1550 }
1551 }
1552
1553 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1554 {
1555 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1556 struct r600_db_state *a = (struct r600_db_state*)atom;
1557
1558 if (a->rsurf && a->rsurf->db_htile_surface) {
1559 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1560 unsigned reloc_idx;
1561
1562 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1563 r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1564 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1565 reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer,
1566 RADEON_USAGE_READWRITE, RADEON_PRIO_DEPTH_META);
1567 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1568 cs->buf[cs->cdw++] = reloc_idx;
1569 } else {
1570 r600_write_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1571 }
1572 }
1573
1574 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1575 {
1576 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1577 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1578 unsigned db_render_control = 0;
1579 unsigned db_render_override =
1580 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1581 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1582
1583 if (a->occlusion_query_enabled) {
1584 if (rctx->b.chip_class >= R700) {
1585 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1586 }
1587 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1588 }
1589 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
1590 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1591 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1592 /* This is to fix a lockup when hyperz and alpha test are enabled at
1593 * the same time somehow GPU get confuse on which order to pick for
1594 * z test
1595 */
1596 if (rctx->alphatest_state.sx_alpha_test_control) {
1597 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
1598 }
1599 } else {
1600 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1601 }
1602 if (a->flush_depthstencil_through_cb) {
1603 assert(a->copy_depth || a->copy_stencil);
1604
1605 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1606 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1607 S_028D0C_COPY_CENTROID(1) |
1608 S_028D0C_COPY_SAMPLE(a->copy_sample);
1609 } else if (a->flush_depthstencil_in_place) {
1610 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(1) |
1611 S_028D0C_STENCIL_COMPRESS_DISABLE(1);
1612 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1613 }
1614 if (a->htile_clear) {
1615 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1616 }
1617
1618 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1619 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1620 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1621 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1622 }
1623
1624 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1625 {
1626 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1627 struct r600_config_state *a = (struct r600_config_state*)atom;
1628
1629 r600_write_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1630 r600_write_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
1631 }
1632
1633 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1634 {
1635 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1636 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1637
1638 while (dirty_mask) {
1639 struct pipe_vertex_buffer *vb;
1640 struct r600_resource *rbuffer;
1641 unsigned offset;
1642 unsigned buffer_index = u_bit_scan(&dirty_mask);
1643
1644 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1645 rbuffer = (struct r600_resource*)vb->buffer;
1646 assert(rbuffer);
1647
1648 offset = vb->buffer_offset;
1649
1650 /* fetch resources start at index 320 */
1651 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1652 radeon_emit(cs, (320 + buffer_index) * 7);
1653 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1654 radeon_emit(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1655 radeon_emit(cs, /* RESOURCEi_WORD2 */
1656 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1657 S_038008_STRIDE(vb->stride));
1658 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1659 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1660 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1661 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1662
1663 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1664 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1665 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1666 }
1667 }
1668
1669 static void r600_emit_constant_buffers(struct r600_context *rctx,
1670 struct r600_constbuf_state *state,
1671 unsigned buffer_id_base,
1672 unsigned reg_alu_constbuf_size,
1673 unsigned reg_alu_const_cache)
1674 {
1675 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1676 uint32_t dirty_mask = state->dirty_mask;
1677
1678 while (dirty_mask) {
1679 struct pipe_constant_buffer *cb;
1680 struct r600_resource *rbuffer;
1681 unsigned offset;
1682 unsigned buffer_index = ffs(dirty_mask) - 1;
1683 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1684 cb = &state->cb[buffer_index];
1685 rbuffer = (struct r600_resource*)cb->buffer;
1686 assert(rbuffer);
1687
1688 offset = cb->buffer_offset;
1689
1690 if (!gs_ring_buffer) {
1691 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1692 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1693 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1694 }
1695
1696 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1697 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1698 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1699
1700 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1701 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
1702 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1703 radeon_emit(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1704 radeon_emit(cs, /* RESOURCEi_WORD2 */
1705 S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1706 S_038008_STRIDE(gs_ring_buffer ? 4 : 16));
1707 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1708 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1709 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1710 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1711
1712 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1713 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1714 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
1715
1716 dirty_mask &= ~(1 << buffer_index);
1717 }
1718 state->dirty_mask = 0;
1719 }
1720
1721 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1722 {
1723 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 160,
1724 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1725 R_028980_ALU_CONST_CACHE_VS_0);
1726 }
1727
1728 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1729 {
1730 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
1731 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1732 R_0289C0_ALU_CONST_CACHE_GS_0);
1733 }
1734
1735 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1736 {
1737 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
1738 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1739 R_028940_ALU_CONST_CACHE_PS_0);
1740 }
1741
1742 static void r600_emit_sampler_views(struct r600_context *rctx,
1743 struct r600_samplerview_state *state,
1744 unsigned resource_id_base)
1745 {
1746 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1747 uint32_t dirty_mask = state->dirty_mask;
1748
1749 while (dirty_mask) {
1750 struct r600_pipe_sampler_view *rview;
1751 unsigned resource_index = u_bit_scan(&dirty_mask);
1752 unsigned reloc;
1753
1754 rview = state->views[resource_index];
1755 assert(rview);
1756
1757 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1758 radeon_emit(cs, (resource_id_base + resource_index) * 7);
1759 radeon_emit_array(cs, rview->tex_resource_words, 7);
1760
1761 reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->tex_resource,
1762 RADEON_USAGE_READ,
1763 rview->tex_resource->b.b.nr_samples > 1 ?
1764 RADEON_PRIO_SHADER_TEXTURE_MSAA :
1765 RADEON_PRIO_SHADER_TEXTURE_RO);
1766 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1767 radeon_emit(cs, reloc);
1768 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1769 radeon_emit(cs, reloc);
1770 }
1771 state->dirty_mask = 0;
1772 }
1773
1774 /* Resource IDs:
1775 * PS: 0 .. +160
1776 * VS: 160 .. +160
1777 * FS: 320 .. +16
1778 * GS: 336 .. +160
1779 */
1780
1781 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1782 {
1783 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 160 + R600_MAX_CONST_BUFFERS);
1784 }
1785
1786 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1787 {
1788 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
1789 }
1790
1791 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1792 {
1793 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
1794 }
1795
1796 static void r600_emit_sampler_states(struct r600_context *rctx,
1797 struct r600_textures_info *texinfo,
1798 unsigned resource_id_base,
1799 unsigned border_color_reg)
1800 {
1801 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1802 uint32_t dirty_mask = texinfo->states.dirty_mask;
1803
1804 while (dirty_mask) {
1805 struct r600_pipe_sampler_state *rstate;
1806 struct r600_pipe_sampler_view *rview;
1807 unsigned i = u_bit_scan(&dirty_mask);
1808
1809 rstate = texinfo->states.states[i];
1810 assert(rstate);
1811 rview = texinfo->views.views[i];
1812
1813 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1814 * filtering between layers.
1815 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1816 */
1817 if (rview) {
1818 enum pipe_texture_target target = rview->base.texture->target;
1819 if (target == PIPE_TEXTURE_1D_ARRAY ||
1820 target == PIPE_TEXTURE_2D_ARRAY) {
1821 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1822 texinfo->is_array_sampler[i] = true;
1823 } else {
1824 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1825 texinfo->is_array_sampler[i] = false;
1826 }
1827 }
1828
1829 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1830 radeon_emit(cs, (resource_id_base + i) * 3);
1831 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
1832
1833 if (rstate->border_color_use) {
1834 unsigned offset;
1835
1836 offset = border_color_reg;
1837 offset += i * 16;
1838 r600_write_config_reg_seq(cs, offset, 4);
1839 radeon_emit_array(cs, rstate->border_color.ui, 4);
1840 }
1841 }
1842 texinfo->states.dirty_mask = 0;
1843 }
1844
1845 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1846 {
1847 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1848 }
1849
1850 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1851 {
1852 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1853 }
1854
1855 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1856 {
1857 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1858 }
1859
1860 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1861 {
1862 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1863 unsigned tmp;
1864
1865 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1866 S_009508_SYNC_GRADIENT(1) |
1867 S_009508_SYNC_WALKER(1) |
1868 S_009508_SYNC_ALIGNER(1);
1869 if (!rctx->seamless_cube_map.enabled) {
1870 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1871 }
1872 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1873 }
1874
1875 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1876 {
1877 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1878 uint8_t mask = s->sample_mask;
1879
1880 r600_write_context_reg(rctx->b.rings.gfx.cs, R_028C48_PA_SC_AA_MASK,
1881 mask | (mask << 8) | (mask << 16) | (mask << 24));
1882 }
1883
1884 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
1885 {
1886 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1887 struct r600_cso_state *state = (struct r600_cso_state*)a;
1888 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
1889
1890 r600_write_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
1891 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1892 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->buffer,
1893 RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA));
1894 }
1895
1896 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
1897 {
1898 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1899 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
1900
1901 uint32_t v2 = 0, primid = 0;
1902
1903 if (state->geom_enable) {
1904 uint32_t cut_val;
1905
1906 if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 128)
1907 cut_val = V_028A40_GS_CUT_128;
1908 else if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 256)
1909 cut_val = V_028A40_GS_CUT_256;
1910 else if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 512)
1911 cut_val = V_028A40_GS_CUT_512;
1912 else
1913 cut_val = V_028A40_GS_CUT_1024;
1914
1915 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1916 S_028A40_CUT_MODE(cut_val);
1917
1918 if (rctx->gs_shader->current->shader.gs_prim_id_input)
1919 primid = 1;
1920 }
1921
1922 r600_write_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
1923 r600_write_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
1924 }
1925
1926 static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
1927 {
1928 struct pipe_screen *screen = rctx->b.b.screen;
1929 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1930 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
1931 struct r600_resource *rbuffer;
1932
1933 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1934 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1935 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1936
1937 if (state->enable) {
1938 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
1939 r600_write_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
1940 (r600_resource_va(screen, &rbuffer->b.b)) >> 8);
1941 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1942 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1943 RADEON_USAGE_READWRITE,
1944 RADEON_PRIO_SHADER_RESOURCE_RW));
1945 r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
1946 state->esgs_ring.buffer_size >> 8);
1947
1948 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
1949 r600_write_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
1950 (r600_resource_va(screen, &rbuffer->b.b)) >> 8);
1951 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1952 radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
1953 RADEON_USAGE_READWRITE,
1954 RADEON_PRIO_SHADER_RESOURCE_RW));
1955 r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
1956 state->gsvs_ring.buffer_size >> 8);
1957 } else {
1958 r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
1959 r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
1960 }
1961
1962 r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1963 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1964 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1965 }
1966
1967 /* Adjust GPR allocation on R6xx/R7xx */
1968 bool r600_adjust_gprs(struct r600_context *rctx)
1969 {
1970 unsigned num_ps_gprs = rctx->ps_shader->current->shader.bc.ngpr;
1971 unsigned num_vs_gprs, num_es_gprs, num_gs_gprs;
1972 unsigned new_num_ps_gprs = num_ps_gprs;
1973 unsigned new_num_vs_gprs, new_num_es_gprs, new_num_gs_gprs;
1974 unsigned cur_num_ps_gprs = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
1975 unsigned cur_num_vs_gprs = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
1976 unsigned cur_num_gs_gprs = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
1977 unsigned cur_num_es_gprs = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
1978 unsigned def_num_ps_gprs = rctx->default_ps_gprs;
1979 unsigned def_num_vs_gprs = rctx->default_vs_gprs;
1980 unsigned def_num_gs_gprs = 0;
1981 unsigned def_num_es_gprs = 0;
1982 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
1983 /* hardware will reserve twice num_clause_temp_gprs */
1984 unsigned max_gprs = def_num_gs_gprs + def_num_es_gprs + def_num_ps_gprs + def_num_vs_gprs + def_num_clause_temp_gprs * 2;
1985 unsigned tmp, tmp2;
1986
1987 if (rctx->gs_shader) {
1988 num_es_gprs = rctx->vs_shader->current->shader.bc.ngpr;
1989 num_gs_gprs = rctx->gs_shader->current->shader.bc.ngpr;
1990 num_vs_gprs = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
1991 } else {
1992 num_es_gprs = 0;
1993 num_gs_gprs = 0;
1994 num_vs_gprs = rctx->vs_shader->current->shader.bc.ngpr;
1995 }
1996 new_num_vs_gprs = num_vs_gprs;
1997 new_num_es_gprs = num_es_gprs;
1998 new_num_gs_gprs = num_gs_gprs;
1999
2000 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2001 if (new_num_ps_gprs > cur_num_ps_gprs || new_num_vs_gprs > cur_num_vs_gprs ||
2002 new_num_es_gprs > cur_num_es_gprs || new_num_gs_gprs > cur_num_gs_gprs) {
2003 /* try to use switch back to default */
2004 if (new_num_ps_gprs > def_num_ps_gprs || new_num_vs_gprs > def_num_vs_gprs ||
2005 new_num_gs_gprs > def_num_gs_gprs || new_num_es_gprs > def_num_es_gprs) {
2006 /* always privilege vs stage so that at worst we have the
2007 * pixel stage producing wrong output (not the vertex
2008 * stage) */
2009 new_num_ps_gprs = max_gprs - ((new_num_vs_gprs - new_num_es_gprs - new_num_gs_gprs) + def_num_clause_temp_gprs * 2);
2010 new_num_vs_gprs = num_vs_gprs;
2011 new_num_gs_gprs = num_gs_gprs;
2012 new_num_es_gprs = num_es_gprs;
2013 } else {
2014 new_num_ps_gprs = def_num_ps_gprs;
2015 new_num_vs_gprs = def_num_vs_gprs;
2016 new_num_es_gprs = def_num_es_gprs;
2017 new_num_gs_gprs = def_num_gs_gprs;
2018 }
2019 } else {
2020 return true;
2021 }
2022
2023 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2024 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2025 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2026 * it will lockup. So in this case just discard the draw command
2027 * and don't change the current gprs repartitions.
2028 */
2029 if (num_ps_gprs > new_num_ps_gprs || num_vs_gprs > new_num_vs_gprs ||
2030 num_gs_gprs > new_num_gs_gprs || num_es_gprs > new_num_es_gprs) {
2031 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2032 "for a combined maximum of %d\n",
2033 num_ps_gprs, num_vs_gprs, num_es_gprs, num_gs_gprs, max_gprs);
2034 return false;
2035 }
2036
2037 /* in some case we endup recomputing the current value */
2038 tmp = S_008C04_NUM_PS_GPRS(new_num_ps_gprs) |
2039 S_008C04_NUM_VS_GPRS(new_num_vs_gprs) |
2040 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2041
2042 tmp2 = S_008C08_NUM_ES_GPRS(new_num_es_gprs) |
2043 S_008C08_NUM_GS_GPRS(new_num_gs_gprs);
2044 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2045 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2046 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2;
2047 rctx->config_state.atom.dirty = true;
2048 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2049 }
2050 return true;
2051 }
2052
2053 void r600_init_atom_start_cs(struct r600_context *rctx)
2054 {
2055 int ps_prio;
2056 int vs_prio;
2057 int gs_prio;
2058 int es_prio;
2059 int num_ps_gprs;
2060 int num_vs_gprs;
2061 int num_gs_gprs;
2062 int num_es_gprs;
2063 int num_temp_gprs;
2064 int num_ps_threads;
2065 int num_vs_threads;
2066 int num_gs_threads;
2067 int num_es_threads;
2068 int num_ps_stack_entries;
2069 int num_vs_stack_entries;
2070 int num_gs_stack_entries;
2071 int num_es_stack_entries;
2072 enum radeon_family family;
2073 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2074 uint32_t tmp;
2075
2076 r600_init_command_buffer(cb, 256);
2077
2078 /* R6xx requires this packet at the start of each command buffer */
2079 if (rctx->b.chip_class == R600) {
2080 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2081 r600_store_value(cb, 0);
2082 }
2083 /* All asics require this one */
2084 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2085 r600_store_value(cb, 0x80000000);
2086 r600_store_value(cb, 0x80000000);
2087
2088 /* We're setting config registers here. */
2089 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2090 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2091
2092 family = rctx->b.family;
2093 ps_prio = 0;
2094 vs_prio = 1;
2095 gs_prio = 2;
2096 es_prio = 3;
2097 switch (family) {
2098 case CHIP_R600:
2099 num_ps_gprs = 192;
2100 num_vs_gprs = 56;
2101 num_temp_gprs = 4;
2102 num_gs_gprs = 0;
2103 num_es_gprs = 0;
2104 num_ps_threads = 136;
2105 num_vs_threads = 48;
2106 num_gs_threads = 4;
2107 num_es_threads = 4;
2108 num_ps_stack_entries = 128;
2109 num_vs_stack_entries = 128;
2110 num_gs_stack_entries = 0;
2111 num_es_stack_entries = 0;
2112 break;
2113 case CHIP_RV630:
2114 case CHIP_RV635:
2115 num_ps_gprs = 84;
2116 num_vs_gprs = 36;
2117 num_temp_gprs = 4;
2118 num_gs_gprs = 0;
2119 num_es_gprs = 0;
2120 num_ps_threads = 144;
2121 num_vs_threads = 40;
2122 num_gs_threads = 4;
2123 num_es_threads = 4;
2124 num_ps_stack_entries = 40;
2125 num_vs_stack_entries = 40;
2126 num_gs_stack_entries = 32;
2127 num_es_stack_entries = 16;
2128 break;
2129 case CHIP_RV610:
2130 case CHIP_RV620:
2131 case CHIP_RS780:
2132 case CHIP_RS880:
2133 default:
2134 num_ps_gprs = 84;
2135 num_vs_gprs = 36;
2136 num_temp_gprs = 4;
2137 num_gs_gprs = 0;
2138 num_es_gprs = 0;
2139 num_ps_threads = 136;
2140 num_vs_threads = 48;
2141 num_gs_threads = 4;
2142 num_es_threads = 4;
2143 num_ps_stack_entries = 40;
2144 num_vs_stack_entries = 40;
2145 num_gs_stack_entries = 32;
2146 num_es_stack_entries = 16;
2147 break;
2148 case CHIP_RV670:
2149 num_ps_gprs = 144;
2150 num_vs_gprs = 40;
2151 num_temp_gprs = 4;
2152 num_gs_gprs = 0;
2153 num_es_gprs = 0;
2154 num_ps_threads = 136;
2155 num_vs_threads = 48;
2156 num_gs_threads = 4;
2157 num_es_threads = 4;
2158 num_ps_stack_entries = 40;
2159 num_vs_stack_entries = 40;
2160 num_gs_stack_entries = 32;
2161 num_es_stack_entries = 16;
2162 break;
2163 case CHIP_RV770:
2164 num_ps_gprs = 130;
2165 num_vs_gprs = 56;
2166 num_temp_gprs = 4;
2167 num_gs_gprs = 31;
2168 num_es_gprs = 31;
2169 num_ps_threads = 180;
2170 num_vs_threads = 60;
2171 num_gs_threads = 4;
2172 num_es_threads = 4;
2173 num_ps_stack_entries = 128;
2174 num_vs_stack_entries = 128;
2175 num_gs_stack_entries = 128;
2176 num_es_stack_entries = 128;
2177 break;
2178 case CHIP_RV730:
2179 case CHIP_RV740:
2180 num_ps_gprs = 84;
2181 num_vs_gprs = 36;
2182 num_temp_gprs = 4;
2183 num_gs_gprs = 0;
2184 num_es_gprs = 0;
2185 num_ps_threads = 180;
2186 num_vs_threads = 60;
2187 num_gs_threads = 4;
2188 num_es_threads = 4;
2189 num_ps_stack_entries = 128;
2190 num_vs_stack_entries = 128;
2191 num_gs_stack_entries = 0;
2192 num_es_stack_entries = 0;
2193 break;
2194 case CHIP_RV710:
2195 num_ps_gprs = 192;
2196 num_vs_gprs = 56;
2197 num_temp_gprs = 4;
2198 num_gs_gprs = 0;
2199 num_es_gprs = 0;
2200 num_ps_threads = 136;
2201 num_vs_threads = 48;
2202 num_gs_threads = 4;
2203 num_es_threads = 4;
2204 num_ps_stack_entries = 128;
2205 num_vs_stack_entries = 128;
2206 num_gs_stack_entries = 0;
2207 num_es_stack_entries = 0;
2208 break;
2209 }
2210
2211 rctx->default_ps_gprs = num_ps_gprs;
2212 rctx->default_vs_gprs = num_vs_gprs;
2213 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2214
2215 /* SQ_CONFIG */
2216 tmp = 0;
2217 switch (family) {
2218 case CHIP_RV610:
2219 case CHIP_RV620:
2220 case CHIP_RS780:
2221 case CHIP_RS880:
2222 case CHIP_RV710:
2223 break;
2224 default:
2225 tmp |= S_008C00_VC_ENABLE(1);
2226 break;
2227 }
2228 tmp |= S_008C00_DX9_CONSTS(0);
2229 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2230 tmp |= S_008C00_PS_PRIO(ps_prio);
2231 tmp |= S_008C00_VS_PRIO(vs_prio);
2232 tmp |= S_008C00_GS_PRIO(gs_prio);
2233 tmp |= S_008C00_ES_PRIO(es_prio);
2234 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2235
2236 /* SQ_GPR_RESOURCE_MGMT_2 */
2237 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2238 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2239 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2240 r600_store_value(cb, tmp);
2241
2242 /* SQ_THREAD_RESOURCE_MGMT */
2243 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2244 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2245 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2246 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2247 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2248
2249 /* SQ_STACK_RESOURCE_MGMT_1 */
2250 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2251 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2252 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2253
2254 /* SQ_STACK_RESOURCE_MGMT_2 */
2255 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2256 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2257 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2258
2259 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2260
2261 if (rctx->b.chip_class >= R700) {
2262 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2263 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2264 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2265 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2266 } else {
2267 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2268 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2269 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2270 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2271 }
2272 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2273 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2274 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2275 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2276 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2277 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2278 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2279 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2280 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2281 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2282
2283 /* to avoid GPU doing any preloading of constant from random address */
2284 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2285 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2286 r600_store_value(cb, 0);
2287 r600_store_value(cb, 0);
2288 r600_store_value(cb, 0);
2289 r600_store_value(cb, 0);
2290 r600_store_value(cb, 0);
2291 r600_store_value(cb, 0);
2292 r600_store_value(cb, 0);
2293 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2294 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2295 r600_store_value(cb, 0);
2296 r600_store_value(cb, 0);
2297 r600_store_value(cb, 0);
2298 r600_store_value(cb, 0);
2299 r600_store_value(cb, 0);
2300 r600_store_value(cb, 0);
2301 r600_store_value(cb, 0);
2302
2303 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2304 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2305 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2306 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2307 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2308 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2309 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2310 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2311 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2312 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2313 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2314 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2315 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2316 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2317
2318 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2319 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2320 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2321
2322 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2323 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2324 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2325
2326 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2327
2328 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2329
2330 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2331
2332 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2333 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2334 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2335 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2336
2337 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2338 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2339 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2340 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2341
2342 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2343 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2344
2345 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2346 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2347 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2348 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2349 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2350
2351 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * 16);
2352 for (tmp = 0; tmp < 16; tmp++) {
2353 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2354 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2355 }
2356
2357 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2358
2359 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2360 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2361
2362 if (rctx->b.chip_class >= R700) {
2363 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2364 }
2365
2366 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2367 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2368 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2369 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2370 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2371
2372 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2373 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2374 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2375
2376 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2377 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2378 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2379
2380 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5);
2381 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2382 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2383 r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2384 r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2385 r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2386
2387 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2388
2389 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2390 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2391 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2392
2393 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2394
2395 if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
2396 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2397 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2398 if (rctx->screen->b.has_streamout) {
2399 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2400 }
2401
2402 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2403 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2404 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF);
2405 }
2406
2407 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2408 {
2409 struct r600_context *rctx = (struct r600_context *)ctx;
2410 struct r600_command_buffer *cb = &shader->command_buffer;
2411 struct r600_shader *rshader = &shader->shader;
2412 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2413 int pos_index = -1, face_index = -1;
2414 unsigned tmp, sid, ufi = 0;
2415 int need_linear = 0;
2416 unsigned z_export = 0, stencil_export = 0;
2417 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2418
2419 if (!cb->buf) {
2420 r600_init_command_buffer(cb, 64);
2421 } else {
2422 cb->num_dw = 0;
2423 }
2424
2425 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2426 for (i = 0; i < rshader->ninput; i++) {
2427 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2428 pos_index = i;
2429 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2430 face_index = i;
2431
2432 sid = rshader->input[i].spi_sid;
2433
2434 tmp = S_028644_SEMANTIC(sid);
2435
2436 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2437 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2438 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2439 rctx->rasterizer && rctx->rasterizer->flatshade))
2440 tmp |= S_028644_FLAT_SHADE(1);
2441
2442 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2443 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2444 tmp |= S_028644_PT_SPRITE_TEX(1);
2445 }
2446
2447 if (rshader->input[i].centroid)
2448 tmp |= S_028644_SEL_CENTROID(1);
2449
2450 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2451 need_linear = 1;
2452 tmp |= S_028644_SEL_LINEAR(1);
2453 }
2454
2455 r600_store_value(cb, tmp);
2456 }
2457
2458 db_shader_control = 0;
2459 for (i = 0; i < rshader->noutput; i++) {
2460 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2461 z_export = 1;
2462 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2463 stencil_export = 1;
2464 }
2465 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2466 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2467 if (rshader->uses_kill)
2468 db_shader_control |= S_02880C_KILL_ENABLE(1);
2469
2470 exports_ps = 0;
2471 for (i = 0; i < rshader->noutput; i++) {
2472 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2473 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2474 exports_ps |= 1;
2475 }
2476 }
2477 num_cout = rshader->nr_ps_color_exports;
2478 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2479 if (!exports_ps) {
2480 /* always at least export 1 component per pixel */
2481 exports_ps = 2;
2482 }
2483
2484 shader->nr_ps_color_outputs = num_cout;
2485
2486 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2487 S_0286CC_PERSP_GRADIENT_ENA(1)|
2488 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2489 spi_input_z = 0;
2490 if (pos_index != -1) {
2491 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2492 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2493 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2494 S_0286CC_BARYC_SAMPLE_CNTL(1));
2495 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2496 }
2497
2498 spi_ps_in_control_1 = 0;
2499 if (face_index != -1) {
2500 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2501 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2502 }
2503
2504 /* HW bug in original R600 */
2505 if (rctx->b.family == CHIP_R600)
2506 ufi = 1;
2507
2508 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2509 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2510 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2511
2512 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2513
2514 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2515 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2516 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2517 S_028850_STACK_SIZE(rshader->bc.nstack) |
2518 S_028850_UNCACHED_FIRST_INST(ufi));
2519 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2520
2521 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2522 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2523
2524 /* only set some bits here, the other bits are set in the dsa state */
2525 shader->db_shader_control = db_shader_control;
2526 shader->ps_depth_export = z_export | stencil_export;
2527
2528 shader->sprite_coord_enable = sprite_coord_enable;
2529 if (rctx->rasterizer)
2530 shader->flatshade = rctx->rasterizer->flatshade;
2531 }
2532
2533 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2534 {
2535 struct r600_command_buffer *cb = &shader->command_buffer;
2536 struct r600_shader *rshader = &shader->shader;
2537 unsigned spi_vs_out_id[10] = {};
2538 unsigned i, tmp, nparams = 0;
2539
2540 for (i = 0; i < rshader->noutput; i++) {
2541 if (rshader->output[i].spi_sid) {
2542 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2543 spi_vs_out_id[nparams / 4] |= tmp;
2544 nparams++;
2545 }
2546 }
2547
2548 r600_init_command_buffer(cb, 32);
2549
2550 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2551 for (i = 0; i < 10; i++) {
2552 r600_store_value(cb, spi_vs_out_id[i]);
2553 }
2554
2555 /* Certain attributes (position, psize, etc.) don't count as params.
2556 * VS is required to export at least one param and r600_shader_from_tgsi()
2557 * takes care of adding a dummy export.
2558 */
2559 if (nparams < 1)
2560 nparams = 1;
2561
2562 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2563 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2564 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2565 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2566 S_028868_STACK_SIZE(rshader->bc.nstack));
2567 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2568 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2569
2570 shader->pa_cl_vs_out_cntl =
2571 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2572 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2573 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2574 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
2575 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
2576 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) |
2577 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport);
2578 }
2579
2580 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2581 {
2582 struct r600_context *rctx = (struct r600_context *)ctx;
2583 struct r600_command_buffer *cb = &shader->command_buffer;
2584 struct r600_shader *rshader = &shader->shader;
2585 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
2586 unsigned gsvs_itemsize =
2587 (cp_shader->ring_item_size * rshader->gs_max_out_vertices) >> 2;
2588
2589 r600_init_command_buffer(cb, 64);
2590
2591 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2592 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
2593
2594 if (rctx->b.chip_class >= R700) {
2595 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
2596 S_028B38_MAX_VERT_OUT(rshader->gs_max_out_vertices));
2597 }
2598 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
2599 r600_conv_prim_to_gs_out(rshader->gs_output_prim));
2600
2601 r600_store_context_reg_seq(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE, 4);
2602 r600_store_value(cb, cp_shader->ring_item_size >> 2);
2603 r600_store_value(cb, 0);
2604 r600_store_value(cb, 0);
2605 r600_store_value(cb, 0);
2606
2607 r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
2608 (rshader->ring_item_size) >> 2);
2609
2610 r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE,
2611 gsvs_itemsize);
2612
2613 /* FIXME calculate these values somehow ??? */
2614 r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2);
2615 r600_store_value(cb, 0x80); /* GS_PER_ES */
2616 r600_store_value(cb, 0x100); /* ES_PER_GS */
2617 r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1);
2618 r600_store_value(cb, 0x2); /* GS_PER_VS */
2619
2620 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS,
2621 S_02887C_NUM_GPRS(rshader->bc.ngpr) |
2622 S_02887C_STACK_SIZE(rshader->bc.nstack));
2623 r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS,
2624 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
2625 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2626 }
2627
2628 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2629 {
2630 struct r600_command_buffer *cb = &shader->command_buffer;
2631 struct r600_shader *rshader = &shader->shader;
2632
2633 r600_init_command_buffer(cb, 32);
2634
2635 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
2636 S_028890_NUM_GPRS(rshader->bc.ngpr) |
2637 S_028890_STACK_SIZE(rshader->bc.nstack));
2638 r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES,
2639 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
2640 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2641 }
2642
2643
2644 void *r600_create_resolve_blend(struct r600_context *rctx)
2645 {
2646 struct pipe_blend_state blend;
2647 unsigned i;
2648
2649 memset(&blend, 0, sizeof(blend));
2650 blend.independent_blend_enable = true;
2651 for (i = 0; i < 2; i++) {
2652 blend.rt[i].colormask = 0xf;
2653 blend.rt[i].blend_enable = 1;
2654 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2655 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2656 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2657 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2658 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2659 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2660 }
2661 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2662 }
2663
2664 void *r700_create_resolve_blend(struct r600_context *rctx)
2665 {
2666 struct pipe_blend_state blend;
2667
2668 memset(&blend, 0, sizeof(blend));
2669 blend.independent_blend_enable = true;
2670 blend.rt[0].colormask = 0xf;
2671 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2672 }
2673
2674 void *r600_create_decompress_blend(struct r600_context *rctx)
2675 {
2676 struct pipe_blend_state blend;
2677
2678 memset(&blend, 0, sizeof(blend));
2679 blend.independent_blend_enable = true;
2680 blend.rt[0].colormask = 0xf;
2681 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2682 }
2683
2684 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2685 {
2686 struct pipe_depth_stencil_alpha_state dsa;
2687 boolean quirk = false;
2688
2689 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2690 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2691 quirk = true;
2692
2693 memset(&dsa, 0, sizeof(dsa));
2694
2695 if (quirk) {
2696 dsa.depth.enabled = 1;
2697 dsa.depth.func = PIPE_FUNC_LEQUAL;
2698 dsa.stencil[0].enabled = 1;
2699 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2700 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2701 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2702 dsa.stencil[0].writemask = 0xff;
2703 }
2704
2705 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2706 }
2707
2708 void r600_update_db_shader_control(struct r600_context * rctx)
2709 {
2710 bool dual_export;
2711 unsigned db_shader_control;
2712
2713 if (!rctx->ps_shader) {
2714 return;
2715 }
2716
2717 dual_export = rctx->framebuffer.export_16bpc &&
2718 !rctx->ps_shader->current->ps_depth_export;
2719
2720 db_shader_control = rctx->ps_shader->current->db_shader_control |
2721 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2722
2723 /* When alpha test is enabled we can't trust the hw to make the proper
2724 * decision on the order in which ztest should be run related to fragment
2725 * shader execution.
2726 *
2727 * If alpha test is enabled perform z test after fragment. RE_Z (early
2728 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2729 */
2730 if (rctx->alphatest_state.sx_alpha_test_control) {
2731 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2732 } else {
2733 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2734 }
2735
2736 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
2737 rctx->db_misc_state.db_shader_control = db_shader_control;
2738 rctx->db_misc_state.atom.dirty = true;
2739 }
2740 }
2741
2742 static INLINE unsigned r600_array_mode(unsigned mode)
2743 {
2744 switch (mode) {
2745 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
2746 break;
2747 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
2748 break;
2749 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
2750 default:
2751 case RADEON_SURF_MODE_LINEAR: return V_0280A0_ARRAY_LINEAR_GENERAL;
2752 }
2753 }
2754
2755 static boolean r600_dma_copy_tile(struct r600_context *rctx,
2756 struct pipe_resource *dst,
2757 unsigned dst_level,
2758 unsigned dst_x,
2759 unsigned dst_y,
2760 unsigned dst_z,
2761 struct pipe_resource *src,
2762 unsigned src_level,
2763 unsigned src_x,
2764 unsigned src_y,
2765 unsigned src_z,
2766 unsigned copy_height,
2767 unsigned pitch,
2768 unsigned bpp)
2769 {
2770 struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs;
2771 struct r600_texture *rsrc = (struct r600_texture*)src;
2772 struct r600_texture *rdst = (struct r600_texture*)dst;
2773 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
2774 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
2775 uint64_t base, addr;
2776
2777 dst_mode = rdst->surface.level[dst_level].mode;
2778 src_mode = rsrc->surface.level[src_level].mode;
2779 /* downcast linear aligned to linear to simplify test */
2780 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
2781 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
2782 assert(dst_mode != src_mode);
2783
2784 y = 0;
2785 lbpp = util_logbase2(bpp);
2786 pitch_tile_max = ((pitch / bpp) / 8) - 1;
2787
2788 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
2789 /* T2L */
2790 array_mode = r600_array_mode(src_mode);
2791 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
2792 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2793 /* linear height must be the same as the slice tile max height, it's ok even
2794 * if the linear destination/source have smaller heigh as the size of the
2795 * dma packet will be using the copy_height which is always smaller or equal
2796 * to the linear height
2797 */
2798 height = rsrc->surface.level[src_level].npix_y;
2799 detile = 1;
2800 x = src_x;
2801 y = src_y;
2802 z = src_z;
2803 base = rsrc->surface.level[src_level].offset;
2804 addr = rdst->surface.level[dst_level].offset;
2805 addr += rdst->surface.level[dst_level].slice_size * dst_z;
2806 addr += dst_y * pitch + dst_x * bpp;
2807 } else {
2808 /* L2T */
2809 array_mode = r600_array_mode(dst_mode);
2810 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
2811 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2812 /* linear height must be the same as the slice tile max height, it's ok even
2813 * if the linear destination/source have smaller heigh as the size of the
2814 * dma packet will be using the copy_height which is always smaller or equal
2815 * to the linear height
2816 */
2817 height = rdst->surface.level[dst_level].npix_y;
2818 detile = 0;
2819 x = dst_x;
2820 y = dst_y;
2821 z = dst_z;
2822 base = rdst->surface.level[dst_level].offset;
2823 addr = rsrc->surface.level[src_level].offset;
2824 addr += rsrc->surface.level[src_level].slice_size * src_z;
2825 addr += src_y * pitch + src_x * bpp;
2826 }
2827 /* check that we are in dw/base alignment constraint */
2828 if (addr % 4 || base % 256) {
2829 return FALSE;
2830 }
2831
2832 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2833 * line in the blit. Compute max 8 line we can copy in the size limit
2834 */
2835 cheight = ((R600_DMA_COPY_MAX_SIZE_DW * 4) / pitch) & 0xfffffff8;
2836 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
2837 r600_need_dma_space(&rctx->b, ncopy * 7);
2838
2839 for (i = 0; i < ncopy; i++) {
2840 cheight = cheight > copy_height ? copy_height : cheight;
2841 size = (cheight * pitch) / 4;
2842 /* emit reloc before writting cs so that cs is always in consistent state */
2843 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rsrc->resource, RADEON_USAGE_READ,
2844 RADEON_PRIO_MIN);
2845 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rdst->resource, RADEON_USAGE_WRITE,
2846 RADEON_PRIO_MIN);
2847 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 1, 0, size);
2848 cs->buf[cs->cdw++] = base >> 8;
2849 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
2850 (lbpp << 24) | ((height - 1) << 10) |
2851 pitch_tile_max;
2852 cs->buf[cs->cdw++] = (slice_tile_max << 12) | (z << 0);
2853 cs->buf[cs->cdw++] = (x << 3) | (y << 17);
2854 cs->buf[cs->cdw++] = addr & 0xfffffffc;
2855 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
2856 copy_height -= cheight;
2857 addr += cheight * pitch;
2858 y += cheight;
2859 }
2860 return TRUE;
2861 }
2862
2863 static void r600_dma_copy(struct pipe_context *ctx,
2864 struct pipe_resource *dst,
2865 unsigned dst_level,
2866 unsigned dstx, unsigned dsty, unsigned dstz,
2867 struct pipe_resource *src,
2868 unsigned src_level,
2869 const struct pipe_box *src_box)
2870 {
2871 struct r600_context *rctx = (struct r600_context *)ctx;
2872 struct r600_texture *rsrc = (struct r600_texture*)src;
2873 struct r600_texture *rdst = (struct r600_texture*)dst;
2874 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
2875 unsigned src_w, dst_w;
2876 unsigned src_x, src_y;
2877 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
2878
2879 if (rctx->b.rings.dma.cs == NULL) {
2880 goto fallback;
2881 }
2882
2883 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
2884 if (dst_x % 4 || src_box->x % 4 || src_box->width % 4)
2885 goto fallback;
2886
2887 r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
2888 return;
2889 }
2890
2891 if (src->format != dst->format || src_box->depth > 1) {
2892 goto fallback;
2893 }
2894
2895 src_x = util_format_get_nblocksx(src->format, src_box->x);
2896 dst_x = util_format_get_nblocksx(src->format, dst_x);
2897 src_y = util_format_get_nblocksy(src->format, src_box->y);
2898 dst_y = util_format_get_nblocksy(src->format, dst_y);
2899
2900 bpp = rdst->surface.bpe;
2901 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
2902 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
2903 src_w = rsrc->surface.level[src_level].npix_x;
2904 dst_w = rdst->surface.level[dst_level].npix_x;
2905 copy_height = src_box->height / rsrc->surface.blk_h;
2906
2907 dst_mode = rdst->surface.level[dst_level].mode;
2908 src_mode = rsrc->surface.level[src_level].mode;
2909 /* downcast linear aligned to linear to simplify test */
2910 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
2911 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
2912
2913 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
2914 /* strict requirement on r6xx/r7xx */
2915 goto fallback;
2916 }
2917 /* lot of constraint on alignment this should capture them all */
2918 if (src_pitch % 8 || src_box->y % 8 || dst_y % 8) {
2919 goto fallback;
2920 }
2921
2922 if (src_mode == dst_mode) {
2923 uint64_t dst_offset, src_offset, size;
2924
2925 /* simple dma blit would do NOTE code here assume :
2926 * src_box.x/y == 0
2927 * dst_x/y == 0
2928 * dst_pitch == src_pitch
2929 */
2930 src_offset= rsrc->surface.level[src_level].offset;
2931 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
2932 src_offset += src_y * src_pitch + src_x * bpp;
2933 dst_offset = rdst->surface.level[dst_level].offset;
2934 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
2935 dst_offset += dst_y * dst_pitch + dst_x * bpp;
2936 size = src_box->height * src_pitch;
2937 /* must be dw aligned */
2938 if (dst_offset % 4 || src_offset % 4 || size % 4) {
2939 goto fallback;
2940 }
2941 r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size);
2942 } else {
2943 if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
2944 src, src_level, src_x, src_y, src_box->z,
2945 copy_height, dst_pitch, bpp)) {
2946 goto fallback;
2947 }
2948 }
2949 return;
2950
2951 fallback:
2952 ctx->resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
2953 src, src_level, src_box);
2954 }
2955
2956 void r600_init_state_functions(struct r600_context *rctx)
2957 {
2958 unsigned id = 4;
2959 int i;
2960
2961 /* !!!
2962 * To avoid GPU lockup registers must be emited in a specific order
2963 * (no kidding ...). The order below is important and have been
2964 * partialy infered from analyzing fglrx command stream.
2965 *
2966 * Don't reorder atom without carefully checking the effect (GPU lockup
2967 * or piglit regression).
2968 * !!!
2969 */
2970
2971 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
2972
2973 /* shader const */
2974 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
2975 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
2976 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
2977
2978 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2979 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
2980 */
2981 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
2982 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
2983 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
2984 /* resource */
2985 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
2986 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
2987 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
2988 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
2989
2990 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 7);
2991
2992 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
2993 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
2994 rctx->sample_mask.sample_mask = ~0;
2995
2996 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
2997 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
2998 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
2999 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3000 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3001 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3002 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3003 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3004 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3005 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
3006 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3007 for (i = 0;i < 16; i++) {
3008 r600_init_atom(rctx, &rctx->scissor[i].atom, id++, r600_emit_scissor_state, 4);
3009 r600_init_atom(rctx, &rctx->viewport[i].atom, id++, r600_emit_viewport_state, 8);
3010 rctx->scissor[i].idx = i;
3011 rctx->viewport[i].idx = i;
3012 }
3013 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3014 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3015 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3016 rctx->atoms[id++] = &rctx->b.streamout.begin_atom;
3017 rctx->atoms[id++] = &rctx->b.streamout.enable_atom;
3018 r600_init_atom(rctx, &rctx->vertex_shader.atom, id++, r600_emit_shader, 23);
3019 r600_init_atom(rctx, &rctx->pixel_shader.atom, id++, r600_emit_shader, 0);
3020 r600_init_atom(rctx, &rctx->geometry_shader.atom, id++, r600_emit_shader, 0);
3021 r600_init_atom(rctx, &rctx->export_shader.atom, id++, r600_emit_shader, 0);
3022 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0);
3023 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0);
3024
3025 rctx->b.b.create_blend_state = r600_create_blend_state;
3026 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3027 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3028 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3029 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3030 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3031 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3032 rctx->b.b.set_scissor_states = r600_set_scissor_states;
3033 rctx->b.b.get_sample_position = r600_get_sample_position;
3034 rctx->b.dma_copy = r600_dma_copy;
3035 }
3036 /* this function must be last */