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r600g: Do colorformat endian swap for PIPE_USAGE_STAGING
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
144 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
145 {
146 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
147 }
148
149 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
150 {
151 return r600_translate_colorformat(chip, format) != ~0U &&
152 r600_translate_colorswap(format) != ~0U;
153 }
154
155 static bool r600_is_zs_format_supported(enum pipe_format format)
156 {
157 return r600_translate_dbformat(format) != ~0U;
158 }
159
160 boolean r600_is_format_supported(struct pipe_screen *screen,
161 enum pipe_format format,
162 enum pipe_texture_target target,
163 unsigned sample_count,
164 unsigned usage)
165 {
166 struct r600_screen *rscreen = (struct r600_screen*)screen;
167 unsigned retval = 0;
168
169 if (target >= PIPE_MAX_TEXTURE_TYPES) {
170 R600_ERR("r600: unsupported texture type %d\n", target);
171 return FALSE;
172 }
173
174 if (!util_format_is_supported(format, usage))
175 return FALSE;
176
177 if (sample_count > 1) {
178 if (!rscreen->has_msaa)
179 return FALSE;
180
181 /* R11G11B10 is broken on R6xx. */
182 if (rscreen->b.chip_class == R600 &&
183 format == PIPE_FORMAT_R11G11B10_FLOAT)
184 return FALSE;
185
186 /* MSAA integer colorbuffers hang. */
187 if (util_format_is_pure_integer(format) &&
188 !util_format_is_depth_or_stencil(format))
189 return FALSE;
190
191 switch (sample_count) {
192 case 2:
193 case 4:
194 case 8:
195 break;
196 default:
197 return FALSE;
198 }
199 }
200
201 if (usage & PIPE_BIND_SAMPLER_VIEW) {
202 if (target == PIPE_BUFFER) {
203 if (r600_is_vertex_format_supported(format))
204 retval |= PIPE_BIND_SAMPLER_VIEW;
205 } else {
206 if (r600_is_sampler_format_supported(screen, format))
207 retval |= PIPE_BIND_SAMPLER_VIEW;
208 }
209 }
210
211 if ((usage & (PIPE_BIND_RENDER_TARGET |
212 PIPE_BIND_DISPLAY_TARGET |
213 PIPE_BIND_SCANOUT |
214 PIPE_BIND_SHARED |
215 PIPE_BIND_BLENDABLE)) &&
216 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
217 retval |= usage &
218 (PIPE_BIND_RENDER_TARGET |
219 PIPE_BIND_DISPLAY_TARGET |
220 PIPE_BIND_SCANOUT |
221 PIPE_BIND_SHARED);
222 if (!util_format_is_pure_integer(format) &&
223 !util_format_is_depth_or_stencil(format))
224 retval |= usage & PIPE_BIND_BLENDABLE;
225 }
226
227 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
228 r600_is_zs_format_supported(format)) {
229 retval |= PIPE_BIND_DEPTH_STENCIL;
230 }
231
232 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
233 r600_is_vertex_format_supported(format)) {
234 retval |= PIPE_BIND_VERTEX_BUFFER;
235 }
236
237 if (usage & PIPE_BIND_TRANSFER_READ)
238 retval |= PIPE_BIND_TRANSFER_READ;
239 if (usage & PIPE_BIND_TRANSFER_WRITE)
240 retval |= PIPE_BIND_TRANSFER_WRITE;
241
242 return retval == usage;
243 }
244
245 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
246 {
247 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
248 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
249 float offset_units = state->offset_units;
250 float offset_scale = state->offset_scale;
251
252 switch (state->zs_format) {
253 case PIPE_FORMAT_Z24X8_UNORM:
254 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
255 offset_units *= 2.0f;
256 break;
257 case PIPE_FORMAT_Z16_UNORM:
258 offset_units *= 4.0f;
259 break;
260 default:;
261 }
262
263 radeon_set_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
264 radeon_emit(cs, fui(offset_scale));
265 radeon_emit(cs, fui(offset_units));
266 radeon_emit(cs, fui(offset_scale));
267 radeon_emit(cs, fui(offset_units));
268 }
269
270 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
271 {
272 int j = state->independent_blend_enable ? i : 0;
273
274 unsigned eqRGB = state->rt[j].rgb_func;
275 unsigned srcRGB = state->rt[j].rgb_src_factor;
276 unsigned dstRGB = state->rt[j].rgb_dst_factor;
277
278 unsigned eqA = state->rt[j].alpha_func;
279 unsigned srcA = state->rt[j].alpha_src_factor;
280 unsigned dstA = state->rt[j].alpha_dst_factor;
281 uint32_t bc = 0;
282
283 if (!state->rt[j].blend_enable)
284 return 0;
285
286 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
287 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
288 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
289
290 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
291 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
292 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
293 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
294 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
295 }
296 return bc;
297 }
298
299 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
300 const struct pipe_blend_state *state,
301 int mode)
302 {
303 struct r600_context *rctx = (struct r600_context *)ctx;
304 uint32_t color_control = 0, target_mask = 0;
305 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
306
307 if (!blend) {
308 return NULL;
309 }
310
311 r600_init_command_buffer(&blend->buffer, 20);
312 r600_init_command_buffer(&blend->buffer_no_blend, 20);
313
314 /* R600 does not support per-MRT blends */
315 if (rctx->b.family > CHIP_R600)
316 color_control |= S_028808_PER_MRT_BLEND(1);
317
318 if (state->logicop_enable) {
319 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
320 } else {
321 color_control |= (0xcc << 16);
322 }
323 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
324 if (state->independent_blend_enable) {
325 for (int i = 0; i < 8; i++) {
326 if (state->rt[i].blend_enable) {
327 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
328 }
329 target_mask |= (state->rt[i].colormask << (4 * i));
330 }
331 } else {
332 for (int i = 0; i < 8; i++) {
333 if (state->rt[0].blend_enable) {
334 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
335 }
336 target_mask |= (state->rt[0].colormask << (4 * i));
337 }
338 }
339
340 if (target_mask)
341 color_control |= S_028808_SPECIAL_OP(mode);
342 else
343 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
344
345 /* only MRT0 has dual src blend */
346 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
347 blend->cb_target_mask = target_mask;
348 blend->cb_color_control = color_control;
349 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
350 blend->alpha_to_one = state->alpha_to_one;
351
352 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
353 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
354 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
355 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
356 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
357 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
358
359 /* Copy over the registers set so far into buffer_no_blend. */
360 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
361 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
362
363 /* Only add blend registers if blending is enabled. */
364 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
365 return blend;
366 }
367
368 /* The first R600 does not support per-MRT blends */
369 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
370 r600_get_blend_control(state, 0));
371
372 if (rctx->b.family > CHIP_R600) {
373 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
374 for (int i = 0; i < 8; i++) {
375 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
376 }
377 }
378 return blend;
379 }
380
381 static void *r600_create_blend_state(struct pipe_context *ctx,
382 const struct pipe_blend_state *state)
383 {
384 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
385 }
386
387 static void *r600_create_dsa_state(struct pipe_context *ctx,
388 const struct pipe_depth_stencil_alpha_state *state)
389 {
390 unsigned db_depth_control, alpha_test_control, alpha_ref;
391 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
392
393 if (!dsa) {
394 return NULL;
395 }
396
397 r600_init_command_buffer(&dsa->buffer, 3);
398
399 dsa->valuemask[0] = state->stencil[0].valuemask;
400 dsa->valuemask[1] = state->stencil[1].valuemask;
401 dsa->writemask[0] = state->stencil[0].writemask;
402 dsa->writemask[1] = state->stencil[1].writemask;
403 dsa->zwritemask = state->depth.writemask;
404
405 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
406 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
407 S_028800_ZFUNC(state->depth.func);
408
409 /* stencil */
410 if (state->stencil[0].enabled) {
411 db_depth_control |= S_028800_STENCIL_ENABLE(1);
412 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
413 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
414 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
415 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
416
417 if (state->stencil[1].enabled) {
418 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
419 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
420 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
421 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
422 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
423 }
424 }
425
426 /* alpha */
427 alpha_test_control = 0;
428 alpha_ref = 0;
429 if (state->alpha.enabled) {
430 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
431 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
432 alpha_ref = fui(state->alpha.ref_value);
433 }
434 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
435 dsa->alpha_ref = alpha_ref;
436
437 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
438 return dsa;
439 }
440
441 static void *r600_create_rs_state(struct pipe_context *ctx,
442 const struct pipe_rasterizer_state *state)
443 {
444 struct r600_context *rctx = (struct r600_context *)ctx;
445 unsigned tmp, sc_mode_cntl, spi_interp;
446 float psize_min, psize_max;
447 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
448
449 if (!rs) {
450 return NULL;
451 }
452
453 r600_init_command_buffer(&rs->buffer, 30);
454
455 rs->flatshade = state->flatshade;
456 rs->sprite_coord_enable = state->sprite_coord_enable;
457 rs->two_side = state->light_twoside;
458 rs->clip_plane_enable = state->clip_plane_enable;
459 rs->pa_sc_line_stipple = state->line_stipple_enable ?
460 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
461 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
462 rs->pa_cl_clip_cntl =
463 S_028810_PS_UCP_MODE(3) |
464 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
465 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
466 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
467 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
468 if (rctx->b.chip_class == R700) {
469 rs->pa_cl_clip_cntl |=
470 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
471 }
472 rs->multisample_enable = state->multisample;
473
474 /* offset */
475 rs->offset_units = state->offset_units;
476 rs->offset_scale = state->offset_scale * 16.0f;
477 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
478
479 if (state->point_size_per_vertex) {
480 psize_min = util_get_min_point_size(state);
481 psize_max = 8192;
482 } else {
483 /* Force the point size to be as if the vertex output was disabled. */
484 psize_min = state->point_size;
485 psize_max = state->point_size;
486 }
487
488 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
489 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
490 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
491 S_028A4C_PS_ITER_SAMPLE(state->multisample && rctx->ps_iter_samples > 1);
492 if (rctx->b.family == CHIP_RV770) {
493 /* workaround possible rendering corruption on RV770 with hyperz together with sample shading */
494 sc_mode_cntl |= S_028A4C_TILE_COVER_DISABLE(state->multisample && rctx->ps_iter_samples > 1);
495 }
496 if (rctx->b.chip_class >= R700) {
497 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
498 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
499 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
500 } else {
501 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
502 rs->scissor_enable = state->scissor;
503 }
504
505 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
506 if (state->sprite_coord_enable) {
507 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
508 S_0286D4_PNT_SPRITE_OVRD_X(2) |
509 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
510 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
511 S_0286D4_PNT_SPRITE_OVRD_W(1);
512 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
513 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
514 }
515 }
516
517 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
518 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
519 tmp = r600_pack_float_12p4(state->point_size/2);
520 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
521 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
522 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
523 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
524 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
525 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
526 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
527
528 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
529 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
530 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
531 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
532 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
533 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
534
535 rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
536 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
537 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
538 S_028814_FACE(!state->front_ccw) |
539 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
540 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
541 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
542 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
543 state->fill_back != PIPE_POLYGON_MODE_FILL) |
544 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
545 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
546 if (rctx->b.chip_class == R700) {
547 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl);
548 }
549 if (rctx->b.chip_class == R600) {
550 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC,
551 S_028350_MULTIPASS(state->rasterizer_discard));
552 }
553 return rs;
554 }
555
556 static void *r600_create_sampler_state(struct pipe_context *ctx,
557 const struct pipe_sampler_state *state)
558 {
559 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
560 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
561
562 if (!ss) {
563 return NULL;
564 }
565
566 ss->seamless_cube_map = state->seamless_cube_map;
567 ss->border_color_use = sampler_state_needs_border_color(state);
568
569 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
570 ss->tex_sampler_words[0] =
571 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
572 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
573 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
574 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
575 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
576 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
577 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
578 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
579 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
580 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
581 ss->tex_sampler_words[1] =
582 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
583 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
584 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
585 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
586 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
587
588 if (ss->border_color_use) {
589 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
590 }
591 return ss;
592 }
593
594 static struct pipe_sampler_view *
595 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
596 unsigned width0, unsigned height0)
597
598 {
599 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
600 int stride = util_format_get_blocksize(view->base.format);
601 unsigned format, num_format, format_comp, endian;
602 uint64_t offset = view->base.u.buf.first_element * stride;
603 unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
604
605 r600_vertex_data_type(view->base.format,
606 &format, &num_format, &format_comp,
607 &endian);
608
609 view->tex_resource = &tmp->resource;
610 view->skip_mip_address_reloc = true;
611
612 view->tex_resource_words[0] = offset;
613 view->tex_resource_words[1] = size - 1;
614 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(offset >> 32UL) |
615 S_038008_STRIDE(stride) |
616 S_038008_DATA_FORMAT(format) |
617 S_038008_NUM_FORMAT_ALL(num_format) |
618 S_038008_FORMAT_COMP_ALL(format_comp) |
619 S_038008_ENDIAN_SWAP(endian);
620 view->tex_resource_words[3] = 0;
621 /*
622 * in theory dword 4 is for number of elements, for use with resinfo,
623 * but it seems to utterly fail to work, the amd gpu shader analyser
624 * uses a const buffer to store the element sizes for buffer txq
625 */
626 view->tex_resource_words[4] = 0;
627 view->tex_resource_words[5] = 0;
628 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
629 return &view->base;
630 }
631
632 struct pipe_sampler_view *
633 r600_create_sampler_view_custom(struct pipe_context *ctx,
634 struct pipe_resource *texture,
635 const struct pipe_sampler_view *state,
636 unsigned width_first_level, unsigned height_first_level)
637 {
638 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
639 struct r600_texture *tmp = (struct r600_texture*)texture;
640 unsigned format, endian;
641 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
642 unsigned char swizzle[4], array_mode = 0;
643 unsigned width, height, depth, offset_level, last_level;
644
645 if (!view)
646 return NULL;
647
648 /* initialize base object */
649 view->base = *state;
650 view->base.texture = NULL;
651 pipe_reference(NULL, &texture->reference);
652 view->base.texture = texture;
653 view->base.reference.count = 1;
654 view->base.context = ctx;
655
656 if (texture->target == PIPE_BUFFER)
657 return texture_buffer_sampler_view(view, texture->width0, 1);
658
659 swizzle[0] = state->swizzle_r;
660 swizzle[1] = state->swizzle_g;
661 swizzle[2] = state->swizzle_b;
662 swizzle[3] = state->swizzle_a;
663
664 format = r600_translate_texformat(ctx->screen, state->format,
665 swizzle,
666 &word4, &yuv_format);
667 assert(format != ~0);
668 if (format == ~0) {
669 FREE(view);
670 return NULL;
671 }
672
673 if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) {
674 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
675 FREE(view);
676 return NULL;
677 }
678 tmp = tmp->flushed_depth_texture;
679 }
680
681 endian = r600_colorformat_endian_swap(format);
682
683 offset_level = state->u.tex.first_level;
684 last_level = state->u.tex.last_level - offset_level;
685 width = width_first_level;
686 height = height_first_level;
687 depth = u_minify(texture->depth0, offset_level);
688 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
689
690 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
691 height = 1;
692 depth = texture->array_size;
693 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
694 depth = texture->array_size;
695 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
696 depth = texture->array_size / 6;
697 switch (tmp->surface.level[offset_level].mode) {
698 case RADEON_SURF_MODE_LINEAR_ALIGNED:
699 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
700 break;
701 case RADEON_SURF_MODE_1D:
702 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
703 break;
704 case RADEON_SURF_MODE_2D:
705 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
706 break;
707 case RADEON_SURF_MODE_LINEAR:
708 default:
709 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
710 break;
711 }
712
713 if (state->format == PIPE_FORMAT_X24S8_UINT ||
714 state->format == PIPE_FORMAT_S8X24_UINT ||
715 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
716 state->format == PIPE_FORMAT_S8_UINT)
717 view->is_stencil_sampler = true;
718
719 view->tex_resource = &tmp->resource;
720 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
721 S_038000_TILE_MODE(array_mode) |
722 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
723 S_038000_PITCH((pitch / 8) - 1) |
724 S_038000_TEX_WIDTH(width - 1));
725 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
726 S_038004_TEX_DEPTH(depth - 1) |
727 S_038004_DATA_FORMAT(format));
728 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
729 if (offset_level >= tmp->surface.last_level) {
730 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
731 } else {
732 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
733 }
734 view->tex_resource_words[4] = (word4 |
735 S_038010_REQUEST_SIZE(1) |
736 S_038010_ENDIAN_SWAP(endian) |
737 S_038010_BASE_LEVEL(0));
738 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
739 S_038014_LAST_ARRAY(state->u.tex.last_layer));
740 if (texture->nr_samples > 1) {
741 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
742 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
743 } else {
744 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
745 }
746 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
747 S_038018_MAX_ANISO(4 /* max 16 samples */));
748 return &view->base;
749 }
750
751 static struct pipe_sampler_view *
752 r600_create_sampler_view(struct pipe_context *ctx,
753 struct pipe_resource *tex,
754 const struct pipe_sampler_view *state)
755 {
756 return r600_create_sampler_view_custom(ctx, tex, state,
757 u_minify(tex->width0, state->u.tex.first_level),
758 u_minify(tex->height0, state->u.tex.first_level));
759 }
760
761 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
762 {
763 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
764 struct pipe_clip_state *state = &rctx->clip_state.state;
765
766 radeon_set_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
767 radeon_emit_array(cs, (unsigned*)state, 6*4);
768 }
769
770 static void r600_set_polygon_stipple(struct pipe_context *ctx,
771 const struct pipe_poly_stipple *state)
772 {
773 }
774
775 static void r600_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
776 {
777 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
778 struct r600_scissor_state *rstate = &rctx->scissor;
779 struct pipe_scissor_state *state;
780 bool do_disable_workaround = false;
781 uint32_t dirty_mask;
782 unsigned i, offset;
783 uint32_t tl, br;
784
785 if (rctx->b.chip_class == R600 && !rctx->scissor.enable) {
786 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
787 br = S_028244_BR_X(8192) | S_028244_BR_Y(8192);
788 do_disable_workaround = true;
789 }
790
791 dirty_mask = rstate->dirty_mask;
792 while (dirty_mask != 0)
793 {
794 i = u_bit_scan(&dirty_mask);
795 offset = i * 4 * 2;
796 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + offset, 2);
797 if (!do_disable_workaround) {
798 state = &rstate->scissor[i];
799 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) |
800 S_028240_WINDOW_OFFSET_DISABLE(1);
801 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
802 }
803 radeon_emit(cs, tl);
804 radeon_emit(cs, br);
805 }
806 rstate->dirty_mask = 0;
807 rstate->atom.num_dw = 0;
808 }
809
810 static void r600_set_scissor_states(struct pipe_context *ctx,
811 unsigned start_slot,
812 unsigned num_scissors,
813 const struct pipe_scissor_state *state)
814 {
815 struct r600_context *rctx = (struct r600_context *)ctx;
816 struct r600_scissor_state *rstate = &rctx->scissor;
817 int i;
818
819 for (i = start_slot ; i < start_slot + num_scissors; i++)
820 rstate->scissor[i] = state[i - start_slot];
821 rstate->dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
822 rstate->atom.num_dw = util_bitcount(rstate->dirty_mask) * 4;
823
824 if (rctx->b.chip_class == R600 && !rstate->enable)
825 return;
826
827 r600_mark_atom_dirty(rctx, &rstate->atom);
828 }
829
830 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
831 unsigned size, unsigned alignment)
832 {
833 struct pipe_resource buffer;
834
835 memset(&buffer, 0, sizeof buffer);
836 buffer.target = PIPE_BUFFER;
837 buffer.format = PIPE_FORMAT_R8_UNORM;
838 buffer.bind = PIPE_BIND_CUSTOM;
839 buffer.usage = PIPE_USAGE_DEFAULT;
840 buffer.flags = 0;
841 buffer.width0 = size;
842 buffer.height0 = 1;
843 buffer.depth0 = 1;
844 buffer.array_size = 1;
845
846 return (struct r600_resource*)
847 r600_buffer_create(&rscreen->b.b, &buffer, alignment);
848 }
849
850 static void r600_init_color_surface(struct r600_context *rctx,
851 struct r600_surface *surf,
852 bool force_cmask_fmask)
853 {
854 struct r600_screen *rscreen = rctx->screen;
855 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
856 unsigned level = surf->base.u.tex.level;
857 unsigned pitch, slice;
858 unsigned color_info;
859 unsigned color_view;
860 unsigned format, swap, ntype, endian;
861 unsigned offset;
862 const struct util_format_description *desc;
863 int i;
864 bool blend_bypass = 0, blend_clamp = 1;
865
866 if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
867 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
868 rtex = rtex->flushed_depth_texture;
869 assert(rtex);
870 }
871
872 offset = rtex->surface.level[level].offset;
873 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
874 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
875 offset += rtex->surface.level[level].slice_size *
876 surf->base.u.tex.first_layer;
877 color_view = 0;
878 } else
879 color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
880 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
881
882 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
883 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
884 if (slice) {
885 slice = slice - 1;
886 }
887 color_info = 0;
888 switch (rtex->surface.level[level].mode) {
889 case RADEON_SURF_MODE_LINEAR_ALIGNED:
890 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
891 break;
892 case RADEON_SURF_MODE_1D:
893 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
894 break;
895 case RADEON_SURF_MODE_2D:
896 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
897 break;
898 case RADEON_SURF_MODE_LINEAR:
899 default:
900 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
901 break;
902 }
903
904 desc = util_format_description(surf->base.format);
905
906 for (i = 0; i < 4; i++) {
907 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
908 break;
909 }
910 }
911
912 ntype = V_0280A0_NUMBER_UNORM;
913 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
914 ntype = V_0280A0_NUMBER_SRGB;
915 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
916 if (desc->channel[i].normalized)
917 ntype = V_0280A0_NUMBER_SNORM;
918 else if (desc->channel[i].pure_integer)
919 ntype = V_0280A0_NUMBER_SINT;
920 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
921 if (desc->channel[i].normalized)
922 ntype = V_0280A0_NUMBER_UNORM;
923 else if (desc->channel[i].pure_integer)
924 ntype = V_0280A0_NUMBER_UINT;
925 }
926
927 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
928 assert(format != ~0);
929
930 swap = r600_translate_colorswap(surf->base.format);
931 assert(swap != ~0);
932
933 endian = r600_colorformat_endian_swap(format);
934
935 /* set blend bypass according to docs if SINT/UINT or
936 8/24 COLOR variants */
937 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
938 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
939 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
940 blend_clamp = 0;
941 blend_bypass = 1;
942 }
943
944 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
945
946 color_info |= S_0280A0_FORMAT(format) |
947 S_0280A0_COMP_SWAP(swap) |
948 S_0280A0_BLEND_BYPASS(blend_bypass) |
949 S_0280A0_BLEND_CLAMP(blend_clamp) |
950 S_0280A0_NUMBER_TYPE(ntype) |
951 S_0280A0_ENDIAN(endian);
952
953 /* EXPORT_NORM is an optimzation that can be enabled for better
954 * performance in certain cases
955 */
956 if (rctx->b.chip_class == R600) {
957 /* EXPORT_NORM can be enabled if:
958 * - 11-bit or smaller UNORM/SNORM/SRGB
959 * - BLEND_CLAMP is enabled
960 * - BLEND_FLOAT32 is disabled
961 */
962 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
963 (desc->channel[i].size < 12 &&
964 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
965 ntype != V_0280A0_NUMBER_UINT &&
966 ntype != V_0280A0_NUMBER_SINT) &&
967 G_0280A0_BLEND_CLAMP(color_info) &&
968 !G_0280A0_BLEND_FLOAT32(color_info)) {
969 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
970 surf->export_16bpc = true;
971 }
972 } else {
973 /* EXPORT_NORM can be enabled if:
974 * - 11-bit or smaller UNORM/SNORM/SRGB
975 * - 16-bit or smaller FLOAT
976 */
977 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
978 ((desc->channel[i].size < 12 &&
979 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
980 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
981 (desc->channel[i].size < 17 &&
982 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
983 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
984 surf->export_16bpc = true;
985 }
986 }
987
988 /* These might not always be initialized to zero. */
989 surf->cb_color_base = offset >> 8;
990 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
991 S_028060_SLICE_TILE_MAX(slice);
992 surf->cb_color_fmask = surf->cb_color_base;
993 surf->cb_color_cmask = surf->cb_color_base;
994 surf->cb_color_mask = 0;
995
996 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
997 &rtex->resource.b.b);
998 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
999 &rtex->resource.b.b);
1000
1001 if (rtex->cmask.size) {
1002 surf->cb_color_cmask = rtex->cmask.offset >> 8;
1003 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
1004
1005 if (rtex->fmask.size) {
1006 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1007 surf->cb_color_fmask = rtex->fmask.offset >> 8;
1008 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
1009 } else { /* cmask only */
1010 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
1011 }
1012 } else if (force_cmask_fmask) {
1013 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1014 *
1015 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1016 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1017 * because it's not an MSAA buffer.
1018 */
1019 struct r600_cmask_info cmask;
1020 struct r600_fmask_info fmask;
1021
1022 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
1023 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
1024
1025 /* CMASK. */
1026 if (!rctx->dummy_cmask ||
1027 rctx->dummy_cmask->b.b.width0 < cmask.size ||
1028 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1029 struct pipe_transfer *transfer;
1030 void *ptr;
1031
1032 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1033 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1034
1035 /* Set the contents to 0xCC. */
1036 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1037 memset(ptr, 0xCC, cmask.size);
1038 pipe_buffer_unmap(&rctx->b.b, transfer);
1039 }
1040 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1041 &rctx->dummy_cmask->b.b);
1042
1043 /* FMASK. */
1044 if (!rctx->dummy_fmask ||
1045 rctx->dummy_fmask->b.b.width0 < fmask.size ||
1046 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1047 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1048 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1049
1050 }
1051 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1052 &rctx->dummy_fmask->b.b);
1053
1054 /* Init the registers. */
1055 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1056 surf->cb_color_cmask = 0;
1057 surf->cb_color_fmask = 0;
1058 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1059 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1060 }
1061
1062 surf->cb_color_info = color_info;
1063 surf->cb_color_view = color_view;
1064 surf->color_initialized = true;
1065 }
1066
1067 static void r600_init_depth_surface(struct r600_context *rctx,
1068 struct r600_surface *surf)
1069 {
1070 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1071 unsigned level, pitch, slice, format, offset, array_mode;
1072
1073 level = surf->base.u.tex.level;
1074 offset = rtex->surface.level[level].offset;
1075 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1076 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1077 if (slice) {
1078 slice = slice - 1;
1079 }
1080 switch (rtex->surface.level[level].mode) {
1081 case RADEON_SURF_MODE_2D:
1082 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1083 break;
1084 case RADEON_SURF_MODE_1D:
1085 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1086 case RADEON_SURF_MODE_LINEAR:
1087 default:
1088 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1089 break;
1090 }
1091
1092 format = r600_translate_dbformat(surf->base.format);
1093 assert(format != ~0);
1094
1095 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1096 surf->db_depth_base = offset >> 8;
1097 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1098 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1099 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1100 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1101
1102 switch (surf->base.format) {
1103 case PIPE_FORMAT_Z24X8_UNORM:
1104 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1105 surf->pa_su_poly_offset_db_fmt_cntl =
1106 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1107 break;
1108 case PIPE_FORMAT_Z32_FLOAT:
1109 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1110 surf->pa_su_poly_offset_db_fmt_cntl =
1111 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1112 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1113 break;
1114 case PIPE_FORMAT_Z16_UNORM:
1115 surf->pa_su_poly_offset_db_fmt_cntl =
1116 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1117 break;
1118 default:;
1119 }
1120
1121 /* use htile only for first level */
1122 if (rtex->htile_buffer && !level) {
1123 surf->db_htile_data_base = 0;
1124 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1125 S_028D24_HTILE_HEIGHT(1) |
1126 S_028D24_FULL_CACHE(1);
1127 /* preload is not working properly on r6xx/r7xx */
1128 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1129 }
1130
1131 surf->depth_initialized = true;
1132 }
1133
1134 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1135 const struct pipe_framebuffer_state *state)
1136 {
1137 struct r600_context *rctx = (struct r600_context *)ctx;
1138 struct r600_surface *surf;
1139 struct r600_texture *rtex;
1140 unsigned i;
1141
1142 if (rctx->framebuffer.state.nr_cbufs) {
1143 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1144 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1145 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1146 }
1147 if (rctx->framebuffer.state.zsbuf) {
1148 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
1149 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
1150
1151 rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
1152 if (rctx->b.chip_class >= R700 && rtex->htile_buffer) {
1153 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
1154 }
1155 }
1156
1157 /* Set the new state. */
1158 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1159
1160 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1161 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1162 util_format_is_pure_integer(state->cbufs[0]->format);
1163 rctx->framebuffer.compressed_cb_mask = 0;
1164 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1165 state->cbufs[0] && state->cbufs[1] &&
1166 state->cbufs[0]->texture->nr_samples > 1 &&
1167 state->cbufs[1]->texture->nr_samples <= 1;
1168 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1169
1170 /* Colorbuffers. */
1171 for (i = 0; i < state->nr_cbufs; i++) {
1172 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1173 bool force_cmask_fmask = rctx->b.chip_class == R600 &&
1174 rctx->framebuffer.is_msaa_resolve &&
1175 i == 1;
1176
1177 surf = (struct r600_surface*)state->cbufs[i];
1178 if (!surf)
1179 continue;
1180
1181 rtex = (struct r600_texture*)surf->base.texture;
1182 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1183
1184 if (!surf->color_initialized || force_cmask_fmask) {
1185 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1186 if (force_cmask_fmask) {
1187 /* re-initialize later without compression */
1188 surf->color_initialized = false;
1189 }
1190 }
1191
1192 if (!surf->export_16bpc) {
1193 rctx->framebuffer.export_16bpc = false;
1194 }
1195
1196 if (rtex->fmask.size && rtex->cmask.size) {
1197 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1198 }
1199 }
1200
1201 /* Update alpha-test state dependencies.
1202 * Alpha-test is done on the first colorbuffer only. */
1203 if (state->nr_cbufs) {
1204 bool alphatest_bypass = false;
1205
1206 surf = (struct r600_surface*)state->cbufs[0];
1207 if (surf) {
1208 alphatest_bypass = surf->alphatest_bypass;
1209 }
1210
1211 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1212 rctx->alphatest_state.bypass = alphatest_bypass;
1213 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1214 }
1215 }
1216
1217 /* ZS buffer. */
1218 if (state->zsbuf) {
1219 surf = (struct r600_surface*)state->zsbuf;
1220
1221 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1222
1223 if (!surf->depth_initialized) {
1224 r600_init_depth_surface(rctx, surf);
1225 }
1226
1227 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1228 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1229 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1230 }
1231
1232 if (rctx->db_state.rsurf != surf) {
1233 rctx->db_state.rsurf = surf;
1234 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1235 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1236 }
1237 } else if (rctx->db_state.rsurf) {
1238 rctx->db_state.rsurf = NULL;
1239 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1240 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1241 }
1242
1243 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1244 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1245 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1246 }
1247
1248 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1249 rctx->alphatest_state.bypass = false;
1250 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1251 }
1252
1253 /* Calculate the CS size. */
1254 rctx->framebuffer.atom.num_dw =
1255 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1256
1257 if (rctx->framebuffer.state.nr_cbufs) {
1258 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
1259 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
1260 }
1261 if (rctx->framebuffer.state.zsbuf) {
1262 rctx->framebuffer.atom.num_dw += 16;
1263 } else if (rctx->screen->b.info.drm_minor >= 18) {
1264 rctx->framebuffer.atom.num_dw += 3;
1265 }
1266 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1267 rctx->framebuffer.atom.num_dw += 2;
1268 }
1269
1270 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1271
1272 r600_set_sample_locations_constant_buffer(rctx);
1273 }
1274
1275 static uint32_t sample_locs_2x[] = {
1276 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1277 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1278 };
1279 static unsigned max_dist_2x = 4;
1280
1281 static uint32_t sample_locs_4x[] = {
1282 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1283 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1284 };
1285 static unsigned max_dist_4x = 6;
1286 static uint32_t sample_locs_8x[] = {
1287 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1288 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1289 };
1290 static unsigned max_dist_8x = 7;
1291
1292 static void r600_get_sample_position(struct pipe_context *ctx,
1293 unsigned sample_count,
1294 unsigned sample_index,
1295 float *out_value)
1296 {
1297 int offset, index;
1298 struct {
1299 int idx:4;
1300 } val;
1301 switch (sample_count) {
1302 case 1:
1303 default:
1304 out_value[0] = out_value[1] = 0.5;
1305 break;
1306 case 2:
1307 offset = 4 * (sample_index * 2);
1308 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1309 out_value[0] = (float)(val.idx + 8) / 16.0f;
1310 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1311 out_value[1] = (float)(val.idx + 8) / 16.0f;
1312 break;
1313 case 4:
1314 offset = 4 * (sample_index * 2);
1315 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1316 out_value[0] = (float)(val.idx + 8) / 16.0f;
1317 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1318 out_value[1] = (float)(val.idx + 8) / 16.0f;
1319 break;
1320 case 8:
1321 offset = 4 * (sample_index % 4 * 2);
1322 index = (sample_index / 4);
1323 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1324 out_value[0] = (float)(val.idx + 8) / 16.0f;
1325 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1326 out_value[1] = (float)(val.idx + 8) / 16.0f;
1327 break;
1328 }
1329 }
1330
1331 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1332 {
1333 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1334 unsigned max_dist = 0;
1335
1336 if (rctx->b.family == CHIP_R600) {
1337 switch (nr_samples) {
1338 default:
1339 nr_samples = 0;
1340 break;
1341 case 2:
1342 radeon_set_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1343 max_dist = max_dist_2x;
1344 break;
1345 case 4:
1346 radeon_set_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1347 max_dist = max_dist_4x;
1348 break;
1349 case 8:
1350 radeon_set_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1351 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1352 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1353 max_dist = max_dist_8x;
1354 break;
1355 }
1356 } else {
1357 switch (nr_samples) {
1358 default:
1359 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1360 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1361 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1362 nr_samples = 0;
1363 break;
1364 case 2:
1365 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1366 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1367 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1368 max_dist = max_dist_2x;
1369 break;
1370 case 4:
1371 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1372 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1373 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1374 max_dist = max_dist_4x;
1375 break;
1376 case 8:
1377 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1378 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1379 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1380 max_dist = max_dist_8x;
1381 break;
1382 }
1383 }
1384
1385 if (nr_samples > 1) {
1386 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1387 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1388 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1389 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1390 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1391 } else {
1392 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1393 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1394 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1395 }
1396 }
1397
1398 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1399 {
1400 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1401 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1402 unsigned nr_cbufs = state->nr_cbufs;
1403 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1404 unsigned i, sbu = 0;
1405
1406 /* Colorbuffers. */
1407 radeon_set_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1408 for (i = 0; i < nr_cbufs; i++) {
1409 radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0);
1410 }
1411 /* set CB_COLOR1_INFO for possible dual-src blending */
1412 if (i == 1 && cb[0]) {
1413 radeon_emit(cs, cb[0]->cb_color_info);
1414 i++;
1415 }
1416 for (; i < 8; i++) {
1417 radeon_emit(cs, 0);
1418 }
1419
1420 if (nr_cbufs) {
1421 for (i = 0; i < nr_cbufs; i++) {
1422 unsigned reloc;
1423
1424 if (!cb[i])
1425 continue;
1426
1427 /* COLOR_BASE */
1428 radeon_set_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1429
1430 reloc = radeon_add_to_buffer_list(&rctx->b,
1431 &rctx->b.gfx,
1432 (struct r600_resource*)cb[i]->base.texture,
1433 RADEON_USAGE_READWRITE,
1434 cb[i]->base.texture->nr_samples > 1 ?
1435 RADEON_PRIO_COLOR_BUFFER_MSAA :
1436 RADEON_PRIO_COLOR_BUFFER);
1437 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1438 radeon_emit(cs, reloc);
1439
1440 /* FMASK */
1441 radeon_set_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1442
1443 reloc = radeon_add_to_buffer_list(&rctx->b,
1444 &rctx->b.gfx,
1445 cb[i]->cb_buffer_fmask,
1446 RADEON_USAGE_READWRITE,
1447 cb[i]->base.texture->nr_samples > 1 ?
1448 RADEON_PRIO_COLOR_BUFFER_MSAA :
1449 RADEON_PRIO_COLOR_BUFFER);
1450 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1451 radeon_emit(cs, reloc);
1452
1453 /* CMASK */
1454 radeon_set_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1455
1456 reloc = radeon_add_to_buffer_list(&rctx->b,
1457 &rctx->b.gfx,
1458 cb[i]->cb_buffer_cmask,
1459 RADEON_USAGE_READWRITE,
1460 cb[i]->base.texture->nr_samples > 1 ?
1461 RADEON_PRIO_COLOR_BUFFER_MSAA :
1462 RADEON_PRIO_COLOR_BUFFER);
1463 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1464 radeon_emit(cs, reloc);
1465 }
1466
1467 radeon_set_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1468 for (i = 0; i < nr_cbufs; i++) {
1469 radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0);
1470 }
1471
1472 radeon_set_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1473 for (i = 0; i < nr_cbufs; i++) {
1474 radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0);
1475 }
1476
1477 radeon_set_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1478 for (i = 0; i < nr_cbufs; i++) {
1479 radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0);
1480 }
1481
1482 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1483 }
1484
1485 /* SURFACE_BASE_UPDATE */
1486 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1487 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1488 radeon_emit(cs, sbu);
1489 sbu = 0;
1490 }
1491
1492 /* Zbuffer. */
1493 if (state->zsbuf) {
1494 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1495 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1496 &rctx->b.gfx,
1497 (struct r600_resource*)state->zsbuf->texture,
1498 RADEON_USAGE_READWRITE,
1499 surf->base.texture->nr_samples > 1 ?
1500 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1501 RADEON_PRIO_DEPTH_BUFFER);
1502
1503 radeon_set_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1504 surf->pa_su_poly_offset_db_fmt_cntl);
1505
1506 radeon_set_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1507 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1508 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1509 radeon_set_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1510 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1511 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1512
1513 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1514 radeon_emit(cs, reloc);
1515
1516 radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1517
1518 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1519 } else if (rctx->screen->b.info.drm_minor >= 18) {
1520 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1521 * Older kernels are out of luck. */
1522 radeon_set_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1523 }
1524
1525 /* SURFACE_BASE_UPDATE */
1526 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1527 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1528 radeon_emit(cs, sbu);
1529 sbu = 0;
1530 }
1531
1532 /* Framebuffer dimensions. */
1533 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1534 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1535 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1536 radeon_emit(cs, S_028244_BR_X(state->width) |
1537 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1538
1539 if (rctx->framebuffer.is_msaa_resolve) {
1540 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1541 } else {
1542 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1543 * will assure that the alpha-test will work even if there is
1544 * no colorbuffer bound. */
1545 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1546 (1ull << MAX2(nr_cbufs, 1)) - 1);
1547 }
1548
1549 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1550 }
1551
1552 static void r600_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1553 {
1554 struct r600_context *rctx = (struct r600_context *)ctx;
1555
1556 if (rctx->ps_iter_samples == min_samples)
1557 return;
1558
1559 rctx->ps_iter_samples = min_samples;
1560 if (rctx->framebuffer.nr_samples > 1) {
1561 r600_mark_atom_dirty(rctx, &rctx->rasterizer_state.atom);
1562 if (rctx->b.chip_class == R600)
1563 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1564 }
1565 }
1566
1567 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1568 {
1569 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1570 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1571
1572 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1573 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1574 if (rctx->b.chip_class == R600) {
1575 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1576 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1577 } else {
1578 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1579 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1580 }
1581 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1582 } else {
1583 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1584 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1585 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1586
1587 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1588 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1589 /* Always enable the first color output to make sure alpha-test works even without one. */
1590 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1591 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1592 a->cb_color_control |
1593 S_028808_MULTIWRITE_ENABLE(multiwrite));
1594 }
1595 }
1596
1597 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1598 {
1599 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1600 struct r600_db_state *a = (struct r600_db_state*)atom;
1601
1602 if (a->rsurf && a->rsurf->db_htile_surface) {
1603 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1604 unsigned reloc_idx;
1605
1606 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1607 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1608 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1609 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer,
1610 RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
1611 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1612 cs->buf[cs->cdw++] = reloc_idx;
1613 } else {
1614 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1615 }
1616 }
1617
1618 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1619 {
1620 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1621 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1622 unsigned db_render_control = 0;
1623 unsigned db_render_override =
1624 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1625 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1626
1627 if (rctx->b.chip_class >= R700) {
1628 switch (a->ps_conservative_z) {
1629 default: /* fall through */
1630 case TGSI_FS_DEPTH_LAYOUT_ANY:
1631 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_ANY_Z);
1632 break;
1633 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1634 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_GREATER_THAN_Z);
1635 break;
1636 case TGSI_FS_DEPTH_LAYOUT_LESS:
1637 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_LESS_THAN_Z);
1638 break;
1639 }
1640 }
1641
1642 if (a->occlusion_query_enabled) {
1643 if (rctx->b.chip_class >= R700) {
1644 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1645 }
1646 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1647 }
1648 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
1649 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1650 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1651 /* This is to fix a lockup when hyperz and alpha test are enabled at
1652 * the same time somehow GPU get confuse on which order to pick for
1653 * z test
1654 */
1655 if (rctx->alphatest_state.sx_alpha_test_control) {
1656 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
1657 }
1658 } else {
1659 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1660 }
1661 if (rctx->b.chip_class == R600 && rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) {
1662 /* sample shading and hyperz causes lockups on R6xx chips */
1663 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1664 }
1665 if (a->flush_depthstencil_through_cb) {
1666 assert(a->copy_depth || a->copy_stencil);
1667
1668 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1669 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1670 S_028D0C_COPY_CENTROID(1) |
1671 S_028D0C_COPY_SAMPLE(a->copy_sample);
1672
1673 if (rctx->b.chip_class == R600)
1674 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1675
1676 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
1677 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
1678 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1679 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1680 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1681 S_028D0C_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1682 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1683 }
1684 if (a->htile_clear) {
1685 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1686 }
1687
1688 /* RV770 workaround for a hang with 8x MSAA. */
1689 if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) {
1690 db_render_override |= S_028D10_MAX_TILES_IN_DTT(6);
1691 }
1692
1693 radeon_set_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1694 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1695 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1696 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1697 }
1698
1699 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1700 {
1701 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1702 struct r600_config_state *a = (struct r600_config_state*)atom;
1703
1704 radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1705 radeon_set_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
1706 }
1707
1708 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1709 {
1710 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1711 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1712
1713 while (dirty_mask) {
1714 struct pipe_vertex_buffer *vb;
1715 struct r600_resource *rbuffer;
1716 unsigned offset;
1717 unsigned buffer_index = u_bit_scan(&dirty_mask);
1718
1719 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1720 rbuffer = (struct r600_resource*)vb->buffer;
1721 assert(rbuffer);
1722
1723 offset = vb->buffer_offset;
1724
1725 /* fetch resources start at index 320 (OFFSET_FS) */
1726 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1727 radeon_emit(cs, (R600_FETCH_CONSTANTS_OFFSET_FS + buffer_index) * 7);
1728 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1729 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1730 radeon_emit(cs, /* RESOURCEi_WORD2 */
1731 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1732 S_038008_STRIDE(vb->stride));
1733 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1734 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1735 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1736 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1737
1738 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1739 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1740 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1741 }
1742 }
1743
1744 static void r600_emit_constant_buffers(struct r600_context *rctx,
1745 struct r600_constbuf_state *state,
1746 unsigned buffer_id_base,
1747 unsigned reg_alu_constbuf_size,
1748 unsigned reg_alu_const_cache)
1749 {
1750 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1751 uint32_t dirty_mask = state->dirty_mask;
1752
1753 while (dirty_mask) {
1754 struct pipe_constant_buffer *cb;
1755 struct r600_resource *rbuffer;
1756 unsigned offset;
1757 unsigned buffer_index = ffs(dirty_mask) - 1;
1758 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1759 cb = &state->cb[buffer_index];
1760 rbuffer = (struct r600_resource*)cb->buffer;
1761 assert(rbuffer);
1762
1763 offset = cb->buffer_offset;
1764
1765 if (!gs_ring_buffer) {
1766 radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1767 DIV_ROUND_UP(cb->buffer_size, 256));
1768 radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1769 }
1770
1771 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1772 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1773 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1774
1775 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1776 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
1777 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1778 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1779 radeon_emit(cs, /* RESOURCEi_WORD2 */
1780 S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1781 S_038008_STRIDE(gs_ring_buffer ? 4 : 16));
1782 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1783 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1784 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1785 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1786
1787 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1788 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1789 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1790
1791 dirty_mask &= ~(1 << buffer_index);
1792 }
1793 state->dirty_mask = 0;
1794 }
1795
1796 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1797 {
1798 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1799 R600_FETCH_CONSTANTS_OFFSET_VS,
1800 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1801 R_028980_ALU_CONST_CACHE_VS_0);
1802 }
1803
1804 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1805 {
1806 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1807 R600_FETCH_CONSTANTS_OFFSET_GS,
1808 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1809 R_0289C0_ALU_CONST_CACHE_GS_0);
1810 }
1811
1812 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1813 {
1814 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1815 R600_FETCH_CONSTANTS_OFFSET_PS,
1816 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1817 R_028940_ALU_CONST_CACHE_PS_0);
1818 }
1819
1820 static void r600_emit_sampler_views(struct r600_context *rctx,
1821 struct r600_samplerview_state *state,
1822 unsigned resource_id_base)
1823 {
1824 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1825 uint32_t dirty_mask = state->dirty_mask;
1826
1827 while (dirty_mask) {
1828 struct r600_pipe_sampler_view *rview;
1829 unsigned resource_index = u_bit_scan(&dirty_mask);
1830 unsigned reloc;
1831
1832 rview = state->views[resource_index];
1833 assert(rview);
1834
1835 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1836 radeon_emit(cs, (resource_id_base + resource_index) * 7);
1837 radeon_emit_array(cs, rview->tex_resource_words, 7);
1838
1839 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
1840 RADEON_USAGE_READ,
1841 r600_get_sampler_view_priority(rview->tex_resource));
1842 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1843 radeon_emit(cs, reloc);
1844 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1845 radeon_emit(cs, reloc);
1846 }
1847 state->dirty_mask = 0;
1848 }
1849
1850
1851 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1852 {
1853 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, R600_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS);
1854 }
1855
1856 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1857 {
1858 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, R600_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS);
1859 }
1860
1861 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1862 {
1863 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS);
1864 }
1865
1866 static void r600_emit_sampler_states(struct r600_context *rctx,
1867 struct r600_textures_info *texinfo,
1868 unsigned resource_id_base,
1869 unsigned border_color_reg)
1870 {
1871 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1872 uint32_t dirty_mask = texinfo->states.dirty_mask;
1873
1874 while (dirty_mask) {
1875 struct r600_pipe_sampler_state *rstate;
1876 struct r600_pipe_sampler_view *rview;
1877 unsigned i = u_bit_scan(&dirty_mask);
1878
1879 rstate = texinfo->states.states[i];
1880 assert(rstate);
1881 rview = texinfo->views.views[i];
1882
1883 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1884 * filtering between layers.
1885 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1886 */
1887 if (rview) {
1888 enum pipe_texture_target target = rview->base.texture->target;
1889 if (target == PIPE_TEXTURE_1D_ARRAY ||
1890 target == PIPE_TEXTURE_2D_ARRAY) {
1891 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1892 texinfo->is_array_sampler[i] = true;
1893 } else {
1894 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1895 texinfo->is_array_sampler[i] = false;
1896 }
1897 }
1898
1899 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1900 radeon_emit(cs, (resource_id_base + i) * 3);
1901 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
1902
1903 if (rstate->border_color_use) {
1904 unsigned offset;
1905
1906 offset = border_color_reg;
1907 offset += i * 16;
1908 radeon_set_config_reg_seq(cs, offset, 4);
1909 radeon_emit_array(cs, rstate->border_color.ui, 4);
1910 }
1911 }
1912 texinfo->states.dirty_mask = 0;
1913 }
1914
1915 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1916 {
1917 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1918 }
1919
1920 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1921 {
1922 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1923 }
1924
1925 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1926 {
1927 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1928 }
1929
1930 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1931 {
1932 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1933 unsigned tmp;
1934
1935 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1936 S_009508_SYNC_GRADIENT(1) |
1937 S_009508_SYNC_WALKER(1) |
1938 S_009508_SYNC_ALIGNER(1);
1939 if (!rctx->seamless_cube_map.enabled) {
1940 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1941 }
1942 radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1943 }
1944
1945 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1946 {
1947 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1948 uint8_t mask = s->sample_mask;
1949
1950 radeon_set_context_reg(rctx->b.gfx.cs, R_028C48_PA_SC_AA_MASK,
1951 mask | (mask << 8) | (mask << 16) | (mask << 24));
1952 }
1953
1954 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
1955 {
1956 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1957 struct r600_cso_state *state = (struct r600_cso_state*)a;
1958 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
1959
1960 radeon_set_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
1961 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1962 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
1963 RADEON_USAGE_READ,
1964 RADEON_PRIO_INTERNAL_SHADER));
1965 }
1966
1967 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
1968 {
1969 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
1970 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
1971
1972 uint32_t v2 = 0, primid = 0;
1973
1974 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
1975 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1976 primid = 1;
1977 }
1978
1979 if (state->geom_enable) {
1980 uint32_t cut_val;
1981
1982 if (rctx->gs_shader->gs_max_out_vertices <= 128)
1983 cut_val = V_028A40_GS_CUT_128;
1984 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
1985 cut_val = V_028A40_GS_CUT_256;
1986 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
1987 cut_val = V_028A40_GS_CUT_512;
1988 else
1989 cut_val = V_028A40_GS_CUT_1024;
1990
1991 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1992 S_028A40_CUT_MODE(cut_val);
1993
1994 if (rctx->gs_shader->current->shader.gs_prim_id_input)
1995 primid = 1;
1996 }
1997
1998 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
1999 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2000 }
2001
2002 static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2003 {
2004 struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
2005 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2006 struct r600_resource *rbuffer;
2007
2008 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2009 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2010 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2011
2012 if (state->enable) {
2013 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2014 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
2015 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2016 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2017 RADEON_USAGE_READWRITE,
2018 RADEON_PRIO_RINGS_STREAMOUT));
2019 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2020 state->esgs_ring.buffer_size >> 8);
2021
2022 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2023 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
2024 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2025 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2026 RADEON_USAGE_READWRITE,
2027 RADEON_PRIO_RINGS_STREAMOUT));
2028 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2029 state->gsvs_ring.buffer_size >> 8);
2030 } else {
2031 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2032 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2033 }
2034
2035 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2036 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2037 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2038 }
2039
2040 /* Adjust GPR allocation on R6xx/R7xx */
2041 bool r600_adjust_gprs(struct r600_context *rctx)
2042 {
2043 unsigned num_gprs[R600_NUM_HW_STAGES];
2044 unsigned new_gprs[R600_NUM_HW_STAGES];
2045 unsigned cur_gprs[R600_NUM_HW_STAGES];
2046 unsigned def_gprs[R600_NUM_HW_STAGES];
2047 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
2048 unsigned max_gprs;
2049 unsigned tmp, tmp2;
2050 unsigned i;
2051 bool need_recalc = false, use_default = true;
2052
2053 /* hardware will reserve twice num_clause_temp_gprs */
2054 max_gprs = def_num_clause_temp_gprs * 2;
2055 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2056 def_gprs[i] = rctx->default_gprs[i];
2057 max_gprs += def_gprs[i];
2058 }
2059
2060 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2061 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2062 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2063 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2064
2065 num_gprs[R600_HW_STAGE_PS] = rctx->ps_shader->current->shader.bc.ngpr;
2066 if (rctx->gs_shader) {
2067 num_gprs[R600_HW_STAGE_ES] = rctx->vs_shader->current->shader.bc.ngpr;
2068 num_gprs[R600_HW_STAGE_GS] = rctx->gs_shader->current->shader.bc.ngpr;
2069 num_gprs[R600_HW_STAGE_VS] = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
2070 } else {
2071 num_gprs[R600_HW_STAGE_ES] = 0;
2072 num_gprs[R600_HW_STAGE_GS] = 0;
2073 num_gprs[R600_HW_STAGE_VS] = rctx->vs_shader->current->shader.bc.ngpr;
2074 }
2075
2076 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2077 new_gprs[i] = num_gprs[i];
2078 if (new_gprs[i] > cur_gprs[i])
2079 need_recalc = true;
2080 if (new_gprs[i] > def_gprs[i])
2081 use_default = false;
2082 }
2083
2084 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2085 if (!need_recalc)
2086 return true;
2087
2088 /* try to use switch back to default */
2089 if (!use_default) {
2090 /* always privilege vs stage so that at worst we have the
2091 * pixel stage producing wrong output (not the vertex
2092 * stage) */
2093 new_gprs[R600_HW_STAGE_PS] = max_gprs - def_num_clause_temp_gprs * 2;
2094 for (i = R600_HW_STAGE_VS; i < R600_NUM_HW_STAGES; i++)
2095 new_gprs[R600_HW_STAGE_PS] -= new_gprs[i];
2096 } else {
2097 for (i = 0; i < R600_NUM_HW_STAGES; i++)
2098 new_gprs[i] = def_gprs[i];
2099 }
2100
2101 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2102 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2103 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2104 * it will lockup. So in this case just discard the draw command
2105 * and don't change the current gprs repartitions.
2106 */
2107 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2108 if (num_gprs[i] > new_gprs[i]) {
2109 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2110 "for a combined maximum of %d\n",
2111 num_gprs[R600_HW_STAGE_PS], num_gprs[R600_HW_STAGE_VS], num_gprs[R600_HW_STAGE_ES], num_gprs[R600_HW_STAGE_GS], max_gprs);
2112 return false;
2113 }
2114 }
2115
2116 /* in some case we endup recomputing the current value */
2117 tmp = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
2118 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
2119 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2120
2121 tmp2 = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
2122 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
2123 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2124 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2125 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2;
2126 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
2127 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2128 }
2129 return true;
2130 }
2131
2132 void r600_init_atom_start_cs(struct r600_context *rctx)
2133 {
2134 int ps_prio;
2135 int vs_prio;
2136 int gs_prio;
2137 int es_prio;
2138 int num_ps_gprs;
2139 int num_vs_gprs;
2140 int num_gs_gprs;
2141 int num_es_gprs;
2142 int num_temp_gprs;
2143 int num_ps_threads;
2144 int num_vs_threads;
2145 int num_gs_threads;
2146 int num_es_threads;
2147 int num_ps_stack_entries;
2148 int num_vs_stack_entries;
2149 int num_gs_stack_entries;
2150 int num_es_stack_entries;
2151 enum radeon_family family;
2152 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2153 uint32_t tmp, i;
2154
2155 r600_init_command_buffer(cb, 256);
2156
2157 /* R6xx requires this packet at the start of each command buffer */
2158 if (rctx->b.chip_class == R600) {
2159 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2160 r600_store_value(cb, 0);
2161 }
2162 /* All asics require this one */
2163 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2164 r600_store_value(cb, 0x80000000);
2165 r600_store_value(cb, 0x80000000);
2166
2167 /* We're setting config registers here. */
2168 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2169 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2170
2171 family = rctx->b.family;
2172 ps_prio = 0;
2173 vs_prio = 1;
2174 gs_prio = 2;
2175 es_prio = 3;
2176 switch (family) {
2177 case CHIP_R600:
2178 num_ps_gprs = 192;
2179 num_vs_gprs = 56;
2180 num_temp_gprs = 4;
2181 num_gs_gprs = 0;
2182 num_es_gprs = 0;
2183 num_ps_threads = 136;
2184 num_vs_threads = 48;
2185 num_gs_threads = 4;
2186 num_es_threads = 4;
2187 num_ps_stack_entries = 128;
2188 num_vs_stack_entries = 128;
2189 num_gs_stack_entries = 0;
2190 num_es_stack_entries = 0;
2191 break;
2192 case CHIP_RV630:
2193 case CHIP_RV635:
2194 num_ps_gprs = 84;
2195 num_vs_gprs = 36;
2196 num_temp_gprs = 4;
2197 num_gs_gprs = 0;
2198 num_es_gprs = 0;
2199 num_ps_threads = 144;
2200 num_vs_threads = 40;
2201 num_gs_threads = 4;
2202 num_es_threads = 4;
2203 num_ps_stack_entries = 40;
2204 num_vs_stack_entries = 40;
2205 num_gs_stack_entries = 32;
2206 num_es_stack_entries = 16;
2207 break;
2208 case CHIP_RV610:
2209 case CHIP_RV620:
2210 case CHIP_RS780:
2211 case CHIP_RS880:
2212 default:
2213 num_ps_gprs = 84;
2214 num_vs_gprs = 36;
2215 num_temp_gprs = 4;
2216 num_gs_gprs = 0;
2217 num_es_gprs = 0;
2218 /* use limits 40 VS and at least 16 ES/GS */
2219 num_ps_threads = 120;
2220 num_vs_threads = 40;
2221 num_gs_threads = 16;
2222 num_es_threads = 16;
2223 num_ps_stack_entries = 40;
2224 num_vs_stack_entries = 40;
2225 num_gs_stack_entries = 32;
2226 num_es_stack_entries = 16;
2227 break;
2228 case CHIP_RV670:
2229 num_ps_gprs = 144;
2230 num_vs_gprs = 40;
2231 num_temp_gprs = 4;
2232 num_gs_gprs = 0;
2233 num_es_gprs = 0;
2234 num_ps_threads = 136;
2235 num_vs_threads = 48;
2236 num_gs_threads = 4;
2237 num_es_threads = 4;
2238 num_ps_stack_entries = 40;
2239 num_vs_stack_entries = 40;
2240 num_gs_stack_entries = 32;
2241 num_es_stack_entries = 16;
2242 break;
2243 case CHIP_RV770:
2244 num_ps_gprs = 130;
2245 num_vs_gprs = 56;
2246 num_temp_gprs = 4;
2247 num_gs_gprs = 31;
2248 num_es_gprs = 31;
2249 num_ps_threads = 180;
2250 num_vs_threads = 60;
2251 num_gs_threads = 4;
2252 num_es_threads = 4;
2253 num_ps_stack_entries = 128;
2254 num_vs_stack_entries = 128;
2255 num_gs_stack_entries = 128;
2256 num_es_stack_entries = 128;
2257 break;
2258 case CHIP_RV730:
2259 case CHIP_RV740:
2260 num_ps_gprs = 84;
2261 num_vs_gprs = 36;
2262 num_temp_gprs = 4;
2263 num_gs_gprs = 0;
2264 num_es_gprs = 0;
2265 num_ps_threads = 180;
2266 num_vs_threads = 60;
2267 num_gs_threads = 4;
2268 num_es_threads = 4;
2269 num_ps_stack_entries = 128;
2270 num_vs_stack_entries = 128;
2271 num_gs_stack_entries = 0;
2272 num_es_stack_entries = 0;
2273 break;
2274 case CHIP_RV710:
2275 num_ps_gprs = 192;
2276 num_vs_gprs = 56;
2277 num_temp_gprs = 4;
2278 num_gs_gprs = 0;
2279 num_es_gprs = 0;
2280 num_ps_threads = 136;
2281 num_vs_threads = 48;
2282 num_gs_threads = 4;
2283 num_es_threads = 4;
2284 num_ps_stack_entries = 128;
2285 num_vs_stack_entries = 128;
2286 num_gs_stack_entries = 0;
2287 num_es_stack_entries = 0;
2288 break;
2289 }
2290
2291 rctx->default_gprs[R600_HW_STAGE_PS] = num_ps_gprs;
2292 rctx->default_gprs[R600_HW_STAGE_VS] = num_vs_gprs;
2293 rctx->default_gprs[R600_HW_STAGE_GS] = 0;
2294 rctx->default_gprs[R600_HW_STAGE_ES] = 0;
2295
2296 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2297
2298 /* SQ_CONFIG */
2299 tmp = 0;
2300 switch (family) {
2301 case CHIP_RV610:
2302 case CHIP_RV620:
2303 case CHIP_RS780:
2304 case CHIP_RS880:
2305 case CHIP_RV710:
2306 break;
2307 default:
2308 tmp |= S_008C00_VC_ENABLE(1);
2309 break;
2310 }
2311 tmp |= S_008C00_DX9_CONSTS(0);
2312 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2313 tmp |= S_008C00_PS_PRIO(ps_prio);
2314 tmp |= S_008C00_VS_PRIO(vs_prio);
2315 tmp |= S_008C00_GS_PRIO(gs_prio);
2316 tmp |= S_008C00_ES_PRIO(es_prio);
2317 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2318
2319 /* SQ_GPR_RESOURCE_MGMT_2 */
2320 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2321 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2322 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2323 r600_store_value(cb, tmp);
2324
2325 /* SQ_THREAD_RESOURCE_MGMT */
2326 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2327 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2328 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2329 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2330 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2331
2332 /* SQ_STACK_RESOURCE_MGMT_1 */
2333 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2334 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2335 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2336
2337 /* SQ_STACK_RESOURCE_MGMT_2 */
2338 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2339 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2340 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2341
2342 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2343
2344 if (rctx->b.chip_class >= R700) {
2345 r600_store_context_reg(cb, R_028A50_VGT_ENHANCE, 4);
2346 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2347 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2348 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2349 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2350 } else {
2351 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2352 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2353 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2354 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2355 }
2356 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2357 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2358 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2359 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2360 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2361 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2362 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2363 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2364 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2365 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2366
2367 /* to avoid GPU doing any preloading of constant from random address */
2368 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2369 for (i = 0; i < 16; i++)
2370 r600_store_value(cb, 0);
2371
2372 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2373 for (i = 0; i < 16; i++)
2374 r600_store_value(cb, 0);
2375
2376 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2377 for (i = 0; i < 16; i++)
2378 r600_store_value(cb, 0);
2379
2380 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2381 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2382 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2383 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2384 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2385 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2386 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2387 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2388 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2389 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2390 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2391 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2392 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2393 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2394
2395 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2396 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2397 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2398
2399 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2400 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2401 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2402
2403 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2404
2405 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2406
2407 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2408
2409 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2410 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2411 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2412 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2413
2414 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2415 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2416 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2417 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2418
2419 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2420 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2421
2422 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2423 r600_store_value(cb, fui(1.0)); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2424 r600_store_value(cb, fui(1.0)); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2425 r600_store_value(cb, fui(1.0)); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2426 r600_store_value(cb, fui(1.0)); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2427
2428 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS);
2429 for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) {
2430 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2431 r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2432 }
2433
2434 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2435 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2436
2437 if (rctx->b.chip_class >= R700) {
2438 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2439 }
2440
2441 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2442 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2443 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2444 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2445 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2446
2447 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2448 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2449 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2450
2451 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2452 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2453 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2454
2455 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5);
2456 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2457 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2458 r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2459 r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2460 r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2461
2462 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2463
2464 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2465 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2466 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2467
2468 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2469
2470 if (rctx->b.chip_class == R700)
2471 r600_store_context_reg(cb, R_028350_SX_MISC, 0);
2472 if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
2473 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2474
2475 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2476 if (rctx->screen->b.has_streamout) {
2477 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2478 }
2479
2480 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2481 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2482 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF);
2483 }
2484
2485 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2486 {
2487 struct r600_context *rctx = (struct r600_context *)ctx;
2488 struct r600_command_buffer *cb = &shader->command_buffer;
2489 struct r600_shader *rshader = &shader->shader;
2490 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2491 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2492 unsigned tmp, sid, ufi = 0;
2493 int need_linear = 0;
2494 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2495 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2496
2497 if (!cb->buf) {
2498 r600_init_command_buffer(cb, 64);
2499 } else {
2500 cb->num_dw = 0;
2501 }
2502
2503 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2504 for (i = 0; i < rshader->ninput; i++) {
2505 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2506 pos_index = i;
2507 if (rshader->input[i].name == TGSI_SEMANTIC_FACE && face_index == -1)
2508 face_index = i;
2509 if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID)
2510 fixed_pt_position_index = i;
2511
2512 sid = rshader->input[i].spi_sid;
2513
2514 tmp = S_028644_SEMANTIC(sid);
2515
2516 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2517 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2518 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2519 rctx->rasterizer && rctx->rasterizer->flatshade))
2520 tmp |= S_028644_FLAT_SHADE(1);
2521
2522 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2523 sprite_coord_enable & (1 << rshader->input[i].sid)) {
2524 tmp |= S_028644_PT_SPRITE_TEX(1);
2525 }
2526
2527 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID)
2528 tmp |= S_028644_SEL_CENTROID(1);
2529
2530 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE)
2531 tmp |= S_028644_SEL_SAMPLE(1);
2532
2533 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2534 need_linear = 1;
2535 tmp |= S_028644_SEL_LINEAR(1);
2536 }
2537
2538 r600_store_value(cb, tmp);
2539 }
2540
2541 db_shader_control = 0;
2542 for (i = 0; i < rshader->noutput; i++) {
2543 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2544 z_export = 1;
2545 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2546 stencil_export = 1;
2547 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
2548 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
2549 mask_export = 1;
2550 }
2551 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2552 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2553 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
2554 if (rshader->uses_kill)
2555 db_shader_control |= S_02880C_KILL_ENABLE(1);
2556
2557 exports_ps = 0;
2558 for (i = 0; i < rshader->noutput; i++) {
2559 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2560 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
2561 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2562 exports_ps |= 1;
2563 }
2564 }
2565 num_cout = rshader->nr_ps_color_exports;
2566 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2567 if (!exports_ps) {
2568 /* always at least export 1 component per pixel */
2569 exports_ps = 2;
2570 }
2571
2572 shader->nr_ps_color_outputs = num_cout;
2573
2574 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2575 S_0286CC_PERSP_GRADIENT_ENA(1)|
2576 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2577 spi_input_z = 0;
2578 if (pos_index != -1) {
2579 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2580 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
2581 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2582 S_0286CC_BARYC_SAMPLE_CNTL(1)) |
2583 S_0286CC_POSITION_SAMPLE(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE);
2584 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2585 }
2586
2587 spi_ps_in_control_1 = 0;
2588 if (face_index != -1) {
2589 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2590 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2591 }
2592 if (fixed_pt_position_index != -1) {
2593 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
2594 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
2595 }
2596
2597 /* HW bug in original R600 */
2598 if (rctx->b.family == CHIP_R600)
2599 ufi = 1;
2600
2601 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2602 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2603 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2604
2605 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2606
2607 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2608 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2609 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2610 S_028850_STACK_SIZE(rshader->bc.nstack) |
2611 S_028850_UNCACHED_FIRST_INST(ufi));
2612 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2613
2614 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2615 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2616
2617 /* only set some bits here, the other bits are set in the dsa state */
2618 shader->db_shader_control = db_shader_control;
2619 shader->ps_depth_export = z_export | stencil_export | mask_export;
2620
2621 shader->sprite_coord_enable = sprite_coord_enable;
2622 if (rctx->rasterizer)
2623 shader->flatshade = rctx->rasterizer->flatshade;
2624 }
2625
2626 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2627 {
2628 struct r600_command_buffer *cb = &shader->command_buffer;
2629 struct r600_shader *rshader = &shader->shader;
2630 unsigned spi_vs_out_id[10] = {};
2631 unsigned i, tmp, nparams = 0;
2632
2633 for (i = 0; i < rshader->noutput; i++) {
2634 if (rshader->output[i].spi_sid) {
2635 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2636 spi_vs_out_id[nparams / 4] |= tmp;
2637 nparams++;
2638 }
2639 }
2640
2641 r600_init_command_buffer(cb, 32);
2642
2643 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2644 for (i = 0; i < 10; i++) {
2645 r600_store_value(cb, spi_vs_out_id[i]);
2646 }
2647
2648 /* Certain attributes (position, psize, etc.) don't count as params.
2649 * VS is required to export at least one param and r600_shader_from_tgsi()
2650 * takes care of adding a dummy export.
2651 */
2652 if (nparams < 1)
2653 nparams = 1;
2654
2655 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2656 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2657 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2658 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2659 S_028868_STACK_SIZE(rshader->bc.nstack));
2660 if (rshader->vs_position_window_space) {
2661 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2662 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
2663 } else {
2664 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2665 S_028818_VTX_W0_FMT(1) |
2666 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2667 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2668 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2669
2670 }
2671 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2672 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2673
2674 shader->pa_cl_vs_out_cntl =
2675 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2676 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2677 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2678 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
2679 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
2680 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) |
2681 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport);
2682 }
2683
2684 #define RV610_GSVS_ALIGN 32
2685 #define R600_GSVS_ALIGN 16
2686
2687 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2688 {
2689 struct r600_context *rctx = (struct r600_context *)ctx;
2690 struct r600_command_buffer *cb = &shader->command_buffer;
2691 struct r600_shader *rshader = &shader->shader;
2692 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
2693 unsigned gsvs_itemsize =
2694 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2;
2695
2696 /* some r600s needs gsvs itemsize aligned to cacheline size
2697 this was fixed in rs780 and above. */
2698 switch (rctx->b.family) {
2699 case CHIP_RV610:
2700 gsvs_itemsize = align(gsvs_itemsize, RV610_GSVS_ALIGN);
2701 break;
2702 case CHIP_R600:
2703 case CHIP_RV630:
2704 case CHIP_RV670:
2705 case CHIP_RV620:
2706 case CHIP_RV635:
2707 gsvs_itemsize = align(gsvs_itemsize, R600_GSVS_ALIGN);
2708 break;
2709 default:
2710 break;
2711 }
2712
2713 r600_init_command_buffer(cb, 64);
2714
2715 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2716 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
2717
2718 if (rctx->b.chip_class >= R700) {
2719 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
2720 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
2721 }
2722 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
2723 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
2724
2725 r600_store_context_reg(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE,
2726 cp_shader->ring_item_sizes[0] >> 2);
2727
2728 r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
2729 (rshader->ring_item_sizes[0]) >> 2);
2730
2731 r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE,
2732 gsvs_itemsize);
2733
2734 /* FIXME calculate these values somehow ??? */
2735 r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2);
2736 r600_store_value(cb, 0x80); /* GS_PER_ES */
2737 r600_store_value(cb, 0x100); /* ES_PER_GS */
2738 r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1);
2739 r600_store_value(cb, 0x2); /* GS_PER_VS */
2740
2741 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS,
2742 S_02887C_NUM_GPRS(rshader->bc.ngpr) |
2743 S_02887C_STACK_SIZE(rshader->bc.nstack));
2744 r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, 0);
2745 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2746 }
2747
2748 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2749 {
2750 struct r600_command_buffer *cb = &shader->command_buffer;
2751 struct r600_shader *rshader = &shader->shader;
2752
2753 r600_init_command_buffer(cb, 32);
2754
2755 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
2756 S_028890_NUM_GPRS(rshader->bc.ngpr) |
2757 S_028890_STACK_SIZE(rshader->bc.nstack));
2758 r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, 0);
2759 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2760 }
2761
2762
2763 void *r600_create_resolve_blend(struct r600_context *rctx)
2764 {
2765 struct pipe_blend_state blend;
2766 unsigned i;
2767
2768 memset(&blend, 0, sizeof(blend));
2769 blend.independent_blend_enable = true;
2770 for (i = 0; i < 2; i++) {
2771 blend.rt[i].colormask = 0xf;
2772 blend.rt[i].blend_enable = 1;
2773 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2774 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2775 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2776 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2777 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2778 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2779 }
2780 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2781 }
2782
2783 void *r700_create_resolve_blend(struct r600_context *rctx)
2784 {
2785 struct pipe_blend_state blend;
2786
2787 memset(&blend, 0, sizeof(blend));
2788 blend.independent_blend_enable = true;
2789 blend.rt[0].colormask = 0xf;
2790 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2791 }
2792
2793 void *r600_create_decompress_blend(struct r600_context *rctx)
2794 {
2795 struct pipe_blend_state blend;
2796
2797 memset(&blend, 0, sizeof(blend));
2798 blend.independent_blend_enable = true;
2799 blend.rt[0].colormask = 0xf;
2800 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2801 }
2802
2803 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2804 {
2805 struct pipe_depth_stencil_alpha_state dsa;
2806 boolean quirk = false;
2807
2808 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2809 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2810 quirk = true;
2811
2812 memset(&dsa, 0, sizeof(dsa));
2813
2814 if (quirk) {
2815 dsa.depth.enabled = 1;
2816 dsa.depth.func = PIPE_FUNC_LEQUAL;
2817 dsa.stencil[0].enabled = 1;
2818 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2819 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2820 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2821 dsa.stencil[0].writemask = 0xff;
2822 }
2823
2824 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2825 }
2826
2827 void r600_update_db_shader_control(struct r600_context * rctx)
2828 {
2829 bool dual_export;
2830 unsigned db_shader_control;
2831 uint8_t ps_conservative_z;
2832
2833 if (!rctx->ps_shader) {
2834 return;
2835 }
2836
2837 dual_export = rctx->framebuffer.export_16bpc &&
2838 !rctx->ps_shader->current->ps_depth_export;
2839
2840 db_shader_control = rctx->ps_shader->current->db_shader_control |
2841 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2842
2843 ps_conservative_z = rctx->ps_shader->current->shader.ps_conservative_z;
2844
2845 /* When alpha test is enabled we can't trust the hw to make the proper
2846 * decision on the order in which ztest should be run related to fragment
2847 * shader execution.
2848 *
2849 * If alpha test is enabled perform z test after fragment. RE_Z (early
2850 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2851 */
2852 if (rctx->alphatest_state.sx_alpha_test_control) {
2853 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2854 } else {
2855 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2856 }
2857
2858 if (db_shader_control != rctx->db_misc_state.db_shader_control ||
2859 ps_conservative_z != rctx->db_misc_state.ps_conservative_z) {
2860 rctx->db_misc_state.db_shader_control = db_shader_control;
2861 rctx->db_misc_state.ps_conservative_z = ps_conservative_z;
2862 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
2863 }
2864 }
2865
2866 static inline unsigned r600_array_mode(unsigned mode)
2867 {
2868 switch (mode) {
2869 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
2870 break;
2871 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
2872 break;
2873 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
2874 default:
2875 case RADEON_SURF_MODE_LINEAR: return V_0280A0_ARRAY_LINEAR_GENERAL;
2876 }
2877 }
2878
2879 static boolean r600_dma_copy_tile(struct r600_context *rctx,
2880 struct pipe_resource *dst,
2881 unsigned dst_level,
2882 unsigned dst_x,
2883 unsigned dst_y,
2884 unsigned dst_z,
2885 struct pipe_resource *src,
2886 unsigned src_level,
2887 unsigned src_x,
2888 unsigned src_y,
2889 unsigned src_z,
2890 unsigned copy_height,
2891 unsigned pitch,
2892 unsigned bpp)
2893 {
2894 struct radeon_winsys_cs *cs = rctx->b.dma.cs;
2895 struct r600_texture *rsrc = (struct r600_texture*)src;
2896 struct r600_texture *rdst = (struct r600_texture*)dst;
2897 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
2898 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
2899 uint64_t base, addr;
2900
2901 dst_mode = rdst->surface.level[dst_level].mode;
2902 src_mode = rsrc->surface.level[src_level].mode;
2903 /* downcast linear aligned to linear to simplify test */
2904 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
2905 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
2906 assert(dst_mode != src_mode);
2907
2908 y = 0;
2909 lbpp = util_logbase2(bpp);
2910 pitch_tile_max = ((pitch / bpp) / 8) - 1;
2911
2912 if (dst_mode == RADEON_SURF_MODE_LINEAR) {
2913 /* T2L */
2914 array_mode = r600_array_mode(src_mode);
2915 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
2916 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2917 /* linear height must be the same as the slice tile max height, it's ok even
2918 * if the linear destination/source have smaller heigh as the size of the
2919 * dma packet will be using the copy_height which is always smaller or equal
2920 * to the linear height
2921 */
2922 height = rsrc->surface.level[src_level].npix_y;
2923 detile = 1;
2924 x = src_x;
2925 y = src_y;
2926 z = src_z;
2927 base = rsrc->surface.level[src_level].offset;
2928 addr = rdst->surface.level[dst_level].offset;
2929 addr += rdst->surface.level[dst_level].slice_size * dst_z;
2930 addr += dst_y * pitch + dst_x * bpp;
2931 } else {
2932 /* L2T */
2933 array_mode = r600_array_mode(dst_mode);
2934 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
2935 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2936 /* linear height must be the same as the slice tile max height, it's ok even
2937 * if the linear destination/source have smaller heigh as the size of the
2938 * dma packet will be using the copy_height which is always smaller or equal
2939 * to the linear height
2940 */
2941 height = rdst->surface.level[dst_level].npix_y;
2942 detile = 0;
2943 x = dst_x;
2944 y = dst_y;
2945 z = dst_z;
2946 base = rdst->surface.level[dst_level].offset;
2947 addr = rsrc->surface.level[src_level].offset;
2948 addr += rsrc->surface.level[src_level].slice_size * src_z;
2949 addr += src_y * pitch + src_x * bpp;
2950 }
2951 /* check that we are in dw/base alignment constraint */
2952 if (addr % 4 || base % 256) {
2953 return FALSE;
2954 }
2955
2956 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2957 * line in the blit. Compute max 8 line we can copy in the size limit
2958 */
2959 cheight = ((R600_DMA_COPY_MAX_SIZE_DW * 4) / pitch) & 0xfffffff8;
2960 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
2961 r600_need_dma_space(&rctx->b, ncopy * 7);
2962
2963 for (i = 0; i < ncopy; i++) {
2964 cheight = cheight > copy_height ? copy_height : cheight;
2965 size = (cheight * pitch) / 4;
2966 /* emit reloc before writing cs so that cs is always in consistent state */
2967 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, RADEON_USAGE_READ,
2968 RADEON_PRIO_SDMA_TEXTURE);
2969 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE,
2970 RADEON_PRIO_SDMA_TEXTURE);
2971 cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 1, 0, size);
2972 cs->buf[cs->cdw++] = base >> 8;
2973 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
2974 (lbpp << 24) | ((height - 1) << 10) |
2975 pitch_tile_max;
2976 cs->buf[cs->cdw++] = (slice_tile_max << 12) | (z << 0);
2977 cs->buf[cs->cdw++] = (x << 3) | (y << 17);
2978 cs->buf[cs->cdw++] = addr & 0xfffffffc;
2979 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
2980 copy_height -= cheight;
2981 addr += cheight * pitch;
2982 y += cheight;
2983 }
2984 return TRUE;
2985 }
2986
2987 static void r600_dma_copy(struct pipe_context *ctx,
2988 struct pipe_resource *dst,
2989 unsigned dst_level,
2990 unsigned dstx, unsigned dsty, unsigned dstz,
2991 struct pipe_resource *src,
2992 unsigned src_level,
2993 const struct pipe_box *src_box)
2994 {
2995 struct r600_context *rctx = (struct r600_context *)ctx;
2996 struct r600_texture *rsrc = (struct r600_texture*)src;
2997 struct r600_texture *rdst = (struct r600_texture*)dst;
2998 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
2999 unsigned src_w, dst_w;
3000 unsigned src_x, src_y;
3001 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3002
3003 if (rctx->b.dma.cs == NULL) {
3004 goto fallback;
3005 }
3006
3007 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3008 if (dst_x % 4 || src_box->x % 4 || src_box->width % 4)
3009 goto fallback;
3010
3011 r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3012 return;
3013 }
3014
3015 if (src->format != dst->format || src_box->depth > 1) {
3016 goto fallback;
3017 }
3018
3019 src_x = util_format_get_nblocksx(src->format, src_box->x);
3020 dst_x = util_format_get_nblocksx(src->format, dst_x);
3021 src_y = util_format_get_nblocksy(src->format, src_box->y);
3022 dst_y = util_format_get_nblocksy(src->format, dst_y);
3023
3024 bpp = rdst->surface.bpe;
3025 dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
3026 src_pitch = rsrc->surface.level[src_level].pitch_bytes;
3027 src_w = rsrc->surface.level[src_level].npix_x;
3028 dst_w = rdst->surface.level[dst_level].npix_x;
3029 copy_height = src_box->height / rsrc->surface.blk_h;
3030
3031 dst_mode = rdst->surface.level[dst_level].mode;
3032 src_mode = rsrc->surface.level[src_level].mode;
3033 /* downcast linear aligned to linear to simplify test */
3034 src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
3035 dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
3036
3037 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3038 /* strict requirement on r6xx/r7xx */
3039 goto fallback;
3040 }
3041 /* lot of constraint on alignment this should capture them all */
3042 if (src_pitch % 8 || src_box->y % 8 || dst_y % 8) {
3043 goto fallback;
3044 }
3045
3046 if (src_mode == dst_mode) {
3047 uint64_t dst_offset, src_offset, size;
3048
3049 /* simple dma blit would do NOTE code here assume :
3050 * src_box.x/y == 0
3051 * dst_x/y == 0
3052 * dst_pitch == src_pitch
3053 */
3054 src_offset= rsrc->surface.level[src_level].offset;
3055 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
3056 src_offset += src_y * src_pitch + src_x * bpp;
3057 dst_offset = rdst->surface.level[dst_level].offset;
3058 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
3059 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3060 size = src_box->height * src_pitch;
3061 /* must be dw aligned */
3062 if (dst_offset % 4 || src_offset % 4 || size % 4) {
3063 goto fallback;
3064 }
3065 r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size);
3066 } else {
3067 if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3068 src, src_level, src_x, src_y, src_box->z,
3069 copy_height, dst_pitch, bpp)) {
3070 goto fallback;
3071 }
3072 }
3073 return;
3074
3075 fallback:
3076 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3077 src, src_level, src_box);
3078 }
3079
3080 void r600_init_state_functions(struct r600_context *rctx)
3081 {
3082 unsigned id = 1;
3083 unsigned i;
3084 /* !!!
3085 * To avoid GPU lockup registers must be emited in a specific order
3086 * (no kidding ...). The order below is important and have been
3087 * partialy infered from analyzing fglrx command stream.
3088 *
3089 * Don't reorder atom without carefully checking the effect (GPU lockup
3090 * or piglit regression).
3091 * !!!
3092 */
3093
3094 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
3095
3096 /* shader const */
3097 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
3098 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
3099 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
3100
3101 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3102 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
3103 */
3104 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
3105 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
3106 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
3107 /* resource */
3108 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
3109 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
3110 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
3111 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
3112
3113 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3114
3115 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3116 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3117 rctx->sample_mask.sample_mask = ~0;
3118
3119 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3120 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3121 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3122 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3123 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3124 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3125 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3126 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3127 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3128 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
3129 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3130 r600_init_atom(rctx, &rctx->scissor.atom, id++, r600_emit_scissor_state, 0);
3131 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 0);
3132 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3133 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3134 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3135 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3136 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3137 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3138 for (i = 0; i < R600_NUM_HW_STAGES; i++)
3139 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3140 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0);
3141 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0);
3142
3143 rctx->b.b.create_blend_state = r600_create_blend_state;
3144 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3145 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3146 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3147 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3148 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3149 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3150 rctx->b.b.set_min_samples = r600_set_min_samples;
3151 rctx->b.b.set_scissor_states = r600_set_scissor_states;
3152 rctx->b.b.get_sample_position = r600_get_sample_position;
3153 rctx->b.dma_copy = r600_dma_copy;
3154 }
3155 /* this function must be last */