2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_formats.h"
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
32 static uint32_t r600_translate_blend_function(int blend_func
)
36 return V_028804_COMB_DST_PLUS_SRC
;
37 case PIPE_BLEND_SUBTRACT
:
38 return V_028804_COMB_SRC_MINUS_DST
;
39 case PIPE_BLEND_REVERSE_SUBTRACT
:
40 return V_028804_COMB_DST_MINUS_SRC
;
42 return V_028804_COMB_MIN_DST_SRC
;
44 return V_028804_COMB_MAX_DST_SRC
;
46 R600_ERR("Unknown blend function %d\n", blend_func
);
53 static uint32_t r600_translate_blend_factor(int blend_fact
)
56 case PIPE_BLENDFACTOR_ONE
:
57 return V_028804_BLEND_ONE
;
58 case PIPE_BLENDFACTOR_SRC_COLOR
:
59 return V_028804_BLEND_SRC_COLOR
;
60 case PIPE_BLENDFACTOR_SRC_ALPHA
:
61 return V_028804_BLEND_SRC_ALPHA
;
62 case PIPE_BLENDFACTOR_DST_ALPHA
:
63 return V_028804_BLEND_DST_ALPHA
;
64 case PIPE_BLENDFACTOR_DST_COLOR
:
65 return V_028804_BLEND_DST_COLOR
;
66 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
67 return V_028804_BLEND_SRC_ALPHA_SATURATE
;
68 case PIPE_BLENDFACTOR_CONST_COLOR
:
69 return V_028804_BLEND_CONST_COLOR
;
70 case PIPE_BLENDFACTOR_CONST_ALPHA
:
71 return V_028804_BLEND_CONST_ALPHA
;
72 case PIPE_BLENDFACTOR_ZERO
:
73 return V_028804_BLEND_ZERO
;
74 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
75 return V_028804_BLEND_ONE_MINUS_SRC_COLOR
;
76 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
77 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA
;
78 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
79 return V_028804_BLEND_ONE_MINUS_DST_ALPHA
;
80 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
81 return V_028804_BLEND_ONE_MINUS_DST_COLOR
;
82 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
83 return V_028804_BLEND_ONE_MINUS_CONST_COLOR
;
84 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
85 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA
;
86 case PIPE_BLENDFACTOR_SRC1_COLOR
:
87 return V_028804_BLEND_SRC1_COLOR
;
88 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
89 return V_028804_BLEND_SRC1_ALPHA
;
90 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
91 return V_028804_BLEND_INV_SRC1_COLOR
;
92 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
93 return V_028804_BLEND_INV_SRC1_ALPHA
;
95 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
102 static unsigned r600_tex_dim(unsigned dim
, unsigned nr_samples
)
106 case PIPE_TEXTURE_1D
:
107 return V_038000_SQ_TEX_DIM_1D
;
108 case PIPE_TEXTURE_1D_ARRAY
:
109 return V_038000_SQ_TEX_DIM_1D_ARRAY
;
110 case PIPE_TEXTURE_2D
:
111 case PIPE_TEXTURE_RECT
:
112 return nr_samples
> 1 ? V_038000_SQ_TEX_DIM_2D_MSAA
:
113 V_038000_SQ_TEX_DIM_2D
;
114 case PIPE_TEXTURE_2D_ARRAY
:
115 return nr_samples
> 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA
:
116 V_038000_SQ_TEX_DIM_2D_ARRAY
;
117 case PIPE_TEXTURE_3D
:
118 return V_038000_SQ_TEX_DIM_3D
;
119 case PIPE_TEXTURE_CUBE
:
120 return V_038000_SQ_TEX_DIM_CUBEMAP
;
124 static uint32_t r600_translate_dbformat(enum pipe_format format
)
127 case PIPE_FORMAT_Z16_UNORM
:
128 return V_028010_DEPTH_16
;
129 case PIPE_FORMAT_Z24X8_UNORM
:
130 return V_028010_DEPTH_X8_24
;
131 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
132 return V_028010_DEPTH_8_24
;
133 case PIPE_FORMAT_Z32_FLOAT
:
134 return V_028010_DEPTH_32_FLOAT
;
135 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
136 return V_028010_DEPTH_X24_8_32_FLOAT
;
142 static uint32_t r600_translate_colorswap(enum pipe_format format
)
146 case PIPE_FORMAT_A8_UNORM
:
147 case PIPE_FORMAT_A8_SNORM
:
148 case PIPE_FORMAT_A8_UINT
:
149 case PIPE_FORMAT_A8_SINT
:
150 case PIPE_FORMAT_A16_UNORM
:
151 case PIPE_FORMAT_A16_SNORM
:
152 case PIPE_FORMAT_A16_UINT
:
153 case PIPE_FORMAT_A16_SINT
:
154 case PIPE_FORMAT_A16_FLOAT
:
155 case PIPE_FORMAT_A32_UINT
:
156 case PIPE_FORMAT_A32_SINT
:
157 case PIPE_FORMAT_A32_FLOAT
:
158 case PIPE_FORMAT_R4A4_UNORM
:
159 return V_0280A0_SWAP_ALT_REV
;
160 case PIPE_FORMAT_I8_UNORM
:
161 case PIPE_FORMAT_I8_SNORM
:
162 case PIPE_FORMAT_I8_UINT
:
163 case PIPE_FORMAT_I8_SINT
:
164 case PIPE_FORMAT_L8_UNORM
:
165 case PIPE_FORMAT_L8_SNORM
:
166 case PIPE_FORMAT_L8_UINT
:
167 case PIPE_FORMAT_L8_SINT
:
168 case PIPE_FORMAT_L8_SRGB
:
169 case PIPE_FORMAT_L16_UNORM
:
170 case PIPE_FORMAT_L16_SNORM
:
171 case PIPE_FORMAT_L16_UINT
:
172 case PIPE_FORMAT_L16_SINT
:
173 case PIPE_FORMAT_L16_FLOAT
:
174 case PIPE_FORMAT_L32_UINT
:
175 case PIPE_FORMAT_L32_SINT
:
176 case PIPE_FORMAT_L32_FLOAT
:
177 case PIPE_FORMAT_I16_UNORM
:
178 case PIPE_FORMAT_I16_SNORM
:
179 case PIPE_FORMAT_I16_UINT
:
180 case PIPE_FORMAT_I16_SINT
:
181 case PIPE_FORMAT_I16_FLOAT
:
182 case PIPE_FORMAT_I32_UINT
:
183 case PIPE_FORMAT_I32_SINT
:
184 case PIPE_FORMAT_I32_FLOAT
:
185 case PIPE_FORMAT_R8_UNORM
:
186 case PIPE_FORMAT_R8_SNORM
:
187 case PIPE_FORMAT_R8_UINT
:
188 case PIPE_FORMAT_R8_SINT
:
189 return V_0280A0_SWAP_STD
;
191 case PIPE_FORMAT_L4A4_UNORM
:
192 case PIPE_FORMAT_A4R4_UNORM
:
193 return V_0280A0_SWAP_ALT
;
195 /* 16-bit buffers. */
196 case PIPE_FORMAT_B5G6R5_UNORM
:
197 return V_0280A0_SWAP_STD_REV
;
199 case PIPE_FORMAT_B5G5R5A1_UNORM
:
200 case PIPE_FORMAT_B5G5R5X1_UNORM
:
201 return V_0280A0_SWAP_ALT
;
203 case PIPE_FORMAT_B4G4R4A4_UNORM
:
204 case PIPE_FORMAT_B4G4R4X4_UNORM
:
205 return V_0280A0_SWAP_ALT
;
207 case PIPE_FORMAT_Z16_UNORM
:
208 return V_0280A0_SWAP_STD
;
210 case PIPE_FORMAT_L8A8_UNORM
:
211 case PIPE_FORMAT_L8A8_SNORM
:
212 case PIPE_FORMAT_L8A8_UINT
:
213 case PIPE_FORMAT_L8A8_SINT
:
214 case PIPE_FORMAT_L8A8_SRGB
:
215 case PIPE_FORMAT_L16A16_UNORM
:
216 case PIPE_FORMAT_L16A16_SNORM
:
217 case PIPE_FORMAT_L16A16_UINT
:
218 case PIPE_FORMAT_L16A16_SINT
:
219 case PIPE_FORMAT_L16A16_FLOAT
:
220 case PIPE_FORMAT_L32A32_UINT
:
221 case PIPE_FORMAT_L32A32_SINT
:
222 case PIPE_FORMAT_L32A32_FLOAT
:
223 return V_0280A0_SWAP_ALT
;
224 case PIPE_FORMAT_R8G8_UNORM
:
225 case PIPE_FORMAT_R8G8_SNORM
:
226 case PIPE_FORMAT_R8G8_UINT
:
227 case PIPE_FORMAT_R8G8_SINT
:
228 return V_0280A0_SWAP_STD
;
230 case PIPE_FORMAT_R16_UNORM
:
231 case PIPE_FORMAT_R16_SNORM
:
232 case PIPE_FORMAT_R16_UINT
:
233 case PIPE_FORMAT_R16_SINT
:
234 case PIPE_FORMAT_R16_FLOAT
:
235 return V_0280A0_SWAP_STD
;
237 /* 32-bit buffers. */
239 case PIPE_FORMAT_A8B8G8R8_SRGB
:
240 return V_0280A0_SWAP_STD_REV
;
241 case PIPE_FORMAT_B8G8R8A8_SRGB
:
242 return V_0280A0_SWAP_ALT
;
244 case PIPE_FORMAT_B8G8R8A8_UNORM
:
245 case PIPE_FORMAT_B8G8R8X8_UNORM
:
246 return V_0280A0_SWAP_ALT
;
248 case PIPE_FORMAT_A8R8G8B8_UNORM
:
249 case PIPE_FORMAT_X8R8G8B8_UNORM
:
250 return V_0280A0_SWAP_ALT_REV
;
251 case PIPE_FORMAT_R8G8B8A8_SNORM
:
252 case PIPE_FORMAT_R8G8B8A8_UNORM
:
253 case PIPE_FORMAT_R8G8B8X8_UNORM
:
254 case PIPE_FORMAT_R8G8B8A8_SINT
:
255 case PIPE_FORMAT_R8G8B8A8_UINT
:
256 return V_0280A0_SWAP_STD
;
258 case PIPE_FORMAT_A8B8G8R8_UNORM
:
259 case PIPE_FORMAT_X8B8G8R8_UNORM
:
260 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
261 return V_0280A0_SWAP_STD_REV
;
263 case PIPE_FORMAT_Z24X8_UNORM
:
264 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
265 return V_0280A0_SWAP_STD
;
267 case PIPE_FORMAT_X8Z24_UNORM
:
268 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
269 return V_0280A0_SWAP_STD
;
271 case PIPE_FORMAT_R10G10B10A2_UNORM
:
272 case PIPE_FORMAT_R10G10B10X2_SNORM
:
273 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
274 return V_0280A0_SWAP_STD
;
276 case PIPE_FORMAT_B10G10R10A2_UNORM
:
277 case PIPE_FORMAT_B10G10R10A2_UINT
:
278 return V_0280A0_SWAP_ALT
;
280 case PIPE_FORMAT_R11G11B10_FLOAT
:
281 case PIPE_FORMAT_R16G16_UNORM
:
282 case PIPE_FORMAT_R16G16_SNORM
:
283 case PIPE_FORMAT_R16G16_FLOAT
:
284 case PIPE_FORMAT_R16G16_UINT
:
285 case PIPE_FORMAT_R16G16_SINT
:
286 case PIPE_FORMAT_R32_UINT
:
287 case PIPE_FORMAT_R32_SINT
:
288 case PIPE_FORMAT_R32_FLOAT
:
289 case PIPE_FORMAT_Z32_FLOAT
:
290 return V_0280A0_SWAP_STD
;
292 /* 64-bit buffers. */
293 case PIPE_FORMAT_R32G32_FLOAT
:
294 case PIPE_FORMAT_R32G32_UINT
:
295 case PIPE_FORMAT_R32G32_SINT
:
296 case PIPE_FORMAT_R16G16B16A16_UNORM
:
297 case PIPE_FORMAT_R16G16B16A16_SNORM
:
298 case PIPE_FORMAT_R16G16B16A16_UINT
:
299 case PIPE_FORMAT_R16G16B16A16_SINT
:
300 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
301 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
303 /* 128-bit buffers. */
304 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
305 case PIPE_FORMAT_R32G32B32A32_SNORM
:
306 case PIPE_FORMAT_R32G32B32A32_UNORM
:
307 case PIPE_FORMAT_R32G32B32A32_SINT
:
308 case PIPE_FORMAT_R32G32B32A32_UINT
:
309 return V_0280A0_SWAP_STD
;
311 R600_ERR("unsupported colorswap format %d\n", format
);
317 static uint32_t r600_translate_colorformat(enum pipe_format format
)
320 case PIPE_FORMAT_L4A4_UNORM
:
321 case PIPE_FORMAT_R4A4_UNORM
:
322 case PIPE_FORMAT_A4R4_UNORM
:
323 return V_0280A0_COLOR_4_4
;
326 case PIPE_FORMAT_A8_UNORM
:
327 case PIPE_FORMAT_A8_SNORM
:
328 case PIPE_FORMAT_A8_UINT
:
329 case PIPE_FORMAT_A8_SINT
:
330 case PIPE_FORMAT_I8_UNORM
:
331 case PIPE_FORMAT_I8_SNORM
:
332 case PIPE_FORMAT_I8_UINT
:
333 case PIPE_FORMAT_I8_SINT
:
334 case PIPE_FORMAT_L8_UNORM
:
335 case PIPE_FORMAT_L8_SNORM
:
336 case PIPE_FORMAT_L8_UINT
:
337 case PIPE_FORMAT_L8_SINT
:
338 case PIPE_FORMAT_L8_SRGB
:
339 case PIPE_FORMAT_R8_UNORM
:
340 case PIPE_FORMAT_R8_SNORM
:
341 case PIPE_FORMAT_R8_UINT
:
342 case PIPE_FORMAT_R8_SINT
:
343 return V_0280A0_COLOR_8
;
345 /* 16-bit buffers. */
346 case PIPE_FORMAT_B5G6R5_UNORM
:
347 return V_0280A0_COLOR_5_6_5
;
349 case PIPE_FORMAT_B5G5R5A1_UNORM
:
350 case PIPE_FORMAT_B5G5R5X1_UNORM
:
351 return V_0280A0_COLOR_1_5_5_5
;
353 case PIPE_FORMAT_B4G4R4A4_UNORM
:
354 case PIPE_FORMAT_B4G4R4X4_UNORM
:
355 return V_0280A0_COLOR_4_4_4_4
;
357 case PIPE_FORMAT_Z16_UNORM
:
358 return V_0280A0_COLOR_16
;
360 case PIPE_FORMAT_L8A8_UNORM
:
361 case PIPE_FORMAT_L8A8_SNORM
:
362 case PIPE_FORMAT_L8A8_UINT
:
363 case PIPE_FORMAT_L8A8_SINT
:
364 case PIPE_FORMAT_L8A8_SRGB
:
365 case PIPE_FORMAT_R8G8_UNORM
:
366 case PIPE_FORMAT_R8G8_SNORM
:
367 case PIPE_FORMAT_R8G8_UINT
:
368 case PIPE_FORMAT_R8G8_SINT
:
369 return V_0280A0_COLOR_8_8
;
371 case PIPE_FORMAT_R16_UNORM
:
372 case PIPE_FORMAT_R16_SNORM
:
373 case PIPE_FORMAT_R16_UINT
:
374 case PIPE_FORMAT_R16_SINT
:
375 case PIPE_FORMAT_A16_UNORM
:
376 case PIPE_FORMAT_A16_SNORM
:
377 case PIPE_FORMAT_A16_UINT
:
378 case PIPE_FORMAT_A16_SINT
:
379 case PIPE_FORMAT_L16_UNORM
:
380 case PIPE_FORMAT_L16_SNORM
:
381 case PIPE_FORMAT_L16_UINT
:
382 case PIPE_FORMAT_L16_SINT
:
383 case PIPE_FORMAT_I16_UNORM
:
384 case PIPE_FORMAT_I16_SNORM
:
385 case PIPE_FORMAT_I16_UINT
:
386 case PIPE_FORMAT_I16_SINT
:
387 return V_0280A0_COLOR_16
;
389 case PIPE_FORMAT_R16_FLOAT
:
390 case PIPE_FORMAT_A16_FLOAT
:
391 case PIPE_FORMAT_L16_FLOAT
:
392 case PIPE_FORMAT_I16_FLOAT
:
393 return V_0280A0_COLOR_16_FLOAT
;
395 /* 32-bit buffers. */
396 case PIPE_FORMAT_A8B8G8R8_SRGB
:
397 case PIPE_FORMAT_A8B8G8R8_UNORM
:
398 case PIPE_FORMAT_A8R8G8B8_UNORM
:
399 case PIPE_FORMAT_B8G8R8A8_SRGB
:
400 case PIPE_FORMAT_B8G8R8A8_UNORM
:
401 case PIPE_FORMAT_B8G8R8X8_UNORM
:
402 case PIPE_FORMAT_R8G8B8A8_SNORM
:
403 case PIPE_FORMAT_R8G8B8A8_UNORM
:
404 case PIPE_FORMAT_R8G8B8X8_UNORM
:
405 case PIPE_FORMAT_R8SG8SB8UX8U_NORM
:
406 case PIPE_FORMAT_X8B8G8R8_UNORM
:
407 case PIPE_FORMAT_X8R8G8B8_UNORM
:
408 case PIPE_FORMAT_R8G8B8A8_SINT
:
409 case PIPE_FORMAT_R8G8B8A8_UINT
:
410 return V_0280A0_COLOR_8_8_8_8
;
412 case PIPE_FORMAT_R10G10B10A2_UNORM
:
413 case PIPE_FORMAT_R10G10B10X2_SNORM
:
414 case PIPE_FORMAT_B10G10R10A2_UNORM
:
415 case PIPE_FORMAT_B10G10R10A2_UINT
:
416 case PIPE_FORMAT_R10SG10SB10SA2U_NORM
:
417 return V_0280A0_COLOR_2_10_10_10
;
419 case PIPE_FORMAT_Z24X8_UNORM
:
420 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
421 return V_0280A0_COLOR_8_24
;
423 case PIPE_FORMAT_X8Z24_UNORM
:
424 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
425 return V_0280A0_COLOR_24_8
;
427 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
428 return V_0280A0_COLOR_X24_8_32_FLOAT
;
430 case PIPE_FORMAT_R32_UINT
:
431 case PIPE_FORMAT_R32_SINT
:
432 case PIPE_FORMAT_A32_UINT
:
433 case PIPE_FORMAT_A32_SINT
:
434 case PIPE_FORMAT_L32_UINT
:
435 case PIPE_FORMAT_L32_SINT
:
436 case PIPE_FORMAT_I32_UINT
:
437 case PIPE_FORMAT_I32_SINT
:
438 return V_0280A0_COLOR_32
;
440 case PIPE_FORMAT_R32_FLOAT
:
441 case PIPE_FORMAT_A32_FLOAT
:
442 case PIPE_FORMAT_L32_FLOAT
:
443 case PIPE_FORMAT_I32_FLOAT
:
444 case PIPE_FORMAT_Z32_FLOAT
:
445 return V_0280A0_COLOR_32_FLOAT
;
447 case PIPE_FORMAT_R16G16_FLOAT
:
448 case PIPE_FORMAT_L16A16_FLOAT
:
449 return V_0280A0_COLOR_16_16_FLOAT
;
451 case PIPE_FORMAT_R16G16_UNORM
:
452 case PIPE_FORMAT_R16G16_SNORM
:
453 case PIPE_FORMAT_R16G16_UINT
:
454 case PIPE_FORMAT_R16G16_SINT
:
455 case PIPE_FORMAT_L16A16_UNORM
:
456 case PIPE_FORMAT_L16A16_SNORM
:
457 case PIPE_FORMAT_L16A16_UINT
:
458 case PIPE_FORMAT_L16A16_SINT
:
459 return V_0280A0_COLOR_16_16
;
461 case PIPE_FORMAT_R11G11B10_FLOAT
:
462 return V_0280A0_COLOR_10_11_11_FLOAT
;
464 /* 64-bit buffers. */
465 case PIPE_FORMAT_R16G16B16A16_UINT
:
466 case PIPE_FORMAT_R16G16B16A16_SINT
:
467 case PIPE_FORMAT_R16G16B16A16_UNORM
:
468 case PIPE_FORMAT_R16G16B16A16_SNORM
:
469 return V_0280A0_COLOR_16_16_16_16
;
471 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
472 return V_0280A0_COLOR_16_16_16_16_FLOAT
;
474 case PIPE_FORMAT_R32G32_FLOAT
:
475 case PIPE_FORMAT_L32A32_FLOAT
:
476 return V_0280A0_COLOR_32_32_FLOAT
;
478 case PIPE_FORMAT_R32G32_SINT
:
479 case PIPE_FORMAT_R32G32_UINT
:
480 case PIPE_FORMAT_L32A32_UINT
:
481 case PIPE_FORMAT_L32A32_SINT
:
482 return V_0280A0_COLOR_32_32
;
484 /* 128-bit buffers. */
485 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
486 return V_0280A0_COLOR_32_32_32_32_FLOAT
;
487 case PIPE_FORMAT_R32G32B32A32_SNORM
:
488 case PIPE_FORMAT_R32G32B32A32_UNORM
:
489 case PIPE_FORMAT_R32G32B32A32_SINT
:
490 case PIPE_FORMAT_R32G32B32A32_UINT
:
491 return V_0280A0_COLOR_32_32_32_32
;
494 case PIPE_FORMAT_UYVY
:
495 case PIPE_FORMAT_YUYV
:
497 return ~0U; /* Unsupported. */
501 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat
)
503 if (R600_BIG_ENDIAN
) {
504 switch(colorformat
) {
505 case V_0280A0_COLOR_4_4
:
509 case V_0280A0_COLOR_8
:
512 /* 16-bit buffers. */
513 case V_0280A0_COLOR_5_6_5
:
514 case V_0280A0_COLOR_1_5_5_5
:
515 case V_0280A0_COLOR_4_4_4_4
:
516 case V_0280A0_COLOR_16
:
517 case V_0280A0_COLOR_8_8
:
520 /* 32-bit buffers. */
521 case V_0280A0_COLOR_8_8_8_8
:
522 case V_0280A0_COLOR_2_10_10_10
:
523 case V_0280A0_COLOR_8_24
:
524 case V_0280A0_COLOR_24_8
:
525 case V_0280A0_COLOR_32_FLOAT
:
526 case V_0280A0_COLOR_16_16_FLOAT
:
527 case V_0280A0_COLOR_16_16
:
530 /* 64-bit buffers. */
531 case V_0280A0_COLOR_16_16_16_16
:
532 case V_0280A0_COLOR_16_16_16_16_FLOAT
:
535 case V_0280A0_COLOR_32_32_FLOAT
:
536 case V_0280A0_COLOR_32_32
:
537 case V_0280A0_COLOR_X24_8_32_FLOAT
:
540 /* 128-bit buffers. */
541 case V_0280A0_COLOR_32_32_32_FLOAT
:
542 case V_0280A0_COLOR_32_32_32_32_FLOAT
:
543 case V_0280A0_COLOR_32_32_32_32
:
546 return ENDIAN_NONE
; /* Unsupported. */
553 static bool r600_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
555 return r600_translate_texformat(screen
, format
, NULL
, NULL
, NULL
) != ~0U;
558 static bool r600_is_colorbuffer_format_supported(enum pipe_format format
)
560 return r600_translate_colorformat(format
) != ~0U &&
561 r600_translate_colorswap(format
) != ~0U;
564 static bool r600_is_zs_format_supported(enum pipe_format format
)
566 return r600_translate_dbformat(format
) != ~0U;
569 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
570 enum pipe_format format
,
571 enum pipe_texture_target target
,
572 unsigned sample_count
,
575 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
578 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
579 R600_ERR("r600: unsupported texture type %d\n", target
);
583 if (!util_format_is_supported(format
, usage
))
586 if (sample_count
> 1) {
587 if (rscreen
->info
.drm_minor
< 22)
590 /* R11G11B10 is broken on R6xx. */
591 if (rscreen
->chip_class
== R600
&&
592 format
== PIPE_FORMAT_R11G11B10_FLOAT
)
595 /* MSAA integer colorbuffers hang. */
596 if (util_format_is_pure_integer(format
) &&
597 !util_format_is_depth_or_stencil(format
))
600 switch (sample_count
) {
610 if ((usage
& PIPE_BIND_SAMPLER_VIEW
) &&
611 r600_is_sampler_format_supported(screen
, format
)) {
612 retval
|= PIPE_BIND_SAMPLER_VIEW
;
615 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
616 PIPE_BIND_DISPLAY_TARGET
|
618 PIPE_BIND_SHARED
)) &&
619 r600_is_colorbuffer_format_supported(format
)) {
621 (PIPE_BIND_RENDER_TARGET
|
622 PIPE_BIND_DISPLAY_TARGET
|
627 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
628 r600_is_zs_format_supported(format
)) {
629 retval
|= PIPE_BIND_DEPTH_STENCIL
;
632 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
633 r600_is_vertex_format_supported(format
)) {
634 retval
|= PIPE_BIND_VERTEX_BUFFER
;
637 if (usage
& PIPE_BIND_TRANSFER_READ
)
638 retval
|= PIPE_BIND_TRANSFER_READ
;
639 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
640 retval
|= PIPE_BIND_TRANSFER_WRITE
;
642 return retval
== usage
;
645 static void r600_emit_polygon_offset(struct r600_context
*rctx
, struct r600_atom
*a
)
647 struct radeon_winsys_cs
*cs
= rctx
->cs
;
648 struct r600_poly_offset_state
*state
= (struct r600_poly_offset_state
*)a
;
649 float offset_units
= state
->offset_units
;
650 float offset_scale
= state
->offset_scale
;
652 switch (state
->zs_format
) {
653 case PIPE_FORMAT_Z24X8_UNORM
:
654 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
655 offset_units
*= 2.0f
;
657 case PIPE_FORMAT_Z16_UNORM
:
658 offset_units
*= 4.0f
;
663 r600_write_context_reg_seq(cs
, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE
, 4);
664 r600_write_value(cs
, fui(offset_scale
));
665 r600_write_value(cs
, fui(offset_units
));
666 r600_write_value(cs
, fui(offset_scale
));
667 r600_write_value(cs
, fui(offset_units
));
670 static uint32_t r600_get_blend_control(const struct pipe_blend_state
*state
, unsigned i
)
672 int j
= state
->independent_blend_enable
? i
: 0;
674 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
675 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
676 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
678 unsigned eqA
= state
->rt
[j
].alpha_func
;
679 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
680 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
683 if (!state
->rt
[j
].blend_enable
)
686 bc
|= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB
));
687 bc
|= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB
));
688 bc
|= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB
));
690 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
691 bc
|= S_028804_SEPARATE_ALPHA_BLEND(1);
692 bc
|= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA
));
693 bc
|= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA
));
694 bc
|= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA
));
699 static void *r600_create_blend_state_mode(struct pipe_context
*ctx
,
700 const struct pipe_blend_state
*state
,
703 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
704 uint32_t color_control
= 0, target_mask
= 0;
705 struct r600_blend_state
*blend
= CALLOC_STRUCT(r600_blend_state
);
711 r600_init_command_buffer(&blend
->buffer
, 20);
712 r600_init_command_buffer(&blend
->buffer_no_blend
, 20);
714 /* R600 does not support per-MRT blends */
715 if (rctx
->family
> CHIP_R600
)
716 color_control
|= S_028808_PER_MRT_BLEND(1);
718 if (state
->logicop_enable
) {
719 color_control
|= (state
->logicop_func
<< 16) | (state
->logicop_func
<< 20);
721 color_control
|= (0xcc << 16);
723 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
724 if (state
->independent_blend_enable
) {
725 for (int i
= 0; i
< 8; i
++) {
726 if (state
->rt
[i
].blend_enable
) {
727 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
729 target_mask
|= (state
->rt
[i
].colormask
<< (4 * i
));
732 for (int i
= 0; i
< 8; i
++) {
733 if (state
->rt
[0].blend_enable
) {
734 color_control
|= S_028808_TARGET_BLEND_ENABLE(1 << i
);
736 target_mask
|= (state
->rt
[0].colormask
<< (4 * i
));
741 color_control
|= S_028808_SPECIAL_OP(mode
);
743 color_control
|= S_028808_SPECIAL_OP(V_028808_DISABLE
);
745 /* only MRT0 has dual src blend */
746 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
747 blend
->cb_target_mask
= target_mask
;
748 blend
->cb_color_control
= color_control
;
749 blend
->cb_color_control_no_blend
= color_control
& C_028808_TARGET_BLEND_ENABLE
;
750 blend
->alpha_to_one
= state
->alpha_to_one
;
752 r600_store_context_reg(&blend
->buffer
, R_028D44_DB_ALPHA_TO_MASK
,
753 S_028D44_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
754 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
755 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
756 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
757 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
759 /* Copy over the registers set so far into buffer_no_blend. */
760 memcpy(blend
->buffer_no_blend
.buf
, blend
->buffer
.buf
, blend
->buffer
.num_dw
* 4);
761 blend
->buffer_no_blend
.num_dw
= blend
->buffer
.num_dw
;
763 /* Only add blend registers if blending is enabled. */
764 if (!G_028808_TARGET_BLEND_ENABLE(color_control
)) {
768 /* The first R600 does not support per-MRT blends */
769 r600_store_context_reg(&blend
->buffer
, R_028804_CB_BLEND_CONTROL
,
770 r600_get_blend_control(state
, 0));
772 if (rctx
->family
> CHIP_R600
) {
773 r600_store_context_reg_seq(&blend
->buffer
, R_028780_CB_BLEND0_CONTROL
, 8);
774 for (int i
= 0; i
< 8; i
++) {
775 r600_store_value(&blend
->buffer
, r600_get_blend_control(state
, i
));
781 static void *r600_create_blend_state(struct pipe_context
*ctx
,
782 const struct pipe_blend_state
*state
)
784 return r600_create_blend_state_mode(ctx
, state
, V_028808_SPECIAL_NORMAL
);
787 static void *r600_create_dsa_state(struct pipe_context
*ctx
,
788 const struct pipe_depth_stencil_alpha_state
*state
)
790 unsigned db_depth_control
, alpha_test_control
, alpha_ref
;
791 struct r600_dsa_state
*dsa
= CALLOC_STRUCT(r600_dsa_state
);
797 r600_init_command_buffer(&dsa
->buffer
, 3);
799 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
800 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
801 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
802 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
804 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
805 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
806 S_028800_ZFUNC(state
->depth
.func
);
809 if (state
->stencil
[0].enabled
) {
810 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
811 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
); /* translates straight */
812 db_depth_control
|= S_028800_STENCILFAIL(r600_translate_stencil_op(state
->stencil
[0].fail_op
));
813 db_depth_control
|= S_028800_STENCILZPASS(r600_translate_stencil_op(state
->stencil
[0].zpass_op
));
814 db_depth_control
|= S_028800_STENCILZFAIL(r600_translate_stencil_op(state
->stencil
[0].zfail_op
));
816 if (state
->stencil
[1].enabled
) {
817 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
818 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
); /* translates straight */
819 db_depth_control
|= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].fail_op
));
820 db_depth_control
|= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state
->stencil
[1].zpass_op
));
821 db_depth_control
|= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state
->stencil
[1].zfail_op
));
826 alpha_test_control
= 0;
828 if (state
->alpha
.enabled
) {
829 alpha_test_control
= S_028410_ALPHA_FUNC(state
->alpha
.func
);
830 alpha_test_control
|= S_028410_ALPHA_TEST_ENABLE(1);
831 alpha_ref
= fui(state
->alpha
.ref_value
);
833 dsa
->sx_alpha_test_control
= alpha_test_control
& 0xff;
834 dsa
->alpha_ref
= alpha_ref
;
836 r600_store_context_reg(&dsa
->buffer
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
840 static void *r600_create_rs_state(struct pipe_context
*ctx
,
841 const struct pipe_rasterizer_state
*state
)
843 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
844 unsigned tmp
, sc_mode_cntl
, spi_interp
;
845 float psize_min
, psize_max
;
846 struct r600_rasterizer_state
*rs
= CALLOC_STRUCT(r600_rasterizer_state
);
852 r600_init_command_buffer(&rs
->buffer
, 30);
854 rs
->flatshade
= state
->flatshade
;
855 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
856 rs
->two_side
= state
->light_twoside
;
857 rs
->clip_plane_enable
= state
->clip_plane_enable
;
858 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
859 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
860 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
861 rs
->pa_cl_clip_cntl
=
862 S_028810_PS_UCP_MODE(3) |
863 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
864 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
865 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
866 rs
->multisample_enable
= state
->multisample
;
869 rs
->offset_units
= state
->offset_units
;
870 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
871 rs
->offset_enable
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
873 if (state
->point_size_per_vertex
) {
874 psize_min
= util_get_min_point_size(state
);
877 /* Force the point size to be as if the vertex output was disabled. */
878 psize_min
= state
->point_size
;
879 psize_max
= state
->point_size
;
882 sc_mode_cntl
= S_028A4C_MSAA_ENABLE(state
->multisample
) |
883 S_028A4C_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
884 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
885 if (rctx
->chip_class
>= R700
) {
886 sc_mode_cntl
|= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
887 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
888 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state
->scissor
);
890 sc_mode_cntl
|= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
891 rs
->scissor_enable
= state
->scissor
;
894 spi_interp
= S_0286D4_FLAT_SHADE_ENA(1);
895 if (state
->sprite_coord_enable
) {
896 spi_interp
|= S_0286D4_PNT_SPRITE_ENA(1) |
897 S_0286D4_PNT_SPRITE_OVRD_X(2) |
898 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
899 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
900 S_0286D4_PNT_SPRITE_OVRD_W(1);
901 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
902 spi_interp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
906 r600_store_context_reg_seq(&rs
->buffer
, R_028A00_PA_SU_POINT_SIZE
, 3);
907 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
908 tmp
= r600_pack_float_12p4(state
->point_size
/2);
909 r600_store_value(&rs
->buffer
, /* R_028A00_PA_SU_POINT_SIZE */
910 S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
911 r600_store_value(&rs
->buffer
, /* R_028A04_PA_SU_POINT_MINMAX */
912 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
913 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
914 r600_store_value(&rs
->buffer
, /* R_028A08_PA_SU_LINE_CNTL */
915 S_028A08_WIDTH(r600_pack_float_12p4(state
->line_width
/2)));
917 r600_store_context_reg(&rs
->buffer
, R_0286D4_SPI_INTERP_CONTROL_0
, spi_interp
);
918 r600_store_context_reg(&rs
->buffer
, R_028A4C_PA_SC_MODE_CNTL
, sc_mode_cntl
);
919 r600_store_context_reg(&rs
->buffer
, R_028C08_PA_SU_VTX_CNTL
,
920 S_028C08_PIX_CENTER_HALF(state
->gl_rasterization_rules
) |
921 S_028C08_QUANT_MODE(V_028C08_X_1_256TH
));
922 r600_store_context_reg(&rs
->buffer
, R_028DFC_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
923 r600_store_context_reg(&rs
->buffer
, R_028814_PA_SU_SC_MODE_CNTL
,
924 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
925 S_028814_CULL_FRONT(state
->cull_face
& PIPE_FACE_FRONT
? 1 : 0) |
926 S_028814_CULL_BACK(state
->cull_face
& PIPE_FACE_BACK
? 1 : 0) |
927 S_028814_FACE(!state
->front_ccw
) |
928 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
929 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
930 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
931 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
932 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
933 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state
->fill_front
)) |
934 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state
->fill_back
)));
935 r600_store_context_reg(&rs
->buffer
, R_028350_SX_MISC
, S_028350_MULTIPASS(state
->rasterizer_discard
));
939 static void *r600_create_sampler_state(struct pipe_context
*ctx
,
940 const struct pipe_sampler_state
*state
)
942 struct r600_pipe_sampler_state
*ss
= CALLOC_STRUCT(r600_pipe_sampler_state
);
944 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 4 : 0;
950 ss
->seamless_cube_map
= state
->seamless_cube_map
;
951 ss
->border_color_use
= false;
952 util_pack_color(state
->border_color
.f
, PIPE_FORMAT_B8G8R8A8_UNORM
, &uc
);
953 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
954 ss
->tex_sampler_words
[0] = S_03C000_CLAMP_X(r600_tex_wrap(state
->wrap_s
)) |
955 S_03C000_CLAMP_Y(r600_tex_wrap(state
->wrap_t
)) |
956 S_03C000_CLAMP_Z(r600_tex_wrap(state
->wrap_r
)) |
957 S_03C000_XY_MAG_FILTER(r600_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
958 S_03C000_XY_MIN_FILTER(r600_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
959 S_03C000_MIP_FILTER(r600_tex_mipfilter(state
->min_mip_filter
)) |
960 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
961 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state
->compare_func
)) |
962 S_03C000_BORDER_COLOR_TYPE(uc
.ui
? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER
: 0);
963 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
964 ss
->tex_sampler_words
[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 6)) |
965 S_03C004_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 6)) |
966 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 6));
967 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
968 ss
->tex_sampler_words
[2] = S_03C008_TYPE(1);
970 ss
->border_color_use
= true;
971 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
972 ss
->border_color
[0] = fui(state
->border_color
.f
[0]);
973 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
974 ss
->border_color
[1] = fui(state
->border_color
.f
[1]);
975 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
976 ss
->border_color
[2] = fui(state
->border_color
.f
[2]);
977 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
978 ss
->border_color
[3] = fui(state
->border_color
.f
[3]);
983 struct pipe_sampler_view
*
984 r600_create_sampler_view_custom(struct pipe_context
*ctx
,
985 struct pipe_resource
*texture
,
986 const struct pipe_sampler_view
*state
,
987 unsigned width_first_level
, unsigned height_first_level
)
989 struct r600_pipe_sampler_view
*view
= CALLOC_STRUCT(r600_pipe_sampler_view
);
990 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
991 unsigned format
, endian
;
992 uint32_t word4
= 0, yuv_format
= 0, pitch
= 0;
993 unsigned char swizzle
[4], array_mode
= 0, tile_type
= 0;
994 unsigned width
, height
, depth
, offset_level
, last_level
;
999 /* initialize base object */
1000 view
->base
= *state
;
1001 view
->base
.texture
= NULL
;
1002 pipe_reference(NULL
, &texture
->reference
);
1003 view
->base
.texture
= texture
;
1004 view
->base
.reference
.count
= 1;
1005 view
->base
.context
= ctx
;
1007 swizzle
[0] = state
->swizzle_r
;
1008 swizzle
[1] = state
->swizzle_g
;
1009 swizzle
[2] = state
->swizzle_b
;
1010 swizzle
[3] = state
->swizzle_a
;
1012 format
= r600_translate_texformat(ctx
->screen
, state
->format
,
1014 &word4
, &yuv_format
);
1015 assert(format
!= ~0);
1021 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
) {
1022 if (!r600_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
1026 tmp
= tmp
->flushed_depth_texture
;
1029 endian
= r600_colorformat_endian_swap(format
);
1031 offset_level
= state
->u
.tex
.first_level
;
1032 last_level
= state
->u
.tex
.last_level
- offset_level
;
1033 width
= width_first_level
;
1034 height
= height_first_level
;
1035 depth
= tmp
->surface
.level
[offset_level
].npix_z
;
1036 pitch
= tmp
->surface
.level
[offset_level
].nblk_x
* util_format_get_blockwidth(state
->format
);
1037 tile_type
= tmp
->tile_type
;
1039 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
1041 depth
= texture
->array_size
;
1042 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
1043 depth
= texture
->array_size
;
1045 switch (tmp
->surface
.level
[offset_level
].mode
) {
1046 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1047 array_mode
= V_038000_ARRAY_LINEAR_ALIGNED
;
1049 case RADEON_SURF_MODE_1D
:
1050 array_mode
= V_038000_ARRAY_1D_TILED_THIN1
;
1052 case RADEON_SURF_MODE_2D
:
1053 array_mode
= V_038000_ARRAY_2D_TILED_THIN1
;
1055 case RADEON_SURF_MODE_LINEAR
:
1057 array_mode
= V_038000_ARRAY_LINEAR_GENERAL
;
1061 view
->tex_resource
= &tmp
->resource
;
1062 view
->tex_resource_words
[0] = (S_038000_DIM(r600_tex_dim(texture
->target
, texture
->nr_samples
)) |
1063 S_038000_TILE_MODE(array_mode
) |
1064 S_038000_TILE_TYPE(tile_type
) |
1065 S_038000_PITCH((pitch
/ 8) - 1) |
1066 S_038000_TEX_WIDTH(width
- 1));
1067 view
->tex_resource_words
[1] = (S_038004_TEX_HEIGHT(height
- 1) |
1068 S_038004_TEX_DEPTH(depth
- 1) |
1069 S_038004_DATA_FORMAT(format
));
1070 view
->tex_resource_words
[2] = tmp
->surface
.level
[offset_level
].offset
>> 8;
1071 if (offset_level
>= tmp
->surface
.last_level
) {
1072 view
->tex_resource_words
[3] = tmp
->surface
.level
[offset_level
].offset
>> 8;
1074 view
->tex_resource_words
[3] = tmp
->surface
.level
[offset_level
+ 1].offset
>> 8;
1076 view
->tex_resource_words
[4] = (word4
|
1077 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE
) |
1078 S_038010_REQUEST_SIZE(1) |
1079 S_038010_ENDIAN_SWAP(endian
) |
1080 S_038010_BASE_LEVEL(0));
1081 view
->tex_resource_words
[5] = (S_038014_BASE_ARRAY(state
->u
.tex
.first_layer
) |
1082 S_038014_LAST_ARRAY(state
->u
.tex
.last_layer
));
1083 if (texture
->nr_samples
> 1) {
1084 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1085 view
->tex_resource_words
[5] |= S_038014_LAST_LEVEL(util_logbase2(texture
->nr_samples
));
1087 view
->tex_resource_words
[5] |= S_038014_LAST_LEVEL(last_level
);
1089 view
->tex_resource_words
[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE
) |
1090 S_038018_MAX_ANISO(4 /* max 16 samples */));
1094 static struct pipe_sampler_view
*
1095 r600_create_sampler_view(struct pipe_context
*ctx
,
1096 struct pipe_resource
*tex
,
1097 const struct pipe_sampler_view
*state
)
1099 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1101 return r600_create_sampler_view_custom(ctx
, tex
, state
,
1102 rtex
->surface
.level
[state
->u
.tex
.first_level
].npix_x
,
1103 rtex
->surface
.level
[state
->u
.tex
.first_level
].npix_y
);
1106 static void r600_emit_clip_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1108 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1109 struct pipe_clip_state
*state
= &rctx
->clip_state
.state
;
1111 r600_write_context_reg_seq(cs
, R_028E20_PA_CL_UCP0_X
, 6*4);
1112 r600_write_array(cs
, 6*4, (unsigned*)state
);
1115 static void r600_set_polygon_stipple(struct pipe_context
*ctx
,
1116 const struct pipe_poly_stipple
*state
)
1120 static void r600_emit_scissor_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1122 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1123 struct pipe_scissor_state
*state
= &rctx
->scissor
.scissor
;
1125 if (rctx
->chip_class
!= R600
|| rctx
->scissor
.enable
) {
1126 r600_write_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 2);
1127 r600_write_value(cs
, S_028240_TL_X(state
->minx
) | S_028240_TL_Y(state
->miny
) |
1128 S_028240_WINDOW_OFFSET_DISABLE(1));
1129 r600_write_value(cs
, S_028244_BR_X(state
->maxx
) | S_028244_BR_Y(state
->maxy
));
1131 r600_write_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 2);
1132 r600_write_value(cs
, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1133 S_028240_WINDOW_OFFSET_DISABLE(1));
1134 r600_write_value(cs
, S_028244_BR_X(8192) | S_028244_BR_Y(8192));
1138 static void r600_set_scissor_state(struct pipe_context
*ctx
,
1139 const struct pipe_scissor_state
*state
)
1141 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1143 rctx
->scissor
.scissor
= *state
;
1145 if (rctx
->chip_class
== R600
&& !rctx
->scissor
.enable
)
1148 rctx
->scissor
.atom
.dirty
= true;
1151 static struct r600_resource
*r600_buffer_create_helper(struct r600_screen
*rscreen
,
1152 unsigned size
, unsigned alignment
)
1154 struct pipe_resource buffer
;
1156 memset(&buffer
, 0, sizeof buffer
);
1157 buffer
.target
= PIPE_BUFFER
;
1158 buffer
.format
= PIPE_FORMAT_R8_UNORM
;
1159 buffer
.bind
= PIPE_BIND_CUSTOM
;
1160 buffer
.usage
= PIPE_USAGE_STATIC
;
1162 buffer
.width0
= size
;
1165 buffer
.array_size
= 1;
1167 return (struct r600_resource
*)
1168 r600_buffer_create(&rscreen
->screen
, &buffer
, alignment
);
1171 static void r600_init_color_surface(struct r600_context
*rctx
,
1172 struct r600_surface
*surf
,
1173 bool force_cmask_fmask
)
1175 struct r600_screen
*rscreen
= rctx
->screen
;
1176 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1177 unsigned level
= surf
->base
.u
.tex
.level
;
1178 unsigned pitch
, slice
;
1179 unsigned color_info
;
1180 unsigned format
, swap
, ntype
, endian
;
1182 const struct util_format_description
*desc
;
1184 bool blend_bypass
= 0, blend_clamp
= 1;
1186 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
1187 r600_init_flushed_depth_texture(&rctx
->context
, surf
->base
.texture
, NULL
);
1188 rtex
= rtex
->flushed_depth_texture
;
1192 offset
= rtex
->surface
.level
[level
].offset
;
1193 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1194 offset
+= rtex
->surface
.level
[level
].slice_size
*
1195 surf
->base
.u
.tex
.first_layer
;
1197 pitch
= rtex
->surface
.level
[level
].nblk_x
/ 8 - 1;
1198 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1203 switch (rtex
->surface
.level
[level
].mode
) {
1204 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1205 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED
);
1207 case RADEON_SURF_MODE_1D
:
1208 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1
);
1210 case RADEON_SURF_MODE_2D
:
1211 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1
);
1213 case RADEON_SURF_MODE_LINEAR
:
1215 color_info
= S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL
);
1219 desc
= util_format_description(surf
->base
.format
);
1221 for (i
= 0; i
< 4; i
++) {
1222 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1227 ntype
= V_0280A0_NUMBER_UNORM
;
1228 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1229 ntype
= V_0280A0_NUMBER_SRGB
;
1230 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1231 if (desc
->channel
[i
].normalized
)
1232 ntype
= V_0280A0_NUMBER_SNORM
;
1233 else if (desc
->channel
[i
].pure_integer
)
1234 ntype
= V_0280A0_NUMBER_SINT
;
1235 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1236 if (desc
->channel
[i
].normalized
)
1237 ntype
= V_0280A0_NUMBER_UNORM
;
1238 else if (desc
->channel
[i
].pure_integer
)
1239 ntype
= V_0280A0_NUMBER_UINT
;
1242 format
= r600_translate_colorformat(surf
->base
.format
);
1243 assert(format
!= ~0);
1245 swap
= r600_translate_colorswap(surf
->base
.format
);
1248 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1249 endian
= ENDIAN_NONE
;
1251 endian
= r600_colorformat_endian_swap(format
);
1254 /* set blend bypass according to docs if SINT/UINT or
1255 8/24 COLOR variants */
1256 if (ntype
== V_0280A0_NUMBER_UINT
|| ntype
== V_0280A0_NUMBER_SINT
||
1257 format
== V_0280A0_COLOR_8_24
|| format
== V_0280A0_COLOR_24_8
||
1258 format
== V_0280A0_COLOR_X24_8_32_FLOAT
) {
1263 surf
->alphatest_bypass
= ntype
== V_0280A0_NUMBER_UINT
|| ntype
== V_0280A0_NUMBER_SINT
;
1265 color_info
|= S_0280A0_FORMAT(format
) |
1266 S_0280A0_COMP_SWAP(swap
) |
1267 S_0280A0_BLEND_BYPASS(blend_bypass
) |
1268 S_0280A0_BLEND_CLAMP(blend_clamp
) |
1269 S_0280A0_NUMBER_TYPE(ntype
) |
1270 S_0280A0_ENDIAN(endian
);
1272 /* EXPORT_NORM is an optimzation that can be enabled for better
1273 * performance in certain cases
1275 if (rctx
->chip_class
== R600
) {
1276 /* EXPORT_NORM can be enabled if:
1277 * - 11-bit or smaller UNORM/SNORM/SRGB
1278 * - BLEND_CLAMP is enabled
1279 * - BLEND_FLOAT32 is disabled
1281 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1282 (desc
->channel
[i
].size
< 12 &&
1283 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1284 ntype
!= V_0280A0_NUMBER_UINT
&&
1285 ntype
!= V_0280A0_NUMBER_SINT
) &&
1286 G_0280A0_BLEND_CLAMP(color_info
) &&
1287 !G_0280A0_BLEND_FLOAT32(color_info
)) {
1288 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
1289 surf
->export_16bpc
= true;
1292 /* EXPORT_NORM can be enabled if:
1293 * - 11-bit or smaller UNORM/SNORM/SRGB
1294 * - 16-bit or smaller FLOAT
1296 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
&&
1297 ((desc
->channel
[i
].size
< 12 &&
1298 desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1299 ntype
!= V_0280A0_NUMBER_UINT
&& ntype
!= V_0280A0_NUMBER_SINT
) ||
1300 (desc
->channel
[i
].size
< 17 &&
1301 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
))) {
1302 color_info
|= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM
);
1303 surf
->export_16bpc
= true;
1307 /* These might not always be initialized to zero. */
1308 surf
->cb_color_base
= offset
>> 8;
1309 surf
->cb_color_size
= S_028060_PITCH_TILE_MAX(pitch
) |
1310 S_028060_SLICE_TILE_MAX(slice
);
1311 surf
->cb_color_fmask
= surf
->cb_color_base
;
1312 surf
->cb_color_cmask
= surf
->cb_color_base
;
1313 surf
->cb_color_mask
= 0;
1315 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
,
1316 &rtex
->resource
.b
.b
);
1317 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
,
1318 &rtex
->resource
.b
.b
);
1320 if (rtex
->cmask_size
) {
1321 surf
->cb_color_cmask
= rtex
->cmask_offset
>> 8;
1322 surf
->cb_color_mask
|= S_028100_CMASK_BLOCK_MAX(rtex
->cmask_slice_tile_max
);
1324 if (rtex
->fmask_size
) {
1325 color_info
|= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE
);
1326 surf
->cb_color_fmask
= rtex
->fmask_offset
>> 8;
1327 surf
->cb_color_mask
|= S_028100_FMASK_TILE_MAX(slice
);
1328 } else { /* cmask only */
1329 color_info
|= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE
);
1331 } else if (force_cmask_fmask
) {
1332 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1334 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1335 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1336 * because it's not an MSAA buffer.
1338 struct r600_cmask_info cmask
;
1339 struct r600_fmask_info fmask
;
1341 r600_texture_get_cmask_info(rscreen
, rtex
, &cmask
);
1342 r600_texture_get_fmask_info(rscreen
, rtex
, 8, &fmask
);
1345 if (!rctx
->dummy_cmask
||
1346 rctx
->dummy_cmask
->buf
->size
< cmask
.size
||
1347 rctx
->dummy_cmask
->buf
->alignment
% cmask
.alignment
!= 0) {
1348 struct pipe_transfer
*transfer
;
1351 pipe_resource_reference((struct pipe_resource
**)&rctx
->dummy_cmask
, NULL
);
1352 rctx
->dummy_cmask
= r600_buffer_create_helper(rscreen
, cmask
.size
, cmask
.alignment
);
1354 /* Set the contents to 0xCC. */
1355 ptr
= pipe_buffer_map(&rctx
->context
, &rctx
->dummy_cmask
->b
.b
, PIPE_TRANSFER_WRITE
, &transfer
);
1356 memset(ptr
, 0xCC, cmask
.size
);
1357 pipe_buffer_unmap(&rctx
->context
, transfer
);
1359 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
,
1360 &rctx
->dummy_cmask
->b
.b
);
1363 if (!rctx
->dummy_fmask
||
1364 rctx
->dummy_fmask
->buf
->size
< fmask
.size
||
1365 rctx
->dummy_fmask
->buf
->alignment
% fmask
.alignment
!= 0) {
1366 pipe_resource_reference((struct pipe_resource
**)&rctx
->dummy_fmask
, NULL
);
1367 rctx
->dummy_fmask
= r600_buffer_create_helper(rscreen
, fmask
.size
, fmask
.alignment
);
1370 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
,
1371 &rctx
->dummy_fmask
->b
.b
);
1373 /* Init the registers. */
1374 color_info
|= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE
);
1375 surf
->cb_color_cmask
= 0;
1376 surf
->cb_color_fmask
= 0;
1377 surf
->cb_color_mask
= S_028100_CMASK_BLOCK_MAX(cmask
.slice_tile_max
) |
1378 S_028100_FMASK_TILE_MAX(slice
);
1381 surf
->cb_color_info
= color_info
;
1383 if (rtex
->surface
.level
[level
].mode
< RADEON_SURF_MODE_1D
) {
1384 surf
->cb_color_view
= 0;
1386 surf
->cb_color_view
= S_028080_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1387 S_028080_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1390 surf
->color_initialized
= true;
1393 static void r600_init_depth_surface(struct r600_context
*rctx
,
1394 struct r600_surface
*surf
)
1396 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1397 unsigned level
, pitch
, slice
, format
, offset
, array_mode
;
1399 level
= surf
->base
.u
.tex
.level
;
1400 offset
= rtex
->surface
.level
[level
].offset
;
1401 pitch
= rtex
->surface
.level
[level
].nblk_x
/ 8 - 1;
1402 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1406 switch (rtex
->surface
.level
[level
].mode
) {
1407 case RADEON_SURF_MODE_2D
:
1408 array_mode
= V_0280A0_ARRAY_2D_TILED_THIN1
;
1410 case RADEON_SURF_MODE_1D
:
1411 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1412 case RADEON_SURF_MODE_LINEAR
:
1414 array_mode
= V_0280A0_ARRAY_1D_TILED_THIN1
;
1418 format
= r600_translate_dbformat(surf
->base
.format
);
1419 assert(format
!= ~0);
1421 surf
->db_depth_info
= S_028010_ARRAY_MODE(array_mode
) | S_028010_FORMAT(format
);
1422 surf
->db_depth_base
= offset
>> 8;
1423 surf
->db_depth_view
= S_028004_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1424 S_028004_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1425 surf
->db_depth_size
= S_028000_PITCH_TILE_MAX(pitch
) | S_028000_SLICE_TILE_MAX(slice
);
1426 surf
->db_prefetch_limit
= (rtex
->surface
.level
[level
].nblk_y
/ 8) - 1;
1428 switch (surf
->base
.format
) {
1429 case PIPE_FORMAT_Z24X8_UNORM
:
1430 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1431 surf
->pa_su_poly_offset_db_fmt_cntl
=
1432 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1434 case PIPE_FORMAT_Z32_FLOAT
:
1435 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1436 surf
->pa_su_poly_offset_db_fmt_cntl
=
1437 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1438 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1440 case PIPE_FORMAT_Z16_UNORM
:
1441 surf
->pa_su_poly_offset_db_fmt_cntl
=
1442 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1447 surf
->depth_initialized
= true;
1450 static void r600_set_framebuffer_state(struct pipe_context
*ctx
,
1451 const struct pipe_framebuffer_state
*state
)
1453 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1454 struct r600_surface
*surf
;
1455 struct r600_texture
*rtex
;
1458 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1459 rctx
->flags
|= R600_CONTEXT_CB_FLUSH
;
1461 if (rctx
->chip_class
>= R700
&&
1462 rctx
->framebuffer
.state
.cbufs
[0]->texture
->nr_samples
> 1) {
1463 rctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV_CB_META
;
1466 if (rctx
->framebuffer
.state
.zsbuf
) {
1467 rctx
->flags
|= R600_CONTEXT_DB_FLUSH
;
1470 if (rctx
->chip_class
== R600
) {
1471 rctx
->flags
|= R600_CONTEXT_FLUSH_AND_INV
;
1474 /* Set the new state. */
1475 util_copy_framebuffer_state(&rctx
->framebuffer
.state
, state
);
1477 rctx
->framebuffer
.export_16bpc
= state
->nr_cbufs
!= 0;
1478 rctx
->framebuffer
.cb0_is_integer
= state
->nr_cbufs
&&
1479 util_format_is_pure_integer(state
->cbufs
[0]->format
);
1480 rctx
->framebuffer
.compressed_cb_mask
= 0;
1481 rctx
->framebuffer
.is_msaa_resolve
= state
->nr_cbufs
== 2 &&
1482 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
1483 state
->cbufs
[1]->texture
->nr_samples
<= 1;
1485 if (state
->nr_cbufs
)
1486 rctx
->framebuffer
.nr_samples
= state
->cbufs
[0]->texture
->nr_samples
;
1487 else if (state
->zsbuf
)
1488 rctx
->framebuffer
.nr_samples
= state
->zsbuf
->texture
->nr_samples
;
1490 rctx
->framebuffer
.nr_samples
= 0;
1493 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
1494 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1495 bool force_cmask_fmask
= rctx
->chip_class
== R600
&&
1496 rctx
->framebuffer
.is_msaa_resolve
&&
1499 surf
= (struct r600_surface
*)state
->cbufs
[i
];
1500 rtex
= (struct r600_texture
*)surf
->base
.texture
;
1502 if (!surf
->color_initialized
|| force_cmask_fmask
) {
1503 r600_init_color_surface(rctx
, surf
, force_cmask_fmask
);
1504 if (force_cmask_fmask
) {
1505 /* re-initialize later without compression */
1506 surf
->color_initialized
= false;
1510 if (!surf
->export_16bpc
) {
1511 rctx
->framebuffer
.export_16bpc
= false;
1514 if (rtex
->fmask_size
&& rtex
->cmask_size
) {
1515 rctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
1519 /* Update alpha-test state dependencies.
1520 * Alpha-test is done on the first colorbuffer only. */
1521 if (state
->nr_cbufs
) {
1522 surf
= (struct r600_surface
*)state
->cbufs
[0];
1523 if (rctx
->alphatest_state
.bypass
!= surf
->alphatest_bypass
) {
1524 rctx
->alphatest_state
.bypass
= surf
->alphatest_bypass
;
1525 rctx
->alphatest_state
.atom
.dirty
= true;
1531 surf
= (struct r600_surface
*)state
->zsbuf
;
1533 if (!surf
->depth_initialized
) {
1534 r600_init_depth_surface(rctx
, surf
);
1537 if (state
->zsbuf
->format
!= rctx
->poly_offset_state
.zs_format
) {
1538 rctx
->poly_offset_state
.zs_format
= state
->zsbuf
->format
;
1539 rctx
->poly_offset_state
.atom
.dirty
= true;
1543 if (rctx
->cb_misc_state
.nr_cbufs
!= state
->nr_cbufs
) {
1544 rctx
->cb_misc_state
.nr_cbufs
= state
->nr_cbufs
;
1545 rctx
->cb_misc_state
.atom
.dirty
= true;
1548 if (state
->nr_cbufs
== 0 && rctx
->alphatest_state
.bypass
) {
1549 rctx
->alphatest_state
.bypass
= false;
1550 rctx
->alphatest_state
.atom
.dirty
= true;
1553 /* Calculate the CS size. */
1554 rctx
->framebuffer
.atom
.num_dw
=
1555 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1557 if (rctx
->framebuffer
.state
.nr_cbufs
) {
1558 rctx
->framebuffer
.atom
.num_dw
+= 6 * (2 + rctx
->framebuffer
.state
.nr_cbufs
);
1559 rctx
->framebuffer
.atom
.num_dw
+= 6 * rctx
->framebuffer
.state
.nr_cbufs
; /* relocs */
1562 if (rctx
->framebuffer
.state
.zsbuf
) {
1563 rctx
->framebuffer
.atom
.num_dw
+= 16;
1564 } else if (rctx
->screen
->info
.drm_minor
>= 18) {
1565 rctx
->framebuffer
.atom
.num_dw
+= 3;
1567 if (rctx
->family
> CHIP_R600
&& rctx
->family
< CHIP_RV770
) {
1568 rctx
->framebuffer
.atom
.num_dw
+= 2;
1571 rctx
->framebuffer
.atom
.dirty
= true;
1574 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1575 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1576 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1577 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1578 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1580 static void r600_emit_msaa_state(struct r600_context
*rctx
, int nr_samples
)
1582 static uint32_t sample_locs_2x
[] = {
1583 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1584 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1586 static unsigned max_dist_2x
= 4;
1587 static uint32_t sample_locs_4x
[] = {
1588 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1589 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1591 static unsigned max_dist_4x
= 6;
1592 static uint32_t sample_locs_8x
[] = {
1593 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1594 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1596 static unsigned max_dist_8x
= 8;
1598 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1599 unsigned max_dist
= 0;
1601 if (rctx
->family
== CHIP_R600
) {
1602 switch (nr_samples
) {
1607 r600_write_config_reg(cs
, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S
, sample_locs_2x
[0]);
1608 max_dist
= max_dist_2x
;
1611 r600_write_config_reg(cs
, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S
, sample_locs_4x
[0]);
1612 max_dist
= max_dist_4x
;
1615 r600_write_config_reg_seq(cs
, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0
, 2);
1616 r600_write_value(cs
, sample_locs_8x
[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1617 r600_write_value(cs
, sample_locs_8x
[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1618 max_dist
= max_dist_8x
;
1622 switch (nr_samples
) {
1624 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1625 r600_write_value(cs
, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1626 r600_write_value(cs
, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1630 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1631 r600_write_value(cs
, sample_locs_2x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1632 r600_write_value(cs
, sample_locs_2x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1633 max_dist
= max_dist_2x
;
1636 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1637 r600_write_value(cs
, sample_locs_4x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1638 r600_write_value(cs
, sample_locs_4x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1639 max_dist
= max_dist_4x
;
1642 r600_write_context_reg_seq(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX
, 2);
1643 r600_write_value(cs
, sample_locs_8x
[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1644 r600_write_value(cs
, sample_locs_8x
[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1645 max_dist
= max_dist_8x
;
1650 if (nr_samples
> 1) {
1651 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1652 r600_write_value(cs
, S_028C00_LAST_PIXEL(1) |
1653 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1654 r600_write_value(cs
, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples
)) |
1655 S_028C04_MAX_SAMPLE_DIST(max_dist
)); /* R_028C04_PA_SC_AA_CONFIG */
1657 r600_write_context_reg_seq(cs
, R_028C00_PA_SC_LINE_CNTL
, 2);
1658 r600_write_value(cs
, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1659 r600_write_value(cs
, 0); /* R_028C04_PA_SC_AA_CONFIG */
1663 static void r600_emit_framebuffer_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1665 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1666 struct pipe_framebuffer_state
*state
= &rctx
->framebuffer
.state
;
1667 unsigned nr_cbufs
= state
->nr_cbufs
;
1668 struct r600_surface
**cb
= (struct r600_surface
**)&state
->cbufs
[0];
1669 unsigned i
, sbu
= 0;
1672 r600_write_context_reg_seq(cs
, R_0280A0_CB_COLOR0_INFO
, 8);
1673 for (i
= 0; i
< nr_cbufs
; i
++) {
1674 r600_write_value(cs
, cb
[i
]->cb_color_info
);
1676 /* set CB_COLOR1_INFO for possible dual-src blending */
1678 r600_write_value(cs
, cb
[0]->cb_color_info
);
1681 for (; i
< 8; i
++) {
1682 r600_write_value(cs
, 0);
1687 r600_write_context_reg_seq(cs
, R_028040_CB_COLOR0_BASE
, nr_cbufs
);
1688 for (i
= 0; i
< nr_cbufs
; i
++) {
1689 r600_write_value(cs
, cb
[i
]->cb_color_base
);
1693 for (i
= 0; i
< nr_cbufs
; i
++) {
1694 unsigned reloc
= r600_context_bo_reloc(rctx
,
1695 (struct r600_resource
*)cb
[i
]->base
.texture
,
1696 RADEON_USAGE_READWRITE
);
1697 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1698 r600_write_value(cs
, reloc
);
1701 r600_write_context_reg_seq(cs
, R_028060_CB_COLOR0_SIZE
, nr_cbufs
);
1702 for (i
= 0; i
< nr_cbufs
; i
++) {
1703 r600_write_value(cs
, cb
[i
]->cb_color_size
);
1706 r600_write_context_reg_seq(cs
, R_028080_CB_COLOR0_VIEW
, nr_cbufs
);
1707 for (i
= 0; i
< nr_cbufs
; i
++) {
1708 r600_write_value(cs
, cb
[i
]->cb_color_view
);
1711 r600_write_context_reg_seq(cs
, R_028100_CB_COLOR0_MASK
, nr_cbufs
);
1712 for (i
= 0; i
< nr_cbufs
; i
++) {
1713 r600_write_value(cs
, cb
[i
]->cb_color_mask
);
1717 r600_write_context_reg_seq(cs
, R_0280E0_CB_COLOR0_FRAG
, nr_cbufs
);
1718 for (i
= 0; i
< nr_cbufs
; i
++) {
1719 r600_write_value(cs
, cb
[i
]->cb_color_fmask
);
1722 for (i
= 0; i
< nr_cbufs
; i
++) {
1723 unsigned reloc
= r600_context_bo_reloc(rctx
,
1724 cb
[i
]->cb_buffer_fmask
,
1725 RADEON_USAGE_READWRITE
);
1726 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1727 r600_write_value(cs
, reloc
);
1731 r600_write_context_reg_seq(cs
, R_0280C0_CB_COLOR0_TILE
, nr_cbufs
);
1732 for (i
= 0; i
< nr_cbufs
; i
++) {
1733 r600_write_value(cs
, cb
[i
]->cb_color_cmask
);
1736 for (i
= 0; i
< nr_cbufs
; i
++) {
1737 unsigned reloc
= r600_context_bo_reloc(rctx
,
1738 cb
[i
]->cb_buffer_cmask
,
1739 RADEON_USAGE_READWRITE
);
1740 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1741 r600_write_value(cs
, reloc
);
1744 sbu
|= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs
);
1749 struct r600_surface
*surf
= (struct r600_surface
*)state
->zsbuf
;
1750 unsigned reloc
= r600_context_bo_reloc(rctx
,
1751 (struct r600_resource
*)state
->zsbuf
->texture
,
1752 RADEON_USAGE_READWRITE
);
1754 r600_write_context_reg(cs
, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1755 surf
->pa_su_poly_offset_db_fmt_cntl
);
1757 r600_write_context_reg_seq(cs
, R_028000_DB_DEPTH_SIZE
, 2);
1758 r600_write_value(cs
, surf
->db_depth_size
); /* R_028000_DB_DEPTH_SIZE */
1759 r600_write_value(cs
, surf
->db_depth_view
); /* R_028004_DB_DEPTH_VIEW */
1760 r600_write_context_reg_seq(cs
, R_02800C_DB_DEPTH_BASE
, 2);
1761 r600_write_value(cs
, surf
->db_depth_base
); /* R_02800C_DB_DEPTH_BASE */
1762 r600_write_value(cs
, surf
->db_depth_info
); /* R_028010_DB_DEPTH_INFO */
1764 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1765 r600_write_value(cs
, reloc
);
1767 r600_write_context_reg(cs
, R_028D34_DB_PREFETCH_LIMIT
, surf
->db_prefetch_limit
);
1769 sbu
|= SURFACE_BASE_UPDATE_DEPTH
;
1770 } else if (rctx
->screen
->info
.drm_minor
>= 18) {
1771 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1772 * Older kernels are out of luck. */
1773 r600_write_context_reg(cs
, R_028010_DB_DEPTH_INFO
, S_028010_FORMAT(V_028010_DEPTH_INVALID
));
1776 /* SURFACE_BASE_UPDATE */
1777 if (rctx
->family
> CHIP_R600
&& rctx
->family
< CHIP_RV770
&& sbu
) {
1778 r600_write_value(cs
, PKT3(PKT3_SURFACE_BASE_UPDATE
, 0, 0));
1779 r600_write_value(cs
, sbu
);
1782 /* Framebuffer dimensions. */
1783 r600_write_context_reg_seq(cs
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, 2);
1784 r600_write_value(cs
, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1785 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1786 r600_write_value(cs
, S_028244_BR_X(state
->width
) |
1787 S_028244_BR_Y(state
->height
)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1789 if (rctx
->framebuffer
.is_msaa_resolve
) {
1790 r600_write_context_reg(cs
, R_0287A0_CB_SHADER_CONTROL
, 1);
1792 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1793 * will assure that the alpha-test will work even if there is
1794 * no colorbuffer bound. */
1795 r600_write_context_reg(cs
, R_0287A0_CB_SHADER_CONTROL
,
1796 (1ull << MAX2(nr_cbufs
, 1)) - 1);
1799 r600_emit_msaa_state(rctx
, rctx
->framebuffer
.nr_samples
);
1802 static void r600_emit_cb_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1804 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1805 struct r600_cb_misc_state
*a
= (struct r600_cb_misc_state
*)atom
;
1807 if (G_028808_SPECIAL_OP(a
->cb_color_control
) == V_028808_SPECIAL_RESOLVE_BOX
) {
1808 r600_write_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1809 if (rctx
->chip_class
== R600
) {
1810 r600_write_value(cs
, 0xff); /* R_028238_CB_TARGET_MASK */
1811 r600_write_value(cs
, 0xff); /* R_02823C_CB_SHADER_MASK */
1813 r600_write_value(cs
, 0xf); /* R_028238_CB_TARGET_MASK */
1814 r600_write_value(cs
, 0xf); /* R_02823C_CB_SHADER_MASK */
1816 r600_write_context_reg(cs
, R_028808_CB_COLOR_CONTROL
, a
->cb_color_control
);
1818 unsigned fb_colormask
= (1ULL << ((unsigned)a
->nr_cbufs
* 4)) - 1;
1819 unsigned ps_colormask
= (1ULL << ((unsigned)a
->nr_ps_color_outputs
* 4)) - 1;
1820 unsigned multiwrite
= a
->multiwrite
&& a
->nr_cbufs
> 1;
1822 r600_write_context_reg_seq(cs
, R_028238_CB_TARGET_MASK
, 2);
1823 r600_write_value(cs
, a
->blend_colormask
& fb_colormask
); /* R_028238_CB_TARGET_MASK */
1824 /* Always enable the first color output to make sure alpha-test works even without one. */
1825 r600_write_value(cs
, 0xf | (multiwrite
? fb_colormask
: ps_colormask
)); /* R_02823C_CB_SHADER_MASK */
1826 r600_write_context_reg(cs
, R_028808_CB_COLOR_CONTROL
,
1827 a
->cb_color_control
|
1828 S_028808_MULTIWRITE_ENABLE(multiwrite
));
1832 static void r600_emit_db_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1834 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1835 struct r600_db_misc_state
*a
= (struct r600_db_misc_state
*)atom
;
1836 unsigned db_render_control
= 0;
1837 unsigned db_render_override
=
1838 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE
) |
1839 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE
) |
1840 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE
);
1842 if (a
->occlusion_query_enabled
) {
1843 if (rctx
->chip_class
>= R700
) {
1844 db_render_control
|= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1846 db_render_override
|= S_028D10_NOOP_CULL_DISABLE(1);
1848 if (a
->flush_depthstencil_through_cb
) {
1849 assert(a
->copy_depth
|| a
->copy_stencil
);
1851 db_render_control
|= S_028D0C_DEPTH_COPY_ENABLE(a
->copy_depth
) |
1852 S_028D0C_STENCIL_COPY_ENABLE(a
->copy_stencil
) |
1853 S_028D0C_COPY_CENTROID(1) |
1854 S_028D0C_COPY_SAMPLE(a
->copy_sample
);
1857 r600_write_context_reg_seq(cs
, R_028D0C_DB_RENDER_CONTROL
, 2);
1858 r600_write_value(cs
, db_render_control
); /* R_028D0C_DB_RENDER_CONTROL */
1859 r600_write_value(cs
, db_render_override
); /* R_028D10_DB_RENDER_OVERRIDE */
1862 static void r600_emit_vertex_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1864 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1865 uint32_t dirty_mask
= rctx
->vertex_buffer_state
.dirty_mask
;
1867 while (dirty_mask
) {
1868 struct pipe_vertex_buffer
*vb
;
1869 struct r600_resource
*rbuffer
;
1871 unsigned buffer_index
= u_bit_scan(&dirty_mask
);
1873 vb
= &rctx
->vertex_buffer_state
.vb
[buffer_index
];
1874 rbuffer
= (struct r600_resource
*)vb
->buffer
;
1877 offset
= vb
->buffer_offset
;
1879 /* fetch resources start at index 320 */
1880 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1881 r600_write_value(cs
, (320 + buffer_index
) * 7);
1882 r600_write_value(cs
, offset
); /* RESOURCEi_WORD0 */
1883 r600_write_value(cs
, rbuffer
->buf
->size
- offset
- 1); /* RESOURCEi_WORD1 */
1884 r600_write_value(cs
, /* RESOURCEi_WORD2 */
1885 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1886 S_038008_STRIDE(vb
->stride
));
1887 r600_write_value(cs
, 0); /* RESOURCEi_WORD3 */
1888 r600_write_value(cs
, 0); /* RESOURCEi_WORD4 */
1889 r600_write_value(cs
, 0); /* RESOURCEi_WORD5 */
1890 r600_write_value(cs
, 0xc0000000); /* RESOURCEi_WORD6 */
1892 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1893 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
1897 static void r600_emit_constant_buffers(struct r600_context
*rctx
,
1898 struct r600_constbuf_state
*state
,
1899 unsigned buffer_id_base
,
1900 unsigned reg_alu_constbuf_size
,
1901 unsigned reg_alu_const_cache
)
1903 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1904 uint32_t dirty_mask
= state
->dirty_mask
;
1906 while (dirty_mask
) {
1907 struct pipe_constant_buffer
*cb
;
1908 struct r600_resource
*rbuffer
;
1910 unsigned buffer_index
= ffs(dirty_mask
) - 1;
1912 cb
= &state
->cb
[buffer_index
];
1913 rbuffer
= (struct r600_resource
*)cb
->buffer
;
1916 offset
= cb
->buffer_offset
;
1918 r600_write_context_reg(cs
, reg_alu_constbuf_size
+ buffer_index
* 4,
1919 ALIGN_DIVUP(cb
->buffer_size
>> 4, 16));
1920 r600_write_context_reg(cs
, reg_alu_const_cache
+ buffer_index
* 4, offset
>> 8);
1922 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1923 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
1925 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1926 r600_write_value(cs
, (buffer_id_base
+ buffer_index
) * 7);
1927 r600_write_value(cs
, offset
); /* RESOURCEi_WORD0 */
1928 r600_write_value(cs
, rbuffer
->buf
->size
- offset
- 1); /* RESOURCEi_WORD1 */
1929 r600_write_value(cs
, /* RESOURCEi_WORD2 */
1930 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1931 S_038008_STRIDE(16));
1932 r600_write_value(cs
, 0); /* RESOURCEi_WORD3 */
1933 r600_write_value(cs
, 0); /* RESOURCEi_WORD4 */
1934 r600_write_value(cs
, 0); /* RESOURCEi_WORD5 */
1935 r600_write_value(cs
, 0xc0000000); /* RESOURCEi_WORD6 */
1937 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1938 r600_write_value(cs
, r600_context_bo_reloc(rctx
, rbuffer
, RADEON_USAGE_READ
));
1940 dirty_mask
&= ~(1 << buffer_index
);
1942 state
->dirty_mask
= 0;
1945 static void r600_emit_vs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1947 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
], 160,
1948 R_028180_ALU_CONST_BUFFER_SIZE_VS_0
,
1949 R_028980_ALU_CONST_CACHE_VS_0
);
1952 static void r600_emit_gs_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1954 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
], 336,
1955 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0
,
1956 R_0289C0_ALU_CONST_CACHE_GS_0
);
1959 static void r600_emit_ps_constant_buffers(struct r600_context
*rctx
, struct r600_atom
*atom
)
1961 r600_emit_constant_buffers(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
], 0,
1962 R_028140_ALU_CONST_BUFFER_SIZE_PS_0
,
1963 R_028940_ALU_CONST_CACHE_PS_0
);
1966 static void r600_emit_sampler_views(struct r600_context
*rctx
,
1967 struct r600_samplerview_state
*state
,
1968 unsigned resource_id_base
)
1970 struct radeon_winsys_cs
*cs
= rctx
->cs
;
1971 uint32_t dirty_mask
= state
->dirty_mask
;
1973 while (dirty_mask
) {
1974 struct r600_pipe_sampler_view
*rview
;
1975 unsigned resource_index
= u_bit_scan(&dirty_mask
);
1978 rview
= state
->views
[resource_index
];
1981 r600_write_value(cs
, PKT3(PKT3_SET_RESOURCE
, 7, 0));
1982 r600_write_value(cs
, (resource_id_base
+ resource_index
) * 7);
1983 r600_write_array(cs
, 7, rview
->tex_resource_words
);
1985 /* XXX The kernel needs two relocations. This is stupid. */
1986 reloc
= r600_context_bo_reloc(rctx
, rview
->tex_resource
,
1988 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1989 r600_write_value(cs
, reloc
);
1990 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
1991 r600_write_value(cs
, reloc
);
1993 state
->dirty_mask
= 0;
2003 static void r600_emit_vs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2005 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
, 160 + R600_MAX_CONST_BUFFERS
);
2008 static void r600_emit_gs_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2010 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
, 336 + R600_MAX_CONST_BUFFERS
);
2013 static void r600_emit_ps_sampler_views(struct r600_context
*rctx
, struct r600_atom
*atom
)
2015 r600_emit_sampler_views(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
, R600_MAX_CONST_BUFFERS
);
2018 static void r600_emit_sampler_states(struct r600_context
*rctx
,
2019 struct r600_textures_info
*texinfo
,
2020 unsigned resource_id_base
,
2021 unsigned border_color_reg
)
2023 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2024 uint32_t dirty_mask
= texinfo
->states
.dirty_mask
;
2026 while (dirty_mask
) {
2027 struct r600_pipe_sampler_state
*rstate
;
2028 struct r600_pipe_sampler_view
*rview
;
2029 unsigned i
= u_bit_scan(&dirty_mask
);
2031 rstate
= texinfo
->states
.states
[i
];
2033 rview
= texinfo
->views
.views
[i
];
2035 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
2036 * filtering between layers.
2037 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
2040 enum pipe_texture_target target
= rview
->base
.texture
->target
;
2041 if (target
== PIPE_TEXTURE_1D_ARRAY
||
2042 target
== PIPE_TEXTURE_2D_ARRAY
) {
2043 rstate
->tex_sampler_words
[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
2044 texinfo
->is_array_sampler
[i
] = true;
2046 rstate
->tex_sampler_words
[0] &= C_03C000_TEX_ARRAY_OVERRIDE
;
2047 texinfo
->is_array_sampler
[i
] = false;
2051 r600_write_value(cs
, PKT3(PKT3_SET_SAMPLER
, 3, 0));
2052 r600_write_value(cs
, (resource_id_base
+ i
) * 3);
2053 r600_write_array(cs
, 3, rstate
->tex_sampler_words
);
2055 if (rstate
->border_color_use
) {
2058 offset
= border_color_reg
;
2060 r600_write_config_reg_seq(cs
, offset
, 4);
2061 r600_write_array(cs
, 4, rstate
->border_color
);
2064 texinfo
->states
.dirty_mask
= 0;
2067 static void r600_emit_vs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2069 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED
);
2072 static void r600_emit_gs_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2074 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED
);
2077 static void r600_emit_ps_sampler_states(struct r600_context
*rctx
, struct r600_atom
*atom
)
2079 r600_emit_sampler_states(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED
);
2082 static void r600_emit_seamless_cube_map(struct r600_context
*rctx
, struct r600_atom
*atom
)
2084 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2087 tmp
= S_009508_DISABLE_CUBE_ANISO(1) |
2088 S_009508_SYNC_GRADIENT(1) |
2089 S_009508_SYNC_WALKER(1) |
2090 S_009508_SYNC_ALIGNER(1);
2091 if (!rctx
->seamless_cube_map
.enabled
) {
2092 tmp
|= S_009508_DISABLE_CUBE_WRAP(1);
2094 r600_write_config_reg(cs
, R_009508_TA_CNTL_AUX
, tmp
);
2097 static void r600_emit_sample_mask(struct r600_context
*rctx
, struct r600_atom
*a
)
2099 struct r600_sample_mask
*s
= (struct r600_sample_mask
*)a
;
2100 uint8_t mask
= s
->sample_mask
;
2102 r600_write_context_reg(rctx
->cs
, R_028C48_PA_SC_AA_MASK
,
2103 mask
| (mask
<< 8) | (mask
<< 16) | (mask
<< 24));
2106 static void r600_emit_vertex_fetch_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
2108 struct radeon_winsys_cs
*cs
= rctx
->cs
;
2109 struct r600_cso_state
*state
= (struct r600_cso_state
*)a
;
2110 struct r600_resource
*shader
= (struct r600_resource
*)state
->cso
;
2112 r600_write_context_reg(cs
, R_028894_SQ_PGM_START_FS
, 0);
2113 r600_write_value(cs
, PKT3(PKT3_NOP
, 0, 0));
2114 r600_write_value(cs
, r600_context_bo_reloc(rctx
, shader
, RADEON_USAGE_READ
));
2117 void r600_init_state_functions(struct r600_context
*rctx
)
2122 * To avoid GPU lockup registers must be emited in a specific order
2123 * (no kidding ...). The order below is important and have been
2124 * partialy infered from analyzing fglrx command stream.
2126 * Don't reorder atom without carefully checking the effect (GPU lockup
2127 * or piglit regression).
2131 r600_init_atom(rctx
, &rctx
->framebuffer
.atom
, id
++, r600_emit_framebuffer_state
, 0);
2134 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_VERTEX
].atom
, id
++, r600_emit_vs_constant_buffers
, 0);
2135 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_GEOMETRY
].atom
, id
++, r600_emit_gs_constant_buffers
, 0);
2136 r600_init_atom(rctx
, &rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
].atom
, id
++, r600_emit_ps_constant_buffers
, 0);
2138 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2139 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
2141 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].states
.atom
, id
++, r600_emit_vs_sampler_states
, 0);
2142 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].states
.atom
, id
++, r600_emit_gs_sampler_states
, 0);
2143 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].states
.atom
, id
++, r600_emit_ps_sampler_states
, 0);
2145 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_VERTEX
].views
.atom
, id
++, r600_emit_vs_sampler_views
, 0);
2146 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_GEOMETRY
].views
.atom
, id
++, r600_emit_gs_sampler_views
, 0);
2147 r600_init_atom(rctx
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.atom
, id
++, r600_emit_ps_sampler_views
, 0);
2148 r600_init_atom(rctx
, &rctx
->vertex_buffer_state
.atom
, id
++, r600_emit_vertex_buffers
, 0);
2150 r600_init_atom(rctx
, &rctx
->vgt_state
.atom
, id
++, r600_emit_vgt_state
, 6);
2151 r600_init_atom(rctx
, &rctx
->vgt2_state
.atom
, id
++, r600_emit_vgt2_state
, 3);
2153 r600_init_atom(rctx
, &rctx
->seamless_cube_map
.atom
, id
++, r600_emit_seamless_cube_map
, 3);
2154 r600_init_atom(rctx
, &rctx
->sample_mask
.atom
, id
++, r600_emit_sample_mask
, 3);
2155 rctx
->sample_mask
.sample_mask
= ~0;
2157 r600_init_atom(rctx
, &rctx
->alphatest_state
.atom
, id
++, r600_emit_alphatest_state
, 6);
2158 r600_init_atom(rctx
, &rctx
->blend_color
.atom
, id
++, r600_emit_blend_color
, 6);
2159 r600_init_atom(rctx
, &rctx
->blend_state
.atom
, id
++, r600_emit_cso_state
, 0);
2160 r600_init_atom(rctx
, &rctx
->cb_misc_state
.atom
, id
++, r600_emit_cb_misc_state
, 7);
2161 r600_init_atom(rctx
, &rctx
->clip_misc_state
.atom
, id
++, r600_emit_clip_misc_state
, 6);
2162 r600_init_atom(rctx
, &rctx
->clip_state
.atom
, id
++, r600_emit_clip_state
, 26);
2163 r600_init_atom(rctx
, &rctx
->db_misc_state
.atom
, id
++, r600_emit_db_misc_state
, 4);
2164 r600_init_atom(rctx
, &rctx
->dsa_state
.atom
, id
++, r600_emit_cso_state
, 0);
2165 r600_init_atom(rctx
, &rctx
->poly_offset_state
.atom
, id
++, r600_emit_polygon_offset
, 6);
2166 r600_init_atom(rctx
, &rctx
->rasterizer_state
.atom
, id
++, r600_emit_cso_state
, 0);
2167 r600_init_atom(rctx
, &rctx
->scissor
.atom
, id
++, r600_emit_scissor_state
, 4);
2168 r600_init_atom(rctx
, &rctx
->stencil_ref
.atom
, id
++, r600_emit_stencil_ref
, 4);
2169 r600_init_atom(rctx
, &rctx
->viewport
.atom
, id
++, r600_emit_viewport_state
, 8);
2170 r600_init_atom(rctx
, &rctx
->vertex_fetch_shader
.atom
, id
++, r600_emit_vertex_fetch_shader
, 5);
2172 rctx
->context
.create_blend_state
= r600_create_blend_state
;
2173 rctx
->context
.create_depth_stencil_alpha_state
= r600_create_dsa_state
;
2174 rctx
->context
.create_rasterizer_state
= r600_create_rs_state
;
2175 rctx
->context
.create_sampler_state
= r600_create_sampler_state
;
2176 rctx
->context
.create_sampler_view
= r600_create_sampler_view
;
2177 rctx
->context
.set_framebuffer_state
= r600_set_framebuffer_state
;
2178 rctx
->context
.set_polygon_stipple
= r600_set_polygon_stipple
;
2179 rctx
->context
.set_scissor_state
= r600_set_scissor_state
;
2182 /* Adjust GPR allocation on R6xx/R7xx */
2183 void r600_adjust_gprs(struct r600_context
*rctx
)
2185 struct r600_pipe_state rstate
;
2186 unsigned num_ps_gprs
= rctx
->default_ps_gprs
;
2187 unsigned num_vs_gprs
= rctx
->default_vs_gprs
;
2191 if (rctx
->ps_shader
->current
->shader
.bc
.ngpr
> rctx
->default_ps_gprs
) {
2192 diff
= rctx
->ps_shader
->current
->shader
.bc
.ngpr
- rctx
->default_ps_gprs
;
2193 num_vs_gprs
-= diff
;
2194 num_ps_gprs
+= diff
;
2197 if (rctx
->vs_shader
->current
->shader
.bc
.ngpr
> rctx
->default_vs_gprs
)
2199 diff
= rctx
->vs_shader
->current
->shader
.bc
.ngpr
- rctx
->default_vs_gprs
;
2200 num_ps_gprs
-= diff
;
2201 num_vs_gprs
+= diff
;
2205 tmp
|= S_008C04_NUM_PS_GPRS(num_ps_gprs
);
2206 tmp
|= S_008C04_NUM_VS_GPRS(num_vs_gprs
);
2207 tmp
|= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx
->r6xx_num_clause_temp_gprs
);
2209 r600_pipe_state_add_reg(&rstate
, R_008C04_SQ_GPR_RESOURCE_MGMT_1
, tmp
);
2211 r600_context_pipe_state_set(rctx
, &rstate
);
2214 void r600_init_atom_start_cs(struct r600_context
*rctx
)
2229 int num_ps_stack_entries
;
2230 int num_vs_stack_entries
;
2231 int num_gs_stack_entries
;
2232 int num_es_stack_entries
;
2233 enum radeon_family family
;
2234 struct r600_command_buffer
*cb
= &rctx
->start_cs_cmd
;
2237 r600_init_command_buffer(cb
, 256);
2239 /* R6xx requires this packet at the start of each command buffer */
2240 if (rctx
->chip_class
== R600
) {
2241 r600_store_value(cb
, PKT3(PKT3_START_3D_CMDBUF
, 0, 0));
2242 r600_store_value(cb
, 0);
2244 /* All asics require this one */
2245 r600_store_value(cb
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2246 r600_store_value(cb
, 0x80000000);
2247 r600_store_value(cb
, 0x80000000);
2249 family
= rctx
->family
;
2261 num_ps_threads
= 136;
2262 num_vs_threads
= 48;
2265 num_ps_stack_entries
= 128;
2266 num_vs_stack_entries
= 128;
2267 num_gs_stack_entries
= 0;
2268 num_es_stack_entries
= 0;
2277 num_ps_threads
= 144;
2278 num_vs_threads
= 40;
2281 num_ps_stack_entries
= 40;
2282 num_vs_stack_entries
= 40;
2283 num_gs_stack_entries
= 32;
2284 num_es_stack_entries
= 16;
2296 num_ps_threads
= 136;
2297 num_vs_threads
= 48;
2300 num_ps_stack_entries
= 40;
2301 num_vs_stack_entries
= 40;
2302 num_gs_stack_entries
= 32;
2303 num_es_stack_entries
= 16;
2311 num_ps_threads
= 136;
2312 num_vs_threads
= 48;
2315 num_ps_stack_entries
= 40;
2316 num_vs_stack_entries
= 40;
2317 num_gs_stack_entries
= 32;
2318 num_es_stack_entries
= 16;
2326 num_ps_threads
= 188;
2327 num_vs_threads
= 60;
2330 num_ps_stack_entries
= 256;
2331 num_vs_stack_entries
= 256;
2332 num_gs_stack_entries
= 0;
2333 num_es_stack_entries
= 0;
2342 num_ps_threads
= 188;
2343 num_vs_threads
= 60;
2346 num_ps_stack_entries
= 128;
2347 num_vs_stack_entries
= 128;
2348 num_gs_stack_entries
= 0;
2349 num_es_stack_entries
= 0;
2357 num_ps_threads
= 144;
2358 num_vs_threads
= 48;
2361 num_ps_stack_entries
= 128;
2362 num_vs_stack_entries
= 128;
2363 num_gs_stack_entries
= 0;
2364 num_es_stack_entries
= 0;
2368 rctx
->default_ps_gprs
= num_ps_gprs
;
2369 rctx
->default_vs_gprs
= num_vs_gprs
;
2370 rctx
->r6xx_num_clause_temp_gprs
= num_temp_gprs
;
2382 tmp
|= S_008C00_VC_ENABLE(1);
2385 tmp
|= S_008C00_DX9_CONSTS(0);
2386 tmp
|= S_008C00_ALU_INST_PREFER_VECTOR(1);
2387 tmp
|= S_008C00_PS_PRIO(ps_prio
);
2388 tmp
|= S_008C00_VS_PRIO(vs_prio
);
2389 tmp
|= S_008C00_GS_PRIO(gs_prio
);
2390 tmp
|= S_008C00_ES_PRIO(es_prio
);
2391 r600_store_config_reg(cb
, R_008C00_SQ_CONFIG
, tmp
);
2393 /* SQ_GPR_RESOURCE_MGMT_2 */
2394 tmp
= S_008C08_NUM_GS_GPRS(num_gs_gprs
);
2395 tmp
|= S_008C08_NUM_ES_GPRS(num_es_gprs
);
2396 r600_store_config_reg_seq(cb
, R_008C08_SQ_GPR_RESOURCE_MGMT_2
, 4);
2397 r600_store_value(cb
, tmp
);
2399 /* SQ_THREAD_RESOURCE_MGMT */
2400 tmp
= S_008C0C_NUM_PS_THREADS(num_ps_threads
);
2401 tmp
|= S_008C0C_NUM_VS_THREADS(num_vs_threads
);
2402 tmp
|= S_008C0C_NUM_GS_THREADS(num_gs_threads
);
2403 tmp
|= S_008C0C_NUM_ES_THREADS(num_es_threads
);
2404 r600_store_value(cb
, tmp
); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2406 /* SQ_STACK_RESOURCE_MGMT_1 */
2407 tmp
= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries
);
2408 tmp
|= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries
);
2409 r600_store_value(cb
, tmp
); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2411 /* SQ_STACK_RESOURCE_MGMT_2 */
2412 tmp
= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries
);
2413 tmp
|= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries
);
2414 r600_store_value(cb
, tmp
); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2416 r600_store_config_reg(cb
, R_009714_VC_ENHANCE
, 0);
2418 if (rctx
->chip_class
>= R700
) {
2419 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0x00004000);
2420 r600_store_config_reg(cb
, R_009830_DB_DEBUG
, 0);
2421 r600_store_config_reg(cb
, R_009838_DB_WATERMARKS
, 0x00420204);
2422 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 0);
2424 r600_store_config_reg(cb
, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
, 0);
2425 r600_store_config_reg(cb
, R_009830_DB_DEBUG
, 0x82000000);
2426 r600_store_config_reg(cb
, R_009838_DB_WATERMARKS
, 0x01020204);
2427 r600_store_context_reg(cb
, R_0286C8_SPI_THREAD_GROUPING
, 1);
2429 r600_store_context_reg_seq(cb
, R_0288A8_SQ_ESGS_RING_ITEMSIZE
, 9);
2430 r600_store_value(cb
, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2431 r600_store_value(cb
, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2432 r600_store_value(cb
, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2433 r600_store_value(cb
, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2434 r600_store_value(cb
, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2435 r600_store_value(cb
, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2436 r600_store_value(cb
, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2437 r600_store_value(cb
, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2438 r600_store_value(cb
, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2440 /* to avoid GPU doing any preloading of constant from random address */
2441 r600_store_context_reg_seq(cb
, R_028140_ALU_CONST_BUFFER_SIZE_PS_0
, 8);
2442 r600_store_value(cb
, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2443 r600_store_value(cb
, 0);
2444 r600_store_value(cb
, 0);
2445 r600_store_value(cb
, 0);
2446 r600_store_value(cb
, 0);
2447 r600_store_value(cb
, 0);
2448 r600_store_value(cb
, 0);
2449 r600_store_value(cb
, 0);
2450 r600_store_context_reg_seq(cb
, R_028180_ALU_CONST_BUFFER_SIZE_VS_0
, 8);
2451 r600_store_value(cb
, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2452 r600_store_value(cb
, 0);
2453 r600_store_value(cb
, 0);
2454 r600_store_value(cb
, 0);
2455 r600_store_value(cb
, 0);
2456 r600_store_value(cb
, 0);
2457 r600_store_value(cb
, 0);
2458 r600_store_value(cb
, 0);
2460 r600_store_context_reg_seq(cb
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 13);
2461 r600_store_value(cb
, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2462 r600_store_value(cb
, 0); /* R_028A14_VGT_HOS_CNTL */
2463 r600_store_value(cb
, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2464 r600_store_value(cb
, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2465 r600_store_value(cb
, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2466 r600_store_value(cb
, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2467 r600_store_value(cb
, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2468 r600_store_value(cb
, 0); /* R_028A2C_VGT_GROUP_DECR */
2469 r600_store_value(cb
, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2470 r600_store_value(cb
, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2471 r600_store_value(cb
, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2472 r600_store_value(cb
, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2473 r600_store_value(cb
, 0); /* R_028A40_VGT_GS_MODE, 0); */
2475 r600_store_context_reg(cb
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
2476 r600_store_context_reg(cb
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 0);
2477 r600_store_context_reg(cb
, R_028AA4_VGT_INSTANCE_STEP_RATE_1
, 0);
2479 r600_store_context_reg_seq(cb
, R_028AB0_VGT_STRMOUT_EN
, 3);
2480 r600_store_value(cb
, 0); /* R_028AB0_VGT_STRMOUT_EN */
2481 r600_store_value(cb
, 1); /* R_028AB4_VGT_REUSE_OFF */
2482 r600_store_value(cb
, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2484 r600_store_context_reg(cb
, R_028B20_VGT_STRMOUT_BUFFER_EN
, 0);
2486 r600_store_ctl_const(cb
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
2488 r600_store_context_reg_seq(cb
, R_028028_DB_STENCIL_CLEAR
, 2);
2489 r600_store_value(cb
, 0); /* R_028028_DB_STENCIL_CLEAR */
2490 r600_store_value(cb
, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2492 r600_store_context_reg_seq(cb
, R_0286DC_SPI_FOG_CNTL
, 3);
2493 r600_store_value(cb
, 0); /* R_0286DC_SPI_FOG_CNTL */
2494 r600_store_value(cb
, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2495 r600_store_value(cb
, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2497 r600_store_context_reg_seq(cb
, R_028D2C_DB_SRESULTS_COMPARE_STATE1
, 2);
2498 r600_store_value(cb
, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2499 r600_store_value(cb
, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2501 r600_store_context_reg(cb
, R_028820_PA_CL_NANINF_CNTL
, 0);
2502 r600_store_context_reg(cb
, R_028A48_PA_SC_MPASS_PS_CNTL
, 0);
2504 r600_store_context_reg_seq(cb
, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ
, 4);
2505 r600_store_value(cb
, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2506 r600_store_value(cb
, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2507 r600_store_value(cb
, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2508 r600_store_value(cb
, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2510 r600_store_context_reg_seq(cb
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
2511 r600_store_value(cb
, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2512 r600_store_value(cb
, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2514 r600_store_context_reg(cb
, R_028818_PA_CL_VTE_CNTL
, 0x43F);
2516 r600_store_context_reg(cb
, R_028200_PA_SC_WINDOW_OFFSET
, 0);
2517 r600_store_context_reg(cb
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
2519 if (rctx
->chip_class
>= R700
) {
2520 r600_store_context_reg(cb
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2523 r600_store_context_reg_seq(cb
, R_028C30_CB_CLRCMP_CONTROL
, 4);
2524 r600_store_value(cb
, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2525 r600_store_value(cb
, 0); /* R_028C34_CB_CLRCMP_SRC */
2526 r600_store_value(cb
, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2527 r600_store_value(cb
, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2529 r600_store_context_reg_seq(cb
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 2);
2530 r600_store_value(cb
, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2531 r600_store_value(cb
, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2533 r600_store_context_reg_seq(cb
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, 2);
2534 r600_store_value(cb
, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2535 r600_store_value(cb
, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2537 r600_store_context_reg_seq(cb
, R_0288CC_SQ_PGM_CF_OFFSET_PS
, 2);
2538 r600_store_value(cb
, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2539 r600_store_value(cb
, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2541 r600_store_context_reg_seq(cb
, R_028380_SQ_VTX_SEMANTIC_0
, 34);
2542 r600_store_value(cb
, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2543 r600_store_value(cb
, 0);
2544 r600_store_value(cb
, 0);
2545 r600_store_value(cb
, 0);
2546 r600_store_value(cb
, 0);
2547 r600_store_value(cb
, 0);
2548 r600_store_value(cb
, 0);
2549 r600_store_value(cb
, 0);
2550 r600_store_value(cb
, 0);
2551 r600_store_value(cb
, 0);
2552 r600_store_value(cb
, 0);
2553 r600_store_value(cb
, 0);
2554 r600_store_value(cb
, 0);
2555 r600_store_value(cb
, 0);
2556 r600_store_value(cb
, 0);
2557 r600_store_value(cb
, 0);
2558 r600_store_value(cb
, 0);
2559 r600_store_value(cb
, 0);
2560 r600_store_value(cb
, 0);
2561 r600_store_value(cb
, 0);
2562 r600_store_value(cb
, 0);
2563 r600_store_value(cb
, 0);
2564 r600_store_value(cb
, 0);
2565 r600_store_value(cb
, 0);
2566 r600_store_value(cb
, 0);
2567 r600_store_value(cb
, 0);
2568 r600_store_value(cb
, 0);
2569 r600_store_value(cb
, 0);
2570 r600_store_value(cb
, 0);
2571 r600_store_value(cb
, 0);
2572 r600_store_value(cb
, 0);
2573 r600_store_value(cb
, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2574 r600_store_value(cb
, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2575 r600_store_value(cb
, 0); /* R_028404_VGT_MIN_VTX_INDX */
2577 r600_store_context_reg(cb
, R_0288A4_SQ_PGM_RESOURCES_FS
, 0);
2578 r600_store_context_reg(cb
, R_0288DC_SQ_PGM_CF_OFFSET_FS
, 0);
2580 if (rctx
->chip_class
== R700
&& rctx
->screen
->has_streamout
)
2581 r600_store_context_reg(cb
, R_028354_SX_SURFACE_SYNC
, S_028354_SURFACE_SYNC_MASK(0xf));
2582 r600_store_context_reg(cb
, R_028800_DB_DEPTH_CONTROL
, 0);
2583 if (rctx
->screen
->has_streamout
) {
2584 r600_store_context_reg(cb
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
2587 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
, 0x1000FFF);
2588 r600_store_loop_const(cb
, R_03E200_SQ_LOOP_CONST_0
+ (32 * 4), 0x1000FFF);
2591 void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2593 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2594 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2595 struct r600_shader
*rshader
= &shader
->shader
;
2596 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
, db_shader_control
;
2597 int pos_index
= -1, face_index
= -1;
2598 unsigned tmp
, sid
, ufi
= 0;
2599 int need_linear
= 0;
2600 unsigned z_export
= 0, stencil_export
= 0;
2601 unsigned sprite_coord_enable
= rctx
->rasterizer
? rctx
->rasterizer
->sprite_coord_enable
: 0;
2605 for (i
= 0; i
< rshader
->ninput
; i
++) {
2606 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
2608 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
2611 sid
= rshader
->input
[i
].spi_sid
;
2613 tmp
= S_028644_SEMANTIC(sid
);
2615 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
||
2616 rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2617 (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
2618 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
))
2619 tmp
|= S_028644_FLAT_SHADE(1);
2621 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_GENERIC
&&
2622 sprite_coord_enable
& (1 << rshader
->input
[i
].sid
)) {
2623 tmp
|= S_028644_PT_SPRITE_TEX(1);
2626 if (rshader
->input
[i
].centroid
)
2627 tmp
|= S_028644_SEL_CENTROID(1);
2629 if (rshader
->input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
) {
2631 tmp
|= S_028644_SEL_LINEAR(1);
2634 r600_pipe_state_add_reg(rstate
, R_028644_SPI_PS_INPUT_CNTL_0
+ i
* 4,
2638 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2639 for (i
= 0; i
< rshader
->noutput
; i
++) {
2640 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2642 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
2645 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(z_export
);
2646 db_shader_control
|= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export
);
2647 if (rshader
->uses_kill
)
2648 db_shader_control
|= S_02880C_KILL_ENABLE(1);
2651 for (i
= 0; i
< rshader
->noutput
; i
++) {
2652 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
||
2653 rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
) {
2657 num_cout
= rshader
->nr_ps_color_exports
;
2658 exports_ps
|= S_028854_EXPORT_COLORS(num_cout
);
2660 /* always at least export 1 component per pixel */
2664 shader
->nr_ps_color_outputs
= num_cout
;
2666 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(rshader
->ninput
) |
2667 S_0286CC_PERSP_GRADIENT_ENA(1)|
2668 S_0286CC_LINEAR_GRADIENT_ENA(need_linear
);
2670 if (pos_index
!= -1) {
2671 spi_ps_in_control_0
|= (S_0286CC_POSITION_ENA(1) |
2672 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
2673 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
) |
2674 S_0286CC_BARYC_SAMPLE_CNTL(1));
2678 spi_ps_in_control_1
= 0;
2679 if (face_index
!= -1) {
2680 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
2681 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
2684 /* HW bug in original R600 */
2685 if (rctx
->family
== CHIP_R600
)
2688 r600_pipe_state_add_reg(rstate
, R_0286CC_SPI_PS_IN_CONTROL_0
, spi_ps_in_control_0
);
2689 r600_pipe_state_add_reg(rstate
, R_0286D0_SPI_PS_IN_CONTROL_1
, spi_ps_in_control_1
);
2690 r600_pipe_state_add_reg(rstate
, R_0286D8_SPI_INPUT_Z
, spi_input_z
);
2691 r600_pipe_state_add_reg_bo(rstate
,
2692 R_028840_SQ_PGM_START_PS
,
2693 0, shader
->bo
, RADEON_USAGE_READ
);
2694 r600_pipe_state_add_reg(rstate
,
2695 R_028850_SQ_PGM_RESOURCES_PS
,
2696 S_028850_NUM_GPRS(rshader
->bc
.ngpr
) |
2697 S_028850_STACK_SIZE(rshader
->bc
.nstack
) |
2698 S_028850_UNCACHED_FIRST_INST(ufi
));
2699 r600_pipe_state_add_reg(rstate
,
2700 R_028854_SQ_PGM_EXPORTS_PS
,
2702 /* only set some bits here, the other bits are set in the dsa state */
2703 shader
->db_shader_control
= db_shader_control
;
2704 shader
->ps_depth_export
= z_export
| stencil_export
;
2706 shader
->sprite_coord_enable
= sprite_coord_enable
;
2707 if (rctx
->rasterizer
)
2708 shader
->flatshade
= rctx
->rasterizer
->flatshade
;
2711 void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
2713 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2714 struct r600_pipe_state
*rstate
= &shader
->rstate
;
2715 struct r600_shader
*rshader
= &shader
->shader
;
2716 unsigned spi_vs_out_id
[10] = {};
2717 unsigned i
, tmp
, nparams
= 0;
2719 /* clear previous register */
2722 for (i
= 0; i
< rshader
->noutput
; i
++) {
2723 if (rshader
->output
[i
].spi_sid
) {
2724 tmp
= rshader
->output
[i
].spi_sid
<< ((nparams
& 3) * 8);
2725 spi_vs_out_id
[nparams
/ 4] |= tmp
;
2730 for (i
= 0; i
< 10; i
++) {
2731 r600_pipe_state_add_reg(rstate
,
2732 R_028614_SPI_VS_OUT_ID_0
+ i
* 4,
2736 /* Certain attributes (position, psize, etc.) don't count as params.
2737 * VS is required to export at least one param and r600_shader_from_tgsi()
2738 * takes care of adding a dummy export.
2743 r600_pipe_state_add_reg(rstate
,
2744 R_0286C4_SPI_VS_OUT_CONFIG
,
2745 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
2746 r600_pipe_state_add_reg(rstate
,
2747 R_028868_SQ_PGM_RESOURCES_VS
,
2748 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
2749 S_028868_STACK_SIZE(rshader
->bc
.nstack
));
2750 r600_pipe_state_add_reg_bo(rstate
,
2751 R_028858_SQ_PGM_START_VS
,
2752 0, shader
->bo
, RADEON_USAGE_READ
);
2754 shader
->pa_cl_vs_out_cntl
=
2755 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader
->clip_dist_write
& 0x0F) != 0) |
2756 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader
->clip_dist_write
& 0xF0) != 0) |
2757 S_02881C_VS_OUT_MISC_VEC_ENA(rshader
->vs_out_misc_write
) |
2758 S_02881C_USE_VTX_POINT_SIZE(rshader
->vs_out_point_size
);
2761 void *r600_create_resolve_blend(struct r600_context
*rctx
)
2763 struct pipe_blend_state blend
;
2766 memset(&blend
, 0, sizeof(blend
));
2767 blend
.independent_blend_enable
= true;
2768 for (i
= 0; i
< 2; i
++) {
2769 blend
.rt
[i
].colormask
= 0xf;
2770 blend
.rt
[i
].blend_enable
= 1;
2771 blend
.rt
[i
].rgb_func
= PIPE_BLEND_ADD
;
2772 blend
.rt
[i
].alpha_func
= PIPE_BLEND_ADD
;
2773 blend
.rt
[i
].rgb_src_factor
= PIPE_BLENDFACTOR_ZERO
;
2774 blend
.rt
[i
].rgb_dst_factor
= PIPE_BLENDFACTOR_ZERO
;
2775 blend
.rt
[i
].alpha_src_factor
= PIPE_BLENDFACTOR_ZERO
;
2776 blend
.rt
[i
].alpha_dst_factor
= PIPE_BLENDFACTOR_ZERO
;
2778 return r600_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_SPECIAL_RESOLVE_BOX
);
2781 void *r700_create_resolve_blend(struct r600_context
*rctx
)
2783 struct pipe_blend_state blend
;
2785 memset(&blend
, 0, sizeof(blend
));
2786 blend
.independent_blend_enable
= true;
2787 blend
.rt
[0].colormask
= 0xf;
2788 return r600_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_SPECIAL_RESOLVE_BOX
);
2791 void *r600_create_decompress_blend(struct r600_context
*rctx
)
2793 struct pipe_blend_state blend
;
2795 memset(&blend
, 0, sizeof(blend
));
2796 blend
.independent_blend_enable
= true;
2797 blend
.rt
[0].colormask
= 0xf;
2798 return r600_create_blend_state_mode(&rctx
->context
, &blend
, V_028808_SPECIAL_EXPAND_SAMPLES
);
2801 void *r600_create_db_flush_dsa(struct r600_context
*rctx
)
2803 struct pipe_depth_stencil_alpha_state dsa
;
2804 boolean quirk
= false;
2806 if (rctx
->family
== CHIP_RV610
|| rctx
->family
== CHIP_RV630
||
2807 rctx
->family
== CHIP_RV620
|| rctx
->family
== CHIP_RV635
)
2810 memset(&dsa
, 0, sizeof(dsa
));
2813 dsa
.depth
.enabled
= 1;
2814 dsa
.depth
.func
= PIPE_FUNC_LEQUAL
;
2815 dsa
.stencil
[0].enabled
= 1;
2816 dsa
.stencil
[0].func
= PIPE_FUNC_ALWAYS
;
2817 dsa
.stencil
[0].zpass_op
= PIPE_STENCIL_OP_KEEP
;
2818 dsa
.stencil
[0].zfail_op
= PIPE_STENCIL_OP_INCR
;
2819 dsa
.stencil
[0].writemask
= 0xff;
2822 return rctx
->context
.create_depth_stencil_alpha_state(&rctx
->context
, &dsa
);
2825 void r600_update_dual_export_state(struct r600_context
* rctx
)
2827 bool dual_export
= rctx
->framebuffer
.export_16bpc
&&
2828 !rctx
->ps_shader
->current
->ps_depth_export
;
2830 unsigned db_shader_control
= rctx
->ps_shader
->current
->db_shader_control
|
2831 S_02880C_DUAL_EXPORT_ENABLE(dual_export
);
2833 if (db_shader_control
!= rctx
->db_shader_control
) {
2834 struct r600_pipe_state rstate
;
2836 rctx
->db_shader_control
= db_shader_control
;
2838 r600_pipe_state_add_reg(&rstate
, R_02880C_DB_SHADER_CONTROL
, db_shader_control
);
2839 r600_context_pipe_state_set(rctx
, &rstate
);