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r600g: build fetch shader from vertex elements
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_double_list.h>
36 #include <util/u_pack_color.h>
37 #include <util/u_memory.h>
38 #include <util/u_inlines.h>
39 #include <util/u_upload_mgr.h>
40 #include <util/u_framebuffer.h>
41 #include <pipebuffer/pb_buffer.h>
42 #include "r600.h"
43 #include "r600d.h"
44 #include "r600_resource.h"
45 #include "r600_shader.h"
46 #include "r600_pipe.h"
47 #include "r600_state_inlines.h"
48
49 void r600_polygon_offset_update(struct r600_pipe_context *rctx)
50 {
51 struct r600_pipe_state state;
52
53 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
54 state.nregs = 0;
55 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
56 float offset_units = rctx->rasterizer->offset_units;
57 unsigned offset_db_fmt_cntl = 0, depth;
58
59 switch (rctx->framebuffer.zsbuf->texture->format) {
60 case PIPE_FORMAT_Z24X8_UNORM:
61 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
62 depth = -24;
63 offset_units *= 2.0f;
64 break;
65 case PIPE_FORMAT_Z32_FLOAT:
66 depth = -23;
67 offset_units *= 1.0f;
68 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
69 break;
70 case PIPE_FORMAT_Z16_UNORM:
71 depth = -16;
72 offset_units *= 4.0f;
73 break;
74 default:
75 return;
76 }
77 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
78 r600_pipe_state_add_reg(&state,
79 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
80 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
81 r600_pipe_state_add_reg(&state,
82 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
83 fui(offset_units), 0xFFFFFFFF, NULL);
84 r600_pipe_state_add_reg(&state,
85 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
86 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
87 r600_pipe_state_add_reg(&state,
88 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
89 fui(offset_units), 0xFFFFFFFF, NULL);
90 r600_pipe_state_add_reg(&state,
91 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
92 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
93 r600_context_pipe_state_set(&rctx->ctx, &state);
94 }
95 }
96
97 void r600_vertex_buffer_update(struct r600_pipe_context *rctx)
98 {
99 struct r600_pipe_state *rstate;
100 struct r600_resource *rbuffer;
101 struct pipe_vertex_buffer *vertex_buffer;
102 unsigned i, offset;
103
104 /* we don't update until we know vertex elements */
105 if (rctx->vertex_elements == NULL || !rctx->nvertex_buffer)
106 return;
107
108 /* delete previous translated vertex elements */
109 if (rctx->tran.new_velems) {
110 r600_end_vertex_translate(rctx);
111 }
112
113 if (rctx->vertex_elements->incompatible_layout) {
114 /* translate rebind new vertex elements so
115 * return once translated
116 */
117 r600_begin_vertex_translate(rctx);
118 return;
119 }
120
121 if (rctx->any_user_vbs) {
122 r600_upload_user_buffers(rctx);
123 rctx->any_user_vbs = FALSE;
124 }
125
126 if (rctx->vertex_elements->vbuffer_need_offset) {
127 /* one resource per vertex elements */
128 rctx->nvs_resource = rctx->vertex_elements->count;
129 } else {
130 /* bind vertex buffer once */
131 rctx->nvs_resource = rctx->nvertex_buffer;
132 }
133
134 for (i = 0 ; i < rctx->nvs_resource; i++) {
135 rstate = &rctx->vs_resource[i];
136 rstate->id = R600_PIPE_STATE_RESOURCE;
137 rstate->nregs = 0;
138
139 if (rctx->vertex_elements->vbuffer_need_offset) {
140 /* one resource per vertex elements */
141 unsigned vbuffer_index;
142 vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
143 vertex_buffer = &rctx->vertex_buffer[vbuffer_index];
144 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
145 offset = rctx->vertex_elements->vbuffer_offset[i] +
146 vertex_buffer->buffer_offset +
147 r600_bo_offset(rbuffer->bo);
148 } else {
149 /* bind vertex buffer once */
150 vertex_buffer = &rctx->vertex_buffer[i];
151 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
152 offset = vertex_buffer->buffer_offset +
153 r600_bo_offset(rbuffer->bo);
154 }
155
156 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
157 offset, 0xFFFFFFFF, rbuffer->bo);
158 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
159 rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
160 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
161 S_038008_STRIDE(vertex_buffer->stride),
162 0xFFFFFFFF, NULL);
163 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
164 0x00000000, 0xFFFFFFFF, NULL);
165 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
166 0x00000000, 0xFFFFFFFF, NULL);
167 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
168 0x00000000, 0xFFFFFFFF, NULL);
169 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
170 0xC0000000, 0xFFFFFFFF, NULL);
171 r600_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
172 }
173 }
174
175 static void r600_draw_common(struct r600_drawl *draw)
176 {
177 struct r600_pipe_context *rctx = (struct r600_pipe_context *)draw->ctx;
178 struct r600_pipe_state *rstate;
179 struct r600_resource *rbuffer;
180 unsigned i, j, offset, prim;
181 u32 vgt_dma_index_type, vgt_draw_initiator, mask;
182 struct pipe_vertex_buffer *vertex_buffer;
183 struct r600_draw rdraw;
184 struct r600_pipe_state vgt;
185
186 switch (draw->index_size) {
187 case 2:
188 vgt_draw_initiator = 0;
189 vgt_dma_index_type = 0;
190 break;
191 case 4:
192 vgt_draw_initiator = 0;
193 vgt_dma_index_type = 1;
194 break;
195 case 0:
196 vgt_draw_initiator = 2;
197 vgt_dma_index_type = 0;
198 break;
199 default:
200 R600_ERR("unsupported index size %d\n", draw->index_size);
201 return;
202 }
203 if (r600_conv_pipe_prim(draw->mode, &prim))
204 return;
205
206
207 /* rebuild vertex shader if input format changed */
208 if (r600_pipe_shader_update(&rctx->context, rctx->vs_shader))
209 return;
210 if (r600_pipe_shader_update(&rctx->context, rctx->ps_shader))
211 return;
212
213 #if 0
214 for (i = 0 ; i < rctx->vertex_elements->count; i++) {
215 uint32_t word2, format;
216
217 rstate = &rctx->vs_resource[i];
218 rstate->id = R600_PIPE_STATE_RESOURCE;
219 rstate->nregs = 0;
220
221 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
222 vertex_buffer = &rctx->vertex_buffer[j];
223 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
224 offset = rctx->vertex_elements->elements[i].src_offset +
225 vertex_buffer->buffer_offset +
226 r600_bo_offset(rbuffer->bo);
227
228 format = r600_translate_vertex_data_type(rctx->vertex_elements->hw_format[i]);
229
230 word2 = format | S_038008_STRIDE(vertex_buffer->stride);
231
232 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
233 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
234 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2, word2, 0xFFFFFFFF, NULL);
235 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3, 0x00000000, 0xFFFFFFFF, NULL);
236 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
237 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
238 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6, 0xC0000000, 0xFFFFFFFF, NULL);
239 r600_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
240 }
241 #endif
242
243 mask = 0;
244 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
245 mask |= (0xF << (i * 4));
246 }
247
248 vgt.id = R600_PIPE_STATE_VGT;
249 vgt.nregs = 0;
250 r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
251 r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw->index_bias, 0xFFFFFFFF, NULL);
252 r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw->max_index, 0xFFFFFFFF, NULL);
253 r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw->min_index, 0xFFFFFFFF, NULL);
254 r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
255 r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
256 r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
257 r600_context_pipe_state_set(&rctx->ctx, &vgt);
258
259 rdraw.vgt_num_indices = draw->count;
260 rdraw.vgt_num_instances = 1;
261 rdraw.vgt_index_type = vgt_dma_index_type;
262 rdraw.vgt_draw_initiator = vgt_draw_initiator;
263 rdraw.indices = NULL;
264 if (draw->index_buffer) {
265 rbuffer = (struct r600_resource*)draw->index_buffer;
266 rdraw.indices = rbuffer->bo;
267 rdraw.indices_bo_offset = draw->index_buffer_offset;
268 }
269 r600_context_draw(&rctx->ctx, &rdraw);
270 }
271
272 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
273 {
274 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
275 struct r600_drawl draw;
276 boolean translate = FALSE;
277
278 #if 0
279 if (rctx->vertex_elements->incompatible_layout) {
280 r600_begin_vertex_translate(rctx);
281 translate = TRUE;
282 }
283
284 if (rctx->any_user_vbs) {
285 r600_upload_user_buffers(rctx);
286 rctx->any_user_vbs = FALSE;
287 }
288 #endif
289
290 memset(&draw, 0, sizeof(struct r600_drawl));
291 draw.ctx = ctx;
292 draw.mode = info->mode;
293 draw.start = info->start;
294 draw.count = info->count;
295 if (info->indexed && rctx->index_buffer.buffer) {
296 draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
297 draw.min_index = info->min_index;
298 draw.max_index = info->max_index;
299 draw.index_bias = info->index_bias;
300
301 r600_translate_index_buffer(rctx, &rctx->index_buffer.buffer,
302 &rctx->index_buffer.index_size,
303 &draw.start,
304 info->count);
305
306 draw.index_size = rctx->index_buffer.index_size;
307 pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
308 draw.index_buffer_offset = draw.start * draw.index_size;
309 draw.start = 0;
310 r600_upload_index_buffer(rctx, &draw);
311 } else {
312 draw.index_size = 0;
313 draw.index_buffer = NULL;
314 draw.min_index = info->min_index;
315 draw.max_index = info->max_index;
316 draw.index_bias = info->start;
317 }
318 r600_draw_common(&draw);
319
320 if (translate)
321 r600_end_vertex_translate(rctx);
322
323 pipe_resource_reference(&draw.index_buffer, NULL);
324 }
325
326 static void r600_set_blend_color(struct pipe_context *ctx,
327 const struct pipe_blend_color *state)
328 {
329 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
330 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
331
332 if (rstate == NULL)
333 return;
334
335 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
336 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
337 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
338 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
339 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
340 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
341 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
342 r600_context_pipe_state_set(&rctx->ctx, rstate);
343 }
344
345 static void *r600_create_blend_state(struct pipe_context *ctx,
346 const struct pipe_blend_state *state)
347 {
348 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
349 struct r600_pipe_state *rstate;
350 u32 color_control, target_mask;
351
352 if (blend == NULL) {
353 return NULL;
354 }
355 rstate = &blend->rstate;
356
357 rstate->id = R600_PIPE_STATE_BLEND;
358
359 target_mask = 0;
360 color_control = S_028808_PER_MRT_BLEND(1);
361 if (state->logicop_enable) {
362 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
363 } else {
364 color_control |= (0xcc << 16);
365 }
366 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
367 if (state->independent_blend_enable) {
368 for (int i = 0; i < 8; i++) {
369 if (state->rt[i].blend_enable) {
370 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
371 }
372 target_mask |= (state->rt[i].colormask << (4 * i));
373 }
374 } else {
375 for (int i = 0; i < 8; i++) {
376 if (state->rt[0].blend_enable) {
377 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
378 }
379 target_mask |= (state->rt[0].colormask << (4 * i));
380 }
381 }
382 blend->cb_target_mask = target_mask;
383 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
384 color_control, 0xFFFFFFFF, NULL);
385
386 for (int i = 0; i < 8; i++) {
387 unsigned eqRGB = state->rt[i].rgb_func;
388 unsigned srcRGB = state->rt[i].rgb_src_factor;
389 unsigned dstRGB = state->rt[i].rgb_dst_factor;
390
391 unsigned eqA = state->rt[i].alpha_func;
392 unsigned srcA = state->rt[i].alpha_src_factor;
393 unsigned dstA = state->rt[i].alpha_dst_factor;
394 uint32_t bc = 0;
395
396 if (!state->rt[i].blend_enable)
397 continue;
398
399 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
400 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
401 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
402
403 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
404 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
405 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
406 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
407 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
408 }
409
410 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
411 if (i == 0) {
412 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
413 }
414 }
415 return rstate;
416 }
417
418 static void *r600_create_dsa_state(struct pipe_context *ctx,
419 const struct pipe_depth_stencil_alpha_state *state)
420 {
421 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
422 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
423 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
424
425 if (rstate == NULL) {
426 return NULL;
427 }
428
429 rstate->id = R600_PIPE_STATE_DSA;
430 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
431 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
432 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
433 * be set if shader use texkill instruction
434 */
435 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
436 stencil_ref_mask = 0;
437 stencil_ref_mask_bf = 0;
438 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
439 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
440 S_028800_ZFUNC(state->depth.func);
441
442 /* stencil */
443 if (state->stencil[0].enabled) {
444 db_depth_control |= S_028800_STENCIL_ENABLE(1);
445 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
446 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
447 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
448 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
449
450
451 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
452 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
453 if (state->stencil[1].enabled) {
454 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
455 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
456 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
457 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
458 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
459 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
460 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
461 }
462 }
463
464 /* alpha */
465 alpha_test_control = 0;
466 alpha_ref = 0;
467 if (state->alpha.enabled) {
468 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
469 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
470 alpha_ref = fui(state->alpha.ref_value);
471 }
472
473 /* misc */
474 db_render_control = 0;
475 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
476 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
477 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
478 /* TODO db_render_override depends on query */
479 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
480 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
481 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
482 r600_pipe_state_add_reg(rstate,
483 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
484 0xFFFFFFFF & C_028430_STENCILREF, NULL);
485 r600_pipe_state_add_reg(rstate,
486 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
487 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
488 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
489 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
490 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
491 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
492 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
493 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
494 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
495 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
496 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
497 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
498 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
499
500 return rstate;
501 }
502
503 static void *r600_create_rs_state(struct pipe_context *ctx,
504 const struct pipe_rasterizer_state *state)
505 {
506 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
507 struct r600_pipe_state *rstate;
508 unsigned tmp;
509 unsigned prov_vtx = 1, polygon_dual_mode;
510 unsigned clip_rule;
511
512 if (rs == NULL) {
513 return NULL;
514 }
515
516 rstate = &rs->rstate;
517 rs->flatshade = state->flatshade;
518 rs->sprite_coord_enable = state->sprite_coord_enable;
519
520 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
521 /* offset */
522 rs->offset_units = state->offset_units;
523 rs->offset_scale = state->offset_scale * 12.0f;
524
525 rstate->id = R600_PIPE_STATE_RASTERIZER;
526 if (state->flatshade_first)
527 prov_vtx = 0;
528 tmp = S_0286D4_FLAT_SHADE_ENA(1);
529 if (state->sprite_coord_enable) {
530 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
531 S_0286D4_PNT_SPRITE_OVRD_X(2) |
532 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
533 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
534 S_0286D4_PNT_SPRITE_OVRD_W(1);
535 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
536 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
537 }
538 }
539 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
540
541 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
542 state->fill_back != PIPE_POLYGON_MODE_FILL);
543 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
544 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
545 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
546 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
547 S_028814_FACE(!state->front_ccw) |
548 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
549 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
550 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
551 S_028814_POLY_MODE(polygon_dual_mode) |
552 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
553 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
554 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
555 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
556 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
557 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
558 /* point size 12.4 fixed point */
559 tmp = (unsigned)(state->point_size * 8.0);
560 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
561 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
562
563 tmp = (unsigned)state->line_width * 8;
564 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
565
566 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
567 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
568 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
569
570 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
571 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
572 0xFFFFFFFF, NULL);
573
574 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
575 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
576 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
577 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
578 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
579 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
580
581 return rstate;
582 }
583
584 static void *r600_create_sampler_state(struct pipe_context *ctx,
585 const struct pipe_sampler_state *state)
586 {
587 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
588 union util_color uc;
589
590 if (rstate == NULL) {
591 return NULL;
592 }
593
594 rstate->id = R600_PIPE_STATE_SAMPLER;
595 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
596 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
597 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
598 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
599 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
600 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
601 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
602 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
603 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
604 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
605 /* FIXME LOD it depends on texture base level ... */
606 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
607 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
608 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
609 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
610 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
611 if (uc.ui) {
612 r600_pipe_state_add_reg(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
613 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
614 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
615 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
616 }
617 return rstate;
618 }
619
620 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
621 struct pipe_resource *texture,
622 const struct pipe_sampler_view *state)
623 {
624 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
625 struct r600_pipe_state *rstate;
626 const struct util_format_description *desc;
627 struct r600_resource_texture *tmp;
628 struct r600_resource *rbuffer;
629 unsigned format;
630 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
631 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
632 struct r600_bo *bo[2];
633
634 if (resource == NULL)
635 return NULL;
636 rstate = &resource->state;
637
638 /* initialize base object */
639 resource->base = *state;
640 resource->base.texture = NULL;
641 pipe_reference(NULL, &texture->reference);
642 resource->base.texture = texture;
643 resource->base.reference.count = 1;
644 resource->base.context = ctx;
645
646 swizzle[0] = state->swizzle_r;
647 swizzle[1] = state->swizzle_g;
648 swizzle[2] = state->swizzle_b;
649 swizzle[3] = state->swizzle_a;
650 format = r600_translate_texformat(state->format,
651 swizzle,
652 &word4, &yuv_format);
653 if (format == ~0) {
654 format = 0;
655 }
656 desc = util_format_description(state->format);
657 if (desc == NULL) {
658 R600_ERR("unknow format %d\n", state->format);
659 }
660 tmp = (struct r600_resource_texture*)texture;
661 rbuffer = &tmp->resource;
662 bo[0] = rbuffer->bo;
663 bo[1] = rbuffer->bo;
664 /* FIXME depth texture decompression */
665 if (tmp->depth) {
666 r600_texture_depth_flush(ctx, texture);
667 tmp = (struct r600_resource_texture*)texture;
668 rbuffer = &tmp->flushed_depth_texture->resource;
669 bo[0] = rbuffer->bo;
670 bo[1] = rbuffer->bo;
671 }
672 pitch = align(tmp->pitch_in_pixels[0], 8);
673 if (tmp->tiled) {
674 array_mode = tmp->array_mode[0];
675 tile_type = tmp->tile_type;
676 }
677
678 /* FIXME properly handle first level != 0 */
679 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
680 S_038000_DIM(r600_tex_dim(texture->target)) |
681 S_038000_TILE_MODE(array_mode) |
682 S_038000_TILE_TYPE(tile_type) |
683 S_038000_PITCH((pitch / 8) - 1) |
684 S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
685 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
686 S_038004_TEX_HEIGHT(texture->height0 - 1) |
687 S_038004_TEX_DEPTH(texture->depth0 - 1) |
688 S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
689 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
690 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
691 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
692 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
693 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
694 word4 | S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
695 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
696 S_038010_REQUEST_SIZE(1) |
697 S_038010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
698 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
699 S_038014_LAST_LEVEL(state->u.tex.last_level) |
700 S_038014_BASE_ARRAY(0) |
701 S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL);
702 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
703 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
704
705 return &resource->base;
706 }
707
708 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
709 struct pipe_sampler_view **views)
710 {
711 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
712 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
713
714 for (int i = 0; i < count; i++) {
715 if (resource[i]) {
716 r600_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, i);
717 }
718 }
719 }
720
721 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
722 struct pipe_sampler_view **views)
723 {
724 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
725 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
726 int i;
727
728 for (i = 0; i < count; i++) {
729 if (&rctx->ps_samplers.views[i]->base != views[i]) {
730 if (resource[i])
731 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
732 else
733 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
734
735 pipe_sampler_view_reference(
736 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
737 views[i]);
738
739 }
740 }
741 for (i = count; i < NUM_TEX_UNITS; i++) {
742 if (rctx->ps_samplers.views[i]) {
743 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
744 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
745 }
746 }
747 rctx->ps_samplers.n_views = count;
748 }
749
750 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
751 {
752 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
753 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
754
755 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
756 rctx->ps_samplers.n_samplers = count;
757
758 for (int i = 0; i < count; i++) {
759 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
760 }
761 }
762
763 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
764 {
765 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
766 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
767
768 for (int i = 0; i < count; i++) {
769 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
770 }
771 }
772
773 static void r600_set_clip_state(struct pipe_context *ctx,
774 const struct pipe_clip_state *state)
775 {
776 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
777 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
778
779 if (rstate == NULL)
780 return;
781
782 rctx->clip = *state;
783 rstate->id = R600_PIPE_STATE_CLIP;
784 for (int i = 0; i < state->nr; i++) {
785 r600_pipe_state_add_reg(rstate,
786 R_028E20_PA_CL_UCP0_X + i * 16,
787 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
788 r600_pipe_state_add_reg(rstate,
789 R_028E24_PA_CL_UCP0_Y + i * 16,
790 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
791 r600_pipe_state_add_reg(rstate,
792 R_028E28_PA_CL_UCP0_Z + i * 16,
793 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
794 r600_pipe_state_add_reg(rstate,
795 R_028E2C_PA_CL_UCP0_W + i * 16,
796 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
797 }
798 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
799 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
800 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
801 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
802
803 free(rctx->states[R600_PIPE_STATE_CLIP]);
804 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
805 r600_context_pipe_state_set(&rctx->ctx, rstate);
806 }
807
808 static void r600_set_polygon_stipple(struct pipe_context *ctx,
809 const struct pipe_poly_stipple *state)
810 {
811 }
812
813 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
814 {
815 }
816
817 static void r600_set_scissor_state(struct pipe_context *ctx,
818 const struct pipe_scissor_state *state)
819 {
820 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
821 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
822 u32 tl, br;
823
824 if (rstate == NULL)
825 return;
826
827 rstate->id = R600_PIPE_STATE_SCISSOR;
828 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
829 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
830 r600_pipe_state_add_reg(rstate,
831 R_028210_PA_SC_CLIPRECT_0_TL, tl,
832 0xFFFFFFFF, NULL);
833 r600_pipe_state_add_reg(rstate,
834 R_028214_PA_SC_CLIPRECT_0_BR, br,
835 0xFFFFFFFF, NULL);
836 r600_pipe_state_add_reg(rstate,
837 R_028218_PA_SC_CLIPRECT_1_TL, tl,
838 0xFFFFFFFF, NULL);
839 r600_pipe_state_add_reg(rstate,
840 R_02821C_PA_SC_CLIPRECT_1_BR, br,
841 0xFFFFFFFF, NULL);
842 r600_pipe_state_add_reg(rstate,
843 R_028220_PA_SC_CLIPRECT_2_TL, tl,
844 0xFFFFFFFF, NULL);
845 r600_pipe_state_add_reg(rstate,
846 R_028224_PA_SC_CLIPRECT_2_BR, br,
847 0xFFFFFFFF, NULL);
848 r600_pipe_state_add_reg(rstate,
849 R_028228_PA_SC_CLIPRECT_3_TL, tl,
850 0xFFFFFFFF, NULL);
851 r600_pipe_state_add_reg(rstate,
852 R_02822C_PA_SC_CLIPRECT_3_BR, br,
853 0xFFFFFFFF, NULL);
854
855 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
856 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
857 r600_context_pipe_state_set(&rctx->ctx, rstate);
858 }
859
860 static void r600_set_stencil_ref(struct pipe_context *ctx,
861 const struct pipe_stencil_ref *state)
862 {
863 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
864 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
865 u32 tmp;
866
867 if (rstate == NULL)
868 return;
869
870 rctx->stencil_ref = *state;
871 rstate->id = R600_PIPE_STATE_STENCIL_REF;
872 tmp = S_028430_STENCILREF(state->ref_value[0]);
873 r600_pipe_state_add_reg(rstate,
874 R_028430_DB_STENCILREFMASK, tmp,
875 ~C_028430_STENCILREF, NULL);
876 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
877 r600_pipe_state_add_reg(rstate,
878 R_028434_DB_STENCILREFMASK_BF, tmp,
879 ~C_028434_STENCILREF_BF, NULL);
880
881 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
882 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
883 r600_context_pipe_state_set(&rctx->ctx, rstate);
884 }
885
886 static void r600_set_viewport_state(struct pipe_context *ctx,
887 const struct pipe_viewport_state *state)
888 {
889 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
890 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
891
892 if (rstate == NULL)
893 return;
894
895 rctx->viewport = *state;
896 rstate->id = R600_PIPE_STATE_VIEWPORT;
897 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
898 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
899 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
900 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
901 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
902 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
903 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
904 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
905 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
906
907 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
908 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
909 r600_context_pipe_state_set(&rctx->ctx, rstate);
910 }
911
912 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
913 const struct pipe_framebuffer_state *state, int cb)
914 {
915 struct r600_resource_texture *rtex;
916 struct r600_resource *rbuffer;
917 struct r600_surface *surf;
918 unsigned level = state->cbufs[cb]->u.tex.level;
919 unsigned pitch, slice;
920 unsigned color_info;
921 unsigned format, swap, ntype;
922 unsigned offset;
923 const struct util_format_description *desc;
924 struct r600_bo *bo[3];
925
926 surf = (struct r600_surface *)state->cbufs[cb];
927 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
928 rbuffer = &rtex->resource;
929 bo[0] = rbuffer->bo;
930 bo[1] = rbuffer->bo;
931 bo[2] = rbuffer->bo;
932
933 /* XXX quite sure for dx10+ hw don't need any offset hacks */
934 offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture,
935 level, state->cbufs[cb]->u.tex.first_layer);
936 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
937 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
938 ntype = 0;
939 desc = util_format_description(rtex->resource.base.b.format);
940 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
941 ntype = V_0280A0_NUMBER_SRGB;
942
943 format = r600_translate_colorformat(rtex->resource.base.b.format);
944 swap = r600_translate_colorswap(rtex->resource.base.b.format);
945 color_info = S_0280A0_FORMAT(format) |
946 S_0280A0_COMP_SWAP(swap) |
947 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
948 S_0280A0_BLEND_CLAMP(1) |
949 S_0280A0_NUMBER_TYPE(ntype);
950 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
951 color_info |= S_0280A0_SOURCE_FORMAT(1);
952
953 r600_pipe_state_add_reg(rstate,
954 R_028040_CB_COLOR0_BASE + cb * 4,
955 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
956 r600_pipe_state_add_reg(rstate,
957 R_0280A0_CB_COLOR0_INFO + cb * 4,
958 color_info, 0xFFFFFFFF, bo[0]);
959 r600_pipe_state_add_reg(rstate,
960 R_028060_CB_COLOR0_SIZE + cb * 4,
961 S_028060_PITCH_TILE_MAX(pitch) |
962 S_028060_SLICE_TILE_MAX(slice),
963 0xFFFFFFFF, NULL);
964 r600_pipe_state_add_reg(rstate,
965 R_028080_CB_COLOR0_VIEW + cb * 4,
966 0x00000000, 0xFFFFFFFF, NULL);
967 r600_pipe_state_add_reg(rstate,
968 R_0280E0_CB_COLOR0_FRAG + cb * 4,
969 r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]);
970 r600_pipe_state_add_reg(rstate,
971 R_0280C0_CB_COLOR0_TILE + cb * 4,
972 r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]);
973 r600_pipe_state_add_reg(rstate,
974 R_028100_CB_COLOR0_MASK + cb * 4,
975 0x00000000, 0xFFFFFFFF, NULL);
976 }
977
978 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
979 const struct pipe_framebuffer_state *state)
980 {
981 struct r600_resource_texture *rtex;
982 struct r600_resource *rbuffer;
983 struct r600_surface *surf;
984 unsigned level;
985 unsigned pitch, slice, format;
986 unsigned offset;
987
988 if (state->zsbuf == NULL)
989 return;
990
991 level = state->zsbuf->u.tex.level;
992
993 surf = (struct r600_surface *)state->zsbuf;
994 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
995 rtex->tiled = 1;
996 rtex->array_mode[level] = 2;
997 rtex->tile_type = 1;
998 rtex->depth = 1;
999 rbuffer = &rtex->resource;
1000
1001 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1002 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
1003 level, state->zsbuf->u.tex.first_layer);
1004 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
1005 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
1006 format = r600_translate_dbformat(state->zsbuf->texture->format);
1007
1008 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
1009 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
1010 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1011 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1012 0xFFFFFFFF, NULL);
1013 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
1014 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
1015 S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format),
1016 0xFFFFFFFF, rbuffer->bo);
1017 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1018 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL);
1019 }
1020
1021 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1022 const struct pipe_framebuffer_state *state)
1023 {
1024 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1025 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1026 u32 shader_mask, tl, br, shader_control, target_mask;
1027
1028 if (rstate == NULL)
1029 return;
1030
1031 /* unreference old buffer and reference new one */
1032 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1033
1034 util_copy_framebuffer_state(&rctx->framebuffer, state);
1035
1036 rctx->pframebuffer = &rctx->framebuffer;
1037
1038 /* build states */
1039 for (int i = 0; i < state->nr_cbufs; i++) {
1040 r600_cb(rctx, rstate, state, i);
1041 }
1042 if (state->zsbuf) {
1043 r600_db(rctx, rstate, state);
1044 }
1045
1046 target_mask = 0x00000000;
1047 target_mask = 0xFFFFFFFF;
1048 shader_mask = 0;
1049 shader_control = 0;
1050 for (int i = 0; i < state->nr_cbufs; i++) {
1051 target_mask ^= 0xf << (i * 4);
1052 shader_mask |= 0xf << (i * 4);
1053 shader_control |= 1 << i;
1054 }
1055 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1056 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1057
1058 r600_pipe_state_add_reg(rstate,
1059 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1060 0xFFFFFFFF, NULL);
1061 r600_pipe_state_add_reg(rstate,
1062 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1063 0xFFFFFFFF, NULL);
1064 r600_pipe_state_add_reg(rstate,
1065 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1066 0xFFFFFFFF, NULL);
1067 r600_pipe_state_add_reg(rstate,
1068 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1069 0xFFFFFFFF, NULL);
1070 r600_pipe_state_add_reg(rstate,
1071 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1072 0xFFFFFFFF, NULL);
1073 r600_pipe_state_add_reg(rstate,
1074 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1075 0xFFFFFFFF, NULL);
1076 r600_pipe_state_add_reg(rstate,
1077 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1078 0xFFFFFFFF, NULL);
1079 r600_pipe_state_add_reg(rstate,
1080 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1081 0xFFFFFFFF, NULL);
1082 r600_pipe_state_add_reg(rstate,
1083 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1084 0xFFFFFFFF, NULL);
1085 if (rctx->family >= CHIP_RV770) {
1086 r600_pipe_state_add_reg(rstate,
1087 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1088 0xFFFFFFFF, NULL);
1089 }
1090
1091 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1092 shader_control, 0xFFFFFFFF, NULL);
1093 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1094 0x00000000, target_mask, NULL);
1095 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1096 shader_mask, 0xFFFFFFFF, NULL);
1097 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1098 0x00000000, 0xFFFFFFFF, NULL);
1099 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1100 0x00000000, 0xFFFFFFFF, NULL);
1101 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1102 0x00000000, 0xFFFFFFFF, NULL);
1103 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1104 0x01000000, 0xFFFFFFFF, NULL);
1105 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1106 0x00000000, 0xFFFFFFFF, NULL);
1107 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1108 0x000000FF, 0xFFFFFFFF, NULL);
1109 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1110 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1111 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1112 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1113
1114 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1115 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1116 r600_context_pipe_state_set(&rctx->ctx, rstate);
1117
1118 if (state->zsbuf) {
1119 r600_polygon_offset_update(rctx);
1120 }
1121 }
1122
1123 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
1124 struct pipe_resource *buffer)
1125 {
1126 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1127 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
1128
1129 /* Note that the state tracker can unbind constant buffers by
1130 * passing NULL here.
1131 */
1132 if (buffer == NULL) {
1133 return;
1134 }
1135
1136 switch (shader) {
1137 case PIPE_SHADER_VERTEX:
1138 rctx->vs_const_buffer.nregs = 0;
1139 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1140 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1141 ALIGN_DIVUP(buffer->width0 >> 4, 16),
1142 0xFFFFFFFF, NULL);
1143 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1144 R_028980_ALU_CONST_CACHE_VS_0,
1145 r600_bo_offset(rbuffer->bo) >> 8, 0xFFFFFFFF, rbuffer->bo);
1146 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
1147 break;
1148 case PIPE_SHADER_FRAGMENT:
1149 rctx->ps_const_buffer.nregs = 0;
1150 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1151 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1152 ALIGN_DIVUP(buffer->width0 >> 4, 16),
1153 0xFFFFFFFF, NULL);
1154 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1155 R_028940_ALU_CONST_CACHE_PS_0,
1156 r600_bo_offset(rbuffer->bo) >> 8, 0xFFFFFFFF, rbuffer->bo);
1157 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
1158 break;
1159 default:
1160 R600_ERR("unsupported %d\n", shader);
1161 return;
1162 }
1163 }
1164
1165 void r600_init_state_functions(struct r600_pipe_context *rctx)
1166 {
1167 rctx->context.create_blend_state = r600_create_blend_state;
1168 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1169 rctx->context.create_fs_state = r600_create_shader_state;
1170 rctx->context.create_rasterizer_state = r600_create_rs_state;
1171 rctx->context.create_sampler_state = r600_create_sampler_state;
1172 rctx->context.create_sampler_view = r600_create_sampler_view;
1173 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1174 rctx->context.create_vs_state = r600_create_shader_state;
1175 rctx->context.bind_blend_state = r600_bind_blend_state;
1176 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
1177 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
1178 rctx->context.bind_fs_state = r600_bind_ps_shader;
1179 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1180 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1181 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
1182 rctx->context.bind_vs_state = r600_bind_vs_shader;
1183 rctx->context.delete_blend_state = r600_delete_state;
1184 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1185 rctx->context.delete_fs_state = r600_delete_ps_shader;
1186 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1187 rctx->context.delete_sampler_state = r600_delete_state;
1188 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1189 rctx->context.delete_vs_state = r600_delete_vs_shader;
1190 rctx->context.set_blend_color = r600_set_blend_color;
1191 rctx->context.set_clip_state = r600_set_clip_state;
1192 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1193 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
1194 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1195 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1196 rctx->context.set_sample_mask = r600_set_sample_mask;
1197 rctx->context.set_scissor_state = r600_set_scissor_state;
1198 rctx->context.set_stencil_ref = r600_set_stencil_ref;
1199 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1200 rctx->context.set_index_buffer = r600_set_index_buffer;
1201 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
1202 rctx->context.set_viewport_state = r600_set_viewport_state;
1203 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1204 }
1205
1206 void r600_init_config(struct r600_pipe_context *rctx)
1207 {
1208 int ps_prio;
1209 int vs_prio;
1210 int gs_prio;
1211 int es_prio;
1212 int num_ps_gprs;
1213 int num_vs_gprs;
1214 int num_gs_gprs;
1215 int num_es_gprs;
1216 int num_temp_gprs;
1217 int num_ps_threads;
1218 int num_vs_threads;
1219 int num_gs_threads;
1220 int num_es_threads;
1221 int num_ps_stack_entries;
1222 int num_vs_stack_entries;
1223 int num_gs_stack_entries;
1224 int num_es_stack_entries;
1225 enum radeon_family family;
1226 struct r600_pipe_state *rstate = &rctx->config;
1227 u32 tmp;
1228
1229 family = r600_get_family(rctx->radeon);
1230 ps_prio = 0;
1231 vs_prio = 1;
1232 gs_prio = 2;
1233 es_prio = 3;
1234 switch (family) {
1235 case CHIP_R600:
1236 num_ps_gprs = 192;
1237 num_vs_gprs = 56;
1238 num_temp_gprs = 4;
1239 num_gs_gprs = 0;
1240 num_es_gprs = 0;
1241 num_ps_threads = 136;
1242 num_vs_threads = 48;
1243 num_gs_threads = 4;
1244 num_es_threads = 4;
1245 num_ps_stack_entries = 128;
1246 num_vs_stack_entries = 128;
1247 num_gs_stack_entries = 0;
1248 num_es_stack_entries = 0;
1249 break;
1250 case CHIP_RV630:
1251 case CHIP_RV635:
1252 num_ps_gprs = 84;
1253 num_vs_gprs = 36;
1254 num_temp_gprs = 4;
1255 num_gs_gprs = 0;
1256 num_es_gprs = 0;
1257 num_ps_threads = 144;
1258 num_vs_threads = 40;
1259 num_gs_threads = 4;
1260 num_es_threads = 4;
1261 num_ps_stack_entries = 40;
1262 num_vs_stack_entries = 40;
1263 num_gs_stack_entries = 32;
1264 num_es_stack_entries = 16;
1265 break;
1266 case CHIP_RV610:
1267 case CHIP_RV620:
1268 case CHIP_RS780:
1269 case CHIP_RS880:
1270 default:
1271 num_ps_gprs = 84;
1272 num_vs_gprs = 36;
1273 num_temp_gprs = 4;
1274 num_gs_gprs = 0;
1275 num_es_gprs = 0;
1276 num_ps_threads = 136;
1277 num_vs_threads = 48;
1278 num_gs_threads = 4;
1279 num_es_threads = 4;
1280 num_ps_stack_entries = 40;
1281 num_vs_stack_entries = 40;
1282 num_gs_stack_entries = 32;
1283 num_es_stack_entries = 16;
1284 break;
1285 case CHIP_RV670:
1286 num_ps_gprs = 144;
1287 num_vs_gprs = 40;
1288 num_temp_gprs = 4;
1289 num_gs_gprs = 0;
1290 num_es_gprs = 0;
1291 num_ps_threads = 136;
1292 num_vs_threads = 48;
1293 num_gs_threads = 4;
1294 num_es_threads = 4;
1295 num_ps_stack_entries = 40;
1296 num_vs_stack_entries = 40;
1297 num_gs_stack_entries = 32;
1298 num_es_stack_entries = 16;
1299 break;
1300 case CHIP_RV770:
1301 num_ps_gprs = 192;
1302 num_vs_gprs = 56;
1303 num_temp_gprs = 4;
1304 num_gs_gprs = 0;
1305 num_es_gprs = 0;
1306 num_ps_threads = 188;
1307 num_vs_threads = 60;
1308 num_gs_threads = 0;
1309 num_es_threads = 0;
1310 num_ps_stack_entries = 256;
1311 num_vs_stack_entries = 256;
1312 num_gs_stack_entries = 0;
1313 num_es_stack_entries = 0;
1314 break;
1315 case CHIP_RV730:
1316 case CHIP_RV740:
1317 num_ps_gprs = 84;
1318 num_vs_gprs = 36;
1319 num_temp_gprs = 4;
1320 num_gs_gprs = 0;
1321 num_es_gprs = 0;
1322 num_ps_threads = 188;
1323 num_vs_threads = 60;
1324 num_gs_threads = 0;
1325 num_es_threads = 0;
1326 num_ps_stack_entries = 128;
1327 num_vs_stack_entries = 128;
1328 num_gs_stack_entries = 0;
1329 num_es_stack_entries = 0;
1330 break;
1331 case CHIP_RV710:
1332 num_ps_gprs = 192;
1333 num_vs_gprs = 56;
1334 num_temp_gprs = 4;
1335 num_gs_gprs = 0;
1336 num_es_gprs = 0;
1337 num_ps_threads = 144;
1338 num_vs_threads = 48;
1339 num_gs_threads = 0;
1340 num_es_threads = 0;
1341 num_ps_stack_entries = 128;
1342 num_vs_stack_entries = 128;
1343 num_gs_stack_entries = 0;
1344 num_es_stack_entries = 0;
1345 break;
1346 }
1347
1348 rstate->id = R600_PIPE_STATE_CONFIG;
1349
1350 /* SQ_CONFIG */
1351 tmp = 0;
1352 switch (family) {
1353 case CHIP_RV610:
1354 case CHIP_RV620:
1355 case CHIP_RS780:
1356 case CHIP_RS880:
1357 case CHIP_RV710:
1358 break;
1359 default:
1360 tmp |= S_008C00_VC_ENABLE(1);
1361 break;
1362 }
1363 tmp |= S_008C00_DX9_CONSTS(0);
1364 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1365 tmp |= S_008C00_PS_PRIO(ps_prio);
1366 tmp |= S_008C00_VS_PRIO(vs_prio);
1367 tmp |= S_008C00_GS_PRIO(gs_prio);
1368 tmp |= S_008C00_ES_PRIO(es_prio);
1369 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1370
1371 /* SQ_GPR_RESOURCE_MGMT_1 */
1372 tmp = 0;
1373 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1374 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1375 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1376 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1377
1378 /* SQ_GPR_RESOURCE_MGMT_2 */
1379 tmp = 0;
1380 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1381 tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
1382 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1383
1384 /* SQ_THREAD_RESOURCE_MGMT */
1385 tmp = 0;
1386 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1387 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1388 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1389 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1390 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1391
1392 /* SQ_STACK_RESOURCE_MGMT_1 */
1393 tmp = 0;
1394 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1395 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1396 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1397
1398 /* SQ_STACK_RESOURCE_MGMT_2 */
1399 tmp = 0;
1400 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1401 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1402 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1403
1404 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1405 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1406
1407 if (family >= CHIP_RV770) {
1408 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1409 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
1410 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1411 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1412 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1413 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL);
1414 } else {
1415 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1416 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
1417 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1418 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1419 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1420 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL);
1421 }
1422 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1423 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1424 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1425 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1426 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1427 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1428 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1429 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1430 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1431 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1432 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1433 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1434 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1435 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
1436 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
1437 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1438 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1439 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1440 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1441 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1442 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1443 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
1444 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1445 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1446 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1447 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
1448
1449 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1450 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
1451 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
1452 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
1453 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
1454 r600_context_pipe_state_set(&rctx->ctx, rstate);
1455 }
1456
1457 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
1458 {
1459 struct pipe_depth_stencil_alpha_state dsa;
1460 struct r600_pipe_state *rstate;
1461 boolean quirk = false;
1462
1463 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
1464 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
1465 quirk = true;
1466
1467 memset(&dsa, 0, sizeof(dsa));
1468
1469 if (quirk) {
1470 dsa.depth.enabled = 1;
1471 dsa.depth.func = PIPE_FUNC_LEQUAL;
1472 dsa.stencil[0].enabled = 1;
1473 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
1474 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
1475 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
1476 dsa.stencil[0].writemask = 0xff;
1477 }
1478
1479 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1480 r600_pipe_state_add_reg(rstate,
1481 R_02880C_DB_SHADER_CONTROL,
1482 0x0,
1483 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1484 r600_pipe_state_add_reg(rstate,
1485 R_028D0C_DB_RENDER_CONTROL,
1486 S_028D0C_DEPTH_COPY_ENABLE(1) |
1487 S_028D0C_STENCIL_COPY_ENABLE(1) |
1488 S_028D0C_COPY_CENTROID(1),
1489 S_028D0C_DEPTH_COPY_ENABLE(1) |
1490 S_028D0C_STENCIL_COPY_ENABLE(1) |
1491 S_028D0C_COPY_CENTROID(1), NULL);
1492 return rstate;
1493 }