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r600g: implement blit
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600d.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31
32 static uint32_t r600_translate_blend_function(int blend_func)
33 {
34 switch (blend_func) {
35 case PIPE_BLEND_ADD:
36 return V_028804_COMB_DST_PLUS_SRC;
37 case PIPE_BLEND_SUBTRACT:
38 return V_028804_COMB_SRC_MINUS_DST;
39 case PIPE_BLEND_REVERSE_SUBTRACT:
40 return V_028804_COMB_DST_MINUS_SRC;
41 case PIPE_BLEND_MIN:
42 return V_028804_COMB_MIN_DST_SRC;
43 case PIPE_BLEND_MAX:
44 return V_028804_COMB_MAX_DST_SRC;
45 default:
46 R600_ERR("Unknown blend function %d\n", blend_func);
47 assert(0);
48 break;
49 }
50 return 0;
51 }
52
53 static uint32_t r600_translate_blend_factor(int blend_fact)
54 {
55 switch (blend_fact) {
56 case PIPE_BLENDFACTOR_ONE:
57 return V_028804_BLEND_ONE;
58 case PIPE_BLENDFACTOR_SRC_COLOR:
59 return V_028804_BLEND_SRC_COLOR;
60 case PIPE_BLENDFACTOR_SRC_ALPHA:
61 return V_028804_BLEND_SRC_ALPHA;
62 case PIPE_BLENDFACTOR_DST_ALPHA:
63 return V_028804_BLEND_DST_ALPHA;
64 case PIPE_BLENDFACTOR_DST_COLOR:
65 return V_028804_BLEND_DST_COLOR;
66 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
67 return V_028804_BLEND_SRC_ALPHA_SATURATE;
68 case PIPE_BLENDFACTOR_CONST_COLOR:
69 return V_028804_BLEND_CONST_COLOR;
70 case PIPE_BLENDFACTOR_CONST_ALPHA:
71 return V_028804_BLEND_CONST_ALPHA;
72 case PIPE_BLENDFACTOR_ZERO:
73 return V_028804_BLEND_ZERO;
74 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
75 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
76 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
77 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
78 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
79 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
80 case PIPE_BLENDFACTOR_INV_DST_COLOR:
81 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
82 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
83 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
84 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
85 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
86 case PIPE_BLENDFACTOR_SRC1_COLOR:
87 return V_028804_BLEND_SRC1_COLOR;
88 case PIPE_BLENDFACTOR_SRC1_ALPHA:
89 return V_028804_BLEND_SRC1_ALPHA;
90 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
91 return V_028804_BLEND_INV_SRC1_COLOR;
92 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
93 return V_028804_BLEND_INV_SRC1_ALPHA;
94 default:
95 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
96 assert(0);
97 break;
98 }
99 return 0;
100 }
101
102 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
103 {
104 switch (dim) {
105 default:
106 case PIPE_TEXTURE_1D:
107 return V_038000_SQ_TEX_DIM_1D;
108 case PIPE_TEXTURE_1D_ARRAY:
109 return V_038000_SQ_TEX_DIM_1D_ARRAY;
110 case PIPE_TEXTURE_2D:
111 case PIPE_TEXTURE_RECT:
112 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
113 V_038000_SQ_TEX_DIM_2D;
114 case PIPE_TEXTURE_2D_ARRAY:
115 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
116 V_038000_SQ_TEX_DIM_2D_ARRAY;
117 case PIPE_TEXTURE_3D:
118 return V_038000_SQ_TEX_DIM_3D;
119 case PIPE_TEXTURE_CUBE:
120 return V_038000_SQ_TEX_DIM_CUBEMAP;
121 }
122 }
123
124 static uint32_t r600_translate_dbformat(enum pipe_format format)
125 {
126 switch (format) {
127 case PIPE_FORMAT_Z16_UNORM:
128 return V_028010_DEPTH_16;
129 case PIPE_FORMAT_Z24X8_UNORM:
130 return V_028010_DEPTH_X8_24;
131 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
132 return V_028010_DEPTH_8_24;
133 case PIPE_FORMAT_Z32_FLOAT:
134 return V_028010_DEPTH_32_FLOAT;
135 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
136 return V_028010_DEPTH_X24_8_32_FLOAT;
137 default:
138 return ~0U;
139 }
140 }
141
142 static uint32_t r600_translate_colorswap(enum pipe_format format)
143 {
144 switch (format) {
145 /* 8-bit buffers. */
146 case PIPE_FORMAT_A8_UNORM:
147 case PIPE_FORMAT_A8_SNORM:
148 case PIPE_FORMAT_A8_UINT:
149 case PIPE_FORMAT_A8_SINT:
150 case PIPE_FORMAT_A16_UNORM:
151 case PIPE_FORMAT_A16_SNORM:
152 case PIPE_FORMAT_A16_UINT:
153 case PIPE_FORMAT_A16_SINT:
154 case PIPE_FORMAT_A16_FLOAT:
155 case PIPE_FORMAT_A32_UINT:
156 case PIPE_FORMAT_A32_SINT:
157 case PIPE_FORMAT_A32_FLOAT:
158 case PIPE_FORMAT_R4A4_UNORM:
159 return V_0280A0_SWAP_ALT_REV;
160 case PIPE_FORMAT_I8_UNORM:
161 case PIPE_FORMAT_I8_SNORM:
162 case PIPE_FORMAT_I8_UINT:
163 case PIPE_FORMAT_I8_SINT:
164 case PIPE_FORMAT_L8_UNORM:
165 case PIPE_FORMAT_L8_SNORM:
166 case PIPE_FORMAT_L8_UINT:
167 case PIPE_FORMAT_L8_SINT:
168 case PIPE_FORMAT_L8_SRGB:
169 case PIPE_FORMAT_L16_UNORM:
170 case PIPE_FORMAT_L16_SNORM:
171 case PIPE_FORMAT_L16_UINT:
172 case PIPE_FORMAT_L16_SINT:
173 case PIPE_FORMAT_L16_FLOAT:
174 case PIPE_FORMAT_L32_UINT:
175 case PIPE_FORMAT_L32_SINT:
176 case PIPE_FORMAT_L32_FLOAT:
177 case PIPE_FORMAT_I16_UNORM:
178 case PIPE_FORMAT_I16_SNORM:
179 case PIPE_FORMAT_I16_UINT:
180 case PIPE_FORMAT_I16_SINT:
181 case PIPE_FORMAT_I16_FLOAT:
182 case PIPE_FORMAT_I32_UINT:
183 case PIPE_FORMAT_I32_SINT:
184 case PIPE_FORMAT_I32_FLOAT:
185 case PIPE_FORMAT_R8_UNORM:
186 case PIPE_FORMAT_R8_SNORM:
187 case PIPE_FORMAT_R8_UINT:
188 case PIPE_FORMAT_R8_SINT:
189 return V_0280A0_SWAP_STD;
190
191 case PIPE_FORMAT_L4A4_UNORM:
192 case PIPE_FORMAT_A4R4_UNORM:
193 return V_0280A0_SWAP_ALT;
194
195 /* 16-bit buffers. */
196 case PIPE_FORMAT_B5G6R5_UNORM:
197 return V_0280A0_SWAP_STD_REV;
198
199 case PIPE_FORMAT_B5G5R5A1_UNORM:
200 case PIPE_FORMAT_B5G5R5X1_UNORM:
201 return V_0280A0_SWAP_ALT;
202
203 case PIPE_FORMAT_B4G4R4A4_UNORM:
204 case PIPE_FORMAT_B4G4R4X4_UNORM:
205 return V_0280A0_SWAP_ALT;
206
207 case PIPE_FORMAT_Z16_UNORM:
208 return V_0280A0_SWAP_STD;
209
210 case PIPE_FORMAT_L8A8_UNORM:
211 case PIPE_FORMAT_L8A8_SNORM:
212 case PIPE_FORMAT_L8A8_UINT:
213 case PIPE_FORMAT_L8A8_SINT:
214 case PIPE_FORMAT_L8A8_SRGB:
215 case PIPE_FORMAT_L16A16_UNORM:
216 case PIPE_FORMAT_L16A16_SNORM:
217 case PIPE_FORMAT_L16A16_UINT:
218 case PIPE_FORMAT_L16A16_SINT:
219 case PIPE_FORMAT_L16A16_FLOAT:
220 case PIPE_FORMAT_L32A32_UINT:
221 case PIPE_FORMAT_L32A32_SINT:
222 case PIPE_FORMAT_L32A32_FLOAT:
223 return V_0280A0_SWAP_ALT;
224 case PIPE_FORMAT_R8G8_UNORM:
225 case PIPE_FORMAT_R8G8_SNORM:
226 case PIPE_FORMAT_R8G8_UINT:
227 case PIPE_FORMAT_R8G8_SINT:
228 return V_0280A0_SWAP_STD;
229
230 case PIPE_FORMAT_R16_UNORM:
231 case PIPE_FORMAT_R16_SNORM:
232 case PIPE_FORMAT_R16_UINT:
233 case PIPE_FORMAT_R16_SINT:
234 case PIPE_FORMAT_R16_FLOAT:
235 return V_0280A0_SWAP_STD;
236
237 /* 32-bit buffers. */
238
239 case PIPE_FORMAT_A8B8G8R8_SRGB:
240 return V_0280A0_SWAP_STD_REV;
241 case PIPE_FORMAT_B8G8R8A8_SRGB:
242 return V_0280A0_SWAP_ALT;
243
244 case PIPE_FORMAT_B8G8R8A8_UNORM:
245 case PIPE_FORMAT_B8G8R8X8_UNORM:
246 return V_0280A0_SWAP_ALT;
247
248 case PIPE_FORMAT_A8R8G8B8_UNORM:
249 case PIPE_FORMAT_X8R8G8B8_UNORM:
250 return V_0280A0_SWAP_ALT_REV;
251 case PIPE_FORMAT_R8G8B8A8_SNORM:
252 case PIPE_FORMAT_R8G8B8A8_UNORM:
253 case PIPE_FORMAT_R8G8B8X8_UNORM:
254 case PIPE_FORMAT_R8G8B8A8_SINT:
255 case PIPE_FORMAT_R8G8B8A8_UINT:
256 return V_0280A0_SWAP_STD;
257
258 case PIPE_FORMAT_A8B8G8R8_UNORM:
259 case PIPE_FORMAT_X8B8G8R8_UNORM:
260 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
261 return V_0280A0_SWAP_STD_REV;
262
263 case PIPE_FORMAT_Z24X8_UNORM:
264 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
265 return V_0280A0_SWAP_STD;
266
267 case PIPE_FORMAT_X8Z24_UNORM:
268 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
269 return V_0280A0_SWAP_STD;
270
271 case PIPE_FORMAT_R10G10B10A2_UNORM:
272 case PIPE_FORMAT_R10G10B10X2_SNORM:
273 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
274 return V_0280A0_SWAP_STD;
275
276 case PIPE_FORMAT_B10G10R10A2_UNORM:
277 case PIPE_FORMAT_B10G10R10A2_UINT:
278 return V_0280A0_SWAP_ALT;
279
280 case PIPE_FORMAT_R11G11B10_FLOAT:
281 case PIPE_FORMAT_R16G16_UNORM:
282 case PIPE_FORMAT_R16G16_SNORM:
283 case PIPE_FORMAT_R16G16_FLOAT:
284 case PIPE_FORMAT_R16G16_UINT:
285 case PIPE_FORMAT_R16G16_SINT:
286 case PIPE_FORMAT_R32_UINT:
287 case PIPE_FORMAT_R32_SINT:
288 case PIPE_FORMAT_R32_FLOAT:
289 case PIPE_FORMAT_Z32_FLOAT:
290 return V_0280A0_SWAP_STD;
291
292 /* 64-bit buffers. */
293 case PIPE_FORMAT_R32G32_FLOAT:
294 case PIPE_FORMAT_R32G32_UINT:
295 case PIPE_FORMAT_R32G32_SINT:
296 case PIPE_FORMAT_R16G16B16A16_UNORM:
297 case PIPE_FORMAT_R16G16B16A16_SNORM:
298 case PIPE_FORMAT_R16G16B16A16_UINT:
299 case PIPE_FORMAT_R16G16B16A16_SINT:
300 case PIPE_FORMAT_R16G16B16A16_FLOAT:
301 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
302
303 /* 128-bit buffers. */
304 case PIPE_FORMAT_R32G32B32A32_FLOAT:
305 case PIPE_FORMAT_R32G32B32A32_SNORM:
306 case PIPE_FORMAT_R32G32B32A32_UNORM:
307 case PIPE_FORMAT_R32G32B32A32_SINT:
308 case PIPE_FORMAT_R32G32B32A32_UINT:
309 return V_0280A0_SWAP_STD;
310 default:
311 R600_ERR("unsupported colorswap format %d\n", format);
312 return ~0U;
313 }
314 return ~0U;
315 }
316
317 static uint32_t r600_translate_colorformat(enum pipe_format format)
318 {
319 switch (format) {
320 case PIPE_FORMAT_L4A4_UNORM:
321 case PIPE_FORMAT_R4A4_UNORM:
322 case PIPE_FORMAT_A4R4_UNORM:
323 return V_0280A0_COLOR_4_4;
324
325 /* 8-bit buffers. */
326 case PIPE_FORMAT_A8_UNORM:
327 case PIPE_FORMAT_A8_SNORM:
328 case PIPE_FORMAT_A8_UINT:
329 case PIPE_FORMAT_A8_SINT:
330 case PIPE_FORMAT_I8_UNORM:
331 case PIPE_FORMAT_I8_SNORM:
332 case PIPE_FORMAT_I8_UINT:
333 case PIPE_FORMAT_I8_SINT:
334 case PIPE_FORMAT_L8_UNORM:
335 case PIPE_FORMAT_L8_SNORM:
336 case PIPE_FORMAT_L8_UINT:
337 case PIPE_FORMAT_L8_SINT:
338 case PIPE_FORMAT_L8_SRGB:
339 case PIPE_FORMAT_R8_UNORM:
340 case PIPE_FORMAT_R8_SNORM:
341 case PIPE_FORMAT_R8_UINT:
342 case PIPE_FORMAT_R8_SINT:
343 return V_0280A0_COLOR_8;
344
345 /* 16-bit buffers. */
346 case PIPE_FORMAT_B5G6R5_UNORM:
347 return V_0280A0_COLOR_5_6_5;
348
349 case PIPE_FORMAT_B5G5R5A1_UNORM:
350 case PIPE_FORMAT_B5G5R5X1_UNORM:
351 return V_0280A0_COLOR_1_5_5_5;
352
353 case PIPE_FORMAT_B4G4R4A4_UNORM:
354 case PIPE_FORMAT_B4G4R4X4_UNORM:
355 return V_0280A0_COLOR_4_4_4_4;
356
357 case PIPE_FORMAT_Z16_UNORM:
358 return V_0280A0_COLOR_16;
359
360 case PIPE_FORMAT_L8A8_UNORM:
361 case PIPE_FORMAT_L8A8_SNORM:
362 case PIPE_FORMAT_L8A8_UINT:
363 case PIPE_FORMAT_L8A8_SINT:
364 case PIPE_FORMAT_L8A8_SRGB:
365 case PIPE_FORMAT_R8G8_UNORM:
366 case PIPE_FORMAT_R8G8_SNORM:
367 case PIPE_FORMAT_R8G8_UINT:
368 case PIPE_FORMAT_R8G8_SINT:
369 return V_0280A0_COLOR_8_8;
370
371 case PIPE_FORMAT_R16_UNORM:
372 case PIPE_FORMAT_R16_SNORM:
373 case PIPE_FORMAT_R16_UINT:
374 case PIPE_FORMAT_R16_SINT:
375 case PIPE_FORMAT_A16_UNORM:
376 case PIPE_FORMAT_A16_SNORM:
377 case PIPE_FORMAT_A16_UINT:
378 case PIPE_FORMAT_A16_SINT:
379 case PIPE_FORMAT_L16_UNORM:
380 case PIPE_FORMAT_L16_SNORM:
381 case PIPE_FORMAT_L16_UINT:
382 case PIPE_FORMAT_L16_SINT:
383 case PIPE_FORMAT_I16_UNORM:
384 case PIPE_FORMAT_I16_SNORM:
385 case PIPE_FORMAT_I16_UINT:
386 case PIPE_FORMAT_I16_SINT:
387 return V_0280A0_COLOR_16;
388
389 case PIPE_FORMAT_R16_FLOAT:
390 case PIPE_FORMAT_A16_FLOAT:
391 case PIPE_FORMAT_L16_FLOAT:
392 case PIPE_FORMAT_I16_FLOAT:
393 return V_0280A0_COLOR_16_FLOAT;
394
395 /* 32-bit buffers. */
396 case PIPE_FORMAT_A8B8G8R8_SRGB:
397 case PIPE_FORMAT_A8B8G8R8_UNORM:
398 case PIPE_FORMAT_A8R8G8B8_UNORM:
399 case PIPE_FORMAT_B8G8R8A8_SRGB:
400 case PIPE_FORMAT_B8G8R8A8_UNORM:
401 case PIPE_FORMAT_B8G8R8X8_UNORM:
402 case PIPE_FORMAT_R8G8B8A8_SNORM:
403 case PIPE_FORMAT_R8G8B8A8_UNORM:
404 case PIPE_FORMAT_R8G8B8X8_UNORM:
405 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
406 case PIPE_FORMAT_X8B8G8R8_UNORM:
407 case PIPE_FORMAT_X8R8G8B8_UNORM:
408 case PIPE_FORMAT_R8G8B8A8_SINT:
409 case PIPE_FORMAT_R8G8B8A8_UINT:
410 return V_0280A0_COLOR_8_8_8_8;
411
412 case PIPE_FORMAT_R10G10B10A2_UNORM:
413 case PIPE_FORMAT_R10G10B10X2_SNORM:
414 case PIPE_FORMAT_B10G10R10A2_UNORM:
415 case PIPE_FORMAT_B10G10R10A2_UINT:
416 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
417 return V_0280A0_COLOR_2_10_10_10;
418
419 case PIPE_FORMAT_Z24X8_UNORM:
420 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
421 return V_0280A0_COLOR_8_24;
422
423 case PIPE_FORMAT_X8Z24_UNORM:
424 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
425 return V_0280A0_COLOR_24_8;
426
427 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
428 return V_0280A0_COLOR_X24_8_32_FLOAT;
429
430 case PIPE_FORMAT_R32_UINT:
431 case PIPE_FORMAT_R32_SINT:
432 case PIPE_FORMAT_A32_UINT:
433 case PIPE_FORMAT_A32_SINT:
434 case PIPE_FORMAT_L32_UINT:
435 case PIPE_FORMAT_L32_SINT:
436 case PIPE_FORMAT_I32_UINT:
437 case PIPE_FORMAT_I32_SINT:
438 return V_0280A0_COLOR_32;
439
440 case PIPE_FORMAT_R32_FLOAT:
441 case PIPE_FORMAT_A32_FLOAT:
442 case PIPE_FORMAT_L32_FLOAT:
443 case PIPE_FORMAT_I32_FLOAT:
444 case PIPE_FORMAT_Z32_FLOAT:
445 return V_0280A0_COLOR_32_FLOAT;
446
447 case PIPE_FORMAT_R16G16_FLOAT:
448 case PIPE_FORMAT_L16A16_FLOAT:
449 return V_0280A0_COLOR_16_16_FLOAT;
450
451 case PIPE_FORMAT_R16G16_UNORM:
452 case PIPE_FORMAT_R16G16_SNORM:
453 case PIPE_FORMAT_R16G16_UINT:
454 case PIPE_FORMAT_R16G16_SINT:
455 case PIPE_FORMAT_L16A16_UNORM:
456 case PIPE_FORMAT_L16A16_SNORM:
457 case PIPE_FORMAT_L16A16_UINT:
458 case PIPE_FORMAT_L16A16_SINT:
459 return V_0280A0_COLOR_16_16;
460
461 case PIPE_FORMAT_R11G11B10_FLOAT:
462 return V_0280A0_COLOR_10_11_11_FLOAT;
463
464 /* 64-bit buffers. */
465 case PIPE_FORMAT_R16G16B16A16_UINT:
466 case PIPE_FORMAT_R16G16B16A16_SINT:
467 case PIPE_FORMAT_R16G16B16A16_UNORM:
468 case PIPE_FORMAT_R16G16B16A16_SNORM:
469 return V_0280A0_COLOR_16_16_16_16;
470
471 case PIPE_FORMAT_R16G16B16A16_FLOAT:
472 return V_0280A0_COLOR_16_16_16_16_FLOAT;
473
474 case PIPE_FORMAT_R32G32_FLOAT:
475 case PIPE_FORMAT_L32A32_FLOAT:
476 return V_0280A0_COLOR_32_32_FLOAT;
477
478 case PIPE_FORMAT_R32G32_SINT:
479 case PIPE_FORMAT_R32G32_UINT:
480 case PIPE_FORMAT_L32A32_UINT:
481 case PIPE_FORMAT_L32A32_SINT:
482 return V_0280A0_COLOR_32_32;
483
484 /* 128-bit buffers. */
485 case PIPE_FORMAT_R32G32B32A32_FLOAT:
486 return V_0280A0_COLOR_32_32_32_32_FLOAT;
487 case PIPE_FORMAT_R32G32B32A32_SNORM:
488 case PIPE_FORMAT_R32G32B32A32_UNORM:
489 case PIPE_FORMAT_R32G32B32A32_SINT:
490 case PIPE_FORMAT_R32G32B32A32_UINT:
491 return V_0280A0_COLOR_32_32_32_32;
492
493 /* YUV buffers. */
494 case PIPE_FORMAT_UYVY:
495 case PIPE_FORMAT_YUYV:
496 default:
497 return ~0U; /* Unsupported. */
498 }
499 }
500
501 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
502 {
503 if (R600_BIG_ENDIAN) {
504 switch(colorformat) {
505 case V_0280A0_COLOR_4_4:
506 return ENDIAN_NONE;
507
508 /* 8-bit buffers. */
509 case V_0280A0_COLOR_8:
510 return ENDIAN_NONE;
511
512 /* 16-bit buffers. */
513 case V_0280A0_COLOR_5_6_5:
514 case V_0280A0_COLOR_1_5_5_5:
515 case V_0280A0_COLOR_4_4_4_4:
516 case V_0280A0_COLOR_16:
517 case V_0280A0_COLOR_8_8:
518 return ENDIAN_8IN16;
519
520 /* 32-bit buffers. */
521 case V_0280A0_COLOR_8_8_8_8:
522 case V_0280A0_COLOR_2_10_10_10:
523 case V_0280A0_COLOR_8_24:
524 case V_0280A0_COLOR_24_8:
525 case V_0280A0_COLOR_32_FLOAT:
526 case V_0280A0_COLOR_16_16_FLOAT:
527 case V_0280A0_COLOR_16_16:
528 return ENDIAN_8IN32;
529
530 /* 64-bit buffers. */
531 case V_0280A0_COLOR_16_16_16_16:
532 case V_0280A0_COLOR_16_16_16_16_FLOAT:
533 return ENDIAN_8IN16;
534
535 case V_0280A0_COLOR_32_32_FLOAT:
536 case V_0280A0_COLOR_32_32:
537 case V_0280A0_COLOR_X24_8_32_FLOAT:
538 return ENDIAN_8IN32;
539
540 /* 128-bit buffers. */
541 case V_0280A0_COLOR_32_32_32_FLOAT:
542 case V_0280A0_COLOR_32_32_32_32_FLOAT:
543 case V_0280A0_COLOR_32_32_32_32:
544 return ENDIAN_8IN32;
545 default:
546 return ENDIAN_NONE; /* Unsupported. */
547 }
548 } else {
549 return ENDIAN_NONE;
550 }
551 }
552
553 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
554 {
555 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
556 }
557
558 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
559 {
560 return r600_translate_colorformat(format) != ~0U &&
561 r600_translate_colorswap(format) != ~0U;
562 }
563
564 static bool r600_is_zs_format_supported(enum pipe_format format)
565 {
566 return r600_translate_dbformat(format) != ~0U;
567 }
568
569 boolean r600_is_format_supported(struct pipe_screen *screen,
570 enum pipe_format format,
571 enum pipe_texture_target target,
572 unsigned sample_count,
573 unsigned usage)
574 {
575 struct r600_screen *rscreen = (struct r600_screen*)screen;
576 unsigned retval = 0;
577
578 if (target >= PIPE_MAX_TEXTURE_TYPES) {
579 R600_ERR("r600: unsupported texture type %d\n", target);
580 return FALSE;
581 }
582
583 if (!util_format_is_supported(format, usage))
584 return FALSE;
585
586 if (sample_count > 1) {
587 if (rscreen->info.drm_minor < 22)
588 return FALSE;
589
590 /* R11G11B10 is broken on R6xx. */
591 if (rscreen->chip_class == R600 &&
592 format == PIPE_FORMAT_R11G11B10_FLOAT)
593 return FALSE;
594
595 /* MSAA integer colorbuffers hang. */
596 if (util_format_is_pure_integer(format) &&
597 !util_format_is_depth_or_stencil(format))
598 return FALSE;
599
600 switch (sample_count) {
601 case 2:
602 case 4:
603 case 8:
604 break;
605 default:
606 return FALSE;
607 }
608 }
609
610 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
611 r600_is_sampler_format_supported(screen, format)) {
612 retval |= PIPE_BIND_SAMPLER_VIEW;
613 }
614
615 if ((usage & (PIPE_BIND_RENDER_TARGET |
616 PIPE_BIND_DISPLAY_TARGET |
617 PIPE_BIND_SCANOUT |
618 PIPE_BIND_SHARED)) &&
619 r600_is_colorbuffer_format_supported(format)) {
620 retval |= usage &
621 (PIPE_BIND_RENDER_TARGET |
622 PIPE_BIND_DISPLAY_TARGET |
623 PIPE_BIND_SCANOUT |
624 PIPE_BIND_SHARED);
625 }
626
627 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
628 r600_is_zs_format_supported(format)) {
629 retval |= PIPE_BIND_DEPTH_STENCIL;
630 }
631
632 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
633 r600_is_vertex_format_supported(format)) {
634 retval |= PIPE_BIND_VERTEX_BUFFER;
635 }
636
637 if (usage & PIPE_BIND_TRANSFER_READ)
638 retval |= PIPE_BIND_TRANSFER_READ;
639 if (usage & PIPE_BIND_TRANSFER_WRITE)
640 retval |= PIPE_BIND_TRANSFER_WRITE;
641
642 return retval == usage;
643 }
644
645 void r600_polygon_offset_update(struct r600_context *rctx)
646 {
647 struct r600_pipe_state state;
648
649 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
650 state.nregs = 0;
651 if (rctx->rasterizer && rctx->framebuffer.state.zsbuf) {
652 float offset_units = rctx->rasterizer->offset_units;
653 unsigned offset_db_fmt_cntl = 0, depth;
654
655 switch (rctx->framebuffer.state.zsbuf->format) {
656 case PIPE_FORMAT_Z24X8_UNORM:
657 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
658 depth = -24;
659 offset_units *= 2.0f;
660 break;
661 case PIPE_FORMAT_Z32_FLOAT:
662 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
663 depth = -23;
664 offset_units *= 1.0f;
665 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
666 break;
667 case PIPE_FORMAT_Z16_UNORM:
668 depth = -16;
669 offset_units *= 4.0f;
670 break;
671 default:
672 return;
673 }
674 /* XXX some of those reg can be computed with cso */
675 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
676 r600_pipe_state_add_reg(&state,
677 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
678 fui(rctx->rasterizer->offset_scale));
679 r600_pipe_state_add_reg(&state,
680 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
681 fui(offset_units));
682 r600_pipe_state_add_reg(&state,
683 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
684 fui(rctx->rasterizer->offset_scale));
685 r600_pipe_state_add_reg(&state,
686 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
687 fui(offset_units));
688 r600_pipe_state_add_reg(&state,
689 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
690 offset_db_fmt_cntl);
691 r600_context_pipe_state_set(rctx, &state);
692 }
693 }
694
695 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
696 const struct pipe_blend_state *state,
697 int mode)
698 {
699 struct r600_context *rctx = (struct r600_context *)ctx;
700 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
701 struct r600_pipe_state *rstate;
702 uint32_t color_control = 0, target_mask = 0;
703
704 if (blend == NULL) {
705 return NULL;
706 }
707 rstate = &blend->rstate;
708
709 rstate->id = R600_PIPE_STATE_BLEND;
710
711 /* R600 does not support per-MRT blends */
712 if (rctx->family > CHIP_R600)
713 color_control |= S_028808_PER_MRT_BLEND(1);
714
715 if (state->logicop_enable) {
716 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
717 } else {
718 color_control |= (0xcc << 16);
719 }
720 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
721 if (state->independent_blend_enable) {
722 for (int i = 0; i < 8; i++) {
723 if (state->rt[i].blend_enable) {
724 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
725 }
726 target_mask |= (state->rt[i].colormask << (4 * i));
727 }
728 } else {
729 for (int i = 0; i < 8; i++) {
730 if (state->rt[0].blend_enable) {
731 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
732 }
733 target_mask |= (state->rt[0].colormask << (4 * i));
734 }
735 }
736
737 if (target_mask)
738 color_control |= S_028808_SPECIAL_OP(mode);
739 else
740 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
741
742 blend->cb_target_mask = target_mask;
743 blend->cb_color_control = color_control;
744 /* only MRT0 has dual src blend */
745 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
746 for (int i = 0; i < 8; i++) {
747 /* state->rt entries > 0 only written if independent blending */
748 const int j = state->independent_blend_enable ? i : 0;
749
750 unsigned eqRGB = state->rt[j].rgb_func;
751 unsigned srcRGB = state->rt[j].rgb_src_factor;
752 unsigned dstRGB = state->rt[j].rgb_dst_factor;
753
754 unsigned eqA = state->rt[j].alpha_func;
755 unsigned srcA = state->rt[j].alpha_src_factor;
756 unsigned dstA = state->rt[j].alpha_dst_factor;
757 uint32_t bc = 0;
758
759 if (!state->rt[j].blend_enable)
760 continue;
761
762 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
763 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
764 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
765
766 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
767 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
768 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
769 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
770 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
771 }
772
773 /* R600 does not support per-MRT blends */
774 if (rctx->family > CHIP_R600)
775 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc);
776 if (i == 0)
777 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc);
778 }
779
780 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK,
781 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
782 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
783 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
784 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
785 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
786
787 blend->alpha_to_one = state->alpha_to_one;
788 return rstate;
789 }
790
791
792 static void *r600_create_blend_state(struct pipe_context *ctx,
793 const struct pipe_blend_state *state)
794 {
795 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
796 }
797
798 static void *r600_create_dsa_state(struct pipe_context *ctx,
799 const struct pipe_depth_stencil_alpha_state *state)
800 {
801 struct r600_context *rctx = (struct r600_context *)ctx;
802 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
803 unsigned db_depth_control, alpha_test_control, alpha_ref;
804 struct r600_pipe_state *rstate;
805
806 if (dsa == NULL) {
807 return NULL;
808 }
809
810 dsa->valuemask[0] = state->stencil[0].valuemask;
811 dsa->valuemask[1] = state->stencil[1].valuemask;
812 dsa->writemask[0] = state->stencil[0].writemask;
813 dsa->writemask[1] = state->stencil[1].writemask;
814
815 rstate = &dsa->rstate;
816
817 rstate->id = R600_PIPE_STATE_DSA;
818 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
819 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
820 S_028800_ZFUNC(state->depth.func);
821
822 /* stencil */
823 if (state->stencil[0].enabled) {
824 db_depth_control |= S_028800_STENCIL_ENABLE(1);
825 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
826 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
827 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
828 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
829
830 if (state->stencil[1].enabled) {
831 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
832 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
833 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
834 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
835 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
836 }
837 }
838
839 /* alpha */
840 alpha_test_control = 0;
841 alpha_ref = 0;
842 if (state->alpha.enabled) {
843 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
844 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
845 alpha_ref = fui(state->alpha.ref_value);
846 }
847 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
848 dsa->alpha_ref = alpha_ref;
849
850 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
851 return rstate;
852 }
853
854 static void *r600_create_rs_state(struct pipe_context *ctx,
855 const struct pipe_rasterizer_state *state)
856 {
857 struct r600_context *rctx = (struct r600_context *)ctx;
858 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
859 struct r600_pipe_state *rstate;
860 unsigned tmp;
861 unsigned prov_vtx = 1, polygon_dual_mode;
862 unsigned sc_mode_cntl;
863 float psize_min, psize_max;
864
865 if (rs == NULL) {
866 return NULL;
867 }
868
869 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
870 state->fill_back != PIPE_POLYGON_MODE_FILL);
871
872 if (state->flatshade_first)
873 prov_vtx = 0;
874
875 rstate = &rs->rstate;
876 rs->flatshade = state->flatshade;
877 rs->sprite_coord_enable = state->sprite_coord_enable;
878 rs->two_side = state->light_twoside;
879 rs->clip_plane_enable = state->clip_plane_enable;
880 rs->pa_sc_line_stipple = state->line_stipple_enable ?
881 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
882 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
883 rs->pa_cl_clip_cntl =
884 S_028810_PS_UCP_MODE(3) |
885 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
886 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
887 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
888 rs->multisample_enable = state->multisample;
889
890 /* offset */
891 rs->offset_units = state->offset_units;
892 rs->offset_scale = state->offset_scale * 12.0f;
893
894 rstate->id = R600_PIPE_STATE_RASTERIZER;
895 tmp = S_0286D4_FLAT_SHADE_ENA(1);
896 if (state->sprite_coord_enable) {
897 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
898 S_0286D4_PNT_SPRITE_OVRD_X(2) |
899 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
900 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
901 S_0286D4_PNT_SPRITE_OVRD_W(1);
902 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
903 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
904 }
905 }
906 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
907
908 /* point size 12.4 fixed point */
909 tmp = r600_pack_float_12p4(state->point_size/2);
910 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
911
912 if (state->point_size_per_vertex) {
913 psize_min = util_get_min_point_size(state);
914 psize_max = 8192;
915 } else {
916 /* Force the point size to be as if the vertex output was disabled. */
917 psize_min = state->point_size;
918 psize_max = state->point_size;
919 }
920 /* Divide by two, because 0.5 = 1 pixel. */
921 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
922 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
923 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
924
925 tmp = r600_pack_float_12p4(state->line_width/2);
926 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
927
928 if (rctx->chip_class >= R700) {
929 sc_mode_cntl =
930 S_028A4C_MSAA_ENABLE(state->multisample) |
931 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
932 S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
933 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
934 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
935 } else {
936 sc_mode_cntl =
937 S_028A4C_MSAA_ENABLE(state->multisample) |
938 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
939 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
940 rs->scissor_enable = state->scissor;
941 }
942 sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
943
944 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
945
946 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
947 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
948 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
949
950 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
951 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
952 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
953 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
954 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
955 S_028814_FACE(!state->front_ccw) |
956 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
957 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
958 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
959 S_028814_POLY_MODE(polygon_dual_mode) |
960 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
961 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
962 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
963 return rstate;
964 }
965
966 static void *r600_create_sampler_state(struct pipe_context *ctx,
967 const struct pipe_sampler_state *state)
968 {
969 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
970 union util_color uc;
971 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
972
973 if (ss == NULL) {
974 return NULL;
975 }
976
977 ss->seamless_cube_map = state->seamless_cube_map;
978 ss->border_color_use = false;
979 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
980 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
981 ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
982 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
983 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
984 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
985 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
986 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
987 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
988 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
989 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
990 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
991 ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
992 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
993 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
994 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
995 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
996 if (uc.ui) {
997 ss->border_color_use = true;
998 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
999 ss->border_color[0] = fui(state->border_color.f[0]);
1000 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
1001 ss->border_color[1] = fui(state->border_color.f[1]);
1002 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
1003 ss->border_color[2] = fui(state->border_color.f[2]);
1004 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
1005 ss->border_color[3] = fui(state->border_color.f[3]);
1006 }
1007 return ss;
1008 }
1009
1010 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
1011 struct pipe_resource *texture,
1012 const struct pipe_sampler_view *state)
1013 {
1014 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1015 struct r600_texture *tmp = (struct r600_texture*)texture;
1016 unsigned format, endian;
1017 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1018 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1019 unsigned width, height, depth, offset_level, last_level;
1020
1021 if (view == NULL)
1022 return NULL;
1023
1024 /* initialize base object */
1025 view->base = *state;
1026 view->base.texture = NULL;
1027 pipe_reference(NULL, &texture->reference);
1028 view->base.texture = texture;
1029 view->base.reference.count = 1;
1030 view->base.context = ctx;
1031
1032 swizzle[0] = state->swizzle_r;
1033 swizzle[1] = state->swizzle_g;
1034 swizzle[2] = state->swizzle_b;
1035 swizzle[3] = state->swizzle_a;
1036
1037 format = r600_translate_texformat(ctx->screen, state->format,
1038 swizzle,
1039 &word4, &yuv_format);
1040 assert(format != ~0);
1041 if (format == ~0) {
1042 FREE(view);
1043 return NULL;
1044 }
1045
1046 if (tmp->is_depth && !tmp->is_flushing_texture) {
1047 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1048 FREE(view);
1049 return NULL;
1050 }
1051 tmp = tmp->flushed_depth_texture;
1052 }
1053
1054 endian = r600_colorformat_endian_swap(format);
1055
1056 offset_level = state->u.tex.first_level;
1057 last_level = state->u.tex.last_level - offset_level;
1058 width = tmp->surface.level[offset_level].npix_x;
1059 height = tmp->surface.level[offset_level].npix_y;
1060 depth = tmp->surface.level[offset_level].npix_z;
1061 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1062 tile_type = tmp->tile_type;
1063
1064 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1065 height = 1;
1066 depth = texture->array_size;
1067 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1068 depth = texture->array_size;
1069 }
1070 switch (tmp->surface.level[offset_level].mode) {
1071 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1072 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1073 break;
1074 case RADEON_SURF_MODE_1D:
1075 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1076 break;
1077 case RADEON_SURF_MODE_2D:
1078 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1079 break;
1080 case RADEON_SURF_MODE_LINEAR:
1081 default:
1082 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1083 break;
1084 }
1085
1086 view->tex_resource = &tmp->resource;
1087 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1088 S_038000_TILE_MODE(array_mode) |
1089 S_038000_TILE_TYPE(tile_type) |
1090 S_038000_PITCH((pitch / 8) - 1) |
1091 S_038000_TEX_WIDTH(width - 1));
1092 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
1093 S_038004_TEX_DEPTH(depth - 1) |
1094 S_038004_DATA_FORMAT(format));
1095 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
1096 if (offset_level >= tmp->surface.last_level) {
1097 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
1098 } else {
1099 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1100 }
1101 view->tex_resource_words[4] = (word4 |
1102 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1103 S_038010_REQUEST_SIZE(1) |
1104 S_038010_ENDIAN_SWAP(endian) |
1105 S_038010_BASE_LEVEL(0));
1106 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1107 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1108 if (texture->nr_samples > 1) {
1109 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1110 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
1111 } else {
1112 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
1113 }
1114 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1115 S_038018_MAX_ANISO(4 /* max 16 samples */));
1116 return &view->base;
1117 }
1118
1119 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1120 {
1121 struct radeon_winsys_cs *cs = rctx->cs;
1122 struct pipe_clip_state *state = &rctx->clip_state.state;
1123
1124 r600_write_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
1125 r600_write_array(cs, 6*4, (unsigned*)state);
1126 }
1127
1128 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1129 const struct pipe_poly_stipple *state)
1130 {
1131 }
1132
1133 void r600_set_scissor_state(struct r600_context *rctx,
1134 const struct pipe_scissor_state *state)
1135 {
1136 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1137 uint32_t tl, br;
1138
1139 if (rstate == NULL)
1140 return;
1141
1142 rstate->id = R600_PIPE_STATE_SCISSOR;
1143 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1144 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1145 r600_pipe_state_add_reg(rstate,
1146 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1147 r600_pipe_state_add_reg(rstate,
1148 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1149
1150 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1151 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1152 r600_context_pipe_state_set(rctx, rstate);
1153 }
1154
1155 static void r600_pipe_set_scissor_state(struct pipe_context *ctx,
1156 const struct pipe_scissor_state *state)
1157 {
1158 struct r600_context *rctx = (struct r600_context *)ctx;
1159
1160 rctx->scissor = *state;
1161
1162 if (rctx->chip_class == R600 && !rctx->scissor_enable)
1163 return;
1164
1165 r600_set_scissor_state(rctx, state);
1166 }
1167
1168 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
1169 unsigned size, unsigned alignment)
1170 {
1171 struct pipe_resource buffer;
1172
1173 memset(&buffer, 0, sizeof buffer);
1174 buffer.target = PIPE_BUFFER;
1175 buffer.format = PIPE_FORMAT_R8_UNORM;
1176 buffer.bind = PIPE_BIND_CUSTOM;
1177 buffer.usage = PIPE_USAGE_STATIC;
1178 buffer.flags = 0;
1179 buffer.width0 = size;
1180 buffer.height0 = 1;
1181 buffer.depth0 = 1;
1182 buffer.array_size = 1;
1183
1184 return (struct r600_resource*)
1185 r600_buffer_create(&rscreen->screen, &buffer, alignment);
1186 }
1187
1188 static void r600_init_color_surface(struct r600_context *rctx,
1189 struct r600_surface *surf,
1190 bool force_cmask_fmask)
1191 {
1192 struct r600_screen *rscreen = rctx->screen;
1193 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1194 unsigned level = surf->base.u.tex.level;
1195 unsigned pitch, slice;
1196 unsigned color_info;
1197 unsigned format, swap, ntype, endian;
1198 unsigned offset;
1199 const struct util_format_description *desc;
1200 int i;
1201 bool blend_bypass = 0, blend_clamp = 1;
1202
1203 if (rtex->is_depth && !rtex->is_flushing_texture) {
1204 r600_init_flushed_depth_texture(&rctx->context, surf->base.texture, NULL);
1205 rtex = rtex->flushed_depth_texture;
1206 assert(rtex);
1207 }
1208
1209 offset = rtex->surface.level[level].offset;
1210 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1211 offset += rtex->surface.level[level].slice_size *
1212 surf->base.u.tex.first_layer;
1213 }
1214 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1215 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1216 if (slice) {
1217 slice = slice - 1;
1218 }
1219 color_info = 0;
1220 switch (rtex->surface.level[level].mode) {
1221 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1222 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1223 break;
1224 case RADEON_SURF_MODE_1D:
1225 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1226 break;
1227 case RADEON_SURF_MODE_2D:
1228 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1229 break;
1230 case RADEON_SURF_MODE_LINEAR:
1231 default:
1232 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1233 break;
1234 }
1235
1236 desc = util_format_description(surf->base.format);
1237
1238 for (i = 0; i < 4; i++) {
1239 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1240 break;
1241 }
1242 }
1243
1244 ntype = V_0280A0_NUMBER_UNORM;
1245 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1246 ntype = V_0280A0_NUMBER_SRGB;
1247 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1248 if (desc->channel[i].normalized)
1249 ntype = V_0280A0_NUMBER_SNORM;
1250 else if (desc->channel[i].pure_integer)
1251 ntype = V_0280A0_NUMBER_SINT;
1252 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1253 if (desc->channel[i].normalized)
1254 ntype = V_0280A0_NUMBER_UNORM;
1255 else if (desc->channel[i].pure_integer)
1256 ntype = V_0280A0_NUMBER_UINT;
1257 }
1258
1259 format = r600_translate_colorformat(surf->base.format);
1260 assert(format != ~0);
1261
1262 swap = r600_translate_colorswap(surf->base.format);
1263 assert(swap != ~0);
1264
1265 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1266 endian = ENDIAN_NONE;
1267 } else {
1268 endian = r600_colorformat_endian_swap(format);
1269 }
1270
1271 /* set blend bypass according to docs if SINT/UINT or
1272 8/24 COLOR variants */
1273 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1274 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1275 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1276 blend_clamp = 0;
1277 blend_bypass = 1;
1278 }
1279
1280 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
1281
1282 color_info |= S_0280A0_FORMAT(format) |
1283 S_0280A0_COMP_SWAP(swap) |
1284 S_0280A0_BLEND_BYPASS(blend_bypass) |
1285 S_0280A0_BLEND_CLAMP(blend_clamp) |
1286 S_0280A0_NUMBER_TYPE(ntype) |
1287 S_0280A0_ENDIAN(endian);
1288
1289 /* EXPORT_NORM is an optimzation that can be enabled for better
1290 * performance in certain cases
1291 */
1292 if (rctx->chip_class == R600) {
1293 /* EXPORT_NORM can be enabled if:
1294 * - 11-bit or smaller UNORM/SNORM/SRGB
1295 * - BLEND_CLAMP is enabled
1296 * - BLEND_FLOAT32 is disabled
1297 */
1298 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1299 (desc->channel[i].size < 12 &&
1300 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1301 ntype != V_0280A0_NUMBER_UINT &&
1302 ntype != V_0280A0_NUMBER_SINT) &&
1303 G_0280A0_BLEND_CLAMP(color_info) &&
1304 !G_0280A0_BLEND_FLOAT32(color_info)) {
1305 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1306 surf->export_16bpc = true;
1307 }
1308 } else {
1309 /* EXPORT_NORM can be enabled if:
1310 * - 11-bit or smaller UNORM/SNORM/SRGB
1311 * - 16-bit or smaller FLOAT
1312 */
1313 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1314 ((desc->channel[i].size < 12 &&
1315 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1316 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1317 (desc->channel[i].size < 17 &&
1318 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1319 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1320 surf->export_16bpc = true;
1321 }
1322 }
1323
1324 /* These might not always be initialized to zero. */
1325 surf->cb_color_base = offset >> 8;
1326 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
1327 S_028060_SLICE_TILE_MAX(slice);
1328 surf->cb_color_fmask = surf->cb_color_base;
1329 surf->cb_color_cmask = surf->cb_color_base;
1330 surf->cb_color_mask = 0;
1331
1332 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1333 &rtex->resource.b.b);
1334 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1335 &rtex->resource.b.b);
1336
1337 if (rtex->cmask_size) {
1338 surf->cb_color_cmask = rtex->cmask_offset >> 8;
1339 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask_slice_tile_max);
1340
1341 if (rtex->fmask_size) {
1342 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1343 surf->cb_color_fmask = rtex->fmask_offset >> 8;
1344 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(slice);
1345 } else { /* cmask only */
1346 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
1347 }
1348 } else if (force_cmask_fmask) {
1349 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1350 *
1351 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1352 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1353 * because it's not an MSAA buffer.
1354 */
1355 struct r600_cmask_info cmask;
1356 struct r600_fmask_info fmask;
1357
1358 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
1359 r600_texture_get_fmask_info(rscreen, rtex, 8, &fmask);
1360
1361 /* CMASK. */
1362 if (!rctx->dummy_cmask ||
1363 rctx->dummy_cmask->buf->size < cmask.size ||
1364 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1365 struct pipe_transfer *transfer;
1366 void *ptr;
1367
1368 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1369 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1370
1371 /* Set the contents to 0xCC. */
1372 ptr = pipe_buffer_map(&rctx->context, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1373 memset(ptr, 0xCC, cmask.size);
1374 pipe_buffer_unmap(&rctx->context, transfer);
1375 }
1376 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1377 &rctx->dummy_cmask->b.b);
1378
1379 /* FMASK. */
1380 if (!rctx->dummy_fmask ||
1381 rctx->dummy_fmask->buf->size < fmask.size ||
1382 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1383 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1384 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1385
1386 }
1387 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1388 &rctx->dummy_fmask->b.b);
1389
1390 /* Init the registers. */
1391 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1392 surf->cb_color_cmask = 0;
1393 surf->cb_color_fmask = 0;
1394 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1395 S_028100_FMASK_TILE_MAX(slice);
1396 }
1397
1398 surf->cb_color_info = color_info;
1399
1400 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1401 surf->cb_color_view = 0;
1402 } else {
1403 surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
1404 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
1405 }
1406
1407 surf->color_initialized = true;
1408 }
1409
1410 static void r600_init_depth_surface(struct r600_context *rctx,
1411 struct r600_surface *surf)
1412 {
1413 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1414 unsigned level, pitch, slice, format, offset, array_mode;
1415
1416 level = surf->base.u.tex.level;
1417 offset = rtex->surface.level[level].offset;
1418 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1419 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1420 if (slice) {
1421 slice = slice - 1;
1422 }
1423 switch (rtex->surface.level[level].mode) {
1424 case RADEON_SURF_MODE_2D:
1425 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1426 break;
1427 case RADEON_SURF_MODE_1D:
1428 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1429 case RADEON_SURF_MODE_LINEAR:
1430 default:
1431 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1432 break;
1433 }
1434
1435 format = r600_translate_dbformat(surf->base.format);
1436 assert(format != ~0);
1437
1438 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1439 surf->db_depth_base = offset >> 8;
1440 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1441 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1442 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1443 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1444
1445 surf->depth_initialized = true;
1446 }
1447
1448 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1449 const struct pipe_framebuffer_state *state)
1450 {
1451 struct r600_context *rctx = (struct r600_context *)ctx;
1452 struct r600_surface *surf;
1453 struct r600_texture *rtex;
1454 unsigned i;
1455
1456 if (rctx->framebuffer.state.nr_cbufs) {
1457 rctx->flags |= R600_CONTEXT_CB_FLUSH;
1458
1459 if (rctx->chip_class >= R700 &&
1460 rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
1461 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
1462 }
1463 }
1464 if (rctx->framebuffer.state.zsbuf) {
1465 rctx->flags |= R600_CONTEXT_DB_FLUSH;
1466 }
1467 /* R6xx errata */
1468 if (rctx->chip_class == R600) {
1469 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
1470 }
1471
1472 /* Set the new state. */
1473 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1474
1475 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1476 rctx->framebuffer.cb0_is_integer = state->nr_cbufs &&
1477 util_format_is_pure_integer(state->cbufs[0]->format);
1478 rctx->framebuffer.compressed_cb_mask = 0;
1479 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1480 state->cbufs[0]->texture->nr_samples > 1 &&
1481 state->cbufs[1]->texture->nr_samples <= 1;
1482
1483 if (state->nr_cbufs)
1484 rctx->framebuffer.nr_samples = state->cbufs[0]->texture->nr_samples;
1485 else if (state->zsbuf)
1486 rctx->framebuffer.nr_samples = state->zsbuf->texture->nr_samples;
1487 else
1488 rctx->framebuffer.nr_samples = 0;
1489
1490 /* Colorbuffers. */
1491 for (i = 0; i < state->nr_cbufs; i++) {
1492 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1493 bool force_cmask_fmask = rctx->chip_class == R600 &&
1494 rctx->framebuffer.is_msaa_resolve &&
1495 i == 1;
1496
1497 surf = (struct r600_surface*)state->cbufs[i];
1498 rtex = (struct r600_texture*)surf->base.texture;
1499
1500 if (!surf->color_initialized || force_cmask_fmask) {
1501 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1502 if (force_cmask_fmask) {
1503 /* re-initialize later without compression */
1504 surf->color_initialized = false;
1505 }
1506 }
1507
1508 if (!surf->export_16bpc) {
1509 rctx->framebuffer.export_16bpc = false;
1510 }
1511
1512 if (rtex->fmask_size && rtex->cmask_size) {
1513 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1514 }
1515 }
1516
1517 /* Update alpha-test state dependencies.
1518 * Alpha-test is done on the first colorbuffer only. */
1519 if (state->nr_cbufs) {
1520 surf = (struct r600_surface*)state->cbufs[0];
1521 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1522 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1523 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1524 }
1525 }
1526
1527 /* ZS buffer. */
1528 if (state->zsbuf) {
1529 surf = (struct r600_surface*)state->zsbuf;
1530
1531 if (!surf->depth_initialized) {
1532 r600_init_depth_surface(rctx, surf);
1533 }
1534
1535 r600_polygon_offset_update(rctx);
1536 }
1537
1538 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1539 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1540 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1541 }
1542
1543 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1544 rctx->alphatest_state.bypass = false;
1545 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1546 }
1547
1548 /* Calculate the CS size. */
1549 rctx->framebuffer.atom.num_dw =
1550 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1551
1552 if (rctx->framebuffer.state.nr_cbufs) {
1553 rctx->framebuffer.atom.num_dw += 6 * (2 + rctx->framebuffer.state.nr_cbufs);
1554 rctx->framebuffer.atom.num_dw += 6 * rctx->framebuffer.state.nr_cbufs; /* relocs */
1555
1556 }
1557 if (rctx->framebuffer.state.zsbuf) {
1558 rctx->framebuffer.atom.num_dw += 13;
1559 } else if (rctx->screen->info.drm_minor >= 18) {
1560 rctx->framebuffer.atom.num_dw += 3;
1561 }
1562 if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770) {
1563 rctx->framebuffer.atom.num_dw += 2;
1564 }
1565
1566 r600_atom_dirty(rctx, &rctx->framebuffer.atom);
1567 }
1568
1569 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1570 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1571 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1572 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1573 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1574
1575 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1576 {
1577 static uint32_t sample_locs_2x[] = {
1578 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1579 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1580 };
1581 static unsigned max_dist_2x = 4;
1582 static uint32_t sample_locs_4x[] = {
1583 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1584 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1585 };
1586 static unsigned max_dist_4x = 6;
1587 static uint32_t sample_locs_8x[] = {
1588 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1589 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1590 };
1591 static unsigned max_dist_8x = 8;
1592
1593 struct radeon_winsys_cs *cs = rctx->cs;
1594 unsigned max_dist = 0;
1595
1596 if (rctx->family == CHIP_R600) {
1597 switch (nr_samples) {
1598 default:
1599 nr_samples = 0;
1600 break;
1601 case 2:
1602 r600_write_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1603 max_dist = max_dist_2x;
1604 break;
1605 case 4:
1606 r600_write_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1607 max_dist = max_dist_4x;
1608 break;
1609 case 8:
1610 r600_write_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1611 r600_write_value(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1612 r600_write_value(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1613 max_dist = max_dist_8x;
1614 break;
1615 }
1616 } else {
1617 switch (nr_samples) {
1618 default:
1619 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1620 r600_write_value(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1621 r600_write_value(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1622 nr_samples = 0;
1623 break;
1624 case 2:
1625 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1626 r600_write_value(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1627 r600_write_value(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1628 max_dist = max_dist_2x;
1629 break;
1630 case 4:
1631 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1632 r600_write_value(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1633 r600_write_value(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1634 max_dist = max_dist_4x;
1635 break;
1636 case 8:
1637 r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1638 r600_write_value(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1639 r600_write_value(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1640 max_dist = max_dist_8x;
1641 break;
1642 }
1643 }
1644
1645 if (nr_samples > 1) {
1646 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1647 r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
1648 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1649 r600_write_value(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1650 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1651 } else {
1652 r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1653 r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1654 r600_write_value(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1655 }
1656 }
1657
1658 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1659 {
1660 struct radeon_winsys_cs *cs = rctx->cs;
1661 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1662 unsigned nr_cbufs = state->nr_cbufs;
1663 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1664 unsigned i, sbu = 0;
1665
1666 /* Colorbuffers. */
1667 r600_write_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1668 for (i = 0; i < nr_cbufs; i++) {
1669 r600_write_value(cs, cb[i]->cb_color_info);
1670 }
1671 /* set CB_COLOR1_INFO for possible dual-src blending */
1672 if (i == 1) {
1673 r600_write_value(cs, cb[0]->cb_color_info);
1674 i++;
1675 }
1676 for (; i < 8; i++) {
1677 r600_write_value(cs, 0);
1678 }
1679
1680 if (nr_cbufs) {
1681 /* COLOR_BASE */
1682 r600_write_context_reg_seq(cs, R_028040_CB_COLOR0_BASE, nr_cbufs);
1683 for (i = 0; i < nr_cbufs; i++) {
1684 r600_write_value(cs, cb[i]->cb_color_base);
1685 }
1686
1687 /* relocations */
1688 for (i = 0; i < nr_cbufs; i++) {
1689 unsigned reloc = r600_context_bo_reloc(rctx,
1690 (struct r600_resource*)cb[i]->base.texture,
1691 RADEON_USAGE_READWRITE);
1692 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1693 r600_write_value(cs, reloc);
1694 }
1695
1696 r600_write_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1697 for (i = 0; i < nr_cbufs; i++) {
1698 r600_write_value(cs, cb[i]->cb_color_size);
1699 }
1700
1701 r600_write_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1702 for (i = 0; i < nr_cbufs; i++) {
1703 r600_write_value(cs, cb[i]->cb_color_view);
1704 }
1705
1706 r600_write_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1707 for (i = 0; i < nr_cbufs; i++) {
1708 r600_write_value(cs, cb[i]->cb_color_mask);
1709 }
1710
1711 /* FMASK. */
1712 r600_write_context_reg_seq(cs, R_0280E0_CB_COLOR0_FRAG, nr_cbufs);
1713 for (i = 0; i < nr_cbufs; i++) {
1714 r600_write_value(cs, cb[i]->cb_color_fmask);
1715 }
1716 /* relocations */
1717 for (i = 0; i < nr_cbufs; i++) {
1718 unsigned reloc = r600_context_bo_reloc(rctx,
1719 cb[i]->cb_buffer_fmask,
1720 RADEON_USAGE_READWRITE);
1721 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1722 r600_write_value(cs, reloc);
1723 }
1724
1725 /* CMASK. */
1726 r600_write_context_reg_seq(cs, R_0280C0_CB_COLOR0_TILE, nr_cbufs);
1727 for (i = 0; i < nr_cbufs; i++) {
1728 r600_write_value(cs, cb[i]->cb_color_cmask);
1729 }
1730 /* relocations */
1731 for (i = 0; i < nr_cbufs; i++) {
1732 unsigned reloc = r600_context_bo_reloc(rctx,
1733 cb[i]->cb_buffer_cmask,
1734 RADEON_USAGE_READWRITE);
1735 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1736 r600_write_value(cs, reloc);
1737 }
1738
1739 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1740 }
1741
1742 /* Zbuffer. */
1743 if (state->zsbuf) {
1744 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1745 unsigned reloc = r600_context_bo_reloc(rctx,
1746 (struct r600_resource*)state->zsbuf->texture,
1747 RADEON_USAGE_READWRITE);
1748
1749 r600_write_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1750 r600_write_value(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1751 r600_write_value(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1752 r600_write_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1753 r600_write_value(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1754 r600_write_value(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1755
1756 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1757 r600_write_value(cs, reloc);
1758
1759 r600_write_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1760
1761 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1762 } else if (rctx->screen->info.drm_minor >= 18) {
1763 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1764 * Older kernels are out of luck. */
1765 r600_write_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1766 }
1767
1768 /* SURFACE_BASE_UPDATE */
1769 if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770 && sbu) {
1770 r600_write_value(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1771 r600_write_value(cs, sbu);
1772 }
1773
1774 /* Framebuffer dimensions. */
1775 r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1776 r600_write_value(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1777 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1778 r600_write_value(cs, S_028244_BR_X(state->width) |
1779 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1780
1781 if (rctx->framebuffer.is_msaa_resolve) {
1782 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1783 } else {
1784 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1785 * will assure that the alpha-test will work even if there is
1786 * no colorbuffer bound. */
1787 r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1788 (1ull << MAX2(nr_cbufs, 1)) - 1);
1789 }
1790
1791 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1792 }
1793
1794 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1795 {
1796 struct radeon_winsys_cs *cs = rctx->cs;
1797 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1798
1799 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1800 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1801 if (rctx->chip_class == R600) {
1802 r600_write_value(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1803 r600_write_value(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1804 } else {
1805 r600_write_value(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1806 r600_write_value(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1807 }
1808 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1809 } else {
1810 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1811 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1812 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1813
1814 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1815 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1816 /* Always enable the first color output to make sure alpha-test works even without one. */
1817 r600_write_value(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1818 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1819 a->cb_color_control |
1820 S_028808_MULTIWRITE_ENABLE(multiwrite));
1821 }
1822 }
1823
1824 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1825 {
1826 struct radeon_winsys_cs *cs = rctx->cs;
1827 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1828 unsigned db_render_control = 0;
1829 unsigned db_render_override =
1830 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
1831 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1832 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1833
1834 if (a->occlusion_query_enabled) {
1835 if (rctx->chip_class >= R700) {
1836 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1837 }
1838 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1839 }
1840 if (a->flush_depthstencil_through_cb) {
1841 assert(a->copy_depth || a->copy_stencil);
1842
1843 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1844 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1845 S_028D0C_COPY_CENTROID(1) |
1846 S_028D0C_COPY_SAMPLE(a->copy_sample);
1847 }
1848
1849 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1850 r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1851 r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1852 }
1853
1854 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1855 {
1856 struct radeon_winsys_cs *cs = rctx->cs;
1857 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1858
1859 while (dirty_mask) {
1860 struct pipe_vertex_buffer *vb;
1861 struct r600_resource *rbuffer;
1862 unsigned offset;
1863 unsigned buffer_index = u_bit_scan(&dirty_mask);
1864
1865 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1866 rbuffer = (struct r600_resource*)vb->buffer;
1867 assert(rbuffer);
1868
1869 offset = vb->buffer_offset;
1870
1871 /* fetch resources start at index 320 */
1872 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1873 r600_write_value(cs, (320 + buffer_index) * 7);
1874 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1875 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1876 r600_write_value(cs, /* RESOURCEi_WORD2 */
1877 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1878 S_038008_STRIDE(vb->stride));
1879 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1880 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1881 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1882 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1883
1884 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1885 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1886 }
1887 }
1888
1889 static void r600_emit_constant_buffers(struct r600_context *rctx,
1890 struct r600_constbuf_state *state,
1891 unsigned buffer_id_base,
1892 unsigned reg_alu_constbuf_size,
1893 unsigned reg_alu_const_cache)
1894 {
1895 struct radeon_winsys_cs *cs = rctx->cs;
1896 uint32_t dirty_mask = state->dirty_mask;
1897
1898 while (dirty_mask) {
1899 struct pipe_constant_buffer *cb;
1900 struct r600_resource *rbuffer;
1901 unsigned offset;
1902 unsigned buffer_index = ffs(dirty_mask) - 1;
1903
1904 cb = &state->cb[buffer_index];
1905 rbuffer = (struct r600_resource*)cb->buffer;
1906 assert(rbuffer);
1907
1908 offset = cb->buffer_offset;
1909
1910 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1911 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1912 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1913
1914 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1915 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1916
1917 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1918 r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
1919 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1920 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1921 r600_write_value(cs, /* RESOURCEi_WORD2 */
1922 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1923 S_038008_STRIDE(16));
1924 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1925 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1926 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1927 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1928
1929 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1930 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1931
1932 dirty_mask &= ~(1 << buffer_index);
1933 }
1934 state->dirty_mask = 0;
1935 }
1936
1937 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1938 {
1939 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 160,
1940 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1941 R_028980_ALU_CONST_CACHE_VS_0);
1942 }
1943
1944 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1945 {
1946 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 336,
1947 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1948 R_0289C0_ALU_CONST_CACHE_GS_0);
1949 }
1950
1951 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1952 {
1953 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 0,
1954 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1955 R_028940_ALU_CONST_CACHE_PS_0);
1956 }
1957
1958 static void r600_emit_sampler_views(struct r600_context *rctx,
1959 struct r600_samplerview_state *state,
1960 unsigned resource_id_base)
1961 {
1962 struct radeon_winsys_cs *cs = rctx->cs;
1963 uint32_t dirty_mask = state->dirty_mask;
1964
1965 while (dirty_mask) {
1966 struct r600_pipe_sampler_view *rview;
1967 unsigned resource_index = u_bit_scan(&dirty_mask);
1968 unsigned reloc;
1969
1970 rview = state->views[resource_index];
1971 assert(rview);
1972
1973 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1974 r600_write_value(cs, (resource_id_base + resource_index) * 7);
1975 r600_write_array(cs, 7, rview->tex_resource_words);
1976
1977 /* XXX The kernel needs two relocations. This is stupid. */
1978 reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
1979 RADEON_USAGE_READ);
1980 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1981 r600_write_value(cs, reloc);
1982 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1983 r600_write_value(cs, reloc);
1984 }
1985 state->dirty_mask = 0;
1986 }
1987
1988 /* Resource IDs:
1989 * PS: 0 .. +160
1990 * VS: 160 .. +160
1991 * FS: 320 .. +16
1992 * GS: 336 .. +160
1993 */
1994
1995 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1996 {
1997 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 160 + R600_MAX_CONST_BUFFERS);
1998 }
1999
2000 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2001 {
2002 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
2003 }
2004
2005 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2006 {
2007 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
2008 }
2009
2010 static void r600_emit_sampler_states(struct r600_context *rctx,
2011 struct r600_textures_info *texinfo,
2012 unsigned resource_id_base,
2013 unsigned border_color_reg)
2014 {
2015 struct radeon_winsys_cs *cs = rctx->cs;
2016 uint32_t dirty_mask = texinfo->states.dirty_mask;
2017
2018 while (dirty_mask) {
2019 struct r600_pipe_sampler_state *rstate;
2020 struct r600_pipe_sampler_view *rview;
2021 unsigned i = u_bit_scan(&dirty_mask);
2022
2023 rstate = texinfo->states.states[i];
2024 assert(rstate);
2025 rview = texinfo->views.views[i];
2026
2027 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
2028 * filtering between layers.
2029 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
2030 */
2031 if (rview) {
2032 enum pipe_texture_target target = rview->base.texture->target;
2033 if (target == PIPE_TEXTURE_1D_ARRAY ||
2034 target == PIPE_TEXTURE_2D_ARRAY) {
2035 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
2036 texinfo->is_array_sampler[i] = true;
2037 } else {
2038 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
2039 texinfo->is_array_sampler[i] = false;
2040 }
2041 }
2042
2043 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2044 r600_write_value(cs, (resource_id_base + i) * 3);
2045 r600_write_array(cs, 3, rstate->tex_sampler_words);
2046
2047 if (rstate->border_color_use) {
2048 unsigned offset;
2049
2050 offset = border_color_reg;
2051 offset += i * 16;
2052 r600_write_config_reg_seq(cs, offset, 4);
2053 r600_write_array(cs, 4, rstate->border_color);
2054 }
2055 }
2056 texinfo->states.dirty_mask = 0;
2057 }
2058
2059 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2060 {
2061 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
2062 }
2063
2064 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2065 {
2066 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
2067 }
2068
2069 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2070 {
2071 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
2072 }
2073
2074 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
2075 {
2076 struct radeon_winsys_cs *cs = rctx->cs;
2077 unsigned tmp;
2078
2079 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
2080 S_009508_SYNC_GRADIENT(1) |
2081 S_009508_SYNC_WALKER(1) |
2082 S_009508_SYNC_ALIGNER(1);
2083 if (!rctx->seamless_cube_map.enabled) {
2084 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
2085 }
2086 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
2087 }
2088
2089 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2090 {
2091 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2092 uint8_t mask = s->sample_mask;
2093
2094 r600_write_context_reg(rctx->cs, R_028C48_PA_SC_AA_MASK,
2095 mask | (mask << 8) | (mask << 16) | (mask << 24));
2096 }
2097
2098 void r600_init_state_functions(struct r600_context *rctx)
2099 {
2100 unsigned id = 4;
2101
2102 /* !!!
2103 * To avoid GPU lockup registers must be emited in a specific order
2104 * (no kidding ...). The order below is important and have been
2105 * partialy infered from analyzing fglrx command stream.
2106 *
2107 * Don't reorder atom without carefully checking the effect (GPU lockup
2108 * or piglit regression).
2109 * !!!
2110 */
2111
2112 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
2113
2114 /* shader const */
2115 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
2116 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
2117 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
2118
2119 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2120 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
2121 */
2122 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
2123 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
2124 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
2125 /* resource */
2126 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
2127 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
2128 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
2129 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
2130
2131 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 6);
2132 r600_init_atom(rctx, &rctx->vgt2_state.atom, id++, r600_emit_vgt2_state, 3);
2133
2134 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
2135 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
2136 rctx->sample_mask.sample_mask = ~0;
2137
2138 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
2139 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
2140 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
2141 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
2142 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
2143 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 4);
2144 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
2145 r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
2146
2147 rctx->context.create_blend_state = r600_create_blend_state;
2148 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
2149 rctx->context.create_rasterizer_state = r600_create_rs_state;
2150 rctx->context.create_sampler_state = r600_create_sampler_state;
2151 rctx->context.create_sampler_view = r600_create_sampler_view;
2152 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
2153 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
2154 rctx->context.set_scissor_state = r600_pipe_set_scissor_state;
2155 }
2156
2157 /* Adjust GPR allocation on R6xx/R7xx */
2158 void r600_adjust_gprs(struct r600_context *rctx)
2159 {
2160 struct r600_pipe_state rstate;
2161 unsigned num_ps_gprs = rctx->default_ps_gprs;
2162 unsigned num_vs_gprs = rctx->default_vs_gprs;
2163 unsigned tmp;
2164 int diff;
2165
2166 if (rctx->ps_shader->current->shader.bc.ngpr > rctx->default_ps_gprs) {
2167 diff = rctx->ps_shader->current->shader.bc.ngpr - rctx->default_ps_gprs;
2168 num_vs_gprs -= diff;
2169 num_ps_gprs += diff;
2170 }
2171
2172 if (rctx->vs_shader->current->shader.bc.ngpr > rctx->default_vs_gprs)
2173 {
2174 diff = rctx->vs_shader->current->shader.bc.ngpr - rctx->default_vs_gprs;
2175 num_ps_gprs -= diff;
2176 num_vs_gprs += diff;
2177 }
2178
2179 tmp = 0;
2180 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2181 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2182 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
2183 rstate.nregs = 0;
2184 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp);
2185
2186 r600_context_pipe_state_set(rctx, &rstate);
2187 }
2188
2189 void r600_init_atom_start_cs(struct r600_context *rctx)
2190 {
2191 int ps_prio;
2192 int vs_prio;
2193 int gs_prio;
2194 int es_prio;
2195 int num_ps_gprs;
2196 int num_vs_gprs;
2197 int num_gs_gprs;
2198 int num_es_gprs;
2199 int num_temp_gprs;
2200 int num_ps_threads;
2201 int num_vs_threads;
2202 int num_gs_threads;
2203 int num_es_threads;
2204 int num_ps_stack_entries;
2205 int num_vs_stack_entries;
2206 int num_gs_stack_entries;
2207 int num_es_stack_entries;
2208 enum radeon_family family;
2209 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2210 uint32_t tmp;
2211
2212 r600_init_command_buffer(rctx, cb, 0, 256);
2213
2214 /* R6xx requires this packet at the start of each command buffer */
2215 if (rctx->chip_class == R600) {
2216 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2217 r600_store_value(cb, 0);
2218 }
2219 /* All asics require this one */
2220 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2221 r600_store_value(cb, 0x80000000);
2222 r600_store_value(cb, 0x80000000);
2223
2224 family = rctx->family;
2225 ps_prio = 0;
2226 vs_prio = 1;
2227 gs_prio = 2;
2228 es_prio = 3;
2229 switch (family) {
2230 case CHIP_R600:
2231 num_ps_gprs = 192;
2232 num_vs_gprs = 56;
2233 num_temp_gprs = 4;
2234 num_gs_gprs = 0;
2235 num_es_gprs = 0;
2236 num_ps_threads = 136;
2237 num_vs_threads = 48;
2238 num_gs_threads = 4;
2239 num_es_threads = 4;
2240 num_ps_stack_entries = 128;
2241 num_vs_stack_entries = 128;
2242 num_gs_stack_entries = 0;
2243 num_es_stack_entries = 0;
2244 break;
2245 case CHIP_RV630:
2246 case CHIP_RV635:
2247 num_ps_gprs = 84;
2248 num_vs_gprs = 36;
2249 num_temp_gprs = 4;
2250 num_gs_gprs = 0;
2251 num_es_gprs = 0;
2252 num_ps_threads = 144;
2253 num_vs_threads = 40;
2254 num_gs_threads = 4;
2255 num_es_threads = 4;
2256 num_ps_stack_entries = 40;
2257 num_vs_stack_entries = 40;
2258 num_gs_stack_entries = 32;
2259 num_es_stack_entries = 16;
2260 break;
2261 case CHIP_RV610:
2262 case CHIP_RV620:
2263 case CHIP_RS780:
2264 case CHIP_RS880:
2265 default:
2266 num_ps_gprs = 84;
2267 num_vs_gprs = 36;
2268 num_temp_gprs = 4;
2269 num_gs_gprs = 0;
2270 num_es_gprs = 0;
2271 num_ps_threads = 136;
2272 num_vs_threads = 48;
2273 num_gs_threads = 4;
2274 num_es_threads = 4;
2275 num_ps_stack_entries = 40;
2276 num_vs_stack_entries = 40;
2277 num_gs_stack_entries = 32;
2278 num_es_stack_entries = 16;
2279 break;
2280 case CHIP_RV670:
2281 num_ps_gprs = 144;
2282 num_vs_gprs = 40;
2283 num_temp_gprs = 4;
2284 num_gs_gprs = 0;
2285 num_es_gprs = 0;
2286 num_ps_threads = 136;
2287 num_vs_threads = 48;
2288 num_gs_threads = 4;
2289 num_es_threads = 4;
2290 num_ps_stack_entries = 40;
2291 num_vs_stack_entries = 40;
2292 num_gs_stack_entries = 32;
2293 num_es_stack_entries = 16;
2294 break;
2295 case CHIP_RV770:
2296 num_ps_gprs = 192;
2297 num_vs_gprs = 56;
2298 num_temp_gprs = 4;
2299 num_gs_gprs = 0;
2300 num_es_gprs = 0;
2301 num_ps_threads = 188;
2302 num_vs_threads = 60;
2303 num_gs_threads = 0;
2304 num_es_threads = 0;
2305 num_ps_stack_entries = 256;
2306 num_vs_stack_entries = 256;
2307 num_gs_stack_entries = 0;
2308 num_es_stack_entries = 0;
2309 break;
2310 case CHIP_RV730:
2311 case CHIP_RV740:
2312 num_ps_gprs = 84;
2313 num_vs_gprs = 36;
2314 num_temp_gprs = 4;
2315 num_gs_gprs = 0;
2316 num_es_gprs = 0;
2317 num_ps_threads = 188;
2318 num_vs_threads = 60;
2319 num_gs_threads = 0;
2320 num_es_threads = 0;
2321 num_ps_stack_entries = 128;
2322 num_vs_stack_entries = 128;
2323 num_gs_stack_entries = 0;
2324 num_es_stack_entries = 0;
2325 break;
2326 case CHIP_RV710:
2327 num_ps_gprs = 192;
2328 num_vs_gprs = 56;
2329 num_temp_gprs = 4;
2330 num_gs_gprs = 0;
2331 num_es_gprs = 0;
2332 num_ps_threads = 144;
2333 num_vs_threads = 48;
2334 num_gs_threads = 0;
2335 num_es_threads = 0;
2336 num_ps_stack_entries = 128;
2337 num_vs_stack_entries = 128;
2338 num_gs_stack_entries = 0;
2339 num_es_stack_entries = 0;
2340 break;
2341 }
2342
2343 rctx->default_ps_gprs = num_ps_gprs;
2344 rctx->default_vs_gprs = num_vs_gprs;
2345 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2346
2347 /* SQ_CONFIG */
2348 tmp = 0;
2349 switch (family) {
2350 case CHIP_RV610:
2351 case CHIP_RV620:
2352 case CHIP_RS780:
2353 case CHIP_RS880:
2354 case CHIP_RV710:
2355 break;
2356 default:
2357 tmp |= S_008C00_VC_ENABLE(1);
2358 break;
2359 }
2360 tmp |= S_008C00_DX9_CONSTS(0);
2361 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2362 tmp |= S_008C00_PS_PRIO(ps_prio);
2363 tmp |= S_008C00_VS_PRIO(vs_prio);
2364 tmp |= S_008C00_GS_PRIO(gs_prio);
2365 tmp |= S_008C00_ES_PRIO(es_prio);
2366 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2367
2368 /* SQ_GPR_RESOURCE_MGMT_2 */
2369 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2370 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2371 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2372 r600_store_value(cb, tmp);
2373
2374 /* SQ_THREAD_RESOURCE_MGMT */
2375 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2376 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2377 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2378 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2379 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2380
2381 /* SQ_STACK_RESOURCE_MGMT_1 */
2382 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2383 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2384 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2385
2386 /* SQ_STACK_RESOURCE_MGMT_2 */
2387 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2388 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2389 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2390
2391 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2392
2393 if (rctx->chip_class >= R700) {
2394 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2395 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2396 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2397 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2398 } else {
2399 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2400 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2401 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2402 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2403 }
2404 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2405 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2406 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2407 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2408 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2409 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2410 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2411 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2412 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2413 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2414
2415 /* to avoid GPU doing any preloading of constant from random address */
2416 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8);
2417 r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */
2418 r600_store_value(cb, 0);
2419 r600_store_value(cb, 0);
2420 r600_store_value(cb, 0);
2421 r600_store_value(cb, 0);
2422 r600_store_value(cb, 0);
2423 r600_store_value(cb, 0);
2424 r600_store_value(cb, 0);
2425 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8);
2426 r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */
2427 r600_store_value(cb, 0);
2428 r600_store_value(cb, 0);
2429 r600_store_value(cb, 0);
2430 r600_store_value(cb, 0);
2431 r600_store_value(cb, 0);
2432 r600_store_value(cb, 0);
2433 r600_store_value(cb, 0);
2434
2435 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2436 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2437 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2438 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2439 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2440 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2441 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2442 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2443 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2444 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2445 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2446 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2447 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2448 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2449
2450 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2451 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2452 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2453
2454 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2455 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2456 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2457 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2458
2459 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2460
2461 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2462 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2463 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2464
2465 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2466
2467 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2468 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2469 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2470
2471 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2472 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2473 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2474 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2475
2476 r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2477 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2478 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2479
2480 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2481 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2482
2483 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2484 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2485 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2486 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2487 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2488
2489 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2490 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2491 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2492
2493 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2494
2495 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2496 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2497
2498 if (rctx->chip_class >= R700) {
2499 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2500 }
2501
2502 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2503 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2504 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2505 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2506 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2507
2508 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2509 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2510 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2511
2512 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2513 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2514 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2515
2516 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2517 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2518 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2519
2520 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2521 r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2522
2523 if (rctx->chip_class == R700 && rctx->screen->has_streamout)
2524 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2525 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2526 if (rctx->screen->has_streamout) {
2527 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2528 }
2529
2530 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2531 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2532 }
2533
2534 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2535 {
2536 struct r600_context *rctx = (struct r600_context *)ctx;
2537 struct r600_pipe_state *rstate = &shader->rstate;
2538 struct r600_shader *rshader = &shader->shader;
2539 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2540 int pos_index = -1, face_index = -1;
2541 unsigned tmp, sid, ufi = 0;
2542 int need_linear = 0;
2543 unsigned z_export = 0, stencil_export = 0;
2544
2545 rstate->nregs = 0;
2546
2547 for (i = 0; i < rshader->ninput; i++) {
2548 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2549 pos_index = i;
2550 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2551 face_index = i;
2552
2553 sid = rshader->input[i].spi_sid;
2554
2555 tmp = S_028644_SEMANTIC(sid);
2556
2557 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2558 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2559 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2560 rctx->rasterizer && rctx->rasterizer->flatshade))
2561 tmp |= S_028644_FLAT_SHADE(1);
2562
2563 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2564 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2565 tmp |= S_028644_PT_SPRITE_TEX(1);
2566 }
2567
2568 if (rshader->input[i].centroid)
2569 tmp |= S_028644_SEL_CENTROID(1);
2570
2571 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2572 need_linear = 1;
2573 tmp |= S_028644_SEL_LINEAR(1);
2574 }
2575
2576 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2577 tmp);
2578 }
2579
2580 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2581 for (i = 0; i < rshader->noutput; i++) {
2582 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2583 z_export = 1;
2584 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2585 stencil_export = 1;
2586 }
2587 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2588 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2589 if (rshader->uses_kill)
2590 db_shader_control |= S_02880C_KILL_ENABLE(1);
2591
2592 exports_ps = 0;
2593 for (i = 0; i < rshader->noutput; i++) {
2594 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2595 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2596 exports_ps |= 1;
2597 }
2598 }
2599 num_cout = rshader->nr_ps_color_exports;
2600 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2601 if (!exports_ps) {
2602 /* always at least export 1 component per pixel */
2603 exports_ps = 2;
2604 }
2605
2606 shader->nr_ps_color_outputs = num_cout;
2607
2608 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2609 S_0286CC_PERSP_GRADIENT_ENA(1)|
2610 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2611 spi_input_z = 0;
2612 if (pos_index != -1) {
2613 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2614 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2615 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2616 S_0286CC_BARYC_SAMPLE_CNTL(1));
2617 spi_input_z |= 1;
2618 }
2619
2620 spi_ps_in_control_1 = 0;
2621 if (face_index != -1) {
2622 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2623 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2624 }
2625
2626 /* HW bug in original R600 */
2627 if (rctx->family == CHIP_R600)
2628 ufi = 1;
2629
2630 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2631 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2632 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2633 r600_pipe_state_add_reg_bo(rstate,
2634 R_028840_SQ_PGM_START_PS,
2635 0, shader->bo, RADEON_USAGE_READ);
2636 r600_pipe_state_add_reg(rstate,
2637 R_028850_SQ_PGM_RESOURCES_PS,
2638 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2639 S_028850_STACK_SIZE(rshader->bc.nstack) |
2640 S_028850_UNCACHED_FIRST_INST(ufi));
2641 r600_pipe_state_add_reg(rstate,
2642 R_028854_SQ_PGM_EXPORTS_PS,
2643 exports_ps);
2644 /* only set some bits here, the other bits are set in the dsa state */
2645 shader->db_shader_control = db_shader_control;
2646 shader->ps_depth_export = z_export | stencil_export;
2647
2648 shader->sprite_coord_enable = rctx->sprite_coord_enable;
2649 if (rctx->rasterizer)
2650 shader->flatshade = rctx->rasterizer->flatshade;
2651 }
2652
2653 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2654 {
2655 struct r600_context *rctx = (struct r600_context *)ctx;
2656 struct r600_pipe_state *rstate = &shader->rstate;
2657 struct r600_shader *rshader = &shader->shader;
2658 unsigned spi_vs_out_id[10] = {};
2659 unsigned i, tmp, nparams = 0;
2660
2661 /* clear previous register */
2662 rstate->nregs = 0;
2663
2664 for (i = 0; i < rshader->noutput; i++) {
2665 if (rshader->output[i].spi_sid) {
2666 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2667 spi_vs_out_id[nparams / 4] |= tmp;
2668 nparams++;
2669 }
2670 }
2671
2672 for (i = 0; i < 10; i++) {
2673 r600_pipe_state_add_reg(rstate,
2674 R_028614_SPI_VS_OUT_ID_0 + i * 4,
2675 spi_vs_out_id[i]);
2676 }
2677
2678 /* Certain attributes (position, psize, etc.) don't count as params.
2679 * VS is required to export at least one param and r600_shader_from_tgsi()
2680 * takes care of adding a dummy export.
2681 */
2682 if (nparams < 1)
2683 nparams = 1;
2684
2685 r600_pipe_state_add_reg(rstate,
2686 R_0286C4_SPI_VS_OUT_CONFIG,
2687 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2688 r600_pipe_state_add_reg(rstate,
2689 R_028868_SQ_PGM_RESOURCES_VS,
2690 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2691 S_028868_STACK_SIZE(rshader->bc.nstack));
2692 r600_pipe_state_add_reg_bo(rstate,
2693 R_028858_SQ_PGM_START_VS,
2694 0, shader->bo, RADEON_USAGE_READ);
2695
2696 shader->pa_cl_vs_out_cntl =
2697 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2698 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2699 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2700 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2701 }
2702
2703 void r600_fetch_shader(struct pipe_context *ctx,
2704 struct r600_vertex_element *ve)
2705 {
2706 struct r600_pipe_state *rstate;
2707 struct r600_context *rctx = (struct r600_context *)ctx;
2708
2709 rstate = &ve->rstate;
2710 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2711 rstate->nregs = 0;
2712 r600_pipe_state_add_reg_bo(rstate, R_028894_SQ_PGM_START_FS,
2713 0,
2714 ve->fetch_shader, RADEON_USAGE_READ);
2715 }
2716
2717 void *r600_create_resolve_blend(struct r600_context *rctx)
2718 {
2719 struct pipe_blend_state blend;
2720 struct r600_pipe_state *rstate;
2721 unsigned i;
2722
2723 memset(&blend, 0, sizeof(blend));
2724 blend.independent_blend_enable = true;
2725 for (i = 0; i < 2; i++) {
2726 blend.rt[i].colormask = 0xf;
2727 blend.rt[i].blend_enable = 1;
2728 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2729 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2730 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2731 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2732 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2733 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2734 }
2735 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2736 return rstate;
2737 }
2738
2739 void *r700_create_resolve_blend(struct r600_context *rctx)
2740 {
2741 struct pipe_blend_state blend;
2742 struct r600_pipe_state *rstate;
2743
2744 memset(&blend, 0, sizeof(blend));
2745 blend.independent_blend_enable = true;
2746 blend.rt[0].colormask = 0xf;
2747 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2748 return rstate;
2749 }
2750
2751 void *r600_create_decompress_blend(struct r600_context *rctx)
2752 {
2753 struct pipe_blend_state blend;
2754 struct r600_pipe_state *rstate;
2755
2756 memset(&blend, 0, sizeof(blend));
2757 blend.independent_blend_enable = true;
2758 blend.rt[0].colormask = 0xf;
2759 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2760 return rstate;
2761 }
2762
2763 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2764 {
2765 struct pipe_depth_stencil_alpha_state dsa;
2766 boolean quirk = false;
2767
2768 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2769 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2770 quirk = true;
2771
2772 memset(&dsa, 0, sizeof(dsa));
2773
2774 if (quirk) {
2775 dsa.depth.enabled = 1;
2776 dsa.depth.func = PIPE_FUNC_LEQUAL;
2777 dsa.stencil[0].enabled = 1;
2778 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2779 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2780 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2781 dsa.stencil[0].writemask = 0xff;
2782 }
2783
2784 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2785 }
2786
2787 void r600_update_dual_export_state(struct r600_context * rctx)
2788 {
2789 bool dual_export = rctx->framebuffer.export_16bpc &&
2790 !rctx->ps_shader->current->ps_depth_export;
2791
2792 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2793 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2794
2795 if (db_shader_control != rctx->db_shader_control) {
2796 struct r600_pipe_state rstate;
2797
2798 rctx->db_shader_control = db_shader_control;
2799 rstate.nregs = 0;
2800 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2801 r600_context_pipe_state_set(rctx, &rstate);
2802 }
2803 }