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r600g: use a hash table instead of group
[mesa.git] / src / gallium / drivers / r600 / r600_state2.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <util/u_upload_mgr.h>
43 #include <util/u_index_modify.h>
44 #include <pipebuffer/pb_buffer.h>
45 #include "r600.h"
46 #include "r600d.h"
47 #include "r700_sq.h"
48 struct radeon_state {
49 unsigned dummy;
50 };
51 #include "r600_resource.h"
52 #include "r600_shader.h"
53 #include "r600_pipe.h"
54 #include "r600_state_inlines.h"
55
56 /* r600_shader.c */
57 static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
58 {
59 struct r600_pipe_state *rstate = &shader->rstate;
60 struct r600_shader *rshader = &shader->shader;
61 unsigned spi_vs_out_id[10];
62 unsigned i, tmp;
63
64 /* clear previous register */
65 rstate->nregs = 0;
66
67 /* so far never got proper semantic id from tgsi */
68 for (i = 0; i < 10; i++) {
69 spi_vs_out_id[i] = 0;
70 }
71 for (i = 0; i < 32; i++) {
72 tmp = i << ((i & 3) * 8);
73 spi_vs_out_id[i / 4] |= tmp;
74 }
75 for (i = 0; i < 10; i++) {
76 r600_pipe_state_add_reg(rstate,
77 R_028614_SPI_VS_OUT_ID_0 + i * 4,
78 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
79 }
80
81 r600_pipe_state_add_reg(rstate,
82 R_0286C4_SPI_VS_OUT_CONFIG,
83 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
84 0xFFFFFFFF, NULL);
85 r600_pipe_state_add_reg(rstate,
86 R_028868_SQ_PGM_RESOURCES_VS,
87 S_028868_NUM_GPRS(rshader->bc.ngpr) |
88 S_028868_STACK_SIZE(rshader->bc.nstack),
89 0xFFFFFFFF, NULL);
90 r600_pipe_state_add_reg(rstate,
91 R_0288A4_SQ_PGM_RESOURCES_FS,
92 0x00000000, 0xFFFFFFFF, NULL);
93 r600_pipe_state_add_reg(rstate,
94 R_0288D0_SQ_PGM_CF_OFFSET_VS,
95 0x00000000, 0xFFFFFFFF, NULL);
96 r600_pipe_state_add_reg(rstate,
97 R_0288DC_SQ_PGM_CF_OFFSET_FS,
98 0x00000000, 0xFFFFFFFF, NULL);
99 r600_pipe_state_add_reg(rstate,
100 R_028858_SQ_PGM_START_VS,
101 0x00000000, 0xFFFFFFFF, shader->bo);
102 r600_pipe_state_add_reg(rstate,
103 R_028894_SQ_PGM_START_FS,
104 0x00000000, 0xFFFFFFFF, shader->bo);
105 }
106
107 int r600_find_vs_semantic_index2(struct r600_shader *vs,
108 struct r600_shader *ps, int id)
109 {
110 struct r600_shader_io *input = &ps->input[id];
111
112 for (int i = 0; i < vs->noutput; i++) {
113 if (input->name == vs->output[i].name &&
114 input->sid == vs->output[i].sid) {
115 return i - 1;
116 }
117 }
118 return 0;
119 }
120
121 static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
122 {
123 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
124 struct r600_pipe_state *rstate = &shader->rstate;
125 struct r600_shader *rshader = &shader->shader;
126 unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z;
127 boolean have_pos = FALSE, have_face = FALSE;
128
129 /* clear previous register */
130 rstate->nregs = 0;
131
132 for (i = 0; i < rshader->ninput; i++) {
133 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index2(&rctx->vs_shader->shader, rshader, i));
134 tmp |= S_028644_SEL_CENTROID(1);
135 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
136 have_pos = TRUE;
137 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
138 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
139 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
140 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
141 }
142 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
143 have_face = TRUE;
144 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
145 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
146 tmp |= S_028644_PT_SPRITE_TEX(1);
147 }
148 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
149 }
150 for (i = 0; i < rshader->noutput; i++) {
151 r600_pipe_state_add_reg(rstate,
152 R_02880C_DB_SHADER_CONTROL,
153 S_02880C_Z_EXPORT_ENABLE(1),
154 S_02880C_Z_EXPORT_ENABLE(1), NULL);
155 }
156
157 exports_ps = 0;
158 num_cout = 0;
159 for (i = 0; i < rshader->noutput; i++) {
160 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
161 exports_ps |= 1;
162 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
163 num_cout++;
164 }
165 }
166 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
167 if (!exports_ps) {
168 /* always at least export 1 component per pixel */
169 exports_ps = 2;
170 }
171
172 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
173 S_0286CC_PERSP_GRADIENT_ENA(1);
174 spi_input_z = 0;
175 if (have_pos) {
176 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
177 S_0286CC_BARYC_SAMPLE_CNTL(1);
178 spi_input_z |= 1;
179 }
180 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
181 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, S_0286D0_FRONT_FACE_ENA(have_face), 0xFFFFFFFF, NULL);
182 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
183 r600_pipe_state_add_reg(rstate,
184 R_028840_SQ_PGM_START_PS,
185 0x00000000, 0xFFFFFFFF, shader->bo);
186 r600_pipe_state_add_reg(rstate,
187 R_028850_SQ_PGM_RESOURCES_PS,
188 S_028868_NUM_GPRS(rshader->bc.ngpr) |
189 S_028868_STACK_SIZE(rshader->bc.nstack),
190 0xFFFFFFFF, NULL);
191 r600_pipe_state_add_reg(rstate,
192 R_028854_SQ_PGM_EXPORTS_PS,
193 exports_ps, 0xFFFFFFFF, NULL);
194 r600_pipe_state_add_reg(rstate,
195 R_0288CC_SQ_PGM_CF_OFFSET_PS,
196 0x00000000, 0xFFFFFFFF, NULL);
197
198 if (rshader->uses_kill) {
199 /* only set some bits here, the other bits are set in the dsa state */
200 r600_pipe_state_add_reg(rstate,
201 R_02880C_DB_SHADER_CONTROL,
202 S_02880C_KILL_ENABLE(1),
203 S_02880C_KILL_ENABLE(1), NULL);
204 }
205 }
206
207 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
208 {
209 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
210 struct r600_shader *rshader = &shader->shader;
211 void *ptr;
212
213 /* copy new shader */
214 if (shader->bo == NULL) {
215 shader->bo = radeon_ws_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0);
216 if (shader->bo == NULL) {
217 return -ENOMEM;
218 }
219 ptr = radeon_ws_bo_map(rctx->radeon, shader->bo, 0, NULL);
220 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
221 radeon_ws_bo_unmap(rctx->radeon, shader->bo);
222 }
223 /* build state */
224 rshader->flat_shade = rctx->flatshade;
225 switch (rshader->processor_type) {
226 case TGSI_PROCESSOR_VERTEX:
227 if (rshader->family >= CHIP_CEDAR) {
228 evergreen_pipe_shader_vs(ctx, shader);
229 } else {
230 r600_pipe_shader_vs(ctx, shader);
231 }
232 break;
233 case TGSI_PROCESSOR_FRAGMENT:
234 if (rshader->family >= CHIP_CEDAR) {
235 evergreen_pipe_shader_ps(ctx, shader);
236 } else {
237 r600_pipe_shader_ps(ctx, shader);
238 }
239 break;
240 default:
241 return -EINVAL;
242 }
243 r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
244 return 0;
245 }
246
247 static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rshader)
248 {
249 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
250 struct r600_shader *shader = &rshader->shader;
251 const struct util_format_description *desc;
252 enum pipe_format resource_format[160];
253 unsigned i, nresources = 0;
254 struct r600_bc *bc = &shader->bc;
255 struct r600_bc_cf *cf;
256 struct r600_bc_vtx *vtx;
257
258 if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
259 return 0;
260 if (!memcmp(&rshader->vertex_elements, rctx->vertex_elements, sizeof(struct r600_vertex_element))) {
261 return 0;
262 }
263 rshader->vertex_elements = *rctx->vertex_elements;
264 for (i = 0; i < rctx->vertex_elements->count; i++) {
265 resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
266 }
267 radeon_ws_bo_reference(rctx->radeon, &rshader->bo, NULL);
268 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
269 switch (cf->inst) {
270 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
271 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
272 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
273 desc = util_format_description(resource_format[vtx->buffer_id]);
274 if (desc == NULL) {
275 R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
276 return -EINVAL;
277 }
278 vtx->dst_sel_x = desc->swizzle[0];
279 vtx->dst_sel_y = desc->swizzle[1];
280 vtx->dst_sel_z = desc->swizzle[2];
281 vtx->dst_sel_w = desc->swizzle[3];
282 }
283 break;
284 default:
285 break;
286 }
287 }
288 return r600_bc_build(&shader->bc);
289 }
290
291 int r600_pipe_shader_update2(struct pipe_context *ctx, struct r600_pipe_shader *shader)
292 {
293 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
294 int r;
295
296 if (shader == NULL)
297 return -EINVAL;
298 /* there should be enough input */
299 if (rctx->vertex_elements->count < shader->shader.bc.nresource) {
300 R600_ERR("%d resources provided, expecting %d\n",
301 rctx->vertex_elements->count, shader->shader.bc.nresource);
302 return -EINVAL;
303 }
304 r = r600_shader_update(ctx, shader);
305 if (r)
306 return r;
307 return r600_pipe_shader(ctx, shader);
308 }
309
310 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
311 int r600_pipe_shader_create2(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
312 {
313 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
314 int r;
315
316 //fprintf(stderr, "--------------------------------------------------------------\n");
317 //tgsi_dump(tokens, 0);
318 shader->shader.family = r600_get_family(rctx->radeon);
319 r = r600_shader_from_tgsi(tokens, &shader->shader);
320 if (r) {
321 R600_ERR("translation from TGSI failed !\n");
322 return r;
323 }
324 r = r600_bc_build(&shader->shader.bc);
325 if (r) {
326 R600_ERR("building bytecode failed !\n");
327 return r;
328 }
329 //fprintf(stderr, "______________________________________________________________\n");
330 return 0;
331 }
332 /* r600_shader.c END */
333
334 static const char* r600_get_vendor(struct pipe_screen* pscreen)
335 {
336 return "X.Org";
337 }
338
339 static const char* r600_get_name(struct pipe_screen* pscreen)
340 {
341 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
342 enum radeon_family family = r600_get_family(rscreen->radeon);
343
344 if (family >= CHIP_R600 && family < CHIP_RV770)
345 return "R600 (HD2XXX,HD3XXX)";
346 else if (family < CHIP_CEDAR)
347 return "R700 (HD4XXX)";
348 else
349 return "EVERGREEN";
350 }
351
352 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
353 {
354 switch (param) {
355 /* Supported features (boolean caps). */
356 case PIPE_CAP_NPOT_TEXTURES:
357 case PIPE_CAP_TWO_SIDED_STENCIL:
358 case PIPE_CAP_GLSL:
359 case PIPE_CAP_DUAL_SOURCE_BLEND:
360 case PIPE_CAP_ANISOTROPIC_FILTER:
361 case PIPE_CAP_POINT_SPRITE:
362 case PIPE_CAP_OCCLUSION_QUERY:
363 case PIPE_CAP_TEXTURE_SHADOW_MAP:
364 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
365 case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
366 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
367 case PIPE_CAP_SM3:
368 case PIPE_CAP_TEXTURE_SWIZZLE:
369 case PIPE_CAP_INDEP_BLEND_ENABLE:
370 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
371 case PIPE_CAP_DEPTH_CLAMP:
372 return 1;
373
374 /* Unsupported features (boolean caps). */
375 case PIPE_CAP_TIMER_QUERY:
376 case PIPE_CAP_STREAM_OUTPUT:
377 case PIPE_CAP_INDEP_BLEND_FUNC: /* FIXME allow this */
378 return 0;
379
380 /* Texturing. */
381 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
382 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
383 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
384 return 14;
385 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
386 /* FIXME allow this once infrastructure is there */
387 return 0;
388 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
389 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
390 return 16;
391
392 /* Render targets. */
393 case PIPE_CAP_MAX_RENDER_TARGETS:
394 /* FIXME some r6xx are buggy and can only do 4 */
395 return 8;
396
397 /* Fragment coordinate conventions. */
398 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
399 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
400 return 1;
401 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
402 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
403 return 0;
404
405 default:
406 R600_ERR("r600: unknown param %d\n", param);
407 return 0;
408 }
409 }
410
411 static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
412 {
413 switch (param) {
414 case PIPE_CAP_MAX_LINE_WIDTH:
415 case PIPE_CAP_MAX_LINE_WIDTH_AA:
416 case PIPE_CAP_MAX_POINT_WIDTH:
417 case PIPE_CAP_MAX_POINT_WIDTH_AA:
418 return 8192.0f;
419 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
420 return 16.0f;
421 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
422 return 16.0f;
423 default:
424 R600_ERR("r600: unsupported paramf %d\n", param);
425 return 0.0f;
426 }
427 }
428
429 static boolean r600_is_format_supported(struct pipe_screen* screen,
430 enum pipe_format format,
431 enum pipe_texture_target target,
432 unsigned sample_count,
433 unsigned usage,
434 unsigned geom_flags)
435 {
436 unsigned retval = 0;
437 if (target >= PIPE_MAX_TEXTURE_TYPES) {
438 R600_ERR("r600: unsupported texture type %d\n", target);
439 return FALSE;
440 }
441
442 /* Multisample */
443 if (sample_count > 1)
444 return FALSE;
445
446 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
447 r600_is_sampler_format_supported(format)) {
448 retval |= PIPE_BIND_SAMPLER_VIEW;
449 }
450
451 if ((usage & (PIPE_BIND_RENDER_TARGET |
452 PIPE_BIND_DISPLAY_TARGET |
453 PIPE_BIND_SCANOUT |
454 PIPE_BIND_SHARED)) &&
455 r600_is_colorbuffer_format_supported(format)) {
456 retval |= usage &
457 (PIPE_BIND_RENDER_TARGET |
458 PIPE_BIND_DISPLAY_TARGET |
459 PIPE_BIND_SCANOUT |
460 PIPE_BIND_SHARED);
461 }
462
463 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
464 r600_is_zs_format_supported(format)) {
465 retval |= PIPE_BIND_DEPTH_STENCIL;
466 }
467
468 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
469 r600_is_vertex_format_supported(format))
470 retval |= PIPE_BIND_VERTEX_BUFFER;
471
472 if (usage & PIPE_BIND_TRANSFER_READ)
473 retval |= PIPE_BIND_TRANSFER_READ;
474 if (usage & PIPE_BIND_TRANSFER_WRITE)
475 retval |= PIPE_BIND_TRANSFER_WRITE;
476
477 return retval == usage;
478 }
479
480 static void r600_destroy_screen(struct pipe_screen* pscreen)
481 {
482 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
483
484 if (rscreen == NULL)
485 return;
486 FREE(rscreen);
487 }
488
489 int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
490 static void r600_draw_common(struct r600_drawl *draw)
491 {
492 struct r600_pipe_context *rctx = (struct r600_pipe_context *)draw->ctx;
493 struct r600_pipe_state *rstate;
494 struct r600_resource *rbuffer;
495 unsigned i, j, offset, format, prim;
496 u32 vgt_dma_index_type, vgt_draw_initiator, mask;
497 struct pipe_vertex_buffer *vertex_buffer;
498 struct r600_draw rdraw;
499 struct r600_pipe_state vgt;
500
501 switch (draw->index_size) {
502 case 2:
503 vgt_draw_initiator = 0;
504 vgt_dma_index_type = 0;
505 break;
506 case 4:
507 vgt_draw_initiator = 0;
508 vgt_dma_index_type = 1;
509 break;
510 case 0:
511 vgt_draw_initiator = 2;
512 vgt_dma_index_type = 0;
513 break;
514 default:
515 R600_ERR("unsupported index size %d\n", draw->index_size);
516 return;
517 }
518 if (r600_conv_pipe_prim(draw->mode, &prim))
519 return;
520
521
522 /* rebuild vertex shader if input format changed */
523 if (r600_pipe_shader_update2(&rctx->context, rctx->vs_shader))
524 return;
525 if (r600_pipe_shader_update2(&rctx->context, rctx->ps_shader))
526 return;
527
528 for (i = 0 ; i < rctx->vertex_elements->count; i++) {
529 unsigned num_format = 0, format_comp = 0;
530
531 rstate = &rctx->vs_resource[i];
532 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
533 vertex_buffer = &rctx->vertex_buffer[j];
534 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
535 offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
536 format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
537 rstate->id = R600_PIPE_STATE_RESOURCE;
538 rstate->nregs = 0;
539
540 r600_translate_vertex_num_format(rctx->vertex_elements->elements[i].src_format, &num_format, &format_comp);
541 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
542 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
543 r600_pipe_state_add_reg(rstate,
544 R_038008_RESOURCE0_WORD2,
545 S_038008_STRIDE(vertex_buffer->stride) |
546 S_038008_DATA_FORMAT(format) |
547 S_038008_NUM_FORMAT_ALL(num_format) |
548 S_038008_FORMAT_COMP_ALL(format_comp),
549 0xFFFFFFFF, NULL);
550 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3, 0x00000000, 0xFFFFFFFF, NULL);
551 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
552 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
553 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6, 0xC0000000, 0xFFFFFFFF, NULL);
554 r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, i);
555 }
556
557 mask = 0;
558 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
559 mask |= (0xF << (i * 4));
560 }
561
562 vgt.id = R600_PIPE_STATE_VGT;
563 vgt.nregs = 0;
564 r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
565 r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw->index_bias, 0xFFFFFFFF, NULL);
566 r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw->max_index, 0xFFFFFFFF, NULL);
567 r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw->min_index, 0xFFFFFFFF, NULL);
568 r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
569 /* build late state */
570 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
571 float offset_units = rctx->rasterizer->offset_units;
572 unsigned offset_db_fmt_cntl = 0, depth;
573
574 switch (rctx->framebuffer.zsbuf->texture->format) {
575 case PIPE_FORMAT_Z24X8_UNORM:
576 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
577 depth = -24;
578 offset_units *= 2.0f;
579 break;
580 case PIPE_FORMAT_Z32_FLOAT:
581 depth = -23;
582 offset_units *= 1.0f;
583 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
584 break;
585 case PIPE_FORMAT_Z16_UNORM:
586 depth = -16;
587 offset_units *= 4.0f;
588 break;
589 default:
590 return;
591 }
592 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
593 r600_pipe_state_add_reg(&vgt,
594 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
595 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
596 r600_pipe_state_add_reg(&vgt,
597 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
598 fui(offset_units), 0xFFFFFFFF, NULL);
599 r600_pipe_state_add_reg(&vgt,
600 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
601 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
602 r600_pipe_state_add_reg(&vgt,
603 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
604 fui(offset_units), 0xFFFFFFFF, NULL);
605 r600_pipe_state_add_reg(&vgt,
606 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
607 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
608 }
609 r600_context_pipe_state_set(&rctx->ctx, &vgt);
610
611 rdraw.vgt_num_indices = draw->count;
612 rdraw.vgt_num_instances = 1;
613 rdraw.vgt_index_type = vgt_dma_index_type;
614 rdraw.vgt_draw_initiator = vgt_draw_initiator;
615 rdraw.indices = NULL;
616 if (draw->index_buffer) {
617 rbuffer = (struct r600_resource*)draw->index_buffer;
618 rdraw.indices = rbuffer->bo;
619 rdraw.indices_bo_offset = draw->index_buffer_offset;
620 }
621 r600_context_draw(&rctx->ctx, &rdraw);
622 }
623
624 void r600_translate_index_buffer2(struct r600_pipe_context *r600,
625 struct pipe_resource **index_buffer,
626 unsigned *index_size,
627 unsigned *start, unsigned count)
628 {
629 switch (*index_size) {
630 case 1:
631 util_shorten_ubyte_elts(&r600->context, index_buffer, 0, *start, count);
632 *index_size = 2;
633 *start = 0;
634 break;
635
636 case 2:
637 if (*start % 2 != 0) {
638 util_rebuild_ushort_elts(&r600->context, index_buffer, 0, *start, count);
639 *start = 0;
640 }
641 break;
642
643 case 4:
644 break;
645 }
646 }
647
648 static void r600_draw_vbo2(struct pipe_context *ctx, const struct pipe_draw_info *info)
649 {
650 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
651 struct r600_drawl draw;
652
653 if (rctx->any_user_vbs) {
654 r600_upload_user_buffers2(rctx);
655 rctx->any_user_vbs = FALSE;
656 }
657
658 memset(&draw, 0, sizeof(struct r600_drawl));
659 draw.ctx = ctx;
660 draw.mode = info->mode;
661 draw.start = info->start;
662 draw.count = info->count;
663 if (info->indexed && rctx->index_buffer.buffer) {
664 draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
665 draw.min_index = info->min_index;
666 draw.max_index = info->max_index;
667 draw.index_bias = info->index_bias;
668
669 r600_translate_index_buffer2(rctx, &rctx->index_buffer.buffer,
670 &rctx->index_buffer.index_size,
671 &draw.start,
672 info->count);
673
674 draw.index_size = rctx->index_buffer.index_size;
675 pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
676 draw.index_buffer_offset = draw.start * draw.index_size;
677 draw.start = 0;
678 r600_upload_index_buffer2(rctx, &draw);
679 } else {
680 draw.index_size = 0;
681 draw.index_buffer = NULL;
682 draw.min_index = info->min_index;
683 draw.max_index = info->max_index;
684 draw.index_bias = info->start;
685 }
686 r600_draw_common(&draw);
687
688 pipe_resource_reference(&draw.index_buffer, NULL);
689 }
690
691 static void r600_flush2(struct pipe_context *ctx, unsigned flags,
692 struct pipe_fence_handle **fence)
693 {
694 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
695 #if 0
696 static int dc = 0;
697 char dname[256];
698 #endif
699
700 if (!rctx->ctx.pm4_cdwords)
701 return;
702
703 u_upload_flush(rctx->upload_vb);
704 u_upload_flush(rctx->upload_ib);
705
706 #if 0
707 sprintf(dname, "gallium-%08d.bof", dc);
708 if (dc < 20) {
709 r600_context_dump_bof(&rctx->ctx, dname);
710 R600_ERR("dumped %s\n", dname);
711 }
712 dc++;
713 #endif
714 r600_context_flush(&rctx->ctx);
715 }
716
717 static void r600_destroy_context(struct pipe_context *context)
718 {
719 struct r600_pipe_context *rctx = (struct r600_pipe_context *)context;
720
721 r600_context_fini(&rctx->ctx);
722 for (int i = 0; i < R600_PIPE_NSTATES; i++) {
723 free(rctx->states[i]);
724 }
725
726 u_upload_destroy(rctx->upload_vb);
727 u_upload_destroy(rctx->upload_ib);
728
729 FREE(rctx);
730 }
731
732 static void r600_blitter_save_states(struct pipe_context *ctx)
733 {
734 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
735
736 util_blitter_save_blend(rctx->blitter, rctx->states[R600_PIPE_STATE_BLEND]);
737 util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->states[R600_PIPE_STATE_DSA]);
738 if (rctx->states[R600_PIPE_STATE_STENCIL_REF]) {
739 util_blitter_save_stencil_ref(rctx->blitter, &rctx->stencil_ref);
740 }
741 util_blitter_save_rasterizer(rctx->blitter, rctx->states[R600_PIPE_STATE_RASTERIZER]);
742 util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader);
743 util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader);
744 util_blitter_save_vertex_elements(rctx->blitter, rctx->vertex_elements);
745 if (rctx->states[R600_PIPE_STATE_VIEWPORT]) {
746 util_blitter_save_viewport(rctx->blitter, &rctx->viewport);
747 }
748 if (rctx->states[R600_PIPE_STATE_CLIP]) {
749 util_blitter_save_clip(rctx->blitter, &rctx->clip);
750 }
751 util_blitter_save_vertex_buffers(rctx->blitter, rctx->nvertex_buffer, rctx->vertex_buffer);
752
753 rctx->vertex_elements = NULL;
754
755 /* TODO queries */
756 }
757
758 int r600_blit_uncompress_depth2(struct pipe_context *ctx, struct r600_resource_texture *texture)
759 {
760 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
761 struct pipe_framebuffer_state fb = *rctx->pframebuffer;
762 struct pipe_surface *zsurf, *cbsurf;
763 int level = 0;
764 float depth = 1.0f;
765
766 r600_context_queries_suspend(&rctx->ctx);
767 for (int i = 0; i < fb.nr_cbufs; i++) {
768 fb.cbufs[i] = NULL;
769 pipe_surface_reference(&fb.cbufs[i], rctx->pframebuffer->cbufs[i]);
770 }
771 fb.zsbuf = NULL;
772 pipe_surface_reference(&fb.zsbuf, rctx->pframebuffer->zsbuf);
773
774 zsurf = ctx->screen->get_tex_surface(ctx->screen, &texture->resource.base.b, 0, level, 0,
775 PIPE_BIND_DEPTH_STENCIL);
776
777 cbsurf = ctx->screen->get_tex_surface(ctx->screen, texture->flushed_depth_texture, 0, level, 0,
778 PIPE_BIND_RENDER_TARGET);
779
780 r600_blitter_save_states(ctx);
781 util_blitter_save_framebuffer(rctx->blitter, &fb);
782
783 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
784 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
785 depth = 0.0f;
786
787 util_blitter_custom_depth_stencil(rctx->blitter, zsurf, cbsurf, rctx->custom_dsa_flush, depth);
788
789 pipe_surface_reference(&zsurf, NULL);
790 pipe_surface_reference(&cbsurf, NULL);
791 for (int i = 0; i < fb.nr_cbufs; i++) {
792 pipe_surface_reference(&fb.cbufs[i], NULL);
793 }
794 pipe_surface_reference(&fb.zsbuf, NULL);
795 r600_context_queries_resume(&rctx->ctx);
796
797 return 0;
798 }
799
800 static void r600_clear(struct pipe_context *ctx, unsigned buffers,
801 const float *rgba, double depth, unsigned stencil)
802 {
803 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
804 struct pipe_framebuffer_state *fb = &rctx->framebuffer;
805
806 r600_context_queries_suspend(&rctx->ctx);
807 r600_blitter_save_states(ctx);
808 util_blitter_clear(rctx->blitter, fb->width, fb->height,
809 fb->nr_cbufs, buffers, rgba, depth,
810 stencil);
811 r600_context_queries_resume(&rctx->ctx);
812 }
813
814 static void r600_clear_render_target(struct pipe_context *ctx,
815 struct pipe_surface *dst,
816 const float *rgba,
817 unsigned dstx, unsigned dsty,
818 unsigned width, unsigned height)
819 {
820 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
821 struct pipe_framebuffer_state *fb = &rctx->framebuffer;
822
823 r600_context_queries_suspend(&rctx->ctx);
824 util_blitter_save_framebuffer(rctx->blitter, fb);
825 util_blitter_clear_render_target(rctx->blitter, dst, rgba,
826 dstx, dsty, width, height);
827 r600_context_queries_resume(&rctx->ctx);
828 }
829
830 static void r600_clear_depth_stencil(struct pipe_context *ctx,
831 struct pipe_surface *dst,
832 unsigned clear_flags,
833 double depth,
834 unsigned stencil,
835 unsigned dstx, unsigned dsty,
836 unsigned width, unsigned height)
837 {
838 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
839 struct pipe_framebuffer_state *fb = &rctx->framebuffer;
840
841 r600_context_queries_suspend(&rctx->ctx);
842 util_blitter_save_framebuffer(rctx->blitter, fb);
843 util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil,
844 dstx, dsty, width, height);
845 r600_context_queries_resume(&rctx->ctx);
846 }
847
848
849 static void r600_resource_copy_region(struct pipe_context *ctx,
850 struct pipe_resource *dst,
851 struct pipe_subresource subdst,
852 unsigned dstx, unsigned dsty, unsigned dstz,
853 struct pipe_resource *src,
854 struct pipe_subresource subsrc,
855 unsigned srcx, unsigned srcy, unsigned srcz,
856 unsigned width, unsigned height)
857 {
858 util_resource_copy_region(ctx, dst, subdst, dstx, dsty, dstz,
859 src, subsrc, srcx, srcy, srcz, width, height);
860 }
861
862 static void r600_init_blit_functions2(struct r600_pipe_context *rctx)
863 {
864 rctx->context.clear = r600_clear;
865 rctx->context.clear_render_target = r600_clear_render_target;
866 rctx->context.clear_depth_stencil = r600_clear_depth_stencil;
867 rctx->context.resource_copy_region = r600_resource_copy_region;
868 }
869
870 static void r600_init_context_resource_functions2(struct r600_pipe_context *r600)
871 {
872 r600->context.get_transfer = u_get_transfer_vtbl;
873 r600->context.transfer_map = u_transfer_map_vtbl;
874 r600->context.transfer_flush_region = u_transfer_flush_region_vtbl;
875 r600->context.transfer_unmap = u_transfer_unmap_vtbl;
876 r600->context.transfer_destroy = u_transfer_destroy_vtbl;
877 r600->context.transfer_inline_write = u_transfer_inline_write_vtbl;
878 r600->context.is_resource_referenced = u_is_resource_referenced_vtbl;
879 }
880
881 static void r600_set_blend_color(struct pipe_context *ctx,
882 const struct pipe_blend_color *state)
883 {
884 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
885 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
886
887 if (rstate == NULL)
888 return;
889
890 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
891 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
892 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
893 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
894 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
895 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
896 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
897 r600_context_pipe_state_set(&rctx->ctx, rstate);
898 }
899
900 static void *r600_create_blend_state(struct pipe_context *ctx,
901 const struct pipe_blend_state *state)
902 {
903 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
904 struct r600_pipe_state *rstate;
905 u32 color_control, target_mask;
906
907 if (blend == NULL) {
908 return NULL;
909 }
910 rstate = &blend->rstate;
911
912 rstate->id = R600_PIPE_STATE_BLEND;
913
914 target_mask = 0;
915 color_control = S_028808_PER_MRT_BLEND(1);
916 if (state->logicop_enable) {
917 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
918 } else {
919 color_control |= (0xcc << 16);
920 }
921 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
922 if (state->independent_blend_enable) {
923 for (int i = 0; i < 8; i++) {
924 if (state->rt[i].blend_enable) {
925 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
926 }
927 target_mask |= (state->rt[i].colormask << (4 * i));
928 }
929 } else {
930 for (int i = 0; i < 8; i++) {
931 if (state->rt[0].blend_enable) {
932 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
933 }
934 target_mask |= (state->rt[0].colormask << (4 * i));
935 }
936 }
937 blend->cb_target_mask = target_mask;
938 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
939 color_control, 0xFFFFFFFF, NULL);
940
941 for (int i = 0; i < 8; i++) {
942 unsigned eqRGB = state->rt[i].rgb_func;
943 unsigned srcRGB = state->rt[i].rgb_src_factor;
944 unsigned dstRGB = state->rt[i].rgb_dst_factor;
945
946 unsigned eqA = state->rt[i].alpha_func;
947 unsigned srcA = state->rt[i].alpha_src_factor;
948 unsigned dstA = state->rt[i].alpha_dst_factor;
949 uint32_t bc = 0;
950
951 if (!state->rt[i].blend_enable)
952 continue;
953
954 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
955 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
956 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
957
958 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
959 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
960 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
961 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
962 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
963 }
964
965 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
966 if (i == 0) {
967 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
968 }
969 }
970 return rstate;
971 }
972
973 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
974 {
975 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
976 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
977 struct r600_pipe_state *rstate;
978
979 if (state == NULL)
980 return;
981 rstate = &blend->rstate;
982 rctx->states[rstate->id] = rstate;
983 rctx->cb_target_mask = blend->cb_target_mask;
984 r600_context_pipe_state_set(&rctx->ctx, rstate);
985 }
986
987 static void *r600_create_dsa_state(struct pipe_context *ctx,
988 const struct pipe_depth_stencil_alpha_state *state)
989 {
990 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
991 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
992 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
993
994 if (rstate == NULL) {
995 return NULL;
996 }
997
998 rstate->id = R600_PIPE_STATE_DSA;
999 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
1000 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
1001 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
1002 * be set if shader use texkill instruction
1003 */
1004 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1005 stencil_ref_mask = 0;
1006 stencil_ref_mask_bf = 0;
1007 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1008 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1009 S_028800_ZFUNC(state->depth.func);
1010
1011 /* stencil */
1012 if (state->stencil[0].enabled) {
1013 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1014 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
1015 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
1016 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
1017 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
1018
1019
1020 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
1021 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
1022 if (state->stencil[1].enabled) {
1023 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1024 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
1025 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
1026 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
1027 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
1028 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
1029 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
1030 }
1031 }
1032
1033 /* alpha */
1034 alpha_test_control = 0;
1035 alpha_ref = 0;
1036 if (state->alpha.enabled) {
1037 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
1038 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
1039 alpha_ref = fui(state->alpha.ref_value);
1040 }
1041
1042 /* misc */
1043 db_render_control = 0;
1044 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
1045 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1046 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1047 /* TODO db_render_override depends on query */
1048 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
1049 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
1050 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
1051 r600_pipe_state_add_reg(rstate,
1052 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
1053 0xFFFFFFFF & C_028430_STENCILREF, NULL);
1054 r600_pipe_state_add_reg(rstate,
1055 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
1056 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
1057 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
1058 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
1059 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
1060 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1061 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
1062 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
1063 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
1064 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
1065 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
1066 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
1067 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
1068
1069 return rstate;
1070 }
1071
1072 static void *r600_create_rs_state(struct pipe_context *ctx,
1073 const struct pipe_rasterizer_state *state)
1074 {
1075 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
1076 struct r600_pipe_state *rstate;
1077 unsigned tmp;
1078 unsigned prov_vtx = 1, polygon_dual_mode;
1079
1080 if (rs == NULL) {
1081 return NULL;
1082 }
1083
1084 rstate = &rs->rstate;
1085 rs->flatshade = state->flatshade;
1086 rs->sprite_coord_enable = state->sprite_coord_enable;
1087
1088 /* offset */
1089 rs->offset_units = state->offset_units;
1090 rs->offset_scale = state->offset_scale * 12.0f;
1091
1092 rstate->id = R600_PIPE_STATE_RASTERIZER;
1093 if (state->flatshade_first)
1094 prov_vtx = 0;
1095 tmp = 0x00000001;
1096 if (state->sprite_coord_enable) {
1097 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
1098 S_0286D4_PNT_SPRITE_OVRD_X(2) |
1099 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
1100 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
1101 S_0286D4_PNT_SPRITE_OVRD_W(1);
1102 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
1103 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
1104 }
1105 }
1106 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
1107
1108 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
1109 state->fill_back != PIPE_POLYGON_MODE_FILL);
1110 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
1111 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
1112 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
1113 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
1114 S_028814_FACE(!state->front_ccw) |
1115 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
1116 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
1117 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
1118 S_028814_POLY_MODE(polygon_dual_mode) |
1119 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
1120 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
1121 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
1122 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
1123 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
1124 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1125 /* point size 12.4 fixed point */
1126 tmp = (unsigned)(state->point_size * 8.0);
1127 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
1128 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
1129 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, 0x00000008, 0xFFFFFFFF, NULL);
1130 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
1131 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1132 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
1133 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
1134 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
1135 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
1136 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
1137 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
1138 return rstate;
1139 }
1140
1141 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
1142 {
1143 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
1144 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1145
1146 if (state == NULL)
1147 return;
1148
1149 rctx->flatshade = rs->flatshade;
1150 rctx->sprite_coord_enable = rs->sprite_coord_enable;
1151 rctx->rasterizer = rs;
1152
1153 rctx->states[rs->rstate.id] = &rs->rstate;
1154 r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
1155 }
1156
1157 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
1158 {
1159 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1160 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
1161
1162 if (rctx->rasterizer == rs) {
1163 rctx->rasterizer = NULL;
1164 }
1165 if (rctx->states[rs->rstate.id] == &rs->rstate) {
1166 rctx->states[rs->rstate.id] = NULL;
1167 }
1168 free(rs);
1169 }
1170
1171 static void *r600_create_sampler_state(struct pipe_context *ctx,
1172 const struct pipe_sampler_state *state)
1173 {
1174 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1175 union util_color uc;
1176
1177 if (rstate == NULL) {
1178 return NULL;
1179 }
1180
1181 rstate->id = R600_PIPE_STATE_SAMPLER;
1182 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1183 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
1184 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1185 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1186 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1187 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
1188 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
1189 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1190 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1191 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
1192 /* FIXME LOD it depends on texture base level ... */
1193 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
1194 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1195 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1196 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
1197 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
1198 if (uc.ui) {
1199 r600_pipe_state_add_reg(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
1200 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
1201 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
1202 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
1203 }
1204 return rstate;
1205 }
1206
1207 static void *r600_create_vertex_elements(struct pipe_context *ctx,
1208 unsigned count,
1209 const struct pipe_vertex_element *elements)
1210 {
1211 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
1212
1213 assert(count < 32);
1214 v->count = count;
1215 v->refcount = 1;
1216 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
1217 return v;
1218 }
1219
1220 static void r600_sampler_view_destroy(struct pipe_context *ctx,
1221 struct pipe_sampler_view *state)
1222 {
1223 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
1224
1225 pipe_resource_reference(&state->texture, NULL);
1226 FREE(resource);
1227 }
1228
1229 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
1230 struct pipe_resource *texture,
1231 const struct pipe_sampler_view *state)
1232 {
1233 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
1234 struct r600_pipe_state *rstate;
1235 const struct util_format_description *desc;
1236 struct r600_resource_texture *tmp;
1237 struct r600_resource *rbuffer;
1238 unsigned format;
1239 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1240 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1241 struct radeon_ws_bo *bo[2];
1242
1243 if (resource == NULL)
1244 return NULL;
1245 rstate = &resource->state;
1246
1247 /* initialize base object */
1248 resource->base = *state;
1249 resource->base.texture = NULL;
1250 pipe_reference(NULL, &texture->reference);
1251 resource->base.texture = texture;
1252 resource->base.reference.count = 1;
1253 resource->base.context = ctx;
1254
1255 swizzle[0] = state->swizzle_r;
1256 swizzle[1] = state->swizzle_g;
1257 swizzle[2] = state->swizzle_b;
1258 swizzle[3] = state->swizzle_a;
1259 format = r600_translate_texformat(texture->format,
1260 swizzle,
1261 &word4, &yuv_format);
1262 if (format == ~0) {
1263 format = 0;
1264 }
1265 desc = util_format_description(texture->format);
1266 if (desc == NULL) {
1267 R600_ERR("unknow format %d\n", texture->format);
1268 }
1269 tmp = (struct r600_resource_texture*)texture;
1270 rbuffer = &tmp->resource;
1271 bo[0] = rbuffer->bo;
1272 bo[1] = rbuffer->bo;
1273 /* FIXME depth texture decompression */
1274 if (tmp->depth) {
1275 r600_texture_depth_flush(ctx, texture);
1276 tmp = (struct r600_resource_texture*)texture;
1277 rbuffer = &tmp->flushed_depth_texture->resource;
1278 bo[0] = rbuffer->bo;
1279 bo[1] = rbuffer->bo;
1280 }
1281 pitch = align(tmp->pitch[0] / tmp->bpt, 8);
1282
1283 /* FIXME properly handle first level != 0 */
1284 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
1285 S_038000_DIM(r600_tex_dim(texture->target)) |
1286 S_038000_TILE_MODE(array_mode) |
1287 S_038000_TILE_TYPE(tile_type) |
1288 S_038000_PITCH((pitch / 8) - 1) |
1289 S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
1290 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
1291 S_038004_TEX_HEIGHT(texture->height0 - 1) |
1292 S_038004_TEX_DEPTH(texture->depth0 - 1) |
1293 S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
1294 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
1295 tmp->offset[0] >> 8, 0xFFFFFFFF, bo[0]);
1296 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
1297 tmp->offset[1] >> 8, 0xFFFFFFFF, bo[1]);
1298 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
1299 word4 | S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
1300 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
1301 S_038010_REQUEST_SIZE(1) |
1302 S_038010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
1303 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
1304 S_038014_LAST_LEVEL(state->last_level) |
1305 S_038014_BASE_ARRAY(0) |
1306 S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL);
1307 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
1308 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
1309
1310 return &resource->base;
1311 }
1312
1313 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1314 struct pipe_sampler_view **views)
1315 {
1316 /* TODO */
1317 assert(1);
1318 }
1319
1320 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1321 struct pipe_sampler_view **views)
1322 {
1323 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1324 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1325
1326 for (int i = 0; i < count; i++) {
1327 if (resource[i]) {
1328 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
1329 }
1330 }
1331 }
1332
1333 static void r600_bind_state(struct pipe_context *ctx, void *state)
1334 {
1335 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1336 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
1337
1338 if (state == NULL)
1339 return;
1340 rctx->states[rstate->id] = rstate;
1341 r600_context_pipe_state_set(&rctx->ctx, rstate);
1342 }
1343
1344 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1345 {
1346 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1347 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1348
1349 for (int i = 0; i < count; i++) {
1350 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
1351 }
1352 }
1353
1354 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1355 {
1356 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1357 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1358
1359 /* TODO implement */
1360 for (int i = 0; i < count; i++) {
1361 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
1362 }
1363 }
1364
1365 static void r600_delete_state(struct pipe_context *ctx, void *state)
1366 {
1367 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1368 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
1369
1370 if (rctx->states[rstate->id] == rstate) {
1371 rctx->states[rstate->id] = NULL;
1372 }
1373 for (int i = 0; i < rstate->nregs; i++) {
1374 radeon_ws_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
1375 }
1376 free(rstate);
1377 }
1378
1379 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
1380 {
1381 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
1382
1383 if (v == NULL)
1384 return;
1385 if (--v->refcount)
1386 return;
1387 free(v);
1388 }
1389
1390 static void r600_set_clip_state(struct pipe_context *ctx,
1391 const struct pipe_clip_state *state)
1392 {
1393 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1394 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1395
1396 if (rstate == NULL)
1397 return;
1398
1399 rctx->clip = *state;
1400 rstate->id = R600_PIPE_STATE_CLIP;
1401 for (int i = 0; i < state->nr; i++) {
1402 r600_pipe_state_add_reg(rstate,
1403 R_028E20_PA_CL_UCP0_X + i * 4,
1404 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
1405 r600_pipe_state_add_reg(rstate,
1406 R_028E24_PA_CL_UCP0_Y + i * 4,
1407 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
1408 r600_pipe_state_add_reg(rstate,
1409 R_028E28_PA_CL_UCP0_Z + i * 4,
1410 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
1411 r600_pipe_state_add_reg(rstate,
1412 R_028E2C_PA_CL_UCP0_W + i * 4,
1413 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
1414 }
1415 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
1416 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
1417 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
1418 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
1419
1420 free(rctx->states[R600_PIPE_STATE_CLIP]);
1421 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1422 r600_context_pipe_state_set(&rctx->ctx, rstate);
1423 }
1424
1425 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
1426 {
1427 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1428 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
1429
1430 r600_delete_vertex_element(ctx, rctx->vertex_elements);
1431 rctx->vertex_elements = v;
1432 if (v) {
1433 v->refcount++;
1434 // rctx->vs_rebuild = TRUE;
1435 }
1436 }
1437
1438 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1439 const struct pipe_poly_stipple *state)
1440 {
1441 }
1442
1443 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1444 {
1445 }
1446
1447 static void r600_set_scissor_state(struct pipe_context *ctx,
1448 const struct pipe_scissor_state *state)
1449 {
1450 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1451 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1452 u32 tl, br;
1453
1454 if (rstate == NULL)
1455 return;
1456
1457 rstate->id = R600_PIPE_STATE_SCISSOR;
1458 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1459 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1460 r600_pipe_state_add_reg(rstate,
1461 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1462 0xFFFFFFFF, NULL);
1463 r600_pipe_state_add_reg(rstate,
1464 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1465 0xFFFFFFFF, NULL);
1466 r600_pipe_state_add_reg(rstate,
1467 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1468 0xFFFFFFFF, NULL);
1469 r600_pipe_state_add_reg(rstate,
1470 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1471 0xFFFFFFFF, NULL);
1472 r600_pipe_state_add_reg(rstate,
1473 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1474 0xFFFFFFFF, NULL);
1475 r600_pipe_state_add_reg(rstate,
1476 R_028214_PA_SC_CLIPRECT_0_BR, br,
1477 0xFFFFFFFF, NULL);
1478 r600_pipe_state_add_reg(rstate,
1479 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1480 0xFFFFFFFF, NULL);
1481 r600_pipe_state_add_reg(rstate,
1482 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1483 0xFFFFFFFF, NULL);
1484 r600_pipe_state_add_reg(rstate,
1485 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1486 0xFFFFFFFF, NULL);
1487 r600_pipe_state_add_reg(rstate,
1488 R_028224_PA_SC_CLIPRECT_2_BR, br,
1489 0xFFFFFFFF, NULL);
1490 r600_pipe_state_add_reg(rstate,
1491 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1492 0xFFFFFFFF, NULL);
1493 r600_pipe_state_add_reg(rstate,
1494 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1495 0xFFFFFFFF, NULL);
1496 r600_pipe_state_add_reg(rstate,
1497 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1498 0xFFFFFFFF, NULL);
1499 r600_pipe_state_add_reg(rstate,
1500 R_02820C_PA_SC_CLIPRECT_RULE, 0x0000FFFF,
1501 0xFFFFFFFF, NULL);
1502 if (rctx->family >= CHIP_RV770) {
1503 r600_pipe_state_add_reg(rstate,
1504 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1505 0xFFFFFFFF, NULL);
1506 }
1507
1508 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1509 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1510 r600_context_pipe_state_set(&rctx->ctx, rstate);
1511 }
1512
1513 static void r600_set_stencil_ref(struct pipe_context *ctx,
1514 const struct pipe_stencil_ref *state)
1515 {
1516 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1517 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1518 u32 tmp;
1519
1520 if (rstate == NULL)
1521 return;
1522
1523 rctx->stencil_ref = *state;
1524 rstate->id = R600_PIPE_STATE_STENCIL_REF;
1525 tmp = S_028430_STENCILREF(state->ref_value[0]);
1526 r600_pipe_state_add_reg(rstate,
1527 R_028430_DB_STENCILREFMASK, tmp,
1528 ~C_028430_STENCILREF, NULL);
1529 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
1530 r600_pipe_state_add_reg(rstate,
1531 R_028434_DB_STENCILREFMASK_BF, tmp,
1532 ~C_028434_STENCILREF_BF, NULL);
1533
1534 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
1535 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
1536 r600_context_pipe_state_set(&rctx->ctx, rstate);
1537 }
1538
1539 static void r600_set_viewport_state(struct pipe_context *ctx,
1540 const struct pipe_viewport_state *state)
1541 {
1542 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1543 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1544
1545 if (rstate == NULL)
1546 return;
1547
1548 rctx->viewport = *state;
1549 rstate->id = R600_PIPE_STATE_VIEWPORT;
1550 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
1551 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
1552 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
1553 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
1554 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
1555 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
1556 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
1557 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
1558 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
1559
1560 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1561 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1562 r600_context_pipe_state_set(&rctx->ctx, rstate);
1563 }
1564
1565 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1566 const struct pipe_framebuffer_state *state, int cb)
1567 {
1568 struct r600_resource_texture *rtex;
1569 struct r600_resource *rbuffer;
1570 unsigned level = state->cbufs[cb]->level;
1571 unsigned pitch, slice;
1572 unsigned color_info;
1573 unsigned format, swap, ntype;
1574 const struct util_format_description *desc;
1575 struct radeon_ws_bo *bo[3];
1576
1577 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1578 rbuffer = &rtex->resource;
1579 bo[0] = rbuffer->bo;
1580 bo[1] = rbuffer->bo;
1581 bo[2] = rbuffer->bo;
1582
1583 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
1584 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
1585 ntype = 0;
1586 desc = util_format_description(rtex->resource.base.b.format);
1587 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1588 ntype = V_0280A0_NUMBER_SRGB;
1589
1590 format = r600_translate_colorformat(rtex->resource.base.b.format);
1591 swap = r600_translate_colorswap(rtex->resource.base.b.format);
1592 color_info = S_0280A0_FORMAT(format) |
1593 S_0280A0_COMP_SWAP(swap) |
1594 S_0280A0_BLEND_CLAMP(1) |
1595 S_0280A0_NUMBER_TYPE(ntype);
1596 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1597 color_info |= S_0280A0_SOURCE_FORMAT(1);
1598
1599 r600_pipe_state_add_reg(rstate,
1600 R_028040_CB_COLOR0_BASE + cb * 4,
1601 state->cbufs[cb]->offset >> 8, 0xFFFFFFFF, bo[0]);
1602 r600_pipe_state_add_reg(rstate,
1603 R_0280A0_CB_COLOR0_INFO + cb * 4,
1604 color_info, 0xFFFFFFFF, bo[0]);
1605 r600_pipe_state_add_reg(rstate,
1606 R_028060_CB_COLOR0_SIZE + cb * 4,
1607 S_028060_PITCH_TILE_MAX(pitch) |
1608 S_028060_SLICE_TILE_MAX(slice),
1609 0xFFFFFFFF, NULL);
1610 r600_pipe_state_add_reg(rstate,
1611 R_028080_CB_COLOR0_VIEW + cb * 4,
1612 0x00000000, 0xFFFFFFFF, NULL);
1613 r600_pipe_state_add_reg(rstate,
1614 R_0280E0_CB_COLOR0_FRAG + cb * 4,
1615 0x00000000, 0xFFFFFFFF, bo[1]);
1616 r600_pipe_state_add_reg(rstate,
1617 R_0280C0_CB_COLOR0_TILE + cb * 4,
1618 0x00000000, 0xFFFFFFFF, bo[2]);
1619 r600_pipe_state_add_reg(rstate,
1620 R_028100_CB_COLOR0_MASK + cb * 4,
1621 0x00000000, 0xFFFFFFFF, NULL);
1622 }
1623
1624 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1625 const struct pipe_framebuffer_state *state)
1626 {
1627 struct r600_resource_texture *rtex;
1628 struct r600_resource *rbuffer;
1629 unsigned level;
1630 unsigned pitch, slice, format;
1631
1632 if (state->zsbuf == NULL)
1633 return;
1634
1635 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1636 rtex->tiled = 1;
1637 rtex->array_mode = 2;
1638 rtex->tile_type = 1;
1639 rtex->depth = 1;
1640 rbuffer = &rtex->resource;
1641
1642 level = state->zsbuf->level;
1643 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
1644 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
1645 format = r600_translate_dbformat(state->zsbuf->texture->format);
1646
1647 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
1648 state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
1649 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1650 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1651 0xFFFFFFFF, NULL);
1652 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
1653 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
1654 S_028010_ARRAY_MODE(rtex->array_mode) | S_028010_FORMAT(format),
1655 0xFFFFFFFF, rbuffer->bo);
1656 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1657 (state->zsbuf->height / 8) - 1, 0xFFFFFFFF, NULL);
1658 }
1659
1660 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1661 const struct pipe_framebuffer_state *state)
1662 {
1663 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1664 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1665 u32 shader_mask, tl, br, shader_control, target_mask;
1666
1667 if (rstate == NULL)
1668 return;
1669
1670 /* unreference old buffer and reference new one */
1671 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1672 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
1673 pipe_surface_reference(&rctx->framebuffer.cbufs[i], NULL);
1674 }
1675 for (int i = 0; i < state->nr_cbufs; i++) {
1676 pipe_surface_reference(&rctx->framebuffer.cbufs[i], state->cbufs[i]);
1677 }
1678 pipe_surface_reference(&rctx->framebuffer.zsbuf, state->zsbuf);
1679 rctx->framebuffer = *state;
1680 rctx->pframebuffer = &rctx->framebuffer;
1681
1682 /* build states */
1683 for (int i = 0; i < state->nr_cbufs; i++) {
1684 r600_cb(rctx, rstate, state, i);
1685 }
1686 if (state->zsbuf) {
1687 r600_db(rctx, rstate, state);
1688 }
1689
1690 target_mask = 0x00000000;
1691 target_mask = 0xFFFFFFFF;
1692 shader_mask = 0;
1693 shader_control = 0;
1694 for (int i = 0; i < state->nr_cbufs; i++) {
1695 target_mask ^= 0xf << (i * 4);
1696 shader_mask |= 0xf << (i * 4);
1697 shader_control |= 1 << i;
1698 }
1699 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1700 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1701
1702 r600_pipe_state_add_reg(rstate,
1703 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1704 0xFFFFFFFF, NULL);
1705 r600_pipe_state_add_reg(rstate,
1706 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1707 0xFFFFFFFF, NULL);
1708 r600_pipe_state_add_reg(rstate,
1709 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1710 0xFFFFFFFF, NULL);
1711 r600_pipe_state_add_reg(rstate,
1712 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1713 0xFFFFFFFF, NULL);
1714
1715 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1716 shader_control, 0xFFFFFFFF, NULL);
1717 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1718 0x00000000, target_mask, NULL);
1719 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1720 shader_mask, 0xFFFFFFFF, NULL);
1721 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1722 0x00000000, 0xFFFFFFFF, NULL);
1723 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1724 0x00000000, 0xFFFFFFFF, NULL);
1725 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1726 0x00000000, 0xFFFFFFFF, NULL);
1727 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1728 0x01000000, 0xFFFFFFFF, NULL);
1729 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1730 0x00000000, 0xFFFFFFFF, NULL);
1731 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1732 0x000000FF, 0xFFFFFFFF, NULL);
1733 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1734 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1735 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1736 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1737
1738 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1739 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1740 r600_context_pipe_state_set(&rctx->ctx, rstate);
1741 }
1742
1743 static void r600_set_index_buffer(struct pipe_context *ctx,
1744 const struct pipe_index_buffer *ib)
1745 {
1746 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1747
1748 if (ib) {
1749 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
1750 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
1751 } else {
1752 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
1753 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
1754 }
1755
1756 /* TODO make this more like a state */
1757 }
1758
1759 static void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
1760 const struct pipe_vertex_buffer *buffers)
1761 {
1762 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1763
1764 for (int i = 0; i < rctx->nvertex_buffer; i++) {
1765 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
1766 }
1767 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
1768 for (int i = 0; i < count; i++) {
1769 rctx->vertex_buffer[i].buffer = NULL;
1770 if (r600_buffer_is_user_buffer(buffers[i].buffer))
1771 rctx->any_user_vbs = TRUE;
1772 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
1773 }
1774 rctx->nvertex_buffer = count;
1775 }
1776
1777 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
1778 struct pipe_resource *buffer)
1779 {
1780 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1781 struct r600_pipe_state *rstate;
1782 struct pipe_transfer *transfer;
1783 unsigned *nconst = NULL;
1784 u32 *ptr, offset;
1785
1786 switch (shader) {
1787 case PIPE_SHADER_VERTEX:
1788 rstate = rctx->vs_const;
1789 nconst = &rctx->vs_nconst;
1790 offset = R_030000_SQ_ALU_CONSTANT0_0 + 0x1000;
1791 break;
1792 case PIPE_SHADER_FRAGMENT:
1793 rstate = rctx->ps_const;
1794 nconst = &rctx->ps_nconst;
1795 offset = R_030000_SQ_ALU_CONSTANT0_0;
1796 break;
1797 default:
1798 R600_ERR("unsupported %d\n", shader);
1799 return;
1800 }
1801 if (buffer && buffer->width0 > 0) {
1802 *nconst = buffer->width0 / 16;
1803 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
1804 if (ptr == NULL)
1805 return;
1806 for (int i = 0; i < *nconst; i++, offset += 0x10) {
1807 rstate[i].nregs = 0;
1808 r600_pipe_state_add_reg(&rstate[i], offset + 0x0, ptr[i * 4 + 0], 0xFFFFFFFF, NULL);
1809 r600_pipe_state_add_reg(&rstate[i], offset + 0x4, ptr[i * 4 + 1], 0xFFFFFFFF, NULL);
1810 r600_pipe_state_add_reg(&rstate[i], offset + 0x8, ptr[i * 4 + 2], 0xFFFFFFFF, NULL);
1811 r600_pipe_state_add_reg(&rstate[i], offset + 0xC, ptr[i * 4 + 3], 0xFFFFFFFF, NULL);
1812 r600_context_pipe_state_set(&rctx->ctx, &rstate[i]);
1813 }
1814 pipe_buffer_unmap(ctx, buffer, transfer);
1815 }
1816 }
1817
1818 static void *r600_create_shader_state(struct pipe_context *ctx,
1819 const struct pipe_shader_state *state)
1820 {
1821 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
1822 int r;
1823
1824 r = r600_pipe_shader_create2(ctx, shader, state->tokens);
1825 if (r) {
1826 return NULL;
1827 }
1828 return shader;
1829 }
1830
1831 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
1832 {
1833 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1834
1835 /* TODO delete old shader */
1836 rctx->ps_shader = (struct r600_pipe_shader *)state;
1837 }
1838
1839 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
1840 {
1841 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1842
1843 /* TODO delete old shader */
1844 rctx->vs_shader = (struct r600_pipe_shader *)state;
1845 }
1846
1847 static void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
1848 {
1849 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1850 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1851
1852 if (rctx->ps_shader == shader) {
1853 rctx->ps_shader = NULL;
1854 }
1855 /* TODO proper delete */
1856 free(shader);
1857 }
1858
1859 static void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
1860 {
1861 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1862 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1863
1864 if (rctx->vs_shader == shader) {
1865 rctx->vs_shader = NULL;
1866 }
1867 /* TODO proper delete */
1868 free(shader);
1869 }
1870
1871 static void r600_init_state_functions2(struct r600_pipe_context *rctx)
1872 {
1873 rctx->context.create_blend_state = r600_create_blend_state;
1874 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1875 rctx->context.create_fs_state = r600_create_shader_state;
1876 rctx->context.create_rasterizer_state = r600_create_rs_state;
1877 rctx->context.create_sampler_state = r600_create_sampler_state;
1878 rctx->context.create_sampler_view = r600_create_sampler_view;
1879 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1880 rctx->context.create_vs_state = r600_create_shader_state;
1881 rctx->context.bind_blend_state = r600_bind_blend_state;
1882 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
1883 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
1884 rctx->context.bind_fs_state = r600_bind_ps_shader;
1885 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1886 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1887 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
1888 rctx->context.bind_vs_state = r600_bind_vs_shader;
1889 rctx->context.delete_blend_state = r600_delete_state;
1890 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1891 rctx->context.delete_fs_state = r600_delete_ps_shader;
1892 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1893 rctx->context.delete_sampler_state = r600_delete_state;
1894 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1895 rctx->context.delete_vs_state = r600_delete_vs_shader;
1896 rctx->context.set_blend_color = r600_set_blend_color;
1897 rctx->context.set_clip_state = r600_set_clip_state;
1898 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1899 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
1900 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1901 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1902 rctx->context.set_sample_mask = r600_set_sample_mask;
1903 rctx->context.set_scissor_state = r600_set_scissor_state;
1904 rctx->context.set_stencil_ref = r600_set_stencil_ref;
1905 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1906 rctx->context.set_index_buffer = r600_set_index_buffer;
1907 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
1908 rctx->context.set_viewport_state = r600_set_viewport_state;
1909 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1910 }
1911
1912 static void r600_init_config2(struct r600_pipe_context *rctx)
1913 {
1914 int ps_prio;
1915 int vs_prio;
1916 int gs_prio;
1917 int es_prio;
1918 int num_ps_gprs;
1919 int num_vs_gprs;
1920 int num_gs_gprs;
1921 int num_es_gprs;
1922 int num_temp_gprs;
1923 int num_ps_threads;
1924 int num_vs_threads;
1925 int num_gs_threads;
1926 int num_es_threads;
1927 int num_ps_stack_entries;
1928 int num_vs_stack_entries;
1929 int num_gs_stack_entries;
1930 int num_es_stack_entries;
1931 enum radeon_family family;
1932 struct r600_pipe_state *rstate = &rctx->config;
1933 u32 tmp;
1934
1935 family = r600_get_family(rctx->radeon);
1936 ps_prio = 0;
1937 vs_prio = 1;
1938 gs_prio = 2;
1939 es_prio = 3;
1940 switch (family) {
1941 case CHIP_R600:
1942 num_ps_gprs = 192;
1943 num_vs_gprs = 56;
1944 num_temp_gprs = 4;
1945 num_gs_gprs = 0;
1946 num_es_gprs = 0;
1947 num_ps_threads = 136;
1948 num_vs_threads = 48;
1949 num_gs_threads = 4;
1950 num_es_threads = 4;
1951 num_ps_stack_entries = 128;
1952 num_vs_stack_entries = 128;
1953 num_gs_stack_entries = 0;
1954 num_es_stack_entries = 0;
1955 break;
1956 case CHIP_RV630:
1957 case CHIP_RV635:
1958 num_ps_gprs = 84;
1959 num_vs_gprs = 36;
1960 num_temp_gprs = 4;
1961 num_gs_gprs = 0;
1962 num_es_gprs = 0;
1963 num_ps_threads = 144;
1964 num_vs_threads = 40;
1965 num_gs_threads = 4;
1966 num_es_threads = 4;
1967 num_ps_stack_entries = 40;
1968 num_vs_stack_entries = 40;
1969 num_gs_stack_entries = 32;
1970 num_es_stack_entries = 16;
1971 break;
1972 case CHIP_RV610:
1973 case CHIP_RV620:
1974 case CHIP_RS780:
1975 case CHIP_RS880:
1976 default:
1977 num_ps_gprs = 84;
1978 num_vs_gprs = 36;
1979 num_temp_gprs = 4;
1980 num_gs_gprs = 0;
1981 num_es_gprs = 0;
1982 num_ps_threads = 136;
1983 num_vs_threads = 48;
1984 num_gs_threads = 4;
1985 num_es_threads = 4;
1986 num_ps_stack_entries = 40;
1987 num_vs_stack_entries = 40;
1988 num_gs_stack_entries = 32;
1989 num_es_stack_entries = 16;
1990 break;
1991 case CHIP_RV670:
1992 num_ps_gprs = 144;
1993 num_vs_gprs = 40;
1994 num_temp_gprs = 4;
1995 num_gs_gprs = 0;
1996 num_es_gprs = 0;
1997 num_ps_threads = 136;
1998 num_vs_threads = 48;
1999 num_gs_threads = 4;
2000 num_es_threads = 4;
2001 num_ps_stack_entries = 40;
2002 num_vs_stack_entries = 40;
2003 num_gs_stack_entries = 32;
2004 num_es_stack_entries = 16;
2005 break;
2006 case CHIP_RV770:
2007 num_ps_gprs = 192;
2008 num_vs_gprs = 56;
2009 num_temp_gprs = 4;
2010 num_gs_gprs = 0;
2011 num_es_gprs = 0;
2012 num_ps_threads = 188;
2013 num_vs_threads = 60;
2014 num_gs_threads = 0;
2015 num_es_threads = 0;
2016 num_ps_stack_entries = 256;
2017 num_vs_stack_entries = 256;
2018 num_gs_stack_entries = 0;
2019 num_es_stack_entries = 0;
2020 break;
2021 case CHIP_RV730:
2022 case CHIP_RV740:
2023 num_ps_gprs = 84;
2024 num_vs_gprs = 36;
2025 num_temp_gprs = 4;
2026 num_gs_gprs = 0;
2027 num_es_gprs = 0;
2028 num_ps_threads = 188;
2029 num_vs_threads = 60;
2030 num_gs_threads = 0;
2031 num_es_threads = 0;
2032 num_ps_stack_entries = 128;
2033 num_vs_stack_entries = 128;
2034 num_gs_stack_entries = 0;
2035 num_es_stack_entries = 0;
2036 break;
2037 case CHIP_RV710:
2038 num_ps_gprs = 192;
2039 num_vs_gprs = 56;
2040 num_temp_gprs = 4;
2041 num_gs_gprs = 0;
2042 num_es_gprs = 0;
2043 num_ps_threads = 144;
2044 num_vs_threads = 48;
2045 num_gs_threads = 0;
2046 num_es_threads = 0;
2047 num_ps_stack_entries = 128;
2048 num_vs_stack_entries = 128;
2049 num_gs_stack_entries = 0;
2050 num_es_stack_entries = 0;
2051 break;
2052 }
2053
2054 rstate->id = R600_PIPE_STATE_CONFIG;
2055
2056 /* SQ_CONFIG */
2057 tmp = 0;
2058 switch (family) {
2059 case CHIP_RV610:
2060 case CHIP_RV620:
2061 case CHIP_RS780:
2062 case CHIP_RS880:
2063 case CHIP_RV710:
2064 break;
2065 default:
2066 tmp |= S_008C00_VC_ENABLE(1);
2067 break;
2068 }
2069 tmp |= S_008C00_DX9_CONSTS(1);
2070 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2071 tmp |= S_008C00_PS_PRIO(ps_prio);
2072 tmp |= S_008C00_VS_PRIO(vs_prio);
2073 tmp |= S_008C00_GS_PRIO(gs_prio);
2074 tmp |= S_008C00_ES_PRIO(es_prio);
2075 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
2076
2077 /* SQ_GPR_RESOURCE_MGMT_1 */
2078 tmp = 0;
2079 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2080 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2081 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2082 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
2083
2084 /* SQ_GPR_RESOURCE_MGMT_2 */
2085 tmp = 0;
2086 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
2087 tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
2088 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
2089
2090 /* SQ_THREAD_RESOURCE_MGMT */
2091 tmp = 0;
2092 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
2093 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2094 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2095 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2096 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
2097
2098 /* SQ_STACK_RESOURCE_MGMT_1 */
2099 tmp = 0;
2100 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2101 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2102 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
2103
2104 /* SQ_STACK_RESOURCE_MGMT_2 */
2105 tmp = 0;
2106 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2107 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2108 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
2109
2110 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
2111 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
2112
2113 if (family >= CHIP_RV770) {
2114 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
2115 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
2116 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
2117 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
2118 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
2119 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514000, 0xFFFFFFFF, NULL);
2120 } else {
2121 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
2122 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
2123 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
2124 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
2125 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
2126 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004010, 0xFFFFFFFF, NULL);
2127 }
2128 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
2129 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
2130 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
2131 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
2132 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
2133 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
2134 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
2135 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
2136 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
2137 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
2138 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
2139 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
2140 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
2141 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
2142 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
2143 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
2144 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
2145 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
2146 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
2147 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
2148 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
2149 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
2150 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
2151 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
2152 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
2153 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
2154
2155 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
2156 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
2157 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
2158 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
2159 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
2160 r600_context_pipe_state_set(&rctx->ctx, rstate);
2161 }
2162
2163 static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type)
2164 {
2165 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2166
2167 return (struct pipe_query*)r600_context_query_create(&rctx->ctx, query_type);
2168 }
2169
2170 static void r600_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
2171 {
2172 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2173
2174 r600_context_query_destroy(&rctx->ctx, (struct r600_query *)query);
2175 }
2176
2177 static void r600_begin_query(struct pipe_context *ctx, struct pipe_query *query)
2178 {
2179 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2180 struct r600_query *rquery = (struct r600_query *)query;
2181
2182 rquery->result = 0;
2183 rquery->num_results = 0;
2184 r600_query_begin(&rctx->ctx, (struct r600_query *)query);
2185 }
2186
2187 static void r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
2188 {
2189 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2190
2191 r600_query_end(&rctx->ctx, (struct r600_query *)query);
2192 }
2193
2194 static boolean r600_get_query_result(struct pipe_context *ctx,
2195 struct pipe_query *query,
2196 boolean wait, void *vresult)
2197 {
2198 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2199 struct r600_query *rquery = (struct r600_query *)query;
2200
2201 if (rquery->num_results) {
2202 ctx->flush(ctx, 0, NULL);
2203 }
2204 return r600_context_query_result(&rctx->ctx, (struct r600_query *)query, wait, vresult);
2205 }
2206
2207 static void r600_init_query_functions2(struct r600_pipe_context *rctx)
2208 {
2209 rctx->context.create_query = r600_create_query;
2210 rctx->context.destroy_query = r600_destroy_query;
2211 rctx->context.begin_query = r600_begin_query;
2212 rctx->context.end_query = r600_end_query;
2213 rctx->context.get_query_result = r600_get_query_result;
2214 }
2215
2216 static void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
2217 {
2218 struct pipe_depth_stencil_alpha_state dsa;
2219 struct r600_pipe_state *rstate;
2220 boolean quirk = false;
2221
2222 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2223 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2224 quirk = true;
2225
2226 memset(&dsa, 0, sizeof(dsa));
2227
2228 if (quirk) {
2229 dsa.depth.enabled = 1;
2230 dsa.depth.func = PIPE_FUNC_LEQUAL;
2231 dsa.stencil[0].enabled = 1;
2232 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2233 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2234 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2235 dsa.stencil[0].writemask = 0xff;
2236 }
2237
2238 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2239 r600_pipe_state_add_reg(rstate,
2240 R_02880C_DB_SHADER_CONTROL,
2241 0x0,
2242 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
2243 r600_pipe_state_add_reg(rstate,
2244 R_028D0C_DB_RENDER_CONTROL,
2245 S_028D0C_DEPTH_COPY_ENABLE(1) |
2246 S_028D0C_STENCIL_COPY_ENABLE(1) |
2247 S_028D0C_COPY_CENTROID(1),
2248 S_028D0C_DEPTH_COPY_ENABLE(1) |
2249 S_028D0C_STENCIL_COPY_ENABLE(1) |
2250 S_028D0C_COPY_CENTROID(1), NULL);
2251 return rstate;
2252 }
2253
2254 static struct pipe_context *r600_create_context2(struct pipe_screen *screen, void *priv)
2255 {
2256 struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
2257 struct r600_screen* rscreen = (struct r600_screen *)screen;
2258
2259 if (rctx == NULL)
2260 return NULL;
2261 rctx->context.winsys = rscreen->screen.winsys;
2262 rctx->context.screen = screen;
2263 rctx->context.priv = priv;
2264 rctx->context.destroy = r600_destroy_context;
2265 rctx->context.flush = r600_flush2;
2266
2267 /* Easy accessing of screen/winsys. */
2268 rctx->screen = rscreen;
2269 rctx->radeon = rscreen->radeon;
2270 rctx->family = r600_get_family(rctx->radeon);
2271
2272 r600_init_blit_functions2(rctx);
2273 r600_init_query_functions2(rctx);
2274 r600_init_context_resource_functions2(rctx);
2275
2276 switch (r600_get_family(rctx->radeon)) {
2277 case CHIP_R600:
2278 case CHIP_RV610:
2279 case CHIP_RV630:
2280 case CHIP_RV670:
2281 case CHIP_RV620:
2282 case CHIP_RV635:
2283 case CHIP_RS780:
2284 case CHIP_RS880:
2285 case CHIP_RV770:
2286 case CHIP_RV730:
2287 case CHIP_RV710:
2288 case CHIP_RV740:
2289 rctx->context.draw_vbo = r600_draw_vbo2;
2290 r600_init_state_functions2(rctx);
2291 if (r600_context_init(&rctx->ctx, rctx->radeon)) {
2292 r600_destroy_context(&rctx->context);
2293 return NULL;
2294 }
2295 r600_init_config2(rctx);
2296 break;
2297 case CHIP_CEDAR:
2298 case CHIP_REDWOOD:
2299 case CHIP_JUNIPER:
2300 case CHIP_CYPRESS:
2301 case CHIP_HEMLOCK:
2302 rctx->context.draw_vbo = evergreen_draw;
2303 evergreen_init_state_functions2(rctx);
2304 if (evergreen_context_init(&rctx->ctx, rctx->radeon)) {
2305 r600_destroy_context(&rctx->context);
2306 return NULL;
2307 }
2308 evergreen_init_config2(rctx);
2309 break;
2310 default:
2311 R600_ERR("unsupported family %d\n", r600_get_family(rctx->radeon));
2312 r600_destroy_context(&rctx->context);
2313 return NULL;
2314 }
2315
2316 rctx->upload_ib = u_upload_create(&rctx->context, 32 * 1024, 16,
2317 PIPE_BIND_INDEX_BUFFER);
2318 if (rctx->upload_ib == NULL) {
2319 r600_destroy_context(&rctx->context);
2320 return NULL;
2321 }
2322
2323 rctx->upload_vb = u_upload_create(&rctx->context, 128 * 1024, 16,
2324 PIPE_BIND_VERTEX_BUFFER);
2325 if (rctx->upload_vb == NULL) {
2326 r600_destroy_context(&rctx->context);
2327 return NULL;
2328 }
2329
2330 rctx->blitter = util_blitter_create(&rctx->context);
2331 if (rctx->blitter == NULL) {
2332 FREE(rctx);
2333 return NULL;
2334 }
2335
2336 LIST_INITHEAD(&rctx->query_list);
2337 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
2338
2339 r600_blit_uncompress_depth_ptr = r600_blit_uncompress_depth2;
2340
2341 return &rctx->context;
2342 }
2343
2344 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
2345 {
2346 switch(shader)
2347 {
2348 case PIPE_SHADER_FRAGMENT:
2349 case PIPE_SHADER_VERTEX:
2350 break;
2351 case PIPE_SHADER_GEOMETRY:
2352 /* TODO: support and enable geometry programs */
2353 return 0;
2354 default:
2355 /* TODO: support tessellation on Evergreen */
2356 return 0;
2357 }
2358
2359 /* TODO: all these should be fixed, since r600 surely supports much more! */
2360 switch (param) {
2361 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
2362 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
2363 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
2364 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
2365 return 16384;
2366 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
2367 return 8; /* FIXME */
2368 case PIPE_SHADER_CAP_MAX_INPUTS:
2369 if(shader == PIPE_SHADER_FRAGMENT)
2370 return 10;
2371 else
2372 return 16;
2373 case PIPE_SHADER_CAP_MAX_TEMPS:
2374 return 256; //max native temporaries
2375 case PIPE_SHADER_CAP_MAX_ADDRS:
2376 return 1; //max native address registers/* FIXME Isn't this equal to TEMPS? */
2377 case PIPE_SHADER_CAP_MAX_CONSTS:
2378 return 256; //max native parameters
2379 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
2380 return 1;
2381 case PIPE_SHADER_CAP_MAX_PREDS:
2382 return 0; /* FIXME */
2383 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
2384 return 1;
2385 default:
2386 return 0;
2387 }
2388 }
2389
2390 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
2391 const struct pipe_resource *templ);
2392 struct pipe_resource *r600_user_buffer_create2(struct pipe_screen *screen,
2393 void *ptr, unsigned bytes,
2394 unsigned bind)
2395 {
2396 struct pipe_resource *resource;
2397 struct r600_resource *rresource;
2398 struct pipe_resource desc;
2399 struct radeon *radeon = (struct radeon *)screen->winsys;
2400 void *rptr;
2401
2402 desc.screen = screen;
2403 desc.target = PIPE_BUFFER;
2404 desc.format = PIPE_FORMAT_R8_UNORM;
2405 desc.usage = PIPE_USAGE_IMMUTABLE;
2406 desc.bind = bind;
2407 desc.width0 = bytes;
2408 desc.height0 = 1;
2409 desc.depth0 = 1;
2410 desc.flags = 0;
2411 resource = r600_buffer_create(screen, &desc);
2412 if (resource == NULL) {
2413 return NULL;
2414 }
2415
2416 rresource = (struct r600_resource *)resource;
2417 rptr = radeon_ws_bo_map(radeon, rresource->bo, 0, NULL);
2418 memcpy(rptr, ptr, bytes);
2419 radeon_ws_bo_unmap(radeon, rresource->bo);
2420
2421 return resource;
2422 }
2423
2424 void r600_init_screen_texture_functions(struct pipe_screen *screen);
2425 struct pipe_screen *r600_screen_create2(struct radeon *radeon)
2426 {
2427 struct r600_screen *rscreen;
2428
2429 rscreen = CALLOC_STRUCT(r600_screen);
2430 if (rscreen == NULL) {
2431 return NULL;
2432 }
2433
2434 rscreen->radeon = radeon;
2435 rscreen->screen.winsys = (struct pipe_winsys*)radeon;
2436 rscreen->screen.destroy = r600_destroy_screen;
2437 rscreen->screen.get_name = r600_get_name;
2438 rscreen->screen.get_vendor = r600_get_vendor;
2439 rscreen->screen.get_param = r600_get_param;
2440 rscreen->screen.get_shader_param = r600_get_shader_param;
2441 rscreen->screen.get_paramf = r600_get_paramf;
2442 rscreen->screen.is_format_supported = r600_is_format_supported;
2443 rscreen->screen.context_create = r600_create_context2;
2444 r600_init_screen_texture_functions(&rscreen->screen);
2445 r600_init_screen_resource_functions(&rscreen->screen);
2446 // rscreen->screen.user_buffer_create = r600_user_buffer_create2;
2447
2448 return &rscreen->screen;
2449 }
2450
2451 int r600_upload_index_buffer2(struct r600_pipe_context *rctx, struct r600_drawl *draw)
2452 {
2453 struct pipe_resource *upload_buffer = NULL;
2454 unsigned index_offset = draw->index_buffer_offset;
2455 int ret = 0;
2456
2457 if (r600_buffer_is_user_buffer(draw->index_buffer)) {
2458 ret = u_upload_buffer(rctx->upload_ib,
2459 index_offset,
2460 draw->count * draw->index_size,
2461 draw->index_buffer,
2462 &index_offset,
2463 &upload_buffer);
2464 if (ret) {
2465 goto done;
2466 }
2467 draw->index_buffer_offset = index_offset;
2468
2469 /* Transfer ownership. */
2470 pipe_resource_reference(&draw->index_buffer, upload_buffer);
2471 pipe_resource_reference(&upload_buffer, NULL);
2472 }
2473
2474 done:
2475 return ret;
2476 }
2477
2478 int r600_upload_user_buffers2(struct r600_pipe_context *rctx)
2479 {
2480 enum pipe_error ret = PIPE_OK;
2481 int i, nr;
2482
2483 nr = rctx->vertex_elements->count;
2484
2485 for (i = 0; i < nr; i++) {
2486 struct pipe_vertex_buffer *vb =
2487 &rctx->vertex_buffer[rctx->vertex_elements->elements[i].vertex_buffer_index];
2488
2489 if (r600_buffer_is_user_buffer(vb->buffer)) {
2490 struct pipe_resource *upload_buffer = NULL;
2491 unsigned offset = 0; /*vb->buffer_offset * 4;*/
2492 unsigned size = vb->buffer->width0;
2493 unsigned upload_offset;
2494 ret = u_upload_buffer(rctx->upload_vb,
2495 offset, size,
2496 vb->buffer,
2497 &upload_offset, &upload_buffer);
2498 if (ret)
2499 return ret;
2500
2501 pipe_resource_reference(&vb->buffer, NULL);
2502 vb->buffer = upload_buffer;
2503 vb->buffer_offset = upload_offset;
2504 }
2505 }
2506 return ret;
2507 }