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r600g: bring over fix from old path to new path
[mesa.git] / src / gallium / drivers / r600 / r600_state2.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <util/u_upload_mgr.h>
43 #include <util/u_index_modify.h>
44 #include <pipebuffer/pb_buffer.h>
45 #include "r600.h"
46 #include "r600d.h"
47 #include "r700_sq.h"
48 struct radeon_state {
49 unsigned dummy;
50 };
51 #include "r600_resource.h"
52 #include "r600_shader.h"
53 #include "r600_pipe.h"
54 #include "r600_state_inlines.h"
55
56 /* r600_shader.c */
57 static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
58 {
59 struct r600_pipe_state *rstate = &shader->rstate;
60 struct r600_shader *rshader = &shader->shader;
61 unsigned spi_vs_out_id[10];
62 unsigned i, tmp;
63
64 /* clear previous register */
65 rstate->nregs = 0;
66
67 /* so far never got proper semantic id from tgsi */
68 for (i = 0; i < 10; i++) {
69 spi_vs_out_id[i] = 0;
70 }
71 for (i = 0; i < 32; i++) {
72 tmp = i << ((i & 3) * 8);
73 spi_vs_out_id[i / 4] |= tmp;
74 }
75 for (i = 0; i < 10; i++) {
76 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
77 R_028614_SPI_VS_OUT_ID_0 + i * 4,
78 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
79 }
80
81 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
82 R_0286C4_SPI_VS_OUT_CONFIG,
83 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
84 0xFFFFFFFF, NULL);
85 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
86 R_028868_SQ_PGM_RESOURCES_VS,
87 S_028868_NUM_GPRS(rshader->bc.ngpr) |
88 S_028868_STACK_SIZE(rshader->bc.nstack),
89 0xFFFFFFFF, NULL);
90 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
91 R_0288A4_SQ_PGM_RESOURCES_FS,
92 0x00000000, 0xFFFFFFFF, NULL);
93 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
94 R_0288D0_SQ_PGM_CF_OFFSET_VS,
95 0x00000000, 0xFFFFFFFF, NULL);
96 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
97 R_0288DC_SQ_PGM_CF_OFFSET_FS,
98 0x00000000, 0xFFFFFFFF, NULL);
99 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
100 R_028858_SQ_PGM_START_VS,
101 0x00000000, 0xFFFFFFFF, shader->bo);
102 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
103 R_028894_SQ_PGM_START_FS,
104 0x00000000, 0xFFFFFFFF, shader->bo);
105 }
106
107 static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
108 {
109 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
110 struct r600_pipe_state *rstate = &shader->rstate;
111 struct r600_shader *rshader = &shader->shader;
112 unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z;
113 boolean have_pos = FALSE, have_face = FALSE;
114
115 /* clear previous register */
116 rstate->nregs = 0;
117
118 for (i = 0; i < rshader->ninput; i++) {
119 tmp = S_028644_SEMANTIC(i);
120 tmp |= S_028644_SEL_CENTROID(1);
121 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
122 have_pos = TRUE;
123 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
124 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
125 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
126 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
127 }
128 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
129 have_face = TRUE;
130 if (rctx->sprite_coord_enable & (1 << i)) {
131 tmp |= S_028644_PT_SPRITE_TEX(1);
132 }
133 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
134 }
135
136 exports_ps = 0;
137 num_cout = 0;
138 for (i = 0; i < rshader->noutput; i++) {
139 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
140 exports_ps |= 1;
141 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
142 num_cout++;
143 }
144 }
145 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
146 if (!exports_ps) {
147 /* always at least export 1 component per pixel */
148 exports_ps = 2;
149 }
150
151 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
152 S_0286CC_PERSP_GRADIENT_ENA(1);
153 spi_input_z = 0;
154 if (have_pos) {
155 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
156 S_0286CC_BARYC_SAMPLE_CNTL(1);
157 spi_input_z |= 1;
158 }
159 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
160 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286D0_SPI_PS_IN_CONTROL_1, S_0286D0_FRONT_FACE_ENA(have_face), 0xFFFFFFFF, NULL);
161 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
162 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
163 R_028840_SQ_PGM_START_PS,
164 0x00000000, 0xFFFFFFFF, shader->bo);
165 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
166 R_028850_SQ_PGM_RESOURCES_PS,
167 S_028868_NUM_GPRS(rshader->bc.ngpr) |
168 S_028868_STACK_SIZE(rshader->bc.nstack),
169 0xFFFFFFFF, NULL);
170 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
171 R_028854_SQ_PGM_EXPORTS_PS,
172 exports_ps, 0xFFFFFFFF, NULL);
173 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
174 R_0288CC_SQ_PGM_CF_OFFSET_PS,
175 0x00000000, 0xFFFFFFFF, NULL);
176 }
177
178 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
179 {
180 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
181 struct r600_shader *rshader = &shader->shader;
182 void *ptr;
183
184 /* copy new shader */
185 if (shader->bo == NULL) {
186 shader->bo = radeon_ws_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0);
187 if (shader->bo == NULL) {
188 return -ENOMEM;
189 }
190 ptr = radeon_ws_bo_map(rctx->radeon, shader->bo, 0, NULL);
191 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
192 radeon_ws_bo_unmap(rctx->radeon, shader->bo);
193 }
194 /* build state */
195 rshader->flat_shade = rctx->flatshade;
196 switch (rshader->processor_type) {
197 case TGSI_PROCESSOR_VERTEX:
198 if (rshader->family >= CHIP_CEDAR) {
199 evergreen_pipe_shader_vs(ctx, shader);
200 } else {
201 r600_pipe_shader_vs(ctx, shader);
202 }
203 break;
204 case TGSI_PROCESSOR_FRAGMENT:
205 if (rshader->family >= CHIP_CEDAR) {
206 evergreen_pipe_shader_ps(ctx, shader);
207 } else {
208 r600_pipe_shader_ps(ctx, shader);
209 }
210 break;
211 default:
212 return -EINVAL;
213 }
214 r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
215 return 0;
216 }
217
218 static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rshader)
219 {
220 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
221 struct r600_shader *shader = &rshader->shader;
222 const struct util_format_description *desc;
223 enum pipe_format resource_format[160];
224 unsigned i, nresources = 0;
225 struct r600_bc *bc = &shader->bc;
226 struct r600_bc_cf *cf;
227 struct r600_bc_vtx *vtx;
228
229 if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
230 return 0;
231 for (i = 0; i < rctx->vertex_elements->count; i++) {
232 resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
233 }
234 radeon_ws_bo_reference(rctx->radeon, &rshader->bo, NULL);
235 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
236 switch (cf->inst) {
237 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
238 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
239 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
240 desc = util_format_description(resource_format[vtx->buffer_id]);
241 if (desc == NULL) {
242 R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
243 return -EINVAL;
244 }
245 vtx->dst_sel_x = desc->swizzle[0];
246 vtx->dst_sel_y = desc->swizzle[1];
247 vtx->dst_sel_z = desc->swizzle[2];
248 vtx->dst_sel_w = desc->swizzle[3];
249 }
250 break;
251 default:
252 break;
253 }
254 }
255 return r600_bc_build(&shader->bc);
256 }
257
258 int r600_pipe_shader_update2(struct pipe_context *ctx, struct r600_pipe_shader *shader)
259 {
260 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
261 int r;
262
263 if (shader == NULL)
264 return -EINVAL;
265 /* there should be enough input */
266 if (rctx->vertex_elements->count < shader->shader.bc.nresource) {
267 R600_ERR("%d resources provided, expecting %d\n",
268 rctx->vertex_elements->count, shader->shader.bc.nresource);
269 return -EINVAL;
270 }
271 r = r600_shader_update(ctx, shader);
272 if (r)
273 return r;
274 return r600_pipe_shader(ctx, shader);
275 }
276
277 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
278 int r600_pipe_shader_create2(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
279 {
280 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
281 int r;
282
283 //fprintf(stderr, "--------------------------------------------------------------\n");
284 //tgsi_dump(tokens, 0);
285 shader->shader.family = r600_get_family(rctx->radeon);
286 r = r600_shader_from_tgsi(tokens, &shader->shader);
287 if (r) {
288 R600_ERR("translation from TGSI failed !\n");
289 return r;
290 }
291 r = r600_bc_build(&shader->shader.bc);
292 if (r) {
293 R600_ERR("building bytecode failed !\n");
294 return r;
295 }
296 //fprintf(stderr, "______________________________________________________________\n");
297 return 0;
298 }
299 /* r600_shader.c END */
300
301 static const char* r600_get_vendor(struct pipe_screen* pscreen)
302 {
303 return "X.Org";
304 }
305
306 static const char* r600_get_name(struct pipe_screen* pscreen)
307 {
308 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
309 enum radeon_family family = r600_get_family(rscreen->radeon);
310
311 if (family >= CHIP_R600 && family < CHIP_RV770)
312 return "R600 (HD2XXX,HD3XXX)";
313 else
314 return "R700 (HD4XXX)";
315 }
316
317 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
318 {
319 switch (param) {
320 /* Supported features (boolean caps). */
321 case PIPE_CAP_NPOT_TEXTURES:
322 case PIPE_CAP_TWO_SIDED_STENCIL:
323 case PIPE_CAP_GLSL:
324 case PIPE_CAP_DUAL_SOURCE_BLEND:
325 case PIPE_CAP_ANISOTROPIC_FILTER:
326 case PIPE_CAP_POINT_SPRITE:
327 case PIPE_CAP_OCCLUSION_QUERY:
328 case PIPE_CAP_TEXTURE_SHADOW_MAP:
329 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
330 case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
331 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
332 case PIPE_CAP_SM3:
333 case PIPE_CAP_TEXTURE_SWIZZLE:
334 case PIPE_CAP_INDEP_BLEND_ENABLE:
335 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
336 case PIPE_CAP_DEPTH_CLAMP:
337 return 1;
338
339 /* Unsupported features (boolean caps). */
340 case PIPE_CAP_TIMER_QUERY:
341 case PIPE_CAP_STREAM_OUTPUT:
342 case PIPE_CAP_INDEP_BLEND_FUNC: /* FIXME allow this */
343 return 0;
344
345 /* Texturing. */
346 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
347 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
348 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
349 return 14;
350 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
351 /* FIXME allow this once infrastructure is there */
352 return 0;
353 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
354 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
355 return 16;
356
357 /* Render targets. */
358 case PIPE_CAP_MAX_RENDER_TARGETS:
359 /* FIXME some r6xx are buggy and can only do 4 */
360 return 8;
361
362 /* Fragment coordinate conventions. */
363 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
364 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
365 return 1;
366 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
367 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
368 return 0;
369
370 default:
371 R600_ERR("r600: unknown param %d\n", param);
372 return 0;
373 }
374 }
375
376 static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
377 {
378 switch (param) {
379 case PIPE_CAP_MAX_LINE_WIDTH:
380 case PIPE_CAP_MAX_LINE_WIDTH_AA:
381 case PIPE_CAP_MAX_POINT_WIDTH:
382 case PIPE_CAP_MAX_POINT_WIDTH_AA:
383 return 8192.0f;
384 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
385 return 16.0f;
386 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
387 return 16.0f;
388 default:
389 R600_ERR("r600: unsupported paramf %d\n", param);
390 return 0.0f;
391 }
392 }
393
394 static boolean r600_is_format_supported(struct pipe_screen* screen,
395 enum pipe_format format,
396 enum pipe_texture_target target,
397 unsigned sample_count,
398 unsigned usage,
399 unsigned geom_flags)
400 {
401 unsigned retval = 0;
402 if (target >= PIPE_MAX_TEXTURE_TYPES) {
403 R600_ERR("r600: unsupported texture type %d\n", target);
404 return FALSE;
405 }
406
407 /* Multisample */
408 if (sample_count > 1)
409 return FALSE;
410
411 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
412 r600_is_sampler_format_supported(format)) {
413 retval |= PIPE_BIND_SAMPLER_VIEW;
414 }
415
416 if ((usage & (PIPE_BIND_RENDER_TARGET |
417 PIPE_BIND_DISPLAY_TARGET |
418 PIPE_BIND_SCANOUT |
419 PIPE_BIND_SHARED)) &&
420 r600_is_colorbuffer_format_supported(format)) {
421 retval |= usage &
422 (PIPE_BIND_RENDER_TARGET |
423 PIPE_BIND_DISPLAY_TARGET |
424 PIPE_BIND_SCANOUT |
425 PIPE_BIND_SHARED);
426 }
427
428 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
429 r600_is_zs_format_supported(format)) {
430 retval |= PIPE_BIND_DEPTH_STENCIL;
431 }
432
433 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
434 r600_is_vertex_format_supported(format))
435 retval |= PIPE_BIND_VERTEX_BUFFER;
436
437 if (usage & PIPE_BIND_TRANSFER_READ)
438 retval |= PIPE_BIND_TRANSFER_READ;
439 if (usage & PIPE_BIND_TRANSFER_WRITE)
440 retval |= PIPE_BIND_TRANSFER_WRITE;
441
442 return retval == usage;
443 }
444
445 static void r600_destroy_screen(struct pipe_screen* pscreen)
446 {
447 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
448
449 if (rscreen == NULL)
450 return;
451 FREE(rscreen);
452 }
453
454 int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
455 static void r600_draw_common(struct r600_drawl *draw)
456 {
457 struct r600_pipe_context *rctx = (struct r600_pipe_context *)draw->ctx;
458 struct r600_pipe_state *rstate;
459 struct r600_resource *rbuffer;
460 unsigned i, j, offset, format, prim;
461 u32 vgt_dma_index_type, vgt_draw_initiator, mask;
462 struct pipe_vertex_buffer *vertex_buffer;
463 struct r600_draw rdraw;
464 struct r600_pipe_state vgt;
465
466 /* flush upload buffers */
467 r600_upload_user_buffers2(rctx);
468
469 switch (draw->index_size) {
470 case 2:
471 vgt_draw_initiator = 0;
472 vgt_dma_index_type = 0;
473 break;
474 case 4:
475 vgt_draw_initiator = 0;
476 vgt_dma_index_type = 1;
477 break;
478 case 0:
479 vgt_draw_initiator = 2;
480 vgt_dma_index_type = 0;
481 break;
482 default:
483 R600_ERR("unsupported index size %d\n", draw->index_size);
484 return;
485 }
486 if (r600_conv_pipe_prim(draw->mode, &prim))
487 return;
488
489 /* rebuild vertex shader if input format changed */
490 if (r600_pipe_shader_update2(&rctx->context, rctx->vs_shader))
491 return;
492 if (r600_pipe_shader_update2(&rctx->context, rctx->ps_shader))
493 return;
494
495 for (i = 0 ; i < rctx->vertex_elements->count; i++) {
496 rstate = &rctx->vs_resource[i];
497 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
498 vertex_buffer = &rctx->vertex_buffer[j];
499 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
500 offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
501 format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
502 rstate->id = R600_PIPE_STATE_RESOURCE;
503 rstate->nregs = 0;
504
505 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
506 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
507 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE,
508 R_038008_RESOURCE0_WORD2,
509 S_038008_STRIDE(vertex_buffer->stride) |
510 S_038008_DATA_FORMAT(format),
511 0xFFFFFFFF, NULL);
512 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_03800C_RESOURCE0_WORD3, 0x00000000, 0xFFFFFFFF, NULL);
513 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
514 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
515 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038018_RESOURCE0_WORD6, 0xC0000000, 0xFFFFFFFF, NULL);
516 r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, i);
517 }
518
519 mask = 0;
520 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
521 mask |= (0xF << (i * 4));
522 }
523
524 vgt.id = R600_PIPE_STATE_VGT;
525 vgt.nregs = 0;
526 r600_pipe_state_add_reg(&vgt, R600_GROUP_CONFIG, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
527 r600_pipe_state_add_reg(&vgt, R600_GROUP_CONTEXT, R_028408_VGT_INDX_OFFSET, draw->index_bias, 0xFFFFFFFF, NULL);
528 r600_pipe_state_add_reg(&vgt, R600_GROUP_CONTEXT, R_028400_VGT_MAX_VTX_INDX, draw->max_index, 0xFFFFFFFF, NULL);
529 r600_pipe_state_add_reg(&vgt, R600_GROUP_CONTEXT, R_028404_VGT_MIN_VTX_INDX, draw->min_index, 0xFFFFFFFF, NULL);
530 r600_pipe_state_add_reg(&vgt, R600_GROUP_CONTEXT, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
531 r600_context_pipe_state_set(&rctx->ctx, &vgt);
532
533 rdraw.vgt_num_indices = draw->count;
534 rdraw.vgt_num_instances = 1;
535 rdraw.vgt_index_type = vgt_dma_index_type;
536 rdraw.vgt_draw_initiator = vgt_draw_initiator;
537 rdraw.indices = NULL;
538 if (draw->index_buffer) {
539 rbuffer = (struct r600_resource*)draw->index_buffer;
540 rdraw.indices = rbuffer->bo;
541 rdraw.indices_bo_offset = 0;
542 }
543 r600_context_draw(&rctx->ctx, &rdraw);
544 }
545
546 void r600_translate_index_buffer2(struct r600_pipe_context *r600,
547 struct pipe_resource **index_buffer,
548 unsigned *index_size,
549 unsigned *start, unsigned count)
550 {
551 switch (*index_size) {
552 case 1:
553 util_shorten_ubyte_elts(&r600->context, index_buffer, 0, *start, count);
554 *index_size = 2;
555 *start = 0;
556 break;
557
558 case 2:
559 if (*start % 2 != 0) {
560 util_rebuild_ushort_elts(&r600->context, index_buffer, 0, *start, count);
561 *start = 0;
562 }
563 break;
564
565 case 4:
566 break;
567 }
568 }
569
570 static void r600_draw_vbo2(struct pipe_context *ctx, const struct pipe_draw_info *info)
571 {
572 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
573 struct r600_drawl draw;
574
575 assert(info->index_bias == 0);
576
577 memset(&draw, 0, sizeof(struct r600_drawl));
578 draw.ctx = ctx;
579 draw.mode = info->mode;
580 draw.start = info->start;
581 draw.count = info->count;
582 if (info->indexed && rctx->index_buffer.buffer) {
583 draw.min_index = info->min_index;
584 draw.max_index = info->max_index;
585 draw.index_bias = info->index_bias;
586
587 r600_translate_index_buffer2(rctx, &rctx->index_buffer.buffer,
588 &rctx->index_buffer.index_size,
589 &draw.start,
590 info->count);
591
592 draw.index_size = rctx->index_buffer.index_size;
593 draw.index_buffer = rctx->index_buffer.buffer;
594 draw.index_buffer_offset = draw.start * draw.index_size;
595 draw.start = 0;
596 r600_upload_index_buffer2(rctx, &draw);
597 } else {
598 draw.index_size = 0;
599 draw.index_buffer = NULL;
600 draw.min_index = info->min_index;
601 draw.max_index = info->max_index;
602 draw.index_bias = info->start;
603 }
604 r600_draw_common(&draw);
605 }
606
607 static void r600_flush2(struct pipe_context *ctx, unsigned flags,
608 struct pipe_fence_handle **fence)
609 {
610 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
611 #if 1
612 static int dc = 0;
613 char dname[256];
614 #endif
615
616 if (!rctx->ctx.pm4_cdwords)
617 return;
618
619 u_upload_flush(rctx->upload_vb);
620 u_upload_flush(rctx->upload_ib);
621
622 #if 0
623 sprintf(dname, "gallium-%08d.bof", dc);
624 if (dc < 20) {
625 r600_context_dump_bof(&rctx->ctx, dname);
626 R600_ERR("dumped %s\n", dname);
627 }
628 dc++;
629 #endif
630 r600_context_flush(&rctx->ctx);
631 }
632
633 static void r600_destroy_context(struct pipe_context *context)
634 {
635 struct r600_pipe_context *rctx = (struct r600_pipe_context *)context;
636
637 r600_context_fini(&rctx->ctx);
638 for (int i = 0; i < R600_PIPE_NSTATES; i++) {
639 free(rctx->states[i]);
640 }
641
642 u_upload_destroy(rctx->upload_vb);
643 u_upload_destroy(rctx->upload_ib);
644
645 FREE(rctx);
646 }
647
648 static void r600_blitter_save_states(struct pipe_context *ctx)
649 {
650 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
651
652 util_blitter_save_blend(rctx->blitter, rctx->states[R600_PIPE_STATE_BLEND]);
653 util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->states[R600_PIPE_STATE_DSA]);
654 if (rctx->states[R600_PIPE_STATE_STENCIL_REF]) {
655 util_blitter_save_stencil_ref(rctx->blitter, &rctx->stencil_ref);
656 }
657 util_blitter_save_rasterizer(rctx->blitter, rctx->states[R600_PIPE_STATE_RASTERIZER]);
658 util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader);
659 util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader);
660 util_blitter_save_vertex_elements(rctx->blitter, rctx->vertex_elements);
661 if (rctx->states[R600_PIPE_STATE_VIEWPORT]) {
662 util_blitter_save_viewport(rctx->blitter, &rctx->viewport);
663 }
664 if (rctx->states[R600_PIPE_STATE_CLIP]) {
665 util_blitter_save_clip(rctx->blitter, &rctx->clip);
666 }
667 util_blitter_save_vertex_buffers(rctx->blitter, rctx->nvertex_buffer, rctx->vertex_buffer);
668
669 rctx->vertex_elements = NULL;
670
671 /* TODO queries */
672 }
673
674 static void r600_clear(struct pipe_context *ctx, unsigned buffers,
675 const float *rgba, double depth, unsigned stencil)
676 {
677 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
678 struct pipe_framebuffer_state *fb = &rctx->framebuffer;
679
680 r600_blitter_save_states(ctx);
681 util_blitter_clear(rctx->blitter, fb->width, fb->height,
682 fb->nr_cbufs, buffers, rgba, depth,
683 stencil);
684 }
685
686 static void r600_clear_render_target(struct pipe_context *ctx,
687 struct pipe_surface *dst,
688 const float *rgba,
689 unsigned dstx, unsigned dsty,
690 unsigned width, unsigned height)
691 {
692 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
693 struct pipe_framebuffer_state *fb = &rctx->framebuffer;
694
695 util_blitter_save_framebuffer(rctx->blitter, fb);
696 util_blitter_clear_render_target(rctx->blitter, dst, rgba,
697 dstx, dsty, width, height);
698 }
699
700 static void r600_clear_depth_stencil(struct pipe_context *ctx,
701 struct pipe_surface *dst,
702 unsigned clear_flags,
703 double depth,
704 unsigned stencil,
705 unsigned dstx, unsigned dsty,
706 unsigned width, unsigned height)
707 {
708 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
709 struct pipe_framebuffer_state *fb = &rctx->framebuffer;
710
711 util_blitter_save_framebuffer(rctx->blitter, fb);
712 util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil,
713 dstx, dsty, width, height);
714 }
715
716
717 static void r600_resource_copy_region(struct pipe_context *ctx,
718 struct pipe_resource *dst,
719 struct pipe_subresource subdst,
720 unsigned dstx, unsigned dsty, unsigned dstz,
721 struct pipe_resource *src,
722 struct pipe_subresource subsrc,
723 unsigned srcx, unsigned srcy, unsigned srcz,
724 unsigned width, unsigned height)
725 {
726 util_resource_copy_region(ctx, dst, subdst, dstx, dsty, dstz,
727 src, subsrc, srcx, srcy, srcz, width, height);
728 }
729
730 static void r600_init_blit_functions2(struct r600_pipe_context *rctx)
731 {
732 rctx->context.clear = r600_clear;
733 rctx->context.clear_render_target = r600_clear_render_target;
734 rctx->context.clear_depth_stencil = r600_clear_depth_stencil;
735 rctx->context.resource_copy_region = r600_resource_copy_region;
736 }
737
738 static void r600_init_context_resource_functions2(struct r600_pipe_context *r600)
739 {
740 r600->context.get_transfer = u_get_transfer_vtbl;
741 r600->context.transfer_map = u_transfer_map_vtbl;
742 r600->context.transfer_flush_region = u_transfer_flush_region_vtbl;
743 r600->context.transfer_unmap = u_transfer_unmap_vtbl;
744 r600->context.transfer_destroy = u_transfer_destroy_vtbl;
745 r600->context.transfer_inline_write = u_transfer_inline_write_vtbl;
746 r600->context.is_resource_referenced = u_is_resource_referenced_vtbl;
747 }
748
749 static void r600_set_blend_color(struct pipe_context *ctx,
750 const struct pipe_blend_color *state)
751 {
752 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
753 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
754
755 if (rstate == NULL)
756 return;
757
758 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
759 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
760 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
761 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
762 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
763 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
764 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
765 r600_context_pipe_state_set(&rctx->ctx, rstate);
766 }
767
768 static void *r600_create_blend_state(struct pipe_context *ctx,
769 const struct pipe_blend_state *state)
770 {
771 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
772 struct r600_pipe_state *rstate;
773 u32 color_control, target_mask;
774
775 if (blend == NULL) {
776 return NULL;
777 }
778 rstate = &blend->rstate;
779
780 rstate->id = R600_PIPE_STATE_BLEND;
781
782 target_mask = 0;
783 color_control = S_028808_PER_MRT_BLEND(1);
784 if (state->logicop_enable) {
785 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
786 } else {
787 color_control |= (0xcc << 16);
788 }
789 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
790 if (state->independent_blend_enable) {
791 for (int i = 0; i < 8; i++) {
792 if (state->rt[i].blend_enable) {
793 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
794 }
795 target_mask |= (state->rt[i].colormask << (4 * i));
796 }
797 } else {
798 for (int i = 0; i < 8; i++) {
799 if (state->rt[0].blend_enable) {
800 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
801 }
802 target_mask |= (state->rt[0].colormask << (4 * i));
803 }
804 }
805 blend->cb_target_mask = target_mask;
806 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028808_CB_COLOR_CONTROL,
807 color_control, 0xFFFFFFFF, NULL);
808
809 for (int i = 0; i < 8; i++) {
810 unsigned eqRGB = state->rt[i].rgb_func;
811 unsigned srcRGB = state->rt[i].rgb_src_factor;
812 unsigned dstRGB = state->rt[i].rgb_dst_factor;
813
814 unsigned eqA = state->rt[i].alpha_func;
815 unsigned srcA = state->rt[i].alpha_src_factor;
816 unsigned dstA = state->rt[i].alpha_dst_factor;
817 uint32_t bc = 0;
818
819 if (!state->rt[i].blend_enable)
820 continue;
821
822 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
823 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
824 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
825
826 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
827 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
828 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
829 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
830 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
831 }
832
833 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
834 if (i == 0) {
835 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
836 }
837 }
838 return rstate;
839 }
840
841 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
842 {
843 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
844 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
845 struct r600_pipe_state *rstate;
846
847 if (state == NULL)
848 return;
849 rstate = &blend->rstate;
850 rctx->states[rstate->id] = rstate;
851 rctx->cb_target_mask = blend->cb_target_mask;
852 r600_context_pipe_state_set(&rctx->ctx, rstate);
853 }
854
855 static void *r600_create_dsa_state(struct pipe_context *ctx,
856 const struct pipe_depth_stencil_alpha_state *state)
857 {
858 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
859 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
860 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
861
862 if (rstate == NULL) {
863 return NULL;
864 }
865
866 rstate->id = R600_PIPE_STATE_DSA;
867 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
868 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
869 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
870 * be set if shader use texkill instruction
871 */
872 db_shader_control = 0x210;
873 stencil_ref_mask = 0;
874 stencil_ref_mask_bf = 0;
875 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
876 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
877 S_028800_ZFUNC(state->depth.func);
878
879 /* stencil */
880 if (state->stencil[0].enabled) {
881 db_depth_control |= S_028800_STENCIL_ENABLE(1);
882 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
883 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
884 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
885 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
886
887
888 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
889 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
890 if (state->stencil[1].enabled) {
891 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
892 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
893 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
894 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
895 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
896 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
897 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
898 }
899 }
900
901 /* alpha */
902 alpha_test_control = 0;
903 alpha_ref = 0;
904 if (state->alpha.enabled) {
905 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
906 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
907 alpha_ref = fui(state->alpha.ref_value);
908 }
909
910 /* misc */
911 db_render_control = 0;
912 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
913 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
914 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
915 /* TODO db_render_override depends on query */
916 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
917 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
918 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
919 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
920 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
921 0xFFFFFFFF & C_028430_STENCILREF, NULL);
922 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
923 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
924 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
925 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
926 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
927 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
928 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
929 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
930 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
931 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
932 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
933 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
934 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
935 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
936
937 return rstate;
938 }
939
940 static void *r600_create_rs_state(struct pipe_context *ctx,
941 const struct pipe_rasterizer_state *state)
942 {
943 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
944 struct r600_pipe_state *rstate;
945 float offset_units = 0, offset_scale = 0;
946 unsigned offset_db_fmt_cntl = 0;
947 unsigned tmp;
948 unsigned prov_vtx = 1;
949
950 if (rs == NULL) {
951 return NULL;
952 }
953
954 rstate = &rs->rstate;
955 rs->flatshade = state->flatshade;
956 rs->sprite_coord_enable = state->sprite_coord_enable;
957
958 rstate->id = R600_PIPE_STATE_RASTERIZER;
959 if (state->flatshade_first)
960 prov_vtx = 0;
961 tmp = 0x00000001;
962 if (state->sprite_coord_enable) {
963 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
964 S_0286D4_PNT_SPRITE_OVRD_X(2) |
965 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
966 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
967 S_0286D4_PNT_SPRITE_OVRD_W(1);
968 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
969 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
970 }
971 }
972 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
973
974 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028814_PA_SU_SC_MODE_CNTL,
975 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
976 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
977 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
978 S_028814_FACE(!state->front_ccw) |
979 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
980 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
981 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri), 0xFFFFFFFF, NULL);
982 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02881C_PA_CL_VS_OUT_CNTL,
983 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
984 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
985 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
986 /* point size 12.4 fixed point */
987 tmp = (unsigned)(state->point_size * 8.0);
988 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
989 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
990 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A08_PA_SU_LINE_CNTL, 0x00000008, 0xFFFFFFFF, NULL);
991 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
992 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
993 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
994 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
995 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
996 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
997 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
998 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
999 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
1000 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, fui(offset_scale), 0xFFFFFFFF, NULL);
1001 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units), 0xFFFFFFFF, NULL);
1002 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, fui(offset_scale), 0xFFFFFFFF, NULL);
1003 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units), 0xFFFFFFFF, NULL);
1004 return rstate;
1005 }
1006
1007 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
1008 {
1009 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
1010 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1011
1012 if (state == NULL)
1013 return;
1014
1015 if (rctx->flatshade != rs->flatshade) {
1016 // rctx->ps_rebuild = TRUE;
1017 }
1018 if (rctx->sprite_coord_enable != rs->sprite_coord_enable) {
1019 // rctx->ps_rebuild = TRUE;
1020 }
1021 rctx->flatshade = rs->flatshade;
1022 rctx->sprite_coord_enable = rs->sprite_coord_enable;
1023
1024 rctx->states[rs->rstate.id] = &rs->rstate;
1025 r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
1026 }
1027
1028 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
1029 {
1030 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1031 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
1032
1033 if (rctx->states[rs->rstate.id] == &rs->rstate) {
1034 rctx->states[rs->rstate.id] = NULL;
1035 }
1036 free(rs);
1037 }
1038
1039 static void *r600_create_sampler_state(struct pipe_context *ctx,
1040 const struct pipe_sampler_state *state)
1041 {
1042 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1043 union util_color uc;
1044
1045 if (rstate == NULL) {
1046 return NULL;
1047 }
1048
1049 rstate->id = R600_PIPE_STATE_SAMPLER;
1050 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1051 r600_pipe_state_add_reg(rstate, R600_GROUP_SAMPLER, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
1052 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1053 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1054 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1055 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
1056 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
1057 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1058 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1059 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
1060 /* FIXME LOD it depends on texture base level ... */
1061 r600_pipe_state_add_reg(rstate, R600_GROUP_SAMPLER, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
1062 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1063 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1064 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
1065 r600_pipe_state_add_reg(rstate, R600_GROUP_SAMPLER, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
1066 if (uc.ui) {
1067 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
1068 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
1069 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
1070 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
1071 }
1072 return rstate;
1073 }
1074
1075 static void *r600_create_vertex_elements(struct pipe_context *ctx,
1076 unsigned count,
1077 const struct pipe_vertex_element *elements)
1078 {
1079 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
1080
1081 assert(count < 32);
1082 v->count = count;
1083 v->refcount = 1;
1084 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
1085 return v;
1086 }
1087
1088 static void r600_sampler_view_destroy(struct pipe_context *ctx,
1089 struct pipe_sampler_view *state)
1090 {
1091 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
1092
1093 pipe_resource_reference(&state->texture, NULL);
1094 FREE(resource);
1095 }
1096
1097 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
1098 struct pipe_resource *texture,
1099 const struct pipe_sampler_view *state)
1100 {
1101 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
1102 struct r600_pipe_state *rstate;
1103 const struct util_format_description *desc;
1104 struct r600_resource_texture *tmp;
1105 struct r600_resource *rbuffer;
1106 unsigned format;
1107 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1108 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1109 struct radeon_ws_bo *bo[2];
1110
1111 if (resource == NULL)
1112 return NULL;
1113 rstate = &resource->state;
1114
1115 /* initialize base object */
1116 resource->base = *state;
1117 resource->base.texture = NULL;
1118 pipe_reference(NULL, &texture->reference);
1119 resource->base.texture = texture;
1120 resource->base.reference.count = 1;
1121 resource->base.context = ctx;
1122
1123 swizzle[0] = state->swizzle_r;
1124 swizzle[1] = state->swizzle_g;
1125 swizzle[2] = state->swizzle_b;
1126 swizzle[3] = state->swizzle_a;
1127 format = r600_translate_texformat(texture->format,
1128 swizzle,
1129 &word4, &yuv_format);
1130 if (format == ~0) {
1131 format = 0;
1132 }
1133 desc = util_format_description(texture->format);
1134 if (desc == NULL) {
1135 R600_ERR("unknow format %d\n", texture->format);
1136 }
1137 tmp = (struct r600_resource_texture*)texture;
1138 rbuffer = &tmp->resource;
1139 bo[0] = rbuffer->bo;
1140 bo[1] = rbuffer->bo;
1141 /* FIXME depth texture decompression */
1142 if (tmp->depth) {
1143 #if 0
1144 r = r600_texture_from_depth(ctx, tmp, view->first_level);
1145 if (r) {
1146 return;
1147 }
1148 bo[0] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
1149 bo[1] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
1150 #endif
1151 }
1152 pitch = align(tmp->pitch[0] / tmp->bpt, 8);
1153
1154 /* FIXME properly handle first level != 0 */
1155 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038000_RESOURCE0_WORD0,
1156 S_038000_DIM(r600_tex_dim(texture->target)) |
1157 S_038000_TILE_MODE(array_mode) |
1158 S_038000_TILE_TYPE(tile_type) |
1159 S_038000_PITCH((pitch / 8) - 1) |
1160 S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
1161 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038004_RESOURCE0_WORD1,
1162 S_038004_TEX_HEIGHT(texture->height0 - 1) |
1163 S_038004_TEX_DEPTH(texture->depth0 - 1) |
1164 S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
1165 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038008_RESOURCE0_WORD2,
1166 tmp->offset[0] >> 8, 0xFFFFFFFF, bo[0]);
1167 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_03800C_RESOURCE0_WORD3,
1168 tmp->offset[1] >> 8, 0xFFFFFFFF, bo[1]);
1169 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038010_RESOURCE0_WORD4,
1170 word4 | S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
1171 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
1172 S_038010_REQUEST_SIZE(1) |
1173 S_038010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
1174 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038014_RESOURCE0_WORD5,
1175 S_038014_LAST_LEVEL(state->last_level) |
1176 S_038014_BASE_ARRAY(0) |
1177 S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL);
1178 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038018_RESOURCE0_WORD6,
1179 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
1180
1181 return &resource->base;
1182 }
1183
1184 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1185 struct pipe_sampler_view **views)
1186 {
1187 /* TODO */
1188 assert(1);
1189 }
1190
1191 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1192 struct pipe_sampler_view **views)
1193 {
1194 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1195 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1196
1197 for (int i = 0; i < count; i++) {
1198 if (resource[i]) {
1199 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
1200 }
1201 }
1202 }
1203
1204 static void r600_bind_state(struct pipe_context *ctx, void *state)
1205 {
1206 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1207 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
1208
1209 if (state == NULL)
1210 return;
1211 rctx->states[rstate->id] = rstate;
1212 r600_context_pipe_state_set(&rctx->ctx, rstate);
1213 }
1214
1215 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1216 {
1217 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1218 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1219
1220 for (int i = 0; i < count; i++) {
1221 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
1222 }
1223 }
1224
1225 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1226 {
1227 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1228 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1229
1230 /* TODO implement */
1231 for (int i = 0; i < count; i++) {
1232 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
1233 }
1234 }
1235
1236 static void r600_delete_state(struct pipe_context *ctx, void *state)
1237 {
1238 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1239 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
1240
1241 if (rctx->states[rstate->id] == rstate) {
1242 rctx->states[rstate->id] = NULL;
1243 }
1244 for (int i = 0; i < rstate->nregs; i++) {
1245 radeon_ws_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
1246 }
1247 free(rstate);
1248 }
1249
1250 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
1251 {
1252 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
1253
1254 if (v == NULL)
1255 return;
1256 if (--v->refcount)
1257 return;
1258 free(v);
1259 }
1260
1261 static void r600_set_clip_state(struct pipe_context *ctx,
1262 const struct pipe_clip_state *state)
1263 {
1264 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1265 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1266
1267 if (rstate == NULL)
1268 return;
1269
1270 rctx->clip = *state;
1271 rstate->id = R600_PIPE_STATE_CLIP;
1272 for (int i = 0; i < state->nr; i++) {
1273 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1274 R_028E20_PA_CL_UCP0_X + i * 4,
1275 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
1276 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1277 R_028E24_PA_CL_UCP0_Y + i * 4,
1278 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
1279 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1280 R_028E28_PA_CL_UCP0_Z + i * 4,
1281 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
1282 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1283 R_028E2C_PA_CL_UCP0_W + i * 4,
1284 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
1285 }
1286 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028810_PA_CL_CLIP_CNTL,
1287 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
1288 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
1289 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
1290
1291 free(rctx->states[R600_PIPE_STATE_CLIP]);
1292 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1293 r600_context_pipe_state_set(&rctx->ctx, rstate);
1294 }
1295
1296 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
1297 {
1298 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1299 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
1300
1301 r600_delete_vertex_element(ctx, rctx->vertex_elements);
1302 rctx->vertex_elements = v;
1303 if (v) {
1304 v->refcount++;
1305 // rctx->vs_rebuild = TRUE;
1306 }
1307 }
1308
1309 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1310 const struct pipe_poly_stipple *state)
1311 {
1312 }
1313
1314 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1315 {
1316 }
1317
1318 static void r600_set_scissor_state(struct pipe_context *ctx,
1319 const struct pipe_scissor_state *state)
1320 {
1321 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1322 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1323 u32 tl, br;
1324
1325 if (rstate == NULL)
1326 return;
1327
1328 rstate->id = R600_PIPE_STATE_SCISSOR;
1329 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1330 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1331 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1332 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1333 0xFFFFFFFF, NULL);
1334 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1335 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1336 0xFFFFFFFF, NULL);
1337 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1338 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1339 0xFFFFFFFF, NULL);
1340 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1341 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1342 0xFFFFFFFF, NULL);
1343 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1344 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1345 0xFFFFFFFF, NULL);
1346 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1347 R_028214_PA_SC_CLIPRECT_0_BR, br,
1348 0xFFFFFFFF, NULL);
1349 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1350 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1351 0xFFFFFFFF, NULL);
1352 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1353 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1354 0xFFFFFFFF, NULL);
1355 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1356 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1357 0xFFFFFFFF, NULL);
1358 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1359 R_028224_PA_SC_CLIPRECT_2_BR, br,
1360 0xFFFFFFFF, NULL);
1361 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1362 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1363 0xFFFFFFFF, NULL);
1364 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1365 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1366 0xFFFFFFFF, NULL);
1367 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1368 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1369 0xFFFFFFFF, NULL);
1370 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1371 R_02820C_PA_SC_CLIPRECT_RULE, 0x0000FFFF,
1372 0xFFFFFFFF, NULL);
1373 if (rctx->family >= CHIP_RV770) {
1374 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1375 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1376 0xFFFFFFFF, NULL);
1377 }
1378
1379 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1380 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1381 r600_context_pipe_state_set(&rctx->ctx, rstate);
1382 }
1383
1384 static void r600_set_stencil_ref(struct pipe_context *ctx,
1385 const struct pipe_stencil_ref *state)
1386 {
1387 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1388 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1389 u32 tmp;
1390
1391 if (rstate == NULL)
1392 return;
1393
1394 rctx->stencil_ref = *state;
1395 rstate->id = R600_PIPE_STATE_STENCIL_REF;
1396 tmp = S_028430_STENCILREF(state->ref_value[0]);
1397 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1398 R_028430_DB_STENCILREFMASK, tmp,
1399 ~C_028430_STENCILREF, NULL);
1400 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
1401 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1402 R_028434_DB_STENCILREFMASK_BF, tmp,
1403 ~C_028434_STENCILREF_BF, NULL);
1404
1405 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
1406 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
1407 r600_context_pipe_state_set(&rctx->ctx, rstate);
1408 }
1409
1410 static void r600_set_viewport_state(struct pipe_context *ctx,
1411 const struct pipe_viewport_state *state)
1412 {
1413 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1414 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1415
1416 if (rstate == NULL)
1417 return;
1418
1419 rctx->viewport = *state;
1420 rstate->id = R600_PIPE_STATE_VIEWPORT;
1421 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
1422 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
1423 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
1424 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
1425 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
1426 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
1427 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
1428 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
1429 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
1430
1431 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1432 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1433 r600_context_pipe_state_set(&rctx->ctx, rstate);
1434 }
1435
1436 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1437 const struct pipe_framebuffer_state *state, int cb)
1438 {
1439 struct r600_resource_texture *rtex;
1440 struct r600_resource *rbuffer;
1441 unsigned level = state->cbufs[cb]->level;
1442 unsigned pitch, slice;
1443 unsigned color_info;
1444 unsigned format, swap, ntype;
1445 const struct util_format_description *desc;
1446 struct radeon_ws_bo *bo[3];
1447
1448 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1449 rbuffer = &rtex->resource;
1450 bo[0] = rbuffer->bo;
1451 bo[1] = rbuffer->bo;
1452 bo[2] = rbuffer->bo;
1453
1454 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
1455 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
1456 ntype = 0;
1457 desc = util_format_description(rtex->resource.base.b.format);
1458 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1459 ntype = V_0280A0_NUMBER_SRGB;
1460
1461 format = r600_translate_colorformat(rtex->resource.base.b.format);
1462 swap = r600_translate_colorswap(rtex->resource.base.b.format);
1463 color_info = S_0280A0_FORMAT(format) |
1464 S_0280A0_COMP_SWAP(swap) |
1465 S_0280A0_BLEND_CLAMP(1) |
1466 S_0280A0_SOURCE_FORMAT(1) |
1467 S_0280A0_NUMBER_TYPE(ntype);
1468
1469 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1470 R_028040_CB_COLOR0_BASE + cb * 4,
1471 state->cbufs[cb]->offset >> 8, 0xFFFFFFFF, bo[0]);
1472 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1473 R_0280A0_CB_COLOR0_INFO + cb * 4,
1474 color_info, 0xFFFFFFFF, bo[0]);
1475 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1476 R_028060_CB_COLOR0_SIZE + cb * 4,
1477 S_028060_PITCH_TILE_MAX(pitch) |
1478 S_028060_SLICE_TILE_MAX(slice),
1479 0xFFFFFFFF, NULL);
1480 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1481 R_028080_CB_COLOR0_VIEW + cb * 4,
1482 0x00000000, 0xFFFFFFFF, NULL);
1483 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1484 R_0280E0_CB_COLOR0_FRAG + cb * 4,
1485 0x00000000, 0xFFFFFFFF, bo[1]);
1486 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1487 R_0280C0_CB_COLOR0_TILE + cb * 4,
1488 0x00000000, 0xFFFFFFFF, bo[2]);
1489 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1490 R_028100_CB_COLOR0_MASK + cb * 4,
1491 0x00000000, 0xFFFFFFFF, NULL);
1492 }
1493
1494 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1495 const struct pipe_framebuffer_state *state)
1496 {
1497 struct r600_resource_texture *rtex;
1498 struct r600_resource *rbuffer;
1499 unsigned level;
1500 unsigned pitch, slice, format;
1501
1502 if (state->zsbuf == NULL)
1503 return;
1504
1505 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1506 rtex->tiled = 1;
1507 rtex->array_mode = 2;
1508 rtex->tile_type = 1;
1509 rtex->depth = 1;
1510 rbuffer = &rtex->resource;
1511
1512 level = state->zsbuf->level;
1513 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
1514 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
1515 format = r600_translate_dbformat(state->zsbuf->texture->format);
1516
1517 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02800C_DB_DEPTH_BASE,
1518 state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
1519 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028000_DB_DEPTH_SIZE,
1520 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1521 0xFFFFFFFF, NULL);
1522 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
1523 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028010_DB_DEPTH_INFO,
1524 S_028010_ARRAY_MODE(rtex->array_mode) | S_028010_FORMAT(format),
1525 0xFFFFFFFF, rbuffer->bo);
1526 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D34_DB_PREFETCH_LIMIT,
1527 (state->zsbuf->height / 8) - 1, 0xFFFFFFFF, NULL);
1528 }
1529
1530 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1531 const struct pipe_framebuffer_state *state)
1532 {
1533 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1534 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1535 u32 shader_mask, tl, br, shader_control, target_mask;
1536
1537 if (rstate == NULL)
1538 return;
1539
1540 /* unreference old buffer and reference new one */
1541 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1542 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
1543 pipe_surface_reference(&rctx->framebuffer.cbufs[i], NULL);
1544 }
1545 for (int i = 0; i < state->nr_cbufs; i++) {
1546 pipe_surface_reference(&rctx->framebuffer.cbufs[i], state->cbufs[i]);
1547 }
1548 pipe_surface_reference(&rctx->framebuffer.zsbuf, state->zsbuf);
1549 rctx->framebuffer = *state;
1550
1551 /* build states */
1552 for (int i = 0; i < state->nr_cbufs; i++) {
1553 r600_cb(rctx, rstate, state, i);
1554 }
1555 if (state->zsbuf) {
1556 r600_db(rctx, rstate, state);
1557 }
1558
1559 target_mask = 0x00000000;
1560 target_mask = 0xFFFFFFFF;
1561 shader_mask = 0;
1562 shader_control = 0;
1563 for (int i = 0; i < state->nr_cbufs; i++) {
1564 target_mask ^= 0xf << (i * 4);
1565 shader_mask |= 0xf << (i * 4);
1566 shader_control |= 1 << i;
1567 }
1568 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1569 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1570
1571 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1572 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1573 0xFFFFFFFF, NULL);
1574 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1575 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1576 0xFFFFFFFF, NULL);
1577 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1578 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1579 0xFFFFFFFF, NULL);
1580 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1581 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1582 0xFFFFFFFF, NULL);
1583
1584 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0287A0_CB_SHADER_CONTROL,
1585 shader_control, 0xFFFFFFFF, NULL);
1586 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028238_CB_TARGET_MASK,
1587 0x00000000, target_mask, NULL);
1588 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02823C_CB_SHADER_MASK,
1589 shader_mask, 0xFFFFFFFF, NULL);
1590 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C04_PA_SC_AA_CONFIG,
1591 0x00000000, 0xFFFFFFFF, NULL);
1592 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1593 0x00000000, 0xFFFFFFFF, NULL);
1594 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1595 0x00000000, 0xFFFFFFFF, NULL);
1596 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C30_CB_CLRCMP_CONTROL,
1597 0x01000000, 0xFFFFFFFF, NULL);
1598 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C34_CB_CLRCMP_SRC,
1599 0x00000000, 0xFFFFFFFF, NULL);
1600 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C38_CB_CLRCMP_DST,
1601 0x000000FF, 0xFFFFFFFF, NULL);
1602 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C3C_CB_CLRCMP_MSK,
1603 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1604 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C48_PA_SC_AA_MASK,
1605 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1606
1607 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1608 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1609 r600_context_pipe_state_set(&rctx->ctx, rstate);
1610 }
1611
1612 static void r600_set_index_buffer(struct pipe_context *ctx,
1613 const struct pipe_index_buffer *ib)
1614 {
1615 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1616
1617 if (ib) {
1618 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
1619 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
1620 } else {
1621 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
1622 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
1623 }
1624
1625 /* TODO make this more like a state */
1626 }
1627
1628 static void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
1629 const struct pipe_vertex_buffer *buffers)
1630 {
1631 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1632
1633 for (int i = 0; i < rctx->nvertex_buffer; i++) {
1634 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
1635 }
1636 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
1637 for (int i = 0; i < count; i++) {
1638 rctx->vertex_buffer[i].buffer = NULL;
1639 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
1640 }
1641 rctx->nvertex_buffer = count;
1642 }
1643
1644 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
1645 struct pipe_resource *buffer)
1646 {
1647 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1648 struct r600_pipe_state *rstate;
1649 struct pipe_transfer *transfer;
1650 unsigned *nconst = NULL;
1651 u32 *ptr, offset;
1652
1653 switch (shader) {
1654 case PIPE_SHADER_VERTEX:
1655 rstate = rctx->vs_const;
1656 nconst = &rctx->vs_nconst;
1657 offset = R_030000_SQ_ALU_CONSTANT0_0 + 0x1000;
1658 break;
1659 case PIPE_SHADER_FRAGMENT:
1660 rstate = rctx->ps_const;
1661 nconst = &rctx->ps_nconst;
1662 offset = R_030000_SQ_ALU_CONSTANT0_0;
1663 break;
1664 default:
1665 R600_ERR("unsupported %d\n", shader);
1666 return;
1667 }
1668 if (buffer && buffer->width0 > 0) {
1669 *nconst = buffer->width0 / 16;
1670 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
1671 if (ptr == NULL)
1672 return;
1673 for (int i = 0; i < *nconst; i++, offset += 0x10) {
1674 rstate[i].nregs = 0;
1675 r600_pipe_state_add_reg(&rstate[i], R600_GROUP_ALU_CONST, offset + 0x0, ptr[i * 4 + 0], 0xFFFFFFFF, NULL);
1676 r600_pipe_state_add_reg(&rstate[i], R600_GROUP_ALU_CONST, offset + 0x4, ptr[i * 4 + 1], 0xFFFFFFFF, NULL);
1677 r600_pipe_state_add_reg(&rstate[i], R600_GROUP_ALU_CONST, offset + 0x8, ptr[i * 4 + 2], 0xFFFFFFFF, NULL);
1678 r600_pipe_state_add_reg(&rstate[i], R600_GROUP_ALU_CONST, offset + 0xC, ptr[i * 4 + 3], 0xFFFFFFFF, NULL);
1679 r600_context_pipe_state_set(&rctx->ctx, &rstate[i]);
1680 }
1681 pipe_buffer_unmap(ctx, buffer, transfer);
1682 }
1683 }
1684
1685 static void *r600_create_shader_state(struct pipe_context *ctx,
1686 const struct pipe_shader_state *state)
1687 {
1688 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
1689 int r;
1690
1691 r = r600_pipe_shader_create2(ctx, shader, state->tokens);
1692 if (r) {
1693 return NULL;
1694 }
1695 return shader;
1696 }
1697
1698 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
1699 {
1700 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1701
1702 /* TODO delete old shader */
1703 rctx->ps_shader = (struct r600_pipe_shader *)state;
1704 }
1705
1706 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
1707 {
1708 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1709
1710 /* TODO delete old shader */
1711 rctx->vs_shader = (struct r600_pipe_shader *)state;
1712 }
1713
1714 static void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
1715 {
1716 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1717 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1718
1719 if (rctx->ps_shader == shader) {
1720 rctx->ps_shader = NULL;
1721 }
1722 /* TODO proper delete */
1723 free(shader);
1724 }
1725
1726 static void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
1727 {
1728 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1729 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1730
1731 if (rctx->vs_shader == shader) {
1732 rctx->vs_shader = NULL;
1733 }
1734 /* TODO proper delete */
1735 free(shader);
1736 }
1737
1738 static void r600_init_state_functions2(struct r600_pipe_context *rctx)
1739 {
1740 rctx->context.create_blend_state = r600_create_blend_state;
1741 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1742 rctx->context.create_fs_state = r600_create_shader_state;
1743 rctx->context.create_rasterizer_state = r600_create_rs_state;
1744 rctx->context.create_sampler_state = r600_create_sampler_state;
1745 rctx->context.create_sampler_view = r600_create_sampler_view;
1746 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1747 rctx->context.create_vs_state = r600_create_shader_state;
1748 rctx->context.bind_blend_state = r600_bind_blend_state;
1749 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
1750 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
1751 rctx->context.bind_fs_state = r600_bind_ps_shader;
1752 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1753 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1754 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
1755 rctx->context.bind_vs_state = r600_bind_vs_shader;
1756 rctx->context.delete_blend_state = r600_delete_state;
1757 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1758 rctx->context.delete_fs_state = r600_delete_ps_shader;
1759 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1760 rctx->context.delete_sampler_state = r600_delete_state;
1761 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1762 rctx->context.delete_vs_state = r600_delete_vs_shader;
1763 rctx->context.set_blend_color = r600_set_blend_color;
1764 rctx->context.set_clip_state = r600_set_clip_state;
1765 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1766 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
1767 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1768 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1769 rctx->context.set_sample_mask = r600_set_sample_mask;
1770 rctx->context.set_scissor_state = r600_set_scissor_state;
1771 rctx->context.set_stencil_ref = r600_set_stencil_ref;
1772 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1773 rctx->context.set_index_buffer = r600_set_index_buffer;
1774 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
1775 rctx->context.set_viewport_state = r600_set_viewport_state;
1776 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1777 }
1778
1779 static void r600_init_config2(struct r600_pipe_context *rctx)
1780 {
1781 int ps_prio;
1782 int vs_prio;
1783 int gs_prio;
1784 int es_prio;
1785 int num_ps_gprs;
1786 int num_vs_gprs;
1787 int num_gs_gprs;
1788 int num_es_gprs;
1789 int num_temp_gprs;
1790 int num_ps_threads;
1791 int num_vs_threads;
1792 int num_gs_threads;
1793 int num_es_threads;
1794 int num_ps_stack_entries;
1795 int num_vs_stack_entries;
1796 int num_gs_stack_entries;
1797 int num_es_stack_entries;
1798 enum radeon_family family;
1799 struct r600_pipe_state *rstate = &rctx->config;
1800 u32 tmp;
1801
1802 family = r600_get_family(rctx->radeon);
1803 ps_prio = 0;
1804 vs_prio = 1;
1805 gs_prio = 2;
1806 es_prio = 3;
1807 switch (family) {
1808 case CHIP_R600:
1809 num_ps_gprs = 192;
1810 num_vs_gprs = 56;
1811 num_temp_gprs = 4;
1812 num_gs_gprs = 0;
1813 num_es_gprs = 0;
1814 num_ps_threads = 136;
1815 num_vs_threads = 48;
1816 num_gs_threads = 4;
1817 num_es_threads = 4;
1818 num_ps_stack_entries = 128;
1819 num_vs_stack_entries = 128;
1820 num_gs_stack_entries = 0;
1821 num_es_stack_entries = 0;
1822 break;
1823 case CHIP_RV630:
1824 case CHIP_RV635:
1825 num_ps_gprs = 84;
1826 num_vs_gprs = 36;
1827 num_temp_gprs = 4;
1828 num_gs_gprs = 0;
1829 num_es_gprs = 0;
1830 num_ps_threads = 144;
1831 num_vs_threads = 40;
1832 num_gs_threads = 4;
1833 num_es_threads = 4;
1834 num_ps_stack_entries = 40;
1835 num_vs_stack_entries = 40;
1836 num_gs_stack_entries = 32;
1837 num_es_stack_entries = 16;
1838 break;
1839 case CHIP_RV610:
1840 case CHIP_RV620:
1841 case CHIP_RS780:
1842 case CHIP_RS880:
1843 default:
1844 num_ps_gprs = 84;
1845 num_vs_gprs = 36;
1846 num_temp_gprs = 4;
1847 num_gs_gprs = 0;
1848 num_es_gprs = 0;
1849 num_ps_threads = 136;
1850 num_vs_threads = 48;
1851 num_gs_threads = 4;
1852 num_es_threads = 4;
1853 num_ps_stack_entries = 40;
1854 num_vs_stack_entries = 40;
1855 num_gs_stack_entries = 32;
1856 num_es_stack_entries = 16;
1857 break;
1858 case CHIP_RV670:
1859 num_ps_gprs = 144;
1860 num_vs_gprs = 40;
1861 num_temp_gprs = 4;
1862 num_gs_gprs = 0;
1863 num_es_gprs = 0;
1864 num_ps_threads = 136;
1865 num_vs_threads = 48;
1866 num_gs_threads = 4;
1867 num_es_threads = 4;
1868 num_ps_stack_entries = 40;
1869 num_vs_stack_entries = 40;
1870 num_gs_stack_entries = 32;
1871 num_es_stack_entries = 16;
1872 break;
1873 case CHIP_RV770:
1874 num_ps_gprs = 192;
1875 num_vs_gprs = 56;
1876 num_temp_gprs = 4;
1877 num_gs_gprs = 0;
1878 num_es_gprs = 0;
1879 num_ps_threads = 188;
1880 num_vs_threads = 60;
1881 num_gs_threads = 0;
1882 num_es_threads = 0;
1883 num_ps_stack_entries = 256;
1884 num_vs_stack_entries = 256;
1885 num_gs_stack_entries = 0;
1886 num_es_stack_entries = 0;
1887 break;
1888 case CHIP_RV730:
1889 case CHIP_RV740:
1890 num_ps_gprs = 84;
1891 num_vs_gprs = 36;
1892 num_temp_gprs = 4;
1893 num_gs_gprs = 0;
1894 num_es_gprs = 0;
1895 num_ps_threads = 188;
1896 num_vs_threads = 60;
1897 num_gs_threads = 0;
1898 num_es_threads = 0;
1899 num_ps_stack_entries = 128;
1900 num_vs_stack_entries = 128;
1901 num_gs_stack_entries = 0;
1902 num_es_stack_entries = 0;
1903 break;
1904 case CHIP_RV710:
1905 num_ps_gprs = 192;
1906 num_vs_gprs = 56;
1907 num_temp_gprs = 4;
1908 num_gs_gprs = 0;
1909 num_es_gprs = 0;
1910 num_ps_threads = 144;
1911 num_vs_threads = 48;
1912 num_gs_threads = 0;
1913 num_es_threads = 0;
1914 num_ps_stack_entries = 128;
1915 num_vs_stack_entries = 128;
1916 num_gs_stack_entries = 0;
1917 num_es_stack_entries = 0;
1918 break;
1919 }
1920
1921 rstate->id = R600_PIPE_STATE_CONFIG;
1922
1923 /* SQ_CONFIG */
1924 tmp = 0;
1925 switch (family) {
1926 case CHIP_RV610:
1927 case CHIP_RV620:
1928 case CHIP_RS780:
1929 case CHIP_RS880:
1930 case CHIP_RV710:
1931 break;
1932 default:
1933 tmp |= S_008C00_VC_ENABLE(1);
1934 break;
1935 }
1936 tmp |= S_008C00_DX9_CONSTS(1);
1937 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1938 tmp |= S_008C00_PS_PRIO(ps_prio);
1939 tmp |= S_008C00_VS_PRIO(vs_prio);
1940 tmp |= S_008C00_GS_PRIO(gs_prio);
1941 tmp |= S_008C00_ES_PRIO(es_prio);
1942 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1943
1944 /* SQ_GPR_RESOURCE_MGMT_1 */
1945 tmp = 0;
1946 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1947 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1948 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1949 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1950
1951 /* SQ_GPR_RESOURCE_MGMT_2 */
1952 tmp = 0;
1953 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1954 tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
1955 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1956
1957 /* SQ_THREAD_RESOURCE_MGMT */
1958 tmp = 0;
1959 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1960 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1961 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1962 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1963 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1964
1965 /* SQ_STACK_RESOURCE_MGMT_1 */
1966 tmp = 0;
1967 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1968 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1969 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1970
1971 /* SQ_STACK_RESOURCE_MGMT_2 */
1972 tmp = 0;
1973 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1974 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1975 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1976
1977 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1978 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1979
1980 if (family >= CHIP_RV770) {
1981 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1982 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
1983 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1984 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1985 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1986 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A4C_PA_SC_MODE_CNTL, 0x00514000, 0xFFFFFFFF, NULL);
1987 } else {
1988 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1989 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
1990 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1991 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1992 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1993 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A4C_PA_SC_MODE_CNTL, 0x00004010, 0xFFFFFFFF, NULL);
1994 }
1995 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1996 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1997 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1998 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1999 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
2000 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
2001 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
2002 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
2003 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
2004 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
2005 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
2006 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
2007 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
2008 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
2009 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
2010 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
2011 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
2012 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
2013 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
2014 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
2015 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
2016 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
2017 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
2018 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
2019 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
2020 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
2021
2022 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
2023 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
2024 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
2025 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
2026 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
2027 r600_context_pipe_state_set(&rctx->ctx, rstate);
2028 }
2029
2030 static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type)
2031 {
2032 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2033
2034 return (struct pipe_query*)r600_context_query_create(&rctx->ctx, query_type);
2035 }
2036
2037 static void r600_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
2038 {
2039 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2040
2041 r600_context_query_destroy(&rctx->ctx, (struct r600_query *)query);
2042 }
2043
2044 static void r600_begin_query(struct pipe_context *ctx, struct pipe_query *query)
2045 {
2046 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2047 struct r600_query *rquery = (struct r600_query *)query;
2048
2049 rquery->result = 0;
2050 rquery->num_results = 0;
2051 r600_query_begin(&rctx->ctx, (struct r600_query *)query);
2052 }
2053
2054 static void r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
2055 {
2056 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2057
2058 r600_query_end(&rctx->ctx, (struct r600_query *)query);
2059 }
2060
2061 static boolean r600_get_query_result(struct pipe_context *ctx,
2062 struct pipe_query *query,
2063 boolean wait, void *vresult)
2064 {
2065 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2066 struct r600_query *rquery = (struct r600_query *)query;
2067
2068 if (rquery->num_results) {
2069 ctx->flush(ctx, 0, NULL);
2070 }
2071 return r600_context_query_result(&rctx->ctx, (struct r600_query *)query, wait, vresult);
2072 }
2073
2074 static void r600_init_query_functions2(struct r600_pipe_context *rctx)
2075 {
2076 rctx->context.create_query = r600_create_query;
2077 rctx->context.destroy_query = r600_destroy_query;
2078 rctx->context.begin_query = r600_begin_query;
2079 rctx->context.end_query = r600_end_query;
2080 rctx->context.get_query_result = r600_get_query_result;
2081 }
2082
2083 static struct pipe_context *r600_create_context2(struct pipe_screen *screen, void *priv)
2084 {
2085 struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
2086 struct r600_screen* rscreen = (struct r600_screen *)screen;
2087
2088 if (rctx == NULL)
2089 return NULL;
2090 rctx->context.winsys = rscreen->screen.winsys;
2091 rctx->context.screen = screen;
2092 rctx->context.priv = priv;
2093 rctx->context.destroy = r600_destroy_context;
2094 rctx->context.flush = r600_flush2;
2095
2096 /* Easy accessing of screen/winsys. */
2097 rctx->screen = rscreen;
2098 rctx->radeon = rscreen->radeon;
2099 rctx->family = r600_get_family(rctx->radeon);
2100
2101 r600_init_blit_functions2(rctx);
2102 r600_init_query_functions2(rctx);
2103 r600_init_context_resource_functions2(rctx);
2104
2105 switch (r600_get_family(rctx->radeon)) {
2106 case CHIP_R600:
2107 case CHIP_RV610:
2108 case CHIP_RV630:
2109 case CHIP_RV670:
2110 case CHIP_RV620:
2111 case CHIP_RV635:
2112 case CHIP_RS780:
2113 case CHIP_RS880:
2114 case CHIP_RV770:
2115 case CHIP_RV730:
2116 case CHIP_RV710:
2117 case CHIP_RV740:
2118 rctx->context.draw_vbo = r600_draw_vbo2;
2119 r600_init_state_functions2(rctx);
2120 if (r600_context_init(&rctx->ctx, rctx->radeon)) {
2121 r600_destroy_context(&rctx->context);
2122 return NULL;
2123 }
2124 r600_init_config2(rctx);
2125 break;
2126 case CHIP_CEDAR:
2127 case CHIP_REDWOOD:
2128 case CHIP_JUNIPER:
2129 case CHIP_CYPRESS:
2130 case CHIP_HEMLOCK:
2131 rctx->context.draw_vbo = evergreen_draw;
2132 evergreen_init_state_functions2(rctx);
2133 if (evergreen_context_init(&rctx->ctx, rctx->radeon)) {
2134 r600_destroy_context(&rctx->context);
2135 return NULL;
2136 }
2137 evergreen_init_config2(rctx);
2138 break;
2139 default:
2140 R600_ERR("unsupported family %d\n", r600_get_family(rctx->radeon));
2141 r600_destroy_context(&rctx->context);
2142 return NULL;
2143 }
2144
2145 rctx->upload_ib = u_upload_create(&rctx->context, 32 * 1024, 16,
2146 PIPE_BIND_INDEX_BUFFER);
2147 if (rctx->upload_ib == NULL) {
2148 r600_destroy_context(&rctx->context);
2149 return NULL;
2150 }
2151
2152 rctx->upload_vb = u_upload_create(&rctx->context, 128 * 1024, 16,
2153 PIPE_BIND_VERTEX_BUFFER);
2154 if (rctx->upload_vb == NULL) {
2155 r600_destroy_context(&rctx->context);
2156 return NULL;
2157 }
2158
2159 rctx->blitter = util_blitter_create(&rctx->context);
2160 if (rctx->blitter == NULL) {
2161 FREE(rctx);
2162 return NULL;
2163 }
2164
2165 return &rctx->context;
2166 }
2167
2168 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
2169 {
2170 switch(shader)
2171 {
2172 case PIPE_SHADER_FRAGMENT:
2173 case PIPE_SHADER_VERTEX:
2174 break;
2175 case PIPE_SHADER_GEOMETRY:
2176 /* TODO: support and enable geometry programs */
2177 return 0;
2178 default:
2179 /* TODO: support tessellation on Evergreen */
2180 return 0;
2181 }
2182
2183 /* TODO: all these should be fixed, since r600 surely supports much more! */
2184 switch (param) {
2185 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
2186 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
2187 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
2188 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
2189 return 16384;
2190 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
2191 return 8; /* FIXME */
2192 case PIPE_SHADER_CAP_MAX_INPUTS:
2193 if(shader == PIPE_SHADER_FRAGMENT)
2194 return 10;
2195 else
2196 return 16;
2197 case PIPE_SHADER_CAP_MAX_TEMPS:
2198 return 256; //max native temporaries
2199 case PIPE_SHADER_CAP_MAX_ADDRS:
2200 return 1; //max native address registers/* FIXME Isn't this equal to TEMPS? */
2201 case PIPE_SHADER_CAP_MAX_CONSTS:
2202 return 256; //max native parameters
2203 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
2204 return 1;
2205 case PIPE_SHADER_CAP_MAX_PREDS:
2206 return 0; /* FIXME */
2207 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
2208 return 1;
2209 default:
2210 return 0;
2211 }
2212 }
2213
2214 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
2215 const struct pipe_resource *templ);
2216 struct pipe_resource *r600_user_buffer_create2(struct pipe_screen *screen,
2217 void *ptr, unsigned bytes,
2218 unsigned bind)
2219 {
2220 struct pipe_resource *resource;
2221 struct r600_resource *rresource;
2222 struct pipe_resource desc;
2223 struct radeon *radeon = (struct radeon *)screen->winsys;
2224 void *rptr;
2225
2226 desc.screen = screen;
2227 desc.target = PIPE_BUFFER;
2228 desc.format = PIPE_FORMAT_R8_UNORM;
2229 desc.usage = PIPE_USAGE_IMMUTABLE;
2230 desc.bind = bind;
2231 desc.width0 = bytes;
2232 desc.height0 = 1;
2233 desc.depth0 = 1;
2234 desc.flags = 0;
2235 resource = r600_buffer_create(screen, &desc);
2236 if (resource == NULL) {
2237 return NULL;
2238 }
2239
2240 rresource = (struct r600_resource *)resource;
2241 rptr = radeon_ws_bo_map(radeon, rresource->bo, 0, NULL);
2242 memcpy(rptr, ptr, bytes);
2243 radeon_ws_bo_unmap(radeon, rresource->bo);
2244
2245 return resource;
2246 }
2247
2248 void r600_init_screen_texture_functions(struct pipe_screen *screen);
2249 struct pipe_screen *r600_screen_create2(struct radeon *radeon)
2250 {
2251 struct r600_screen *rscreen;
2252
2253 rscreen = CALLOC_STRUCT(r600_screen);
2254 if (rscreen == NULL) {
2255 return NULL;
2256 }
2257
2258 rscreen->radeon = radeon;
2259 rscreen->screen.winsys = (struct pipe_winsys*)radeon;
2260 rscreen->screen.destroy = r600_destroy_screen;
2261 rscreen->screen.get_name = r600_get_name;
2262 rscreen->screen.get_vendor = r600_get_vendor;
2263 rscreen->screen.get_param = r600_get_param;
2264 rscreen->screen.get_shader_param = r600_get_shader_param;
2265 rscreen->screen.get_paramf = r600_get_paramf;
2266 rscreen->screen.is_format_supported = r600_is_format_supported;
2267 rscreen->screen.context_create = r600_create_context2;
2268 r600_init_screen_texture_functions(&rscreen->screen);
2269 r600_init_screen_resource_functions(&rscreen->screen);
2270 // rscreen->screen.user_buffer_create = r600_user_buffer_create2;
2271
2272 return &rscreen->screen;
2273 }
2274
2275 int r600_upload_index_buffer2(struct r600_pipe_context *rctx, struct r600_drawl *draw)
2276 {
2277 struct pipe_resource *upload_buffer = NULL;
2278 unsigned index_offset = draw->index_buffer_offset;
2279 int ret = 0;
2280
2281 if (r600_buffer_is_user_buffer(draw->index_buffer)) {
2282 ret = u_upload_buffer(rctx->upload_ib,
2283 index_offset,
2284 draw->count * draw->index_size,
2285 draw->index_buffer,
2286 &index_offset,
2287 &upload_buffer);
2288 if (ret) {
2289 goto done;
2290 }
2291 draw->index_buffer_offset = index_offset;
2292 draw->index_buffer = upload_buffer;
2293 }
2294
2295 done:
2296 return ret;
2297 }
2298
2299 int r600_upload_user_buffers2(struct r600_pipe_context *rctx)
2300 {
2301 enum pipe_error ret = PIPE_OK;
2302 int i, nr;
2303
2304 nr = rctx->vertex_elements->count;
2305
2306 for (i = 0; i < nr; i++) {
2307 struct pipe_vertex_buffer *vb =
2308 &rctx->vertex_buffer[rctx->vertex_elements->elements[i].vertex_buffer_index];
2309
2310 if (r600_buffer_is_user_buffer(vb->buffer)) {
2311 struct pipe_resource *upload_buffer = NULL;
2312 unsigned offset = 0; /*vb->buffer_offset * 4;*/
2313 unsigned size = vb->buffer->width0;
2314 unsigned upload_offset;
2315 ret = u_upload_buffer(rctx->upload_vb,
2316 offset, size,
2317 vb->buffer,
2318 &upload_offset, &upload_buffer);
2319 if (ret)
2320 return ret;
2321
2322 pipe_resource_reference(&vb->buffer, NULL);
2323 vb->buffer = upload_buffer;
2324 vb->buffer_offset = upload_offset;
2325 }
2326 }
2327 return ret;
2328 }