projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: initial evergreen support in new path
[mesa.git] / src / gallium / drivers / r600 / r600_state2.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <pipebuffer/pb_buffer.h>
43 #include "r600.h"
44 #include "r600d.h"
45 #include "r700_sq.h"
46 struct radeon_state {
47 unsigned dummy;
48 };
49 #include "r600_resource.h"
50 #include "r600_shader.h"
51 #include "r600_pipe.h"
52 #include "r600_state_inlines.h"
53
54 /* r600_shader.c */
55 static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
56 {
57 struct r600_pipe_state *rstate = &shader->rstate;
58 struct r600_shader *rshader = &shader->shader;
59 unsigned spi_vs_out_id[10];
60 unsigned i, tmp;
61
62 /* clear previous register */
63 rstate->nregs = 0;
64
65 /* so far never got proper semantic id from tgsi */
66 for (i = 0; i < 10; i++) {
67 spi_vs_out_id[i] = 0;
68 }
69 for (i = 0; i < 32; i++) {
70 tmp = i << ((i & 3) * 8);
71 spi_vs_out_id[i / 4] |= tmp;
72 }
73 for (i = 0; i < 10; i++) {
74 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
75 R_028614_SPI_VS_OUT_ID_0 + i * 4,
76 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
77 }
78
79 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
80 R_0286C4_SPI_VS_OUT_CONFIG,
81 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
82 0xFFFFFFFF, NULL);
83 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
84 R_028868_SQ_PGM_RESOURCES_VS,
85 S_028868_NUM_GPRS(rshader->bc.ngpr) |
86 S_028868_STACK_SIZE(rshader->bc.nstack),
87 0xFFFFFFFF, NULL);
88 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
89 R_0288A4_SQ_PGM_RESOURCES_FS,
90 0x00000000, 0xFFFFFFFF, NULL);
91 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
92 R_0288D0_SQ_PGM_CF_OFFSET_VS,
93 0x00000000, 0xFFFFFFFF, NULL);
94 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
95 R_0288DC_SQ_PGM_CF_OFFSET_FS,
96 0x00000000, 0xFFFFFFFF, NULL);
97 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
98 R_028858_SQ_PGM_START_VS,
99 0x00000000, 0xFFFFFFFF, shader->bo);
100 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
101 R_028894_SQ_PGM_START_FS,
102 0x00000000, 0xFFFFFFFF, shader->bo);
103 }
104
105 static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
106 {
107 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
108 struct r600_pipe_state *rstate = &shader->rstate;
109 struct r600_shader *rshader = &shader->shader;
110 unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z;
111 boolean have_pos = FALSE;
112
113 /* clear previous register */
114 rstate->nregs = 0;
115
116 for (i = 0; i < rshader->ninput; i++) {
117 tmp = S_028644_SEMANTIC(i);
118 tmp |= S_028644_SEL_CENTROID(1);
119 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
120 have_pos = TRUE;
121 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
122 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
123 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
124 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
125 }
126 if (rctx->sprite_coord_enable & (1 << i)) {
127 tmp |= S_028644_PT_SPRITE_TEX(1);
128 }
129 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
130 }
131
132 exports_ps = 0;
133 num_cout = 0;
134 for (i = 0; i < rshader->noutput; i++) {
135 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
136 exports_ps |= 1;
137 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
138 num_cout++;
139 }
140 }
141 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
142 if (!exports_ps) {
143 /* always at least export 1 component per pixel */
144 exports_ps = 2;
145 }
146
147 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
148 S_0286CC_PERSP_GRADIENT_ENA(1);
149 spi_input_z = 0;
150 if (have_pos) {
151 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
152 S_0286CC_BARYC_SAMPLE_CNTL(1);
153 spi_input_z |= 1;
154 }
155 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
156 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286D0_SPI_PS_IN_CONTROL_1, 0x00000000, 0xFFFFFFFF, NULL);
157 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
158 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
159 R_028840_SQ_PGM_START_PS,
160 0x00000000, 0xFFFFFFFF, shader->bo);
161 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
162 R_028850_SQ_PGM_RESOURCES_PS,
163 S_028868_NUM_GPRS(rshader->bc.ngpr) |
164 S_028868_STACK_SIZE(rshader->bc.nstack),
165 0xFFFFFFFF, NULL);
166 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
167 R_028854_SQ_PGM_EXPORTS_PS,
168 exports_ps, 0xFFFFFFFF, NULL);
169 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
170 R_0288CC_SQ_PGM_CF_OFFSET_PS,
171 0x00000000, 0xFFFFFFFF, NULL);
172 }
173
174 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
175 {
176 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
177 struct r600_shader *rshader = &shader->shader;
178 void *ptr;
179
180 /* copy new shader */
181 if (shader->bo == NULL) {
182 shader->bo = radeon_ws_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0);
183 if (shader->bo == NULL) {
184 return -ENOMEM;
185 }
186 ptr = radeon_ws_bo_map(rctx->radeon, shader->bo, 0, NULL);
187 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
188 radeon_ws_bo_unmap(rctx->radeon, shader->bo);
189 }
190 /* build state */
191 rshader->flat_shade = rctx->flatshade;
192 switch (rshader->processor_type) {
193 case TGSI_PROCESSOR_VERTEX:
194 if (rshader->family >= CHIP_CEDAR) {
195 evergreen_pipe_shader_vs(ctx, shader);
196 } else {
197 r600_pipe_shader_vs(ctx, shader);
198 }
199 break;
200 case TGSI_PROCESSOR_FRAGMENT:
201 if (rshader->family >= CHIP_CEDAR) {
202 evergreen_pipe_shader_ps(ctx, shader);
203 } else {
204 r600_pipe_shader_ps(ctx, shader);
205 }
206 break;
207 default:
208 return -EINVAL;
209 }
210 r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
211 return 0;
212 }
213
214 static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rshader)
215 {
216 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
217 struct r600_shader *shader = &rshader->shader;
218 const struct util_format_description *desc;
219 enum pipe_format resource_format[160];
220 unsigned i, nresources = 0;
221 struct r600_bc *bc = &shader->bc;
222 struct r600_bc_cf *cf;
223 struct r600_bc_vtx *vtx;
224
225 if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
226 return 0;
227 for (i = 0; i < rctx->vertex_elements->count; i++) {
228 resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
229 }
230 radeon_ws_bo_reference(rctx->radeon, &rshader->bo, NULL);
231 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
232 switch (cf->inst) {
233 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
234 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
235 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
236 desc = util_format_description(resource_format[vtx->buffer_id]);
237 if (desc == NULL) {
238 R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
239 return -EINVAL;
240 }
241 vtx->dst_sel_x = desc->swizzle[0];
242 vtx->dst_sel_y = desc->swizzle[1];
243 vtx->dst_sel_z = desc->swizzle[2];
244 vtx->dst_sel_w = desc->swizzle[3];
245 }
246 break;
247 default:
248 break;
249 }
250 }
251 return r600_bc_build(&shader->bc);
252 }
253
254 int r600_pipe_shader_update2(struct pipe_context *ctx, struct r600_pipe_shader *shader)
255 {
256 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
257 int r;
258
259 if (shader == NULL)
260 return -EINVAL;
261 /* there should be enough input */
262 if (rctx->vertex_elements->count < shader->shader.bc.nresource) {
263 R600_ERR("%d resources provided, expecting %d\n",
264 rctx->vertex_elements->count, shader->shader.bc.nresource);
265 return -EINVAL;
266 }
267 r = r600_shader_update(ctx, shader);
268 if (r)
269 return r;
270 return r600_pipe_shader(ctx, shader);
271 }
272
273 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
274 int r600_pipe_shader_create2(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
275 {
276 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
277 int r;
278
279 //fprintf(stderr, "--------------------------------------------------------------\n");
280 //tgsi_dump(tokens, 0);
281 shader->shader.family = r600_get_family(rctx->radeon);
282 r = r600_shader_from_tgsi(tokens, &shader->shader);
283 if (r) {
284 R600_ERR("translation from TGSI failed !\n");
285 return r;
286 }
287 r = r600_bc_build(&shader->shader.bc);
288 if (r) {
289 R600_ERR("building bytecode failed !\n");
290 return r;
291 }
292 //fprintf(stderr, "______________________________________________________________\n");
293 return 0;
294 }
295 /* r600_shader.c END */
296
297 static const char* r600_get_vendor(struct pipe_screen* pscreen)
298 {
299 return "X.Org";
300 }
301
302 static const char* r600_get_name(struct pipe_screen* pscreen)
303 {
304 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
305 enum radeon_family family = r600_get_family(rscreen->radeon);
306
307 if (family >= CHIP_R600 && family < CHIP_RV770)
308 return "R600 (HD2XXX,HD3XXX)";
309 else
310 return "R700 (HD4XXX)";
311 }
312
313 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
314 {
315 switch (param) {
316 /* Supported features (boolean caps). */
317 case PIPE_CAP_NPOT_TEXTURES:
318 case PIPE_CAP_TWO_SIDED_STENCIL:
319 case PIPE_CAP_GLSL:
320 case PIPE_CAP_DUAL_SOURCE_BLEND:
321 case PIPE_CAP_ANISOTROPIC_FILTER:
322 case PIPE_CAP_POINT_SPRITE:
323 case PIPE_CAP_OCCLUSION_QUERY:
324 case PIPE_CAP_TEXTURE_SHADOW_MAP:
325 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
326 case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
327 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
328 case PIPE_CAP_SM3:
329 case PIPE_CAP_TEXTURE_SWIZZLE:
330 case PIPE_CAP_INDEP_BLEND_ENABLE:
331 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
332 case PIPE_CAP_DEPTH_CLAMP:
333 return 1;
334
335 /* Unsupported features (boolean caps). */
336 case PIPE_CAP_TIMER_QUERY:
337 case PIPE_CAP_STREAM_OUTPUT:
338 case PIPE_CAP_INDEP_BLEND_FUNC: /* FIXME allow this */
339 return 0;
340
341 /* Texturing. */
342 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
343 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
344 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
345 return 14;
346 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
347 /* FIXME allow this once infrastructure is there */
348 return 0;
349 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
350 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
351 return 16;
352
353 /* Render targets. */
354 case PIPE_CAP_MAX_RENDER_TARGETS:
355 /* FIXME some r6xx are buggy and can only do 4 */
356 return 8;
357
358 /* Fragment coordinate conventions. */
359 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
360 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
361 return 1;
362 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
363 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
364 return 0;
365
366 default:
367 R600_ERR("r600: unknown param %d\n", param);
368 return 0;
369 }
370 }
371
372 static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
373 {
374 switch (param) {
375 case PIPE_CAP_MAX_LINE_WIDTH:
376 case PIPE_CAP_MAX_LINE_WIDTH_AA:
377 case PIPE_CAP_MAX_POINT_WIDTH:
378 case PIPE_CAP_MAX_POINT_WIDTH_AA:
379 return 8192.0f;
380 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
381 return 16.0f;
382 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
383 return 16.0f;
384 default:
385 R600_ERR("r600: unsupported paramf %d\n", param);
386 return 0.0f;
387 }
388 }
389
390 static boolean r600_is_format_supported(struct pipe_screen* screen,
391 enum pipe_format format,
392 enum pipe_texture_target target,
393 unsigned sample_count,
394 unsigned usage,
395 unsigned geom_flags)
396 {
397 unsigned retval = 0;
398 if (target >= PIPE_MAX_TEXTURE_TYPES) {
399 R600_ERR("r600: unsupported texture type %d\n", target);
400 return FALSE;
401 }
402
403 /* Multisample */
404 if (sample_count > 1)
405 return FALSE;
406
407 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
408 r600_is_sampler_format_supported(format)) {
409 retval |= PIPE_BIND_SAMPLER_VIEW;
410 }
411
412 if ((usage & (PIPE_BIND_RENDER_TARGET |
413 PIPE_BIND_DISPLAY_TARGET |
414 PIPE_BIND_SCANOUT |
415 PIPE_BIND_SHARED)) &&
416 r600_is_colorbuffer_format_supported(format)) {
417 retval |= usage &
418 (PIPE_BIND_RENDER_TARGET |
419 PIPE_BIND_DISPLAY_TARGET |
420 PIPE_BIND_SCANOUT |
421 PIPE_BIND_SHARED);
422 }
423
424 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
425 r600_is_zs_format_supported(format)) {
426 retval |= PIPE_BIND_DEPTH_STENCIL;
427 }
428
429 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
430 r600_is_vertex_format_supported(format))
431 retval |= PIPE_BIND_VERTEX_BUFFER;
432
433 if (usage & PIPE_BIND_TRANSFER_READ)
434 retval |= PIPE_BIND_TRANSFER_READ;
435 if (usage & PIPE_BIND_TRANSFER_WRITE)
436 retval |= PIPE_BIND_TRANSFER_WRITE;
437
438 return retval == usage;
439 }
440
441 static void r600_destroy_screen(struct pipe_screen* pscreen)
442 {
443 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
444
445 if (rscreen == NULL)
446 return;
447 FREE(rscreen);
448 }
449
450 int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
451 static void r600_draw_common(struct r600_drawl *draw)
452 {
453 struct r600_pipe_context *rctx = (struct r600_pipe_context *)draw->ctx;
454 struct r600_pipe_state *rstate;
455 struct r600_resource *rbuffer;
456 unsigned i, j, offset, format, prim;
457 u32 vgt_dma_index_type, vgt_draw_initiator, mask;
458 struct pipe_vertex_buffer *vertex_buffer;
459 struct r600_draw rdraw;
460 struct r600_pipe_state vgt;
461
462
463 switch (draw->index_size) {
464 case 2:
465 vgt_draw_initiator = 0;
466 vgt_dma_index_type = 0;
467 break;
468 case 4:
469 vgt_draw_initiator = 0;
470 vgt_dma_index_type = 1;
471 break;
472 case 0:
473 vgt_draw_initiator = 2;
474 vgt_dma_index_type = 0;
475 break;
476 default:
477 R600_ERR("unsupported index size %d\n", draw->index_size);
478 return;
479 }
480 if (r600_conv_pipe_prim(draw->mode, &prim))
481 return;
482
483 /* rebuild vertex shader if input format changed */
484 if (r600_pipe_shader_update2(&rctx->context, rctx->vs_shader))
485 return;
486 if (r600_pipe_shader_update2(&rctx->context, rctx->ps_shader))
487 return;
488
489 for (i = 0 ; i < rctx->vertex_elements->count; i++) {
490 rstate = &rctx->vs_resource[i];
491 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
492 vertex_buffer = &rctx->vertex_buffer[j];
493 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
494 offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
495 format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
496 rstate->id = R600_PIPE_STATE_RESOURCE;
497 rstate->nregs = 0;
498
499 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
500 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
501 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE,
502 R_038008_RESOURCE0_WORD2,
503 S_038008_STRIDE(vertex_buffer->stride) |
504 S_038008_DATA_FORMAT(format),
505 0xFFFFFFFF, NULL);
506 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_03800C_RESOURCE0_WORD3, 0x00000000, 0xFFFFFFFF, NULL);
507 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
508 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
509 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038018_RESOURCE0_WORD6, 0xC0000000, 0xFFFFFFFF, NULL);
510 r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, i);
511 }
512
513 mask = 0;
514 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
515 mask |= (0xF << (i * 4));
516 }
517
518 vgt.id = R600_PIPE_STATE_VGT;
519 vgt.nregs = 0;
520 r600_pipe_state_add_reg(&vgt, R600_GROUP_CONFIG, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
521 r600_pipe_state_add_reg(&vgt, R600_GROUP_CONTEXT, R_028408_VGT_INDX_OFFSET, draw->start, 0xFFFFFFFF, NULL);
522 r600_pipe_state_add_reg(&vgt, R600_GROUP_CONTEXT, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
523 r600_context_pipe_state_set(&rctx->ctx, &vgt);
524
525 rdraw.vgt_num_indices = draw->count;
526 rdraw.vgt_num_instances = 1;
527 rdraw.vgt_index_type = vgt_dma_index_type;
528 rdraw.vgt_draw_initiator = vgt_draw_initiator;
529 rdraw.indices = NULL;
530 if (draw->index_buffer) {
531 rbuffer = (struct r600_resource*)draw->index_buffer;
532 rdraw.indices = rbuffer->bo;
533 rdraw.indices_bo_offset = 0;
534 }
535 r600_context_draw(&rctx->ctx, &rdraw);
536 }
537
538 static void r600_draw_vbo2(struct pipe_context *ctx, const struct pipe_draw_info *info)
539 {
540 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
541 struct r600_drawl draw;
542
543 assert(info->index_bias == 0);
544
545 draw.ctx = ctx;
546 draw.mode = info->mode;
547 draw.start = info->start;
548 draw.count = info->count;
549 if (info->indexed && rctx->index_buffer.buffer) {
550 draw.index_size = rctx->index_buffer.index_size;
551 draw.index_buffer = rctx->index_buffer.buffer;
552 assert(rctx->index_buffer.offset %
553 rctx->index_buffer.index_size == 0);
554 draw.start += rctx->index_buffer.offset /
555 rctx->index_buffer.index_size;
556 } else {
557 draw.index_size = 0;
558 draw.index_buffer = NULL;
559 }
560 r600_draw_common(&draw);
561 }
562
563 static void r600_flush2(struct pipe_context *ctx, unsigned flags,
564 struct pipe_fence_handle **fence)
565 {
566 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
567 #if 0
568 static int dc = 0;
569 char dname[256];
570 #endif
571
572 if (!rctx->ctx.pm4_cdwords)
573 return;
574
575 #if 0
576 sprintf(dname, "gallium-%08d.bof", dc);
577 if (dc < 20) {
578 r600_context_dump_bof(&rctx->ctx, dname);
579 R600_ERR("dumped %s\n", dname);
580 }
581 dc++;
582 #endif
583 r600_context_flush(&rctx->ctx);
584 }
585
586 static void r600_destroy_context(struct pipe_context *context)
587 {
588 struct r600_pipe_context *rctx = (struct r600_pipe_context *)context;
589
590 r600_context_fini(&rctx->ctx);
591 for (int i = 0; i < R600_PIPE_NSTATES; i++) {
592 free(rctx->states[i]);
593 }
594 FREE(rctx);
595 }
596
597 static void r600_blitter_save_states(struct pipe_context *ctx)
598 {
599 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
600
601 util_blitter_save_blend(rctx->blitter, rctx->states[R600_PIPE_STATE_BLEND]);
602 util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->states[R600_PIPE_STATE_DSA]);
603 if (rctx->states[R600_PIPE_STATE_STENCIL_REF]) {
604 util_blitter_save_stencil_ref(rctx->blitter, &rctx->stencil_ref);
605 }
606 util_blitter_save_rasterizer(rctx->blitter, rctx->states[R600_PIPE_STATE_RASTERIZER]);
607 util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader);
608 util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader);
609 util_blitter_save_vertex_elements(rctx->blitter, rctx->vertex_elements);
610 if (rctx->states[R600_PIPE_STATE_VIEWPORT]) {
611 util_blitter_save_viewport(rctx->blitter, &rctx->viewport);
612 }
613 if (rctx->states[R600_PIPE_STATE_CLIP]) {
614 util_blitter_save_clip(rctx->blitter, &rctx->clip);
615 }
616 util_blitter_save_vertex_buffers(rctx->blitter, rctx->nvertex_buffer, rctx->vertex_buffer);
617
618 rctx->vertex_elements = NULL;
619
620 /* TODO queries */
621 }
622
623 static void r600_clear(struct pipe_context *ctx, unsigned buffers,
624 const float *rgba, double depth, unsigned stencil)
625 {
626 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
627 struct pipe_framebuffer_state *fb = &rctx->framebuffer;
628
629 r600_blitter_save_states(ctx);
630 util_blitter_clear(rctx->blitter, fb->width, fb->height,
631 fb->nr_cbufs, buffers, rgba, depth,
632 stencil);
633 }
634
635 static void r600_clear_render_target(struct pipe_context *ctx,
636 struct pipe_surface *dst,
637 const float *rgba,
638 unsigned dstx, unsigned dsty,
639 unsigned width, unsigned height)
640 {
641 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
642 struct pipe_framebuffer_state *fb = &rctx->framebuffer;
643
644 util_blitter_save_framebuffer(rctx->blitter, fb);
645 util_blitter_clear_render_target(rctx->blitter, dst, rgba,
646 dstx, dsty, width, height);
647 }
648
649 static void r600_clear_depth_stencil(struct pipe_context *ctx,
650 struct pipe_surface *dst,
651 unsigned clear_flags,
652 double depth,
653 unsigned stencil,
654 unsigned dstx, unsigned dsty,
655 unsigned width, unsigned height)
656 {
657 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
658 struct pipe_framebuffer_state *fb = &rctx->framebuffer;
659
660 util_blitter_save_framebuffer(rctx->blitter, fb);
661 util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil,
662 dstx, dsty, width, height);
663 }
664
665
666 static void r600_resource_copy_region(struct pipe_context *ctx,
667 struct pipe_resource *dst,
668 struct pipe_subresource subdst,
669 unsigned dstx, unsigned dsty, unsigned dstz,
670 struct pipe_resource *src,
671 struct pipe_subresource subsrc,
672 unsigned srcx, unsigned srcy, unsigned srcz,
673 unsigned width, unsigned height)
674 {
675 util_resource_copy_region(ctx, dst, subdst, dstx, dsty, dstz,
676 src, subsrc, srcx, srcy, srcz, width, height);
677 }
678
679 static void r600_init_blit_functions2(struct r600_pipe_context *rctx)
680 {
681 rctx->context.clear = r600_clear;
682 rctx->context.clear_render_target = r600_clear_render_target;
683 rctx->context.clear_depth_stencil = r600_clear_depth_stencil;
684 rctx->context.resource_copy_region = r600_resource_copy_region;
685 }
686
687 static void r600_init_context_resource_functions2(struct r600_pipe_context *r600)
688 {
689 r600->context.get_transfer = u_get_transfer_vtbl;
690 r600->context.transfer_map = u_transfer_map_vtbl;
691 r600->context.transfer_flush_region = u_transfer_flush_region_vtbl;
692 r600->context.transfer_unmap = u_transfer_unmap_vtbl;
693 r600->context.transfer_destroy = u_transfer_destroy_vtbl;
694 r600->context.transfer_inline_write = u_transfer_inline_write_vtbl;
695 r600->context.is_resource_referenced = u_is_resource_referenced_vtbl;
696 }
697
698 static void r600_set_blend_color(struct pipe_context *ctx,
699 const struct pipe_blend_color *state)
700 {
701 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
702 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
703
704 if (rstate == NULL)
705 return;
706
707 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
708 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
709 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
710 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
711 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
712 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
713 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
714 r600_context_pipe_state_set(&rctx->ctx, rstate);
715 }
716
717 static void *r600_create_blend_state(struct pipe_context *ctx,
718 const struct pipe_blend_state *state)
719 {
720 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
721 struct r600_pipe_state *rstate;
722 u32 color_control, target_mask;
723
724 if (blend == NULL) {
725 return NULL;
726 }
727 rstate = &blend->rstate;
728
729 rstate->id = R600_PIPE_STATE_BLEND;
730
731 target_mask = 0;
732 color_control = S_028808_PER_MRT_BLEND(1);
733 if (state->logicop_enable) {
734 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
735 } else {
736 color_control |= (0xcc << 16);
737 }
738 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
739 if (state->independent_blend_enable) {
740 for (int i = 0; i < 8; i++) {
741 if (state->rt[i].blend_enable) {
742 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
743 }
744 target_mask |= (state->rt[i].colormask << (4 * i));
745 }
746 } else {
747 for (int i = 0; i < 8; i++) {
748 if (state->rt[0].blend_enable) {
749 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
750 }
751 target_mask |= (state->rt[0].colormask << (4 * i));
752 }
753 }
754 blend->cb_target_mask = target_mask;
755 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028808_CB_COLOR_CONTROL,
756 color_control, 0xFFFFFFFF, NULL);
757
758 for (int i = 0; i < 8; i++) {
759 unsigned eqRGB = state->rt[i].rgb_func;
760 unsigned srcRGB = state->rt[i].rgb_src_factor;
761 unsigned dstRGB = state->rt[i].rgb_dst_factor;
762
763 unsigned eqA = state->rt[i].alpha_func;
764 unsigned srcA = state->rt[i].alpha_src_factor;
765 unsigned dstA = state->rt[i].alpha_dst_factor;
766 uint32_t bc = 0;
767
768 if (!state->rt[i].blend_enable)
769 continue;
770
771 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
772 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
773 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
774
775 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
776 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
777 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
778 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
779 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
780 }
781
782 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
783 if (i == 0) {
784 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
785 }
786 }
787 return rstate;
788 }
789
790 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
791 {
792 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
793 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
794 struct r600_pipe_state *rstate;
795
796 if (state == NULL)
797 return;
798 rstate = &blend->rstate;
799 rctx->states[rstate->id] = rstate;
800 rctx->cb_target_mask = blend->cb_target_mask;
801 r600_context_pipe_state_set(&rctx->ctx, rstate);
802 }
803
804 static void *r600_create_dsa_state(struct pipe_context *ctx,
805 const struct pipe_depth_stencil_alpha_state *state)
806 {
807 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
808 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
809 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
810
811 if (rstate == NULL) {
812 return NULL;
813 }
814
815 rstate->id = R600_PIPE_STATE_DSA;
816 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
817 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
818 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
819 * be set if shader use texkill instruction
820 */
821 db_shader_control = 0x210;
822 stencil_ref_mask = 0;
823 stencil_ref_mask_bf = 0;
824 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
825 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
826 S_028800_ZFUNC(state->depth.func);
827
828 /* stencil */
829 if (state->stencil[0].enabled) {
830 db_depth_control |= S_028800_STENCIL_ENABLE(1);
831 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
832 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
833 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
834 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
835
836
837 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
838 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
839 if (state->stencil[1].enabled) {
840 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
841 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
842 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
843 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
844 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
845 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
846 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
847 }
848 }
849
850 /* alpha */
851 alpha_test_control = 0;
852 alpha_ref = 0;
853 if (state->alpha.enabled) {
854 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
855 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
856 alpha_ref = fui(state->alpha.ref_value);
857 }
858
859 /* misc */
860 db_render_control = 0;
861 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
862 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
863 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
864 /* TODO db_render_override depends on query */
865 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
866 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
867 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
868 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
869 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
870 0xFFFFFFFF & C_028430_STENCILREF, NULL);
871 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
872 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
873 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
874 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
875 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
876 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
877 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
878 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
879 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
880 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
881 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
882 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
883 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
884 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
885
886 return rstate;
887 }
888
889 static void *r600_create_rs_state(struct pipe_context *ctx,
890 const struct pipe_rasterizer_state *state)
891 {
892 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
893 struct r600_pipe_state *rstate;
894 float offset_units = 0, offset_scale = 0;
895 unsigned offset_db_fmt_cntl = 0;
896 unsigned tmp;
897 unsigned prov_vtx = 1;
898
899 if (rs == NULL) {
900 return NULL;
901 }
902
903 rstate = &rs->rstate;
904 rs->flatshade = state->flatshade;
905 rs->sprite_coord_enable = state->sprite_coord_enable;
906
907 rstate->id = R600_PIPE_STATE_RASTERIZER;
908 if (state->flatshade_first)
909 prov_vtx = 0;
910 tmp = 0x00000001;
911 if (state->sprite_coord_enable) {
912 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
913 S_0286D4_PNT_SPRITE_OVRD_X(2) |
914 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
915 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
916 S_0286D4_PNT_SPRITE_OVRD_W(1);
917 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
918 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
919 }
920 }
921 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
922
923 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028814_PA_SU_SC_MODE_CNTL,
924 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
925 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
926 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
927 S_028814_FACE(!state->front_ccw) |
928 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
929 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
930 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri), 0xFFFFFFFF, NULL);
931 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02881C_PA_CL_VS_OUT_CNTL,
932 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
933 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
934 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
935 /* point size 12.4 fixed point */
936 tmp = (unsigned)(state->point_size * 8.0);
937 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
938 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
939 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A08_PA_SU_LINE_CNTL, 0x00000008, 0xFFFFFFFF, NULL);
940 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
941 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
942 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
943 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
944 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
945 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
946 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
947 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
948 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
949 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, fui(offset_scale), 0xFFFFFFFF, NULL);
950 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units), 0xFFFFFFFF, NULL);
951 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, fui(offset_scale), 0xFFFFFFFF, NULL);
952 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units), 0xFFFFFFFF, NULL);
953 return rstate;
954 }
955
956 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
957 {
958 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
959 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
960
961 if (state == NULL)
962 return;
963
964 if (rctx->flatshade != rs->flatshade) {
965 // rctx->ps_rebuild = TRUE;
966 }
967 if (rctx->sprite_coord_enable != rs->sprite_coord_enable) {
968 // rctx->ps_rebuild = TRUE;
969 }
970 rctx->flatshade = rs->flatshade;
971 rctx->sprite_coord_enable = rs->sprite_coord_enable;
972
973 rctx->states[rs->rstate.id] = &rs->rstate;
974 r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
975 }
976
977 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
978 {
979 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
980 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
981
982 if (rctx->states[rs->rstate.id] == &rs->rstate) {
983 rctx->states[rs->rstate.id] = NULL;
984 }
985 free(rs);
986 }
987
988 static void *r600_create_sampler_state(struct pipe_context *ctx,
989 const struct pipe_sampler_state *state)
990 {
991 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
992 union util_color uc;
993
994 if (rstate == NULL) {
995 return NULL;
996 }
997
998 rstate->id = R600_PIPE_STATE_SAMPLER;
999 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1000 r600_pipe_state_add_reg(rstate, R600_GROUP_SAMPLER, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
1001 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1002 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1003 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1004 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
1005 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
1006 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1007 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1008 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
1009 /* FIXME LOD it depends on texture base level ... */
1010 r600_pipe_state_add_reg(rstate, R600_GROUP_SAMPLER, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
1011 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1012 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1013 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
1014 r600_pipe_state_add_reg(rstate, R600_GROUP_SAMPLER, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
1015 if (uc.ui) {
1016 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
1017 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
1018 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
1019 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
1020 }
1021 return rstate;
1022 }
1023
1024 static void *r600_create_vertex_elements(struct pipe_context *ctx,
1025 unsigned count,
1026 const struct pipe_vertex_element *elements)
1027 {
1028 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
1029
1030 assert(count < 32);
1031 v->count = count;
1032 v->refcount = 1;
1033 memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
1034 return v;
1035 }
1036
1037 static void r600_sampler_view_destroy(struct pipe_context *ctx,
1038 struct pipe_sampler_view *state)
1039 {
1040 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
1041
1042 pipe_resource_reference(&state->texture, NULL);
1043 FREE(resource);
1044 }
1045
1046 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
1047 struct pipe_resource *texture,
1048 const struct pipe_sampler_view *state)
1049 {
1050 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
1051 struct r600_pipe_state *rstate;
1052 const struct util_format_description *desc;
1053 struct r600_resource_texture *tmp;
1054 struct r600_resource *rbuffer;
1055 unsigned format;
1056 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1057 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1058 struct radeon_ws_bo *bo[2];
1059
1060 if (resource == NULL)
1061 return NULL;
1062 rstate = &resource->state;
1063
1064 /* initialize base object */
1065 resource->base = *state;
1066 resource->base.texture = NULL;
1067 pipe_reference(NULL, &texture->reference);
1068 resource->base.texture = texture;
1069 resource->base.reference.count = 1;
1070 resource->base.context = ctx;
1071
1072 swizzle[0] = state->swizzle_r;
1073 swizzle[1] = state->swizzle_g;
1074 swizzle[2] = state->swizzle_b;
1075 swizzle[3] = state->swizzle_a;
1076 format = r600_translate_texformat(texture->format,
1077 swizzle,
1078 &word4, &yuv_format);
1079 if (format == ~0) {
1080 format = 0;
1081 }
1082 desc = util_format_description(texture->format);
1083 if (desc == NULL) {
1084 R600_ERR("unknow format %d\n", texture->format);
1085 }
1086 tmp = (struct r600_resource_texture*)texture;
1087 rbuffer = &tmp->resource;
1088 bo[0] = rbuffer->bo;
1089 bo[1] = rbuffer->bo;
1090 /* FIXME depth texture decompression */
1091 if (tmp->depth) {
1092 #if 0
1093 r = r600_texture_from_depth(ctx, tmp, view->first_level);
1094 if (r) {
1095 return;
1096 }
1097 bo[0] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
1098 bo[1] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
1099 #endif
1100 }
1101 pitch = align(tmp->pitch[0] / tmp->bpt, 8);
1102
1103 /* FIXME properly handle first level != 0 */
1104 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038000_RESOURCE0_WORD0,
1105 S_038000_DIM(r600_tex_dim(texture->target)) |
1106 S_038000_TILE_MODE(array_mode) |
1107 S_038000_TILE_TYPE(tile_type) |
1108 S_038000_PITCH((pitch / 8) - 1) |
1109 S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
1110 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038004_RESOURCE0_WORD1,
1111 S_038004_TEX_HEIGHT(texture->height0 - 1) |
1112 S_038004_TEX_DEPTH(texture->depth0 - 1) |
1113 S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
1114 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038008_RESOURCE0_WORD2,
1115 tmp->offset[0] >> 8, 0xFFFFFFFF, bo[0]);
1116 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_03800C_RESOURCE0_WORD3,
1117 tmp->offset[1] >> 8, 0xFFFFFFFF, bo[1]);
1118 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038010_RESOURCE0_WORD4,
1119 word4 | S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
1120 S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
1121 S_038010_REQUEST_SIZE(1) |
1122 S_038010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
1123 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038014_RESOURCE0_WORD5,
1124 S_038014_LAST_LEVEL(state->last_level) |
1125 S_038014_BASE_ARRAY(0) |
1126 S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL);
1127 r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038018_RESOURCE0_WORD6,
1128 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
1129
1130 return &resource->base;
1131 }
1132
1133 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1134 struct pipe_sampler_view **views)
1135 {
1136 /* TODO */
1137 assert(1);
1138 }
1139
1140 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1141 struct pipe_sampler_view **views)
1142 {
1143 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1144 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1145
1146 for (int i = 0; i < count; i++) {
1147 if (resource[i]) {
1148 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
1149 }
1150 }
1151 }
1152
1153 static void r600_bind_state(struct pipe_context *ctx, void *state)
1154 {
1155 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1156 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
1157
1158 if (state == NULL)
1159 return;
1160 rctx->states[rstate->id] = rstate;
1161 r600_context_pipe_state_set(&rctx->ctx, rstate);
1162 }
1163
1164 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1165 {
1166 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1167 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1168
1169 for (int i = 0; i < count; i++) {
1170 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
1171 }
1172 }
1173
1174 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1175 {
1176 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1177 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1178
1179 /* TODO implement */
1180 for (int i = 0; i < count; i++) {
1181 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
1182 }
1183 }
1184
1185 static void r600_delete_state(struct pipe_context *ctx, void *state)
1186 {
1187 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1188 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
1189
1190 if (rctx->states[rstate->id] == rstate) {
1191 rctx->states[rstate->id] = NULL;
1192 }
1193 for (int i = 0; i < rstate->nregs; i++) {
1194 radeon_ws_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
1195 }
1196 free(rstate);
1197 }
1198
1199 static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
1200 {
1201 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
1202
1203 if (v == NULL)
1204 return;
1205 if (--v->refcount)
1206 return;
1207 free(v);
1208 }
1209
1210 static void r600_set_clip_state(struct pipe_context *ctx,
1211 const struct pipe_clip_state *state)
1212 {
1213 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1214 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1215
1216 if (rstate == NULL)
1217 return;
1218
1219 rctx->clip = *state;
1220 rstate->id = R600_PIPE_STATE_CLIP;
1221 for (int i = 0; i < state->nr; i++) {
1222 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1223 R_028E20_PA_CL_UCP0_X + i * 4,
1224 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
1225 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1226 R_028E24_PA_CL_UCP0_Y + i * 4,
1227 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
1228 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1229 R_028E28_PA_CL_UCP0_Z + i * 4,
1230 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
1231 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1232 R_028E2C_PA_CL_UCP0_W + i * 4,
1233 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
1234 }
1235 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028810_PA_CL_CLIP_CNTL,
1236 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
1237 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
1238 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
1239
1240 free(rctx->states[R600_PIPE_STATE_CLIP]);
1241 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1242 r600_context_pipe_state_set(&rctx->ctx, rstate);
1243 }
1244
1245 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
1246 {
1247 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1248 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
1249
1250 r600_delete_vertex_element(ctx, rctx->vertex_elements);
1251 rctx->vertex_elements = v;
1252 if (v) {
1253 v->refcount++;
1254 // rctx->vs_rebuild = TRUE;
1255 }
1256 }
1257
1258 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1259 const struct pipe_poly_stipple *state)
1260 {
1261 }
1262
1263 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1264 {
1265 }
1266
1267 static void r600_set_scissor_state(struct pipe_context *ctx,
1268 const struct pipe_scissor_state *state)
1269 {
1270 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1271 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1272 u32 tl, br;
1273
1274 if (rstate == NULL)
1275 return;
1276
1277 rstate->id = R600_PIPE_STATE_SCISSOR;
1278 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1279 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1280 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1281 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1282 0xFFFFFFFF, NULL);
1283 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1284 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1285 0xFFFFFFFF, NULL);
1286 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1287 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1288 0xFFFFFFFF, NULL);
1289 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1290 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1291 0xFFFFFFFF, NULL);
1292 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1293 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1294 0xFFFFFFFF, NULL);
1295 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1296 R_028214_PA_SC_CLIPRECT_0_BR, br,
1297 0xFFFFFFFF, NULL);
1298 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1299 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1300 0xFFFFFFFF, NULL);
1301 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1302 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1303 0xFFFFFFFF, NULL);
1304 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1305 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1306 0xFFFFFFFF, NULL);
1307 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1308 R_028224_PA_SC_CLIPRECT_2_BR, br,
1309 0xFFFFFFFF, NULL);
1310 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1311 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1312 0xFFFFFFFF, NULL);
1313 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1314 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1315 0xFFFFFFFF, NULL);
1316 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1317 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1318 0xFFFFFFFF, NULL);
1319 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1320 R_02820C_PA_SC_CLIPRECT_RULE, 0x0000FFFF,
1321 0xFFFFFFFF, NULL);
1322 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1323 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1324 0xFFFFFFFF, NULL);
1325
1326 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1327 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1328 r600_context_pipe_state_set(&rctx->ctx, rstate);
1329 }
1330
1331 static void r600_set_stencil_ref(struct pipe_context *ctx,
1332 const struct pipe_stencil_ref *state)
1333 {
1334 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1335 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1336 u32 tmp;
1337
1338 if (rstate == NULL)
1339 return;
1340
1341 rctx->stencil_ref = *state;
1342 rstate->id = R600_PIPE_STATE_STENCIL_REF;
1343 tmp = S_028430_STENCILREF(state->ref_value[0]);
1344 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1345 R_028430_DB_STENCILREFMASK, tmp,
1346 ~C_028430_STENCILREF, NULL);
1347 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
1348 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1349 R_028434_DB_STENCILREFMASK_BF, tmp,
1350 ~C_028434_STENCILREF_BF, NULL);
1351
1352 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
1353 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
1354 r600_context_pipe_state_set(&rctx->ctx, rstate);
1355 }
1356
1357 static void r600_set_viewport_state(struct pipe_context *ctx,
1358 const struct pipe_viewport_state *state)
1359 {
1360 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1361 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1362
1363 if (rstate == NULL)
1364 return;
1365
1366 rctx->viewport = *state;
1367 rstate->id = R600_PIPE_STATE_VIEWPORT;
1368 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
1369 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
1370 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
1371 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
1372 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
1373 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
1374 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
1375 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
1376 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
1377
1378 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1379 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1380 r600_context_pipe_state_set(&rctx->ctx, rstate);
1381 }
1382
1383 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1384 const struct pipe_framebuffer_state *state, int cb)
1385 {
1386 struct r600_resource_texture *rtex;
1387 struct r600_resource *rbuffer;
1388 unsigned level = state->cbufs[cb]->level;
1389 unsigned pitch, slice;
1390 unsigned color_info;
1391 unsigned format, swap, ntype;
1392 const struct util_format_description *desc;
1393 struct radeon_ws_bo *bo[3];
1394
1395 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1396 rbuffer = &rtex->resource;
1397 bo[0] = rbuffer->bo;
1398 bo[1] = rbuffer->bo;
1399 bo[2] = rbuffer->bo;
1400
1401 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
1402 slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
1403 ntype = 0;
1404 desc = util_format_description(rtex->resource.base.b.format);
1405 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1406 ntype = V_0280A0_NUMBER_SRGB;
1407
1408 format = r600_translate_colorformat(rtex->resource.base.b.format);
1409 swap = r600_translate_colorswap(rtex->resource.base.b.format);
1410 color_info = S_0280A0_FORMAT(format) |
1411 S_0280A0_COMP_SWAP(swap) |
1412 S_0280A0_BLEND_CLAMP(1) |
1413 S_0280A0_SOURCE_FORMAT(1) |
1414 S_0280A0_NUMBER_TYPE(ntype);
1415
1416 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1417 R_028040_CB_COLOR0_BASE + cb * 4,
1418 state->cbufs[cb]->offset >> 8, 0xFFFFFFFF, bo[0]);
1419 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1420 R_0280A0_CB_COLOR0_INFO + cb * 4,
1421 color_info, 0xFFFFFFFF, NULL);
1422 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1423 R_028060_CB_COLOR0_SIZE + cb * 4,
1424 S_028060_PITCH_TILE_MAX(pitch) |
1425 S_028060_SLICE_TILE_MAX(slice),
1426 0xFFFFFFFF, NULL);
1427 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1428 R_028080_CB_COLOR0_VIEW + cb * 4,
1429 0x00000000, 0xFFFFFFFF, NULL);
1430 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1431 R_0280E0_CB_COLOR0_FRAG + cb * 4,
1432 0x00000000, 0xFFFFFFFF, bo[1]);
1433 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1434 R_0280C0_CB_COLOR0_TILE + cb * 4,
1435 0x00000000, 0xFFFFFFFF, bo[2]);
1436 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1437 R_028100_CB_COLOR0_MASK + cb * 4,
1438 0x00000000, 0xFFFFFFFF, NULL);
1439 }
1440
1441 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1442 const struct pipe_framebuffer_state *state)
1443 {
1444 struct r600_resource_texture *rtex;
1445 struct r600_resource *rbuffer;
1446 unsigned level;
1447 unsigned pitch, slice, format;
1448
1449 if (state->zsbuf == NULL)
1450 return;
1451
1452 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1453 rtex->tiled = 1;
1454 rtex->array_mode = 2;
1455 rtex->tile_type = 1;
1456 rtex->depth = 1;
1457 rbuffer = &rtex->resource;
1458
1459 level = state->zsbuf->level;
1460 pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
1461 slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
1462 format = r600_translate_dbformat(state->zsbuf->texture->format);
1463
1464 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02800C_DB_DEPTH_BASE,
1465 state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
1466 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028000_DB_DEPTH_SIZE,
1467 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1468 0xFFFFFFFF, NULL);
1469 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
1470 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028010_DB_DEPTH_INFO,
1471 S_028010_ARRAY_MODE(rtex->array_mode) | S_028010_FORMAT(format),
1472 0xFFFFFFFF, NULL);
1473 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D34_DB_PREFETCH_LIMIT,
1474 (state->zsbuf->height / 8) - 1, 0xFFFFFFFF, NULL);
1475 }
1476
1477 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1478 const struct pipe_framebuffer_state *state)
1479 {
1480 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1481 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1482 u32 shader_mask, tl, br, shader_control, target_mask;
1483
1484 if (rstate == NULL)
1485 return;
1486
1487 /* unreference old buffer and reference new one */
1488 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1489 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
1490 pipe_surface_reference(&rctx->framebuffer.cbufs[i], NULL);
1491 }
1492 for (int i = 0; i < state->nr_cbufs; i++) {
1493 pipe_surface_reference(&rctx->framebuffer.cbufs[i], state->cbufs[i]);
1494 }
1495 pipe_surface_reference(&rctx->framebuffer.zsbuf, state->zsbuf);
1496 rctx->framebuffer = *state;
1497
1498 /* build states */
1499 for (int i = 0; i < state->nr_cbufs; i++) {
1500 r600_cb(rctx, rstate, state, i);
1501 }
1502 if (state->zsbuf) {
1503 r600_db(rctx, rstate, state);
1504 }
1505
1506 target_mask = 0x00000000;
1507 target_mask = 0xFFFFFFFF;
1508 shader_mask = 0;
1509 shader_control = 0;
1510 for (int i = 0; i < state->nr_cbufs; i++) {
1511 target_mask ^= 0xf << (i * 4);
1512 shader_mask |= 0xf << (i * 4);
1513 shader_control |= 1 << i;
1514 }
1515 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1516 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1517
1518 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1519 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1520 0xFFFFFFFF, NULL);
1521 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1522 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1523 0xFFFFFFFF, NULL);
1524 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1525 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1526 0xFFFFFFFF, NULL);
1527 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
1528 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1529 0xFFFFFFFF, NULL);
1530
1531 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0287A0_CB_SHADER_CONTROL,
1532 shader_control, 0xFFFFFFFF, NULL);
1533 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028238_CB_TARGET_MASK,
1534 0x00000000, target_mask, NULL);
1535 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02823C_CB_SHADER_MASK,
1536 shader_mask, 0xFFFFFFFF, NULL);
1537 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C04_PA_SC_AA_CONFIG,
1538 0x00000000, 0xFFFFFFFF, NULL);
1539 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1540 0x00000000, 0xFFFFFFFF, NULL);
1541 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1542 0x00000000, 0xFFFFFFFF, NULL);
1543 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C30_CB_CLRCMP_CONTROL,
1544 0x01000000, 0xFFFFFFFF, NULL);
1545 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C34_CB_CLRCMP_SRC,
1546 0x00000000, 0xFFFFFFFF, NULL);
1547 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C38_CB_CLRCMP_DST,
1548 0x000000FF, 0xFFFFFFFF, NULL);
1549 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C3C_CB_CLRCMP_MSK,
1550 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1551 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C48_PA_SC_AA_MASK,
1552 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1553
1554 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1555 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1556 r600_context_pipe_state_set(&rctx->ctx, rstate);
1557 }
1558
1559 static void r600_set_index_buffer(struct pipe_context *ctx,
1560 const struct pipe_index_buffer *ib)
1561 {
1562 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1563
1564 if (ib) {
1565 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
1566 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
1567 } else {
1568 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
1569 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
1570 }
1571
1572 /* TODO make this more like a state */
1573 }
1574
1575 static void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
1576 const struct pipe_vertex_buffer *buffers)
1577 {
1578 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1579
1580 for (int i = 0; i < rctx->nvertex_buffer; i++) {
1581 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
1582 }
1583 memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
1584 for (int i = 0; i < count; i++) {
1585 rctx->vertex_buffer[i].buffer = NULL;
1586 pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
1587 }
1588 rctx->nvertex_buffer = count;
1589 }
1590
1591 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
1592 struct pipe_resource *buffer)
1593 {
1594 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1595 struct r600_pipe_state *rstate;
1596 struct pipe_transfer *transfer;
1597 unsigned *nconst = NULL;
1598 u32 *ptr, offset;
1599
1600 switch (shader) {
1601 case PIPE_SHADER_VERTEX:
1602 rstate = rctx->vs_const;
1603 nconst = &rctx->vs_nconst;
1604 offset = R_030000_SQ_ALU_CONSTANT0_0 + 0x1000;
1605 break;
1606 case PIPE_SHADER_FRAGMENT:
1607 rstate = rctx->ps_const;
1608 nconst = &rctx->ps_nconst;
1609 offset = R_030000_SQ_ALU_CONSTANT0_0;
1610 break;
1611 default:
1612 R600_ERR("unsupported %d\n", shader);
1613 return;
1614 }
1615 if (buffer && buffer->width0 > 0) {
1616 *nconst = buffer->width0 / 16;
1617 ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
1618 if (ptr == NULL)
1619 return;
1620 for (int i = 0; i < *nconst; i++, offset += 0x10) {
1621 rstate[i].nregs = 0;
1622 r600_pipe_state_add_reg(&rstate[i], R600_GROUP_ALU_CONST, offset + 0x0, ptr[i * 4 + 0], 0xFFFFFFFF, NULL);
1623 r600_pipe_state_add_reg(&rstate[i], R600_GROUP_ALU_CONST, offset + 0x4, ptr[i * 4 + 1], 0xFFFFFFFF, NULL);
1624 r600_pipe_state_add_reg(&rstate[i], R600_GROUP_ALU_CONST, offset + 0x8, ptr[i * 4 + 2], 0xFFFFFFFF, NULL);
1625 r600_pipe_state_add_reg(&rstate[i], R600_GROUP_ALU_CONST, offset + 0xC, ptr[i * 4 + 3], 0xFFFFFFFF, NULL);
1626 r600_context_pipe_state_set(&rctx->ctx, &rstate[i]);
1627 }
1628 pipe_buffer_unmap(ctx, buffer, transfer);
1629 }
1630 }
1631
1632 static void *r600_create_shader_state(struct pipe_context *ctx,
1633 const struct pipe_shader_state *state)
1634 {
1635 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
1636 int r;
1637
1638 r = r600_pipe_shader_create2(ctx, shader, state->tokens);
1639 if (r) {
1640 return NULL;
1641 }
1642 return shader;
1643 }
1644
1645 static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
1646 {
1647 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1648
1649 /* TODO delete old shader */
1650 rctx->ps_shader = (struct r600_pipe_shader *)state;
1651 }
1652
1653 static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
1654 {
1655 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1656
1657 /* TODO delete old shader */
1658 rctx->vs_shader = (struct r600_pipe_shader *)state;
1659 }
1660
1661 static void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
1662 {
1663 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1664 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1665
1666 if (rctx->ps_shader == shader) {
1667 rctx->ps_shader = NULL;
1668 }
1669 /* TODO proper delete */
1670 free(shader);
1671 }
1672
1673 static void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
1674 {
1675 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1676 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
1677
1678 if (rctx->vs_shader == shader) {
1679 rctx->vs_shader = NULL;
1680 }
1681 /* TODO proper delete */
1682 free(shader);
1683 }
1684
1685 static void r600_init_state_functions2(struct r600_pipe_context *rctx)
1686 {
1687 rctx->context.create_blend_state = r600_create_blend_state;
1688 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1689 rctx->context.create_fs_state = r600_create_shader_state;
1690 rctx->context.create_rasterizer_state = r600_create_rs_state;
1691 rctx->context.create_sampler_state = r600_create_sampler_state;
1692 rctx->context.create_sampler_view = r600_create_sampler_view;
1693 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1694 rctx->context.create_vs_state = r600_create_shader_state;
1695 rctx->context.bind_blend_state = r600_bind_blend_state;
1696 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
1697 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
1698 rctx->context.bind_fs_state = r600_bind_ps_shader;
1699 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1700 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1701 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
1702 rctx->context.bind_vs_state = r600_bind_vs_shader;
1703 rctx->context.delete_blend_state = r600_delete_state;
1704 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1705 rctx->context.delete_fs_state = r600_delete_ps_shader;
1706 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1707 rctx->context.delete_sampler_state = r600_delete_state;
1708 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1709 rctx->context.delete_vs_state = r600_delete_vs_shader;
1710 rctx->context.set_blend_color = r600_set_blend_color;
1711 rctx->context.set_clip_state = r600_set_clip_state;
1712 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1713 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
1714 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1715 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1716 rctx->context.set_sample_mask = r600_set_sample_mask;
1717 rctx->context.set_scissor_state = r600_set_scissor_state;
1718 rctx->context.set_stencil_ref = r600_set_stencil_ref;
1719 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1720 rctx->context.set_index_buffer = r600_set_index_buffer;
1721 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
1722 rctx->context.set_viewport_state = r600_set_viewport_state;
1723 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1724 }
1725
1726 static void r600_init_config2(struct r600_pipe_context *rctx)
1727 {
1728 int ps_prio;
1729 int vs_prio;
1730 int gs_prio;
1731 int es_prio;
1732 int num_ps_gprs;
1733 int num_vs_gprs;
1734 int num_gs_gprs;
1735 int num_es_gprs;
1736 int num_temp_gprs;
1737 int num_ps_threads;
1738 int num_vs_threads;
1739 int num_gs_threads;
1740 int num_es_threads;
1741 int num_ps_stack_entries;
1742 int num_vs_stack_entries;
1743 int num_gs_stack_entries;
1744 int num_es_stack_entries;
1745 enum radeon_family family;
1746 struct r600_pipe_state *rstate = &rctx->config;
1747 u32 tmp;
1748
1749 family = r600_get_family(rctx->radeon);
1750 ps_prio = 0;
1751 vs_prio = 1;
1752 gs_prio = 2;
1753 es_prio = 3;
1754 switch (family) {
1755 case CHIP_R600:
1756 num_ps_gprs = 192;
1757 num_vs_gprs = 56;
1758 num_temp_gprs = 4;
1759 num_gs_gprs = 0;
1760 num_es_gprs = 0;
1761 num_ps_threads = 136;
1762 num_vs_threads = 48;
1763 num_gs_threads = 4;
1764 num_es_threads = 4;
1765 num_ps_stack_entries = 128;
1766 num_vs_stack_entries = 128;
1767 num_gs_stack_entries = 0;
1768 num_es_stack_entries = 0;
1769 break;
1770 case CHIP_RV630:
1771 case CHIP_RV635:
1772 num_ps_gprs = 84;
1773 num_vs_gprs = 36;
1774 num_temp_gprs = 4;
1775 num_gs_gprs = 0;
1776 num_es_gprs = 0;
1777 num_ps_threads = 144;
1778 num_vs_threads = 40;
1779 num_gs_threads = 4;
1780 num_es_threads = 4;
1781 num_ps_stack_entries = 40;
1782 num_vs_stack_entries = 40;
1783 num_gs_stack_entries = 32;
1784 num_es_stack_entries = 16;
1785 break;
1786 case CHIP_RV610:
1787 case CHIP_RV620:
1788 case CHIP_RS780:
1789 case CHIP_RS880:
1790 default:
1791 num_ps_gprs = 84;
1792 num_vs_gprs = 36;
1793 num_temp_gprs = 4;
1794 num_gs_gprs = 0;
1795 num_es_gprs = 0;
1796 num_ps_threads = 136;
1797 num_vs_threads = 48;
1798 num_gs_threads = 4;
1799 num_es_threads = 4;
1800 num_ps_stack_entries = 40;
1801 num_vs_stack_entries = 40;
1802 num_gs_stack_entries = 32;
1803 num_es_stack_entries = 16;
1804 break;
1805 case CHIP_RV670:
1806 num_ps_gprs = 144;
1807 num_vs_gprs = 40;
1808 num_temp_gprs = 4;
1809 num_gs_gprs = 0;
1810 num_es_gprs = 0;
1811 num_ps_threads = 136;
1812 num_vs_threads = 48;
1813 num_gs_threads = 4;
1814 num_es_threads = 4;
1815 num_ps_stack_entries = 40;
1816 num_vs_stack_entries = 40;
1817 num_gs_stack_entries = 32;
1818 num_es_stack_entries = 16;
1819 break;
1820 case CHIP_RV770:
1821 num_ps_gprs = 192;
1822 num_vs_gprs = 56;
1823 num_temp_gprs = 4;
1824 num_gs_gprs = 0;
1825 num_es_gprs = 0;
1826 num_ps_threads = 188;
1827 num_vs_threads = 60;
1828 num_gs_threads = 0;
1829 num_es_threads = 0;
1830 num_ps_stack_entries = 256;
1831 num_vs_stack_entries = 256;
1832 num_gs_stack_entries = 0;
1833 num_es_stack_entries = 0;
1834 break;
1835 case CHIP_RV730:
1836 case CHIP_RV740:
1837 num_ps_gprs = 84;
1838 num_vs_gprs = 36;
1839 num_temp_gprs = 4;
1840 num_gs_gprs = 0;
1841 num_es_gprs = 0;
1842 num_ps_threads = 188;
1843 num_vs_threads = 60;
1844 num_gs_threads = 0;
1845 num_es_threads = 0;
1846 num_ps_stack_entries = 128;
1847 num_vs_stack_entries = 128;
1848 num_gs_stack_entries = 0;
1849 num_es_stack_entries = 0;
1850 break;
1851 case CHIP_RV710:
1852 num_ps_gprs = 192;
1853 num_vs_gprs = 56;
1854 num_temp_gprs = 4;
1855 num_gs_gprs = 0;
1856 num_es_gprs = 0;
1857 num_ps_threads = 144;
1858 num_vs_threads = 48;
1859 num_gs_threads = 0;
1860 num_es_threads = 0;
1861 num_ps_stack_entries = 128;
1862 num_vs_stack_entries = 128;
1863 num_gs_stack_entries = 0;
1864 num_es_stack_entries = 0;
1865 break;
1866 }
1867
1868 rstate->id = R600_PIPE_STATE_CONFIG;
1869
1870 /* SQ_CONFIG */
1871 tmp = 0;
1872 switch (family) {
1873 case CHIP_RV610:
1874 case CHIP_RV620:
1875 case CHIP_RS780:
1876 case CHIP_RS880:
1877 case CHIP_RV710:
1878 break;
1879 default:
1880 tmp |= S_008C00_VC_ENABLE(1);
1881 break;
1882 }
1883 tmp |= S_008C00_DX9_CONSTS(1);
1884 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1885 tmp |= S_008C00_PS_PRIO(ps_prio);
1886 tmp |= S_008C00_VS_PRIO(vs_prio);
1887 tmp |= S_008C00_GS_PRIO(gs_prio);
1888 tmp |= S_008C00_ES_PRIO(es_prio);
1889 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1890
1891 /* SQ_GPR_RESOURCE_MGMT_1 */
1892 tmp = 0;
1893 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1894 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1895 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1896 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1897
1898 /* SQ_GPR_RESOURCE_MGMT_2 */
1899 tmp = 0;
1900 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1901 tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
1902 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1903
1904 /* SQ_THREAD_RESOURCE_MGMT */
1905 tmp = 0;
1906 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1907 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1908 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1909 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1910 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1911
1912 /* SQ_STACK_RESOURCE_MGMT_1 */
1913 tmp = 0;
1914 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1915 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1916 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1917
1918 /* SQ_STACK_RESOURCE_MGMT_2 */
1919 tmp = 0;
1920 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1921 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1922 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1923
1924 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1925 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1926
1927 if (family >= CHIP_RV770) {
1928 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1929 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
1930 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1931 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1932 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1933 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A4C_PA_SC_MODE_CNTL, 0x00514000, 0xFFFFFFFF, NULL);
1934 } else {
1935 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1936 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
1937 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1938 r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1939 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1940 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A4C_PA_SC_MODE_CNTL, 0x00004010, 0xFFFFFFFF, NULL);
1941 }
1942 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1943 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1944 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1945 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1946 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1947 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1948 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1949 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1950 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1951 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1952 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1953 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1954 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1955 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
1956 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
1957 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1958 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1959 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1960 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1961 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1962 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1963 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
1964 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1965 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1966 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1967 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
1968
1969 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028400_VGT_MAX_VTX_INDX, 0x00FFFFFF, 0xFFFFFFFF, NULL);
1970 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028404_VGT_MIN_VTX_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1971 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1972 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
1973 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
1974 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
1975 r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
1976 r600_context_pipe_state_set(&rctx->ctx, rstate);
1977 }
1978
1979 static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type)
1980 {
1981 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1982
1983 return (struct pipe_query*)r600_context_query_create(&rctx->ctx, query_type);
1984 }
1985
1986 static void r600_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
1987 {
1988 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1989
1990 r600_context_query_destroy(&rctx->ctx, (struct r600_query *)query);
1991 }
1992
1993 static void r600_begin_query(struct pipe_context *ctx, struct pipe_query *query)
1994 {
1995 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1996 struct r600_query *rquery = (struct r600_query *)query;
1997
1998 rquery->result = 0;
1999 rquery->num_results = 0;
2000 r600_query_begin(&rctx->ctx, (struct r600_query *)query);
2001 }
2002
2003 static void r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
2004 {
2005 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2006
2007 r600_query_end(&rctx->ctx, (struct r600_query *)query);
2008 }
2009
2010 static boolean r600_get_query_result(struct pipe_context *ctx,
2011 struct pipe_query *query,
2012 boolean wait, void *vresult)
2013 {
2014 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2015 struct r600_query *rquery = (struct r600_query *)query;
2016
2017 if (rquery->num_results) {
2018 ctx->flush(ctx, 0, NULL);
2019 }
2020 return r600_context_query_result(&rctx->ctx, (struct r600_query *)query, wait, vresult);
2021 }
2022
2023 static void r600_init_query_functions2(struct r600_pipe_context *rctx)
2024 {
2025 rctx->context.create_query = r600_create_query;
2026 rctx->context.destroy_query = r600_destroy_query;
2027 rctx->context.begin_query = r600_begin_query;
2028 rctx->context.end_query = r600_end_query;
2029 rctx->context.get_query_result = r600_get_query_result;
2030 }
2031
2032 static struct pipe_context *r600_create_context2(struct pipe_screen *screen, void *priv)
2033 {
2034 struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
2035 struct r600_screen* rscreen = (struct r600_screen *)screen;
2036
2037 if (rctx == NULL)
2038 return NULL;
2039 rctx->context.winsys = rscreen->screen.winsys;
2040 rctx->context.screen = screen;
2041 rctx->context.priv = priv;
2042 rctx->context.destroy = r600_destroy_context;
2043 rctx->context.flush = r600_flush2;
2044
2045 /* Easy accessing of screen/winsys. */
2046 rctx->screen = rscreen;
2047 rctx->radeon = rscreen->radeon;
2048
2049 r600_init_blit_functions2(rctx);
2050 r600_init_query_functions2(rctx);
2051 r600_init_context_resource_functions2(rctx);
2052
2053 rctx->blitter = util_blitter_create(&rctx->context);
2054 if (rctx->blitter == NULL) {
2055 FREE(rctx);
2056 return NULL;
2057 }
2058
2059 switch (r600_get_family(rctx->radeon)) {
2060 case CHIP_R600:
2061 case CHIP_RV610:
2062 case CHIP_RV630:
2063 case CHIP_RV670:
2064 case CHIP_RV620:
2065 case CHIP_RV635:
2066 case CHIP_RS780:
2067 case CHIP_RS880:
2068 case CHIP_RV770:
2069 case CHIP_RV730:
2070 case CHIP_RV710:
2071 case CHIP_RV740:
2072 rctx->context.draw_vbo = r600_draw_vbo2;
2073 r600_init_state_functions2(rctx);
2074 if (r600_context_init(&rctx->ctx, rctx->radeon)) {
2075 r600_destroy_context(&rctx->context);
2076 return NULL;
2077 }
2078 r600_init_config2(rctx);
2079 break;
2080 case CHIP_CEDAR:
2081 case CHIP_REDWOOD:
2082 case CHIP_JUNIPER:
2083 case CHIP_CYPRESS:
2084 case CHIP_HEMLOCK:
2085 rctx->context.draw_vbo = evergreen_draw;
2086 evergreen_init_state_functions2(rctx);
2087 if (evergreen_context_init(&rctx->ctx, rctx->radeon)) {
2088 r600_destroy_context(&rctx->context);
2089 return NULL;
2090 }
2091 evergreen_init_config2(rctx);
2092 break;
2093 default:
2094 R600_ERR("unsupported family %d\n", r600_get_family(rctx->radeon));
2095 r600_destroy_context(&rctx->context);
2096 return NULL;
2097 }
2098
2099 return &rctx->context;
2100 }
2101
2102 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
2103 {
2104 switch(shader)
2105 {
2106 case PIPE_SHADER_FRAGMENT:
2107 case PIPE_SHADER_VERTEX:
2108 break;
2109 case PIPE_SHADER_GEOMETRY:
2110 /* TODO: support and enable geometry programs */
2111 return 0;
2112 default:
2113 /* TODO: support tessellation on Evergreen */
2114 return 0;
2115 }
2116
2117 /* TODO: all these should be fixed, since r600 surely supports much more! */
2118 switch (param) {
2119 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
2120 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
2121 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
2122 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
2123 return 16384;
2124 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
2125 return 8; /* FIXME */
2126 case PIPE_SHADER_CAP_MAX_INPUTS:
2127 if(shader == PIPE_SHADER_FRAGMENT)
2128 return 10;
2129 else
2130 return 16;
2131 case PIPE_SHADER_CAP_MAX_TEMPS:
2132 return 256; //max native temporaries
2133 case PIPE_SHADER_CAP_MAX_ADDRS:
2134 return 1; //max native address registers/* FIXME Isn't this equal to TEMPS? */
2135 case PIPE_SHADER_CAP_MAX_CONSTS:
2136 return 256; //max native parameters
2137 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
2138 return 1;
2139 case PIPE_SHADER_CAP_MAX_PREDS:
2140 return 0; /* FIXME */
2141 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
2142 /* TODO: support this! */
2143 return 0;
2144 default:
2145 return 0;
2146 }
2147 }
2148
2149 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
2150 const struct pipe_resource *templ);
2151 struct pipe_resource *r600_user_buffer_create2(struct pipe_screen *screen,
2152 void *ptr, unsigned bytes,
2153 unsigned bind)
2154 {
2155 struct pipe_resource *resource;
2156 struct r600_resource *rresource;
2157 struct pipe_resource desc;
2158 struct radeon *radeon = (struct radeon *)screen->winsys;
2159 void *rptr;
2160
2161 desc.screen = screen;
2162 desc.target = PIPE_BUFFER;
2163 desc.format = PIPE_FORMAT_R8_UNORM;
2164 desc.usage = PIPE_USAGE_IMMUTABLE;
2165 desc.bind = bind;
2166 desc.width0 = bytes;
2167 desc.height0 = 1;
2168 desc.depth0 = 1;
2169 desc.flags = 0;
2170 resource = r600_buffer_create(screen, &desc);
2171 if (resource == NULL) {
2172 return NULL;
2173 }
2174
2175 rresource = (struct r600_resource *)resource;
2176 rptr = radeon_ws_bo_map(radeon, rresource->bo, 0, NULL);
2177 memcpy(rptr, ptr, bytes);
2178 radeon_ws_bo_unmap(radeon, rresource->bo);
2179
2180 return resource;
2181 }
2182
2183 void r600_init_screen_texture_functions(struct pipe_screen *screen);
2184 struct pipe_screen *r600_screen_create2(struct radeon *radeon)
2185 {
2186 struct r600_screen *rscreen;
2187
2188 rscreen = CALLOC_STRUCT(r600_screen);
2189 if (rscreen == NULL) {
2190 return NULL;
2191 }
2192
2193 rscreen->radeon = radeon;
2194 rscreen->screen.winsys = (struct pipe_winsys*)radeon;
2195 rscreen->screen.destroy = r600_destroy_screen;
2196 rscreen->screen.get_name = r600_get_name;
2197 rscreen->screen.get_vendor = r600_get_vendor;
2198 rscreen->screen.get_param = r600_get_param;
2199 rscreen->screen.get_shader_param = r600_get_shader_param;
2200 rscreen->screen.get_paramf = r600_get_paramf;
2201 rscreen->screen.is_format_supported = r600_is_format_supported;
2202 rscreen->screen.context_create = r600_create_context2;
2203 r600_init_screen_texture_functions(&rscreen->screen);
2204 r600_init_screen_resource_functions(&rscreen->screen);
2205 rscreen->screen.user_buffer_create = r600_user_buffer_create2;
2206
2207 return &rscreen->screen;
2208 }